mirror of
https://github.com/86Box/probing-tools.git
synced 2026-02-27 17:34:27 -07:00
372 lines
9.2 KiB
C
372 lines
9.2 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box Probing Tools distribution.
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*
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* Common library for C-based tools.
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*
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2021 RichardG.
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*
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*/
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#ifdef __POSIX_UEFI__
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# include <uefi.h>
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#else
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# include <stdio.h>
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#endif
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#include "clib_pci.h"
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#include "clib_sys.h"
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uint8_t pci_mechanism = 0, pci_device_count = 0;
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/* Configuration functions. */
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uint32_t
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pci_cf8(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg)
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{
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/* Generate a PCI port CF8h dword. */
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multi_t ret;
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ret.u8[3] = 0x80;
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ret.u8[2] = bus;
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ret.u8[1] = dev << 3;
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ret.u8[1] |= func & 7;
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ret.u8[0] = reg & 0xfc;
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return ret.u32;
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}
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uint16_t
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pci_get_io_bar(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint16_t size, const char *name)
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{
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uint16_t ret, temp;
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printf("%s I/O BAR is ", name);
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/* Read BAR register. */
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ret = pci_readw(bus, dev, func, reg);
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if (!(ret & 0x0001) || (ret == 0xffff)) {
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temp = pci_readw(bus, dev, func, reg | 0x2);
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printf("invalid! (%04X%04X)", temp, ret);
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ret = 0;
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} else {
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/* Assign BAR if unassigned. */
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ret &= ~(size - 1);
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if (ret) {
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printf("assigned to %04X", ret);
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} else {
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printf("unassigned ");
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/* Find I/O range for the BAR. */
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ret = io_find_range(size);
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if (ret) {
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/* Assign and check value. */
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pci_writew(bus, dev, func, reg, ret | 0x0001);
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temp = pci_readw(bus, dev, func, reg);
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if ((temp & ~(size - 1)) == ret) {
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printf("(assigning to %04X)", ret);
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} else {
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ret = pci_readw(bus, dev, func, reg | 0x2);
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printf("and not responding! (%04X%04X)", ret, temp);
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ret = 0;
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}
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} else {
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printf("and no suitable range was found!");
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}
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}
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}
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printf("\n");
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return ret;
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}
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#ifdef IS_32BIT
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uint32_t
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pci_get_mem_bar(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint32_t size, const char *name)
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{
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uint32_t ret;
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printf("%s memory BAR is ", name);
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/* Read BAR register. */
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ret = pci_readl(bus, dev, func, reg);
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if ((ret & 0x00000001) || (ret == 0xffffffff)) {
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printf("invalid! (%08X)", ret);
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ret = 0;
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} else {
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/* Don't even try to find a valid memory range if the BAR is unassigned. */
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ret &= ~(size - 1);
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if (ret)
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printf("assigned to %08X", ret);
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else
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printf("unassigned!");
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}
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printf("\n");
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return ret;
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}
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#endif
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int
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pci_init()
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{
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multi_t cf8;
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cf8.u32 = 0x80001234;
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/* Determine the supported PCI configuration mechanism. */
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cli();
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outl(0xcf8, cf8.u32);
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cf8.u32 = inl(0xcf8);
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if (cf8.u32 == 0x80001234) {
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pci_mechanism = 1;
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pci_device_count = 32;
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} else {
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outb(0xcf8, 0x00);
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outb(0xcfa, 0x00);
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if ((inb(0xcf8) == 0x00) && (inb(0xcfa) == 0x00)) {
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pci_mechanism = 2;
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pci_device_count = 16;
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}
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}
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sti();
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if (pci_mechanism == 0)
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printf("Failed to probe PCI configuration mechanism (%04X%04X). Is this a PCI system?\n", cf8.u16[1], cf8.u16[0]);
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return pci_mechanism;
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}
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uint8_t
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pci_readb(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg)
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{
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uint8_t ret;
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uint16_t data_port;
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uint32_t cf8;
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switch (pci_mechanism) {
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case 1:
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data_port = 0xcfc | (reg & 0x03);
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cf8 = pci_cf8(bus, dev, func, reg);
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cli();
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outl(0xcf8, cf8);
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ret = inb(data_port);
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sti();
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break;
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case 2:
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cf8 = pci_readl(bus, dev, func, reg);
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ret = cf8 >> ((reg & 0x03) << 3);
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break;
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default:
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ret = 0xff;
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break;
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}
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return ret;
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}
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uint16_t
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pci_readw(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg)
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{
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uint16_t ret, data_port;
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uint32_t cf8;
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switch (pci_mechanism) {
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case 1:
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data_port = 0xcfc | (reg & 0x02);
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cf8 = pci_cf8(bus, dev, func, reg);
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cli();
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outl(0xcf8, cf8);
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ret = inw(data_port);
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sti();
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break;
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case 2:
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cf8 = pci_readl(bus, dev, func, reg);
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ret = cf8 >> ((reg & 0x02) << 3);
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break;
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default:
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ret = 0xffff;
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break;
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}
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return ret;
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}
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uint32_t
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pci_readl(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg)
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{
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uint16_t data_port;
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uint32_t ret, cf8;
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switch (pci_mechanism) {
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case 1:
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cf8 = pci_cf8(bus, dev, func, reg);
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cli();
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outl(0xcf8, cf8);
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ret = inl(0xcfc);
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sti();
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break;
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case 2:
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func = 0x80 | (func << 1);
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data_port = 0xc000 | (dev << 8) | (reg & 0xfc);
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cli();
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outb(0xcf8, func);
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outb(0xcfa, bus);
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ret = inl(data_port);
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sti();
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break;
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default:
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ret = 0xffffffff;
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break;
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}
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return ret;
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}
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void
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pci_writeb(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint8_t val)
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{
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uint8_t shift;
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uint16_t data_port;
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uint32_t cf8;
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switch (pci_mechanism) {
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case 1:
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data_port = 0xcfc | (reg & 0x03);
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cf8 = pci_cf8(bus, dev, func, reg);
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cli();
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outl(0xcf8, cf8);
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outb(data_port, val);
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sti();
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break;
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case 2:
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cf8 = pci_readl(bus, dev, func, reg);
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shift = (reg & 0x03) << 3;
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cf8 &= ~(0x000000ff << shift);
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cf8 |= val << shift;
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pci_writel(bus, dev, func, reg, cf8);
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break;
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}
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}
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void
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pci_writew(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint16_t val)
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{
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uint8_t shift;
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uint16_t data_port;
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uint32_t cf8;
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switch (pci_mechanism) {
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case 1:
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data_port = 0xcfc | (reg & 0x02);
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cf8 = pci_cf8(bus, dev, func, reg);
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cli();
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outl(0xcf8, cf8);
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outw(data_port, val);
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sti();
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break;
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case 2:
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cf8 = pci_readl(bus, dev, func, reg);
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shift = (reg & 0x02) << 3;
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cf8 &= ~(0x0000ffff << shift);
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cf8 |= val << shift;
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pci_writel(bus, dev, func, reg, cf8);
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break;
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}
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}
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void
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pci_writel(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint32_t val)
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{
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uint16_t data_port;
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uint32_t cf8;
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switch (pci_mechanism) {
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case 1:
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cf8 = pci_cf8(bus, dev, func, reg);
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cli();
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outl(0xcf8, cf8);
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outl(0xcfc, val);
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sti();
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break;
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case 2:
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func = 0x80 | (func << 1);
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data_port = 0xc000 | (dev << 8) | (reg & 0xfc);
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cli();
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outb(0xcf8, func);
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outb(0xcfa, bus);
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outl(data_port, val);
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sti();
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break;
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}
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}
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void
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pci_scan_bus(uint8_t bus,
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void (*callback)(uint8_t bus, uint8_t dev, uint8_t func,
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uint16_t ven_id, uint16_t dev_id))
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{
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uint8_t dev, func, header_type;
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multi_t dev_id;
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/* Iterate through devices. */
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for (dev = 0; dev < pci_device_count; dev++) {
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/* Iterate through functions. */
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for (func = 0; func < 8; func++) {
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/* Read vendor/device ID. */
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#ifdef DEBUG
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if ((bus < DEBUG) && (dev <= bus) && (func == 0)) {
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dev_id.u16[0] = rand();
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dev_id.u16[1] = rand();
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} else {
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dev_id.u32 = 0xffffffff;
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}
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#else
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dev_id.u32 = pci_readl(bus, dev, func, 0x00);
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#endif
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/* Callback if this is a valid ID. */
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if (dev_id.u32 && (dev_id.u32 != 0xffffffff)) {
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callback(bus, dev, func, dev_id.u16[0], dev_id.u16[1]);
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} else {
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/* Stop or move on to the next function if there's nothing here. */
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if (func)
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continue;
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else
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break;
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}
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/* Read header type. */
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#ifdef DEBUG
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header_type = (bus < (DEBUG - 1)) ? 0x01 : 0x00;
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#else
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header_type = pci_readb(bus, dev, func, 0x0e);
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#endif
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/* If this is a bridge, mark that we should probe its bus. */
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if (header_type & 0x7f) {
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/* Scan the secondary bus. */
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#ifdef DEBUG
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pci_scan_bus(bus + 1, callback);
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#else
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pci_scan_bus(pci_readb(bus, dev, func, 0x19), callback);
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#endif
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}
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/* If we're at the first function, stop if this is not a multi-function device. */
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if ((func == 0) && !(header_type & 0x80))
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break;
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}
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}
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}
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