From a2abb497e2d75d67cc9d4482a785e7910aabcc86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <13226155+dhrdlicka@users.noreply.github.com> Date: Thu, 1 May 2025 21:02:59 +0200 Subject: [PATCH 1/5] Fix header guard warning --- src/qt/qt_iconindicators.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/qt/qt_iconindicators.hpp b/src/qt/qt_iconindicators.hpp index 861e41d94..12f82f259 100644 --- a/src/qt/qt_iconindicators.hpp +++ b/src/qt/qt_iconindicators.hpp @@ -1,5 +1,5 @@ #ifndef QT_ICONINDICATORS_HPP -# define QT_INDICATORS_HPP +# define QT_ICONINDICATORS_HPP #include #include @@ -14,4 +14,4 @@ enum IconIndicator { QPixmap getIconWithIndicator(const QIcon &icon, const QSize &size, QIcon::Mode iconMode, IconIndicator indicator); -#endif \ No newline at end of file +#endif From a72142f2b5395e04e40cbf0ecb0dd3ed73174d39 Mon Sep 17 00:00:00 2001 From: GreaseMonkey Date: Fri, 2 May 2025 10:51:34 +1200 Subject: [PATCH 2/5] Fix EGA/VGA/SVGA odd-even handling of write mask Matches my AMD Stoney + S3 Trio64V2, and also Intel's 2023 GPU docs (which *still* tend to be more accurate than IBM's), and makes more sense than what we've (I've?) been doing. --- src/video/vid_ega.c | 4 +--- src/video/vid_svga.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/video/vid_ega.c b/src/video/vid_ega.c index 8333e522e..b828239c0 100644 --- a/src/video/vid_ega.c +++ b/src/video/vid_ega.c @@ -1180,9 +1180,7 @@ ega_write(uint32_t addr, uint8_t val, void *priv) cycles -= video_timing_write_b; if (ega->chain2_write) { - writemask2 &= ~0xa; - if (addr & 1) - writemask2 <<= 1; + writemask2 &= 0x5 << (addr & 1); } addr = ega_remap_cpu_addr(addr, ega); diff --git a/src/video/vid_svga.c b/src/video/vid_svga.c index 67469ed22..86a57c00e 100644 --- a/src/video/vid_svga.c +++ b/src/video/vid_svga.c @@ -1689,9 +1689,7 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *priv) addr &= ~3; addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff); } else if (svga->chain2_write) { - writemask2 &= ~0xa; - if (addr & 1) - writemask2 <<= 1; + writemask2 &= 0x5 << (addr & 1); addr &= ~1; addr <<= 2; } else From 5e85f4533a18026311f5249b1cab826034a590a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Fri, 2 May 2025 02:06:02 +0200 Subject: [PATCH 3/5] Update RAM limits for SiS 471 machines --- src/machine/machine_table.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index c269c7b0f..77132b6b5 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -7089,7 +7089,7 @@ const machine_t machines[] = { .flags = MACHINE_APM, .ram = { .min = 1024, - .max = 65536, + .max = 131072, .step = 1024 }, .nvrmask = 127, @@ -7129,7 +7129,7 @@ const machine_t machines[] = { .flags = MACHINE_APM, .ram = { .min = 1024, - .max = 65536, + .max = 131072, .step = 1024 }, .nvrmask = 127, @@ -7209,7 +7209,7 @@ const machine_t machines[] = { .flags = MACHINE_APM, .ram = { .min = 1024, - .max = 65536, + .max = 131072, .step = 1024 }, .nvrmask = 127, @@ -7249,7 +7249,7 @@ const machine_t machines[] = { .flags = MACHINE_APM, .ram = { .min = 1024, - .max = 65536, + .max = 131072, .step = 1024 }, .nvrmask = 127, @@ -7368,9 +7368,9 @@ const machine_t machines[] = { .bus_flags = MACHINE_PS2, .flags = MACHINE_IDE_DUAL | MACHINE_SUPER_IO | MACHINE_APM | MACHINE_VIDEO, .ram = { - .min = 1024, - .max = 65536, - .step = 1024 + .min = 4096, + .max = 69632, + .step = 4096 }, .nvrmask = 127, .kbc_device = NULL, From 7885c28ea2ad5597d8c52c73b750d59a0bce2ad4 Mon Sep 17 00:00:00 2001 From: OBattler Date: Fri, 2 May 2025 02:17:09 +0200 Subject: [PATCH 4/5] SiS 471: Fix RAM bank values (and some other minor things), fixes #5534. --- src/chipset/sis_85c4xx.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/src/chipset/sis_85c4xx.c b/src/chipset/sis_85c4xx.c index 003b66697..51f7fd4e6 100644 --- a/src/chipset/sis_85c4xx.c +++ b/src/chipset/sis_85c4xx.c @@ -33,6 +33,7 @@ #include <86box/mem.h> #include <86box/smram.h> #include <86box/pic.h> +#include <86box/keyboard.h> #include <86box/machine.h> #include <86box/chipset.h> @@ -79,8 +80,8 @@ static uint8_t ram_471[64] = { 0x00, 0x00, 0x01, 0x01, 0x02, 0x20, 0x09, 0x09, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, - 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, - 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e }; + 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, + 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d }; static uint8_t ram_tg486g[64] = { 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, @@ -544,12 +545,23 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv) case 0x23: if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) { valxor = val ^ dev->regs[rel_reg]; - if (rel_reg == 0x00) + + if (!dev->is_471 && (rel_reg == 0x00)) dev->regs[rel_reg] = (dev->regs[rel_reg] & 0x1f) | (val & 0xe0); else dev->regs[rel_reg] = val; switch (rel_reg) { + case 0x00: + if (val & 0x01) { + kbc_at_set_fast_reset(0); + cpu_cpurst_on_sr = 1; + } else { + kbc_at_set_fast_reset(1); + cpu_cpurst_on_sr = 0; + } + break; + case 0x01: cpu_cache_ext_enabled = ((val & 0x84) == 0x84); cpu_update_waitstates(); @@ -560,6 +572,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv) case 0x08: if (valxor) sis_85c4xx_recalcmapping(dev); + if (rel_reg == 0x08) + flushmmucache(); break; case 0x09: @@ -681,10 +695,16 @@ sis_85c4xx_reset(void *priv) if (dev->is_471) { dev->regs[0x09] = 0x40; if (mem_size_mb >= 64) { - if ((mem_size_mb >= 65) && (mem_size_mb < 68)) - dev->regs[0x09] |= 0x22; + if ((mem_size_mb >= 64) && (mem_size_mb < 68)) + dev->regs[0x09] |= 0x33; + if ((mem_size_mb >= 68) && (mem_size_mb < 72)) + dev->regs[0x09] |= 0x2b; + if ((mem_size_mb >= 72) && (mem_size_mb < 80)) + dev->regs[0x09] |= 0x2d; + if ((mem_size_mb >= 80) && (mem_size_mb < 96)) + dev->regs[0x09] |= 0x2f; else - dev->regs[0x09] |= 0x24; + dev->regs[0x09] |= 0x29; } else if (!strcmp(machine_get_internal_name(), "tg486g")) dev->regs[0x09] |= ram_tg486g[mem_size_mb]; else @@ -718,6 +738,9 @@ sis_85c4xx_reset(void *priv) soft_reset_mask = 0; sis_85c471_banks_recalc(dev); + + kbc_at_set_fast_reset(1); + cpu_cpurst_on_sr = 0; } else { /* Bits 6 and 7 must be clear on the SiS 40x. */ if (dev->reg_base == 0x60) From 384af874f5dee71ce0cd300d9186561d2d2227d8 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Sat, 3 May 2025 17:02:30 +0600 Subject: [PATCH 5/5] Bochs VBE: Update for 0.9c ROM --- src/video/vid_bochs_vbe.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/video/vid_bochs_vbe.c b/src/video/vid_bochs_vbe.c index 36185214c..a87890c75 100644 --- a/src/video/vid_bochs_vbe.c +++ b/src/video/vid_bochs_vbe.c @@ -811,22 +811,22 @@ bochs_vbe_init(const device_t *info) dev->vram_size = device_get_config_int("memory") * (1 << 20); rom_init(&dev->bios_rom, "roms/video/bochs/VGABIOS-lgpl-latest.bin", - 0xc0000, 0x10000, 0xffff, 0x0000, + 0xc0000, 0x8000, 0x7fff, 0x0000, MEM_MAPPING_EXTERNAL); if (dev->id5_val == VBE_DISPI_ID4) { /* Patch the BIOS to match the PCI ID. */ dev->bios_rom.rom[0x010c] = 0xee; - dev->bios_rom.rom[0x8dff] -= (0xee - 0x34); + dev->bios_rom.rom[0x7fff] -= (0xee - 0x34); dev->bios_rom.rom[0x010d] = 0x80; - dev->bios_rom.rom[0x8dff] -= (0x80 - 0x12); + dev->bios_rom.rom[0x7fff] -= (0x80 - 0x12); dev->bios_rom.rom[0x010e] = 0xef; - dev->bios_rom.rom[0x8dff] -= (0xef - 0x11); + dev->bios_rom.rom[0x7fff] -= (0xef - 0x11); dev->bios_rom.rom[0x010f] = 0xbe; - dev->bios_rom.rom[0x8dff] -= (0xbe - 0x11); + dev->bios_rom.rom[0x7fff] -= (0xbe - 0x11); } video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_bochs);