mirror/86Box
1
0
Fork 0
mirror of https://github.com/86Box/86Box.git synced 2026-02-26 14:03:16 -07:00
Code Issues Packages Projects Releases Activity

Nvidia NV3 initial implementation from the old repo when it was a fork.

Browse Source
This commit is contained in:
starfrost013
2024-11-27 16:29:26 +00:00
parent 781320817f
commit 15a2f6435c
26 changed files with 4074 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/video/CMakeLists.txt
View File

@@ -27,7 +27,21 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c
vid_tkd8001_ramdac.c vid_att20c49x_ramdac.c vid_s3.c vid_s3_virge.c
vid_ibm_rgb528_ramdac.c vid_sdac_ramdac.c vid_ogc.c vid_mga.c vid_nga.c
vid_tvp3026_ramdac.c vid_att2xc498_ramdac.c vid_xga.c
vid_bochs_vbe.c)
vid_bochs_vbe.c
nv/nv_base.c
nv/nv3/nv3_core.c nv/nv3/nv3_core_arbiter.c nv/nv3/nv3_interrupt.c
nv/nv3/subsystems/nv3_pramdac.c
nv/nv3/subsystems/nv3_pfifo.c
nv/nv3/subsystems/nv3_pgraph.c
nv/nv3/subsystems/nv3_pmc.c
nv/nv3/subsystems/nv3_pme.c
nv/nv3/subsystems/nv3_pextdev.c
nv/nv3/subsystems/nv3_pfb.c
nv/nv3/subsystems/nv3_pbus.c nv/nv3/subsystems/nv3_pbus_dma.c
nv/nv3/subsystems/nv3_ptimer.c
nv/nv3/subsystems/nv3_pramin.c nv/nv3/subsystems/nv3_pramin_ramht.c nv/nv3/subsystems/nv3_pramin_ramfc.c nv/nv3/subsystems/nv3_pramin_ramro.c
nv/nv3/subsystems/nv3_pvideo.c
)
if(G100)
target_compile_definitions(vid PRIVATE USE_G100)

837
src/video/nv/nv3/nv3_core.c Normal file
View File

@@ -0,0 +1,837 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 bringup and device emulation.
*
* Notes:
* xfree86 ref has INVERTED bit numbering? What?
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/io.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
nv3_t* nv3;
// Prototypes for functions only used in this translation unit
void nv3_init_mappings_mmio();
void nv3_init_mappings_svga();
void nv3_shutdown_mappings_mmio();
void nv3_shutdown_mappings_svga();
uint8_t nv3_svga_in(uint16_t addr, void* priv);
void nv3_svga_out(uint16_t addr, uint8_t val, void* priv);
// All MMIO regs are 32-bit i believe internally
// so we have to do some munging to get this to read
// Read 8-bit MMIO
uint8_t nv3_mmio_read8(uint32_t addr, void* priv)
{
// see if unaligned reads are a problem
uint32_t ret = nv3_mmio_read32(addr, priv);
return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFF);
}
// Read 16-bit MMIO
uint16_t nv3_mmio_read16(uint32_t addr, void* priv)
{
uint32_t ret = nv3_mmio_read32(addr, priv);
return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFFFF);
}
// Read 32-bit MMIO
uint32_t nv3_mmio_read32(uint32_t addr, void* priv)
{
return nv3_mmio_arbitrate_read(addr);
}
// Write 8-bit MMIO
void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv)
{
// overwrite first 8bits of a 32 bit value
uint32_t new_val = nv3_mmio_read32(addr, NULL);
new_val &= (~0xFF << (addr & 3) << 3);
new_val |= (val << ((addr & 3) << 3));
nv3_mmio_write32(addr, new_val, priv);
}
// Write 16-bit MMIO
void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv)
{
// overwrite first 16bits of a 32 bit value
uint32_t new_val = nv3_mmio_read32(addr, NULL);
new_val &= (~0xFFFF << (addr & 3) << 3);
new_val |= (val << ((addr & 3) << 3));
nv3_mmio_write32(addr, new_val, priv);
}
// Write 32-bit MMIO
void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
{
nv3_mmio_arbitrate_write(addr, val);
}
// PCI stuff
// BAR0 Pointer to MMIO space
// BAR1 Pointer to Linear Framebuffer (NV_USER)
uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
{
uint8_t ret = 0x00;
// figure out what size this gets read as first
// seems func does not matter at least here?
switch (addr)
{
// Get the pci vendor id..
case NV3_PCI_CFG_VENDOR_ID:
ret = (PCI_VENDOR_SGS_NV & 0xFF);
break;
case NV3_PCI_CFG_VENDOR_ID + 1: // all access 8bit
ret = (PCI_VENDOR_SGS_NV >> 8);
break;
// device id
case NV3_PCI_CFG_DEVICE_ID:
ret = (PCI_DEVICE_NV3 & 0xFF);
break;
case NV3_PCI_CFG_DEVICE_ID+1:
ret = (PCI_DEVICE_NV3 >> 8);
break;
// various capabilities
// IO space enabled
// Memory space enabled
// Bus master enabled
// Write/inval enabled
// Pal snoop enabled
// Capabiliies list enabled
// 66Mhz FSB capable
case PCI_REG_COMMAND_L:
ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L]; // we actually respond to the fucking
break;
case PCI_REG_COMMAND_H:
ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] | NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back
break;
// pci status register
case PCI_REG_STATUS_L:
if (nv3->pextdev.straps
& NV3_PSTRAPS_BUS_SPEED_66MHZ)
ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE);
else
ret = nv3->pci_config.pci_regs[PCI_REG_STATUS_L];
break;
case PCI_REG_STATUS_H:
ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING);
break;
case NV3_PCI_CFG_REVISION:
ret = NV3_PCI_CFG_REVISION_B00; // Commercial release
break;
case PCI_REG_PROG_IF:
ret = 0x00;
break;
case NV3_PCI_CFG_SUBCLASS_CODE:
ret = 0x00; // nothing
break;
case NV3_PCI_CFG_CLASS_CODE:
ret = NV3_PCI_CFG_CLASS_CODE_VGA; // CLASS_CODE_VGA
break;
case NV3_PCI_CFG_CACHE_LINE_SIZE:
ret = NV3_PCI_CFG_CACHE_LINE_SIZE_DEFAULT_FROM_VBIOS;
break;
case NV3_PCI_CFG_LATENCY_TIMER:
case NV3_PCI_CFG_HEADER_TYPE:
case NV3_PCI_CFG_BIST:
ret = 0x00;
break;
// BARs are marked as prefetchable per the datasheet
case NV3_PCI_CFG_BAR0_L:
case NV3_PCI_CFG_BAR1_L:
// only bit that matters is bit 3 (prefetch bit)
ret =(NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED << NV3_PCI_CFG_BAR_PREFETCHABLE);
break;
// These registers are hardwired to zero per the datasheet
// Writes have no effect, we can just handle it here though
case NV3_PCI_CFG_BAR0_BYTE1 ... NV3_PCI_CFG_BAR0_BYTE2:
case NV3_PCI_CFG_BAR1_BYTE1 ... NV3_PCI_CFG_BAR1_BYTE2:
ret = 0x00;
break;
// MMIO base address
case NV3_PCI_CFG_BAR0_BASE_ADDRESS:
ret = nv3->nvbase.bar0_mmio_base >> 24;//8bit value
break;
case NV3_PCI_CFG_BAR1_BASE_ADDRESS:
ret = nv3->nvbase.bar1_lfb_base >> 24; //8bit value
break;
case NV3_PCI_CFG_ENABLE_VBIOS:
ret = nv3->pci_config.vbios_enabled;
break;
case NV3_PCI_CFG_INT_LINE:
ret = nv3->pci_config.int_line;
break;
case NV3_PCI_CFG_INT_PIN:
ret = PCI_INTA;
break;
case NV3_PCI_CFG_MIN_GRANT:
ret = NV3_PCI_CFG_MIN_GRANT_DEFAULT;
break;
case NV3_PCI_CFG_MAX_LATENCY:
ret = NV3_PCI_CFG_MAX_LATENCY_DEFAULT;
break;
//bar2-5 are not used and hardwired to 0
case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END:
ret = 0x00;
break;
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START:
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END:
ret = nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)];
break;
default: // by default just return pci_config.pci_regs
ret = nv3->pci_config.pci_regs[addr];
break;
}
nv_log("NV3: nv3_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret);
return ret;
}
void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
{
// TOTAL IRRELEVANCY
// some addresses are not writable so can't have any effect and can't be allowed to be modified using this code
// only the most significant byte of the PCI BARs can be modified
if (addr >= NV3_PCI_CFG_BAR0_L && addr <= NV3_PCI_CFG_BAR0_BYTE2
&& addr >= NV3_PCI_CFG_BAR1_L && addr <= NV3_PCI_CFG_BAR1_BYTE2)
return;
nv_log("NV3: nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val);
nv3->pci_config.pci_regs[addr] = val;
switch (addr)
{
// standard pci command stuff
case PCI_REG_COMMAND_L:
nv3->pci_config.pci_regs[PCI_REG_COMMAND_L] = val;
// actually update the mappings
nv3_update_mappings();
break;
// pci status register
case PCI_REG_STATUS_L:
nv3->pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE);
break;
case PCI_REG_STATUS_H:
nv3->pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING);
break;
//TODO: ACTUALLY REMAP THE MMIO AND NV_USER
case NV3_PCI_CFG_BAR0_BASE_ADDRESS:
nv3->nvbase.bar0_mmio_base = val << 24;
nv3_update_mappings();
break;
case NV3_PCI_CFG_BAR1_BASE_ADDRESS:
nv3->nvbase.bar1_lfb_base = val << 24;
nv3_update_mappings();
break;
case NV3_PCI_CFG_ENABLE_VBIOS:
case NV3_PCI_CFG_VBIOS_BASE:
// make sure we are actually toggling the vbios, not the rom base
if (addr == NV3_PCI_CFG_ENABLE_VBIOS)
nv3->pci_config.vbios_enabled = (val & 0x01);
if (nv3->pci_config.vbios_enabled)
{
// First see if we simply wanted to change the VBIOS location
// Enable it in case it was disabled before
mem_mapping_enable(&nv3->nvbase.vbios.mapping);
if (addr != NV3_PCI_CFG_ENABLE_VBIOS)
{
uint32_t old_addr = nv3->nvbase.vbios.mapping.base;
// 9bit register
uint32_t new_addr = nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 |
nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16;
// move it
mem_mapping_set_addr(&nv3->nvbase.vbios.mapping, new_addr, 0x8000);
nv_log("...i like to move it move it (VBIOS Relocation) 0x%04x -> 0x%04x\n", old_addr, new_addr);
}
else
{
nv_log("...VBIOS Enable\n");
}
}
else
{
nv_log("...VBIOS Disable\n");
mem_mapping_disable(&nv3->nvbase.vbios.mapping);
}
break;
case NV3_PCI_CFG_INT_LINE:
nv3->pci_config.int_line = val;
break;
//bar2-5 are not used and can't be written to
case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END:
break;
// these are mirrored to the subsystem id and also stored in the ROMBIOS
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START:
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END:
nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val;
break;
default:
}
}
void nv3_close(void* priv)
{
svga_close(&nv3->nvbase.svga);
free(nv3);
}
//
// SVGA functions
//
void nv3_recalc_timings(svga_t* svga)
{
nv3_t* nv3 = (nv3_t*)svga->priv;
svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16;
svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3;
// should these actually use separate values?
// i don't we should force the top 2 bits to 1...
// required for VESA resolutions, force parameters higher
if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400;
if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400;
if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400;
if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400;
if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400;
if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01)
svga->hdisp += 0x100; // large screen bit
// Set the pixel mode
switch (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03)
{
///0x0 is VGA textmode
case NV3_CRTC_REGISTER_PIXELMODE_8BPP:
svga->bpp = 8;
svga->lowres = 0;
svga->render = svga_render_8bpp_highres;
break;
case NV3_CRTC_REGISTER_PIXELMODE_16BPP:
svga->bpp = 16;
svga->lowres = 0;
svga->render = svga_render_16bpp_highres;
break;
case NV3_CRTC_REGISTER_PIXELMODE_32BPP:
svga->bpp = 32;
svga->lowres = 0;
svga->render = svga_render_32bpp_highres;
break;
}
// from nv_riva128
if (((svga->miscout >> 2) & 2) == 2)
{
// set clocks
nv3_pramdac_set_pixel_clock();
nv3_pramdac_set_vram_clock();
}
}
void nv3_speed_changed(void* priv)
{
nv3_recalc_timings(&nv3->nvbase.svga);
}
// Force Redraw
// Reset etc.
void nv3_force_redraw(void* priv)
{
nv3->nvbase.svga.fullchange = changeframecount;
}
// Read from SVGA core memory
uint8_t nv3_svga_in(uint16_t addr, void* priv)
{
nv3_t* nv3 = (nv3_t*)priv;
uint8_t ret = 0x00;
// If we need to RMA from GPU MMIO, go do that
if (addr >= NV3_RMA_REGISTER_START
&& addr <= NV3_RMA_REGISTER_END)
{
if (!(nv3->pbus.rma.mode & 0x01))
return ret;
// must be dword aligned
uint32_t real_rma_read_addr = ((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX - 1) << 1) + (addr & 0x03);
ret = nv3_pbus_rma_read(real_rma_read_addr);
return ret;
}
// mask off b0/d0 registers
if ((((addr & 0xFFF0) == 0x3D0
|| (addr & 0xFFF0) == 0x3B0) && addr < 0x3de)
&& !(nv3->nvbase.svga.miscout & 1))
addr ^= 0x60;
switch (addr)
{
// Alias for "get current SVGA CRTC register ID"
case 0x3D4:
ret = nv3->nvbase.svga.crtcreg;
break;
case 0x3D5:
// Support the extended NVIDIA CRTC register range
switch (nv3->nvbase.svga.crtcreg)
{
default:
ret = nv3->nvbase.svga.crtc[nv3->nvbase.svga.crtcreg];
}
break;
default:
ret = svga_in(addr, &nv3->nvbase.svga);
break;
}
return ret; //TEMP
}
// Write to SVGA core memory
void nv3_svga_out(uint16_t addr, uint8_t val, void* priv)
{
// If we need to RMA to GPU MMIO, go do that
if (addr >= NV3_RMA_REGISTER_START
&& addr <= NV3_RMA_REGISTER_END)
{
// we don't need to store these registers...
nv3->pbus.rma.rma_regs[addr & 3] = val;
if (!(nv3->pbus.rma.mode & 0x01)) // we are halfway through sending something
return;
uint32_t real_rma_write_addr = ((nv3->pbus.rma.mode & (NV3_CRTC_REGISTER_RMA_MODE_MAX - 1)) << 1) + (addr & 0x03);
nv3_pbus_rma_write(real_rma_write_addr, nv3->pbus.rma.rma_regs[addr & 3]);
return;
}
// mask off b0/d0 registers
if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0)
&& addr < 0x3de)
&& !(nv3->nvbase.svga.miscout & 1))//miscout bit 7 controls mappping
addr ^= 0x60;
uint8_t crtcreg = nv3->nvbase.svga.crtcreg;
uint8_t old_value;
// todo:
// RMA
// Pixel formats (8bit vs 555 vs 565)
// VBE 3.0?
switch (addr)
{
case 0x3D4:
// real mode access to GPU MMIO space...
nv3->nvbase.svga.crtcreg = val;
break;
// support the extended crtc regs and debug this out
case 0x3D5:
// Implements the VGA Protect register
if ((nv3->nvbase.svga.crtcreg < NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80))
return;
// Ignore certain bits when VGA Protect register set and we are writing to CRTC register=07h
if ((nv3->nvbase.svga.crtcreg == NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80))
val = (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_OVERFLOW] & ~0x10) | (val & 0x10);
// set the register value...
nv3->nvbase.svga.crtc[crtcreg] = val;
// ...now act on it
// Handle nvidia extended Bank0/Bank1 IDs
switch (crtcreg)
{
case NV3_CRTC_REGISTER_READ_BANK:
nv3->nvbase.cio_read_bank = val;
if (nv3->nvbase.svga.chain4) // chain4 addressing (planar?)
nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 15;
else
nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 13; // extended bank numbers
break;
case NV3_CRTC_REGISTER_WRITE_BANK:
nv3->nvbase.cio_write_bank = val;
if (nv3->nvbase.svga.chain4)
nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 15;
else
nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 13;
break;
case NV3_CRTC_REGISTER_RMA:
nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX;
break;
}
break;
default:
svga_out(addr, val, &nv3->nvbase.svga);
break;
}
}
void nv3_draw_cursor(svga_t* svga, int32_t drawline)
{
nv_log("nv3_draw_cursor drawline=0x%04x", drawline);
}
// Initialise the MMIO mappings
void nv3_init_mappings_mmio()
{
nv_log("NV3: Initialising 32MB MMIO area\n");
// 0x0 - 1000000: regs
// 0x1000000-2000000
// initialize the mmio mapping
mem_mapping_add(&nv3->nvbase.mmio_mapping, 0, 0,
nv3_mmio_read8,
nv3_mmio_read16,
nv3_mmio_read32,
nv3_mmio_write8,
nv3_mmio_write16,
nv3_mmio_write32,
NULL, MEM_MAPPING_EXTERNAL, nv3);
// initialize the mmio mapping
mem_mapping_add(&nv3->nvbase.ramin_mapping, 0, 0,
nv3_ramin_read8,
nv3_ramin_read16,
nv3_ramin_read32,
nv3_ramin_write8,
nv3_ramin_write16,
nv3_ramin_write32,
NULL, MEM_MAPPING_EXTERNAL, nv3);
mem_mapping_add(&nv3->nvbase.ramin_mapping_mirror, 0, 0,
nv3_ramin_read8,
nv3_ramin_read16,
nv3_ramin_read32,
nv3_ramin_write8,
nv3_ramin_write16,
nv3_ramin_write32,
NULL, MEM_MAPPING_EXTERNAL, nv3);
}
void nv3_init_mappings_svga()
{
nv_log("NV3: Initialising SVGA core memory mapping\n");
// setup the svga mappings
mem_mapping_set(&nv3->nvbase.framebuffer_mapping, 0, 0,
svga_read_linear,
svga_readw_linear,
svga_readl_linear,
svga_write_linear,
svga_writew_linear,
svga_writel_linear,
NULL, 0, &nv3->nvbase.svga);
// the SVGA/LFB mapping is also mirrored
mem_mapping_set(&nv3->nvbase.framebuffer_mapping_mirror, 0, 0,
svga_read_linear,
svga_readw_linear,
svga_readl_linear,
svga_write_linear,
svga_writew_linear,
svga_writel_linear,
NULL, 0, &nv3->nvbase.svga);
io_sethandler(0x03c0, 0x0020,
nv3_svga_in, NULL, NULL,
nv3_svga_out, NULL, NULL,
nv3);
}
void nv3_init_mappings()
{
nv3_init_mappings_mmio();
nv3_init_mappings_svga();
}
// Updates the mappings after initialisation.
void nv3_update_mappings()
{
// setting this to 0 doesn't seem to disable it, based on the datasheet
nv_log("\nMemory Mapping Config Change:\n");
(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n");
io_removehandler(0x03c0, 0x0020,
nv3_svga_in, NULL, NULL,
nv3_svga_out, NULL, NULL,
nv3);
if (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
io_sethandler(0x03c0, 0x0020,
nv3_svga_in, NULL, NULL,
nv3_svga_out, NULL, NULL,
nv3);
// turn off bar0 and bar1 by defualt
mem_mapping_disable(&nv3->nvbase.mmio_mapping);
mem_mapping_disable(&nv3->nvbase.framebuffer_mapping);
mem_mapping_disable(&nv3->nvbase.framebuffer_mapping_mirror);
mem_mapping_disable(&nv3->nvbase.ramin_mapping);
mem_mapping_disable(&nv3->nvbase.ramin_mapping_mirror);
if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM)
{
nv_log("NV3: The memory was turned off, not much is going to happen.\n");
return;
}
mem_mapping_enable(&nv3->nvbase.mmio_mapping);
mem_mapping_enable(&nv3->nvbase.framebuffer_mapping);
mem_mapping_enable(&nv3->nvbase.framebuffer_mapping_mirror);
mem_mapping_enable(&nv3->nvbase.ramin_mapping);
mem_mapping_enable(&nv3->nvbase.ramin_mapping_mirror);
// first map bar0
nv_log("NV3: BAR0 (MMIO Base) = 0x%08x\n", nv3->nvbase.bar0_mmio_base);
//mem_mapping_enable(&nv3->nvbase.mmio_mapping); // should have no effect if already enabled
mem_mapping_set_addr(&nv3->nvbase.mmio_mapping, nv3->nvbase.bar0_mmio_base, NV3_MMIO_SIZE);
// if this breaks anything, remove it
// skeptical that 0 is used to disable...
nv_log("NV3: BAR1 (Linear Framebuffer / NV_USER Base & RAMIN) = 0x%08x\n", nv3->nvbase.bar1_lfb_base);
// this is likely mirrored
// 4x on 2mb cards
// 2x on 4mb cards
// and not at all on 8mb
mem_mapping_enable(&nv3->nvbase.framebuffer_mapping);
mem_mapping_enable(&nv3->nvbase.framebuffer_mapping_mirror);
mem_mapping_enable(&nv3->nvbase.ramin_mapping);
mem_mapping_enable(&nv3->nvbase.ramin_mapping_mirror);
mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_MMIO_SIZE);
// 4MB VRAM memory map:
// LFB_BASE+VRAM_SIZE=RAMIN Mirror(?) 0x1400000 (VERIFY PCBOX)
// LFB_BASE+VRAM_SIZE*2=LFB Mirror(?) 0x1800000
// LFB_BASE+VRAM_SIZE*3=Definitely RAMIN (then it ends, the total ram space is 16mb) 0x1C00000
mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + VRAM_SIZE_4MB, VRAM_SIZE_4MB);
mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + (VRAM_SIZE_4MB * 2), VRAM_SIZE_4MB);
mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + (VRAM_SIZE_4MB * 3), VRAM_SIZE_4MB);
// TODO: RAMIN and its mirror
// Did we change the banked SVGA mode?
switch (nv3->nvbase.svga.gdcreg[0x06] & 0x0c)
{
case NV3_CRTC_BANKED_128K_A0000:
nv_log("NV3: SVGA Banked Mode = 128K @ A0000h\n");
mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000
nv3->nvbase.svga.banked_mask = 0x1FFFF;
break;
case NV3_CRTC_BANKED_64K_A0000:
nv_log("NV3: SVGA Banked Mode = 64K @ A0000h\n");
mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000
nv3->nvbase.svga.banked_mask = 0xFFFF;
break;
case NV3_CRTC_BANKED_32K_B0000:
nv_log("NV3: SVGA Banked Mode = 32K @ B0000h\n");
mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000
nv3->nvbase.svga.banked_mask = 0x7FFF;
break;
case NV3_CRTC_BANKED_32K_B8000:
nv_log("NV3: SVGA Banked Mode = 32K @ B8000h\n");
mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000
nv3->nvbase.svga.banked_mask = 0x7FFF;
break;
}
}
//
// Init code
//
void* nv3_init(const device_t *info)
{
nv_log("NV3: initialising core\n");
// currently using ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS]
// ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS] seems to be broken :(
int32_t err = rom_init(&nv3->nvbase.vbios, NV3_VBIOS_ERAZOR_V15403, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (err)
nv_log("NV3: failed to load VBIOS err=%d\n", err);
else
nv_log("NV3: Successfully loaded VBIOS %s\n", NV3_VBIOS_ERAZOR_V15403);
// set up the bus and start setting up SVGA core
if (nv3->nvbase.bus_generation == nv_bus_pci)
{
nv_log("NV3: using PCI bus\n");
pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot);
svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, VRAM_SIZE_4MB,
nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL);
}
else if (nv3->nvbase.bus_generation == nv_bus_agp_1x)
{
nv_log("NV3: using AGP 1X bus\n");
pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot);
svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, VRAM_SIZE_4MB,
nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL);
}
// set vram
nv_log("NV3: VRAM=%d bytes\n", nv3->nvbase.svga.vram_max);
// init memory mappings
nv3_init_mappings();
// make us actually exist
nv3->pci_config.int_line = 0xFF; // per datasheet
nv3->pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM;
// svga is done, so now initialise the real gpu
nv_log("NV3: Initialising GPU core...\n");
nv3_pextdev_init(); // Initialise Straps
nv3_pmc_init(); // Initialise Master Control
nv3_pbus_init(); // Initialise Bus (the 128 part of riva)
nv3_pfb_init(); // Initialise Framebuffer Interface
nv3_pramdac_init(); // Initialise RAMDAC (CLUT, final pixel presentation etc)
nv3_pfifo_init(); // Initialise FIFO for graphics object submission
nv3_pgraph_init(); // Initialise accelerated graphics engine
nv3_ptimer_init(); // Initialise programmable interval timer
nv3_pvideo_init(); // Initialise video overlay engines
return nv3;
}
// This function simply allocates ram and sets the bus to pci before initialising.
void* nv3_init_pci(const device_t* info)
{
nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
nv3->nvbase.bus_generation = nv_bus_pci;
nv3_init(info);
}
// This function simply allocates ram and sets the bus to agp before initialising.
void* nv3_init_agp(const device_t* info)
{
nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
nv3->nvbase.bus_generation = nv_bus_agp_1x;
nv3_init(info);
}
// NV3 (RIVA 128)
// PCI
// 2MB or 4MB VRAM
const device_t nv3_device_pci =
{
.name = "NVidia RIVA 128 (NV3) PCI",
.internal_name = "nv3",
.flags = DEVICE_PCI,
.local = 0,
.init = nv3_init_pci,
.close = nv3_close,
.speed_changed = nv3_speed_changed,
.force_redraw = nv3_force_redraw
};
// NV3 (RIVA 128)
// AGP
// 2MB or 4MB VRAM
const device_t nv3_device_agp =
{
.name = "NVidia RIVA 128 (NV3) AGP",
.internal_name = "nv3_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = nv3_init_agp,
.close = nv3_close,
.speed_changed = nv3_speed_changed,
.force_redraw = nv3_force_redraw
};

198
src/video/nv/nv3/nv3_core_arbiter.c Normal file
View File

@@ -0,0 +1,198 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* The insane NV3 MMIO arbiter.
* Writes to ALL sections of the GPU based on the write position
* All writes are internally considered to be 32-bit! Be careful...
*
* Also handles interrupt dispatch
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
// STANDARD NV3 includes
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Gets a register...
// move this somewhere else when we have more models
nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs)
{
for (int32_t reg_num = 0; reg_num < num_regs; reg_num++)
{
if (register_list[reg_num].address == NV_REG_LIST_END)
break; //unimplemented
if (register_list[reg_num].address == address)
return &register_list[reg_num];
}
return NULL;
}
// Arbitrates an MMIO read
uint32_t nv3_mmio_arbitrate_read(uint32_t address)
{
uint32_t ret = 0x00;
// note: some registers are byte aligned not dword aligned
// only very few are though, so they can be handled specially, using the register list most likely
address &= 0xFFFFFC;
// gigantic set of if statements to send the write to the right subsystem
if (address >= NV3_PMC_START && address <= NV3_PMC_END)
ret = nv3_pmc_read(address);
else if (address >= NV3_CIO_START && address <= NV3_CIO_END)
ret = nv3_cio_read(address);
else if (address >= NV3_PBUS_PCI_START && address <= NV3_PBUS_PCI_END)
ret = nv3_pci_read(0x00, address & 0xFF, NULL);
else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END)
ret = nv3_pbus_read(address);
else if (address >= NV3_PFB_START && address <= NV3_PFB_END)
ret = nv3_pfb_read(address);
else if (address >= NV3_PRM_START && address <= NV3_PRM_END)
ret = nv3_prm_read(address);
else if (address >= NV3_PRMIO_START && address <= NV3_PRMIO_END)
ret = nv3_prmio_read(address);
else if (address >= NV3_PTIMER_START && address <= NV3_PTIMER_END)
ret = nv3_ptimer_read(address);
else if (address >= NV3_PFB_START && address <= NV3_PFB_END)
ret = nv3_pfb_read(address);
else if (address >= NV3_PEXTDEV_START && address <= NV3_PEXTDEV_END)
ret = nv3_pextdev_read(address);
else if (address >= NV3_PROM_START && address <= NV3_PROM_END)
ret = nv3_prom_read(address);
else if (address >= NV3_PALT_START && address <= NV3_PALT_END)
ret = nv3_palt_read(address);
else if (address >= NV3_PME_START && address <= NV3_PME_END)
ret = nv3_pme_read(address);
else if (address >= NV3_PGRAPH_START && address <= NV3_PGRAPH_REAL_END) // what we're actually doing here determined by nv3_pgraph_* func
ret = nv3_pgraph_read(address);
else if (address >= NV3_PRMCIO_START && address <= NV3_PRMCIO_END)
ret = nv3_prmcio_read(address);
else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END)
ret = nv3_pvideo_read(address);
else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END)
ret = nv3_pramdac_read(address);
else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END)
ret = nv3_vram_read(address);
else if (address >= NV3_USER_START && address <= NV3_USER_END)
ret = nv3_user_read(address);
else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END)
ret = nv3_pramin_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function
else
{
nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address);
return 0x00;
}
nv_log("NV3: MMIO read, 0x%08x <- 0x%08x\n", ret, address);
return ret;
}
void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value)
{
// note: some registers are byte aligned not dword aligned
// only very few are though, so they can be handled specially, using the register list most likely
address &= 0xFFFFFC;
// gigantic set of if statements to send the write to the right subsystem
if (address >= NV3_PMC_START && address <= NV3_PMC_END)
nv3_pmc_write(address, value);
else if (address >= NV3_CIO_START && address <= NV3_CIO_END)
nv3_cio_write(address, value);
else if (address >= NV3_PBUS_PCI_START && address <= NV3_PBUS_PCI_END) // PCI mirrored at 0x1800 in MMIO
nv3_pci_write(0x00, address & 0xFF, value, NULL); // priv does not matter
else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END)
nv3_pbus_write(address, value);
else if (address >= NV3_PFIFO_START && address <= NV3_PFIFO_END)
nv3_pfifo_write(address, value);
else if (address >= NV3_PRM_START && address <= NV3_PRM_END)
nv3_prm_write(address, value);
else if (address >= NV3_PRMIO_START && address <= NV3_PRMIO_END)
nv3_prmio_write(address, value);
else if (address >= NV3_PTIMER_START && address <= NV3_PTIMER_END)
nv3_ptimer_write(address, value);
else if (address >= NV3_PFB_START && address <= NV3_PFB_END)
nv3_pfb_write(address, value);
else if (address >= NV3_PEXTDEV_START && address <= NV3_PEXTDEV_END)
nv3_pextdev_write(address, value);
else if (address >= NV3_PROM_START && address <= NV3_PROM_END)
nv3_prom_write(address, value);
else if (address >= NV3_PALT_START && address <= NV3_PALT_END)
nv3_palt_write(address, value);
else if (address >= NV3_PME_START && address <= NV3_PME_END)
nv3_pme_write(address, value);
else if (address >= NV3_PGRAPH_START && address <= NV3_PGRAPH_REAL_END) // what we're actually doing here is determined by the nv3_pgraph_* functions
nv3_pgraph_write(address, value);
else if (address >= NV3_PRMCIO_START && address <= NV3_PRMCIO_END)
nv3_prmcio_write(address, value);
else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END)
nv3_pvideo_write(address, value);
else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END)
nv3_pramdac_write(address, value);
else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END)
nv3_vram_write(address, value);
else if (address >= NV3_USER_START && address <= NV3_USER_END)
nv3_user_write(address, value);
else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END)
nv3_pramin_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions
else
{
nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address);
return;
}
nv_log("NV3: MMIO write, 0x%08x -> 0x%08x\n", value, address);
}
// //
// ******* DUMMY FUNCTIONS FOR UNIMPLEMENTED SUBSYSTEMS ******* //
// //
// Read and Write functions for GPU subsystems
// Remove the ones that aren't used here eventually, have all of htem for now
uint32_t nv3_cio_read(uint32_t address) { return 0; };
void nv3_cio_write(uint32_t address, uint32_t value) {};
uint32_t nv3_prm_read(uint32_t address) { return 0; };
void nv3_prm_write(uint32_t address, uint32_t value) {};
uint32_t nv3_prmio_read(uint32_t address) { return 0; };
void nv3_prmio_write(uint32_t address, uint32_t value) {};
uint32_t nv3_ptimer_read(uint32_t address) { return 0; };
void nv3_ptimer_write(uint32_t address, uint32_t value) {};
uint32_t nv3_prom_read(uint32_t address) { return 0; };
void nv3_prom_write(uint32_t address, uint32_t value) {};
uint32_t nv3_palt_read(uint32_t address) { return 0; };
void nv3_palt_write(uint32_t address, uint32_t value) {};
// TODO: PGRAPH class registers
uint32_t nv3_prmcio_read(uint32_t address) { return 0; };
void nv3_prmcio_write(uint32_t address, uint32_t value) {};
uint32_t nv3_vram_read(uint32_t address) { return 0; };
void nv3_vram_write(uint32_t address, uint32_t value) {};
uint32_t nv3_user_read(uint32_t address) { return 0; };
void nv3_user_write(uint32_t address, uint32_t value) {};
uint32_t nv3_pramin_read(uint32_t address) { return 0; };
void nv3_pramin_write(uint32_t address, uint32_t value) {};

0
src/video/nv/nv3/nv3_interrupt.c Normal file
View File

249
src/video/nv/nv3/subsystems/nv3_pbus.c Normal file
View File

@@ -0,0 +1,249 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PBUS: 128-bit unified bus
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email dataess ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// NV3 PBUS RMA - Real Mode Access for VBIOS
// This basically works like a shifter, you write one byte at a time from [0x3d0...0x3d3] and it shifts it in to build a 32-bit MMIO address...
// Putting this in pbus because imo it makes the most sense (related to memory access/memory interface)
nv_register_t pbus_registers[] = {
{ NV3_PBUS_INTR, "PBUS - Interrupt Status", NULL, NULL},
{ NV3_PBUS_INTR_EN, "PBUS - Interrupt Enable", NULL, NULL,},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
void nv3_pbus_init()
{
nv_log("NV3: Initialising PBUS...");
nv_log("Done\n");
}
uint32_t nv3_pbus_read(uint32_t address)
{
nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0]));
// todo: friendly logging
nv_log("NV3: PBUS Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
switch (reg->address)
{
case NV3_PBUS_INTR:
return nv3->pbus.interrupt_status;
break;
case NV3_PBUS_INTR_EN:
return nv3->pbus.interrupt_enable;
break;
}
}
}
return 0x0;
}
void nv3_pbus_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0]));
nv_log("NV3: PBUS Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
switch (reg->address)
{
// Interrupt registers
// Interrupt state:
// Bit 0 - PCI Bus Error
case NV3_PBUS_INTR:
nv3->pbus.interrupt_status &= ~value;
nv3_pmc_clear_interrupts();
break;
case NV3_PBUS_INTR_EN:
nv3->pbus.interrupt_enable = value & 0x00000001;
break;
}
}
}
}
uint8_t nv3_pbus_rma_read(uint16_t addr)
{
addr &= 0xFF;
uint32_t real_final_address;
uint8_t ret;
switch (addr)
{
// signature so you know reads work
case 0x00:
ret = NV3_RMA_SIGNATURE_MSB;
break;
case 0x01:
ret = NV3_RMA_SIGNATURE_BYTE2;
break;
case 0x02:
ret = NV3_RMA_SIGNATURE_BYTE1;
break;
case 0x03:
ret = NV3_RMA_SIGNATURE_LSB;
break;
case 0x08 ... 0x0B:
// reads must be dword aligned
real_final_address = (nv3->pbus.rma.addr + (addr & 0x03));
if (nv3->pbus.rma.addr < NV3_MMIO_SIZE)
ret = nv3_mmio_read8(real_final_address, NULL);
else
{
// ABOVE CODE IS TEMPORARY UNTIL PNVM EXISTS!!!!!
// would svga->fast work?
nv3->nvbase.svga.chain4 = true;
nv3->nvbase.svga.packed_chain4 = true;
ret = svga_read_linear((real_final_address - NV3_MMIO_SIZE) & (VRAM_SIZE_4MB - 1), &nv3->nvbase.svga);
nv3->nvbase.svga.chain4 = false;
nv3->nvbase.svga.packed_chain4 = false;
}
// log current location for vbios RE
nv_log("NV3: MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
addr, real_final_address, ret);
break;
}
return ret;
}
// Implements a 32-bit write using 16 bit port number
void nv3_pbus_rma_write(uint16_t addr, uint8_t val)
{
uint8_t ret = 0x00;
// addresses are in reality 8bit so just mask it to be safe
addr &= 0xFF;
// format:
// 0x00 ID
// 0x04 Pointer to data
// 0x08 Data port(?)
// 0x0B Data - 32bit. SENT IN THE RIGHT ORDER FOR ONCE WAHOO!
// 0x10 Increment (?) data - implemented the same as data for now
if (addr < 0x08)
{
switch (addr % 0x04)
{
case 0x00: // lowest byte
nv3->pbus.rma.addr &= ~0xff;
nv3->pbus.rma.addr |= val;
break;
case 0x01: // 2nd highest byte
nv3->pbus.rma.addr &= ~0xff00;
nv3->pbus.rma.addr |= (val << 8);
break;
case 0x02: // 3rd highest byte
nv3->pbus.rma.addr &= ~0xff0000;
nv3->pbus.rma.addr |= (val << 16);
break;
case 0x03: // 4th highest byte
nv3->pbus.rma.addr &= ~0xff000000;
nv3->pbus.rma.addr |= (val << 24);
break;
}
}
// Data to send to MMIO
else
{
switch (addr % 0x04)
{
case 0x00: // lowest byte
nv3->pbus.rma.data &= ~0xff;
nv3->pbus.rma.data |= val;
break;
case 0x01: // 2nd highest byte
nv3->pbus.rma.data &= ~0xff00;
nv3->pbus.rma.data |= (val << 8);
break;
case 0x02: // 3rd highest byte
nv3->pbus.rma.data &= ~0xff0000;
nv3->pbus.rma.data |= (val << 16);
break;
case 0x03: // 4th highest byte
nv3->pbus.rma.data &= ~0xff000000;
nv3->pbus.rma.data |= (val << 24);
nv_log("NV3: MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
addr, nv3->pbus.rma.addr, nv3->pbus.rma.data);
if (nv3->pbus.rma.addr < NV3_MMIO_SIZE)
nv3_mmio_write32(nv3->pbus.rma.addr, nv3->pbus.rma.data, NULL);
else // failsafe code, i don't think you will ever write outside of VRAM?
{
nv3->nvbase.svga.chain4 = true;
nv3->nvbase.svga.packed_chain4 = true;
svga_writel_linear((nv3->pbus.rma.addr - NV3_MMIO_SIZE) & (VRAM_SIZE_4MB - 1), nv3->pbus.rma.data, &nv3->nvbase.svga);
nv3->nvbase.svga.chain4 = false;
nv3->nvbase.svga.packed_chain4 = false;
}
break;
}
}
if (addr & 0x10)
nv3->pbus.rma.addr += 0x04; // Alignment
}

31
src/video/nv/nv3/subsystems/nv3_pbus_dma.c Normal file
View File

@@ -0,0 +1,31 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PBUS DMA: DMA Engine
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...

149
src/video/nv/nv3/subsystems/nv3_pextdev.c Normal file
View File

@@ -0,0 +1,149 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PEXTDEV - External Devices
* Including straps
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
void nv3_pextdev_init()
{
nv_log("NV3: Initialising PEXTDEV....\n");
// Set the chip straps
// Make these configurable in the future...
// Current settings
// AGP2X Disabled
// TV Mode NTSC
// Crystal 13.5 Mhz
// Bus width 128-Bit (some gpus were sold as 64bit for cost reduction)
//
nv_log("NV3: Initialising straps...\n");
nv3->pextdev.straps =
(NV3_PSTRAPS_AGP2X_DISABLED << NV3_PSTRAPS_AGP2X) |
(NV3_PSTRAPS_TVMODE_NTSC << NV3_PSTRAPS_TVMODE) |
(NV3_PSTRAPS_CRYSTAL_13500K << NV3_PSTRAPS_CRYSTAL);
// figure out the bus
if (nv3->nvbase.bus_generation == nv_bus_pci)
nv3->pextdev.straps |= (NV3_PSTRAPS_BUS_TYPE_PCI << NV3_PSTRAPS_BUS_TYPE);
else
nv3->pextdev.straps |= (NV3_PSTRAPS_BUS_TYPE_AGP << NV3_PSTRAPS_BUS_TYPE);
// now the lower bits
nv3->pextdev.straps |=
(NV3_PSTRAPS_BUS_WIDTH_128BIT << NV3_PSTRAPS_BUS_WIDTH) |
(NV3_PSTRAPS_BIOS_PRESENT << NV3_PSTRAPS_BIOS) |
(NV3_PSTRAPS_BUS_SPEED_66MHZ << NV3_PSTRAPS_BUS_SPEED);
nv_log("NV3: Straps = 0x%04x\n", nv3->pextdev.straps);
nv_log("NV3: Initialising PEXTDEV: Done\n");
}
//
// ****** PEXTDEV register list START ******
//
nv_register_t pextdev_registers[] = {
{ NV3_PSTRAPS, "Straps - Chip Configuration", NULL, NULL },
{ NV_REG_LIST_END, NULL, NULL, NULL }, // sentinel value
};
//
// ****** Read/Write functions start ******
//
uint32_t nv3_pextdev_read(uint32_t address)
{
nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0]));
// todo: friendly logging
// special consideration for straps
if (address == NV3_PSTRAPS)
{
nv_log("NV3: Straps Read (current value=0x%08x)\n", nv3->pextdev.straps);
}
else
{
nv_log("NV3: PEXTDEV Read from 0x%08x", address);
}
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
switch (reg->address)
{
case NV3_PSTRAPS:
return nv3->pextdev.straps;
}
}
}
return 0x0;
}
void nv3_pextdev_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0]));
nv_log("NV3: PEXTDEV Write 0x%08x -> 0x%08x\n", value, address);
// special consideration for straps
if (address == NV3_PSTRAPS)
{
nv_log("NV3: Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps);
return;
}
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
}
}

109
src/video/nv/nv3/subsystems/nv3_pfb.c Normal file
View File

@@ -0,0 +1,109 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PFB: Framebuffer
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
nv_register_t pfb_registers[] = {
{ NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
void nv3_pfb_init()
{
nv_log("NV3: Initialising PFB...");
// initial configuration:
// ram 4mb
// bus width 128bit
// extension ram none (was this ever used?)
// ram banks 4 (based on observation of physical RIVA 128 with 4mb, does 1 bank = 1chip?)
// twiddle off (check this on a real card once it's actually installed)
nv3->pfb.boot = (NV3_PFB_BOOT_RAM_EXTENSION_NONE << (NV3_PFB_BOOT_RAM_EXTENSION)
| (NV3_PFB_BOOT_RAM_DATA_TWIDDLE_OFF << NV3_PFB_BOOT_RAM_DATA_TWIDDLE)
| (NV3_PFB_BOOT_RAM_BANKS_4 << NV3_PFB_BOOT_RAM_BANKS)
| (NV3_PFB_BOOT_RAM_WIDTH_128 << NV3_PFB_BOOT_RAM_WIDTH)
| (NV3_PFB_BOOT_RAM_AMOUNT_4MB << NV3_PFB_BOOT_RAM_AMOUNT)
);
nv_log("Done\n");
}
uint32_t nv3_pfb_read(uint32_t address)
{
nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0]));
// todo: friendly logging
nv_log("NV3: PFB Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
switch (reg->address)
{
case NV3_PFB_BOOT:
return nv3->pfb.boot;
break;
}
}
}
return 0x0;
}
void nv3_pfb_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0]));
nv_log("NV3: PFB Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
}
}

146
src/video/nv/nv3/subsystems/nv3_pfifo.c Normal file
View File

@@ -0,0 +1,146 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 pfifo (FIFO for graphics object submission)
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...
//
// ****** pfifo register list START ******
//
nv_register_t pfifo_registers[] = {
{ NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL},
{ NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
// PFIFO init code
void nv3_pfifo_init()
{
nv_log("NV3: Initialising PFIFO...");
nv_log("Done!\n");
}
uint32_t nv3_pfifo_read(uint32_t address)
{
// before doing anything, check the subsystem enablement state
if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO)
& NV3_PMC_ENABLE_PFIFO_ENABLED)
{
nv_log("NV3: Repressing PFIFO read. The subsystem is disabled according to pmc_enable, returning 0\n");
return 0x00;
}
nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0]));
// todo: friendly logging
nv_log("NV3: PFIFO Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
// Interrupt state:
// Bit 0 - Cache Error
// Bit 4 - RAMRO Triggered
// Bit 8 - RAMRO Overflow (too many invalid dma objects)
// Bit 12 - DMA Pusher
// Bit 16 - DMA Page Table Entry (pagefault?)
switch (reg->address)
{
case NV3_PFIFO_INTR:
return nv3->pfifo.interrupt_status;
case NV3_PFIFO_INTR_EN:
return nv3->pfifo.interrupt_enable;
}
}
}
return 0x0;
}
void nv3_pfifo_write(uint32_t address, uint32_t value)
{
// before doing anything, check the subsystem enablement
if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO)
& NV3_PMC_ENABLE_PFIFO_ENABLED)
{
nv_log("NV3: Repressing PFIFO write. The subsystem is disabled according to pmc_enable\n");
return;
}
nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0]));
nv_log("NV3: pfifo Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
switch (reg->address)
{
// Interrupt state:
// Bit 0 - Cache Error
// Bit 4 - RAMRO Triggered
// Bit 8 - RAMRO Overflow (too many invalid dma objects)
// Bit 12 - DMA Pusher
// Bit 16 - DMA Page Table Entry (pagefault?)
case NV3_PFIFO_INTR:
nv3->pfifo.interrupt_status &= ~value;
nv3_pmc_clear_interrupts();
break;
case NV3_PFIFO_INTR_EN:
nv3->pbus.interrupt_enable = value & 0x00001111;
break;
}
}
}
}

151
src/video/nv/nv3/subsystems/nv3_pgraph.c Normal file
View File

@@ -0,0 +1,151 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PGRAPH (Scene Graph for 2D/3D Accelerated Graphics)
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...
//
// ****** PGRAPH register list START ******
//
void nv3_pgraph_init()
{
nv_log("NV3: Initialising PGRAPH...");
nv_log("Done!\n");
}
nv_register_t pgraph_registers[] = {
{ NV3_PGRAPH_INTR_0, "PGRAPH Interrupt Status 0", NULL, NULL },
{ NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL },
{ NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL },
{ NV3_PGRAPH_INTR_EN_1, "PGRAPH Interrupt Enable 1", NULL, NULL },
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
uint32_t nv3_pgraph_read(uint32_t address)
{
// before doing anything, check that this is even enabled..
if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH)
& NV3_PMC_ENABLE_PGRAPH_ENABLED)
{
nv_log("NV3: Repressing PGRAPH read. The subsystem is disabled according to pmc_enable, returning 0\n");
return 0x00;
}
nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0]));
// todo: friendly logging
nv_log("NV3: PGRAPH Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
switch (reg->address)
{
//interrupt status and enable regs
case NV3_PGRAPH_INTR_0:
return nv3->pgraph.interrupt_status_0;
case NV3_PGRAPH_INTR_1:
return nv3->pgraph.interrupt_status_1;
case NV3_PGRAPH_INTR_EN_0:
return nv3->pgraph.interrupt_enable_0;
case NV3_PGRAPH_INTR_EN_1:
return nv3->pgraph.interrupt_enable_1;
}
}
}
return 0x0;
}
void nv3_pgraph_write(uint32_t address, uint32_t value)
{
if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH)
& NV3_PMC_ENABLE_PGRAPH_ENABLED)
{
nv_log("NV3: Repressing PGRAPH write. The subsystem is disabled according to pmc_enable\n");
return;
}
nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0]));
nv_log("NV3: pgraph Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
switch (reg->address)
{
//interrupt status and enable regs
case NV3_PGRAPH_INTR_0:
nv3->pgraph.interrupt_status_0 &= ~value;
//we changed interrupt state
nv3_pmc_clear_interrupts();
break;
case NV3_PGRAPH_INTR_1:
nv3->pgraph.interrupt_status_1 &= ~value;
//we changed interrupt state
nv3_pmc_clear_interrupts();
break;
// Only bits divisible by 4 matter
// and only bit0-16 is defined in intr_1
case NV3_PGRAPH_INTR_EN_0:
nv3->pgraph.interrupt_enable_0 = value & 0x11111111;
break;
case NV3_PGRAPH_INTR_EN_1:
nv3->pgraph.interrupt_enable_1 = value & 0x00011111;
break;
}
}
}
}

236
src/video/nv/nv3/subsystems/nv3_pmc.c Normal file
View File

@@ -0,0 +1,236 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PMC - Master control for the chip
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...
void nv3_pmc_init()
{
nv_log("NV3: Initialising PMC....\n");
nv3->pmc.boot = NV3_BOOT_REG_DEFAULT;
nv_log("NV3: Initialising PMC: Done\n");
}
//
// ****** PMC register list START ******
//
nv_register_t pmc_registers[] = {
{ NV3_PMC_BOOT, "PMC: Boot Manufacturing Information", NULL, NULL },
{ NV3_PMC_INTERRUPT_STATUS, "PMC: Current Pending Subsystem Interrupts", NULL, NULL},
{ NV3_PMC_INTERRUPT_ENABLE, "PMC: Global Interrupt Enable", NULL, NULL,},
{ NV3_PMC_ENABLE, "PMC: Global Subsystem Enable", NULL, NULL },
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
uint32_t nv3_pmc_clear_interrupts()
{
nv_log("NV3: Clearing IRQs\n");
pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
}
// Handle hardware interrupts
// We only clear when we need to, in other functions...
uint32_t nv3_pmc_handle_interrupts(bool send_now)
{
// TODO:
// PGRAPH DMA INTR_EN (there is no DMA engine yet)
// PRM Real-Mode Compatibility Interrupts
uint32_t new_intr_value;
// set the new interrupt value
// PAUDIO not used
// IF NV3 REV A EMULATION IS ADDED, ADD THIS COMPONENT!
// the registers are designed to line up so you can enable specific interrupts
// Check Mediaport interrupts
if (nv3->pme.interrupt_status & nv3->pme.interrupt_enable)
new_intr_value |= (NV3_PMC_INTERRUPT_PMEDIA_PENDING << NV3_PMC_INTERRUPT_PMEDIA);
// Check FIFO interrupts
if (nv3->pfifo.interrupt_status & nv3->pfifo.interrupt_enable)
new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO);
// PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...clean this up once we verify it
if (nv3->pgraph.interrupt_status_0 & (1 << 8))
new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB);
else if (nv3->pgraph.interrupt_status_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt
new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0);
// Check second pgraph interrupt register
if (nv3->pgraph.interrupt_status_1 & nv3->pgraph.interrupt_enable_1)
new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH1_PENDING << NV3_PMC_INTERRUPT_PGRAPH1);
// check video overlay interrupts
if (nv3->pvideo.interrupt_status & nv3->pvideo.interrupt_enable)
new_intr_value |= (NV3_PMC_INTERRUPT_PVIDEO_PENDING << NV3_PMC_INTERRUPT_PVIDEO);
// check PIT interrupts
if (nv3->ptimer.interrupt_status & nv3->ptimer.interrupt_enable)
new_intr_value |= (NV3_PMC_INTERRUPT_PTIMER_PENDING << NV3_PMC_INTERRUPT_PTIMER);
// check bus interrupts
if (nv3->pbus.interrupt_status & nv3->pbus.interrupt_enable)
new_intr_value |= (NV3_PMC_INTERRUPT_PBUS_PENDING << NV3_PMC_INTERRUPT_PBUS);
// check SW interrupts
if (nv3->pmc.interrupt_status & (1 << NV3_PMC_INTERRUPT_SOFTWARE))
new_intr_value |= (NV3_PMC_INTERRUPT_SOFTWARE_PENDING << NV3_PMC_INTERRUPT_SOFTWARE);
nv3->pmc.interrupt_status = new_intr_value;
// ***TODO: DOes INTR still change if INTR_EN=0???***
// If interrupts are disabled don't bother
if (!nv3->pmc.interrupt_enable)
nv3_pmc_clear_interrupts();
// if we actually need to send the interrupt (i.e. this is a write) send it now
if (send_now)
{
if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF))
{
if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE)
{
nv_log("NV3: Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status);
pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
}
else
nv_log("NV3: NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status);
}
else
{
if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_SOFTWARE)
{
nv_log("NV3: Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status);
pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
}
else
nv_log("NV3: NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status);
}
}
return nv3->pmc.interrupt_status;
}
//
// ****** Read/Write functions start ******
//
uint32_t nv3_pmc_read(uint32_t address)
{
nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0]));
// todo: friendly logging
nv_log("NV3: PMC Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
switch (reg->address)
{
case NV3_PMC_BOOT:
return nv3->pmc.boot;
case NV3_PMC_INTERRUPT_STATUS:
nv3_pmc_clear_interrupts();
return nv3_pmc_handle_interrupts(false);
case NV3_PMC_INTERRUPT_ENABLE:
//TODO: ACTUALLY CHANGE THE INTERRUPT STATE
return nv3->pmc.interrupt_enable;
case NV3_PMC_ENABLE:
return nv3->pmc.enable;
}
}
}
return 0x0;
}
void nv3_pmc_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0]));
nv_log("NV3: PMC Write 0x%08x -> 0x%08x", value, address);
// if the register actually exists...
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// ... call its on-write function
if (reg->on_write)
reg->on_write(value);
else
{
// if it doesn't have one fallback to a switch statement
switch (reg->address)
{
case NV3_PMC_INTERRUPT_STATUS:
// this
if (!(nv3->pmc.interrupt_status & (NV3_PMC_INTERRUPT_SOFTWARE - 1)))
{
nv_log("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger "
" an interrupt on, rather than writing to NV3_PMC_INTERRUPT_STATUS (Or this is a bug)...NV3_PMC_INTERRUPT_STATUS=0x%08x)\n", nv3->pmc.interrupt_enable);
return;
}
nv3_pmc_handle_interrupts(true);
nv3->pmc.interrupt_status = value;
break;
case NV3_PMC_INTERRUPT_ENABLE:
nv3->pmc.interrupt_enable = value;
break;
case NV3_PMC_ENABLE:
nv3->pmc.enable = value;
break;
}
}
}
}

123
src/video/nv/nv3/subsystems/nv3_pme.c Normal file
View File

@@ -0,0 +1,123 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 pme: Nvidia Mediaport - External MPEG Decode Interface
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
nv_register_t pme_registers[] = {
{ NV3_PME_INTR, "PME - Interrupt Status", NULL, NULL},
{ NV3_PME_INTR_EN, "PME - Interrupt Enable", NULL, NULL,},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
void nv3_pme_init()
{
nv_log("NV3: Initialising PME...");
nv_log("Done\n");
}
uint32_t nv3_pme_read(uint32_t address)
{
nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0]));
// todo: friendly logging
nv_log("NV3: PME Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
// Interrupt state:
// Bit 0 - Image Notifier
// Bit 4 - Vertical Blank Interfal Notifier
// Bit 8 - Video Notifier
// Bit 12 - Audio Notifier
// Bit 16 - VMI Notifer
switch (reg->address)
{
case NV3_PME_INTR:
return nv3->pme.interrupt_status;
case NV3_PME_INTR_EN:
return nv3->pme.interrupt_enable;
}
}
}
return 0x0;
}
void nv3_pme_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0]));
nv_log("NV3: PME Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
switch (reg->address)
{
// Interrupt state:
// Bit 0 - Image Notifier
// Bit 4 - Vertical Blank Interfal Notifier
// Bit 8 - Video Notifier
// Bit 12 - Audio Notifier
// Bit 16 - VMI Notifer
case NV3_PME_INTR:
nv3->pme.interrupt_status &= ~value;
nv3_pmc_clear_interrupts();
break;
case NV3_PME_INTR_EN:
nv3->pme.interrupt_enable = value & 0x00001111;
break;
}
}
}
}

307
src/video/nv/nv3/subsystems/nv3_pramdac.c Normal file
View File

@@ -0,0 +1,307 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 bringup and device emulation.
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
// nv3_pramdac.c: NV3 RAMDAC
// Todo: Allow overridability using 68050C register...
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
void nv3_pramdac_init()
{
nv_log("NV3: Initialising PRAMDAC\n");
// defaults, these come from vbios in reality
// driver defaults are nonsensical(?), or the algorithm is wrong
// munged this to 100mhz for now
nv3->pramdac.memory_clock_m = nv3->pramdac.pixel_clock_m = 0x07;
nv3->pramdac.memory_clock_n = nv3->pramdac.pixel_clock_n = 0xc8;
nv3->pramdac.memory_clock_p = nv3->pramdac.pixel_clock_p = 0x0c;
nv3_pramdac_set_pixel_clock();
nv3_pramdac_set_vram_clock();
nv_log("NV3: Initialising PRAMDAC: Done\n");
}
uint32_t nv3_pramdac_get_vram_clock_register()
{
// pack into 19 bits
// M divisor [7-0]
// N divisor [16-8]
// P divisor [18-16]
return (nv3->pramdac.memory_clock_m << 16) & 0xFF;
+ (nv3->pramdac.memory_clock_n << 8) & 0xFF;
+ (nv3->pramdac.memory_clock_p) & 0x07; // 0-3
}
uint32_t nv3_pramdac_get_pixel_clock_register()
{
return (nv3->pramdac.pixel_clock_m << 16) & 0xFF;
+ (nv3->pramdac.pixel_clock_n << 8) & 0xFF;
+ (nv3->pramdac.pixel_clock_p) & 0x07; // 0-3
}
void nv3_pramdac_set_vram_clock_register(uint32_t value)
{
nv3->pramdac.memory_clock_m = value & 0xFF;
nv3->pramdac.memory_clock_n = (value >> 8) & 0xFF;
nv3->pramdac.memory_clock_p = (value >> 16) & 0x07;
nv3_pramdac_set_vram_clock();
}
void nv3_pramdac_set_pixel_clock_register(uint32_t value)
{
nv3->pramdac.pixel_clock_m = value & 0xFF;
nv3->pramdac.pixel_clock_n = (value >> 8) & 0xFF;
nv3->pramdac.pixel_clock_p = (value >> 16) & 0x07;
nv3_pramdac_set_pixel_clock();
}
void nv3_pramdac_set_vram_clock()
{
// from driver and vbios source
float frequency = 13500000.0f;
// prevent division by 0
if (nv3->pramdac.memory_clock_m == 0)
nv3->pramdac.memory_clock_m == 1;
else
frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p);
nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f);
}
void nv3_pramdac_set_pixel_clock()
{
// frequency divider algorithm from old varcem/86box/pcbox riva driver,
// verified by reversing NT drivers v1.50e CalcMNP [symbols] function
// todo: actually implement it
// missing section
// not really needed.
// if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500)
// {
// freq = 13500000.0f;
// }
// else
//
// {
// freq = 14318000.0f;
// }
float frequency = 13500000.0f;
// prevent division by 0
if (nv3->pramdac.pixel_clock_m == 0)
nv3->pramdac.pixel_clock_m == 1;
else
frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p);
nv3->nvbase.svga.clock = cpuclock / frequency;
nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f);
}
//
// ****** PRAMDAC register list START ******
//
// NULL means handle in read functions
nv_register_t pramdac_registers[] =
{
{ NV3_PRAMDAC_CLOCK_PIXEL, "PRAMDAC - NV3 GPU Core - Pixel clock", nv3_pramdac_get_pixel_clock_register, nv3_pramdac_set_pixel_clock_register },
{ NV3_PRAMDAC_CLOCK_MEMORY, "PRAMDAC - NV3 GPU Core - Memory clock", nv3_pramdac_get_vram_clock_register, nv3_pramdac_set_vram_clock_register },
{ NV3_PRAMDAC_COEFF_SELECT, "PRAMDAC - PLL Clock Coefficient Select", NULL, NULL},
{ NV3_PRAMDAC_GENERAL_CONTROL, "PRAMDAC - General Control", NULL, NULL },
{ NV3_PRAMDAC_VSERR_WIDTH, "PRAMDAC - Vertical Sync Error Width", NULL, NULL},
{ NV3_PRAMDAC_VEQU_END, "PRAMDAC - VEqu End", NULL, NULL},
{ NV3_PRAMDAC_VBBLANK_END, "PRAMDAC - VBBlank End", NULL, NULL},
{ NV3_PRAMDAC_VBLANK_END, "PRAMDAC - Vertical Blanking Interval End", NULL, NULL},
{ NV3_PRAMDAC_VBLANK_START, "PRAMDAC - Vertical Blanking Interval Start", NULL, NULL},
{ NV3_PRAMDAC_VEQU_START, "PRAMDAC - VEqu Start", NULL, NULL},
{ NV3_PRAMDAC_VTOTAL, "PRAMDAC - Total Vertical Lines", NULL, NULL},
{ NV3_PRAMDAC_HSYNC_WIDTH, "PRAMDAC - Horizontal Sync Pulse Width", NULL, NULL},
{ NV3_PRAMDAC_HBURST_START, "PRAMDAC - Horizontal Burst Signal Start", NULL, NULL},
{ NV3_PRAMDAC_HBURST_END, "PRAMDAC - Horizontal Burst Signal Start", NULL, NULL},
{ NV3_PRAMDAC_HTOTAL, "PRAMDAC - Total Horizontal Lines", NULL, NULL},
{ NV3_PRAMDAC_HEQU_WIDTH, "PRAMDAC - HEqu End", NULL, NULL},
{ NV3_PRAMDAC_HSERR_WIDTH, "PRAMDAC - Horizontal Sync Error", NULL, NULL},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
//
// ****** Read/Write functions start ******
//
uint32_t nv3_pramdac_read(uint32_t address)
{
nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0]));
// todo: friendly logging
nv_log("NV3: PRAMDAC Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
//s hould be pretty easy to understand
switch (reg->address)
{
case NV3_PRAMDAC_COEFF_SELECT:
return nv3->pramdac.coeff_select;
case NV3_PRAMDAC_GENERAL_CONTROL:
return nv3->pramdac.general_control;
case NV3_PRAMDAC_VSERR_WIDTH:
return nv3->pramdac.vserr_width;
case NV3_PRAMDAC_VBBLANK_END:
return nv3->pramdac.vbblank_end;
case NV3_PRAMDAC_VBLANK_END:
return nv3->pramdac.vblank_end;
case NV3_PRAMDAC_VBLANK_START:
return nv3->pramdac.vblank_start;
case NV3_PRAMDAC_VEQU_START:
return nv3->pramdac.vequ_start;
case NV3_PRAMDAC_VTOTAL:
return nv3->pramdac.vtotal;
case NV3_PRAMDAC_HSYNC_WIDTH:
return nv3->pramdac.hsync_width;
case NV3_PRAMDAC_HBURST_START:
return nv3->pramdac.hburst_start;
case NV3_PRAMDAC_HBURST_END:
return nv3->pramdac.hburst_end;
case NV3_PRAMDAC_HBLANK_START:
return nv3->pramdac.hblank_start;
case NV3_PRAMDAC_HBLANK_END:
return nv3->pramdac.hblank_end;
case NV3_PRAMDAC_HTOTAL:
return nv3->pramdac.htotal;
case NV3_PRAMDAC_HEQU_WIDTH:
return nv3->pramdac.hequ_width;
case NV3_PRAMDAC_HSERR_WIDTH:
return nv3->pramdac.hserr_width;
}
}
}
return 0x0;
}
void nv3_pramdac_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0]));
nv_log("NV3: PRAMDAC Write 0x%08x -> 0x%08x", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
//s hould be pretty easy to understand
// we also update the SVGA state here
switch (reg->address)
{
case NV3_PRAMDAC_COEFF_SELECT:
nv3->pramdac.coeff_select = value;
break;
case NV3_PRAMDAC_GENERAL_CONTROL:
nv3->pramdac.general_control = value;
break;
case NV3_PRAMDAC_VSERR_WIDTH:
//vslines?
nv3->pramdac.vserr_width = value;
break;
case NV3_PRAMDAC_VBBLANK_END:
nv3->pramdac.vbblank_end = value;
break;
case NV3_PRAMDAC_VBLANK_END:
nv3->pramdac.vblank_end = value;
break;
case NV3_PRAMDAC_VBLANK_START:
nv3->nvbase.svga.vblankstart = value;
nv3->pramdac.vblank_start = value;
break;
case NV3_PRAMDAC_VEQU_START:
nv3->pramdac.vequ_start = value;
break;
case NV3_PRAMDAC_VTOTAL:
nv3->pramdac.vtotal = value;
nv3->nvbase.svga.vtotal = value;
break;
case NV3_PRAMDAC_HSYNC_WIDTH:
nv3->pramdac.hsync_width = value;
break;
case NV3_PRAMDAC_HBURST_START:
nv3->pramdac.hburst_start = value;
break;
case NV3_PRAMDAC_HBURST_END:
nv3->pramdac.hburst_end = value;
break;
case NV3_PRAMDAC_HBLANK_START:
nv3->nvbase.svga.hblankstart = value;
nv3->pramdac.hblank_start = value;
break;
case NV3_PRAMDAC_HBLANK_END:
nv3->nvbase.svga.hblank_end_val = value;
nv3->pramdac.hblank_end = value;
break;
case NV3_PRAMDAC_HTOTAL:
nv3->pramdac.htotal = value;
nv3->nvbase.svga.htotal = value;
break;
case NV3_PRAMDAC_HEQU_WIDTH:
nv3->pramdac.hequ_width = value;
break;
case NV3_PRAMDAC_HSERR_WIDTH:
nv3->pramdac.hserr_width = value;
break;
}
}
}
}

149
src/video/nv/nv3/subsystems/nv3_pramin.c Normal file
View File

@@ -0,0 +1,149 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PRAMIN - Basically, this is how we know what to render.
* Has a giant hashtable of all the submitted DMA objects using a pseudo-C++ class system
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// i believe the main loop is to walk the hashtable in RAMIN (last 0.5 MB of VRAM),
// find the objects that were submitted from DMA
// (going from software -> nvidia d3d / ogl implementation -> resource manager client -> nvapi -> nvrm -> GPU PFIFO -> GPU PBUS -> GPU PFB RAMIN -> PGRAPH)
// and then rendering each of those using PGRAPH
// Notes for all of these functions:
// Structures in RAMIN are stored from the bottom of vram up in reverse order
// this can be explained without bitwise math like so:
// real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size)
// reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card)
// Read 8-bit ramin
uint8_t nv3_ramin_read8(uint32_t addr, void* priv)
{
addr &= (VRAM_SIZE_4MB - 1);
uint32_t raw_addr = addr; // saved after and
addr ^= (VRAM_SIZE_4MB - 0x10);
uint8_t val = nv3->nvbase.svga.vram[addr];
nv_log("NV3: Read byte from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr);
return val;
}
// Read 16-bit ramin
uint16_t nv3_ramin_read16(uint32_t addr, void* priv)
{
addr &= (VRAM_SIZE_4MB - 1);
// why does this not work in one line
svga_t* svga = &nv3->nvbase.svga;
uint16_t* vram_16bit = (uint16_t*)svga->vram;
uint32_t raw_addr = addr; // saved after and
addr ^= (VRAM_SIZE_4MB - 0x10);
addr >>= 1; // what
uint16_t val = vram_16bit[addr]; // what
nv_log("NV3: Read word from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr);
return val;
}
// Read 32-bit ramin
uint32_t nv3_ramin_read32(uint32_t addr, void* priv)
{
addr &= (VRAM_SIZE_4MB - 1);
// why does this not work in one line
svga_t* svga = &nv3->nvbase.svga;
uint32_t* vram_32bit = (uint32_t*)svga->vram;
uint32_t raw_addr = addr; // saved after and
addr ^= (VRAM_SIZE_4MB - 0x10);
addr >>= 2; // what
uint32_t val = vram_32bit[addr];
nv_log("NV3: Read dword from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr);
return val;
}
// Write 8-bit ramin
void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv)
{
addr &= (VRAM_SIZE_4MB - 1);
uint32_t raw_addr = addr; // saved after and
// Structures in RAMIN are stored from the bottom of vram up in reverse order
// this can be explained without bitwise math like so:
// real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size)
// reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card)
addr ^= (VRAM_SIZE_4MB - 0x10);
nv3->nvbase.svga.vram[addr] = val;
nv_log("NV3: Write byte to ramin addr=0x%08x val=0x%08x (raw address=0x%08x)", addr, val, raw_addr);
}
// Write 16-bit ramin
void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv)
{
addr &= (VRAM_SIZE_4MB - 1);
// why does this not work in one line
svga_t* svga = &nv3->nvbase.svga;
uint16_t* vram_16bit = (uint16_t*)svga->vram;
uint32_t raw_addr = addr; // saved after and
addr ^= (VRAM_SIZE_4MB - 0x10);
addr >>= 1; // what
vram_16bit[addr] = val;
nv_log("NV3: Write word to ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr);
}
// Write 32-bit ramin
void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv)
{
addr &= (VRAM_SIZE_4MB - 1);
// why does this not work in one line
svga_t* svga = &nv3->nvbase.svga;
uint32_t* vram_32bit = (uint32_t*)svga->vram;
uint32_t raw_addr = addr; // saved after and
addr ^= (VRAM_SIZE_4MB - 0x10);
addr >>= 2; // what
vram_32bit[addr] = val;
nv_log("NV3: Write dword to ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr);
}

31
src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c Normal file
View File

@@ -0,0 +1,31 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PFIFO RAMFC area: Stores context unused DMA channels
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...

31
src/video/nv/nv3/subsystems/nv3_pramin_ramht.c Normal file
View File

@@ -0,0 +1,31 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PFIFO hashtable (Quickly access submitted DMA objects)
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...

31
src/video/nv/nv3/subsystems/nv3_pramin_ramro.c Normal file
View File

@@ -0,0 +1,31 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PFIFO ram runout area (you fucked up)
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// Single unified write function...

120
src/video/nv/nv3/subsystems/nv3_ptimer.c Normal file
View File

@@ -0,0 +1,120 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PTIMER - PIT emulation
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
nv_register_t ptimer_registers[] = {
{ NV3_PTIMER_INTR, "PTIMER - Interrupt Status", NULL, NULL},
{ NV3_PTIMER_INTR_EN, "PTIMER - Interrupt Enable", NULL, NULL,},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
// ptimer init code
void nv3_ptimer_init()
{
nv_log("NV3: Initialising PTIMER...");
nv_log("Done!\n");
}
uint32_t nv3_ptimer_read(uint32_t address)
{
// before doing anything, check the subsystem enablement
nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0]));
// todo: friendly logging
nv_log("NV3: PTIMER Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
// Interrupt state:
// Bit 0: Alarm
switch (reg->address)
{
case NV3_PTIMER_INTR:
return nv3->ptimer.interrupt_status;
case NV3_PTIMER_INTR_EN:
return nv3->ptimer.interrupt_enable;
}
}
}
return 0x00;
}
void nv3_ptimer_write(uint32_t address, uint32_t value)
{
// before doing anything, check the subsystem enablement
nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0]));
nv_log("NV3: PTIMER Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
switch (reg->address)
{
// Interrupt state:
// Bit 0 - Alarm
case NV3_PTIMER_INTR:
nv3->ptimer.interrupt_status &= ~value;
nv3_pmc_clear_interrupts();
break;
case NV3_PTIMER_INTR_EN:
nv3->ptimer.interrupt_enable = value & 0x00000001;
break;
}
}
}
}

121
src/video/nv/nv3/subsystems/nv3_pvideo.c Normal file
View File

@@ -0,0 +1,121 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NV3 PVIDEO - Video Overlay
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <86Box/86box.h>
#include <86Box/device.h>
#include <86Box/mem.h>
#include <86box/pci.h>
#include <86Box/rom.h> // DEPENDENT!!!
#include <86Box/video.h>
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
nv_register_t pvideo_registers[] = {
{ NV3_PVIDEO_INTR, "PVIDEO - Interrupt Status", NULL, NULL},
{ NV3_PVIDEO_INTR_EN, "PVIDEO - Interrupt Enable", NULL, NULL,},
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
// ptimer init code
void nv3_pvideo_init()
{
nv_log("Initialising PVIDEO...");
nv_log("Done!\n");
}
uint32_t nv3_pvideo_read(uint32_t address)
{
// before doing anything, check the subsystem enablement
nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0]));
// todo: friendly logging
nv_log("NV3: PVIDEO Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_read)
return reg->on_read();
else
{
// Interrupt state:
// Bit 0 - Notifier
switch (reg->address)
{
case NV3_PVIDEO_INTR:
return nv3->pvideo.interrupt_status;
case NV3_PVIDEO_INTR_EN:
return nv3->pvideo.interrupt_enable;
}
}
}
return 0x0;
}
void nv3_pvideo_write(uint32_t address, uint32_t value)
{
// before doing anything, check the subsystem enablement
nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0]));
nv_log("NV3: PVIDEO Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
reg->on_write(value);
else
{
switch (reg->address)
{
// Interrupt state:
// Bit 0 - Notifier
case NV3_PVIDEO_INTR:
nv3->pvideo.interrupt_status &= ~value;
nv3_pmc_clear_interrupts();
break;
case NV3_PVIDEO_INTR_EN:
nv3->pvideo.interrupt_enable = value & 0x00000001;
break;
}
}
}
}

47
src/video/nv/nv_base.c Normal file
View File

@@ -0,0 +1,47 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Base file for emulation of NVidia video cards.
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024 starfrost
*/
// Common NV1/3/4... init
#define HAVE_STDARG_H // wtf is this crap
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <86box/86box.h>
#include <86box/nv/vid_nv.h>
// Common logging
#ifdef ENABLE_NV_LOG
int nv_do_log = ENABLE_NV_LOG;
void nv_log(const char *fmt, ...)
{
va_list ap;
if (nv_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
void
nv_log(const char *fmt, ...)
{
}
#endif

3
src/video/vid_table.c
View File

@@ -249,6 +249,9 @@ video_cards[] = {
{ &compaq_voodoo_3_3500_agp_device },
{ &voodoo_3_3500_se_agp_device },
{ &voodoo_3_3500_si_agp_device },
{ &nv3_device_agp },
{ &nv3_device_pci },
{ NULL }
// clang-format on
};