From 7afe30205465fdeada5ecdf5961a177e2e804c14 Mon Sep 17 00:00:00 2001 From: Dimitar Angelov Date: Tue, 2 Apr 2024 11:22:31 +0200 Subject: [PATCH 01/31] Adding Pravetz-16S definition --- src/include/86box/machine.h | 1 + src/machine/m_xt.c | 15 ++++++++++++++ src/machine/machine_table.c | 39 +++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index f97d1a37c..7253a5656 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -918,6 +918,7 @@ extern int machine_xt_v20xt_init(const machine_t *); extern int machine_xt_iskra3104_init(const machine_t *); extern int machine_xt_pravetz16_imko4_init(const machine_t *); +extern int machine_xt_pravetz16s_cpu12_init(const machine_t *); extern int machine_xt_micoms_xl7turbo_init(const machine_t *); /* m_xt_compaq.c */ diff --git a/src/machine/m_xt.c b/src/machine/m_xt.c index 9a0b39a89..7baaa4ef3 100644 --- a/src/machine/m_xt.c +++ b/src/machine/m_xt.c @@ -368,6 +368,21 @@ machine_xt_pravetz16_imko4_init(const machine_t *model) return ret; } +int +machine_xt_pravetz16s_cpu12_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear("roms/machines/pravetz16s/PR16S.BIN", + 0x000fe000, 8192, 0); + + if (bios_only || !ret) + return ret; + + machine_xt_init_ex(model); + return ret; +} + int machine_xt_micoms_xl7turbo_init(const machine_t *model) { diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index c2bb3925b..6238bcbb5 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -1339,6 +1339,45 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + { + .name = "[8088] Pravetz 16S / CPU12", + .internal_name = "pravetz16s", + .type = MACHINE_TYPE_8088, + .chipset = MACHINE_CHIPSET_DISCRETE, + .init = machine_xt_pravetz16s_cpu12_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_8088, + .block = CPU_BLOCK_NONE, + .min_bus = 0, + .max_bus = 0, + .min_voltage = 0, + .max_voltage = 0, + .min_multi = 0, + .max_multi = 0 + }, + .bus_flags = MACHINE_PC, + .flags = MACHINE_FLAGS_NONE, + .ram = { + .min = 64, + .max = 640, + .step = 64 + }, + .nvrmask = 0, + .kbc_device = &keyboard_xt_device, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, { .name = "[8088] Sanyo SX-16", .internal_name = "sansx16", From b9a39d07f865d730d712860ec12e0685c6805348 Mon Sep 17 00:00:00 2001 From: Dimitar Angelov Date: Tue, 2 Apr 2024 15:44:57 +0200 Subject: [PATCH 02/31] Update of min/max bus and min/max RAM --- src/machine/machine_table.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 6238bcbb5..4ac38f607 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -1340,7 +1340,7 @@ const machine_t machines[] = { .net_device = NULL }, { - .name = "[8088] Pravetz 16S / CPU12", + .name = "[8088] Pravetz 16S / CPU12+", .internal_name = "pravetz16s", .type = MACHINE_TYPE_8088, .chipset = MACHINE_CHIPSET_DISCRETE, @@ -1352,8 +1352,8 @@ const machine_t machines[] = { .cpu = { .package = CPU_PKG_8088, .block = CPU_BLOCK_NONE, - .min_bus = 0, - .max_bus = 0, + .min_bus = 4772728, + .max_bus = 12000000, .min_voltage = 0, .max_voltage = 0, .min_multi = 0, @@ -1362,9 +1362,9 @@ const machine_t machines[] = { .bus_flags = MACHINE_PC, .flags = MACHINE_FLAGS_NONE, .ram = { - .min = 64, - .max = 640, - .step = 64 + .min = 512, + .max = 1024, + .step = 128 }, .nvrmask = 0, .kbc_device = &keyboard_xt_device, From 7aa3728c3f49c9f196601f2811c439ac376fe4ce Mon Sep 17 00:00:00 2001 From: Dimitar Angelov Date: Tue, 2 Apr 2024 17:02:26 +0200 Subject: [PATCH 03/31] Corrected for CPU12 Plus --- src/include/86box/machine.h | 2 +- src/machine/m_xt.c | 2 +- src/machine/machine_table.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 7253a5656..6690a46c2 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -918,7 +918,7 @@ extern int machine_xt_v20xt_init(const machine_t *); extern int machine_xt_iskra3104_init(const machine_t *); extern int machine_xt_pravetz16_imko4_init(const machine_t *); -extern int machine_xt_pravetz16s_cpu12_init(const machine_t *); +extern int machine_xt_pravetz16s_cpu12p_init(const machine_t *); extern int machine_xt_micoms_xl7turbo_init(const machine_t *); /* m_xt_compaq.c */ diff --git a/src/machine/m_xt.c b/src/machine/m_xt.c index 7baaa4ef3..3c1539016 100644 --- a/src/machine/m_xt.c +++ b/src/machine/m_xt.c @@ -369,7 +369,7 @@ machine_xt_pravetz16_imko4_init(const machine_t *model) } int -machine_xt_pravetz16s_cpu12_init(const machine_t *model) +machine_xt_pravetz16s_cpu12p_init(const machine_t *model) { int ret; diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 4ac38f607..9f084d723 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -1340,11 +1340,11 @@ const machine_t machines[] = { .net_device = NULL }, { - .name = "[8088] Pravetz 16S / CPU12+", + .name = "[8088] Pravetz 16S / CPU12 Plus", .internal_name = "pravetz16s", .type = MACHINE_TYPE_8088, .chipset = MACHINE_CHIPSET_DISCRETE, - .init = machine_xt_pravetz16s_cpu12_init, + .init = machine_xt_pravetz16s_cpu12p_init, .p1_handler = NULL, .gpio_handler = NULL, .available_flag = MACHINE_AVAILABLE, From 072a6c5a05198f51fd1f69ee34f65e467b9b77f4 Mon Sep 17 00:00:00 2001 From: jbs Date: Tue, 16 Apr 2024 11:50:53 -0300 Subject: [PATCH 04/31] For Qt5 add Gui Private Include Header. Fix C++ union initializer syntax in src/sound/snd_opl_ymfm.cpp --- src/qt/CMakeLists.txt | 6 +++++- src/sound/snd_opl_ymfm.cpp | 8 ++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/qt/CMakeLists.txt b/src/qt/CMakeLists.txt index 422989a44..b5204e724 100644 --- a/src/qt/CMakeLists.txt +++ b/src/qt/CMakeLists.txt @@ -41,8 +41,12 @@ endif() set(CMAKE_FIND_PACKAGE_PREFER_CONFIG OFF) find_package(Threads REQUIRED) -find_package(Qt${QT_MAJOR} COMPONENTS Core Widgets Network OpenGL REQUIRED) +find_package(Qt${QT_MAJOR} COMPONENTS Core Widgets Network OpenGL Gui REQUIRED) find_package(Qt${QT_MAJOR}LinguistTools REQUIRED NO_CMAKE_FIND_ROOT_PATH) +if(NOT USE_QT6) + # For in src/qt/qt_mainwindow.cpp + include_directories(${Qt5Gui_PRIVATE_INCLUDE_DIRS}) +endif () # TODO: Is this the correct way to do this, and is it required on any # other platforms or with Qt 5? diff --git a/src/sound/snd_opl_ymfm.cpp b/src/sound/snd_opl_ymfm.cpp index 55e7f1984..a08aac92b 100644 --- a/src/sound/snd_opl_ymfm.cpp +++ b/src/sound/snd_opl_ymfm.cpp @@ -433,7 +433,7 @@ const device_t ym3812_ymfm_device = { .init = ymfm_drv_init, .close = ymfm_drv_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = NULL @@ -447,7 +447,7 @@ const device_t ymf262_ymfm_device = { .init = ymfm_drv_init, .close = ymfm_drv_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = NULL @@ -461,7 +461,7 @@ const device_t ymf289b_ymfm_device = { .init = ymfm_drv_init, .close = ymfm_drv_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = NULL @@ -475,7 +475,7 @@ const device_t ymf278b_ymfm_device = { .init = ymfm_drv_init, .close = ymfm_drv_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = NULL From b4907799908f6f7e35eb9fa9a5508f87ee52f000 Mon Sep 17 00:00:00 2001 From: Jos van Mourik Date: Sun, 21 Jul 2024 01:03:55 +0200 Subject: [PATCH 05/31] Add Mode Hexadecimal to allow Photo Play games to work with touch --- src/device/mouse_microtouch_touchscreen.c | 144 +++++++++++++--------- 1 file changed, 89 insertions(+), 55 deletions(-) diff --git a/src/device/mouse_microtouch_touchscreen.c b/src/device/mouse_microtouch_touchscreen.c index af5ef5bf0..e1a965513 100644 --- a/src/device/mouse_microtouch_touchscreen.c +++ b/src/device/mouse_microtouch_touchscreen.c @@ -39,7 +39,8 @@ enum mtouch_modes { MODE_TABLET = 1, - MODE_RAW = 2 + MODE_RAW = 2, + MODE_HEX = 3 }; typedef struct mouse_microtouch_t { @@ -50,7 +51,7 @@ typedef struct mouse_microtouch_t { char cmd[512]; int cmd_pos; int mode; - uint8_t cal_cntr, pen_mode; + uint8_t cal_cntr, pen_mode, prev_b; bool soh; bool in_reset; serial_t *serial; @@ -93,80 +94,85 @@ microtouch_process_commands(mouse_microtouch_t *mtouch) for (i = 0; i < strlen(mtouch->cmd); i++) { mtouch->cmd[i] = toupper(mtouch->cmd[i]); } - if (mtouch->cmd[0] == 'Z') { + if (mtouch->cmd[0] == 'Z') { // Null fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'O') { + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'O') { // Finger Only mtouch->pen_mode = 1; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'U' && mtouch->cmd[1] == 'T') { + if (mtouch->cmd[0] == 'U' && mtouch->cmd[1] == 'T') { // Unit Type fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "TP****00\r", sizeof("TP****00\r") - 1); } - if (mtouch->cmd[0] == 'O' && mtouch->cmd[1] == 'I') { + if (mtouch->cmd[0] == 'O' && mtouch->cmd[1] == 'I') { // Output Identity fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "P50200\r", sizeof("P50200\r") - 1); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'T') { + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'T') { // Format Tablet mtouch->mode = MODE_TABLET; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'R') { + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'H') { // Format Hexadecimal + mtouch->mode = MODE_HEX; + fifo8_push(&mtouch->resp, 1); + fifo8_push_all(&mtouch->resp, (uint8_t *)"0\r", 2); + } + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'R') { // Format Raw mtouch->mode = MODE_RAW; mtouch->cal_cntr = 0; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'M' && mtouch->cmd[1] == 'S') { + if (mtouch->cmd[0] == 'M' && mtouch->cmd[1] == 'S') { // Mode Stream fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'R') { + if (mtouch->cmd[0] == 'R') { // Reset mtouch->in_reset = true; mtouch->mode = MODE_TABLET; mtouch->cal_cntr = 0; mtouch->pen_mode = 3; timer_on_auto(&mtouch->reset_timer, 500. * 1000.); } - if (mtouch->cmd[0] == 'A' && (mtouch->cmd[1] == 'D' || mtouch->cmd[1] == 'E')) { + if (mtouch->cmd[0] == 'A' && (mtouch->cmd[1] == 'D' || mtouch->cmd[1] == 'E')) { // Autobaud Enable/Disable fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'N' && mtouch->cmd[1] == 'M') { + if (mtouch->cmd[0] == 'N' && mtouch->cmd[1] == 'M') { // ?? fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "1\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'Q') { + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'Q') { // ?? fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "1\r", 2); } - if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'F') { + if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'F') { // ?? fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "1\r", 2); } if (mtouch->cmd[0] == 'P') { - if (mtouch->cmd[1] == 'F') mtouch->pen_mode = 3; - else if (mtouch->cmd[1] == 'O') mtouch->pen_mode = 2; + if (mtouch->cmd[1] == 'F') mtouch->pen_mode = 3; // Pen or Finger + else if (mtouch->cmd[1] == 'O') mtouch->pen_mode = 2; // Pen Only fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'C' && (mtouch->cmd[1] == 'N' || mtouch->cmd[1] == 'X')) { + if (mtouch->cmd[0] == 'C' && (mtouch->cmd[1] == 'N' || mtouch->cmd[1] == 'X')) { // Calibrate New/Extended fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); mtouch->cal_cntr = 2; } - if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'P' && mtouch->cmd[2] == '1') { + if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'P' && mtouch->cmd[2] == '1') { // Get Parameter Block 1 fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "A\r", 2); fifo8_push_all(&mtouch->resp, (uint8_t *) "0000000000000000000000000\r", sizeof("0000000000000000000000000\r") - 1); fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'S' && mtouch->cmd[1] == 'P' && mtouch->cmd[2] == '1') { + if (mtouch->cmd[0] == 'S' && mtouch->cmd[1] == 'P' && mtouch->cmd[2] == '1') { // Set Parameter Block 1 fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "A\r", 2); } @@ -219,46 +225,52 @@ static int mtouch_poll(void *priv) { mouse_microtouch_t *dev = (mouse_microtouch_t *) priv; + + if (fifo8_num_free(&dev->resp) <= 10 || dev->mode == MODE_RAW) { + return 0; + } + + unsigned int abs_x_int = 0, abs_y_int = 0; + double abs_x; + double abs_y; + int b = mouse_get_buttons_ex(); - if (dev->mode != MODE_RAW && fifo8_num_free(&dev->resp) >= 10) { - unsigned int abs_x_int = 0, abs_y_int = 0; - double abs_x; - double abs_y; - int b = mouse_get_buttons_ex(); - mouse_get_abs_coords(&abs_x, &abs_y); - dev->b |= !!(b & 3); - + mouse_get_abs_coords(&abs_x, &abs_y); + dev->b |= !!(b & 3); // any button pressed + + if (abs_x >= 1.0) + abs_x = 1.0; + if (abs_y >= 1.0) + abs_y = 1.0; + if (abs_x <= 0.0) + abs_x = 0.0; + if (abs_y <= 0.0) + abs_y = 0.0; + if (enable_overscan) { + int index = mouse_tablet_in_proximity - 1; + if (mouse_tablet_in_proximity == -1) + mouse_tablet_in_proximity = 0; + + abs_x *= monitors[index].mon_unscaled_size_x - 1; + abs_y *= monitors[index].mon_efscrnsz_y - 1; + + if (abs_x <= (monitors[index].mon_overscan_x / 2.)) { + abs_x = (monitors[index].mon_overscan_x / 2.); + } + if (abs_y <= (monitors[index].mon_overscan_y / 2.)) { + abs_y = (monitors[index].mon_overscan_y / 2.); + } + abs_x -= (monitors[index].mon_overscan_x / 2.); + abs_y -= (monitors[index].mon_overscan_y / 2.); + abs_x = abs_x / (double) monitors[index].mon_xsize; + abs_y = abs_y / (double) monitors[index].mon_ysize; if (abs_x >= 1.0) abs_x = 1.0; if (abs_y >= 1.0) abs_y = 1.0; - if (abs_x <= 0.0) - abs_x = 0.0; - if (abs_y <= 0.0) - abs_y = 0.0; - if (enable_overscan) { - int index = mouse_tablet_in_proximity - 1; - if (mouse_tablet_in_proximity == -1) - mouse_tablet_in_proximity = 0; + } - abs_x *= monitors[index].mon_unscaled_size_x - 1; - abs_y *= monitors[index].mon_efscrnsz_y - 1; - - if (abs_x <= (monitors[index].mon_overscan_x / 2.)) { - abs_x = (monitors[index].mon_overscan_x / 2.); - } - if (abs_y <= (monitors[index].mon_overscan_y / 2.)) { - abs_y = (monitors[index].mon_overscan_y / 2.); - } - abs_x -= (monitors[index].mon_overscan_x / 2.); - abs_y -= (monitors[index].mon_overscan_y / 2.); - abs_x = abs_x / (double) monitors[index].mon_xsize; - abs_y = abs_y / (double) monitors[index].mon_ysize; - if (abs_x >= 1.0) - abs_x = 1.0; - if (abs_y >= 1.0) - abs_y = 1.0; - } + if (dev->mode == MODE_TABLET) { if (dev->cal_cntr && (!(dev->b & 1) && !!(b & 3))) { dev->b |= 1; } else if (dev->cal_cntr && ((dev->b & 1) && !(b & 3))) { @@ -268,7 +280,7 @@ mtouch_poll(void *priv) if (dev->cal_cntr) { return 0; } - if (!!(b & 3)) { + if (!!(b & 3)) { // Hover dev->abs_x = abs_x; dev->abs_y = abs_y; dev->b |= 1; @@ -281,7 +293,7 @@ mtouch_poll(void *priv) fifo8_push(&dev->resp, (abs_x_int >> 7) & 0b1111111); fifo8_push(&dev->resp, abs_y_int & 0b1111111); fifo8_push(&dev->resp, (abs_y_int >> 7) & 0b1111111); - } else if ((dev->b & 1) && !(b & 3)) { + } else if ((dev->b & 1) && !(b & 3)) { // Touch dev->b &= ~1; abs_x_int = dev->abs_x * 16383; abs_y_int = 16383 - dev->abs_y * 16383; @@ -297,6 +309,28 @@ mtouch_poll(void *priv) fifo8_push(&dev->resp, (abs_y_int >> 7) & 0b1111111); } } + + else if (dev->mode == MODE_HEX) { + abs_x_int = abs_x * 1023; + abs_y_int = 1023 - (abs_y * 1023); + char buffer[20]; + + if (dev->cal_cntr && !b && dev->prev_b) { + microtouch_calibrate_timer(dev); + } + else if (b & 1) { + if (dev->prev_b == 0) { // Touchdown + snprintf(buffer, sizeof(buffer), "\x19%03X,%03X\r", abs_x_int, abs_y_int); + } else { // Touch Continuation + snprintf(buffer, sizeof(buffer), "\x1c%03X,%03X\r", abs_x_int, abs_y_int); + } + fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer)); + } else if (dev->prev_b == 1) { // Liftoff + snprintf(buffer, sizeof(buffer), "\x18%03X,%03X\r", abs_x_int, abs_y_int); + fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer)); + } + dev->prev_b = b & 1; + } return 0; } From 189be035d2e1093a80eaec826d62dd996e315901 Mon Sep 17 00:00:00 2001 From: rilysh Date: Sun, 21 Jul 2024 12:49:06 +0530 Subject: [PATCH 06/31] Mark plat_vidapi() argument as const and remove the NULL * plat_vidapi() accepts char pointer, which never gets modifed later on. Mark it as const. * In src/config.c, va_name is initialized as NULL, however, plat_vidapi_name() never returns a NULL pointer, nor it was initialized under a condition branch. Removing NULL, might save one instruction, which requires zeroing the register before setting its initial value. --- src/config.c | 2 +- src/include/86box/plat.h | 2 +- src/qt/qt.c | 2 +- src/unix/unix_sdl.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/config.c b/src/config.c index 23b78f117..2c0781028 100644 --- a/src/config.c +++ b/src/config.c @@ -1720,7 +1720,7 @@ save_general(void) char temp[512]; char buffer[512] = { 0 }; - const char *va_name = NULL; + const char *va_name; ini_section_set_int(cat, "vid_resize", vid_resize); if (vid_resize == 0) diff --git a/src/include/86box/plat.h b/src/include/86box/plat.h index 26f5d5cc8..4a310ab44 100644 --- a/src/include/86box/plat.h +++ b/src/include/86box/plat.h @@ -153,7 +153,7 @@ extern uint32_t plat_get_ticks(void); extern void plat_delay_ms(uint32_t count); extern void plat_pause(int p); extern void plat_mouse_capture(int on); -extern int plat_vidapi(char *name); +extern int plat_vidapi(const char *name); extern char *plat_vidapi_name(int api); extern void plat_resize(int x, int y, int monitor_index); extern void plat_resize_request(int x, int y, int monitor_index); diff --git a/src/qt/qt.c b/src/qt/qt.c index 47f5b9410..a9a6460eb 100644 --- a/src/qt/qt.c +++ b/src/qt/qt.c @@ -38,7 +38,7 @@ qt_nvr_save(void) char icon_set[256] = ""; /* name of the iconset to be used */ int -plat_vidapi(char *api) +plat_vidapi(const char *api) { if (!strcasecmp(api, "default") || !strcasecmp(api, "system")) { return 0; diff --git a/src/unix/unix_sdl.c b/src/unix/unix_sdl.c index c7cc898be..002e33fd6 100644 --- a/src/unix/unix_sdl.c +++ b/src/unix/unix_sdl.c @@ -392,7 +392,7 @@ sdl_reload(void) } int -plat_vidapi(char *api) +plat_vidapi(UNUSED(const char *api)) { return 0; } From 422ebb322b9a1c59fb91e0a759ccb2b0e473e3c5 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sun, 21 Jul 2024 15:13:16 +0200 Subject: [PATCH 07/31] Migrate device configuration regardless of what instance it is. --- src/device.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/device.c b/src/device.c index cf0764946..41f4b74d5 100644 --- a/src/device.c +++ b/src/device.c @@ -97,14 +97,12 @@ device_set_context(device_context_t *c, const device_t *dev, int inst) if (inst) { sprintf(c->name, "%s #%i", dev->name, inst); - /* If this is the first instance and a numbered section is not present, but a non-numbered - section of the same name is, rename the non-numbered section to numbered. */ - if (inst == 1) { - const void *sec = config_find_section(c->name); - void * single_sec = config_find_section((char *) dev->name); - if ((sec == NULL) && (single_sec != NULL)) - config_rename_section(single_sec, c->name); - } + /* If a numbered section is not present, but a non-numbered of the same name + is, rename the non-numbered section to numbered. */ + const void *sec = config_find_section(c->name); + void * single_sec = config_find_section((char *) dev->name); + if ((sec == NULL) && (single_sec != NULL)) + config_rename_section(single_sec, c->name); } else sprintf(c->name, "%s", dev->name); } From d89d9c65f78dd19dfe1b5aa2b51c05bcccf9edc3 Mon Sep 17 00:00:00 2001 From: Jos van Mourik Date: Sun, 21 Jul 2024 17:52:42 +0200 Subject: [PATCH 08/31] Minor cleanup --- src/device/mouse_microtouch_touchscreen.c | 66 +++++++++++------------ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/src/device/mouse_microtouch_touchscreen.c b/src/device/mouse_microtouch_touchscreen.c index e1a965513..72ac9c53a 100644 --- a/src/device/mouse_microtouch_touchscreen.c +++ b/src/device/mouse_microtouch_touchscreen.c @@ -40,7 +40,7 @@ enum mtouch_modes { MODE_TABLET = 1, MODE_RAW = 2, - MODE_HEX = 3 + MODE_HEX = 3 }; typedef struct mouse_microtouch_t { @@ -94,69 +94,69 @@ microtouch_process_commands(mouse_microtouch_t *mtouch) for (i = 0; i < strlen(mtouch->cmd); i++) { mtouch->cmd[i] = toupper(mtouch->cmd[i]); } - if (mtouch->cmd[0] == 'Z') { // Null + if (mtouch->cmd[0] == 'Z') { /* Null */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'O') { // Finger Only + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'O') { /* Finger Only */ mtouch->pen_mode = 1; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'U' && mtouch->cmd[1] == 'T') { // Unit Type + if (mtouch->cmd[0] == 'U' && mtouch->cmd[1] == 'T') { /* Unit Type */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "TP****00\r", sizeof("TP****00\r") - 1); } - if (mtouch->cmd[0] == 'O' && mtouch->cmd[1] == 'I') { // Output Identity + if (mtouch->cmd[0] == 'O' && mtouch->cmd[1] == 'I') { /* Output Identity */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "P50200\r", sizeof("P50200\r") - 1); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'T') { // Format Tablet + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'T') { /* Format Tablet */ mtouch->mode = MODE_TABLET; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'H') { // Format Hexadecimal - mtouch->mode = MODE_HEX; + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'H') { /* Format Hexadecimal */ + mtouch->mode = MODE_HEX; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *)"0\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'R') { // Format Raw + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'R') { /* Format Raw */ mtouch->mode = MODE_RAW; mtouch->cal_cntr = 0; fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'M' && mtouch->cmd[1] == 'S') { // Mode Stream + if (mtouch->cmd[0] == 'M' && mtouch->cmd[1] == 'S') { /* Mode Stream */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'R') { // Reset + if (mtouch->cmd[0] == 'R') { /* Reset */ mtouch->in_reset = true; mtouch->mode = MODE_TABLET; mtouch->cal_cntr = 0; mtouch->pen_mode = 3; timer_on_auto(&mtouch->reset_timer, 500. * 1000.); } - if (mtouch->cmd[0] == 'A' && (mtouch->cmd[1] == 'D' || mtouch->cmd[1] == 'E')) { // Autobaud Enable/Disable + if (mtouch->cmd[0] == 'A' && (mtouch->cmd[1] == 'D' || mtouch->cmd[1] == 'E')) { /* Autobaud Enable/Disable */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } - if (mtouch->cmd[0] == 'N' && mtouch->cmd[1] == 'M') { // ?? + if (mtouch->cmd[0] == 'N' && mtouch->cmd[1] == 'M') { /* ?? */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "1\r", 2); } - if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'Q') { // ?? + if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'Q') { /* ?? */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "1\r", 2); } - if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'F') { // ?? + if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'F') { /* ?? */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "1\r", 2); } if (mtouch->cmd[0] == 'P') { - if (mtouch->cmd[1] == 'F') mtouch->pen_mode = 3; // Pen or Finger - else if (mtouch->cmd[1] == 'O') mtouch->pen_mode = 2; // Pen Only + if (mtouch->cmd[1] == 'F') mtouch->pen_mode = 3; /* Pen or Finger */ + else if (mtouch->cmd[1] == 'O') mtouch->pen_mode = 2; /* Pen Only */ fifo8_push(&mtouch->resp, 1); fifo8_push_all(&mtouch->resp, (uint8_t *) "0\r", 2); } @@ -225,18 +225,18 @@ static int mtouch_poll(void *priv) { mouse_microtouch_t *dev = (mouse_microtouch_t *) priv; - - if (fifo8_num_free(&dev->resp) <= 10 || dev->mode == MODE_RAW) { - return 0; - } - - unsigned int abs_x_int = 0, abs_y_int = 0; + + if (fifo8_num_free(&dev->resp) <= 10 || dev->mode == MODE_RAW) { + return 0; + } + + unsigned int abs_x_int = 0, abs_y_int = 0; double abs_x; double abs_y; int b = mouse_get_buttons_ex(); mouse_get_abs_coords(&abs_x, &abs_y); - dev->b |= !!(b & 3); // any button pressed + dev->b |= !!(b & 3); /* any button pressed */ if (abs_x >= 1.0) abs_x = 1.0; @@ -280,7 +280,7 @@ mtouch_poll(void *priv) if (dev->cal_cntr) { return 0; } - if (!!(b & 3)) { // Hover + if (!!(b & 3)) { /* Hover */ dev->abs_x = abs_x; dev->abs_y = abs_y; dev->b |= 1; @@ -293,7 +293,7 @@ mtouch_poll(void *priv) fifo8_push(&dev->resp, (abs_x_int >> 7) & 0b1111111); fifo8_push(&dev->resp, abs_y_int & 0b1111111); fifo8_push(&dev->resp, (abs_y_int >> 7) & 0b1111111); - } else if ((dev->b & 1) && !(b & 3)) { // Touch + } else if ((dev->b & 1) && !(b & 3)) { /* Touch */ dev->b &= ~1; abs_x_int = dev->abs_x * 16383; abs_y_int = 16383 - dev->abs_y * 16383; @@ -309,27 +309,27 @@ mtouch_poll(void *priv) fifo8_push(&dev->resp, (abs_y_int >> 7) & 0b1111111); } } - + else if (dev->mode == MODE_HEX) { abs_x_int = abs_x * 1023; abs_y_int = 1023 - (abs_y * 1023); char buffer[20]; - if (dev->cal_cntr && !b && dev->prev_b) { + if (dev->cal_cntr && !b && dev->prev_b) { microtouch_calibrate_timer(dev); - } + } else if (b & 1) { - if (dev->prev_b == 0) { // Touchdown + if (dev->prev_b == 0) { /* Touchdown */ snprintf(buffer, sizeof(buffer), "\x19%03X,%03X\r", abs_x_int, abs_y_int); - } else { // Touch Continuation + } else { /* Touch Continuation */ snprintf(buffer, sizeof(buffer), "\x1c%03X,%03X\r", abs_x_int, abs_y_int); } fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer)); - } else if (dev->prev_b == 1) { // Liftoff + } else if (dev->prev_b == 1) { /* Liftoff */ snprintf(buffer, sizeof(buffer), "\x18%03X,%03X\r", abs_x_int, abs_y_int); fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer)); } - dev->prev_b = b & 1; + dev->prev_b = b & 1; } return 0; } From ad710b710ddf8476eb414cacd6a76c59b98102ba Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 00:01:04 +0200 Subject: [PATCH 09/31] Gave the Acer T100 the missing ALi M5105 Super I/O chip, fixes #4540. --- src/machine/m_at_286_386sx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/machine/m_at_286_386sx.c b/src/machine/m_at_286_386sx.c index 9e9186040..e81eae1f1 100644 --- a/src/machine/m_at_286_386sx.c +++ b/src/machine/m_at_286_386sx.c @@ -725,6 +725,7 @@ machine_at_acer100t_init(const machine_t *model) if (gfxcard[0] == VID_INTERNAL) device_add(&oti077_acer100t_device); + device_add(&ali5105_device); return ret; } From f06fae90c8c8a038708df819cff58d9b12dbd8b3 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 18:03:03 -0400 Subject: [PATCH 10/31] Fix pravetz16s compile --- src/machine/m_xt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/machine/m_xt.c b/src/machine/m_xt.c index f1c325582..c340d5a9b 100644 --- a/src/machine/m_xt.c +++ b/src/machine/m_xt.c @@ -375,7 +375,8 @@ machine_xt_pravetz16s_cpu12p_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_xt_init_ex(model); + machine_xt_common_init(model, 0); + return ret; } From fc714e727029645da3d7ecc50d6ec2bdaed533e6 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 00:07:39 +0200 Subject: [PATCH 11/31] Backported the VLSI 82c113 Super I/O chip from my branch because of two machines we already had that require it. --- src/include/86box/sio.h | 1 + src/machine/m_at_286_386sx.c | 7 +- src/machine/m_at_386dx_486.c | 2 +- src/sio/CMakeLists.txt | 2 +- src/sio/sio_vl82c113.c | 163 +++++++++++++++++++++++++++++++++++ 5 files changed, 172 insertions(+), 3 deletions(-) create mode 100644 src/sio/sio_vl82c113.c diff --git a/src/include/86box/sio.h b/src/include/86box/sio.h index 6b7d46987..7f40203b4 100644 --- a/src/include/86box/sio.h +++ b/src/include/86box/sio.h @@ -88,6 +88,7 @@ extern const device_t um8669f_device; extern const device_t um8669f_ide_device; extern const device_t um8669f_ide_sec_device; extern const device_t via_vt82c686_sio_device; +extern const device_t vl82c113_device; extern const device_t w83787f_88h_device; extern const device_t w83787f_device; extern const device_t w83787f_ide_device; diff --git a/src/machine/m_at_286_386sx.c b/src/machine/m_at_286_386sx.c index e81eae1f1..4632e00df 100644 --- a/src/machine/m_at_286_386sx.c +++ b/src/machine/m_at_286_386sx.c @@ -644,7 +644,12 @@ machine_at_cmdsl386sx25_init(const machine_t *model) if (gfxcard[0] == VID_INTERNAL) device_add(&gd5402_onboard_device); - machine_at_scamp_common_init(model, 1); + machine_at_common_ide_init(model); + + device_add(&ali5105_device); /* The FDC is part of the ALi M5105. */ + device_add(&vl82c113_device); /* The keyboard controller is part of the VL82c113. */ + + device_add(&vlsi_scamp_device); return ret; } diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 966639476..82f946314 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -375,7 +375,7 @@ machine_at_vect486vl_init(const machine_t *model) // has HDC problems if (gfxcard[0] == VID_INTERNAL) device_add(&gd5428_onboard_device); - device_add(&keyboard_ps2_ami_device); + device_add(&vl82c113_device); device_add(&fdc37c651_ide_device); return ret; diff --git a/src/sio/CMakeLists.txt b/src/sio/CMakeLists.txt index dff0fcd0f..ecb780a9b 100644 --- a/src/sio/CMakeLists.txt +++ b/src/sio/CMakeLists.txt @@ -20,7 +20,7 @@ add_library(sio OBJECT sio_acc3221.c sio_ali5123.c sio_f82c710.c sio_82091aa.c sio_prime3b.c sio_prime3c.c sio_w83787f.c sio_w83877f.c sio_w83977f.c sio_um8663f.c sio_um8669f.c - sio_vt82c686.c) + sio_vl82c113.c sio_vt82c686.c) if(SIO_DETECT) target_sources(sio PRIVATE sio_detect.c) diff --git a/src/sio/sio_vl82c113.c b/src/sio/sio_vl82c113.c new file mode 100644 index 000000000..6a02ef359 --- /dev/null +++ b/src/sio/sio_vl82c113.c @@ -0,0 +1,163 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the VLSI VL82c113 Combination I/O Chip. + * + * Authors: Miran Grca, + * + * Copyright 2024 Miran Grca. + */ +#include +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/io.h> +#include <86box/timer.h> +#include <86box/device.h> +#include <86box/keyboard.h> +#include <86box/nvr.h> +#include <86box/sio.h> + +typedef struct vl82c113_t { + uint8_t index; + uint8_t nvr_enabled; + uint8_t regs[3]; + uint8_t pad; + uint16_t nvr_base; + int cur_reg; + nvr_t *nvr; + void *kbc; +} vl82c113_t; + +static void +vl82c113_nvr_handler(vl82c113_t *dev) +{ + const uint8_t nvr_enabled = (dev->regs[0x00]) & 0x01; + const uint16_t nvr_base = ((dev->regs[0x01] << 8) | dev->regs[0x00]) & 0xfffe; + + if ((nvr_enabled != dev->nvr_enabled) || (nvr_base != dev->nvr_base)) { + if (dev->nvr_enabled && (dev->nvr_base != 0x0000)) + nvr_at_handler(0, dev->nvr_base, dev->nvr); + + dev->nvr_enabled = nvr_enabled; + dev->nvr_base = nvr_base; + + if (dev->nvr_enabled && (dev->nvr_base != 0x0000)) + nvr_at_handler(1, dev->nvr_base, dev->nvr); + } +} + +static void +vl82c113_out(uint16_t port, uint8_t val, void *priv) +{ + vl82c113_t *dev = (vl82c113_t *) priv; + + if (port == 0xec) + dev->index = val; + else if ((dev->index >= 0x1b) && (dev->index <= 0x1d)) { + const uint8_t index = dev->index - 0x1b; + const uint8_t valxor = dev->regs[index] ^ val; + + dev->regs[index] = val; + + switch (index) { + default: + break; + + case 0x00: + case 0x01: + if (valxor) + vl82c113_nvr_handler(dev); + break; + + case 0x02: + if (valxor & 0x02) + kbc_at_set_ps2(dev->kbc, !(val & 0x02)); + break; + } + } +} + +static uint8_t +vl82c113_in(uint16_t port, void *priv) +{ + const vl82c113_t *dev = (vl82c113_t *) priv; + uint8_t ret = 0xff; + + if (port == 0xed) { + if ((dev->index >= 0x1b) && (dev->index <= 0x1d)) + ret = dev->regs[dev->index - 0x1b]; + else if (dev->index == 0x1f) + /* REVID */ + ret = 0xc0; + } + + return ret; +} + +static void +vl82c113_reset(void *priv) +{ + vl82c113_t *dev = (vl82c113_t *) priv; + + memset(dev->regs, 0x00, sizeof(dev->regs)); + + dev->regs[0x00] = 0x71; + dev->regs[0x01] = 0x00; + + dev->regs[0x02] = 0xc3; + + kbc_at_set_ps2(dev->kbc, 0); + + vl82c113_nvr_handler(dev); +} + +static void +vl82c113_close(void *priv) +{ + vl82c113_t *dev = (vl82c113_t *) priv; + + free(dev); +} + +static void * +vl82c113_init(const device_t *info) +{ + vl82c113_t *dev = (vl82c113_t *) calloc(1, sizeof(vl82c113_t)); + + dev->nvr = device_add(&at_nvr_device); + + dev->nvr_enabled = 1; + dev->nvr_base = 0x0070; + + /* Commands are standard. */ + dev->kbc = device_add(&keyboard_at_device); + + vl82c113_reset(dev); + + io_sethandler(0x00ec, 0x0002, vl82c113_in, NULL, NULL, vl82c113_out, NULL, NULL, dev); + + return dev; +} + +const device_t vl82c113_device = { + .name = "VLSI VL82c113 Combination I/O", + .internal_name = "vl82c113", + .flags = 0, + .local = 0, + .init = vl82c113_init, + .close = vl82c113_close, + .reset = vl82c113_reset, + { .available = NULL }, + .speed_changed = NULL, + .force_redraw = NULL, + .config = NULL +}; + From 9ed1e75586ba9814baa4df610027d8f26c5ef22d Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 18:11:38 -0400 Subject: [PATCH 12/31] add missing kbc to pravetz16s --- src/machine/m_xt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/machine/m_xt.c b/src/machine/m_xt.c index c340d5a9b..c11968d33 100644 --- a/src/machine/m_xt.c +++ b/src/machine/m_xt.c @@ -375,6 +375,8 @@ machine_xt_pravetz16s_cpu12p_init(const machine_t *model) if (bios_only || !ret) return ret; + device_add(&keyboard_xt_device); + machine_xt_common_init(model, 0); return ret; From fd00bcca8b95e4523bb0b3f460340fc5bf470ba2 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 00:12:12 +0200 Subject: [PATCH 13/31] Backported the kbc_at_set_ps2() function required by the VL82c113. --- src/device/kbc_at.c | 14 ++++++++++++++ src/include/86box/keyboard.h | 1 + 2 files changed, 15 insertions(+) diff --git a/src/device/kbc_at.c b/src/device/kbc_at.c index 8c94685b7..9ba84888c 100644 --- a/src/device/kbc_at.c +++ b/src/device/kbc_at.c @@ -1189,6 +1189,20 @@ write60_ami(void *priv, uint8_t val) return 1; } +void +kbc_at_set_ps2(void *priv, const uint8_t ps2) +{ + atkbc_t *dev = (atkbc_t *) priv; + + dev->ami_flags = (dev->ami_flags & 0xfe) | (!!ps2); + dev->misc_flags &= ~FLAG_PS2; + if (ps2) { + dev->misc_flags |= FLAG_PS2; + kbc_at_do_poll = kbc_at_poll_ps2; + } else + kbc_at_do_poll = kbc_at_poll_at; +} + static uint8_t write64_ami(void *priv, uint8_t val) { diff --git a/src/include/86box/keyboard.h b/src/include/86box/keyboard.h index 846123627..bf9a76d73 100644 --- a/src/include/86box/keyboard.h +++ b/src/include/86box/keyboard.h @@ -278,6 +278,7 @@ extern int keyboard_isfsexit(void); extern int keyboard_isfsexit_up(void); extern int keyboard_ismsexit(void); extern void keyboard_set_is_amstrad(int ams); +extern void kbc_at_set_ps2(void *priv, uint8_t ps2); extern void kbc_at_set_fast_reset(uint8_t new_fast_reset); extern void kbc_at_handler(int set, void *priv); From ecc7f965a813d6cabfde012000b679df6caa086c Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sat, 20 Jul 2024 22:38:13 -0400 Subject: [PATCH 14/31] Named initializers for IBM & Cyrix CPU's --- src/cpu/cpu_table.c | 376 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 348 insertions(+), 28 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index b9e81aa72..1e756c183 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -1507,10 +1507,58 @@ const cpu_family_t cpu_families[] = { .name = "386SLC", .internal_name = "ibm386slc", .cpus = (const CPU[]) { - {"16", CPU_IBM386SLC, fpus_80386, 16000000, 1, 5000, 0xA301, 0, 0, 0, 3,3,3,3, 2}, - {"20", CPU_IBM386SLC, fpus_80386, 20000000, 1, 5000, 0xA301, 0, 0, 0, 4,4,3,3, 3}, - {"25", CPU_IBM386SLC, fpus_80386, 25000000, 1, 5000, 0xA301, 0, 0, 0, 4,4,3,3, 3}, - {"", 0} + { + .name = "16", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_386SX, @@ -1518,10 +1566,58 @@ const cpu_family_t cpu_families[] = { .name = "Cx486SLC", .internal_name = "cx486slc", .cpus = (const CPU[]) { - {"20", CPU_486SLC, fpus_80386, 20000000, 1, 5000, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, - {"25", CPU_486SLC, fpus_80386, 25000000, 1, 5000, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, - {"33", CPU_486SLC, fpus_80386, 33333333, 1, 5000, 0x400, 0, 0x0000, 0, 6,6,3,3, 4}, - {"", 0} + { + .name = "20", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_386SX, @@ -1529,10 +1625,58 @@ const cpu_family_t cpu_families[] = { .name = "Cx486SRx2", .internal_name = "cx486srx2", .cpus = (const CPU[]) { - {"32", CPU_486SLC, fpus_80386, 32000000, 2, 5000, 0x406, 0, 0x0006, 0, 6,6,6,6, 4}, - {"40", CPU_486SLC, fpus_80386, 40000000, 2, 5000, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, - {"50", CPU_486SLC, fpus_80386, 50000000, 2, 5000, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, - {"", 0} + { + .name = "32", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 32000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "50", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_486SLC_IBM, @@ -1540,8 +1684,24 @@ const cpu_family_t cpu_families[] = { .name = "486SLC", .internal_name = "ibm486slc", .cpus = (const CPU[]) { - {"33", CPU_IBM486SLC, fpus_80386, 33333333, 1, 5000, 0xA401, 0, 0, 0, 6,6,3,3, 4}, - {"", 0} + { + .name = "33", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA401, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_486SLC_IBM, @@ -1549,10 +1709,58 @@ const cpu_family_t cpu_families[] = { .name = "486SLC2", .internal_name = "ibm486slc2", .cpus = (const CPU[]) { - {"40", CPU_IBM486SLC, fpus_80386, 40000000, 2, 5000, 0xA421, 0, 0, 0, 7,7,6,6, 5}, - {"50", CPU_IBM486SLC, fpus_80386, 50000000, 2, 5000, 0xA421, 0, 0, 0, 8,8,6,6, 6}, - {"66", CPU_IBM486SLC, fpus_80386, 66666666, 2, 5000, 0xA421, 0, 0, 0, 12,12,6,6, 8}, - {"", 0} + { + .name = "40", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 5 + }, + { + .name = "50", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_486SLC_IBM, @@ -1560,10 +1768,58 @@ const cpu_family_t cpu_families[] = { .name = "486SLC3", .internal_name = "ibm486slc3", .cpus = (const CPU[]) { - {"60", CPU_IBM486SLC, fpus_80386, 60000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 7}, - {"75", CPU_IBM486SLC, fpus_80386, 75000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 9}, - {"100", CPU_IBM486SLC, fpus_80386, 100000000, 3, 5000, 0xA439, 0, 0, 0, 18,18,9,9, 12}, - {"", 0} + { + .name = "60", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 60000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 7 + }, + { + .name = "75", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 75000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 100000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_486BL, @@ -1571,9 +1827,41 @@ const cpu_family_t cpu_families[] = { .name = "486BL2", .internal_name = "ibm486bl2", .cpus = (const CPU[]) { - {"50", CPU_IBM486BL, fpus_80386, 50000000, 2, 5000, 0xA439, 0, 0, 0, 8,8,6,6, 6}, - {"66", CPU_IBM486BL, fpus_80386, 66666666, 2, 5000, 0xA439, 0, 0, 0, 12,12,6,6, 8}, - {"", 0} + { + .name = "50", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_486BL, @@ -1581,9 +1869,41 @@ const cpu_family_t cpu_families[] = { .name = "486BL3", .internal_name = "ibm486bl3", .cpus = (const CPU[]) { - {"75", CPU_IBM486BL, fpus_80386, 75000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 9}, - {"100", CPU_IBM486BL, fpus_80386, 100000000, 3, 5000, 0xA439, 0, 0, 0, 18,18,9,9, 12}, - {"", 0} + { + .name = "75", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 75000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 100000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { .name = "", 0 } } }, { .package = CPU_PKG_386DX, From 1b4408cf387ebd04eb30b49ec683cd30c6a24924 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sat, 20 Jul 2024 23:30:51 -0400 Subject: [PATCH 15/31] Deal with incorrect formatting offset in cpu_table --- src/cpu/cpu_table.c | 5543 ++++++++++++++++++++++--------------------- 1 file changed, 2807 insertions(+), 2736 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 1e756c183..c24167500 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -71,2760 +71,2831 @@ FPU fpus_internal[] = { const cpu_family_t cpu_families[] = { // clang-format off { - .package = CPU_PKG_8088, - .manufacturer = "Intel", - .name = "8088", - .internal_name = "8088", - .cpus = (const CPU[]) { - { - .name = "4.77", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 4772728, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "7.16", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "8", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, + .package = CPU_PKG_8088, + .manufacturer = "Intel", + .name = "8088", + .internal_name = "8088", + .cpus = (const CPU[]) { + { + .name = "4.77", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 4772728, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "7.16", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "8", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, #if 0 - { - .name = "9.54", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, + { + .name = "9.54", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, #endif - { - .name = "10", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "16", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_8088_EUROPC, - .manufacturer = "Intel", - .name = "8088", - .internal_name = "8088_europc", - .cpus = (const CPU[]) { - { - .name = "4.77", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 4772728, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "7.16", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "9.54", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_8086, - .manufacturer = "Intel", - .name = "8086", - .internal_name = "8086", - .cpus = (const CPU[]) { - { - .name = "7.16", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "8", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "9.54", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "10", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "16", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 2 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_188, - .manufacturer = "Intel", - .name = "80188", - .internal_name = "80188", - .cpus = (const CPU[]) { - { - .name = "6", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 6000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "7.16", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "8", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "9.54", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "10", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "16", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 3 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_8088, - .manufacturer = "NEC", - .name = "V20", - .internal_name = "necv20", - .cpus = (const CPU[]) { - { - .name = "4.77", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 4772728, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "7.16", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "10", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "16", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 2 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_186, - .manufacturer = "Intel", - .name = "80186", - .internal_name = "80186", - .cpus = (const CPU[]) { - { - .name = "6", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 6000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "7.16", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 7159092, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "8", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 8000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "9.54", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 9545456, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "10", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 10000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 12000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "16", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 16000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 20000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 25000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 3 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_8086, - .manufacturer = "NEC", - .name = "V30", - .internal_name = "necv30", - .cpus = (const CPU[]) { - { - .name = "5", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 5000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "8", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "10", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 1 - }, - { - .name = "16", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, - .cache_write_cycles = 0, - .atclk_div = 2 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_286, - .manufacturer = "Intel", - .name = "80286", - .internal_name = "286", - .cpus = (const CPU[]) { - { - .name = "6", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 6000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 2, - .mem_write_cycles = 2, - .cache_read_cycles = 2, - .cache_write_cycles = 2, - .atclk_div = 1 - }, - { - .name = "8", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 2, - .mem_write_cycles = 2, - .cache_read_cycles = 2, - .cache_write_cycles = 2, - .atclk_div = 1 - }, - { - .name = "10", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 2, - .mem_write_cycles = 2, - .cache_read_cycles = 2, - .cache_write_cycles = 2, - .atclk_div = 1 - }, - { - .name = "12", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 12500000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "16", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 4, - .cache_write_cycles = 4, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 4, - .cache_write_cycles = 4, - .atclk_div = 3 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386SX, - .manufacturer = "Intel", - .name = "i386SX", - .internal_name = "i386sx", - .cpus = (const CPU[]) { - { - .name = "16", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386SX, - .manufacturer = "AMD", - .name = "Am386SX", - .internal_name = "am386sx", - .cpus = (const CPU[]) { - { - .name = "16", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386DX, - .manufacturer = "Intel", - .name = "i386DX", - .internal_name = "i386dx", - .cpus = (const CPU[]) { - { - .name = "16", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386DX_DESKPRO386, - .manufacturer = "Intel", - .name = "i386DX", - .internal_name = "i386dx_deskpro386", - .cpus = (const CPU[]) { - { - .name = "16", - .cpu_type = CPU_386DX, - .fpus = fpus_80286, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386DX, - .manufacturer = "Intel", - .name = "RapidCAD", - .internal_name = "rapidcad", - .cpus = (const CPU[]) { - { - .name = "25", - .cpu_type = CPU_RAPIDCAD, - .fpus = fpus_internal, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0340, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_RAPIDCAD, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0340, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_RAPIDCAD, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0340, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386DX, - .manufacturer = "AMD", - .name = "Am386DX", - .internal_name = "am386dx", - .cpus = (const CPU[]) { - { - .name = "25", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_M6117, - .manufacturer = "ALi", - .name = "M6117", - .internal_name = "m6117", - .cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */ - { - .name = "33", - .cpu_type = CPU_386SX, - .fpus = fpus_none, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2309, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_386SX, - .fpus = fpus_none, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2309, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386SLC_IBM, - .manufacturer = "IBM", - .name = "386SLC", - .internal_name = "ibm386slc", - .cpus = (const CPU[]) { - { - .name = "16", - .cpu_type = CPU_IBM386SLC, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA301, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 2 - }, - { - .name = "20", - .cpu_type = CPU_IBM386SLC, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA301, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_IBM386SLC, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA301, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386SX, - .manufacturer = "Cyrix", - .name = "Cx486SLC", - .internal_name = "cx486slc", - .cpus = (const CPU[]) { - { - .name = "20", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x400, - .cpuid_model = 0, - .cyrix_id = 0x0000, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "25", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x400, - .cpuid_model = 0, - .cyrix_id = 0x0000, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x400, - .cpuid_model = 0, - .cyrix_id = 0x0000, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386SX, - .manufacturer = "Cyrix", - .name = "Cx486SRx2", - .internal_name = "cx486srx2", - .cpus = (const CPU[]) { - { - .name = "32", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 32000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x406, - .cpuid_model = 0, - .cyrix_id = 0x0006, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x406, - .cpuid_model = 0, - .cyrix_id = 0x0006, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 6 - }, - { - .name = "50", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x406, - .cpuid_model = 0, - .cyrix_id = 0x0006, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 6 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_486SLC_IBM, - .manufacturer = "IBM", - .name = "486SLC", - .internal_name = "ibm486slc", - .cpus = (const CPU[]) { - { - .name = "33", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA401, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_486SLC_IBM, - .manufacturer = "IBM", - .name = "486SLC2", - .internal_name = "ibm486slc2", - .cpus = (const CPU[]) { - { - .name = "40", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA421, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 5 - }, - { - .name = "50", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA421, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 6 - }, - { - .name = "66", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA421, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 8 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_486SLC_IBM, - .manufacturer = "IBM", - .name = "486SLC3", - .internal_name = "ibm486slc3", - .cpus = (const CPU[]) { - { - .name = "60", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 60000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 7 - }, - { - .name = "75", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 75000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 9 - }, - { - .name = "100", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 100000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 12 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_486BL, - .manufacturer = "IBM", - .name = "486BL2", - .internal_name = "ibm486bl2", - .cpus = (const CPU[]) { - { - .name = "50", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 6 - }, - { - .name = "66", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 8 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_486BL, - .manufacturer = "IBM", - .name = "486BL3", - .internal_name = "ibm486bl3", - .cpus = (const CPU[]) { - { - .name = "75", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 75000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 9 - }, - { - .name = "100", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 100000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 12 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386DX, - .manufacturer = "Cyrix", - .name = "Cx486DLC", - .internal_name = "cx486dlc", - .cpus = (const CPU[]) { - { - .name = "25", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x401, - .cpuid_model = 0, - .cyrix_id = 0x0001, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 3 - }, - { - .name = "33", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x401, - .cpuid_model = 0, - .cyrix_id = 0x0001, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x401, - .cpuid_model = 0, - .cyrix_id = 0x0001, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 5 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_386DX, - .manufacturer = "Cyrix", - .name = "Cx486DRx2", - .internal_name = "cx486drx2", - .cpus = (const CPU[]) { - { - .name = "32", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 32000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 4 - }, - { - .name = "40", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 6 - }, - { - .name = "50", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 6 - }, - { - .name = "66", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 8 - }, - { .name = "", 0 } - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486SX", - .internal_name = "i486sx", - .cpus = (const CPU[]) { - {"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486SX-S", - .internal_name = "i486sx_slenh", - .cpus = (const CPU[]) { - {"25", CPU_i486SX_SLENH, fpus_486sx, 25000000, 1, 5000, 0x423, 0x423, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX_SLENH, fpus_486sx, 33333333, 1, 5000, 0x42a, 0x42a, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486SX2", - .internal_name = "i486sx2", - .cpus = (const CPU[]) { - {"50", CPU_i486SX_SLENH, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66 (Q0569)", CPU_i486SX_SLENH, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX", - .internal_name = "i486dx", - .cpus = (const CPU[]) { - {"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX-S", - .internal_name = "i486dx_slenh", - .cpus = (const CPU[]) { - {"33", CPU_i486DX_SLENH, fpus_internal, 33333333, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX2", - .internal_name = "i486dx2", - .cpus = (const CPU[]) { - {"40", CPU_i486DX, fpus_internal, 40000000, 2, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX, fpus_internal, 50000000, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX, fpus_internal, 66666666, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX2-S", - .internal_name = "i486dx2_slenh", - .cpus = (const CPU[]) { - {"40", CPU_i486DX_SLENH, fpus_internal, 40000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, - .manufacturer = "Intel", - .name = "i486DX2 WB", - .internal_name = "i486dx2_pc330", - .cpus = (const CPU[]) { - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. They are functionally identical*/ - .manufacturer = "Intel", - .name = "iDX4", - .internal_name = "idx4", - .cpus = (const CPU[]) { - {"75", CPU_i486DX_SLENH, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_i486DX_SLENH, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3 | CPU_PKG_SOCKET3_PC330, - .manufacturer = "Intel", - .name = "Pentium OverDrive", - .internal_name = "pentium_p24t", - .cpus = (const CPU[]) { - {"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, - {"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486SX", - .internal_name = "am486sx", - .cpus = (const CPU[]) { - {"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486SX2", - .internal_name = "am486sx2", - .cpus = (const CPU[]) { - {"50", CPU_Am486SX, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486SX, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DX", - .internal_name = "am486dx", - .cpus = (const CPU[]) { - {"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DX2", - .internal_name = "am486dx2", - .cpus = (const CPU[]) { - {"50", CPU_Am486DX, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DX, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DXL", - .internal_name = "am486dxl", - .cpus = (const CPU[]) { - {"33", CPU_Am486DXL, fpus_internal, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DXL, fpus_internal, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DXL2", - .internal_name = "am486dxl2", - .cpus = (const CPU[]) { - {"50", CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am486DX4", - .internal_name = "am486dx4", - .cpus = (const CPU[]) { - {"75", CPU_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"90", CPU_Am486DX, fpus_internal, 90000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"100", CPU_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am486DX2 (Enhanced)", - .internal_name = "am486dx2_slenh", - .cpus = (const CPU[]) { - {"66", CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am486DX4 (Enhanced)", - .internal_name = "am486dx4_slenh", - .cpus = (const CPU[]) { - {"75", CPU_ENH_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_ENH_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_ENH_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am5x86", - .internal_name = "am5x86", - .cpus = (const CPU[]) { - {"133 (P75)", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"150 (P75+)", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - {"160 (P90)", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Cyrix", - .name = "Cx486S", - .internal_name = "cx486s", - .cpus = (const CPU[]) { - {"25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Cyrix", - .name = "Cx486DX", - .internal_name = "cx486dx", - .cpus = (const CPU[]) { - {"33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Cyrix", - .name = "Cx486DX2", - .internal_name = "cx486dx2", - .cpus = (const CPU[]) { - {"50", CPU_Cx486DX, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Cx486DX, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Cx486DX, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "Cyrix", - .name = "Cx486DX4", - .internal_name = "cx486dx4", - .cpus = (const CPU[]) { - {"75", CPU_Cx486DX, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "Cyrix", - .name = "Cx5x86", - .internal_name = "cx5x86", - .cpus = (const CPU[]) { - {"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ - {"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"133", CPU_Cx5x86, fpus_internal, 133333333, 4.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"", 0} - } - }, { - .package = CPU_PKG_STPC, - .manufacturer = "ST", - .name = "STPC-DX", - .internal_name = "stpc_dx", - .cpus = (const CPU[]) { - {"66", CPU_STPC, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"75", CPU_STPC, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"", 0} - } - }, { - .package = CPU_PKG_STPC, - .manufacturer = "ST", - .name = "STPC-DX2", - .internal_name = "stpc_dx2", - .cpus = (const CPU[]) { - {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET4, - .manufacturer = "Intel", - .name = "Pentium", - .internal_name = "pentium_p5", - .cpus = (const CPU[]) { - {"50 (Q0399)", CPU_PENTIUM, fpus_internal, 50000000, 1, 5000, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4,3,3, 6}, - {"60", CPU_PENTIUM, fpus_internal, 60000000, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 7}, - {"66", CPU_PENTIUM, fpus_internal, 66666666, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 8}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET4, - .manufacturer = "Intel", - .name = "Pentium OverDrive", - .internal_name = "pentium_p54c_od5v", - .cpus = (const CPU[]) { - {"100", CPU_PENTIUM, fpus_internal, 100000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8,6,6, 12}, - {"120", CPU_PENTIUM, fpus_internal, 120000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 14}, - {"133", CPU_PENTIUM, fpus_internal, 133333333, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 16}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium", - .internal_name = "pentium_p54c", - .cpus = (const CPU[]) { - {"75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 3520, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, - {"100/66", CPU_PENTIUM, fpus_internal, 100000000, 1.5, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"120", CPU_PENTIUM, fpus_internal, 120000000, 2.0, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"133", CPU_PENTIUM, fpus_internal, 133333333, 2.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUM, fpus_internal, 200000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium MMX", - .internal_name = "pentium_p55c", - .cpus = (const CPU[]) { - {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Mobile Pentium MMX", - .internal_name = "pentium_tillamook", - .cpus = (const CPU[]) { - {"120", CPU_PENTIUMMMX, fpus_internal, 120000000, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133", CPU_PENTIUMMMX, fpus_internal, 133333333, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_PENTIUMMMX, fpus_internal, 266666666, 4.0, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUMMMX, fpus_internal, 300000000, 4.5, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium OverDrive", - .internal_name = "pentium_p54c_od3v", - .cpus = (const CPU[]) { - {"125", CPU_PENTIUM, fpus_internal, 125000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, - {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, - {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium OverDrive MMX", - .internal_name = "pentium_p55c_od", - .cpus = (const CPU[]) { - {"75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 7, 7,4,4, 9}, - {"125", CPU_PENTIUMMMX, fpus_internal, 125000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, - {"150/60", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, - {"166", CPU_PENTIUMMMX, fpus_internal, 166000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, - {"180", CPU_PENTIUMMMX, fpus_internal, 180000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 21}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 24}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "IDT", - .name = "WinChip", - .internal_name = "winchip", - .cpus = (const CPU[]) { - {"75", CPU_WINCHIP, fpus_internal, 75000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"90", CPU_WINCHIP, fpus_internal, 90000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"100", CPU_WINCHIP, fpus_internal, 100000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"120", CPU_WINCHIP, fpus_internal, 120000000, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"133", CPU_WINCHIP, fpus_internal, 133333333, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"150", CPU_WINCHIP, fpus_internal, 150000000, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"166", CPU_WINCHIP, fpus_internal, 166666666, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"180", CPU_WINCHIP, fpus_internal, 180000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"200", CPU_WINCHIP, fpus_internal, 200000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"225", CPU_WINCHIP, fpus_internal, 225000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"240", CPU_WINCHIP, fpus_internal, 240000000, 4.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "IDT", - .name = "WinChip 2", - .internal_name = "winchip2", - .cpus = (const CPU[]) { - {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"225", CPU_WINCHIP2, fpus_internal, 225000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, - {"240", CPU_WINCHIP2, fpus_internal, 240000000, 4.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"250", CPU_WINCHIP2, fpus_internal, 250000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "IDT", - .name = "WinChip 2A", - .internal_name = "winchip2a", - .cpus = (const CPU[]) { - {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"233", CPU_WINCHIP2, fpus_internal, 233333333, 3.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, - {"266", CPU_WINCHIP2, fpus_internal, 233333333, 7.0/3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, - {"300", CPU_WINCHIP2, fpus_internal, 250000000, 2.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, - {"", 0} - } + { + .name = "10", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "16", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_8088_EUROPC, + .manufacturer = "Intel", + .name = "8088", + .internal_name = "8088_europc", + .cpus = (const CPU[]) { + { + .name = "4.77", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 4772728, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "7.16", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "9.54", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_8086, + .manufacturer = "Intel", + .name = "8086", + .internal_name = "8086", + .cpus = (const CPU[]) { + { + .name = "7.16", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "8", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "9.54", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "10", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "16", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 2 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_188, + .manufacturer = "Intel", + .name = "80188", + .internal_name = "80188", + .cpus = (const CPU[]) { + { + .name = "6", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 6000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "7.16", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "8", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "9.54", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "10", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "16", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 3 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_8088, + .manufacturer = "NEC", + .name = "V20", + .internal_name = "necv20", + .cpus = (const CPU[]) { + { + .name = "4.77", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 4772728, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "7.16", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "10", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "16", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 2 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_186, + .manufacturer = "Intel", + .name = "80186", + .internal_name = "80186", + .cpus = (const CPU[]) { + { + .name = "6", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 6000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "7.16", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 7159092, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "8", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 8000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "9.54", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 9545456, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "10", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 10000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 12000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "16", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 16000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 20000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 25000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 3 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_8086, + .manufacturer = "NEC", + .name = "V30", + .internal_name = "necv30", + .cpus = (const CPU[]) { + { + .name = "5", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 5000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "8", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "10", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 1 + }, + { + .name = "16", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, + .cache_write_cycles = 0, + .atclk_div = 2 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_286, + .manufacturer = "Intel", + .name = "80286", + .internal_name = "286", + .cpus = (const CPU[]) { + { + .name = "6", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 6000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 2, + .mem_write_cycles = 2, + .cache_read_cycles = 2, + .cache_write_cycles = 2, + .atclk_div = 1 + }, + { + .name = "8", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 2, + .mem_write_cycles = 2, + .cache_read_cycles = 2, + .cache_write_cycles = 2, + .atclk_div = 1 + }, + { + .name = "10", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 2, + .mem_write_cycles = 2, + .cache_read_cycles = 2, + .cache_write_cycles = 2, + .atclk_div = 1 + }, + { + .name = "12", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 12500000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "16", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 3 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386SX, + .manufacturer = "Intel", + .name = "i386SX", + .internal_name = "i386sx", + .cpus = (const CPU[]) { + { + .name = "16", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386SX, + .manufacturer = "AMD", + .name = "Am386SX", + .internal_name = "am386sx", + .cpus = (const CPU[]) { + { + .name = "16", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386DX, + .manufacturer = "Intel", + .name = "i386DX", + .internal_name = "i386dx", + .cpus = (const CPU[]) { + { + .name = "16", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386DX_DESKPRO386, + .manufacturer = "Intel", + .name = "i386DX", + .internal_name = "i386dx_deskpro386", + .cpus = (const CPU[]) { + { + .name = "16", + .cpu_type = CPU_386DX, + .fpus = fpus_80286, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386DX, + .manufacturer = "Intel", + .name = "RapidCAD", + .internal_name = "rapidcad", + .cpus = (const CPU[]) { + { + .name = "25", + .cpu_type = CPU_RAPIDCAD, + .fpus = fpus_internal, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0340, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_RAPIDCAD, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0340, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_RAPIDCAD, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0340, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386DX, + .manufacturer = "AMD", + .name = "Am386DX", + .internal_name = "am386dx", + .cpus = (const CPU[]) { + { + .name = "25", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_M6117, + .manufacturer = "ALi", + .name = "M6117", + .internal_name = "m6117", + .cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */ + { + .name = "33", + .cpu_type = CPU_386SX, + .fpus = fpus_none, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2309, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_386SX, + .fpus = fpus_none, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2309, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386SLC_IBM, + .manufacturer = "IBM", + .name = "386SLC", + .internal_name = "ibm386slc", + .cpus = (const CPU[]) { + { + .name = "16", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386SX, + .manufacturer = "Cyrix", + .name = "Cx486SLC", + .internal_name = "cx486slc", + .cpus = (const CPU[]) { + { + .name = "20", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386SX, + .manufacturer = "Cyrix", + .name = "Cx486SRx2", + .internal_name = "cx486srx2", + .cpus = (const CPU[]) { + { + .name = "32", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 32000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "50", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_486SLC_IBM, + .manufacturer = "IBM", + .name = "486SLC", + .internal_name = "ibm486slc", + .cpus = (const CPU[]) { + { + .name = "33", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA401, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_486SLC_IBM, + .manufacturer = "IBM", + .name = "486SLC2", + .internal_name = "ibm486slc2", + .cpus = (const CPU[]) { + { + .name = "40", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 5 + }, + { + .name = "50", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_486SLC_IBM, + .manufacturer = "IBM", + .name = "486SLC3", + .internal_name = "ibm486slc3", + .cpus = (const CPU[]) { + { + .name = "60", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 60000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 7 + }, + { + .name = "75", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 75000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 100000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_486BL, + .manufacturer = "IBM", + .name = "486BL2", + .internal_name = "ibm486bl2", + .cpus = (const CPU[]) { + { + .name = "50", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_486BL, + .manufacturer = "IBM", + .name = "486BL3", + .internal_name = "ibm486bl3", + .cpus = (const CPU[]) { + { + .name = "75", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 75000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 100000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386DX, + .manufacturer = "Cyrix", + .name = "Cx486DLC", + .internal_name = "cx486dlc", + .cpus = (const CPU[]) { + { + .name = "25", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x401, + .cpuid_model = 0, + .cyrix_id = 0x0001, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x401, + .cpuid_model = 0, + .cyrix_id = 0x0001, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x401, + .cpuid_model = 0, + .cyrix_id = 0x0001, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_386DX, + .manufacturer = "Cyrix", + .name = "Cx486DRx2", + .internal_name = "cx486drx2", + .cpus = (const CPU[]) { + { + .name = "32", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 32000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "50", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX", + .internal_name = "i486sx", + .cpus = (const CPU[]) { + {"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, + {"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"33", CPU_i486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX-S", + .internal_name = "i486sx_slenh", + .cpus = (const CPU[]) { + {"25", CPU_i486SX_SLENH, fpus_486sx, 25000000, 1, 5000, 0x423, 0x423, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"33", CPU_i486SX_SLENH, fpus_486sx, 33333333, 1, 5000, 0x42a, 0x42a, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX2", + .internal_name = "i486sx2", + .cpus = (const CPU[]) { + {"50", CPU_i486SX_SLENH, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66 (Q0569)", CPU_i486SX_SLENH, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX", + .internal_name = "i486dx", + .cpus = (const CPU[]) { + {"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX-S", + .internal_name = "i486dx_slenh", + .cpus = (const CPU[]) { + {"33", CPU_i486DX_SLENH, fpus_internal, 33333333, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX2", + .internal_name = "i486dx2", + .cpus = (const CPU[]) { + {"40", CPU_i486DX, fpus_internal, 40000000, 2, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"50", CPU_i486DX, fpus_internal, 50000000, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66", CPU_i486DX, fpus_internal, 66666666, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX2-S", + .internal_name = "i486dx2_slenh", + .cpus = (const CPU[]) { + {"40", CPU_i486DX_SLENH, fpus_internal, 40000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, + .manufacturer = "Intel", + .name = "i486DX2 WB", + .internal_name = "i486dx2_pc330", + .cpus = (const CPU[]) { + {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. They are functionally identical*/ + .manufacturer = "Intel", + .name = "iDX4", + .internal_name = "idx4", + .cpus = (const CPU[]) { + {"75", CPU_i486DX_SLENH, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"100", CPU_i486DX_SLENH, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3 | CPU_PKG_SOCKET3_PC330, + .manufacturer = "Intel", + .name = "Pentium OverDrive", + .internal_name = "pentium_p24t", + .cpus = (const CPU[]) { + {"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, + {"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486SX", + .internal_name = "am486sx", + .cpus = (const CPU[]) { + {"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486SX2", + .internal_name = "am486sx2", + .cpus = (const CPU[]) { + {"50", CPU_Am486SX, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Am486SX, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DX", + .internal_name = "am486dx", + .cpus = (const CPU[]) { + {"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DX2", + .internal_name = "am486dx2", + .cpus = (const CPU[]) { + {"50", CPU_Am486DX, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Am486DX, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DXL", + .internal_name = "am486dxl", + .cpus = (const CPU[]) { + {"33", CPU_Am486DXL, fpus_internal, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Am486DXL, fpus_internal, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DXL2", + .internal_name = "am486dxl2", + .cpus = (const CPU[]) { + {"50", CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX4", + .internal_name = "am486dx4", + .cpus = (const CPU[]) { + {"75", CPU_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"90", CPU_Am486DX, fpus_internal, 90000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"100", CPU_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"120", CPU_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX2 (Enhanced)", + .internal_name = "am486dx2_slenh", + .cpus = (const CPU[]) { + {"66", CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX4 (Enhanced)", + .internal_name = "am486dx4_slenh", + .cpus = (const CPU[]) { + {"75", CPU_ENH_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"100", CPU_ENH_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"120", CPU_ENH_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am5x86", + .internal_name = "am5x86", + .cpus = (const CPU[]) { + {"133 (P75)", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + {"150 (P75+)", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ + {"160 (P90)", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Cyrix", + .name = "Cx486S", + .internal_name = "cx486s", + .cpus = (const CPU[]) { + {"25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, + {"33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Cyrix", + .name = "Cx486DX", + .internal_name = "cx486dx", + .cpus = (const CPU[]) { + {"33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Cyrix", + .name = "Cx486DX2", + .internal_name = "cx486dx2", + .cpus = (const CPU[]) { + {"50", CPU_Cx486DX, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Cx486DX, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_Cx486DX, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "Cyrix", + .name = "Cx486DX4", + .internal_name = "cx486dx4", + .cpus = (const CPU[]) { + {"75", CPU_Cx486DX, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "Cyrix", + .name = "Cx5x86", + .internal_name = "cx5x86", + .cpus = (const CPU[]) { + {"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ + {"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"133", CPU_Cx5x86, fpus_internal, 133333333, 4.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_STPC, + .manufacturer = "ST", + .name = "STPC-DX", + .internal_name = "stpc_dx", + .cpus = (const CPU[]) { + {"66", CPU_STPC, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"75", CPU_STPC, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_STPC, + .manufacturer = "ST", + .name = "STPC-DX2", + .internal_name = "stpc_dx2", + .cpus = (const CPU[]) { + {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET4, + .manufacturer = "Intel", + .name = "Pentium", + .internal_name = "pentium_p5", + .cpus = (const CPU[]) { + {"50 (Q0399)", CPU_PENTIUM, fpus_internal, 50000000, 1, 5000, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4,3,3, 6}, + {"60", CPU_PENTIUM, fpus_internal, 60000000, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 7}, + {"66", CPU_PENTIUM, fpus_internal, 66666666, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 8}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET4, + .manufacturer = "Intel", + .name = "Pentium OverDrive", + .internal_name = "pentium_p54c_od5v", + .cpus = (const CPU[]) { + {"100", CPU_PENTIUM, fpus_internal, 100000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8,6,6, 12}, + {"120", CPU_PENTIUM, fpus_internal, 120000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 14}, + {"133", CPU_PENTIUM, fpus_internal, 133333333, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 16}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium", + .internal_name = "pentium_p54c", + .cpus = (const CPU[]) { + {"75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 3520, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, + {"100/66", CPU_PENTIUM, fpus_internal, 100000000, 1.5, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"120", CPU_PENTIUM, fpus_internal, 120000000, 2.0, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"133", CPU_PENTIUM, fpus_internal, 133333333, 2.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"200", CPU_PENTIUM, fpus_internal, 200000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium MMX", + .internal_name = "pentium_p55c", + .cpus = (const CPU[]) { + {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Mobile Pentium MMX", + .internal_name = "pentium_tillamook", + .cpus = (const CPU[]) { + {"120", CPU_PENTIUMMMX, fpus_internal, 120000000, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"133", CPU_PENTIUMMMX, fpus_internal, 133333333, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"150", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"266", CPU_PENTIUMMMX, fpus_internal, 266666666, 4.0, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"300", CPU_PENTIUMMMX, fpus_internal, 300000000, 4.5, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium OverDrive", + .internal_name = "pentium_p54c_od3v", + .cpus = (const CPU[]) { + {"125", CPU_PENTIUM, fpus_internal, 125000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, + {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, + {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium OverDrive MMX", + .internal_name = "pentium_p55c_od", + .cpus = (const CPU[]) { + {"75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 7, 7,4,4, 9}, + {"125", CPU_PENTIUMMMX, fpus_internal, 125000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, + {"150/60", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, + {"166", CPU_PENTIUMMMX, fpus_internal, 166000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, + {"180", CPU_PENTIUMMMX, fpus_internal, 180000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 21}, + {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 24}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "IDT", + .name = "WinChip", + .internal_name = "winchip", + .cpus = (const CPU[]) { + {"75", CPU_WINCHIP, fpus_internal, 75000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, + {"90", CPU_WINCHIP, fpus_internal, 90000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, + {"100", CPU_WINCHIP, fpus_internal, 100000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, + {"120", CPU_WINCHIP, fpus_internal, 120000000, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, + {"133", CPU_WINCHIP, fpus_internal, 133333333, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, + {"150", CPU_WINCHIP, fpus_internal, 150000000, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, + {"166", CPU_WINCHIP, fpus_internal, 166666666, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, + {"180", CPU_WINCHIP, fpus_internal, 180000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, + {"200", CPU_WINCHIP, fpus_internal, 200000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"225", CPU_WINCHIP, fpus_internal, 225000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"240", CPU_WINCHIP, fpus_internal, 240000000, 4.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "IDT", + .name = "WinChip 2", + .internal_name = "winchip2", + .cpus = (const CPU[]) { + {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, + {"225", CPU_WINCHIP2, fpus_internal, 225000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, + {"240", CPU_WINCHIP2, fpus_internal, 240000000, 4.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"250", CPU_WINCHIP2, fpus_internal, 250000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "IDT", + .name = "WinChip 2A", + .internal_name = "winchip2a", + .cpus = (const CPU[]) { + {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, + {"233", CPU_WINCHIP2, fpus_internal, 233333333, 3.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, + {"266", CPU_WINCHIP2, fpus_internal, 233333333, 7.0/3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, + {"300", CPU_WINCHIP2, fpus_internal, 250000000, 2.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, + { .name = "", 0 } + } }, #if defined(DEV_BRANCH) && defined(USE_AMD_K5) { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K5 (Model 0)", - .internal_name = "k5_ssa5", - .cpus = (const CPU[]) { - {"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"90 (PR90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K5 (Model 1/2/3)", - .internal_name = "k5_5k86", - .cpus = (const CPU[]) { - {"90 (PR120)", CPU_5K86, fpus_internal, 120000000, 2.0, 3520, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"100 (PR133)", CPU_5K86, fpus_internal, 133333333, 2.0, 3520, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"105 (PR150)", CPU_5K86, fpus_internal, 150000000, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"116.7 (PR166)", CPU_5K86, fpus_internal, 166666666, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"133 (PR200)", CPU_5K86, fpus_internal, 200000000, 3.0, 3520, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, - {"", 0} - } + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K5 (Model 0)", + .internal_name = "k5_ssa5", + .cpus = (const CPU[]) { + {"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"90 (PR90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K5 (Model 1/2/3)", + .internal_name = "k5_5k86", + .cpus = (const CPU[]) { + {"90 (PR120)", CPU_5K86, fpus_internal, 120000000, 2.0, 3520, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"100 (PR133)", CPU_5K86, fpus_internal, 133333333, 2.0, 3520, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"105 (PR150)", CPU_5K86, fpus_internal, 150000000, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"116.7 (PR166)", CPU_5K86, fpus_internal, 166666666, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, + {"133 (PR200)", CPU_5K86, fpus_internal, 200000000, 3.0, 3520, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + { .name = "", 0 } + } }, #endif { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6 (Model 6)", - .internal_name = "k6_m6", - .cpus = (const CPU[]) { - {"66", CPU_K6, fpus_internal, 66666666, 1.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"", 0} - } + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6 (Model 6)", + .internal_name = "k6_m6", + .cpus = (const CPU[]) { + {"66", CPU_K6, fpus_internal, 66666666, 1.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ + {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ + {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + { .name = "", 0 } + } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6 (Model 7)", - .internal_name = "k6_m7", - .cpus = (const CPU[]) { - {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_K6, fpus_internal, 233333333, 3.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_K6, fpus_internal, 266666666, 4.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_K6, fpus_internal, 300000000, 4.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - {"", 0} - } + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6 (Model 7)", + .internal_name = "k6_m7", + .cpus = (const CPU[]) { + {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ + {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ + {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"233", CPU_K6, fpus_internal, 233333333, 3.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"266", CPU_K6, fpus_internal, 266666666, 4.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"300", CPU_K6, fpus_internal, 300000000, 4.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-2", + .internal_name = "k6_2", + .cpus = (const CPU[]) { + {"100", CPU_K6_2, fpus_internal, 100000000, 1.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_K6_2, fpus_internal, 133333333, 2.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ + {"166", CPU_K6_2, fpus_internal, 166666666, 2.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ + {"200", CPU_K6_2, fpus_internal, 200000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ + {"233", CPU_K6_2, fpus_internal, 233333333, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, + {"266", CPU_K6_2, fpus_internal, 266666666, 4.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, + {"300", CPU_K6_2, fpus_internal, 300000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, + {"333", CPU_K6_2, fpus_internal, 332500000, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, + {"350", CPU_K6_2C, fpus_internal, 350000000, 3.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, + {"366", CPU_K6_2C, fpus_internal, 366666666, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, + {"380", CPU_K6_2C, fpus_internal, 380000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, + {"400/66", CPU_K6_2C, fpus_internal, 400000000, 6.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"400/100", CPU_K6_2C, fpus_internal, 400000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"450", CPU_K6_2C, fpus_internal, 450000000, 4.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"475", CPU_K6_2C, fpus_internal, 475000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"500", CPU_K6_2C, fpus_internal, 500000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"533", CPU_K6_2C, fpus_internal, 533333333, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, + {"550", CPU_K6_2C, fpus_internal, 550000000, 5.5, 2300, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + { .name = "", 0 } + } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-2", - .internal_name = "k6_2", - .cpus = (const CPU[]) { - {"100", CPU_K6_2, fpus_internal, 100000000, 1.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_2, fpus_internal, 133333333, 2.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_2, fpus_internal, 166666666, 2.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_2, fpus_internal, 200000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_2, fpus_internal, 233333333, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, - {"266", CPU_K6_2, fpus_internal, 266666666, 4.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, - {"300", CPU_K6_2, fpus_internal, 300000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, - {"333", CPU_K6_2, fpus_internal, 332500000, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, - {"350", CPU_K6_2C, fpus_internal, 350000000, 3.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, - {"366", CPU_K6_2C, fpus_internal, 366666666, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, - {"380", CPU_K6_2C, fpus_internal, 380000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, - {"400/66", CPU_K6_2C, fpus_internal, 400000000, 6.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"400/100", CPU_K6_2C, fpus_internal, 400000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_2C, fpus_internal, 450000000, 4.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_2C, fpus_internal, 475000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_2C, fpus_internal, 500000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"533", CPU_K6_2C, fpus_internal, 533333333, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"550", CPU_K6_2C, fpus_internal, 550000000, 5.5, 2300, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, - {"", 0} - } + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-2+", + .internal_name = "k6_2p", + .cpus = (const CPU[]) { + {"100", CPU_K6_2P, fpus_internal, 100000000, 1.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_K6_2P, fpus_internal, 133333333, 2.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ + {"166", CPU_K6_2P, fpus_internal, 166666666, 2.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ + {"200", CPU_K6_2P, fpus_internal, 200000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ + {"233", CPU_K6_2P, fpus_internal, 233333333, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ + {"266", CPU_K6_2P, fpus_internal, 266666666, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ + {"300", CPU_K6_2P, fpus_internal, 300000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ + {"333", CPU_K6_2P, fpus_internal, 332500000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ + {"350", CPU_K6_2P, fpus_internal, 350000000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ + {"366", CPU_K6_2P, fpus_internal, 366666666, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ + {"380", CPU_K6_2P, fpus_internal, 380000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ + {"400/66", CPU_K6_2P, fpus_internal, 400000000, 6.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ + {"400/100", CPU_K6_2P, fpus_internal, 400000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ + {"450", CPU_K6_2P, fpus_internal, 450000000, 4.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"475", CPU_K6_2P, fpus_internal, 475000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"500", CPU_K6_2P, fpus_internal, 500000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"533", CPU_K6_2P, fpus_internal, 533333333, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, + {"550", CPU_K6_2P, fpus_internal, 550000000, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + { .name = "", 0 } + } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-2+", - .internal_name = "k6_2p", - .cpus = (const CPU[]) { - {"100", CPU_K6_2P, fpus_internal, 100000000, 1.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_2P, fpus_internal, 133333333, 2.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_2P, fpus_internal, 166666666, 2.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_2P, fpus_internal, 200000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_2P, fpus_internal, 233333333, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_2P, fpus_internal, 266666666, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_2P, fpus_internal, 300000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_2P, fpus_internal, 332500000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_2P, fpus_internal, 350000000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_2P, fpus_internal, 366666666, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_2P, fpus_internal, 380000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400/66", CPU_K6_2P, fpus_internal, 400000000, 6.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ - {"400/100", CPU_K6_2P, fpus_internal, 400000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ - {"450", CPU_K6_2P, fpus_internal, 450000000, 4.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_2P, fpus_internal, 475000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_2P, fpus_internal, 500000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"533", CPU_K6_2P, fpus_internal, 533333333, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"550", CPU_K6_2P, fpus_internal, 550000000, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-III", - .internal_name = "k6_3", - .cpus = (const CPU[]) { - {"100", CPU_K6_3, fpus_internal, 100000000, 1.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_3, fpus_internal, 133333333, 2.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_3, fpus_internal, 166666666, 2.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_3, fpus_internal, 200000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_3, fpus_internal, 233333333, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_3, fpus_internal, 266666666, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_3, fpus_internal, 300000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_3, fpus_internal, 332500000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_3, fpus_internal, 350000000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_3, fpus_internal, 366666666, 5.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_3, fpus_internal, 380000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400", CPU_K6_3, fpus_internal, 400000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_3, fpus_internal, 450000000, 4.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-III+", - .internal_name = "k6_3p", - .cpus = (const CPU[]) { - {"100", CPU_K6_3P, fpus_internal, 100000000, 1.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, /* out of spec */ - {"133", CPU_K6_3P, fpus_internal, 133333333, 2.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_3P, fpus_internal, 166666666, 2.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_3P, fpus_internal, 200000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_3P, fpus_internal, 233333333, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_3P, fpus_internal, 266666666, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_3P, fpus_internal, 300000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_3P, fpus_internal, 332500000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_3P, fpus_internal, 350000000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_3P, fpus_internal, 366666666, 5.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_3P, fpus_internal, 380000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400", CPU_K6_3P, fpus_internal, 400000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_3P, fpus_internal, 450000000, 4.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_3P, fpus_internal, 475000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_3P, fpus_internal, 500000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"", 0} - } + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-III", + .internal_name = "k6_3", + .cpus = (const CPU[]) { + {"100", CPU_K6_3, fpus_internal, 100000000, 1.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_K6_3, fpus_internal, 133333333, 2.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ + {"166", CPU_K6_3, fpus_internal, 166666666, 2.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ + {"200", CPU_K6_3, fpus_internal, 200000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ + {"233", CPU_K6_3, fpus_internal, 233333333, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ + {"266", CPU_K6_3, fpus_internal, 266666666, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ + {"300", CPU_K6_3, fpus_internal, 300000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ + {"333", CPU_K6_3, fpus_internal, 332500000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ + {"350", CPU_K6_3, fpus_internal, 350000000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ + {"366", CPU_K6_3, fpus_internal, 366666666, 5.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ + {"380", CPU_K6_3, fpus_internal, 380000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ + {"400", CPU_K6_3, fpus_internal, 400000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"450", CPU_K6_3, fpus_internal, 450000000, 4.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-III+", + .internal_name = "k6_3p", + .cpus = (const CPU[]) { + {"100", CPU_K6_3P, fpus_internal, 100000000, 1.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, /* out of spec */ + {"133", CPU_K6_3P, fpus_internal, 133333333, 2.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ + {"166", CPU_K6_3P, fpus_internal, 166666666, 2.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ + {"200", CPU_K6_3P, fpus_internal, 200000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ + {"233", CPU_K6_3P, fpus_internal, 233333333, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ + {"266", CPU_K6_3P, fpus_internal, 266666666, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ + {"300", CPU_K6_3P, fpus_internal, 300000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ + {"333", CPU_K6_3P, fpus_internal, 332500000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ + {"350", CPU_K6_3P, fpus_internal, 350000000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ + {"366", CPU_K6_3P, fpus_internal, 366666666, 5.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ + {"380", CPU_K6_3P, fpus_internal, 380000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ + {"400", CPU_K6_3P, fpus_internal, 400000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"450", CPU_K6_3P, fpus_internal, 450000000, 4.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"475", CPU_K6_3P, fpus_internal, 475000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"500", CPU_K6_3P, fpus_internal, 500000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + { .name = "", 0 } + } }, #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "Cx6x86", - .internal_name = "cx6x86", - .cpus = (const CPU[]) { - {"80 (PR90+)", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"100 (PR120+)", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"110 (PR133+)", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"120 (PR150+)", CPU_Cx6x86, fpus_internal, 120000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133 (PR166+)", CPU_Cx6x86, fpus_internal, 133333333, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150 (PR200+)", CPU_Cx6x86, fpus_internal, 150000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "Cx6x86L", - .internal_name = "cx6x86l", - .cpus = (const CPU[]) { - {"110 (PR133+)", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"120 (PR150+)", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133 (PR166+)", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150 (PR200+)", CPU_Cx6x86L, fpus_internal, 150000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "Cx6x86MX", - .internal_name = "cx6x86mx", - .cpus = (const CPU[]) { - {"133 (PR166)", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"166 (PR200)", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"187.5 (PR233)", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"208.3 (PR266)", CPU_Cx6x86MX, fpus_internal, 208333333, 2.5, 2700, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "MII", - .internal_name = "mii", - .cpus = (const CPU[]) { - {"233 (PR300)", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"250/83 (PR333)", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"250/100 (PR366)", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, - {"285 (PR400)", CPU_Cx6x86MX, fpus_internal, 285000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, - {"300 (PR433)", CPU_Cx6x86MX, fpus_internal, 300000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, - {"", 0} - } + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "Cx6x86", + .internal_name = "cx6x86", + .cpus = (const CPU[]) { + {"80 (PR90+)", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"100 (PR120+)", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"110 (PR133+)", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"120 (PR150+)", CPU_Cx6x86, fpus_internal, 120000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"133 (PR166+)", CPU_Cx6x86, fpus_internal, 133333333, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"150 (PR200+)", CPU_Cx6x86, fpus_internal, 150000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "Cx6x86L", + .internal_name = "cx6x86l", + .cpus = (const CPU[]) { + {"110 (PR133+)", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"120 (PR150+)", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"133 (PR166+)", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"150 (PR200+)", CPU_Cx6x86L, fpus_internal, 150000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "Cx6x86MX", + .internal_name = "cx6x86mx", + .cpus = (const CPU[]) { + {"133 (PR166)", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"166 (PR200)", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"187.5 (PR233)", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, + {"208.3 (PR266)", CPU_Cx6x86MX, fpus_internal, 208333333, 2.5, 2700, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "MII", + .internal_name = "mii", + .cpus = (const CPU[]) { + {"233 (PR300)", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, + {"250/83 (PR333)", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, + {"250/100 (PR366)", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, + {"285 (PR400)", CPU_Cx6x86MX, fpus_internal, 285000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, + {"300 (PR433)", CPU_Cx6x86MX, fpus_internal, 300000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, + { .name = "", 0 } + } }, #endif { - .package = CPU_PKG_SOCKET8, - .manufacturer = "Intel", - .name = "Pentium Pro", - .internal_name = "pentiumpro", - .cpus = (const CPU[]) { - {"60", CPU_PENTIUMPRO, fpus_internal, 60000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 1, 1, 7}, /* out of spec */ - {"66", CPU_PENTIUMPRO, fpus_internal, 66666666, 1.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 1, 1, 8}, /* out of spec */ - {"90", CPU_PENTIUMPRO, fpus_internal, 90000000, 1.5, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 11}, /* out of spec */ - {"100", CPU_PENTIUMPRO, fpus_internal, 100000000, 1.5, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 12}, /* out of spec */ - {"120", CPU_PENTIUMPRO, fpus_internal, 120000000, 2.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 5, 5, 14}, /* out of spec */ - {"133", CPU_PENTIUMPRO, fpus_internal, 133333333, 2.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 5, 5, 16}, /* out of spec */ - {"150", CPU_PENTIUMPRO, fpus_internal, 150000000, 2.5, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUMPRO, fpus_internal, 166666666, 2.5, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"180", CPU_PENTIUMPRO, fpus_internal, 180000000, 3.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"200", CPU_PENTIUMPRO, fpus_internal, 200000000, 3.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"", 0} - } + .package = CPU_PKG_SOCKET8, + .manufacturer = "Intel", + .name = "Pentium Pro", + .internal_name = "pentiumpro", + .cpus = (const CPU[]) { + {"60", CPU_PENTIUMPRO, fpus_internal, 60000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 1, 1, 7}, /* out of spec */ + {"66", CPU_PENTIUMPRO, fpus_internal, 66666666, 1.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 1, 1, 8}, /* out of spec */ + {"90", CPU_PENTIUMPRO, fpus_internal, 90000000, 1.5, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 11}, /* out of spec */ + {"100", CPU_PENTIUMPRO, fpus_internal, 100000000, 1.5, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 12}, /* out of spec */ + {"120", CPU_PENTIUMPRO, fpus_internal, 120000000, 2.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 5, 5, 14}, /* out of spec */ + {"133", CPU_PENTIUMPRO, fpus_internal, 133333333, 2.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 5, 5, 16}, /* out of spec */ + {"150", CPU_PENTIUMPRO, fpus_internal, 150000000, 2.5, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"166", CPU_PENTIUMPRO, fpus_internal, 166666666, 2.5, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"180", CPU_PENTIUMPRO, fpus_internal, 180000000, 3.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"200", CPU_PENTIUMPRO, fpus_internal, 200000000, 3.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET8, + .manufacturer = "Intel", + .name = "Pentium II OverDrive", + .internal_name = "pentium2_od", + .cpus = (const CPU[]) { + {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of spec */ + {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12, 6, 6, 16}, /* out of spec */ + {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15, 7, 7, 20}, /* out of spec */ + {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18, 9, 9, 24}, /* out of spec */ + {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 21,21,10,10, 28}, /* out of spec */ + {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 24,24,12,12, 32}, /* out of spec */ + {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 5.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 36}, + {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 40}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Pentium II (Klamath)", + .internal_name = "pentium2_klamath", + .cpus = (const CPU[]) { + {"66", CPU_PENTIUM2, fpus_internal, 66666666, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ + {"100", CPU_PENTIUM2, fpus_internal, 100000000, 1.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_PENTIUM2, fpus_internal, 133333333, 2.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ + {"166", CPU_PENTIUM2, fpus_internal, 166666666, 2.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ + {"200", CPU_PENTIUM2, fpus_internal, 200000000, 3.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, /* out of spec */ + {"233", CPU_PENTIUM2, fpus_internal, 233333333, 3.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"266", CPU_PENTIUM2, fpus_internal, 266666666, 4.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"300", CPU_PENTIUM2, fpus_internal, 300000000, 4.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + { .name = "", 0 } + } }, { - .package = CPU_PKG_SOCKET8, - .manufacturer = "Intel", - .name = "Pentium II OverDrive", - .internal_name = "pentium2_od", - .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18, 9, 9, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 21,21,10,10, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 24,24,12,12, 32}, /* out of spec */ - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 5.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 36}, - {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 40}, - {"", 0} - } + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Pentium II (Deschutes)", + .internal_name = "pentium2_deschutes", + .cpus = (const CPU[]) { + {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ + {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 5, 5, 12}, /* out of spec */ + {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ + {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ + {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, /* out of spec */ + {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, /* out of spec */ + {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"350", CPU_PENTIUM2D, fpus_internal, 350000000, 3.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, + {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, + {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Celeron (Covington)", + .internal_name = "celeron_covington", + .cpus = (const CPU[]) { + {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 6, 6, 8}, /* out of spec */ + {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 9, 9, 12}, /* out of spec */ + {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,12,12, 16}, /* out of spec */ + {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,15,15, 20}, /* out of spec */ + {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,18,18, 24}, /* out of spec */ + {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,21,21, 28}, /* out of spec */ + {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,24,24, 32}, + {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,25,25, 36}, + { .name = "", 0 } + } }, { - .package = CPU_PKG_SLOT1, - .manufacturer = "Intel", - .name = "Pentium II (Klamath)", - .internal_name = "pentium2_klamath", - .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2, fpus_internal, 66666666, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2, fpus_internal, 100000000, 1.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_PENTIUM2, fpus_internal, 133333333, 2.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_PENTIUM2, fpus_internal, 166666666, 2.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2, fpus_internal, 200000000, 3.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, /* out of spec */ - {"233", CPU_PENTIUM2, fpus_internal, 233333333, 3.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_PENTIUM2, fpus_internal, 266666666, 4.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUM2, fpus_internal, 300000000, 4.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"", 0} - } - }, { - .package = CPU_PKG_SLOT1, - .manufacturer = "Intel", - .name = "Pentium II (Deschutes)", - .internal_name = "pentium2_deschutes", - .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 5, 5, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"350", CPU_PENTIUM2D, fpus_internal, 350000000, 3.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, - {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, - {"", 0} - } - }, { - .package = CPU_PKG_SLOT1, - .manufacturer = "Intel", - .name = "Celeron (Covington)", - .internal_name = "celeron_covington", - .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 6, 6, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 9, 9, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,12,12, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,15,15, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,18,18, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,21,21, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,24,24, 32}, - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,25,25, 36}, - {"", 0} - } - }, { - .package = CPU_PKG_SLOT2, - .manufacturer = "Intel", - .name = "Pentium II Xeon", - .internal_name = "pentium2_xeon", - .cpus = (const CPU[]) { - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 12}, /* out of spec */ - {"150", CPU_PENTIUM2D, fpus_internal, 150000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 14,14, 4, 4, 18}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 6, 6, 24}, /* out of spec */ - {"250", CPU_PENTIUM2D, fpus_internal, 250000000, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 22,22, 7, 7, 30}, /* out of spec */ - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, /* out of spec */ - {"350", CPU_PENTIUM2D, fpus_internal, 350000000, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,10,10, 42}, /* out of spec */ - {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET370, - .manufacturer = "Intel", - .name = "Celeron (Mendocino)", - .internal_name = "celeron_mendocino", - .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8, 4, 4, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 11,11, 5, 5, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 14,14, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 17,17, 8, 8, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 19,19, 9, 9, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 22,22,11,11, 32}, /* out of spec */ - {"300A", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 25,25,12,12, 36}, - {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 40}, - {"366", CPU_PENTIUM2D, fpus_internal, 366666666, 5.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 33,33,17,17, 44}, - {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 6.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 36,36,12,12, 48}, - {"433", CPU_PENTIUM2D, fpus_internal, 433333333, 6.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 39,39,13,13, 51}, - {"466", CPU_PENTIUM2D, fpus_internal, 466666666, 7.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 42,42,14,14, 56}, - {"500", CPU_PENTIUM2D, fpus_internal, 500000000, 7.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 45,45,15,15, 60}, - {"533", CPU_PENTIUM2D, fpus_internal, 533333333, 8.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 48,48,17,17, 64}, - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET370, - .manufacturer = "VIA", - .name = "Cyrix III", - .internal_name = "c3_samuel", - .cpus = (const CPU[]) { - {"66", CPU_CYRIX3S, fpus_internal, 66666666, 1.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of multiplier range */ - {"100", CPU_CYRIX3S, fpus_internal, 100000000, 1.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 9, 9, 4, 4, 12}, /* out of multiplier range */ - {"133", CPU_CYRIX3S, fpus_internal, 133333333, 2.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 12, 12, 6, 6, 16}, /* out of multiplier range */ - {"166", CPU_CYRIX3S, fpus_internal, 166666666, 2.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 15, 15, 7, 7, 20}, /* out of multiplier range */ - {"200", CPU_CYRIX3S, fpus_internal, 200000000, 3.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 18, 18, 8, 8, 24}, /* out of multiplier range */ - {"233", CPU_CYRIX3S, fpus_internal, 233333333, 3.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 21, 21, 9, 9, 28}, /* out of multiplier range */ - {"266", CPU_CYRIX3S, fpus_internal, 266666666, 4.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 24, 24, 12, 12, 32}, /* out of multiplier range */ - {"300", CPU_CYRIX3S, fpus_internal, 300000000, 4.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 27, 27, 13, 13, 36}, /* out of spec */ - {"333", CPU_CYRIX3S, fpus_internal, 333333333, 5.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 30, 30, 15, 15, 40}, /* out of spec */ - {"366", CPU_CYRIX3S, fpus_internal, 366666666, 5.5, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 33, 33, 16, 16, 44}, /* out of spec */ - {"400", CPU_CYRIX3S, fpus_internal, 400000000, 6.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 36, 36, 17, 17, 48}, - {"433", CPU_CYRIX3S, fpus_internal, 433333333, 6.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 39, 39, 18, 18, 52}, /* out of spec */ - {"450", CPU_CYRIX3S, fpus_internal, 450000000, 4.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 41, 41, 14, 14, 54}, - {"466", CPU_CYRIX3S, fpus_internal, 466666666, 6.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 42, 42, 14, 14, 56}, /* out of spec */ - {"500", CPU_CYRIX3S, fpus_internal, 500000000, 5.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 45, 45, 15, 15, 60}, - {"533", CPU_CYRIX3S, fpus_internal, 533333333, 8.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 48, 48, 15, 15, 64}, /* out of spec */ - {"550", CPU_CYRIX3S, fpus_internal, 550000000, 5.5, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 50, 50, 17, 17, 66}, - {"600/100", CPU_CYRIX3S, fpus_internal, 600000000, 6.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 54, 54, 18, 18, 72}, - {"600/133", CPU_CYRIX3S, fpus_internal, 600000000, 4.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 54, 54, 13, 13, 72}, - {"650", CPU_CYRIX3S, fpus_internal, 650000000, 6.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 58, 58, 20, 20, 78}, - {"667", CPU_CYRIX3S, fpus_internal, 666666667, 5.0, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 60, 60, 16, 16, 80}, - {"700", CPU_CYRIX3S, fpus_internal, 700000000, 7.0, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 63, 63, 21, 21, 84}, - {"733", CPU_CYRIX3S, fpus_internal, 733333333, 5.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 66, 66, 18, 18, 88}, - {"", 0} - } - }, { - .package = 0, - } + .package = CPU_PKG_SLOT2, + .manufacturer = "Intel", + .name = "Pentium II Xeon", + .internal_name = "pentium2_xeon", + .cpus = (const CPU[]) { + {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 12}, /* out of spec */ + {"150", CPU_PENTIUM2D, fpus_internal, 150000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 14,14, 4, 4, 18}, /* out of spec */ + {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 6, 6, 24}, /* out of spec */ + {"250", CPU_PENTIUM2D, fpus_internal, 250000000, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 22,22, 7, 7, 30}, /* out of spec */ + {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, /* out of spec */ + {"350", CPU_PENTIUM2D, fpus_internal, 350000000, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,10,10, 42}, /* out of spec */ + {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, + {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET370, + .manufacturer = "Intel", + .name = "Celeron (Mendocino)", + .internal_name = "celeron_mendocino", + .cpus = (const CPU[]) { + {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of spec */ + {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8, 4, 4, 12}, /* out of spec */ + {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 11,11, 5, 5, 16}, /* out of spec */ + {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 14,14, 7, 7, 20}, /* out of spec */ + {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 17,17, 8, 8, 24}, /* out of spec */ + {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 19,19, 9, 9, 28}, /* out of spec */ + {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 22,22,11,11, 32}, /* out of spec */ + {"300A", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 25,25,12,12, 36}, + {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 40}, + {"366", CPU_PENTIUM2D, fpus_internal, 366666666, 5.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 33,33,17,17, 44}, + {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 6.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 36,36,12,12, 48}, + {"433", CPU_PENTIUM2D, fpus_internal, 433333333, 6.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 39,39,13,13, 51}, + {"466", CPU_PENTIUM2D, fpus_internal, 466666666, 7.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 42,42,14,14, 56}, + {"500", CPU_PENTIUM2D, fpus_internal, 500000000, 7.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 45,45,15,15, 60}, + {"533", CPU_PENTIUM2D, fpus_internal, 533333333, 8.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 48,48,17,17, 64}, + { .name = "", 0 } + } + }, + { + .package = CPU_PKG_SOCKET370, + .manufacturer = "VIA", + .name = "Cyrix III", + .internal_name = "c3_samuel", + .cpus = (const CPU[]) { + {"66", CPU_CYRIX3S, fpus_internal, 66666666, 1.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of multiplier range */ + {"100", CPU_CYRIX3S, fpus_internal, 100000000, 1.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 9, 9, 4, 4, 12}, /* out of multiplier range */ + {"133", CPU_CYRIX3S, fpus_internal, 133333333, 2.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 12, 12, 6, 6, 16}, /* out of multiplier range */ + {"166", CPU_CYRIX3S, fpus_internal, 166666666, 2.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 15, 15, 7, 7, 20}, /* out of multiplier range */ + {"200", CPU_CYRIX3S, fpus_internal, 200000000, 3.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 18, 18, 8, 8, 24}, /* out of multiplier range */ + {"233", CPU_CYRIX3S, fpus_internal, 233333333, 3.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 21, 21, 9, 9, 28}, /* out of multiplier range */ + {"266", CPU_CYRIX3S, fpus_internal, 266666666, 4.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 24, 24, 12, 12, 32}, /* out of multiplier range */ + {"300", CPU_CYRIX3S, fpus_internal, 300000000, 4.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 27, 27, 13, 13, 36}, /* out of spec */ + {"333", CPU_CYRIX3S, fpus_internal, 333333333, 5.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 30, 30, 15, 15, 40}, /* out of spec */ + {"366", CPU_CYRIX3S, fpus_internal, 366666666, 5.5, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 33, 33, 16, 16, 44}, /* out of spec */ + {"400", CPU_CYRIX3S, fpus_internal, 400000000, 6.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 36, 36, 17, 17, 48}, + {"433", CPU_CYRIX3S, fpus_internal, 433333333, 6.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 39, 39, 18, 18, 52}, /* out of spec */ + {"450", CPU_CYRIX3S, fpus_internal, 450000000, 4.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 41, 41, 14, 14, 54}, + {"466", CPU_CYRIX3S, fpus_internal, 466666666, 6.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 42, 42, 14, 14, 56}, /* out of spec */ + {"500", CPU_CYRIX3S, fpus_internal, 500000000, 5.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 45, 45, 15, 15, 60}, + {"533", CPU_CYRIX3S, fpus_internal, 533333333, 8.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 48, 48, 15, 15, 64}, /* out of spec */ + {"550", CPU_CYRIX3S, fpus_internal, 550000000, 5.5, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 50, 50, 17, 17, 66}, + {"600/100", CPU_CYRIX3S, fpus_internal, 600000000, 6.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 54, 54, 18, 18, 72}, + {"600/133", CPU_CYRIX3S, fpus_internal, 600000000, 4.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 54, 54, 13, 13, 72}, + {"650", CPU_CYRIX3S, fpus_internal, 650000000, 6.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 58, 58, 20, 20, 78}, + {"667", CPU_CYRIX3S, fpus_internal, 666666667, 5.0, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 60, 60, 16, 16, 80}, + {"700", CPU_CYRIX3S, fpus_internal, 700000000, 7.0, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 63, 63, 21, 21, 84}, + {"733", CPU_CYRIX3S, fpus_internal, 733333333, 5.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 66, 66, 18, 18, 88}, + { .name = "", 0 } + } + }, + { .package = 0, 0 } // clang-format on }; From 232b44323cce2f762d7fb7975a83bece56f2a4da Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 00:06:33 -0400 Subject: [PATCH 16/31] Named initializers for soclet 1 486's --- src/cpu/cpu_table.c | 810 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 765 insertions(+), 45 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index c24167500..6ae963c79 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -2071,10 +2071,74 @@ const cpu_family_t cpu_families[] = { .name = "i486SX", .internal_name = "i486sx", .cpus = (const CPU[]) { - {"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + { + .name = "16", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, { .name = "", 0 } } }, @@ -2084,8 +2148,40 @@ const cpu_family_t cpu_families[] = { .name = "i486SX-S", .internal_name = "i486sx_slenh", .cpus = (const CPU[]) { - {"25", CPU_i486SX_SLENH, fpus_486sx, 25000000, 1, 5000, 0x423, 0x423, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX_SLENH, fpus_486sx, 33333333, 1, 5000, 0x42a, 0x42a, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + { + .name = "25", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x423, + .cpuid_model = 0x423, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x42a, + .cpuid_model = 0x42a, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, { .name = "", 0 } } }, @@ -2095,8 +2191,40 @@ const cpu_family_t cpu_families[] = { .name = "i486SX2", .internal_name = "i486sx2", .cpus = (const CPU[]) { - {"50", CPU_i486SX_SLENH, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66 (Q0569)", CPU_i486SX_SLENH, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + { + .name = "50", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0x45b, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66 (Q0569)", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0x45b, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2106,9 +2234,57 @@ const cpu_family_t cpu_families[] = { .name = "i486DX", .internal_name = "i486dx", .cpus = (const CPU[]) { - {"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + { + .name = "25", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x404, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x404, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "50", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x411, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 6 + }, { .name = "", 0 } } }, @@ -2118,8 +2294,40 @@ const cpu_family_t cpu_families[] = { .name = "i486DX-S", .internal_name = "i486dx_slenh", .cpus = (const CPU[]) { - {"33", CPU_i486DX_SLENH, fpus_internal, 33333333, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + { + .name = "33", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x414, + .cpuid_model = 0x414, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x414, + .cpuid_model = 0x414, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 6 + }, { .name = "", 0 } } }, @@ -2129,9 +2337,57 @@ const cpu_family_t cpu_families[] = { .name = "i486DX2", .internal_name = "i486dx2", .cpus = (const CPU[]) { - {"40", CPU_i486DX, fpus_internal, 40000000, 2, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX, fpus_internal, 50000000, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX, fpus_internal, 66666666, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { + .name = "40", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 5 + }, + { + .name = "50", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x433, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x433, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2141,9 +2397,57 @@ const cpu_family_t cpu_families[] = { .name = "i486DX2-S", .internal_name = "i486dx2_slenh", .cpus = (const CPU[]) { - {"40", CPU_i486DX_SLENH, fpus_internal, 40000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { + .name = "40", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 5 + }, + { + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2153,8 +2457,40 @@ const cpu_family_t cpu_families[] = { .name = "i486DX2 WB", .internal_name = "i486dx2_pc330", .cpus = (const CPU[]) { - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x436, + .cpuid_model = 0x436, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x436, + .cpuid_model = 0x436, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2164,8 +2500,40 @@ const cpu_family_t cpu_families[] = { .name = "iDX4", .internal_name = "idx4", .cpus = (const CPU[]) { - {"75", CPU_i486DX_SLENH, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_i486DX_SLENH, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, + { + .name = "75", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0x480, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x483, + .cpuid_model = 0x483, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, { .name = "", 0 } } }, @@ -2186,8 +2554,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486SX", .internal_name = "am486sx", .cpus = (const CPU[]) { - {"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2197,8 +2597,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486SX2", .internal_name = "am486sx2", .cpus = (const CPU[]) { - {"50", CPU_Am486SX, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486SX, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + { + .name = "50", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2208,8 +2640,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX", .internal_name = "am486dx", .cpus = (const CPU[]) { - {"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x412, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x412, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2219,9 +2683,57 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX2", .internal_name = "am486dx2", .cpus = (const CPU[]) { - {"50", CPU_Am486DX, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DX, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "50", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2231,8 +2743,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486DXL", .internal_name = "am486dxl", .cpus = (const CPU[]) { - {"33", CPU_Am486DXL, fpus_internal, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DXL, fpus_internal, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2242,9 +2786,57 @@ const cpu_family_t cpu_families[] = { .name = "Am486DXL2", .internal_name = "am486dxl2", .cpus = (const CPU[]) { - {"50", CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "50", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2302,9 +2894,57 @@ const cpu_family_t cpu_families[] = { .name = "Cx486S", .internal_name = "cx486s", .cpus = (const CPU[]) { - {"25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "25", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 40000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2314,8 +2954,40 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX", .internal_name = "cx486dx", .cpus = (const CPU[]) { - {"33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2325,9 +2997,57 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX2", .internal_name = "cx486dx2", .cpus = (const CPU[]) { - {"50", CPU_Cx486DX, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Cx486DX, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Cx486DX, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "50", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x081b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x0b1b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x311b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, From ed6193abc987aaec30bb0025f6e0af1aed19a9f2 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 18:00:52 -0400 Subject: [PATCH 17/31] Named initializers for soclet 3's --- src/cpu/cpu_table.c | 332 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 312 insertions(+), 20 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 6ae963c79..2ec9a3304 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -2543,8 +2543,40 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive", .internal_name = "pentium_p24t", .cpus = (const CPU[]) { - {"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, - {"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, + { + .name = "63", + .cpu_type = CPU_P24T, + .fpus = fpus_internal, + .rspeed = 62500000, + .multi = 2.5, + .voltage = 5000, + .edx_reset = 0x1531, + .cpuid_model = 0x1531, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 15/2 + }, + { + .name = "83", + .cpu_type = CPU_P24T, + .fpus = fpus_internal, + .rspeed = 83333333, + .multi = 2.5, + .voltage = 5000, + .edx_reset = 0x1532, + .cpuid_model = 0x1532, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2846,10 +2878,74 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX4", .internal_name = "am486dx4", .cpus = (const CPU[]) { - {"75", CPU_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"90", CPU_Am486DX, fpus_internal, 90000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"100", CPU_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + { + .name = "75", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "90", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "100", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 15 + }, { .name = "", 0 } } }, @@ -2859,8 +2955,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX2 (Enhanced)", .internal_name = "am486dx2_slenh", .cpus = (const CPU[]) { - {"66", CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "66", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2870,9 +2998,57 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX4 (Enhanced)", .internal_name = "am486dx4_slenh", .cpus = (const CPU[]) { - {"75", CPU_ENH_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_ENH_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_ENH_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + { + .name = "75", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 15 + }, { .name = "", 0 } } }, @@ -2882,9 +3058,57 @@ const cpu_family_t cpu_families[] = { .name = "Am5x86", .internal_name = "am5x86", .cpus = (const CPU[]) { - {"133 (P75)", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"150 (P75+)", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - {"160 (P90)", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + { + .name = "133 (P75)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x4e0, + .cpuid_model = 0x4e0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 16 + }, + { /*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ + .name = "150 (P75+)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 28, + .mem_write_cycles = 28, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 20 + }, + { /*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + .name = "160 (P90)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 160000000, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x4e0, + .cpuid_model = 0x4e0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 28, + .mem_write_cycles = 28, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 20 + }, { .name = "", 0 } } }, @@ -3057,8 +3281,12 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX4", .internal_name = "cx486dx4", .cpus = (const CPU[]) { - {"75", CPU_Cx486DX, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + { + .name = "75", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 75000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 12,.mem_write_cycles = 12, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 9 + }, + { + .name = "100", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 100000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 15,.mem_write_cycles = 15, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 12 + }, { .name = "", 0 } } }, @@ -3068,10 +3296,74 @@ const cpu_family_t cpu_families[] = { .name = "Cx5x86", .internal_name = "cx5x86", .cpus = (const CPU[]) { - {"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ - {"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"133", CPU_Cx5x86, fpus_internal, 133333333, 4.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + { /*If we're including the Pentium 50, might as well include this*/ + .name = "80", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, + { + .name = "100", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 15 + }, + { + .name = "133", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 16 + }, { .name = "", 0 } } }, From 27f83754b231fdbb346a768d30baef056c6306c3 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 18:52:13 -0400 Subject: [PATCH 18/31] Named initializers for STPC CPU's --- src/cpu/cpu_table.c | 54 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 2ec9a3304..2043f8cb6 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -3373,8 +3373,40 @@ const cpu_family_t cpu_families[] = { .name = "STPC-DX", .internal_name = "stpc_dx", .cpus = (const CPU[]) { - {"66", CPU_STPC, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"75", CPU_STPC, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "66", + .cpu_type = CPU_STPC, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, + { + .name = "75", + .cpu_type = CPU_STPC, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -3384,7 +3416,23 @@ const cpu_family_t cpu_families[] = { .name = "STPC-DX2", .internal_name = "stpc_dx2", .cpus = (const CPU[]) { - {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "133", + .cpu_type = CPU_STPC, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3300, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x0b1b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, From b5f85ba26774a8cef6dd72e846bc8c096869437e Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 19:24:16 -0400 Subject: [PATCH 19/31] Named initializers for soclet 4's --- src/cpu/cpu_table.c | 108 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 102 insertions(+), 6 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 2043f8cb6..34832762f 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -3442,9 +3442,57 @@ const cpu_family_t cpu_families[] = { .name = "Pentium", .internal_name = "pentium_p5", .cpus = (const CPU[]) { - {"50 (Q0399)", CPU_PENTIUM, fpus_internal, 50000000, 1, 5000, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4,3,3, 6}, - {"60", CPU_PENTIUM, fpus_internal, 60000000, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 7}, - {"66", CPU_PENTIUM, fpus_internal, 66666666, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 8}, + { + .name = "50 (Q0399)", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x513, + .cpuid_model = 0x513, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 6 + }, + { + .name = "60", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 60000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x517, + .cpuid_model = 0x517, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 7 + }, + { + .name = "66", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x517, + .cpuid_model = 0x517, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -3454,9 +3502,57 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive", .internal_name = "pentium_p54c_od5v", .cpus = (const CPU[]) { - {"100", CPU_PENTIUM, fpus_internal, 100000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8,6,6, 12}, - {"120", CPU_PENTIUM, fpus_internal, 120000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 14}, - {"133", CPU_PENTIUM, fpus_internal, 133333333, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 16}, + { + .name = "100", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x51A, + .cpuid_model = 0x51A, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x51A, + .cpuid_model = 0x51A, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x51A, + .cpuid_model = 0x51A, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, { .name = "", 0 } } }, From e434b3f837056f75fdacac2364ee4d3f3947dd79 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 02:33:03 +0200 Subject: [PATCH 20/31] Opti x81/391: Fix D0000-DFFFF and E0000-EFFFF shadow RAM and disable excess logging. --- src/chipset/opti391.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/chipset/opti391.c b/src/chipset/opti391.c index 8c5dd7b7c..c4c5534f8 100644 --- a/src/chipset/opti391.c +++ b/src/chipset/opti391.c @@ -106,11 +106,11 @@ opti391_shadow_recalc(opti391_t *dev) for (uint8_t i = 0; i < 8; i++) { base = 0xd0000 + (i << 14); if (base >= 0xe0000) { - sh_master = (dev->regs[0x02] & 0x40); - sh_wp = (dev->regs[0x02] & 0x10); - } else { sh_master = (dev->regs[0x02] & 0x20); sh_wp = (dev->regs[0x02] & 0x08); + } else { + sh_master = (dev->regs[0x02] & 0x40); + sh_wp = (dev->regs[0x02] & 0x10); } sh_enable = dev->regs[0x03] & (1 << i); @@ -253,7 +253,7 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) case 0x02: case 0x03: case 0x06: - pclog("Write %02X: %02X\n", dev->index - dev->reg_base, val); + opti391_log("Write %02X: %02X\n", dev->index - dev->reg_base, val); dev->regs[dev->index - dev->reg_base] = val; opti391_shadow_recalc(dev); break; From 3ccca3991f5ed4e2028483f5ccb2a385e8b489d8 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 02:43:24 +0200 Subject: [PATCH 21/31] More moving of SB IRQ's onto a rimer, fixes #1942. --- src/include/86box/snd_sb_dsp.h | 1 + src/sound/snd_sb_dsp.c | 33 ++++++++++++++++++++++----------- 2 files changed, 23 insertions(+), 11 deletions(-) diff --git a/src/include/86box/snd_sb_dsp.h b/src/include/86box/snd_sb_dsp.h index c179fd197..9bc1d2308 100644 --- a/src/include/86box/snd_sb_dsp.h +++ b/src/include/86box/snd_sb_dsp.h @@ -141,6 +141,7 @@ typedef struct sb_dsp_t { int wb_full; pc_timer_t irq_timer; + pc_timer_t irq16_timer; int busy_count; diff --git a/src/sound/snd_sb_dsp.c b/src/sound/snd_sb_dsp.c index de420c740..53666f71d 100644 --- a/src/sound/snd_sb_dsp.c +++ b/src/sound/snd_sb_dsp.c @@ -1722,19 +1722,18 @@ sb_exec_command(sb_dsp_t *dsp) sb_add_data(dsp, dsp->sb_test); break; case 0xF2: /* Trigger 8-bit IRQ */ - sb_dsp_log("Trigger IRQ\n"); - if (IS_ESS(dsp)) { - if (!timer_is_enabled(&dsp->irq_timer)) { - timer_set_delay_u64(&dsp->irq_timer, (100ULL * TIMER_USEC)); - } - } else { - sb_irq(dsp, 1); - dsp->ess_irq_generic = true; + sb_dsp_log("Trigger 8-bit IRQ\n"); + if (!timer_is_enabled(&dsp->irq_timer)) { + timer_set_delay_u64(&dsp->irq_timer, (100ULL * TIMER_USEC)); } break; case 0xF3: /* Trigger 16-bit IRQ */ - sb_dsp_log("Trigger IRQ\n"); - dsp->ess_irq_generic = true; + sb_dsp_log("Trigger 16-bit IRQ\n"); + if (IS_ESS(dsp)) + dsp->ess_irq_generic = true; + else if (!timer_is_enabled(&dsp->irq16_timer)) { + timer_set_delay_u64(&dsp->irq16_timer, (100ULL * TIMER_USEC)); + } break; case 0xF8: if (dsp->sb_type < SB16) @@ -2061,6 +2060,15 @@ sb_dsp_irq_poll(void *priv) dsp->ess_irq_generic = true; } +void +sb_dsp_irq16_poll(void *priv) +{ + sb_dsp_t *dsp = (sb_dsp_t *) priv; + + sb_irq(dsp, 0); + dsp->ess_irq_generic = true; +} + void sb_dsp_init(sb_dsp_t *dsp, int type, int subtype, void *parent) { @@ -2095,15 +2103,18 @@ sb_dsp_init(sb_dsp_t *dsp, int type, int subtype, void *parent) timer_add(&dsp->input_timer, sb_poll_i, dsp, 0); timer_add(&dsp->wb_timer, NULL, dsp, 0); timer_add(&dsp->irq_timer, sb_dsp_irq_poll, dsp, 0); + timer_add(&dsp->irq16_timer, sb_dsp_irq16_poll, dsp, 0); if (IS_ESS(dsp)) /* Initialize ESS filter to 8 kHz. This will be recalculated when a set frequency command is sent. */ recalc_sb16_filter(0, 8000 * 2); - else + else { + timer_add(&dsp->irq16_timer, sb_dsp_irq16_poll, dsp, 0); /* Initialise SB16 filter to same cutoff as 8-bit SBs (3.2 kHz). This will be recalculated when a set frequency command is sent. */ recalc_sb16_filter(0, 3200 * 2); + } if (IS_ESS(dsp) || (dsp->sb_type >= SBPRO2)) { /* OPL3 or dual OPL2 is stereo. */ if (dsp->sb_has_real_opl) From 91874e231a634cf11592464f78d941184213e386 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 03:19:40 +0200 Subject: [PATCH 22/31] The monster FDC ROM is now optionally writable (also finally made the SCSI NVR's per-instance), closes #4623. --- src/floppy/fdc_monster.c | 73 +++++++++++++++++++++++++++++++++++++-- src/include/86box/mem.h | 5 +++ src/mem/mem.c | 13 +++++++ src/scsi/scsi_aha154x.c | 9 +++-- src/scsi/scsi_ncr53c8xx.c | 14 ++++---- src/scsi/scsi_pcscsi.c | 3 +- 6 files changed, 104 insertions(+), 13 deletions(-) diff --git a/src/floppy/fdc_monster.c b/src/floppy/fdc_monster.c index 1629ac1c4..2feafdf07 100644 --- a/src/floppy/fdc_monster.c +++ b/src/floppy/fdc_monster.c @@ -41,13 +41,71 @@ typedef struct monster_fdc_t { rom_t bios_rom; fdc_t *fdc_pri; fdc_t *fdc_sec; + char *nvr_path; } monster_fdc_t; +static void +rom_write(uint32_t addr, uint8_t val, void *priv) +{ + const rom_t *rom = (rom_t *) priv; + +#ifdef ROM_TRACE + if (rom->mapping.base == ROM_TRACE) + rom_log("ROM: read byte from BIOS at %06lX\n", addr); +#endif + + if (addr < rom->mapping.base) + return; + if (addr >= (rom->mapping.base + rom->sz)) + return; + rom->rom[(addr - rom->mapping.base) & rom->mask] = val; +} + +static void +rom_writew(uint32_t addr, uint16_t val, void *priv) +{ + rom_t *rom = (rom_t *) priv; + +#ifdef ROM_TRACE + if (rom->mapping.base == ROM_TRACE) + rom_log("ROM: read word from BIOS at %06lX\n", addr); +#endif + + if (addr < (rom->mapping.base - 1)) + return; + if (addr >= (rom->mapping.base + rom->sz)) + return; + *(uint16_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask] = val; +} + +static void +rom_writel(uint32_t addr, uint32_t val, void *priv) +{ + rom_t *rom = (rom_t *) priv; + +#ifdef ROM_TRACE + if (rom->mapping.base == ROM_TRACE) + rom_log("ROM: read long from BIOS at %06lX\n", addr); +#endif + + if (addr < (rom->mapping.base - 3)) + return; + if (addr >= (rom->mapping.base + rom->sz)) + return; + *(uint32_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask] = val; +} + static void monster_fdc_close(void *priv) { monster_fdc_t *dev = (monster_fdc_t *) priv; + FILE *f = fopen(dev->nvr_path, "wb"); + if (f != NULL) { + fwrite(dev->bios_rom.rom, 1, 0x2000, f); + fclose(f); + } + free(dev); } @@ -79,9 +137,18 @@ monster_fdc_init(UNUSED(const device_t *info)) fdc_set_dma_ch(dev->fdc_sec, sec_dma); #endif -#if 0 uint8_t rom_writes_enabled = device_get_config_int("rom_writes_enabled"); -#endif + if (rom_writes_enabled) { + mem_mapping_set_write_handler(&dev->bios_rom.mapping, rom_write, rom_writew, rom_writel); + dev->nvr_path = "monster_fdc_0.nvr"; + dev->nvr_path[12] = device_get_instance() + 0x30; + FILE *f = fopen(dev->nvr_path, "rb"); + if (f != NULL) { + fread(dev->bios_rom.rom, 1, 0x2000, f); + fclose(f); + } + } else + dev->nvr_path = NULL; return dev; } @@ -197,6 +264,7 @@ static const device_config_t monster_fdc_config[] = { { .description = "" } } }, +#endif { .name = "rom_writes_enabled", .description = "Enable BIOS extension ROM Writes", @@ -204,7 +272,6 @@ static const device_config_t monster_fdc_config[] = { .default_string = "", .default_int = 0 }, -#endif { .name = "", .description = "", .type = CONFIG_END } // clang-format on }; diff --git a/src/include/86box/mem.h b/src/include/86box/mem.h index beb690918..3c0e0aee0 100644 --- a/src/include/86box/mem.h +++ b/src/include/86box/mem.h @@ -391,6 +391,11 @@ extern void mem_mapping_set_handler(mem_mapping_t *, void (*write_w)(uint32_t addr, uint16_t val, void *priv), void (*write_l)(uint32_t addr, uint32_t val, void *priv)); +extern void mem_mapping_set_write_handler(mem_mapping_t *, + void (*write_b)(uint32_t addr, uint8_t val, void *priv), + void (*write_w)(uint32_t addr, uint16_t val, void *priv), + void (*write_l)(uint32_t addr, uint32_t val, void *priv)); + extern void mem_mapping_set_p(mem_mapping_t *, void *priv); extern void mem_mapping_set_addr(mem_mapping_t *, diff --git a/src/mem/mem.c b/src/mem/mem.c index 8f2e0d935..ae6e4ae00 100644 --- a/src/mem/mem.c +++ b/src/mem/mem.c @@ -2556,6 +2556,19 @@ mem_mapping_set_handler(mem_mapping_t *map, mem_mapping_recalc(map->base, map->size); } +void +mem_mapping_set_write_handler(mem_mapping_t *map, + void (*write_b)(uint32_t addr, uint8_t val, void *priv), + void (*write_w)(uint32_t addr, uint16_t val, void *priv), + void (*write_l)(uint32_t addr, uint32_t val, void *priv)) +{ + map->write_b = write_b; + map->write_w = write_w; + map->write_l = write_l; + + mem_mapping_recalc(map->base, map->size); +} + void mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size) { diff --git a/src/scsi/scsi_aha154x.c b/src/scsi/scsi_aha154x.c index 2927d797c..c811c2c87 100644 --- a/src/scsi/scsi_aha154x.c +++ b/src/scsi/scsi_aha154x.c @@ -1043,7 +1043,8 @@ aha_init(const device_t *info) case AHA_154xC: strcpy(dev->name, "AHA-154xC"); dev->bios_path = "roms/scsi/adaptec/aha1542c102.bin"; - dev->nvr_path = "aha1542c.nvr"; + dev->nvr_path = "aha1542c_0.nvr"; + dev->nvr_path[9] = device_get_instance() + 0x30; dev->fw_rev = "D001"; dev->rom_shram = 0x3F80; /* shadow RAM address base */ dev->rom_shramsz = 128; /* size of shadow RAM */ @@ -1059,7 +1060,8 @@ aha_init(const device_t *info) case AHA_154xCF: strcpy(dev->name, "AHA-154xCF"); dev->bios_path = "roms/scsi/adaptec/aha1542cf211.bin"; - dev->nvr_path = "aha1542cf.nvr"; + dev->nvr_path = "aha1542cf_0.nvr"; + dev->nvr_path[10] = device_get_instance() + 0x30; dev->fw_rev = "E001"; dev->rom_shram = 0x3F80; /* shadow RAM address base */ dev->rom_shramsz = 128; /* size of shadow RAM */ @@ -1080,7 +1082,8 @@ aha_init(const device_t *info) bios_rev = (char *) device_get_config_bios("bios_rev"); dev->bios_path = (char *) device_get_bios_file(info, bios_rev, 0); dev->mcode_path = (char *) device_get_bios_file(info, bios_rev, 1); - dev->nvr_path = "aha1542cp.nvr"; + dev->nvr_path = "aha1542cp_0.nvr"; + dev->nvr_path[10] = device_get_instance() + 0x30; dev->fw_rev = aha1542cp_rev; dev->rom_shram = 0x3F80; /* shadow RAM address base */ dev->rom_shramsz = 128; /* size of shadow RAM */ diff --git a/src/scsi/scsi_ncr53c8xx.c b/src/scsi/scsi_ncr53c8xx.c index f640c49a6..1fd9fcdba 100644 --- a/src/scsi/scsi_ncr53c8xx.c +++ b/src/scsi/scsi_ncr53c8xx.c @@ -2571,37 +2571,39 @@ ncr53c8xx_init(const device_t *info) switch (dev->chip) { case CHIP_810: - dev->nvr_path = "ncr53c810.nvr"; + dev->nvr_path = "ncr53c810_0.nvr"; dev->wide = 0; break; case CHIP_815: dev->chip_rev = 0x04; - dev->nvr_path = "ncr53c815.nvr"; + dev->nvr_path = "ncr53c815_0.nvr"; dev->wide = 0; break; case CHIP_820: - dev->nvr_path = "ncr53c820.nvr"; + dev->nvr_path = "ncr53c820_0.nvr"; dev->wide = 1; break; case CHIP_825: dev->chip_rev = 0x26; - dev->nvr_path = "ncr53c825a.nvr"; + dev->nvr_path = "ncr53c825_0.nvr"; dev->wide = 1; break; case CHIP_860: scsi_bus_set_speed(dev->bus, 20000000.0); dev->chip_rev = 0x04; - dev->nvr_path = "ncr53c860.nvr"; + dev->nvr_path = "ncr53c860_0.nvr"; dev->wide = 1; break; case CHIP_875: scsi_bus_set_speed(dev->bus, 40000000.0); dev->chip_rev = 0x04; - dev->nvr_path = "ncr53c875.nvr"; + dev->nvr_path = "ncr53c875_0.nvr"; dev->wide = 1; break; } + dev->nvr_path[10] = device_get_instance() + 0x30; + ncr53c8xx_pci_bar[0].addr_regs[0] = 1; ncr53c8xx_pci_bar[1].addr_regs[0] = 0; ncr53c8xx_pci_regs[0x04] = 3; diff --git a/src/scsi/scsi_pcscsi.c b/src/scsi/scsi_pcscsi.c index 674bbdabf..48b2d52fa 100644 --- a/src/scsi/scsi_pcscsi.c +++ b/src/scsi/scsi_pcscsi.c @@ -1856,7 +1856,8 @@ dc390_init(UNUSED(const device_t *info)) if (dev->has_bios) esp_bios_disable(dev); - dev->nvr_path = "dc390.nvr"; + dev->nvr_path = "dc390_0.nvr"; + dev->nvr_path[6] = device_get_instance() + 0x30; /* Load the serial EEPROM. */ dc390_load_eeprom(dev); From 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})->setCheckable(true); + menu->addAction(ProgSettings::loadIcon("/cdrom_mute.ico"), tr("&Mute"), [this, i]() { cdromMute(i); })->setCheckable(true); menu->addSeparator(); - menu->addAction(ProgSettings::loadIcon("/cdrom.ico"), tr("&Image..."), [this, i]() { cdromMount(i, 0, nullptr); })->setCheckable(false); - menu->addAction(QApplication::style()->standardIcon(QStyle::SP_DirIcon), tr("&Folder..."), [this, i]() { cdromMount(i, 1, nullptr); })->setCheckable(false); + menu->addAction(ProgSettings::loadIcon("/cdrom_image.ico"), tr("&Image..."), [this, i]() { cdromMount(i, 0, nullptr); })->setCheckable(false); + menu->addAction(ProgSettings::loadIcon("/cdrom_folder.ico"), tr("&Folder..."), [this, i]() { cdromMount(i, 1, nullptr); })->setCheckable(false); menu->addSeparator(); for (int slot = 0; slot < MAX_PREV_IMAGES; slot++) { cdromImageHistoryPos[slot] = menu->children().count(); @@ -160,7 +160,7 @@ MediaMenu::refresh(QMenu *parentMenu) for (const auto &letter : driveLetters) { auto drive = QString("%1:\\").arg(letter); if (GetDriveType(drive.toUtf8().constData()) == DRIVE_CDROM) - menu->addAction(QApplication::style()->standardIcon(QStyle::SP_DriveCDIcon), tr("Host CD/DVD Drive (%1:)").arg(letter), [this, i, letter] { cdromMount(i, 2, QString(R"(\\.\%1:)").arg(letter)); })->setCheckable(false); + menu->addAction(ProgSettings::loadIcon("/cdrom_host.ico"), tr("Host CD/DVD Drive (%1:)").arg(letter), [this, i, letter] { cdromMount(i, 2, QString(R"(\\.\%1:)").arg(letter)); })->setCheckable(false); } menu->addSeparator(); #endif // Q_OS_WINDOWS @@ -587,7 +587,7 @@ MediaMenu::updateImageHistory(int index, int slot, ui::MediaType type) children = menu->children(); imageHistoryUpdatePos = dynamic_cast(children[cdromImageHistoryPos[slot]]); if (fn.left(8) == "ioctl://") { - menu_icon = QApplication::style()->standardIcon(QStyle::SP_DriveCDIcon); + menu_icon = ProgSettings::loadIcon("/cdrom_host.ico"); #ifdef Q_OS_WINDOWS menu_item_name = tr("Host CD/DVD Drive (%1)").arg(fn.right(2)).toUtf8().constData(); #else @@ -595,7 +595,7 @@ MediaMenu::updateImageHistory(int index, int slot, ui::MediaType type) #endif } else { fi.setFile(fn); - menu_icon = fi.isDir() ? QApplication::style()->standardIcon(QStyle::SP_DirIcon) : ProgSettings::loadIcon("/cdrom.ico"); + menu_icon = fi.isDir() ? ProgSettings::loadIcon("/cdrom_folder.ico") : ProgSettings::loadIcon("/cdrom_image.ico"); menu_item_name = fn.isEmpty() ? tr("previous image").toUtf8().constData() : fn.toUtf8().constData(); } imageHistoryUpdatePos->setIcon(menu_icon); @@ -642,7 +642,7 @@ MediaMenu::cdromUpdateMenu(int i) auto childs = menu->children(); auto *muteMenu = dynamic_cast(childs[cdromMutePos]); - muteMenu->setIcon(QApplication::style()->standardIcon((cdrom[i].sound_on == 0) ? QStyle::SP_MediaVolume : QStyle::SP_MediaVolumeMuted)); + muteMenu->setIcon(ProgSettings::loadIcon((cdrom[i].sound_on == 0) ? "/cdrom_unmute.ico" : "/cdrom_mute.ico")); muteMenu->setText((cdrom[i].sound_on == 0) ? tr("&Unmute") : tr("&Mute")); auto *imageMenu = dynamic_cast(childs[cdromImagePos]); @@ -655,13 +655,13 @@ MediaMenu::cdromUpdateMenu(int i) menu_item_name = tr("Host CD/DVD Drive (%1)").arg(name.right(name.length() - 8)); #endif name2 = menu_item_name; - menu_icon = QApplication::style()->standardIcon(QStyle::SP_DriveCDIcon); + menu_icon = ProgSettings::loadIcon("/cdrom_host.ico"); } else { QFileInfo fi(cdrom[i].image_path); menu_item_name = name.isEmpty() ? QString().toUtf8().constData() : name.toUtf8().constData(); name2 = name; - menu_icon = fi.isDir() ? QApplication::style()->standardIcon(QStyle::SP_DirIcon) : ProgSettings::loadIcon("/cdrom.ico"); + menu_icon = fi.isDir() ? ProgSettings::loadIcon("/cdrom_folder.ico") : ProgSettings::loadIcon("/cdrom_image.ico"); } imageMenu->setIcon(menu_icon); imageMenu->setText(QString::asprintf(tr("Eject %s").toUtf8().constData(), menu_item_name.toUtf8().constData())); From af357b5ee5206c8e723b45be6417508477a0bfc8 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 05:09:36 +0200 Subject: [PATCH 28/31] Updated qt_resources.qrc, now they actually work. --- src/qt_resources.qrc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/qt_resources.qrc b/src/qt_resources.qrc index 265fb6376..2c4e9775a 100644 --- a/src/qt_resources.qrc +++ b/src/qt_resources.qrc @@ -11,6 +11,11 @@ qt/icons/cdrom_disabled.ico qt/icons/cdrom_empty.ico qt/icons/cdrom_empty_active.ico + qt/icons/cdrom_mute.ico + qt/icons/cdrom_unmute.ico + qt/icons/cdrom_image.ico + qt/icons/cdrom_folder.ico + qt/icons/cdrom_host.ico qt/icons/display.ico qt/icons/floppy_35.ico qt/icons/floppy_35_active.ico From 62c3fdb2ce8f50f0f49bafe6f8d2c8b18f96015e Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 16:13:46 +0200 Subject: [PATCH 29/31] Correct the maximum RAM amount of the Genoa Unknown 486 to 16 MB. --- src/machine/machine_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 38abd77b8..c26c9b580 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -5697,7 +5697,7 @@ const machine_t machines[] = { .flags = MACHINE_APM, .ram = { .min = 1024, - .max = 65536, + .max = 16384, .step = 1024 }, .nvrmask = 127, From 46db537b74c04b27bd4c17ae28228a50c97ca350 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 16:42:40 +0200 Subject: [PATCH 30/31] Compaq Genoa device now also adds Compaq 386 device, for some reason, that's necessary for shadow RAM to work. --- src/chipset/compaq_386.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/chipset/compaq_386.c b/src/chipset/compaq_386.c index 4eb21de72..6a015937e 100644 --- a/src/chipset/compaq_386.c +++ b/src/chipset/compaq_386.c @@ -37,6 +37,7 @@ #include <86box/vid_cga.h> #include <86box/vid_cga_comp.h> #include <86box/plat_unused.h> +#include <86box/chipset.h> #define RAM_DIAG_L_BASE_MEM_640KB 0x00 #define RAM_DIAG_L_BASE_MEM_INV 0x10 @@ -749,18 +750,22 @@ compaq_386_init(UNUSED(const device_t *info)) static void compaq_genoa_outw(uint16_t port, uint16_t val, void *priv) { - if (port == 0x0c02) { + if (port == 0x0c02) { if (val) - mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); else mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + + flushmmucache_nopc(); } } static void * compaq_genoa_init(UNUSED(const device_t *info)) { - io_sethandler(0x0c02, 3, NULL, NULL, NULL, NULL, compaq_genoa_outw, NULL, ram); + io_sethandler(0x0c02, 2, NULL, NULL, NULL, NULL, compaq_genoa_outw, NULL, NULL); + + device_add(&compaq_386_device); return ram; } From 95894198bf8691a095021819da1224e05e8a4911 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 22 Jul 2024 18:26:10 +0200 Subject: [PATCH 31/31] Genoa Unknown 486: Reset BIOS memory state on soft reset, fixes hangs on soft reset after saving CMOS Setup. --- src/chipset/compaq_386.c | 12 +++++++++--- src/cpu/x86.c | 4 ++-- src/include/86box/device.h | 1 + 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/chipset/compaq_386.c b/src/chipset/compaq_386.c index 6a015937e..a0bd036f3 100644 --- a/src/chipset/compaq_386.c +++ b/src/chipset/compaq_386.c @@ -752,7 +752,7 @@ compaq_genoa_outw(uint16_t port, uint16_t val, void *priv) { if (port == 0x0c02) { if (val) - mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); else mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); @@ -760,6 +760,12 @@ compaq_genoa_outw(uint16_t port, uint16_t val, void *priv) } } +static void +compaq_genoa_reset(void *priv) +{ + mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); +} + static void * compaq_genoa_init(UNUSED(const device_t *info)) { @@ -787,11 +793,11 @@ const device_t compaq_386_device = { const device_t compaq_genoa_device = { .name = "Compaq Genoa Memory Control", .internal_name = "compaq_genoa", - .flags = 0, + .flags = DEVICE_SOFTRESET, .local = 0, .init = compaq_genoa_init, .close = NULL, - .reset = NULL, + .reset = compaq_genoa_reset, { .available = NULL }, .speed_changed = NULL, .force_redraw = NULL, diff --git a/src/cpu/x86.c b/src/cpu/x86.c index 32b274f06..5435f366d 100644 --- a/src/cpu/x86.c +++ b/src/cpu/x86.c @@ -240,7 +240,6 @@ reset_common(int hard) if (!hard && reset_on_hlt) { hlt_reset_pending++; - pclog("hlt_reset_pending = %i\n", hlt_reset_pending); if (hlt_reset_pending == 2) hlt_reset_pending = 0; else @@ -352,7 +351,8 @@ reset_common(int hard) /* If we have an AT or PS/2 keyboard controller, make sure the A20 state is correct. */ device_reset_all(DEVICE_KBC); - } + } else + device_reset_all(DEVICE_SOFTRESET); if (!is286) reset_808x(hard); diff --git a/src/include/86box/device.h b/src/include/86box/device.h index 1a2a6fd8b..67a30b1c8 100644 --- a/src/include/86box/device.h +++ b/src/include/86box/device.h @@ -101,6 +101,7 @@ enum { DEVICE_COM = 0x100000, /* requires a serial port */ DEVICE_LPT = 0x200000, /* requires a parallel port */ DEVICE_KBC = 0x400000, /* is a keyboard controller */ + DEVICE_SOFTRESET = 0x800000, /* requires to be reset on soft reset */ DEVICE_ONBOARD = 0x40000000, /* is on-board */ DEVICE_PIT = 0x80000000, /* device is a PIT */