diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h
index b7c5fa29a..9a4a7c55b 100644
--- a/src/include/86box/nv/vid_nv.h
+++ b/src/include/86box/nv/vid_nv.h
@@ -127,389 +127,5 @@ typedef struct nv_register_s
 
 nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs);
 
-// Default value for the boot information register.
-// Depends on the chip
-#define NV3_BOOT_REG_REV_A00    0x00030100
-#define NV3_BOOT_REG_REV_B00    0x00030110
-#define NV3_BOOT_REG_REV_C00    0x00030120
 
-// Master Control
-typedef struct nv3_pmc_s
-{
-    /* 
-    Holds chip manufacturing information at bootup.
-    Current specification (may change later): pre-packed for convenience
-
-    FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?)
-    31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001
-    little endian 00000000 00000011 00000001 00010001   = 0x00300111
-    */
-    int32_t boot;   
-    int32_t interrupt_status;          // Determines if interrupts are pending for specific subsystems.
-    int32_t interrupt_enable;   // Determines if interrupts are actually enabled.
-    int32_t enable;             // Determines which subsystems are enabled.
-
-} nv3_pmc_t;
-
-typedef struct nv3_pci_config_s
-{
-    uint8_t pci_regs[NV_PCI_NUM_CFG_REGS];  // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability)
-    bool    vbios_enabled;                  // is the vbios enabled?
-    uint8_t int_line;
-} nv3_pci_config_t;
-
-// add enums for eac
-// Chip configuration
-typedef struct nv3_straps_s
-{
-    uint32_t straps;
-} nv3_straps_t;
-
-// Framebuffer
-typedef struct nv3_pfb_s
-{
-    uint32_t boot;
-    uint32_t config_0;
-    uint32_t config_1;
-} nv3_pfb_t;
-
-#define NV3_RMA_NUM_REGS        4
-// Access the GPU from real-mode
-typedef struct nv3_pbus_rma_s
-{
-    uint32_t addr;                      // Address to RMA to
-    uint32_t data;                      // Data to send to MMIO
-    uint8_t mode;                       // the current state of the rma shifting engin
-    uint8_t rma_regs[NV3_RMA_NUM_REGS]; // The rma registers (saved)
-} nv3_pbus_rma_t;
-
-// Bus Configuration
-typedef struct nv3_pbus_s
-{
-    uint32_t interrupt_status;          // Interrupt status
-    uint32_t interrupt_enable;          // Interrupt enable
-    nv3_pbus_rma_t rma;
-} nv3_pbus_t;
-
-// Command submission to PGRAPH
-typedef struct nv_pfifo_s
-{
-    uint32_t interrupt_status;          // Interrupt status
-    uint32_t interrupt_enable;          // Interrupt enable
-} nv3_pfifo_t;
-
-// RAMDAC
-typedef struct nv3_pramdac_s
-{
-    // these should be uint8_t but C math is a lot better with this
-    uint32_t memory_clock_m;    // memory clock M-divider
-    uint32_t memory_clock_n;    // memory clock N-divider
-    uint32_t memory_clock_p;    // memory clock P-divider
-    uint32_t pixel_clock_m;     // pixel clock M-divider
-    uint32_t pixel_clock_n;     // pixel clock N-divider
-    uint32_t pixel_clock_p;     // pixel clock P-divider
-    uint32_t coeff_select;      // coefficient select
-
-    uint32_t general_control;   // general control register
-
-    // this could duplicate SVGA state but I tihnk it's more readable,
-    // we'll just modify both
-    uint32_t vserr_width;       // vertical sync error width
-    uint32_t vequ_end;          // vequ end (not sure what this is)
-    uint32_t vbblank_end;       // vbblank end (not sure what this is)
-    uint32_t vblank_end;        // vblank end
-    uint32_t vblank_start;      // vblank start
-    uint32_t vequ_start;        // vequ start (not sure what this is)
-    uint32_t vtotal;            // vertical total lines
-    uint32_t hsync_width;       // horizontal sync width
-    uint32_t hburst_start;      // horizontal burst signal start (in lines)
-    uint32_t hburst_end;        // horizontal burst signal end (in lines)
-    uint32_t hblank_start;      // horizontal blank start (in lines)
-    uint32_t hblank_end;        // horizontal blank end (in lines)
-    uint32_t htotal;            // horizontal total lines
-    uint32_t hequ_width;        // horizontal equ width (not sure what this is)
-    uint32_t hserr_width;       // horizontal sync error width
-} nv3_pramdac_t;
-
-// Graphics Subsystem
-typedef struct nv3_pgraph_s
-{
-    uint32_t interrupt_status_0;          // Interrupt status 0
-    uint32_t interrupt_enable_0;          // Interrupt enable 0 
-    uint32_t interrupt_status_1;          // Interrupt status 1
-    uint32_t interrupt_enable_1;          // Interrupt enable 1
-} nv3_pgraph_t;
-
-// GPU Manufacturing Configuration (again)
-// In the future this will be configurable
-typedef struct nv3_pextdev_s
-{
-    /*
-    // Disabled     33Mhz
-    // Enabled      66Mhz
-    bool bus_speed;
-    
-    // Disabled     No BIOS
-    // Enabled      BIOS
-    bool bios;
-
-    // RAM Type #1
-    // Disabled     16Mbit (2MB) module size
-    // Enabled      8Mbit (1MB) module size
-    bool ram_type_1;
-
-    // NEC Mode
-    bool nec_mode;
-
-    // Disabled     64-bit
-    // Enabled      128-bit
-    bool bus_width;
-
-    // Disabled     PCI
-    // Enabled      AGP
-    bool bus_type;
-
-    // Disabled     13500
-    // Enabled      14318180
-    bool crystal;
-
-    // TV Mode
-    // 0 - SECAM, 1 - NTSC, 2 - PAL, 3 - none
-    uint8_t tv_mode;
-
-    // AGP 2X mode
-    // Disabled     AGP 1X
-    // Enabled      AGP 2X
-    bool agp_is_2x; 
-    
-    bool unused;
-
-    // Overwrite enable
-    bool overwrite;
-
-    See defines in vid_nv3.h
-    */
-    uint32_t straps;
-    
-    // more ram type stuff here but not used?
-} nv3_pextdev_t;
-
-typedef struct nv3_ptimer_s
-{
-    uint32_t interrupt_status;          // PTIMER Interrupt status
-    uint32_t interrupt_enable;          // PTIMER Interrupt enable
-    uint32_t clock_numerator;           // PTIMER (tick?) numerator
-    uint32_t clock_denominator;         // PTIMER (tick?) denominator
-    uint64_t time;                      // time
-    uint32_t alarm;                     // The value of time when there should be an alarm
-} nv3_ptimer_t;
-
-// Graphics object hashtable
-typedef struct nv3_pramin_ramht_s
-{
-
-} nv3_pramin_ramht_t;
-
-// Anti-fuckup device
-typedef struct nv3_pramin_ramro_s
-{
-
-} nv3_pramin_ramro_t;
-
-// context for unused channels
-typedef struct nv3_pramin_ramfc_s
-{
-
-} nv3_pramin_ramfc_t;
-
-// ????? ram auxillary
-typedef struct nv_pramin_ramau_s
-{
-
-} nv3_pramin_ramau_t;
-
-typedef struct nv3_pramin_s
-{
-
-} nv3_pramin_t;
-
-typedef struct nv3_pvideo_s
-{
-    uint32_t interrupt_status;          // Interrupt status
-    uint32_t interrupt_enable;          // Interrupt enable
-} nv3_pvideo_t;
-
-typedef struct nv3_pme_s                // Mediaport
-{
-    uint32_t interrupt_status;
-    uint32_t interrupt_enable;
-} nv3_pme_t;
-
-typedef struct nv3_s
-{
-    nv_base_t nvbase;   // Base Nvidia structure
-    
-    // Config
-    nv3_straps_t straps;
-    nv3_pci_config_t pci_config;
-
-    // Subsystems
-    nv3_pmc_t pmc;              // Master Control
-    nv3_pfb_t pfb;              // Framebuffer/VRAM
-    nv3_pbus_t pbus;            // Bus Control
-    nv3_pfifo_t pfifo;          // FIFO for command submisison
-
-    nv3_pramdac_t pramdac;      // RAMDAC (CLUT etc)
-    nv3_pgraph_t pgraph;        // 2D/3D Graphics
-    nv3_pextdev_t pextdev;      // Chip configuration
-    nv3_ptimer_t ptimer;        // programmable interval timer
-    nv3_pramin_ramht_t ramht;   // hashtable for PGRAPH objects
-    nv3_pramin_ramro_t ramro;   // anti-fuckup mechanism for idiots who fucked up the FIFO submission
-    nv3_pramin_ramfc_t ramfc;   // context for unused channels
-    nv3_pramin_ramau_t ramau;   // auxillary weirdnes
-    nv3_pramin_t pramin;        // Ram for INput of DMA objects. Very important!
-    nv3_pvideo_t pvideo;        // Video overlay
-    nv3_pme_t pme;              // Mediaport - external MPEG decoder and video interface
-    //more here
-
-} nv3_t;
-
-// device objects
-extern nv3_t* nv3;
-
-// Address of this returned by unimplemented registers to prevent a crash
-extern uint32_t    unimplemented_dummy;
-
-// NV3 stuff
-
-// Device Core
-void*       nv3_init(const device_t *info);
-void        nv3_close(void* priv);
-void        nv3_speed_changed(void *priv);
-void        nv3_force_redraw(void* priv);
-
-// Memory Mapping
-void        nv3_update_mappings();
-uint8_t     nv3_mmio_read8(uint32_t addr, void* priv);                          // Read 8-bit MMIO
-uint16_t    nv3_mmio_read16(uint32_t addr, void* priv);                         // Read 16-bit MMIO
-uint32_t    nv3_mmio_read32(uint32_t addr, void* priv);                         // Read 32-bit MMIO
-void        nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv);            // Write 8-bit MMIO
-void        nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv);          // Write 16-bit MMIO
-void        nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv);          // Write 32-bit MMIO
-
-uint8_t     nv3_svga_in(uint16_t addr, void* priv);                             // Read SVGA compatibility registers
-void        nv3_svga_out(uint16_t addr, uint8_t val, void* priv);               // Write SVGA registers
-uint8_t     nv3_pci_read(int32_t func, int32_t addr, void* priv);               // Read PCI configuration registers
-void        nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers
-
-uint8_t     nv3_ramin_read8(uint32_t addr, void* priv);                          // Read 8-bit RAMIN
-uint16_t    nv3_ramin_read16(uint32_t addr, void* priv);                         // Read 16-bit RAMIN
-uint32_t    nv3_ramin_read32(uint32_t addr, void* priv);                         // Read 32-bit RAMIN
-void        nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv);            // Write 8-bit RAMIN
-void        nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv);          // Write 16-bit RAMIN
-void        nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv);          // Write 32-bit RAMIN
-
-// MMIO Arbitration
-// Determine where the hell in this mess our reads or writes are going
-uint32_t    nv3_mmio_arbitrate_read(uint32_t address);
-void        nv3_mmio_arbitrate_write(uint32_t address, uint32_t value);
-
-// Read and Write functions for GPU subsystems
-// Remove the ones that aren't used here eventually, have all of htem for now
-uint32_t    nv3_pmc_read(uint32_t address);
-void        nv3_pmc_write(uint32_t address, uint32_t value);
-uint32_t    nv3_cio_read(uint32_t address);
-void        nv3_cio_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pbus_read(uint32_t address);
-void        nv3_pbus_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pfifo_read(uint32_t address);
-void        nv3_pfifo_write(uint32_t address, uint32_t value);
-uint32_t    nv3_prm_read(uint32_t address);
-void        nv3_prm_write(uint32_t address, uint32_t value);
-uint32_t    nv3_prmio_read(uint32_t address);
-void        nv3_prmio_write(uint32_t address, uint32_t value);
-uint32_t    nv3_ptimer_read(uint32_t address);
-void        nv3_ptimer_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pfb_read(uint32_t address);
-void        nv3_pfb_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pextdev_read(uint32_t address);
-void        nv3_pextdev_write(uint32_t address, uint32_t value);
-
-// Special consideration for straps
-#define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS)
-#define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x)
-
-uint32_t    nv3_prom_read(uint32_t address);
-void        nv3_prom_write(uint32_t address, uint32_t value);
-uint32_t    nv3_palt_read(uint32_t address);
-void        nv3_palt_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pme_read(uint32_t address);
-void        nv3_pme_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pgraph_read(uint32_t address);
-void        nv3_pgraph_write(uint32_t address, uint32_t value);
-
-// TODO: PGRAPH class registers
-
-uint32_t    nv3_prmcio_read(uint32_t address);
-void        nv3_prmcio_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pvideo_read(uint32_t address);
-void        nv3_pvideo_write(uint32_t address, uint32_t value);
-uint32_t    nv3_pramdac_read(uint32_t address);
-void        nv3_pramdac_write(uint32_t address, uint32_t value);
-uint32_t    nv3_vram_read(uint32_t address);
-void        nv3_vram_write(uint32_t address, uint32_t value);
-#define nv3_nvm_read nv3_vram_read
-#define nv3_nvm_write nv3_vram_write
-uint32_t    nv3_user_read(uint32_t address);
-void        nv3_user_write(uint32_t address, uint32_t value);
-#define nv3_object_submit_start nv3_user_read
-#define nv3_object_submit_end nv3_user_write
-uint32_t    nv3_pramin_read(uint32_t address);
-void        nv3_pramin_write(uint32_t address, uint32_t value);
-// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_*
-
-// GPU subsystems
-
-// NV3 PMC
-void        nv3_pmc_init();
-uint32_t    nv3_pmc_clear_interrupts();
-uint32_t    nv3_pmc_handle_interrupts(bool send_now);
-
-// NV3 PGRAPH
-void        nv3_pgraph_init();
-void        nv3_pgraph_vblank_start(svga_t* svga);
-
-// NV3 PFIFO
-void        nv3_pfifo_init();
-
-
-// NV3 PFB
-void        nv3_pfb_init();
-
-// NV3 PEXTDEV/PSTRAPS
-void        nv3_pextdev_init();
-
-// NV3 PBUS
-void        nv3_pbus_init();
-
-// NV3 PBUS RMA - Real Mode Access for VBIOS
-uint8_t     nv3_pbus_rma_read(uint16_t addr);
-void        nv3_pbus_rma_write(uint16_t addr, uint8_t val);
-
-// NV3 PRAMDAC
-void        nv3_pramdac_init();
-void        nv3_pramdac_set_vram_clock();
-void        nv3_pramdac_set_pixel_clock();
-void        nv3_pramdac_pixel_clock_poll(void* priv);
-void        nv3_pramdac_memory_clock_poll(void* priv);
-
-// NV3 PTIMER
-void        nv3_ptimer_init();
-void        nv3_ptimer_tick();
-
-// NV3 PVIDEO
-void        nv3_pvideo_init();
-
-// NV3 PMEDIA
-void        nv3_pmedia_init();
 #endif
\ No newline at end of file
diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h
index 7e8f6f7c1..db9474602 100644
--- a/src/include/86box/nv/vid_nv3.h
+++ b/src/include/86box/nv/vid_nv3.h
@@ -19,7 +19,6 @@
 // Last updated     2 December 2024
 
 // The GPU base structure
-extern nv3_t* nv3;
 extern const device_config_t nv3_config[];
 
 #define NV3_MMIO_SIZE                                   0x1000000       // Max MMIO size
@@ -31,6 +30,11 @@ extern const device_config_t nv3_config[];
 
 #define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT             1000            // The amount by which we have to ration out the memory clock because it's not fast enough...
                                                                         // Multiply by this value to get the real clock speed.
+// Default value for the boot information register.
+// Depends on the chip
+#define NV3_BOOT_REG_REV_A00    0x00030100
+#define NV3_BOOT_REG_REV_B00    0x00030110
+#define NV3_BOOT_REG_REV_C00    0x00030120
 
 // various vbioses for testing
 // Coming soon: MIROmagic Premium BIOS (when I get mine dumped)
@@ -318,14 +322,15 @@ extern const device_config_t nv3_config[];
 #define NV3_PGRAPH_CONTEXT_USER                         0x400194    // Current DMA context state, may rename
 #define NV3_PGRAPH_CONTEXT_CACHE(i)                     0x4001A0+(i*4)  // Context Cache
 #define NV3_PGRAPH_CONTEXT_CACHE_SIZE                   8
+// TODO: CLIP0/CLIP1 (8 clips min/max in 32bits)
 #define NV3_PGRAPH_ABS_UCLIP_XMIN                       0x40053C    // Clip X minimum
 #define NV3_PGRAPH_ABS_UCLIP_XMAX                       0x400540    // Clip X maximum
 #define NV3_PGRAPH_ABS_UCLIP_YMIN                       0x400544    // Clip Y minimum
 #define NV3_PGRAPH_ABS_UCLIP_YMAX                       0x400548    // Clip Y maximum
-#define NV3_PGRAPH_SRC_CANVAS_MIN                       0x400550    // Minimum Source Canvas for Blit, X,Y position
-#define NV3_PGRAPH_SRC_CANVAS_MAX                       0x400554    // Maximum Source Canvas for Blit, X,Y position
-#define NV3_PGRAPH_DST_CANVAS_MIN                       0x400558    // Minimum Destination Canvas for Blit, X,Y position
-#define NV3_PGRAPH_DST_CANVAS_MAX                       0x40055C    // Maximum Destination Canvas for Blit, X,Y position
+#define NV3_PGRAPH_SRC_CANVAS_MIN                       0x400550    // Minimum Source Canvas for Blit, Y=30:16, X=10:0
+#define NV3_PGRAPH_SRC_CANVAS_MAX                       0x400554    // Maximum Source Canvas for Blit, Y=30:16, X=10:0
+#define NV3_PGRAPH_DST_CANVAS_MIN                       0x400558    // Minimum Destination Canvas for Blit, Y=30:16, X=10:0
+#define NV3_PGRAPH_DST_CANVAS_MAX                       0x40055C    // Maximum Destination Canvas for Blit, Y=30:16, X=10:0
 #define NV3_PGRAPH_PATTERN_COLOR_0_0                    0x400600    
 #define NV3_PGRAPH_PATTERN_COLOR_0_1                    0x400604
 #define NV3_PGRAPH_PATTERN_COLOR_1_0                    0x400608    
@@ -575,5 +580,387 @@ extern const device_config_t nv3_config[];
 #define NV3_CRTC_REGISTER_RMA_MODE_MAX                  0x0F
 
 
+/* 
+    STRUCTURES FOR THE GPU START HERE
+*/
+
 //todo: pixel format
 
+// Master Control
+typedef struct nv3_pmc_s
+{
+    /* 
+    Holds chip manufacturing information at bootup.
+    Current specification (may change later): pre-packed for convenience
+
+    FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?)
+    31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001
+    little endian 00000000 00000011 00000001 00010001   = 0x00300111
+    */
+    int32_t boot;   
+    int32_t interrupt_status;          // Determines if interrupts are pending for specific subsystems.
+    int32_t interrupt_enable;   // Determines if interrupts are actually enabled.
+    int32_t enable;             // Determines which subsystems are enabled.
+
+} nv3_pmc_t;
+
+typedef struct nv3_pci_config_s
+{
+    uint8_t pci_regs[NV_PCI_NUM_CFG_REGS];  // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability)
+    bool    vbios_enabled;                  // is the vbios enabled?
+    uint8_t int_line;
+} nv3_pci_config_t;
+
+// add enums for eac
+// Chip configuration
+typedef struct nv3_straps_s
+{
+    uint32_t straps;
+} nv3_straps_t;
+
+// Framebuffer
+typedef struct nv3_pfb_s
+{
+    uint32_t boot;
+    uint32_t config_0;
+    uint32_t config_1;
+} nv3_pfb_t;
+
+#define NV3_RMA_NUM_REGS        4
+// Access the GPU from real-mode
+typedef struct nv3_pbus_rma_s
+{
+    uint32_t addr;                      // Address to RMA to
+    uint32_t data;                      // Data to send to MMIO
+    uint8_t mode;                       // the current state of the rma shifting engin
+    uint8_t rma_regs[NV3_RMA_NUM_REGS]; // The rma registers (saved)
+} nv3_pbus_rma_t;
+
+// Bus Configuration
+typedef struct nv3_pbus_s
+{
+    uint32_t interrupt_status;          // Interrupt status
+    uint32_t interrupt_enable;          // Interrupt enable
+    nv3_pbus_rma_t rma;
+} nv3_pbus_t;
+
+// Command submission to PGRAPH
+typedef struct nv_pfifo_s
+{
+    uint32_t interrupt_status;          // Interrupt status
+    uint32_t interrupt_enable;          // Interrupt enable
+} nv3_pfifo_t;
+
+// RAMDAC
+typedef struct nv3_pramdac_s
+{
+    // these should be uint8_t but C math is a lot better with this
+    uint32_t memory_clock_m;    // memory clock M-divider
+    uint32_t memory_clock_n;    // memory clock N-divider
+    uint32_t memory_clock_p;    // memory clock P-divider
+    uint32_t pixel_clock_m;     // pixel clock M-divider
+    uint32_t pixel_clock_n;     // pixel clock N-divider
+    uint32_t pixel_clock_p;     // pixel clock P-divider
+    uint32_t coeff_select;      // coefficient select
+
+    uint32_t general_control;   // general control register
+
+    // this could duplicate SVGA state but I tihnk it's more readable,
+    // we'll just modify both
+    uint32_t vserr_width;       // vertical sync error width
+    uint32_t vequ_end;          // vequ end (not sure what this is)
+    uint32_t vbblank_end;       // vbblank end (not sure what this is)
+    uint32_t vblank_end;        // vblank end
+    uint32_t vblank_start;      // vblank start
+    uint32_t vequ_start;        // vequ start (not sure what this is)
+    uint32_t vtotal;            // vertical total lines
+    uint32_t hsync_width;       // horizontal sync width
+    uint32_t hburst_start;      // horizontal burst signal start (in lines)
+    uint32_t hburst_end;        // horizontal burst signal end (in lines)
+    uint32_t hblank_start;      // horizontal blank start (in lines)
+    uint32_t hblank_end;        // horizontal blank end (in lines)
+    uint32_t htotal;            // horizontal total lines
+    uint32_t hequ_width;        // horizontal equ width (not sure what this is)
+    uint32_t hserr_width;       // horizontal sync error width
+} nv3_pramdac_t;
+
+// Graphics Subsystem
+typedef struct nv3_pgraph_s
+{
+    uint32_t interrupt_status_0;          // Interrupt status 0
+    uint32_t interrupt_enable_0;          // Interrupt enable 0 
+    uint32_t interrupt_status_1;          // Interrupt status 1
+    uint32_t interrupt_enable_1;          // Interrupt enable 1
+
+    uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE];  // DMA context cache 
+} nv3_pgraph_t;
+
+// GPU Manufacturing Configuration (again)
+// In the future this will be configurable
+typedef struct nv3_pextdev_s
+{
+    /*
+    // Disabled     33Mhz
+    // Enabled      66Mhz
+    bool bus_speed;
+    
+    // Disabled     No BIOS
+    // Enabled      BIOS
+    bool bios;
+
+    // RAM Type #1
+    // Disabled     16Mbit (2MB) module size
+    // Enabled      8Mbit (1MB) module size
+    bool ram_type_1;
+
+    // NEC Mode
+    bool nec_mode;
+
+    // Disabled     64-bit
+    // Enabled      128-bit
+    bool bus_width;
+
+    // Disabled     PCI
+    // Enabled      AGP
+    bool bus_type;
+
+    // Disabled     13500
+    // Enabled      14318180
+    bool crystal;
+
+    // TV Mode
+    // 0 - SECAM, 1 - NTSC, 2 - PAL, 3 - none
+    uint8_t tv_mode;
+
+    // AGP 2X mode
+    // Disabled     AGP 1X
+    // Enabled      AGP 2X
+    bool agp_is_2x; 
+    
+    bool unused;
+
+    // Overwrite enable
+    bool overwrite;
+
+    See defines in vid_nv3.h
+    */
+    uint32_t straps;
+    
+    // more ram type stuff here but not used?
+} nv3_pextdev_t;
+
+typedef struct nv3_ptimer_s
+{
+    uint32_t interrupt_status;          // PTIMER Interrupt status
+    uint32_t interrupt_enable;          // PTIMER Interrupt enable
+    uint32_t clock_numerator;           // PTIMER (tick?) numerator
+    uint32_t clock_denominator;         // PTIMER (tick?) denominator
+    uint64_t time;                      // time
+    uint32_t alarm;                     // The value of time when there should be an alarm
+} nv3_ptimer_t;
+
+// Graphics object hashtable
+typedef struct nv3_pramin_ramht_s
+{
+
+} nv3_pramin_ramht_t;
+
+// Anti-fuckup device
+typedef struct nv3_pramin_ramro_s
+{
+
+} nv3_pramin_ramro_t;
+
+// context for unused channels
+typedef struct nv3_pramin_ramfc_s
+{
+
+} nv3_pramin_ramfc_t;
+
+// ????? ram auxillary
+typedef struct nv_pramin_ramau_s
+{
+
+} nv3_pramin_ramau_t;
+
+typedef struct nv3_pramin_s
+{
+
+} nv3_pramin_t;
+
+typedef struct nv3_pvideo_s
+{
+    uint32_t interrupt_status;          // Interrupt status
+    uint32_t interrupt_enable;          // Interrupt enable
+} nv3_pvideo_t;
+
+typedef struct nv3_pme_s                // Mediaport
+{
+    uint32_t interrupt_status;
+    uint32_t interrupt_enable;
+} nv3_pme_t;
+
+typedef struct nv3_s
+{
+    nv_base_t nvbase;   // Base Nvidia structure
+    
+    // Config
+    nv3_straps_t straps;
+    nv3_pci_config_t pci_config;
+
+    // Subsystems
+    nv3_pmc_t pmc;              // Master Control
+    nv3_pfb_t pfb;              // Framebuffer/VRAM
+    nv3_pbus_t pbus;            // Bus Control
+    nv3_pfifo_t pfifo;          // FIFO for command submisison
+
+    nv3_pramdac_t pramdac;      // RAMDAC (CLUT etc)
+    nv3_pgraph_t pgraph;        // 2D/3D Graphics
+    nv3_pextdev_t pextdev;      // Chip configuration
+    nv3_ptimer_t ptimer;        // programmable interval timer
+    nv3_pramin_ramht_t ramht;   // hashtable for PGRAPH objects
+    nv3_pramin_ramro_t ramro;   // anti-fuckup mechanism for idiots who fucked up the FIFO submission
+    nv3_pramin_ramfc_t ramfc;   // context for unused channels
+    nv3_pramin_ramau_t ramau;   // auxillary weirdnes
+    nv3_pramin_t pramin;        // Ram for INput of DMA objects. Very important!
+    nv3_pvideo_t pvideo;        // Video overlay
+    nv3_pme_t pme;              // Mediaport - external MPEG decoder and video interface
+    //more here
+
+} nv3_t;
+
+// device objects
+extern nv3_t* nv3;
+
+// NV3 stuff
+
+// Device Core
+void*       nv3_init(const device_t *info);
+void        nv3_close(void* priv);
+void        nv3_speed_changed(void *priv);
+void        nv3_force_redraw(void* priv);
+
+// Memory Mapping
+void        nv3_update_mappings();
+uint8_t     nv3_mmio_read8(uint32_t addr, void* priv);                          // Read 8-bit MMIO
+uint16_t    nv3_mmio_read16(uint32_t addr, void* priv);                         // Read 16-bit MMIO
+uint32_t    nv3_mmio_read32(uint32_t addr, void* priv);                         // Read 32-bit MMIO
+void        nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv);            // Write 8-bit MMIO
+void        nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv);          // Write 16-bit MMIO
+void        nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv);          // Write 32-bit MMIO
+
+uint8_t     nv3_svga_in(uint16_t addr, void* priv);                             // Read SVGA compatibility registers
+void        nv3_svga_out(uint16_t addr, uint8_t val, void* priv);               // Write SVGA registers
+uint8_t     nv3_pci_read(int32_t func, int32_t addr, void* priv);               // Read PCI configuration registers
+void        nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers
+
+uint8_t     nv3_ramin_read8(uint32_t addr, void* priv);                          // Read 8-bit RAMIN
+uint16_t    nv3_ramin_read16(uint32_t addr, void* priv);                         // Read 16-bit RAMIN
+uint32_t    nv3_ramin_read32(uint32_t addr, void* priv);                         // Read 32-bit RAMIN
+void        nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv);            // Write 8-bit RAMIN
+void        nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv);          // Write 16-bit RAMIN
+void        nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv);          // Write 32-bit RAMIN
+
+// MMIO Arbitration
+// Determine where the hell in this mess our reads or writes are going
+uint32_t    nv3_mmio_arbitrate_read(uint32_t address);
+void        nv3_mmio_arbitrate_write(uint32_t address, uint32_t value);
+
+// Read and Write functions for GPU subsystems
+// Remove the ones that aren't used here eventually, have all of htem for now
+uint32_t    nv3_pmc_read(uint32_t address);
+void        nv3_pmc_write(uint32_t address, uint32_t value);
+uint32_t    nv3_cio_read(uint32_t address);
+void        nv3_cio_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pbus_read(uint32_t address);
+void        nv3_pbus_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pfifo_read(uint32_t address);
+void        nv3_pfifo_write(uint32_t address, uint32_t value);
+uint32_t    nv3_prm_read(uint32_t address);
+void        nv3_prm_write(uint32_t address, uint32_t value);
+uint32_t    nv3_prmio_read(uint32_t address);
+void        nv3_prmio_write(uint32_t address, uint32_t value);
+uint32_t    nv3_ptimer_read(uint32_t address);
+void        nv3_ptimer_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pfb_read(uint32_t address);
+void        nv3_pfb_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pextdev_read(uint32_t address);
+void        nv3_pextdev_write(uint32_t address, uint32_t value);
+
+// Special consideration for straps
+#define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS)
+#define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x)
+
+uint32_t    nv3_prom_read(uint32_t address);
+void        nv3_prom_write(uint32_t address, uint32_t value);
+uint32_t    nv3_palt_read(uint32_t address);
+void        nv3_palt_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pme_read(uint32_t address);
+void        nv3_pme_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pgraph_read(uint32_t address);
+void        nv3_pgraph_write(uint32_t address, uint32_t value);
+
+// TODO: PGRAPH class registers
+
+uint32_t    nv3_prmcio_read(uint32_t address);
+void        nv3_prmcio_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pvideo_read(uint32_t address);
+void        nv3_pvideo_write(uint32_t address, uint32_t value);
+uint32_t    nv3_pramdac_read(uint32_t address);
+void        nv3_pramdac_write(uint32_t address, uint32_t value);
+uint32_t    nv3_vram_read(uint32_t address);
+void        nv3_vram_write(uint32_t address, uint32_t value);
+#define nv3_nvm_read nv3_vram_read
+#define nv3_nvm_write nv3_vram_write
+uint32_t    nv3_user_read(uint32_t address);
+void        nv3_user_write(uint32_t address, uint32_t value);
+#define nv3_object_submit_start nv3_user_read
+#define nv3_object_submit_end nv3_user_write
+uint32_t    nv3_pramin_read(uint32_t address);
+void        nv3_pramin_write(uint32_t address, uint32_t value);
+// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_*
+
+// GPU subsystems
+
+// NV3 PMC
+void        nv3_pmc_init();
+uint32_t    nv3_pmc_clear_interrupts();
+uint32_t    nv3_pmc_handle_interrupts(bool send_now);
+
+// NV3 PGRAPH
+void        nv3_pgraph_init();
+void        nv3_pgraph_vblank_start(svga_t* svga);
+
+// NV3 PFIFO
+void        nv3_pfifo_init();
+
+
+// NV3 PFB
+void        nv3_pfb_init();
+
+// NV3 PEXTDEV/PSTRAPS
+void        nv3_pextdev_init();
+
+// NV3 PBUS
+void        nv3_pbus_init();
+
+// NV3 PBUS RMA - Real Mode Access for VBIOS
+uint8_t     nv3_pbus_rma_read(uint16_t addr);
+void        nv3_pbus_rma_write(uint16_t addr, uint8_t val);
+
+// NV3 PRAMDAC (Final presentation)
+void        nv3_pramdac_init();
+void        nv3_pramdac_set_vram_clock();
+void        nv3_pramdac_set_pixel_clock();
+void        nv3_pramdac_pixel_clock_poll(void* priv);
+void        nv3_pramdac_memory_clock_poll(void* priv);
+
+// NV3 PTIMER
+void        nv3_ptimer_init();
+void        nv3_ptimer_tick();
+
+// NV3 PVIDEO
+void        nv3_pvideo_init();
+
+// NV3 PMEDIA (Mediaport)
+void        nv3_pmedia_init();
diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c
index 48c0c93db..e74e6a93d 100644
--- a/src/video/nv/nv3/nv3_core_arbiter.c
+++ b/src/video/nv/nv3/nv3_core_arbiter.c
@@ -111,7 +111,6 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address)
         return 0x00;
     }
 
-    nv_log("NV3: MMIO read, 0x%08x <- 0x%08x\n", ret, address);
     return ret;
 }
 
@@ -171,8 +170,6 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value)
         nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address);
         return;
     }
-
-    nv_log("NV3: MMIO write, 0x%08x -> 0x%08x\n", value, address);
 }
 
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c
index b1696f950..9fa06d019 100644
--- a/src/video/nv/nv3/subsystems/nv3_pgraph.c
+++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c
@@ -47,6 +47,39 @@ nv_register_t pgraph_registers[] = {
     { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL },
     { NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL },
     { NV3_PGRAPH_INTR_EN_1, "PGRAPH Interrupt Enable 1", NULL, NULL },
+    { NV3_PGRAPH_CONTEXT_SWITCH, "PGRAPH DMA Context Switch", NULL, NULL },
+    { NV3_PGRAPH_CONTEXT_CONTROL, "PGRAPH DMA Context Control", NULL, NULL },
+    { NV3_PGRAPH_CONTEXT_USER, "PGRAPH DMA Context User", NULL, NULL },
+    //{ NV3_PGRAPH_CONTEXT_CACHE(0), "PGRAPH DMA Context Cache", NULL, NULL },
+    { NV3_PGRAPH_ABS_UCLIP_XMIN, "PGRAPH Absolute Clip Minimum X [17:0]", NULL, NULL },
+    { NV3_PGRAPH_ABS_UCLIP_XMAX, "PGRAPH Absolute Clip Maximum X [17:0]", NULL, NULL },
+    { NV3_PGRAPH_ABS_UCLIP_YMIN, "PGRAPH Absolute Clip Minimum Y [17:0]", NULL, NULL },
+    { NV3_PGRAPH_ABS_UCLIP_YMAX, "PGRAPH Absolute Clip Maximum Y [17:0]", NULL, NULL },
+    { NV3_PGRAPH_SRC_CANVAS_MIN, "PGRAPH Source Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_SRC_CANVAS_MAX, "PGRAPH Source Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_DST_CANVAS_MIN, "PGRAPH Destination Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_DST_CANVAS_MAX, "PGRAPH Destination Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_PATTERN_COLOR_0_0, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, },
+    { NV3_PGRAPH_PATTERN_COLOR_0_1, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, },
+    { NV3_PGRAPH_PATTERN_COLOR_1_0, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, },
+    { NV3_PGRAPH_PATTERN_COLOR_1_1, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, },
+    { NV3_PGRAPH_PATTERN_BITMAP_HIGH, "PGRAPH Pattern Bitmap (High 32bits)", NULL, NULL},
+    { NV3_PGRAPH_PATTERN_BITMAP_LOW, "PGRAPH Pattern Bitmap (Low 32bits)", NULL, NULL},
+    { NV3_PGRAPH_PATTERN_SHAPE, "PGRAPH Pattern Shape (1:0 - 0=8x8, 1=64x1, 2=1x64)", NULL, NULL},
+    { NV3_PGRAPH_ROP3, "PGRAPH Render Operation ROP3 (2^3 bits = 256 possible operations)", NULL, NULL},
+    { NV3_PGRAPH_PLANE_MASK, "PGRAPH Current Plane Mask (7:0)", NULL, NULL},
+    { NV3_PGRAPH_CHROMA_KEY, "PGRAPH Chroma Key (17:0) (Bit 30 = Alpha, 29:20 = Red, 19:10 = Green, 9:0 = Blue)", NULL, NULL},
+    { NV3_PGRAPH_NOTIFY, "PGRAPH Notifier (Wip...)", NULL, NULL},
+    { NV3_PGRAPH_CLIP0_MIN, "PGRAPH Clip0 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_CLIP0_MAX, "PGRAPH Clip0 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_CLIP1_MIN, "PGRAPH Clip1 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_CLIP1_MAX, "PGRAPH Clip1 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL},
+    { NV3_PGRAPH_FIFO_ACCESS, "PGRAPH - Can we access PFIFO?", NULL, NULL, },
+    { NV3_PGRAPH_STATUS, "PGRAPH Status", NULL, NULL },
+    { NV3_PGRAPH_TRAPPED_ADDRESS, "PGRAPH Trapped Address", NULL, NULL },
+    { NV3_PGRAPH_TRAPPED_DATA, "PGRAPH Trapped Data", NULL, NULL },
+    { NV3_PGRAPH_TRAPPED_INSTANCE, "PGRAPH Trapped Object Instance", NULL, NULL },
+
     { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value 
 };
 
@@ -95,6 +128,18 @@ uint32_t nv3_pgraph_read(uint32_t address)
         }
 
     }
+    else
+    {
+        /* Special exception for memory areas */
+        if (address >= NV3_PGRAPH_CONTEXT_CACHE(0)
+        && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE))
+        {
+            // Addresses should be aligned to 4 bytes.
+            uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0));
+
+            nv_log("NV3: PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]);
+        }
+    }
 
     return 0x0; 
 }
@@ -152,6 +197,19 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
             }
         }
     }
+    else
+    {
+        /* Special exception for memory areas */
+        if (address >= NV3_PGRAPH_CONTEXT_CACHE(0)
+        && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE))
+        {
+            // Addresses should be aligned to 4 bytes.
+            uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0));
+
+            nv_log("NV3: PGRAPH Context Cache Write (Entry=%04x Value=%04x)\n", entry, value);
+            nv3->pgraph.context_cache[entry] = value;
+        }
+    }
 }
 
 // Fire a VALID Pgraph interrupt: num is the bit# of the interrupt in the GPU subsystem INTR_EN register.