mirror of
https://github.com/86Box/86Box.git
synced 2026-02-23 01:48:21 -07:00
Merge branch 'master' into experimental
This commit is contained in:
Melissa Goad
@@ -401,828 +401,6 @@ int checkio(int port)
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||||
return d&(1<<(port&7));
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}
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||||
|
||||
int rep386(int fv)
|
||||
{
|
||||
uint8_t temp;
|
||||
uint32_t c;
|
||||
uint8_t temp2;
|
||||
uint16_t tempw,tempw2,of;
|
||||
uint32_t ipc = cpu_state.oldpc;
|
||||
uint32_t rep32 = cpu_state.op32;
|
||||
uint32_t templ,templ2;
|
||||
int tempz;
|
||||
int tempi;
|
||||
/*Limit the amount of time the instruction is uninterruptable for, so
|
||||
that high frequency timers still work okay. This amount is different
|
||||
for interpreter and recompiler*/
|
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int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100);
|
||||
int reads = 0, reads_l = 0, writes = 0, writes_l = 0, total_cycles = 0;
|
||||
|
||||
if (trap)
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/
|
||||
|
||||
cpu_reps++;
|
||||
|
||||
flags_rebuild();
|
||||
of = flags;
|
||||
startrep:
|
||||
temp=opcode2=readmemb(cs,cpu_state.pc); cpu_state.pc++;
|
||||
c=(rep32&0x200)?ECX:CX;
|
||||
switch (temp|rep32)
|
||||
{
|
||||
case 0xC3: case 0x1C3: case 0x2C3: case 0x3C3:
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||||
cpu_state.pc--;
|
||||
break;
|
||||
case 0x08:
|
||||
cpu_state.pc=ipc+1;
|
||||
break;
|
||||
case 0x26: case 0x126: case 0x226: case 0x326: /*ES:*/
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||||
cpu_state.ea_seg = &_es;
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||||
PREFETCH_PREFIX();
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goto startrep;
|
||||
break;
|
||||
case 0x2E: case 0x12E: case 0x22E: case 0x32E: /*CS:*/
|
||||
cpu_state.ea_seg = &_cs;
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||||
PREFETCH_PREFIX();
|
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goto startrep;
|
||||
case 0x36: case 0x136: case 0x236: case 0x336: /*SS:*/
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||||
cpu_state.ea_seg = &_ss;
|
||||
PREFETCH_PREFIX();
|
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goto startrep;
|
||||
case 0x3E: case 0x13E: case 0x23E: case 0x33E: /*DS:*/
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||||
cpu_state.ea_seg = &_ds;
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||||
PREFETCH_PREFIX();
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||||
goto startrep;
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case 0x64: case 0x164: case 0x264: case 0x364: /*FS:*/
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cpu_state.ea_seg = &_fs;
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PREFETCH_PREFIX();
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goto startrep;
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case 0x65: case 0x165: case 0x265: case 0x365: /*GS:*/
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cpu_state.ea_seg = &_gs;
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PREFETCH_PREFIX();
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goto startrep;
|
||||
case 0x66: case 0x166: case 0x266: case 0x366: /*Data size prefix*/
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rep32 = (rep32 & 0x200) | ((use32 ^ 0x100) & 0x100);
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PREFETCH_PREFIX();
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goto startrep;
|
||||
case 0x67: case 0x167: case 0x267: case 0x367: /*Address size prefix*/
|
||||
rep32 = (rep32 & 0x100) | ((use32 ^ 0x200) & 0x200);
|
||||
PREFETCH_PREFIX();
|
||||
goto startrep;
|
||||
case 0x6C: case 0x16C: /*REP INSB*/
|
||||
if (c>0)
|
||||
{
|
||||
checkio_perm(DX);
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||||
temp2=inb(DX);
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||||
writememb(es,DI,temp2);
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||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
cycles-=15;
|
||||
reads++; writes++; total_cycles += 15;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x26C: case 0x36C: /*REP INSB*/
|
||||
if (c>0)
|
||||
{
|
||||
checkio_perm(DX);
|
||||
temp2=inb(DX);
|
||||
writememb(es,EDI,temp2);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
cycles-=15;
|
||||
reads++; writes++; total_cycles += 15;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x6D: /*REP INSW*/
|
||||
if (c>0)
|
||||
{
|
||||
tempw=inw(DX);
|
||||
writememw(es,DI,tempw);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
cycles-=15;
|
||||
reads++; writes++; total_cycles += 15;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x16D: /*REP INSL*/
|
||||
if (c>0)
|
||||
{
|
||||
templ=inl(DX);
|
||||
writememl(es,DI,templ);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
cycles-=15;
|
||||
reads_l++; writes_l++; total_cycles += 15;
|
||||
}
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||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x26D: /*REP INSW*/
|
||||
if (c>0)
|
||||
{
|
||||
tempw=inw(DX);
|
||||
writememw(es,EDI,tempw);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
cycles-=15;
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||||
reads++; writes++; total_cycles += 15;
|
||||
}
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||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x36D: /*REP INSL*/
|
||||
if (c>0)
|
||||
{
|
||||
templ=inl(DX);
|
||||
writememl(es,EDI,templ);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
cycles-=15;
|
||||
reads_l++; writes_l++; total_cycles += 15;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x6E: case 0x16E: /*REP OUTSB*/
|
||||
if (c>0)
|
||||
{
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
checkio_perm(DX);
|
||||
outb(DX,temp2);
|
||||
if (flags&D_FLAG) SI--;
|
||||
else SI++;
|
||||
c--;
|
||||
cycles-=14;
|
||||
reads++; writes++; total_cycles += 14;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x26E: case 0x36E: /*REP OUTSB*/
|
||||
if (c>0)
|
||||
{
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
checkio_perm(DX);
|
||||
outb(DX,temp2);
|
||||
if (flags&D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
c--;
|
||||
cycles-=14;
|
||||
reads++; writes++; total_cycles += 14;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x6F: /*REP OUTSW*/
|
||||
if (c>0)
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
outw(DX,tempw);
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||||
if (flags&D_FLAG) SI-=2;
|
||||
else SI+=2;
|
||||
c--;
|
||||
cycles-=14;
|
||||
reads++; writes++; total_cycles += 14;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x16F: /*REP OUTSL*/
|
||||
if (c > 0)
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI);
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||||
if (cpu_state.abrt) break;
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||||
outl(DX, templ);
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||||
if (flags & D_FLAG) SI -= 4;
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||||
else SI += 4;
|
||||
c--;
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||||
cycles -= 14;
|
||||
reads_l++; writes_l++; total_cycles += 14;
|
||||
}
|
||||
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
|
||||
else firstrepcycle = 1;
|
||||
break;
|
||||
case 0x26F: /*REP OUTSW*/
|
||||
if (c>0)
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
outw(DX,tempw);
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
else ESI+=2;
|
||||
c--;
|
||||
cycles-=14;
|
||||
reads++; writes++; total_cycles += 14;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x36F: /*REP OUTSL*/
|
||||
if (c > 0)
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
outl(DX, templ);
|
||||
if (flags & D_FLAG) ESI -= 4;
|
||||
else ESI += 4;
|
||||
c--;
|
||||
cycles -= 14;
|
||||
reads_l++; writes_l++; total_cycles += 14;
|
||||
}
|
||||
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
|
||||
else firstrepcycle = 1;
|
||||
break;
|
||||
case 0x90: case 0x190: /*REP NOP*/
|
||||
case 0x290: case 0x390:
|
||||
break;
|
||||
case 0xA4: case 0x1A4: /*REP MOVSB*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI);
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
|
||||
writememb(es,DI,temp2); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
c--;
|
||||
cycles-=(is486)?3:4;
|
||||
ins++;
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2A4: case 0x3A4: /*REP MOVSB*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI);
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
|
||||
writememb(es,EDI,temp2); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
c--;
|
||||
cycles-=(is486)?3:4;
|
||||
ins++;
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xA5: /*REP MOVSW*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+1);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
|
||||
writememw(es,DI,tempw); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { DI-=2; SI-=2; }
|
||||
else { DI+=2; SI+=2; }
|
||||
c--;
|
||||
cycles-=(is486)?3:4;
|
||||
ins++;
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1A5: /*REP MOVSL*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+3);
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
|
||||
writememl(es,DI,templ); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { DI-=4; SI-=4; }
|
||||
else { DI+=4; SI+=4; }
|
||||
c--;
|
||||
cycles-=(is486)?3:4;
|
||||
ins++;
|
||||
reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2A5: /*REP MOVSW*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+1);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
|
||||
writememw(es,EDI,tempw); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
else { EDI+=2; ESI+=2; }
|
||||
c--;
|
||||
cycles-=(is486)?3:4;
|
||||
ins++;
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3A5: /*REP MOVSL*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+3);
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
|
||||
writememl(es,EDI,templ); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
|
||||
else { EDI+=4; ESI+=4; }
|
||||
c--;
|
||||
cycles-=(is486)?3:4;
|
||||
ins++;
|
||||
reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xA6: case 0x1A6: /*REP CMPSB*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
temp = readmemb(cpu_state.ea_seg->base, SI);
|
||||
temp2=readmemb(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub8(temp,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2A6: case 0x3A6: /*REP CMPSB*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
temp = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
temp2=readmemb(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub8(temp,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xA7: /*REP CMPSW*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI);
|
||||
tempw2=readmemw(es,DI);
|
||||
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI-=2; SI-=2; }
|
||||
else { DI+=2; SI+=2; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub16(tempw,tempw2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1A7: /*REP CMPSL*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI);
|
||||
templ2=readmeml(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI-=4; SI-=4; }
|
||||
else { DI+=4; SI+=4; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads_l += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub32(templ,templ2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2A7: /*REP CMPSW*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
tempw2=readmemw(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
else { EDI+=2; ESI+=2; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub16(tempw,tempw2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3A7: /*REP CMPSL*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
templ2=readmeml(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
|
||||
else { EDI+=4; ESI+=4; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads_l += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub32(templ,templ2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
|
||||
case 0xAA: case 0x1AA: /*REP STOSB*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI);
|
||||
writememb(es,DI,AL);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AA: case 0x3AA: /*REP STOSB*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI);
|
||||
writememb(es,EDI,AL);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAB: /*REP STOSW*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+1);
|
||||
writememw(es,DI,AX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AB: /*REP STOSW*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+1);
|
||||
writememw(es,EDI,AX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1AB: /*REP STOSL*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+3);
|
||||
writememl(es,DI,EAX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes_l++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3AB: /*REP STOSL*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+3);
|
||||
writememl(es,EDI,EAX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes_l++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAC: case 0x1AC: /*REP LODSB*/
|
||||
if (c>0)
|
||||
{
|
||||
AL = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI--;
|
||||
else SI++;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AC: case 0x3AC: /*REP LODSB*/
|
||||
if (c>0)
|
||||
{
|
||||
AL = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAD: /*REP LODSW*/
|
||||
if (c>0)
|
||||
{
|
||||
AX = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI-=2;
|
||||
else SI+=2;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1AD: /*REP LODSL*/
|
||||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI-=4;
|
||||
else SI+=4;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads_l++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AD: /*REP LODSW*/
|
||||
if (c>0)
|
||||
{
|
||||
AX = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
else ESI+=2;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3AD: /*REP LODSL*/
|
||||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI-=4;
|
||||
else ESI+=4;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads_l++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAE: case 0x1AE: /*REP SCASB*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
temp2=readmemb(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub8(AL,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AE: case 0x3AE: /*REP SCASB*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
temp2=readmemb(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub8(AL,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAF: /*REP SCASW*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
tempw=readmemw(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub16(AX,tempw);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1AF: /*REP SCASL*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
templ=readmeml(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub32(EAX,templ);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads_l++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AF: /*REP SCASW*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
tempw=readmemw(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub16(AX,tempw);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3AF: /*REP SCASL*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
templ=readmeml(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub32(EAX,templ);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads_l++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
cpu_state.pc = ipc+1;
|
||||
break;
|
||||
}
|
||||
if (rep32&0x200) ECX=c;
|
||||
else CX=c;
|
||||
CPU_BLOCK_END();
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, reads_l, writes, writes_l, 0);
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
int xout=0;
|
||||
|
||||
|
||||
|
||||
@@ -1410,4 +1410,186 @@ OpFn OP_TABLE(386)[1024] =
|
||||
/*d0*/ opD0_a32, opD1_l_a32, opD2_a32, opD3_l_a32, opAAM, opAAD, opSETALC, opXLAT_a32, opESCAPE_d8_a32,opESCAPE_d9_a32,opESCAPE_da_a32,opESCAPE_db_a32,opESCAPE_dc_a32,opESCAPE_dd_a32,opESCAPE_de_a32,opESCAPE_df_a32,
|
||||
/*e0*/ opLOOPNE_l, opLOOPE_l, opLOOP_l, opJECXZ, opIN_AL_imm, opIN_EAX_imm, opOUT_AL_imm, opOUT_EAX_imm, opCALL_r32, opJMP_r32, opJMP_far_a32, opJMP_r8, opIN_AL_DX, opIN_EAX_DX, opOUT_AL_DX, opOUT_EAX_DX,
|
||||
/*f0*/ opLOCK, opINT1, opREPNE, opREPE, opHLT, opCMC, opF6_a32, opF7_l_a32, opCLC, opSTC, opCLI, opSTI, opCLD, opSTD, opINCDEC_b_a32, opFF_l_a32,
|
||||
};
|
||||
|
||||
OpFn OP_TABLE(REPE)[1024] =
|
||||
{
|
||||
/*16-bit data, 16-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPE_w_a16,0, 0, 0, 0, 0, 0, 0, opCS_REPE_w_a16,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPE_w_a16,0, 0, 0, 0, 0, 0, 0, opDS_REPE_w_a16,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPE_w_a16,opGS_REPE_w_a16,op_66_REPE, op_67_REPE, 0, 0, 0, 0, opREP_INSB_a16, opREP_INSW_a16, opREP_OUTSB_a16,opREP_OUTSW_a16,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a16,opREP_MOVSW_a16,opREP_CMPSB_a16_E,opREP_CMPSW_a16_E,0, 0, opREP_STOSB_a16,opREP_STOSW_a16,opREP_LODSB_a16,opREP_LODSW_a16,opREP_SCASB_a16_E,opREP_SCASW_a16_E,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*32-bit data, 16-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPE_l_a16,0, 0, 0, 0, 0, 0, 0, opCS_REPE_l_a16,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPE_l_a16,0, 0, 0, 0, 0, 0, 0, opDS_REPE_l_a16,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPE_l_a16,opGS_REPE_l_a16,op_66_REPE, op_67_REPE, 0, 0, 0, 0, opREP_INSB_a16, opREP_INSL_a16, opREP_OUTSB_a16,opREP_OUTSL_a16,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a16,opREP_MOVSL_a16,opREP_CMPSB_a16_E,opREP_CMPSL_a16_E,0, 0, opREP_STOSB_a16,opREP_STOSL_a16,opREP_LODSB_a16,opREP_LODSL_a16,opREP_SCASB_a16_E,opREP_SCASL_a16_E,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*16-bit data, 32-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPE_w_a32,0, 0, 0, 0, 0, 0, 0, opCS_REPE_w_a32,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPE_w_a32,0, 0, 0, 0, 0, 0, 0, opDS_REPE_w_a32,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPE_w_a32,opGS_REPE_w_a32,op_66_REPE, op_67_REPE, 0, 0, 0, 0, opREP_INSB_a32, opREP_INSW_a32, opREP_OUTSB_a32,opREP_OUTSW_a32,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a32,opREP_MOVSW_a32,opREP_CMPSB_a32_E,opREP_CMPSW_a32_E,0, 0, opREP_STOSB_a32,opREP_STOSW_a32,opREP_LODSB_a32,opREP_LODSW_a32,opREP_SCASB_a32_E,opREP_SCASW_a32_E,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*32-bit data, 32-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPE_l_a32,0, 0, 0, 0, 0, 0, 0, opCS_REPE_l_a32,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPE_l_a32,0, 0, 0, 0, 0, 0, 0, opDS_REPE_l_a32,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPE_l_a32,opGS_REPE_l_a32,op_66_REPE, op_67_REPE, 0, 0, 0, 0, opREP_INSB_a32, opREP_INSL_a32, opREP_OUTSB_a32,opREP_OUTSL_a32,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a32,opREP_MOVSL_a32,opREP_CMPSB_a32_E,opREP_CMPSL_a32_E,0, 0, opREP_STOSB_a32,opREP_STOSL_a32,opREP_LODSB_a32,opREP_LODSL_a32,opREP_SCASB_a32_E,opREP_SCASL_a32_E,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
};
|
||||
|
||||
OpFn OP_TABLE(REPNE)[1024] =
|
||||
{
|
||||
/*16-bit data, 16-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPNE_w_a16,0, 0, 0, 0, 0, 0, 0, opCS_REPNE_w_a16,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPNE_w_a16,0, 0, 0, 0, 0, 0, 0, opDS_REPNE_w_a16,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPNE_w_a16,opGS_REPNE_w_a16,op_66_REPNE, op_67_REPNE, 0, 0, 0, 0, opREP_INSB_a16, opREP_INSW_a16, opREP_OUTSB_a16,opREP_OUTSW_a16,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a16,opREP_MOVSW_a16,opREP_CMPSB_a16_NE,opREP_CMPSW_a16_NE,0, 0, opREP_STOSB_a16,opREP_STOSW_a16,opREP_LODSB_a16,opREP_LODSW_a16,opREP_SCASB_a16_NE,opREP_SCASW_a16_NE,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*32-bit data, 16-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPNE_l_a16,0, 0, 0, 0, 0, 0, 0, opCS_REPNE_l_a16,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPNE_l_a16,0, 0, 0, 0, 0, 0, 0, opDS_REPNE_l_a16,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPNE_l_a16,opGS_REPNE_l_a16,op_66_REPNE, op_67_REPNE, 0, 0, 0, 0, opREP_INSB_a16, opREP_INSL_a16, opREP_OUTSB_a16,opREP_OUTSL_a16,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a16,opREP_MOVSL_a16,opREP_CMPSB_a16_NE,opREP_CMPSL_a16_NE,0, 0, opREP_STOSB_a16,opREP_STOSL_a16,opREP_LODSB_a16,opREP_LODSL_a16,opREP_SCASB_a16_NE,opREP_SCASL_a16_NE,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*16-bit data, 32-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPNE_w_a32,0, 0, 0, 0, 0, 0, 0, opCS_REPNE_w_a32,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPNE_w_a32,0, 0, 0, 0, 0, 0, 0, opDS_REPNE_w_a32,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPNE_w_a32,opGS_REPNE_w_a32,op_66_REPNE, op_67_REPNE, 0, 0, 0, 0, opREP_INSB_a32, opREP_INSW_a32, opREP_OUTSB_a32,opREP_OUTSW_a32,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a32,opREP_MOVSW_a32,opREP_CMPSB_a32_NE,opREP_CMPSW_a32_NE,0, 0, opREP_STOSB_a32,opREP_STOSW_a32,opREP_LODSB_a32,opREP_LODSW_a32,opREP_SCASB_a32_NE,opREP_SCASW_a32_NE,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*32-bit data, 32-bit addr*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*10*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*20*/ 0, 0, 0, 0, 0, 0, opES_REPNE_l_a32,0, 0, 0, 0, 0, 0, 0, opCS_REPNE_l_a32,0,
|
||||
/*30*/ 0, 0, 0, 0, 0, 0, opSS_REPNE_l_a32,0, 0, 0, 0, 0, 0, 0, opDS_REPNE_l_a32,0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*50*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*60*/ 0, 0, 0, 0, opFS_REPNE_l_a32,opGS_REPNE_l_a32,op_66_REPNE, op_67_REPNE, 0, 0, 0, 0, opREP_INSB_a32, opREP_INSL_a32, opREP_OUTSB_a32,opREP_OUTSL_a32,
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*90*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*a0*/ 0, 0, 0, 0, opREP_MOVSB_a32,opREP_MOVSL_a32,opREP_CMPSB_a32_NE,opREP_CMPSL_a32_NE,0, 0, opREP_STOSB_a32,opREP_STOSL_a32,opREP_LODSB_a32,opREP_LODSL_a32,opREP_SCASB_a32_NE,opREP_SCASL_a32_NE,
|
||||
/*b0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*c0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*d0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*e0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*f0*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
};
|
||||
|
||||
@@ -1,4 +1,8 @@
|
||||
#ifndef _CODEGEN_H_
|
||||
#define _CODEGEN_H_
|
||||
|
||||
#include "../mem.h"
|
||||
#include "x86_ops.h"
|
||||
|
||||
#ifdef __amd64__
|
||||
#include "codegen_x86-64.h"
|
||||
@@ -35,10 +39,10 @@
|
||||
|
||||
typedef struct codeblock_t
|
||||
{
|
||||
uint64_t page_mask, page_mask2;
|
||||
uint64_t page_mask, page_mask2;
|
||||
uint64_t *dirty_mask, *dirty_mask2;
|
||||
uint64_t cmp;
|
||||
|
||||
uint64_t cmp;
|
||||
|
||||
/*Previous and next pointers, for the codeblock list associated with
|
||||
each physical page. Two sets of pointers, as a codeblock can be
|
||||
present in two pages.*/
|
||||
@@ -59,7 +63,7 @@ typedef struct codeblock_t
|
||||
uint32_t _cs;
|
||||
uint32_t endpc;
|
||||
uint32_t phys, phys_2;
|
||||
uint32_t status;
|
||||
uint32_t status;
|
||||
uint32_t flags;
|
||||
|
||||
uint8_t data[2048];
|
||||
@@ -70,7 +74,7 @@ typedef struct codeblock_t
|
||||
/*Code block is always entered with the same FPU top-of-stack*/
|
||||
#define CODEBLOCK_STATIC_TOP 2
|
||||
|
||||
static __inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
|
||||
static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
|
||||
{
|
||||
codeblock_t *block = pages[phys >> 12].head;
|
||||
uint64_t a = _cs | ((uint64_t)phys << 32);
|
||||
@@ -88,7 +92,7 @@ static __inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
|
||||
return block;
|
||||
}
|
||||
|
||||
static __inline void codeblock_tree_add(codeblock_t *new_block)
|
||||
static inline void codeblock_tree_add(codeblock_t *new_block)
|
||||
{
|
||||
codeblock_t *block = pages[new_block->phys >> 12].head;
|
||||
uint64_t a = new_block->_cs | ((uint64_t)new_block->phys << 32);
|
||||
@@ -122,7 +126,7 @@ static __inline void codeblock_tree_add(codeblock_t *new_block)
|
||||
}
|
||||
}
|
||||
|
||||
static __inline void codeblock_tree_delete(codeblock_t *block)
|
||||
static inline void codeblock_tree_delete(codeblock_t *block)
|
||||
{
|
||||
codeblock_t *parent = block->parent;
|
||||
|
||||
@@ -252,6 +256,7 @@ void codegen_block_init(uint32_t phys_addr);
|
||||
void codegen_block_remove();
|
||||
void codegen_block_start_recompile(codeblock_t *block);
|
||||
void codegen_block_end_recompile(codeblock_t *block);
|
||||
void codegen_block_end();
|
||||
void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc);
|
||||
void codegen_generate_seg_restore();
|
||||
void codegen_set_op32();
|
||||
@@ -300,7 +305,7 @@ extern int block_pos;
|
||||
|
||||
#define CPU_BLOCK_END() cpu_block_end = 1
|
||||
|
||||
static __inline void addbyte(uint8_t val)
|
||||
static inline void addbyte(uint8_t val)
|
||||
{
|
||||
codeblock[block_current].data[block_pos++] = val;
|
||||
if (block_pos >= BLOCK_MAX)
|
||||
@@ -309,10 +314,10 @@ static __inline void addbyte(uint8_t val)
|
||||
}
|
||||
}
|
||||
|
||||
static __inline void addword(uint16_t val)
|
||||
static inline void addword(uint16_t val)
|
||||
{
|
||||
uint16_t *p = (uint16_t *)&codeblock[block_current].data[block_pos];
|
||||
*p = val;
|
||||
uint16_t *p = (uint16_t *) &codeblock[block_current].data[block_pos];
|
||||
*p = val;
|
||||
block_pos += 2;
|
||||
if (block_pos >= BLOCK_MAX)
|
||||
{
|
||||
@@ -320,10 +325,10 @@ static __inline void addword(uint16_t val)
|
||||
}
|
||||
}
|
||||
|
||||
static __inline void addlong(uint32_t val)
|
||||
static inline void addlong(uint32_t val)
|
||||
{
|
||||
uint32_t *p = (uint32_t *)&codeblock[block_current].data[block_pos];
|
||||
*p = val;
|
||||
uint32_t *p = (uint32_t *) &codeblock[block_current].data[block_pos];
|
||||
*p = val;
|
||||
block_pos += 4;
|
||||
if (block_pos >= BLOCK_MAX)
|
||||
{
|
||||
@@ -331,10 +336,10 @@ static __inline void addlong(uint32_t val)
|
||||
}
|
||||
}
|
||||
|
||||
static __inline void addquad(uint64_t val)
|
||||
static inline void addquad(uint64_t val)
|
||||
{
|
||||
uint64_t *p = (uint64_t *)&codeblock[block_current].data[block_pos];
|
||||
*p = val;
|
||||
uint64_t *p = (uint64_t *) &codeblock[block_current].data[block_pos];
|
||||
*p = val;
|
||||
block_pos += 8;
|
||||
if (block_pos >= BLOCK_MAX)
|
||||
{
|
||||
@@ -360,3 +365,5 @@ extern int codegen_fpu_loaded_iq[8];
|
||||
extern int codegen_reg_loaded[8];
|
||||
|
||||
extern int codegen_in_recompile;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -496,3 +496,97 @@ RecompOpFn recomp_opcodes_df[512] =
|
||||
/*e0*/ ropFSTSW_AX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
};
|
||||
|
||||
RecompOpFn recomp_opcodes_REPE[512] =
|
||||
{
|
||||
/*16-bit data*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*32-bit data*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
};
|
||||
|
||||
RecompOpFn recomp_opcodes_REPNE[512] =
|
||||
{
|
||||
/*16-bit data*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*32-bit data*/
|
||||
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
|
||||
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
|
||||
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
};
|
||||
|
||||
@@ -1,3 +1,8 @@
|
||||
#ifndef _CODEGEN_OPS_H_
|
||||
#define _CODEGEN_OPS_H_
|
||||
|
||||
#include "codegen.h"
|
||||
|
||||
typedef uint32_t (*RecompOpFn)(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block);
|
||||
|
||||
extern RecompOpFn recomp_opcodes[512];
|
||||
@@ -10,6 +15,8 @@ extern RecompOpFn recomp_opcodes_dc[512];
|
||||
extern RecompOpFn recomp_opcodes_dd[512];
|
||||
extern RecompOpFn recomp_opcodes_de[512];
|
||||
extern RecompOpFn recomp_opcodes_df[512];
|
||||
RecompOpFn recomp_opcodes_REPE[512];
|
||||
RecompOpFn recomp_opcodes_REPNE[512];
|
||||
|
||||
#define REG_EAX 0
|
||||
#define REG_ECX 1
|
||||
@@ -35,3 +42,5 @@ extern RecompOpFn recomp_opcodes_df[512];
|
||||
#define REG_DH 6
|
||||
#define REG_BL 3
|
||||
#define REG_BH 7
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,10 +1,12 @@
|
||||
#include "../ibm.h"
|
||||
#include "../mem.h"
|
||||
#include "cpu.h"
|
||||
#include "x86.h"
|
||||
#include "x86_ops.h"
|
||||
#include "x87.h"
|
||||
#include "../mem.h"
|
||||
#include "codegen.h"
|
||||
#include "codegen_ops.h"
|
||||
#include "codegen_timing_common.h"
|
||||
|
||||
#define CYCLES(c) (int *)c
|
||||
#define CYCLES2(c16, c32) (int *)((-1 & ~0xffff) | c16 | (c32 << 8))
|
||||
@@ -247,14 +249,27 @@ static int *opcode_timings_8x[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
static int *opcode_timings_8x_mod3[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
static int *opcode_timings_81[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
static int *opcode_timings_81_mod3[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
|
||||
static int timing_count;
|
||||
static uint8_t last_prefix;
|
||||
static uint32_t regmask_modified;
|
||||
|
||||
static __inline int COUNT(int *c, int op_32)
|
||||
static inline int COUNT(int *c, int op_32)
|
||||
{
|
||||
if ((uintptr_t)c <= 10000)
|
||||
return (int)c;
|
||||
return (int)(uintptr_t)c;
|
||||
if (((uintptr_t)c & ~0xffff) == (-1 & ~0xffff))
|
||||
{
|
||||
if (op_32 & 0x100)
|
||||
@@ -266,6 +281,7 @@ static __inline int COUNT(int *c, int op_32)
|
||||
|
||||
void codegen_timing_486_block_start()
|
||||
{
|
||||
regmask_modified = 0;
|
||||
}
|
||||
|
||||
void codegen_timing_486_start()
|
||||
@@ -283,82 +299,107 @@ void codegen_timing_486_prefix(uint8_t prefix, uint32_t fetchdat)
|
||||
void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
int **timings;
|
||||
uint64_t *deps;
|
||||
int mod3 = ((fetchdat & 0xc0) == 0xc0);
|
||||
|
||||
int bit8 = !(opcode & 1);
|
||||
|
||||
switch (last_prefix)
|
||||
{
|
||||
case 0x0f:
|
||||
timings = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
|
||||
deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
|
||||
break;
|
||||
|
||||
case 0xd8:
|
||||
timings = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
|
||||
deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xd9:
|
||||
timings = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
|
||||
deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
|
||||
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xda:
|
||||
timings = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
|
||||
deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdb:
|
||||
timings = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
|
||||
deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
|
||||
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdc:
|
||||
timings = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
|
||||
deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdd:
|
||||
timings = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
|
||||
deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xde:
|
||||
timings = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
|
||||
deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdf:
|
||||
timings = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
|
||||
deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
|
||||
default:
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x80: case 0x81: case 0x82: case 0x83:
|
||||
timings = mod3 ? opcode_timings_mod3 : opcode_timings_8x;
|
||||
if (!mod3)
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
case 0x80: case 0x82: case 0x83:
|
||||
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
|
||||
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0x81:
|
||||
timings = mod3 ? opcode_timings_81_mod3 : opcode_timings_81;
|
||||
deps = mod3 ? opcode_deps_81_mod3 : opcode_deps_81;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
case 0xc0: case 0xc1: case 0xd0: case 0xd1: case 0xd2: case 0xd3:
|
||||
timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
|
||||
deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
case 0xf6:
|
||||
timings = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
|
||||
deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0xf7:
|
||||
timings = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
|
||||
deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0xff:
|
||||
timings = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
|
||||
deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
default:
|
||||
timings = mod3 ? opcode_timings_mod3 : opcode_timings;
|
||||
deps = mod3 ? opcode_deps_mod3 : opcode_deps;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
timing_count += COUNT(timings[opcode], op_32);
|
||||
if (regmask_modified & get_addr_regmask(deps[opcode], fetchdat, op_32))
|
||||
timing_count++; /*AGI stall*/
|
||||
codegen_block_cycles += timing_count;
|
||||
|
||||
regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8);
|
||||
}
|
||||
|
||||
void codegen_timing_486_block_end()
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
- X/Y pairing
|
||||
- FPU/FXCH pairing
|
||||
- Prefix decode delay
|
||||
- AGI stalls
|
||||
Elements not taken into account :
|
||||
- Branch prediction (beyond most simplistic approximation)
|
||||
- FPU queue
|
||||
@@ -15,6 +16,7 @@
|
||||
#include "x87.h"
|
||||
#include "../mem.h"
|
||||
#include "codegen.h"
|
||||
#include "codegen_timing_common.h"
|
||||
|
||||
/*Instruction has different execution time for 16 and 32 bit data. Does not pair */
|
||||
#define CYCLES_HAS_MULTI (1 << 31)
|
||||
@@ -33,11 +35,6 @@
|
||||
|
||||
#define CYCLES_MASK ((1 << 7) - 1)
|
||||
|
||||
/*Instruction is MMX shift or pack/unpack instruction*/
|
||||
#define MMX_SHIFTPACK (1 << 7)
|
||||
/*Instruction is MMX multiply instruction*/
|
||||
#define MMX_MULTIPLY (1 << 8)
|
||||
|
||||
/*Instruction does not pair*/
|
||||
#define PAIR_NP (0 << 29)
|
||||
/*Instruction pairs in X pipe only*/
|
||||
@@ -49,35 +46,6 @@
|
||||
|
||||
#define PAIR_MASK (3 << 29)
|
||||
|
||||
/*Instruction has input dependency on register in REG field*/
|
||||
#define SRCDEP_REG (1 << 9)
|
||||
/*Instruction has input dependency on register in R/M field*/
|
||||
#define SRCDEP_RM (1 << 10)
|
||||
/*Instruction modifies register in REG field*/
|
||||
#define DSTDEP_REG (1 << 11)
|
||||
/*Instruction modifies register in R/M field*/
|
||||
#define DSTDEP_RM (1 << 12)
|
||||
|
||||
/*Instruction has input dependency on given register*/
|
||||
#define SRCDEP_EAX (1 << 13)
|
||||
#define SRCDEP_ECX (1 << 14)
|
||||
#define SRCDEP_EDX (1 << 15)
|
||||
#define SRCDEP_EBX (1 << 16)
|
||||
#define SRCDEP_ESP (1 << 17)
|
||||
#define SRCDEP_EBP (1 << 18)
|
||||
#define SRCDEP_ESI (1 << 19)
|
||||
#define SRCDEP_EDI (1 << 20)
|
||||
|
||||
/*Instruction modifies given register*/
|
||||
#define DSTDEP_EAX (1 << 21)
|
||||
#define DSTDEP_ECX (1 << 22)
|
||||
#define DSTDEP_EDX (1 << 23)
|
||||
#define DSTDEP_EBX (1 << 24)
|
||||
#define DSTDEP_ESP (1 << 25)
|
||||
#define DSTDEP_EBP (1 << 26)
|
||||
#define DSTDEP_ESI (1 << 27)
|
||||
#define DSTDEP_EDI (1 << 28)
|
||||
|
||||
#define INVALID 0
|
||||
|
||||
static int prev_full;
|
||||
@@ -85,119 +53,74 @@ static uint32_t prev_opcode;
|
||||
static uint32_t *prev_timings;
|
||||
static uint32_t prev_op_32;
|
||||
static uint32_t prev_regmask;
|
||||
static uint64_t *prev_deps;
|
||||
static uint32_t prev_fetchdat;
|
||||
|
||||
#define REGMASK_MMX (1 << 8)
|
||||
static uint32_t regmask_modified;
|
||||
|
||||
static uint32_t get_srcdep_mask(uint32_t data, uint32_t fetchdat, int bit8)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
if (data & SRCDEP_REG)
|
||||
{
|
||||
int reg = (fetchdat >> 3) & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
if (data & SRCDEP_RM)
|
||||
{
|
||||
int reg = fetchdat & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
mask |= ((data >> 16) & 0xff);
|
||||
if (data & (MMX_SHIFTPACK | MMX_MULTIPLY))
|
||||
mask |= REGMASK_MMX;
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
static uint32_t get_dstdep_mask(uint32_t data, uint32_t fetchdat, int bit8)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
if (data & DSTDEP_REG)
|
||||
{
|
||||
int reg = (fetchdat >> 3) & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
if (data & DSTDEP_RM)
|
||||
{
|
||||
int reg = fetchdat & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
mask |= ((data >> 24) & 0xff);
|
||||
if (data & (MMX_SHIFTPACK | MMX_MULTIPLY))
|
||||
mask |= REGMASK_MMX;
|
||||
|
||||
return mask;
|
||||
}
|
||||
static uint32_t opcode_timings[256] =
|
||||
{
|
||||
/* ADD ADD ADD ADD*/
|
||||
/*00*/ PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* ADD ADD PUSH ES POP ES*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(3),
|
||||
/* OR OR OR OR*/
|
||||
PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* OR OR PUSH CS */
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, INVALID,
|
||||
/* ADD ADD ADD ADD*/
|
||||
/*00*/ PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* ADD ADD PUSH ES POP ES*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
|
||||
/* OR OR OR OR*/
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* OR OR PUSH CS */
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), INVALID,
|
||||
|
||||
/* ADC ADC ADC ADC*/
|
||||
/*10*/ PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* ADC ADC PUSH SS POP SS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(3),
|
||||
/* SBB SBB SBB SBB*/
|
||||
PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* SBB SBB PUSH DS POP DS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(3),
|
||||
/* ADC ADC ADC ADC*/
|
||||
/*10*/ PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* ADC ADC PUSH SS POP SS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
|
||||
/* SBB SBB SBB SBB*/
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* SBB SBB PUSH DS POP DS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
|
||||
|
||||
/* AND AND AND AND*/
|
||||
/*20*/ PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* AND AND DAA*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* SUB SUB SUB SUB*/
|
||||
PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* SUB SUB DAS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* AND AND AND AND*/
|
||||
/*20*/ PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* AND AND DAA*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* SUB SUB SUB SUB*/
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* SUB SUB DAS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
|
||||
/* XOR XOR XOR XOR*/
|
||||
/*30*/ PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG | DSTDEP_REG,
|
||||
/* XOR XOR AAA*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* CMP CMP CMP CMP*/
|
||||
PAIR_XY | CYCLES_RM | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG,
|
||||
/* CMP CMP AAS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* XOR XOR XOR XOR*/
|
||||
/*30*/ PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* XOR XOR AAA*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* CMP CMP CMP CMP*/
|
||||
PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM,
|
||||
/* CMP CMP AAS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
|
||||
/* INC EAX INC ECX INC EDX INC EBX*/
|
||||
/*40*/ PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* INC ESP INC EBP INC ESI INC EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* DEC EAX DEC ECX DEC EDX DEC EBX*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* DEC ESP DEC EBP DEC ESI DEC EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* INC EAX INC ECX INC EDX INC EBX*/
|
||||
/*40*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* INC ESP INC EBP INC ESI INC EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* DEC EAX DEC ECX DEC EDX DEC EBX*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* DEC ESP DEC EBP DEC ESI DEC EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/*50*/ PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* POP EAX POP ECX POP EDX POP EBX*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* POP ESP POP EBP POP ESI POP EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/*50*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* POP EAX POP ECX POP EDX POP EBX*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* POP ESP POP EBP POP ESI POP EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
|
||||
/* PUSHA POPA BOUND ARPL*/
|
||||
/*60*/ PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(11), PAIR_NP | CYCLES(9),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
/* PUSH imm IMUL PUSH imm IMUL*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(10), PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(10),
|
||||
/* INSB INSW OUTSB OUTSW*/
|
||||
PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14),
|
||||
/* PUSHA POPA BOUND ARPL*/
|
||||
/*60*/ PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(11), PAIR_NP | CYCLES(9),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
/* PUSH imm IMUL PUSH imm IMUL*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(10), PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(10),
|
||||
/* INSB INSW OUTSB OUTSW*/
|
||||
PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14),
|
||||
|
||||
/* Jxx*/
|
||||
/*70*/ PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
@@ -205,37 +128,37 @@ static uint32_t opcode_timings[256] =
|
||||
PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
|
||||
/*80*/ INVALID, INVALID, INVALID, INVALID,
|
||||
/* TEST TEST XCHG XCHG*/
|
||||
PAIR_XY | CYCLES_RM | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* MOV MOV MOV MOV*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG, PAIR_XY | CYCLES_REG | DSTDEP_REG, PAIR_XY | CYCLES_REG | DSTDEP_REG,
|
||||
/* MOV from seg LEA MOV to seg POP*/
|
||||
PAIR_XY | CYCLES(1), PAIR_XY | CYCLES_REG | DSTDEP_REG, CYCLES(3), PAIR_XY | CYCLES(1),
|
||||
/*80*/ INVALID, INVALID, INVALID, INVALID,
|
||||
/* TEST TEST XCHG XCHG*/
|
||||
PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES_RM, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* MOV MOV MOV MOV*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* MOV from seg LEA MOV to seg POP*/
|
||||
PAIR_XY | CYCLES(1), PAIR_XY | CYCLES_REG, CYCLES(3), PAIR_XY | CYCLES(1),
|
||||
|
||||
/* NOP XCHG XCHG XCHG*/
|
||||
/*90*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* XCHG XCHG XCHG XCHG*/
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* CBW CWD CALL far WAIT*/
|
||||
PAIR_XY | CYCLES(3), PAIR_XY | CYCLES(2), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(5),
|
||||
/* PUSHF POPF SAHF LAHF*/
|
||||
PAIR_XY | CYCLES(2) | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES(9) | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(2),
|
||||
/* NOP XCHG XCHG XCHG*/
|
||||
/*90*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* XCHG XCHG XCHG XCHG*/
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* CBW CWD CALL far WAIT*/
|
||||
PAIR_XY | CYCLES(3), PAIR_XY | CYCLES(2), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(5),
|
||||
/* PUSHF POPF SAHF LAHF*/
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(9), PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(2),
|
||||
|
||||
/* MOV MOV MOV MOV*/
|
||||
/*a0*/ PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX,
|
||||
/* MOVSB MOVSW CMPSB CMPSW*/
|
||||
PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(5), PAIR_NP | CYCLES(5),
|
||||
/* TEST TEST STOSB STOSW*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
/* LODSB LODSW SCASB SCASW*/
|
||||
PAIR_NP | CYCLES(3), PAIR_NP | CYCLES(3), PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
/* MOV MOV MOV MOV*/
|
||||
/*a0*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* MOVSB MOVSW CMPSB CMPSW*/
|
||||
PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(5), PAIR_NP | CYCLES(5),
|
||||
/* TEST TEST STOSB STOSW*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
/* LODSB LODSW SCASB SCASW*/
|
||||
PAIR_NP | CYCLES(3), PAIR_NP | CYCLES(3), PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
|
||||
/* MOV*/
|
||||
/*b0*/ PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_ECX, PAIR_XY | CYCLES_REG | DSTDEP_EDX, PAIR_XY | CYCLES_REG | DSTDEP_EBX,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_ECX, PAIR_XY | CYCLES_REG | DSTDEP_EDX, PAIR_XY | CYCLES_REG | DSTDEP_EBX,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_ECX, PAIR_XY | CYCLES_REG | DSTDEP_EDX, PAIR_XY | CYCLES_REG | DSTDEP_EBX,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_ESP, PAIR_XY | CYCLES_REG | DSTDEP_EBP, PAIR_XY | CYCLES_REG | DSTDEP_ESI, PAIR_XY | CYCLES_REG | DSTDEP_EDI,
|
||||
/*b0*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
|
||||
/* RET imm RET*/
|
||||
/*c0*/ INVALID, INVALID, PAIR_X_BRANCH | CYCLES(3), PAIR_X_BRANCH | CYCLES(2),
|
||||
@@ -253,7 +176,7 @@ static uint32_t opcode_timings[256] =
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
/* LOOPNE LOOPE LOOP JCXZ*/
|
||||
/*e0*/ PAIR_X_BRANCH| CYCLES_BRANCH | SRCDEP_ECX, PAIR_X_BRANCH | CYCLES_BRANCH | SRCDEP_ECX, PAIR_X_BRANCH | CYCLES_BRANCH | SRCDEP_ECX, PAIR_X_BRANCH | CYCLES_BRANCH | SRCDEP_ECX,
|
||||
/*e0*/ PAIR_X_BRANCH| CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
/* IN AL IN AX OUT_AL OUT_AX*/
|
||||
PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14),
|
||||
/* CALL JMP JMP JMP*/
|
||||
@@ -273,68 +196,67 @@ static uint32_t opcode_timings[256] =
|
||||
|
||||
static uint32_t opcode_timings_mod3[256] =
|
||||
{
|
||||
/* ADD ADD ADD ADD*/
|
||||
/*00*/ PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* ADD ADD PUSH ES POP ES*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(3),
|
||||
/* OR OR OR OR*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* OR OR PUSH CS */
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, INVALID,
|
||||
/* ADD ADD ADD ADD*/
|
||||
/*00*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* ADD ADD PUSH ES POP ES*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
|
||||
/* OR OR OR OR*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* OR OR PUSH CS */
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), INVALID,
|
||||
|
||||
/* ADC ADC ADC ADC*/
|
||||
/*10*/ PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* ADC ADC PUSH SS POP SS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(3),
|
||||
/* SBB SBB SBB SBB*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* SBB SBB PUSH DS POP DS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, PAIR_NP | CYCLES(3),
|
||||
/* ADC ADC ADC ADC*/
|
||||
/*10*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* ADC ADC PUSH SS POP SS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
|
||||
/* SBB SBB SBB SBB*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* SBB SBB PUSH DS POP DS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
|
||||
|
||||
/* AND AND AND AND*/
|
||||
/*20*/ PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* AND AND DAA*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(9),
|
||||
/* SUB SUB SUB SUB*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* SUB SUB DAS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(9),
|
||||
/* AND AND AND AND*/
|
||||
/*20*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* AND AND DAA*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* SUB SUB SUB SUB*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* SUB SUB DAS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
|
||||
/* XOR XOR XOR XOR*/
|
||||
/*30*/ PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* XOR XOR AAA*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* CMP CMP CMP CMP*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_RM | SRCDEP_REG,
|
||||
/* CMP CMP AAS*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_EAX, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* XOR XOR XOR XOR*/
|
||||
/*30*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* XOR XOR AAA*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
/* CMP CMP CMP CMP*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* CMP CMP AAS*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, INVALID, PAIR_NP | CYCLES(7),
|
||||
|
||||
/* INC EAX INC ECX INC EDX INC EBX*/
|
||||
/*40*/ PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* INC ESP INC EBP INC ESI INC EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* DEC EAX DEC ECX DEC EDX DEC EBX*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* DEC ESP DEC EBP DEC ESI DEC EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* INC EAX INC ECX INC EDX INC EBX*/
|
||||
/*40*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* INC ESP INC EBP INC ESI INC EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* DEC EAX DEC ECX DEC EDX DEC EBX*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* DEC ESP DEC EBP DEC ESI DEC EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/*50*/ PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* POP EAX POP ECX POP EDX POP EBX*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* POP ESP POP EBP POP ESI POP EDI*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EBP | DSTDEP_EBP | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_ESI | DSTDEP_ESI | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES_REG | SRCDEP_EDI | DSTDEP_EDI | SRCDEP_ESP | DSTDEP_ESP,
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/*50*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* POP EAX POP ECX POP EDX POP EBX*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* POP ESP POP EBP POP ESI POP EDI*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
|
||||
/* PUSHA POPA BOUND ARPL*/
|
||||
/*60*/ PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(11), PAIR_NP | CYCLES(9),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
/* PUSH imm IMUL PUSH imm IMUL*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES(10), PAIR_XY | CYCLES_REG | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES(10),
|
||||
/* INSB INSW OUTSB OUTSW*/
|
||||
PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14),
|
||||
/* PUSHA POPA BOUND ARPL*/
|
||||
/*60*/ PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(6), PAIR_NP | CYCLES(11), PAIR_NP | CYCLES(9),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
/* PUSH imm IMUL PUSH imm IMUL*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(10), PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(10),
|
||||
/* INSB INSW OUTSB OUTSW*/
|
||||
PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14),
|
||||
|
||||
/* Jxx*/
|
||||
/*70*/ PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
@@ -342,13 +264,13 @@ static uint32_t opcode_timings_mod3[256] =
|
||||
PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
|
||||
/*80*/ PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_RM,
|
||||
/* TEST TEST XCHG XCHG*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* MOV MOV MOV MOV*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_REG, PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_REG,
|
||||
/* MOV from seg LEA MOV to seg POP*/
|
||||
PAIR_XY | CYCLES(1), PAIR_XY | CYCLES_REG | DSTDEP_REG, PAIR_NP | CYCLES(3), PAIR_XY | CYCLES(1),
|
||||
/*80*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* TEST TEST XCHG XCHG*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
/* MOV MOV MOV MOV*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* MOV from seg LEA MOV to seg POP*/
|
||||
PAIR_XY | CYCLES(1), PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(3), PAIR_XY | CYCLES(1),
|
||||
|
||||
/* NOP XCHG XCHG XCHG*/
|
||||
/*90*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
@@ -357,22 +279,22 @@ static uint32_t opcode_timings_mod3[256] =
|
||||
/* CBW CWD CALL far WAIT*/
|
||||
PAIR_XY | CYCLES(3), PAIR_XY | CYCLES(2), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(5),
|
||||
/* PUSHF POPF SAHF LAHF*/
|
||||
PAIR_XY | CYCLES(2) | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES(9) | SRCDEP_ESP | DSTDEP_ESP, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(2),
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(9), PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(2),
|
||||
|
||||
/* MOV MOV MOV MOV*/
|
||||
/*a0*/ PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX,
|
||||
/*a0*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
/* MOVSB MOVSW CMPSB CMPSW*/
|
||||
PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(5), PAIR_NP | CYCLES(5),
|
||||
/* TEST TEST STOSB STOSW*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_XY | CYCLES_REG | SRCDEP_EAX, PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
/* LODSB LODSW SCASB SCASW*/
|
||||
PAIR_NP | CYCLES(3), PAIR_NP | CYCLES(3), PAIR_NP | CYCLES(2), PAIR_NP | CYCLES(2),
|
||||
|
||||
/* MOV*/
|
||||
/*b0*/ PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_ECX, PAIR_XY | CYCLES_REG | DSTDEP_EDX, PAIR_XY | CYCLES_REG | DSTDEP_EBX,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_ECX, PAIR_XY | CYCLES_REG | DSTDEP_EDX, PAIR_XY | CYCLES_REG | DSTDEP_EBX,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_EAX, PAIR_XY | CYCLES_REG | DSTDEP_ECX, PAIR_XY | CYCLES_REG | DSTDEP_EDX, PAIR_XY | CYCLES_REG | DSTDEP_EBX,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_ESP, PAIR_XY | CYCLES_REG | DSTDEP_EBP, PAIR_XY | CYCLES_REG | DSTDEP_ESI, PAIR_XY | CYCLES_REG | DSTDEP_EDI,
|
||||
/*b0*/ PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
|
||||
/* RET imm RET*/
|
||||
/*c0*/ INVALID, INVALID, PAIR_X_BRANCH | CYCLES(3), PAIR_X_BRANCH | CYCLES(2),
|
||||
@@ -391,7 +313,7 @@ static uint32_t opcode_timings_mod3[256] =
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
|
||||
/* LOOPNE LOOPE LOOP JCXZ*/
|
||||
/*e0*/ PAIR_X_BRANCH| CYCLES_BRANCH | SRCDEP_ECX, PAIR_X_BRANCH | CYCLES_BRANCH | SRCDEP_ECX, PAIR_X_BRANCH | CYCLES_BRANCH | SRCDEP_ECX, PAIR_X_BRANCH | CYCLES_BRANCH | SRCDEP_ECX,
|
||||
/*e0*/ PAIR_X_BRANCH| CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
/* IN AL IN AX OUT_AL OUT_AX*/
|
||||
PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14), PAIR_NP | CYCLES(14),
|
||||
/* CALL JMP JMP JMP*/
|
||||
@@ -441,15 +363,15 @@ static uint32_t opcode_timings_0f[256] =
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
|
||||
/*60*/ PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
/*60*/ PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
|
||||
/*70*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES(1),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
/*70*/ INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES(1),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
|
||||
/*80*/ PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
@@ -476,20 +398,20 @@ static uint32_t opcode_timings_0f[256] =
|
||||
PAIR_XY | CYCLES(4), PAIR_XY | CYCLES(4), PAIR_XY | CYCLES(4), PAIR_XY | CYCLES(4),
|
||||
PAIR_XY | CYCLES(4), PAIR_XY | CYCLES(4), PAIR_XY | CYCLES(4), PAIR_XY | CYCLES(4),
|
||||
|
||||
/*d0*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM,
|
||||
INVALID, PAIR_X | CYCLES_RM, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
/*d0*/ INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
INVALID, PAIR_X | CYCLES_RM, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
|
||||
/*e0*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, INVALID,
|
||||
INVALID, PAIR_X | CYCLES_RM, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
/*e0*/ INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID,
|
||||
INVALID, PAIR_X | CYCLES_RM, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID, PAIR_X | CYCLES_RM,
|
||||
|
||||
/*f0*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM, PAIR_X | MMX_SHIFTPACK | CYCLES_RM,
|
||||
INVALID, PAIR_X | CYCLES_RM, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID,
|
||||
/*f0*/ INVALID, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM,
|
||||
INVALID, PAIR_X | CYCLES_RM, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID,
|
||||
PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, PAIR_X | CYCLES_RM, INVALID,
|
||||
};
|
||||
static uint32_t opcode_timings_0f_mod3[256] =
|
||||
{
|
||||
@@ -523,15 +445,15 @@ static uint32_t opcode_timings_0f_mod3[256] =
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
|
||||
/*60*/ PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
/*60*/ PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
|
||||
/*70*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES(1),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
/*70*/ INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES(1),
|
||||
INVALID, INVALID, INVALID, INVALID,
|
||||
INVALID, INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
|
||||
/*80*/ PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH, PAIR_X_BRANCH | CYCLES_BRANCH,
|
||||
@@ -557,20 +479,20 @@ static uint32_t opcode_timings_0f_mod3[256] =
|
||||
PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(1),
|
||||
PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(1),
|
||||
|
||||
/*d0*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG,
|
||||
INVALID, PAIR_X | MMX_MULTIPLY | CYCLES_REG, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
/*d0*/ INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
INVALID, PAIR_X | CYCLES_REG, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
|
||||
/*e0*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, INVALID,
|
||||
INVALID, PAIR_X | MMX_MULTIPLY | CYCLES_REG, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
/*e0*/ INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID,
|
||||
INVALID, PAIR_X | CYCLES_REG, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID, PAIR_X | CYCLES_REG,
|
||||
|
||||
/*f0*/ INVALID, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG, PAIR_X | MMX_SHIFTPACK | CYCLES_REG,
|
||||
INVALID, PAIR_X | MMX_MULTIPLY | CYCLES_REG, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID,
|
||||
/*f0*/ INVALID, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG,
|
||||
INVALID, PAIR_X | CYCLES_REG, INVALID, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID,
|
||||
PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, PAIR_X | CYCLES_REG, INVALID,
|
||||
};
|
||||
|
||||
static uint32_t opcode_timings_shift[8] =
|
||||
@@ -580,8 +502,8 @@ static uint32_t opcode_timings_shift[8] =
|
||||
};
|
||||
static uint32_t opcode_timings_shift_mod3[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES(3) | DSTDEP_RM, PAIR_XY | CYCLES(4) | DSTDEP_RM,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(3), PAIR_XY | CYCLES(4),
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
};
|
||||
static uint32_t opcode_timings_shift_imm[8] =
|
||||
{
|
||||
@@ -590,18 +512,18 @@ static uint32_t opcode_timings_shift_imm[8] =
|
||||
};
|
||||
static uint32_t opcode_timings_shift_imm_mod3[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES(3) | DSTDEP_RM, PAIR_XY | CYCLES(4) | DSTDEP_RM,
|
||||
PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM, PAIR_XY | CYCLES_REG | DSTDEP_RM,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES(3), PAIR_XY | CYCLES(4),
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
};
|
||||
static uint32_t opcode_timings_shift_cl[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES(2) | SRCDEP_ECX, PAIR_XY | CYCLES(2) | SRCDEP_ECX, PAIR_XY | CYCLES(8) | SRCDEP_ECX, PAIR_XY | CYCLES(9) | SRCDEP_ECX,
|
||||
PAIR_XY | CYCLES(2) | SRCDEP_ECX, PAIR_XY | CYCLES(2) | SRCDEP_ECX, PAIR_XY | CYCLES(2) | SRCDEP_ECX, PAIR_XY | CYCLES(2) | SRCDEP_ECX,
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(8), PAIR_XY | CYCLES(9),
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
};
|
||||
static uint32_t opcode_timings_shift_cl_mod3[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES(2) | DSTDEP_RM | SRCDEP_ECX, PAIR_XY | CYCLES(2) | DSTDEP_RM | SRCDEP_ECX, PAIR_XY | CYCLES(8) | DSTDEP_RM | SRCDEP_ECX, PAIR_XY | CYCLES(9) | DSTDEP_RM | SRCDEP_ECX,
|
||||
PAIR_XY | CYCLES(2) | DSTDEP_RM | SRCDEP_ECX, PAIR_XY | CYCLES(2) | DSTDEP_RM | SRCDEP_ECX, PAIR_XY | CYCLES(2) | DSTDEP_RM | SRCDEP_ECX, PAIR_XY | CYCLES(2) | DSTDEP_RM | SRCDEP_ECX,
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(8), PAIR_XY | CYCLES(9),
|
||||
PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2), PAIR_XY | CYCLES(2),
|
||||
};
|
||||
|
||||
static uint32_t opcode_timings_f6[8] =
|
||||
@@ -613,22 +535,22 @@ static uint32_t opcode_timings_f6[8] =
|
||||
};
|
||||
static uint32_t opcode_timings_f6_mod3[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_RM, INVALID, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(1),
|
||||
/* TST NOT NEG*/
|
||||
PAIR_XY | CYCLES_REG, INVALID, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(1),
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(4), PAIR_NP | CYCLES(18), PAIR_NP | CYCLES(18)
|
||||
};
|
||||
static uint32_t opcode_timings_f7[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_RM, INVALID, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(1),
|
||||
PAIR_XY | CYCLES_REG, INVALID, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(1),
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
PAIR_NP | CYCLES_MULTI(4,10), PAIR_NP | CYCLES_MULTI(4,10), PAIR_NP | CYCLES_MULTI(19,27), PAIR_NP | CYCLES_MULTI(22,30)
|
||||
};
|
||||
static uint32_t opcode_timings_f7_mod3[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_RM, INVALID, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(1),
|
||||
PAIR_XY | CYCLES_REG, INVALID, PAIR_XY | CYCLES(1), PAIR_XY | CYCLES(1),
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
PAIR_NP | CYCLES_MULTI(4,10), PAIR_NP | CYCLES_MULTI(4,10), PAIR_NP | CYCLES_MULTI(19,27), PAIR_NP | CYCLES_MULTI(22,30)
|
||||
};
|
||||
@@ -637,14 +559,14 @@ static uint32_t opcode_timings_ff[8] =
|
||||
/* INC DEC CALL CALL far*/
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_X_BRANCH | CYCLES(3), PAIR_NP | CYCLES(5),
|
||||
/* JMP JMP far PUSH*/
|
||||
PAIR_X_BRANCH | CYCLES(3), PAIR_NP | CYCLES(5), PAIR_XY | CYCLES(1) | SRCDEP_ESP | DSTDEP_ESP, INVALID
|
||||
PAIR_X_BRANCH | CYCLES(3), PAIR_NP | CYCLES(5), PAIR_XY | CYCLES(1), INVALID
|
||||
};
|
||||
static uint32_t opcode_timings_ff_mod3[8] =
|
||||
{
|
||||
/* INC DEC CALL CALL far*/
|
||||
PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_RM, PAIR_XY | CYCLES_REG | SRCDEP_RM | DSTDEP_RM, PAIR_X_BRANCH | CYCLES(1), PAIR_XY | CYCLES(5),
|
||||
/* JMP JMP far PUSH*/
|
||||
PAIR_X_BRANCH | CYCLES(1), PAIR_XY | CYCLES(5), PAIR_XY | CYCLES(2) | SRCDEP_ESP | DSTDEP_ESP, INVALID
|
||||
/* INC DEC CALL CALL far*/
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_X_BRANCH | CYCLES(1), PAIR_XY | CYCLES(5),
|
||||
/* JMP JMP far PUSH*/
|
||||
PAIR_X_BRANCH | CYCLES(1), PAIR_XY | CYCLES(5), PAIR_XY | CYCLES(2), INVALID
|
||||
};
|
||||
|
||||
static uint32_t opcode_timings_d8[8] =
|
||||
@@ -812,8 +734,23 @@ static uint32_t opcode_timings_df_mod3[8] =
|
||||
|
||||
static uint32_t opcode_timings_8x[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG,
|
||||
PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RMW | SRCDEP_REG, PAIR_XY | CYCLES_RM | SRCDEP_REG
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW,
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM
|
||||
};
|
||||
static uint32_t opcode_timings_8x_mod3[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG
|
||||
};
|
||||
static uint32_t opcode_timings_81[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW,
|
||||
PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RMW, PAIR_XY | CYCLES_RM
|
||||
};
|
||||
static uint32_t opcode_timings_81_mod3[8] =
|
||||
{
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG,
|
||||
PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG, PAIR_XY | CYCLES_REG
|
||||
};
|
||||
|
||||
static int decode_delay;
|
||||
@@ -836,6 +773,7 @@ static inline int COUNT(uint32_t c, int op_32)
|
||||
void codegen_timing_686_block_start()
|
||||
{
|
||||
prev_full = decode_delay = 0;
|
||||
regmask_modified = 0;
|
||||
}
|
||||
|
||||
void codegen_timing_686_start()
|
||||
@@ -853,9 +791,20 @@ void codegen_timing_686_prefix(uint8_t prefix, uint32_t fetchdat)
|
||||
last_prefix = prefix;
|
||||
}
|
||||
|
||||
static int check_agi(uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
uint32_t addr_regmask = get_addr_regmask(deps[opcode], fetchdat, op_32);
|
||||
|
||||
if (addr_regmask & IMPL_ESP)
|
||||
addr_regmask |= (1 << REG_ESP);
|
||||
|
||||
return regmask_modified & addr_regmask;
|
||||
}
|
||||
|
||||
void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
uint32_t *timings;
|
||||
uint64_t *deps;
|
||||
int mod3 = ((fetchdat & 0xc0) == 0xc0);
|
||||
int bit8 = !(opcode & 1);
|
||||
|
||||
@@ -863,80 +812,101 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
case 0x0f:
|
||||
timings = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
|
||||
deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
|
||||
break;
|
||||
|
||||
case 0xd8:
|
||||
timings = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
|
||||
deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xd9:
|
||||
timings = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
|
||||
deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
|
||||
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xda:
|
||||
timings = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
|
||||
deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdb:
|
||||
timings = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
|
||||
deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
|
||||
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdc:
|
||||
timings = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
|
||||
deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdd:
|
||||
timings = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
|
||||
deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xde:
|
||||
timings = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
|
||||
deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdf:
|
||||
timings = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
|
||||
deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
|
||||
default:
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x80: case 0x81: case 0x82: case 0x83:
|
||||
timings = mod3 ? opcode_timings_mod3 : opcode_timings_8x;
|
||||
if (!mod3)
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
case 0x80: case 0x82: case 0x83:
|
||||
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
|
||||
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0x81:
|
||||
timings = mod3 ? opcode_timings_81_mod3 : opcode_timings_81;
|
||||
deps = mod3 ? opcode_deps_81_mod3 : opcode_deps_81;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
case 0xc0: case 0xc1:
|
||||
timings = mod3 ? opcode_timings_shift_imm_mod3 : opcode_timings_shift_imm;
|
||||
deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
|
||||
case 0xd0: case 0xd1:
|
||||
timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
|
||||
deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
|
||||
case 0xd2: case 0xd3:
|
||||
timings = mod3 ? opcode_timings_shift_cl_mod3 : opcode_timings_shift_cl;
|
||||
deps = mod3 ? opcode_deps_shift_cl_mod3 : opcode_deps_shift_cl;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
case 0xf6:
|
||||
timings = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
|
||||
deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0xf7:
|
||||
timings = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
|
||||
deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0xff:
|
||||
timings = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
|
||||
deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
default:
|
||||
timings = mod3 ? opcode_timings_mod3 : opcode_timings;
|
||||
deps = mod3 ? opcode_deps_mod3 : opcode_deps;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -946,33 +916,43 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
|
||||
if (prev_full)
|
||||
{
|
||||
uint8_t regmask = get_srcdep_mask(timings[opcode], fetchdat, bit8);
|
||||
|
||||
uint32_t regmask = get_srcdep_mask(deps[opcode], fetchdat, bit8, op_32);
|
||||
int agi_stall = 0;
|
||||
|
||||
if (regmask & IMPL_ESP)
|
||||
regmask |= SRCDEP_ESP | DSTDEP_ESP;
|
||||
|
||||
if (check_agi(prev_deps, prev_opcode, prev_fetchdat, prev_op_32))
|
||||
agi_stall = 2;
|
||||
|
||||
/*Second instruction in the pair*/
|
||||
if ((timings[opcode] & PAIR_MASK) == PAIR_NP)
|
||||
{
|
||||
/*Instruction can not pair with previous*/
|
||||
/*Run previous now*/
|
||||
codegen_block_cycles += COUNT(prev_timings[prev_opcode], prev_op_32) + decode_delay;
|
||||
decode_delay = (-COUNT(prev_timings[prev_opcode], prev_op_32)) + 1;
|
||||
codegen_block_cycles += COUNT(prev_timings[prev_opcode], prev_op_32) + decode_delay + agi_stall;
|
||||
decode_delay = (-COUNT(prev_timings[prev_opcode], prev_op_32)) + 1 + agi_stall;
|
||||
prev_full = 0;
|
||||
regmask_modified = prev_regmask;
|
||||
}
|
||||
else if (((timings[opcode] & PAIR_MASK) == PAIR_X || (timings[opcode] & PAIR_MASK) == PAIR_X_BRANCH)
|
||||
&& (prev_timings[opcode] & PAIR_MASK) == PAIR_X)
|
||||
{
|
||||
/*Instruction can not pair with previous*/
|
||||
/*Run previous now*/
|
||||
codegen_block_cycles += COUNT(prev_timings[prev_opcode], prev_op_32) + decode_delay;
|
||||
decode_delay = (-COUNT(prev_timings[prev_opcode], prev_op_32)) + 1;
|
||||
codegen_block_cycles += COUNT(prev_timings[prev_opcode], prev_op_32) + decode_delay + agi_stall;
|
||||
decode_delay = (-COUNT(prev_timings[prev_opcode], prev_op_32)) + 1 + agi_stall;
|
||||
prev_full = 0;
|
||||
regmask_modified = prev_regmask;
|
||||
}
|
||||
else if (prev_regmask & regmask)
|
||||
{
|
||||
/*Instruction can not pair with previous*/
|
||||
/*Run previous now*/
|
||||
codegen_block_cycles += COUNT(prev_timings[prev_opcode], prev_op_32) + decode_delay;
|
||||
decode_delay = (-COUNT(prev_timings[prev_opcode], prev_op_32)) + 1;
|
||||
codegen_block_cycles += COUNT(prev_timings[prev_opcode], prev_op_32) + decode_delay + agi_stall;
|
||||
decode_delay = (-COUNT(prev_timings[prev_opcode], prev_op_32)) + 1 + agi_stall;
|
||||
prev_full = 0;
|
||||
regmask_modified = prev_regmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -982,9 +962,14 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
|
||||
if (!t_pair)
|
||||
fatal("Pairable 0 cycles! %02x %02x\n", opcode, prev_opcode);
|
||||
codegen_block_cycles += t_pair;
|
||||
decode_delay = (-t_pair) + 1;
|
||||
|
||||
if (check_agi(deps, opcode, fetchdat, op_32))
|
||||
agi_stall = 2;
|
||||
|
||||
codegen_block_cycles += t_pair + agi_stall;
|
||||
decode_delay = (-t_pair) + 1 + agi_stall;
|
||||
|
||||
regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8) | prev_regmask;
|
||||
prev_full = 0;
|
||||
return;
|
||||
}
|
||||
@@ -996,8 +981,14 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
if ((timings[opcode] & PAIR_MASK) == PAIR_NP || (timings[opcode] & PAIR_MASK) == PAIR_X_BRANCH)
|
||||
{
|
||||
/*Instruction not pairable*/
|
||||
codegen_block_cycles += COUNT(timings[opcode], op_32) + decode_delay;
|
||||
decode_delay = (-COUNT(timings[opcode], op_32)) + 1;
|
||||
int agi_stall = 0;
|
||||
|
||||
if (check_agi(deps, opcode, fetchdat, op_32))
|
||||
agi_stall = 2;
|
||||
|
||||
codegen_block_cycles += COUNT(timings[opcode], op_32) + decode_delay + agi_stall;
|
||||
decode_delay = (-COUNT(timings[opcode], op_32)) + 1 + agi_stall;
|
||||
regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1006,7 +997,11 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
prev_opcode = opcode;
|
||||
prev_timings = timings;
|
||||
prev_op_32 = op_32;
|
||||
prev_regmask = get_dstdep_mask(timings[opcode], fetchdat, bit8);
|
||||
prev_regmask = get_dstdep_mask(deps[opcode], fetchdat, bit8);
|
||||
if (prev_regmask & IMPL_ESP)
|
||||
prev_regmask |= SRCDEP_ESP | DSTDEP_ESP;
|
||||
prev_deps = deps;
|
||||
prev_fetchdat = fetchdat;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
678
src/CPU/codegen_timing_common.c
Normal file
678
src/CPU/codegen_timing_common.c
Normal file
@@ -0,0 +1,678 @@
|
||||
#include "../ibm.h"
|
||||
#include "codegen_timing_common.h"
|
||||
|
||||
uint64_t opcode_deps[256] =
|
||||
{
|
||||
/* ADD ADD ADD ADD*/
|
||||
/*00*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* ADD ADD PUSH ES POP ES*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
|
||||
/* OR OR OR OR*/
|
||||
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* OR OR PUSH CS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, 0,
|
||||
|
||||
/* ADC ADC ADC ADC*/
|
||||
/*10*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* ADC ADC PUSH SS POP SS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
|
||||
/* SBB SBB SBB SBB*/
|
||||
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* SBB SBB PUSH DS POP DS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
|
||||
|
||||
/* AND AND AND AND*/
|
||||
/*20*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* AND AND DAA*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
/* SUB SUB SUB SUB*/
|
||||
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* SUB SUB DAS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
|
||||
/* XOR XOR XOR XOR*/
|
||||
/*30*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* XOR XOR AAA*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
/* CMP CMP CMP CMP*/
|
||||
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM,
|
||||
/* CMP CMP AAS*/
|
||||
SRCDEP_EAX, SRCDEP_EAX, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
|
||||
/* INC EAX INC ECX INC EDX INC EBX*/
|
||||
/*40*/ SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* INC ESP INC EBP INC ESI INC EDI*/
|
||||
SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* DEC EAX DEC ECX DEC EDX DEC EBX*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* DEC ESP DEC EBP DEC ESI DEC EDI*/
|
||||
SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
|
||||
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/*50*/ SRCDEP_EAX | IMPL_ESP, SRCDEP_ECX | IMPL_ESP, SRCDEP_EDX | IMPL_ESP, SRCDEP_EBX | IMPL_ESP,
|
||||
/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
|
||||
SRCDEP_ESP | IMPL_ESP, SRCDEP_EBP | IMPL_ESP, SRCDEP_ESI | IMPL_ESP, SRCDEP_EDI | IMPL_ESP,
|
||||
/* POP EAX POP ECX POP EDX POP EBX*/
|
||||
DSTDEP_EAX | IMPL_ESP, DSTDEP_ECX | IMPL_ESP, DSTDEP_EDX | IMPL_ESP, DSTDEP_EBX | IMPL_ESP,
|
||||
/* POP ESP POP EBP POP ESI POP EDI*/
|
||||
DSTDEP_ESP | IMPL_ESP, DSTDEP_EBP | IMPL_ESP, DSTDEP_ESI | IMPL_ESP, DSTDEP_EDI | IMPL_ESP,
|
||||
|
||||
/* PUSHA POPA BOUND ARPL*/
|
||||
/*60*/ IMPL_ESP, IMPL_ESP, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
/* PUSH imm IMUL PUSH imm IMUL*/
|
||||
IMPL_ESP, DSTDEP_REG | MODRM, IMPL_ESP, DSTDEP_REG | MODRM,
|
||||
/* INSB INSW OUTSB OUTSW*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
/* Jxx*/
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0,
|
||||
/* TEST TEST XCHG XCHG*/
|
||||
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
|
||||
/* MOV MOV MOV MOV*/
|
||||
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, DSTDEP_REG | MODRM, DSTDEP_REG | MODRM,
|
||||
/* MOV from seg LEA MOV to seg POP*/
|
||||
MODRM, DSTDEP_REG | MODRM, MODRM, IMPL_ESP | MODRM,
|
||||
|
||||
/* NOP XCHG XCHG XCHG*/
|
||||
/*90*/ 0, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* XCHG XCHG XCHG XCHG*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBP | DSTDEP_EBP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* CBW CWD CALL far WAIT*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EDX, 0, 0,
|
||||
/* PUSHF POPF SAHF LAHF*/
|
||||
IMPL_ESP, IMPL_ESP, SRCDEP_EAX, DSTDEP_EAX,
|
||||
|
||||
/* MOV MOV MOV MOV*/
|
||||
/*a0*/ DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
|
||||
/* MOVSB MOVSW CMPSB CMPSW*/
|
||||
0, 0, 0, 0,
|
||||
/* TEST TEST STOSB STOSW*/
|
||||
SRCDEP_EAX, SRCDEP_EAX, 0, 0,
|
||||
/* LODSB LODSW SCASB SCASW*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
/* MOV*/
|
||||
/*b0*/ DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
|
||||
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
|
||||
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
|
||||
DSTDEP_ESP, DSTDEP_EBP, DSTDEP_ESI, DSTDEP_EDI,
|
||||
|
||||
/* RET imm RET*/
|
||||
/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
|
||||
/* LES LDS MOV MOV*/
|
||||
DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, MODRM, MODRM,
|
||||
/* ENTER LEAVE RETF RETF*/
|
||||
IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
|
||||
/* INT3 INT INTO IRET*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
|
||||
/*d0*/ 0, 0, 0, 0,
|
||||
/* AAM AAD SETALC XLAT*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX | SRCDEP_EBX,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/* LOOPNE LOOPE LOOP JCXZ*/
|
||||
/*e0*/ SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX,
|
||||
/* IN AL IN AX OUT_AL OUT_AX*/
|
||||
DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
|
||||
/* CALL JMP JMP JMP*/
|
||||
IMPL_ESP, 0, 0, 0,
|
||||
/* IN AL IN AX OUT_AL OUT_AX*/
|
||||
SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | SRCDEP_EAX, SRCDEP_EDX | SRCDEP_EAX,
|
||||
|
||||
/* REPNE REPE*/
|
||||
/*f0*/ 0, 0, 0, 0,
|
||||
/* HLT CMC*/
|
||||
0, 0, 0, 0,
|
||||
/* CLC STC CLI STI*/
|
||||
0, 0, 0, 0,
|
||||
/* CLD STD INCDEC*/
|
||||
0, 0, MODRM, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_mod3[256] =
|
||||
{
|
||||
/* ADD ADD ADD ADD*/
|
||||
/*00*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* ADD ADD PUSH ES POP ES*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
|
||||
/* OR OR OR OR*/
|
||||
SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* OR OR PUSH CS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, 0,
|
||||
|
||||
/* ADC ADC ADC ADC*/
|
||||
/*10*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* ADC ADC PUSH SS POP SS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
|
||||
/* SBB SBB SBB SBB*/
|
||||
SRCDEP_REG |SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* SBB SBB PUSH DS POP DS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
|
||||
|
||||
/* AND AND AND AND*/
|
||||
/*20*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* AND AND DAA*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
/* SUB SUB SUB SUB*/
|
||||
SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* SUB SUB DAS*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
|
||||
/* XOR XOR XOR XOR*/
|
||||
/*30*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* XOR XOR AAA*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
/* CMP CMP CMP CMP*/
|
||||
SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* CMP CMP AAS*/
|
||||
SRCDEP_EAX, SRCDEP_EAX, 0, SRCDEP_EAX | DSTDEP_EAX,
|
||||
|
||||
/* INC EAX INC ECX INC EDX INC EBX*/
|
||||
/*40*/ SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* INC ESP INC EBP INC ESI INC EDI*/
|
||||
SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* DEC EAX DEC ECX DEC EDX DEC EBX*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* DEC ESP DEC EBP DEC ESI DEC EDI*/
|
||||
SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
|
||||
|
||||
/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
|
||||
/*50*/ SRCDEP_EAX | IMPL_ESP, SRCDEP_ECX | IMPL_ESP, SRCDEP_EDX | IMPL_ESP, SRCDEP_EBX | IMPL_ESP,
|
||||
/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
|
||||
SRCDEP_ESP | IMPL_ESP, SRCDEP_EBP | IMPL_ESP, SRCDEP_ESI | IMPL_ESP, SRCDEP_EDI | IMPL_ESP,
|
||||
/* POP EAX POP ECX POP EDX POP EBX*/
|
||||
DSTDEP_EAX | IMPL_ESP, DSTDEP_ECX | IMPL_ESP, DSTDEP_EDX | IMPL_ESP, DSTDEP_EBX | IMPL_ESP,
|
||||
/* POP ESP POP EBP POP ESI POP EDI*/
|
||||
DSTDEP_ESP | IMPL_ESP, DSTDEP_EBP | IMPL_ESP, DSTDEP_ESI | IMPL_ESP, DSTDEP_EDI | IMPL_ESP,
|
||||
|
||||
/* PUSHA POPA BOUND ARPL*/
|
||||
/*60*/ IMPL_ESP, IMPL_ESP, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
/* PUSH imm IMUL PUSH imm IMUL*/
|
||||
IMPL_ESP, DSTDEP_REG | SRCDEP_RM | MODRM, IMPL_ESP, DSTDEP_REG | SRCDEP_RM | MODRM,
|
||||
/* INSB INSW OUTSB OUTSW*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
/* Jxx*/
|
||||
/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/*80*/ 0, 0, 0, 0,
|
||||
/* TEST TEST XCHG XCHG*/
|
||||
SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
/* MOV MOV MOV MOV*/
|
||||
SRCDEP_REG | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_REG | MODRM, SRCDEP_RM | DSTDEP_REG | MODRM,
|
||||
/* MOV from seg LEA MOV to seg POP*/
|
||||
DSTDEP_RM | MODRM, DSTDEP_REG | MODRM, SRCDEP_RM | MODRM, IMPL_ESP | DSTDEP_RM | MODRM,
|
||||
|
||||
/* NOP XCHG XCHG XCHG*/
|
||||
/*90*/ 0, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBX | DSTDEP_EBX,
|
||||
/* XCHG XCHG XCHG XCHG*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBP | DSTDEP_EBP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDI | DSTDEP_EDI,
|
||||
/* CBW CWD CALL far WAIT*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EDX, 0, 0,
|
||||
/* PUSHF POPF SAHF LAHF*/
|
||||
IMPL_ESP, IMPL_ESP, SRCDEP_EAX, DSTDEP_EAX,
|
||||
|
||||
/* MOV MOV MOV MOV*/
|
||||
/*a0*/ DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
|
||||
/* MOVSB MOVSW CMPSB CMPSW*/
|
||||
0, 0, 0, 0,
|
||||
/* TEST TEST STOSB STOSW*/
|
||||
SRCDEP_EAX, SRCDEP_EAX, 0, 0,
|
||||
/* LODSB LODSW SCASB SCASW*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
/* MOV*/
|
||||
/*b0*/ DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
|
||||
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
|
||||
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
|
||||
DSTDEP_ESP, DSTDEP_EBP, DSTDEP_ESI, DSTDEP_EDI,
|
||||
|
||||
/* RET imm RET*/
|
||||
/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
|
||||
/* LES LDS MOV MOV*/
|
||||
DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, DSTDEP_RM | MODRM, DSTDEP_RM | MODRM,
|
||||
/* ENTER LEAVE RETF RETF*/
|
||||
IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
|
||||
/* INT3 INT INTO IRET*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
|
||||
/*d0*/ 0, 0, 0, 0,
|
||||
/* AAM AAD SETALC XLAT*/
|
||||
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX | SRCDEP_EBX,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/* LOOPNE LOOPE LOOP JCXZ*/
|
||||
/*e0*/ SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX,
|
||||
/* IN AL IN AX OUT_AL OUT_AX*/
|
||||
DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
|
||||
/* CALL JMP JMP JMP*/
|
||||
IMPL_ESP, 0, 0, 0,
|
||||
/* IN AL IN AX OUT_AL OUT_AX*/
|
||||
SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | SRCDEP_EAX, SRCDEP_EDX | SRCDEP_EAX,
|
||||
|
||||
/* REPNE REPE*/
|
||||
/*f0*/ 0, 0, 0, 0,
|
||||
/* HLT CMC*/
|
||||
0, 0, 0, 0,
|
||||
/* CLC STC CLI STI*/
|
||||
0, 0, 0, 0,
|
||||
/* CLD STD INCDEC*/
|
||||
0, 0, SRCDEP_RM | DSTDEP_RM | MODRM, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_0f[256] =
|
||||
{
|
||||
/*00*/ MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*10*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*20*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*30*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*50*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*60*/ MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*70*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*80*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*90*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*a0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*b0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*c0*/ MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*d0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*e0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, 0,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*f0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
};
|
||||
uint64_t opcode_deps_0f_mod3[256] =
|
||||
{
|
||||
/*00*/ MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*10*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*20*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*30*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*50*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*60*/ MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*70*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*80*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*90*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*a0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*b0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*c0*/ MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*d0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*e0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, 0,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*f0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_shift[8] =
|
||||
{
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
};
|
||||
uint64_t opcode_deps_shift_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_shift_cl[8] =
|
||||
{
|
||||
MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX,
|
||||
MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX,
|
||||
};
|
||||
uint64_t opcode_deps_shift_cl_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_f6[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
MODRM, 0, MODRM, MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_f6_mod3[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
SRCDEP_RM | MODRM, 0, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_f7[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
MODRM, 0, MODRM, MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_f7_mod3[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
SRCDEP_RM | MODRM, 0, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_ff[8] =
|
||||
{
|
||||
/* INC DEC CALL CALL far*/
|
||||
MODRM, MODRM, MODRM | IMPL_ESP, MODRM,
|
||||
/* JMP JMP far PUSH*/
|
||||
MODRM, MODRM, MODRM | IMPL_ESP, 0
|
||||
};
|
||||
uint64_t opcode_deps_ff_mod3[8] =
|
||||
{
|
||||
/* INC DEC CALL CALL far*/
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM | IMPL_ESP, MODRM,
|
||||
/* JMP JMP far PUSH*/
|
||||
SRCDEP_RM | MODRM, MODRM, SRCDEP_RM | MODRM | IMPL_ESP, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_d8[8] =
|
||||
{
|
||||
/* FADDs FMULs FCOMs FCOMPs*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_POP | FPU_READ_ST0 | MODRM,
|
||||
/* FSUBs FSUBRs FDIVs FDIVRs*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_d8_mod3[8] =
|
||||
{
|
||||
/* FADD FMUL FCOM FCOMP*/
|
||||
FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG, FPU_READ_ST0 | FPU_READ_STREG, FPU_POP | FPU_READ_ST0 | FPU_READ_STREG,
|
||||
/* FSUB FSUBR FDIV FDIVR*/
|
||||
FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_d9[8] =
|
||||
{
|
||||
/* FLDs FSTs FSTPs*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_POP | MODRM,
|
||||
/* FLDENV FLDCW FSTENV FSTCW*/
|
||||
MODRM, MODRM, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_d9_mod3[64] =
|
||||
{
|
||||
/*FLD*/
|
||||
FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG,
|
||||
FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG,
|
||||
/*FXCH*/
|
||||
FPU_FXCH, FPU_FXCH, FPU_FXCH, FPU_FXCH,
|
||||
FPU_FXCH, FPU_FXCH, FPU_FXCH, FPU_FXCH,
|
||||
/*FNOP*/
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*FSTP*/
|
||||
FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP,
|
||||
FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP,
|
||||
/* opFCHS opFABS*/
|
||||
0, 0, 0, 0,
|
||||
/* opFTST opFXAM*/
|
||||
0, 0, 0, 0,
|
||||
/* opFLD1 opFLDL2T opFLDL2E opFLDPI*/
|
||||
FPU_PUSH, FPU_PUSH, FPU_PUSH, FPU_PUSH,
|
||||
/* opFLDEG2 opFLDLN2 opFLDZ*/
|
||||
FPU_PUSH, FPU_PUSH, FPU_PUSH, 0,
|
||||
/* opF2XM1 opFYL2X opFPTAN opFPATAN*/
|
||||
0, 0, 0, 0,
|
||||
/* opFDECSTP opFINCSTP,*/
|
||||
0, 0, 0, 0,
|
||||
/* opFPREM opFSQRT opFSINCOS*/
|
||||
0, 0, 0, 0,
|
||||
/* opFRNDINT opFSCALE opFSIN opFCOS*/
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_da[8] =
|
||||
{
|
||||
/* FIADDl FIMULl FICOMl FICOMPl*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FISUBl FISUBRl FIDIVl FIDIVRl*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_da_mod3[8] =
|
||||
{
|
||||
0, 0, 0, 0,
|
||||
/* FCOMPP*/
|
||||
0, FPU_POP2, 0, 0
|
||||
};
|
||||
|
||||
|
||||
uint64_t opcode_deps_db[8] =
|
||||
{
|
||||
/* FLDil FSTil FSTPil*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FLDe FSTPe*/
|
||||
0, FPU_PUSH | MODRM, 0, FPU_READ_ST0 | FPU_POP | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_db_mod3[64] =
|
||||
{
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/* opFNOP opFCLEX opFINIT*/
|
||||
0, 0, 0, 0,
|
||||
/* opFNOP opFNOP*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_dc[8] =
|
||||
{
|
||||
/* FADDd FMULd FCOMd FCOMPd*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FSUBd FSUBRd FDIVd FDIVRd*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_dc_mod3[8] =
|
||||
{
|
||||
/* opFADDr opFMULr*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG, 0, 0,
|
||||
/* opFSUBRr opFSUBr opFDIVRr opFDIVr*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_dd[8] =
|
||||
{
|
||||
/* FLDd FSTd FSTPd*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FRSTOR FSAVE FSTSW*/
|
||||
MODRM, 0, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_dd_mod3[8] =
|
||||
{
|
||||
/* FFFREE FST FSTP*/
|
||||
0, 0, FPU_READ_ST0 | FPU_WRITE_STREG, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP,
|
||||
/* FUCOM FUCOMP*/
|
||||
FPU_READ_ST0 | FPU_READ_STREG, FPU_READ_ST0 | FPU_READ_STREG | FPU_POP, 0, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_de[8] =
|
||||
{
|
||||
/* FIADDw FIMULw FICOMw FICOMPw*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FISUBw FISUBRw FIDIVw FIDIVRw*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_de_mod3[8] =
|
||||
{
|
||||
/* FADDP FMULP FCOMPP*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, 0, FPU_READ_ST0 | FPU_READ_ST1 | FPU_POP2,
|
||||
/* FSUBP FSUBRP FDIVP FDIVRP*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_df[8] =
|
||||
{
|
||||
/* FILDiw FISTiw FISTPiw*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FILDiq FBSTP FISTPiq*/
|
||||
0, FPU_PUSH | MODRM, FPU_READ_ST0 | FPU_POP | MODRM, FPU_READ_ST0 | FPU_POP | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_df_mod3[8] =
|
||||
{
|
||||
0, 0, 0, 0,
|
||||
/* FSTSW AX*/
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_81[8] =
|
||||
{
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_81_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_8x[8] =
|
||||
{
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_8x_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM
|
||||
};
|
||||
226
src/CPU/codegen_timing_common.h
Normal file
226
src/CPU/codegen_timing_common.h
Normal file
@@ -0,0 +1,226 @@
|
||||
#include "codegen_ops.h"
|
||||
|
||||
/*Instruction has input dependency on register in REG field*/
|
||||
#define SRCDEP_REG (1ull << 0)
|
||||
/*Instruction has input dependency on register in R/M field*/
|
||||
#define SRCDEP_RM (1ull << 1)
|
||||
/*Instruction modifies register in REG field*/
|
||||
#define DSTDEP_REG (1ull << 2)
|
||||
/*Instruction modifies register in R/M field*/
|
||||
#define DSTDEP_RM (1ull << 3)
|
||||
|
||||
#define SRCDEP_SHIFT 4
|
||||
#define DSTDEP_SHIFT 12
|
||||
|
||||
/*Instruction has input dependency on given register*/
|
||||
#define SRCDEP_EAX (1ull << 4)
|
||||
#define SRCDEP_ECX (1ull << 5)
|
||||
#define SRCDEP_EDX (1ull << 6)
|
||||
#define SRCDEP_EBX (1ull << 7)
|
||||
#define SRCDEP_ESP (1ull << 8)
|
||||
#define SRCDEP_EBP (1ull << 9)
|
||||
#define SRCDEP_ESI (1ull << 10)
|
||||
#define SRCDEP_EDI (1ull << 11)
|
||||
|
||||
/*Instruction modifies given register*/
|
||||
#define DSTDEP_EAX (1ull << 12)
|
||||
#define DSTDEP_ECX (1ull << 13)
|
||||
#define DSTDEP_EDX (1ull << 14)
|
||||
#define DSTDEP_EBX (1ull << 15)
|
||||
#define DSTDEP_ESP (1ull << 16)
|
||||
#define DSTDEP_EBP (1ull << 17)
|
||||
#define DSTDEP_ESI (1ull << 18)
|
||||
#define DSTDEP_EDI (1ull << 19)
|
||||
|
||||
/*Instruction has ModR/M byte*/
|
||||
#define MODRM (1ull << 20)
|
||||
/*Instruction implicitly uses ESP*/
|
||||
#define IMPL_ESP (1ull << 21)
|
||||
|
||||
/*Instruction is MMX shift or pack/unpack instruction*/
|
||||
#define MMX_SHIFTPACK (1ull << 22)
|
||||
/*Instruction is MMX multiply instruction*/
|
||||
#define MMX_MULTIPLY (1ull << 23)
|
||||
|
||||
/*Instruction pops the FPU stack*/
|
||||
#define FPU_POP (1ull << 24)
|
||||
/*Instruction pops the FPU stack twice*/
|
||||
#define FPU_POP2 (1ull << 25)
|
||||
/*Instruction pushes onto the FPU stack*/
|
||||
#define FPU_PUSH (1ull << 26)
|
||||
|
||||
/*Instruction writes to ST(0)*/
|
||||
#define FPU_WRITE_ST0 (1ull << 27)
|
||||
/*Instruction reads from ST(0)*/
|
||||
#define FPU_READ_ST0 (1ull << 28)
|
||||
/*Instruction reads from and writes to ST(0)*/
|
||||
#define FPU_RW_ST0 (3ull << 27)
|
||||
|
||||
/*Instruction reads from ST(1)*/
|
||||
#define FPU_READ_ST1 (1ull << 29)
|
||||
/*Instruction writes to ST(1)*/
|
||||
#define FPU_WRITE_ST1 (1ull << 30)
|
||||
/*Instruction reads from and writes to ST(1)*/
|
||||
#define FPU_RW_ST1 (3ull << 29)
|
||||
|
||||
/*Instruction reads from ST(reg)*/
|
||||
#define FPU_READ_STREG (1ull << 31)
|
||||
/*Instruction writes to ST(reg)*/
|
||||
#define FPU_WRITE_STREG (1ull << 32)
|
||||
/*Instruction reads from and writes to ST(reg)*/
|
||||
#define FPU_RW_STREG (3ull << 30)
|
||||
|
||||
#define FPU_FXCH (1ull << 33)
|
||||
|
||||
|
||||
#define REGMASK_IMPL_ESP (1 << 8)
|
||||
#define REGMASK_SHIFTPACK (1 << 9)
|
||||
#define REGMASK_MULTIPLY (1 << 9)
|
||||
|
||||
|
||||
extern uint64_t opcode_deps[256];
|
||||
extern uint64_t opcode_deps_mod3[256];
|
||||
extern uint64_t opcode_deps_0f[256];
|
||||
extern uint64_t opcode_deps_0f_mod3[256];
|
||||
extern uint64_t opcode_deps_shift[8];
|
||||
extern uint64_t opcode_deps_shift_mod3[8];
|
||||
extern uint64_t opcode_deps_shift_cl[8];
|
||||
extern uint64_t opcode_deps_shift_cl_mod3[8];
|
||||
extern uint64_t opcode_deps_f6[8];
|
||||
extern uint64_t opcode_deps_f6_mod3[8];
|
||||
extern uint64_t opcode_deps_f7[8];
|
||||
extern uint64_t opcode_deps_f7_mod3[8];
|
||||
extern uint64_t opcode_deps_ff[8];
|
||||
extern uint64_t opcode_deps_ff_mod3[8];
|
||||
extern uint64_t opcode_deps_d8[8];
|
||||
extern uint64_t opcode_deps_d8_mod3[8];
|
||||
extern uint64_t opcode_deps_d9[8];
|
||||
extern uint64_t opcode_deps_d9_mod3[64];
|
||||
extern uint64_t opcode_deps_da[8];
|
||||
extern uint64_t opcode_deps_da_mod3[8];
|
||||
extern uint64_t opcode_deps_db[8];
|
||||
extern uint64_t opcode_deps_db_mod3[64];
|
||||
extern uint64_t opcode_deps_dc[8];
|
||||
extern uint64_t opcode_deps_dc_mod3[8];
|
||||
extern uint64_t opcode_deps_dd[8];
|
||||
extern uint64_t opcode_deps_dd_mod3[8];
|
||||
extern uint64_t opcode_deps_de[8];
|
||||
extern uint64_t opcode_deps_de_mod3[8];
|
||||
extern uint64_t opcode_deps_df[8];
|
||||
extern uint64_t opcode_deps_df_mod3[8];
|
||||
extern uint64_t opcode_deps_81[8];
|
||||
extern uint64_t opcode_deps_81_mod3[8];
|
||||
extern uint64_t opcode_deps_8x[8];
|
||||
extern uint64_t opcode_deps_8x_mod3[8];
|
||||
|
||||
|
||||
|
||||
static inline uint32_t get_addr_regmask(uint64_t data, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
uint32_t addr_regmask = 0;
|
||||
|
||||
if (data & MODRM)
|
||||
{
|
||||
uint8_t modrm = fetchdat & 0xff;
|
||||
|
||||
if ((modrm & 0xc0) != 0xc0)
|
||||
{
|
||||
if (op_32 & 0x200)
|
||||
{
|
||||
if ((modrm & 0x7) == 4)
|
||||
{
|
||||
uint8_t sib = (fetchdat >> 8) & 0xff;
|
||||
|
||||
if ((modrm & 0xc0) != 0xc0 && (sib & 7) != 5)
|
||||
{
|
||||
addr_regmask = 1 << (sib & 7);
|
||||
if ((sib & 0x38) != 0x20)
|
||||
addr_regmask |= 1 << ((sib >> 3) & 7);
|
||||
}
|
||||
}
|
||||
else if ((modrm & 0xc7) != 5)
|
||||
{
|
||||
addr_regmask = 1 << (modrm & 7);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((modrm & 0xc7) != 0x06)
|
||||
{
|
||||
switch (modrm & 7)
|
||||
{
|
||||
case 0: addr_regmask = REG_BX | REG_SI; break;
|
||||
case 1: addr_regmask = REG_BX | REG_DI; break;
|
||||
case 2: addr_regmask = REG_BP | REG_SI; break;
|
||||
case 3: addr_regmask = REG_BP | REG_DI; break;
|
||||
case 4: addr_regmask = REG_SI; break;
|
||||
case 5: addr_regmask = REG_DI; break;
|
||||
case 6: addr_regmask = REG_BP; break;
|
||||
case 7: addr_regmask = REG_BX; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (data & IMPL_ESP)
|
||||
addr_regmask |= REGMASK_IMPL_ESP;
|
||||
|
||||
return addr_regmask;
|
||||
}
|
||||
|
||||
static inline uint32_t get_srcdep_mask(uint64_t data, uint32_t fetchdat, int bit8, int op_32)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
if (data & SRCDEP_REG)
|
||||
{
|
||||
int reg = (fetchdat >> 3) & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
if (data & SRCDEP_RM)
|
||||
{
|
||||
int reg = fetchdat & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
mask |= ((data >> SRCDEP_SHIFT) & 0xff);
|
||||
if (data & MMX_SHIFTPACK)
|
||||
mask |= REGMASK_SHIFTPACK;
|
||||
if (data & MMX_MULTIPLY)
|
||||
mask |= REGMASK_MULTIPLY;
|
||||
|
||||
mask |= get_addr_regmask(data, fetchdat, op_32);
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline uint32_t get_dstdep_mask(uint64_t data, uint32_t fetchdat, int bit8)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
if (data & DSTDEP_REG)
|
||||
{
|
||||
int reg = (fetchdat >> 3) & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
if (data & DSTDEP_RM)
|
||||
{
|
||||
int reg = fetchdat & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
mask |= ((data >> DSTDEP_SHIFT) & 0xff);
|
||||
if (data & MMX_SHIFTPACK)
|
||||
mask |= REGMASK_SHIFTPACK;
|
||||
if (data & MMX_MULTIPLY)
|
||||
mask |= REGMASK_MULTIPLY;
|
||||
if (data & IMPL_ESP)
|
||||
mask |= REGMASK_IMPL_ESP | (1 << REG_ESP);
|
||||
|
||||
return mask;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,10 +1,12 @@
|
||||
#include "../ibm.h"
|
||||
#include "../mem.h"
|
||||
#include "cpu.h"
|
||||
#include "x86.h"
|
||||
#include "x86_ops.h"
|
||||
#include "x87.h"
|
||||
#include "../mem.h"
|
||||
#include "codegen.h"
|
||||
#include "codegen_ops.h"
|
||||
#include "codegen_timing_common.h"
|
||||
|
||||
#define CYCLES(c) (int *)c
|
||||
#define CYCLES2(c16, c32) (int *)((-1 & ~0xffff) | c16 | (c32 << 8))
|
||||
@@ -247,14 +249,27 @@ static int *opcode_timings_8x[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
static int *opcode_timings_8x_mod3[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
static int *opcode_timings_81[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
static int *opcode_timings_81_mod3[8] =
|
||||
{
|
||||
&timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_mr, &timing_rm
|
||||
};
|
||||
|
||||
static int timing_count;
|
||||
static uint8_t last_prefix;
|
||||
static uint32_t regmask_modified;
|
||||
|
||||
static __inline int COUNT(int *c, int op_32)
|
||||
static inline int COUNT(int *c, int op_32)
|
||||
{
|
||||
if ((uintptr_t)c <= 10000)
|
||||
return (int)c;
|
||||
return (int)(uintptr_t)c;
|
||||
if (((uintptr_t)c & ~0xffff) == (-1 & ~0xffff))
|
||||
{
|
||||
if (op_32 & 0x100)
|
||||
@@ -266,6 +281,7 @@ static __inline int COUNT(int *c, int op_32)
|
||||
|
||||
void codegen_timing_winchip_block_start()
|
||||
{
|
||||
regmask_modified = 0;
|
||||
}
|
||||
|
||||
void codegen_timing_winchip_start()
|
||||
@@ -283,82 +299,107 @@ void codegen_timing_winchip_prefix(uint8_t prefix, uint32_t fetchdat)
|
||||
void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
int **timings;
|
||||
uint64_t *deps;
|
||||
int mod3 = ((fetchdat & 0xc0) == 0xc0);
|
||||
int bit8 = !(opcode & 1);
|
||||
|
||||
switch (last_prefix)
|
||||
{
|
||||
case 0x0f:
|
||||
timings = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
|
||||
deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
|
||||
break;
|
||||
|
||||
case 0xd8:
|
||||
timings = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
|
||||
deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xd9:
|
||||
timings = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
|
||||
deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
|
||||
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xda:
|
||||
timings = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
|
||||
deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdb:
|
||||
timings = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
|
||||
deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
|
||||
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdc:
|
||||
timings = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
|
||||
deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdd:
|
||||
timings = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
|
||||
deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xde:
|
||||
timings = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
|
||||
deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
case 0xdf:
|
||||
timings = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
|
||||
deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
|
||||
opcode = (opcode >> 3) & 7;
|
||||
break;
|
||||
|
||||
default:
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x80: case 0x81: case 0x82: case 0x83:
|
||||
timings = mod3 ? opcode_timings_mod3 : opcode_timings_8x;
|
||||
if (!mod3)
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
case 0x80: case 0x82: case 0x83:
|
||||
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
|
||||
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0x81:
|
||||
timings = mod3 ? opcode_timings_81_mod3 : opcode_timings_81;
|
||||
deps = mod3 ? opcode_deps_81_mod3 : opcode_deps_81;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
case 0xc0: case 0xc1: case 0xd0: case 0xd1: case 0xd2: case 0xd3:
|
||||
timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
|
||||
deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
case 0xf6:
|
||||
timings = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
|
||||
deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0xf7:
|
||||
timings = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
|
||||
deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
case 0xff:
|
||||
timings = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
|
||||
deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
|
||||
opcode = (fetchdat >> 3) & 7;
|
||||
break;
|
||||
|
||||
default:
|
||||
timings = mod3 ? opcode_timings_mod3 : opcode_timings;
|
||||
deps = mod3 ? opcode_deps_mod3 : opcode_deps;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
timing_count += COUNT(timings[opcode], op_32);
|
||||
if (regmask_modified & get_addr_regmask(deps[opcode], fetchdat, op_32))
|
||||
timing_count++; /*AGI stall*/
|
||||
codegen_block_cycles += timing_count;
|
||||
|
||||
regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8);
|
||||
}
|
||||
|
||||
void codegen_timing_winchip_block_end()
|
||||
|
||||
@@ -1049,6 +1049,15 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
|
||||
case 0xf0: /*LOCK*/
|
||||
break;
|
||||
|
||||
case 0xf2: /*REPNE*/
|
||||
op_table = x86_dynarec_opcodes_REPNE;
|
||||
recomp_op_table = recomp_opcodes_REPNE;
|
||||
break;
|
||||
case 0xf3: /*REPE*/
|
||||
op_table = x86_dynarec_opcodes_REPE;
|
||||
recomp_op_table = recomp_opcodes_REPE;
|
||||
break;
|
||||
|
||||
default:
|
||||
goto generate_call;
|
||||
}
|
||||
@@ -1089,6 +1098,13 @@ generate_call:
|
||||
codegen_block_ins = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ((op_table == x86_opcodes_REPNE || op_table == x86_opcodes_REPE) && !op_table[opcode | op_32])
|
||||
{
|
||||
op_table = x86_dynarec_opcodes;
|
||||
recomp_op_table = recomp_opcodes;
|
||||
}
|
||||
|
||||
if (recomp_op_table && recomp_op_table[(opcode | op_32) & 0x1ff])
|
||||
{
|
||||
uint32_t new_pc = recomp_op_table[(opcode | op_32) & 0x1ff](opcode, fetchdat, op_32, op_pc, block);
|
||||
|
||||
@@ -1977,6 +1977,15 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
|
||||
|
||||
case 0xf0: /*LOCK*/
|
||||
break;
|
||||
|
||||
case 0xf2: /*REPNE*/
|
||||
op_table = x86_dynarec_opcodes_REPNE;
|
||||
recomp_op_table = recomp_opcodes_REPNE;
|
||||
break;
|
||||
case 0xf3: /*REPE*/
|
||||
op_table = x86_dynarec_opcodes_REPE;
|
||||
recomp_op_table = recomp_opcodes_REPE;
|
||||
break;
|
||||
|
||||
default:
|
||||
goto generate_call;
|
||||
@@ -2030,6 +2039,12 @@ generate_call:
|
||||
#endif
|
||||
}
|
||||
|
||||
if ((op_table == x86_opcodes_REPNE || op_table == x86_opcodes_REPE) && !op_table[opcode | op_32])
|
||||
{
|
||||
op_table = x86_dynarec_opcodes;
|
||||
recomp_op_table = recomp_opcodes;
|
||||
}
|
||||
|
||||
if (recomp_op_table && recomp_op_table[(opcode | op_32) & 0x1ff])
|
||||
{
|
||||
uint32_t new_pc = recomp_op_table[(opcode | op_32) & 0x1ff](opcode, fetchdat, op_32, op_pc, block);
|
||||
|
||||
@@ -48,6 +48,8 @@ OpFn *x86_dynarec_opcodes_de_a16;
|
||||
OpFn *x86_dynarec_opcodes_de_a32;
|
||||
OpFn *x86_dynarec_opcodes_df_a16;
|
||||
OpFn *x86_dynarec_opcodes_df_a32;
|
||||
OpFn *x86_dynarec_opcodes_REPE;
|
||||
OpFn *x86_dynarec_opcodes_REPNE;
|
||||
|
||||
OpFn *x86_opcodes;
|
||||
OpFn *x86_opcodes_0f;
|
||||
@@ -67,6 +69,8 @@ OpFn *x86_opcodes_de_a16;
|
||||
OpFn *x86_opcodes_de_a32;
|
||||
OpFn *x86_opcodes_df_a16;
|
||||
OpFn *x86_opcodes_df_a32;
|
||||
OpFn *x86_opcodes_REPE;
|
||||
OpFn *x86_opcodes_REPNE;
|
||||
|
||||
enum
|
||||
{
|
||||
@@ -679,6 +683,10 @@ void cpu_set()
|
||||
pclog("is486 - %i %i\n",is486,cpu_s->cpu_type);
|
||||
|
||||
x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
|
||||
x86_opcodes_REPE = ops_REPE;
|
||||
x86_opcodes_REPNE = ops_REPNE;
|
||||
x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
|
||||
x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
|
||||
|
||||
if (hasfpu)
|
||||
{
|
||||
|
||||
@@ -26,6 +26,8 @@ extern OpFn *x86_dynarec_opcodes_de_a16;
|
||||
extern OpFn *x86_dynarec_opcodes_de_a32;
|
||||
extern OpFn *x86_dynarec_opcodes_df_a16;
|
||||
extern OpFn *x86_dynarec_opcodes_df_a32;
|
||||
extern OpFn *x86_dynarec_opcodes_REPE;
|
||||
extern OpFn *x86_dynarec_opcodes_REPNE;
|
||||
|
||||
extern OpFn dynarec_ops_286[1024];
|
||||
extern OpFn dynarec_ops_286_0f[1024];
|
||||
@@ -87,6 +89,9 @@ extern OpFn dynarec_ops_fpu_686_db_a32[256];
|
||||
extern OpFn dynarec_ops_fpu_686_df_a16[256];
|
||||
extern OpFn dynarec_ops_fpu_686_df_a32[256];
|
||||
|
||||
extern OpFn dynarec_ops_REPE[1024];
|
||||
extern OpFn dynarec_ops_REPNE[1024];
|
||||
|
||||
extern OpFn *x86_opcodes;
|
||||
extern OpFn *x86_opcodes_0f;
|
||||
extern OpFn *x86_opcodes_d8_a16;
|
||||
@@ -105,6 +110,8 @@ extern OpFn *x86_opcodes_de_a16;
|
||||
extern OpFn *x86_opcodes_de_a32;
|
||||
extern OpFn *x86_opcodes_df_a16;
|
||||
extern OpFn *x86_opcodes_df_a32;
|
||||
extern OpFn *x86_opcodes_REPE;
|
||||
extern OpFn *x86_opcodes_REPNE;
|
||||
|
||||
extern OpFn ops_286[1024];
|
||||
extern OpFn ops_286_0f[1024];
|
||||
@@ -167,4 +174,7 @@ extern OpFn ops_fpu_686_db_a32[256];
|
||||
extern OpFn ops_fpu_686_df_a16[256];
|
||||
extern OpFn ops_fpu_686_df_a32[256];
|
||||
|
||||
extern OpFn ops_REPE[1024];
|
||||
extern OpFn ops_REPNE[1024];
|
||||
|
||||
#endif /*_X86_OPS_H*/
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
#define op_seg(name, seg) \
|
||||
#define op_seg(name, seg, opcode_table, normal_opcode_table) \
|
||||
static int op ## name ## _w_a16(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetchdat = fastreadl(cs + cpu_state.pc); \
|
||||
@@ -10,7 +10,9 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
|
||||
CLOCK_CYCLES(4); \
|
||||
PREFETCH_PREFIX(); \
|
||||
\
|
||||
return x86_opcodes[fetchdat & 0xff](fetchdat >> 8); \
|
||||
if (opcode_table[fetchdat & 0xff]) \
|
||||
return opcode_table[fetchdat & 0xff](fetchdat >> 8); \
|
||||
return normal_opcode_table[fetchdat & 0xff](fetchdat >> 8); \
|
||||
} \
|
||||
\
|
||||
static int op ## name ## _l_a16(uint32_t fetchdat) \
|
||||
@@ -24,7 +26,9 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
|
||||
CLOCK_CYCLES(4); \
|
||||
PREFETCH_PREFIX(); \
|
||||
\
|
||||
return x86_opcodes[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
|
||||
if (opcode_table[(fetchdat & 0xff) | 0x100]) \
|
||||
return opcode_table[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
|
||||
return normal_opcode_table[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
|
||||
} \
|
||||
\
|
||||
static int op ## name ## _w_a32(uint32_t fetchdat) \
|
||||
@@ -38,7 +42,9 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
|
||||
CLOCK_CYCLES(4); \
|
||||
PREFETCH_PREFIX(); \
|
||||
\
|
||||
return x86_opcodes[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
|
||||
if (opcode_table[(fetchdat & 0xff) | 0x200]) \
|
||||
return opcode_table[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
|
||||
return normal_opcode_table[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
|
||||
} \
|
||||
\
|
||||
static int op ## name ## _l_a32(uint32_t fetchdat) \
|
||||
@@ -52,15 +58,31 @@ static int op ## name ## _l_a32(uint32_t fetchdat) \
|
||||
CLOCK_CYCLES(4); \
|
||||
PREFETCH_PREFIX(); \
|
||||
\
|
||||
return x86_opcodes[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
|
||||
if (opcode_table[(fetchdat & 0xff) | 0x300]) \
|
||||
return opcode_table[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
|
||||
return normal_opcode_table[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
|
||||
}
|
||||
|
||||
op_seg(CS, _cs)
|
||||
op_seg(DS, _ds)
|
||||
op_seg(ES, _es)
|
||||
op_seg(FS, _fs)
|
||||
op_seg(GS, _gs)
|
||||
op_seg(SS, _ss)
|
||||
op_seg(CS, _cs, x86_opcodes, x86_opcodes)
|
||||
op_seg(DS, _ds, x86_opcodes, x86_opcodes)
|
||||
op_seg(ES, _es, x86_opcodes, x86_opcodes)
|
||||
op_seg(FS, _fs, x86_opcodes, x86_opcodes)
|
||||
op_seg(GS, _gs, x86_opcodes, x86_opcodes)
|
||||
op_seg(SS, _ss, x86_opcodes, x86_opcodes)
|
||||
|
||||
op_seg(CS_REPE, _cs, x86_opcodes_REPE, x86_opcodes)
|
||||
op_seg(DS_REPE, _ds, x86_opcodes_REPE, x86_opcodes)
|
||||
op_seg(ES_REPE, _es, x86_opcodes_REPE, x86_opcodes)
|
||||
op_seg(FS_REPE, _fs, x86_opcodes_REPE, x86_opcodes)
|
||||
op_seg(GS_REPE, _gs, x86_opcodes_REPE, x86_opcodes)
|
||||
op_seg(SS_REPE, _ss, x86_opcodes_REPE, x86_opcodes)
|
||||
|
||||
op_seg(CS_REPNE, _cs, x86_opcodes_REPNE, x86_opcodes)
|
||||
op_seg(DS_REPNE, _ds, x86_opcodes_REPNE, x86_opcodes)
|
||||
op_seg(ES_REPNE, _es, x86_opcodes_REPNE, x86_opcodes)
|
||||
op_seg(FS_REPNE, _fs, x86_opcodes_REPNE, x86_opcodes)
|
||||
op_seg(GS_REPNE, _gs, x86_opcodes_REPNE, x86_opcodes)
|
||||
op_seg(SS_REPNE, _ss, x86_opcodes_REPNE, x86_opcodes)
|
||||
|
||||
static int op_66(uint32_t fetchdat) /*Data size select*/
|
||||
{
|
||||
@@ -84,3 +106,56 @@ static int op_67(uint32_t fetchdat) /*Address size select*/
|
||||
PREFETCH_PREFIX();
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
|
||||
static int op_66_REPE(uint32_t fetchdat) /*Data size select*/
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
|
||||
CLOCK_CYCLES(2);
|
||||
PREFETCH_PREFIX();
|
||||
if (x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32])
|
||||
return x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
static int op_67_REPE(uint32_t fetchdat) /*Address size select*/
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
|
||||
CLOCK_CYCLES(2);
|
||||
PREFETCH_PREFIX();
|
||||
if (x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32])
|
||||
return x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
static int op_66_REPNE(uint32_t fetchdat) /*Data size select*/
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
|
||||
CLOCK_CYCLES(2);
|
||||
PREFETCH_PREFIX();
|
||||
if (x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32])
|
||||
return x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
static int op_67_REPNE(uint32_t fetchdat) /*Address size select*/
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
|
||||
CLOCK_CYCLES(2);
|
||||
PREFETCH_PREFIX();
|
||||
if (x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32])
|
||||
return x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
|
||||
@@ -1,12 +1,643 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
extern int trap;
|
||||
|
||||
#define REP_OPS(size, CNT_REG, SRC_REG, DEST_REG) \
|
||||
static int opREP_INSB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint8_t temp; \
|
||||
\
|
||||
check_io_perm(DX); \
|
||||
temp = inb(DX); \
|
||||
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) DEST_REG--; \
|
||||
else DEST_REG++; \
|
||||
CNT_REG--; \
|
||||
cycles -= 15; \
|
||||
reads++; writes++; total_cycles += 15; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_INSW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
\
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
temp = inw(DX); \
|
||||
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) DEST_REG -= 2; \
|
||||
else DEST_REG += 2; \
|
||||
CNT_REG--; \
|
||||
cycles -= 15; \
|
||||
reads++; writes++; total_cycles += 15; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_INSL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
\
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
check_io_perm(DX+2); \
|
||||
check_io_perm(DX+3); \
|
||||
temp = inl(DX); \
|
||||
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) DEST_REG -= 4; \
|
||||
else DEST_REG += 4; \
|
||||
CNT_REG--; \
|
||||
cycles -= 15; \
|
||||
reads++; writes++; total_cycles += 15; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, writes, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
\
|
||||
static int opREP_OUTSB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
check_io_perm(DX); \
|
||||
outb(DX, temp); \
|
||||
if (flags & D_FLAG) SRC_REG--; \
|
||||
else SRC_REG++; \
|
||||
CNT_REG--; \
|
||||
cycles -= 14; \
|
||||
reads++; writes++; total_cycles += 14; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_OUTSW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
outw(DX, temp); \
|
||||
if (flags & D_FLAG) SRC_REG -= 2; \
|
||||
else SRC_REG += 2; \
|
||||
CNT_REG--; \
|
||||
cycles -= 14; \
|
||||
reads++; writes++; total_cycles += 14; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_OUTSL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
check_io_perm(DX+2); \
|
||||
check_io_perm(DX+3); \
|
||||
outl(DX, temp); \
|
||||
if (flags & D_FLAG) SRC_REG -= 4; \
|
||||
else SRC_REG += 4; \
|
||||
CNT_REG--; \
|
||||
cycles -= 14; \
|
||||
reads++; writes++; total_cycles += 14; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, writes, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
\
|
||||
static int opREP_MOVSB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
uint8_t temp; \
|
||||
\
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
|
||||
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
|
||||
else { DEST_REG++; SRC_REG++; } \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 3 : 4; \
|
||||
ins++; \
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
ins--; \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_MOVSW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
\
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
|
||||
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
|
||||
else { DEST_REG += 2; SRC_REG += 2; } \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 3 : 4; \
|
||||
ins++; \
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
ins--; \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_MOVSL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, writes = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
\
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
|
||||
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
|
||||
else { DEST_REG += 4; SRC_REG += 4; } \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 3 : 4; \
|
||||
ins++; \
|
||||
reads++; writes++; total_cycles += is486 ? 3 : 4; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
ins--; \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static int opREP_STOSB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int writes = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
|
||||
writememb(es, DEST_REG, AL); if (cpu_state.abrt) return 1; \
|
||||
if (flags & D_FLAG) DEST_REG--; \
|
||||
else DEST_REG++; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 4 : 5; \
|
||||
writes++; total_cycles += is486 ? 4 : 5; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_STOSW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int writes = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG+1); \
|
||||
writememw(es, DEST_REG, AX); if (cpu_state.abrt) return 1; \
|
||||
if (flags & D_FLAG) DEST_REG -= 2; \
|
||||
else DEST_REG += 2; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 4 : 5; \
|
||||
writes++; total_cycles += is486 ? 4 : 5; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, writes, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_STOSL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int writes = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG+3); \
|
||||
writememl(es, DEST_REG, EAX); if (cpu_state.abrt) return 1; \
|
||||
if (flags & D_FLAG) DEST_REG -= 4; \
|
||||
else DEST_REG += 4; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 4 : 5; \
|
||||
writes++; total_cycles += is486 ? 4 : 5; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, 0, writes, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
\
|
||||
static int opREP_LODSB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
AL = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
if (flags & D_FLAG) SRC_REG--; \
|
||||
else SRC_REG++; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 4 : 5; \
|
||||
reads++; total_cycles += is486 ? 4 : 5; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_LODSW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
if (flags & D_FLAG) SRC_REG -= 2; \
|
||||
else SRC_REG += 2; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 4 : 5; \
|
||||
reads++; total_cycles += is486 ? 4 : 5; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_LODSL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
if (flags & D_FLAG) SRC_REG -= 4; \
|
||||
else SRC_REG += 4; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 4 : 5; \
|
||||
reads++; total_cycles += is486 ? 4 : 5; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
|
||||
|
||||
#define REP_OPS_CMPS_SCAS(size, CNT_REG, SRC_REG, DEST_REG, FV) \
|
||||
static int opREP_CMPSB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0, tempz; \
|
||||
\
|
||||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
|
||||
uint8_t temp2 = readmemb(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
|
||||
else { DEST_REG++; SRC_REG++; } \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 7 : 9; \
|
||||
reads += 2; total_cycles += is486 ? 7 : 9; \
|
||||
setsub8(temp, temp2); \
|
||||
tempz = (ZF_SET()) ? 1 : 0; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_CMPSW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0, tempz; \
|
||||
\
|
||||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
|
||||
uint16_t temp2 = readmemw(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
|
||||
else { DEST_REG += 2; SRC_REG += 2; } \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 7 : 9; \
|
||||
reads += 2; total_cycles += is486 ? 7 : 9; \
|
||||
setsub16(temp, temp2); \
|
||||
tempz = (ZF_SET()) ? 1 : 0; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_CMPSL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0, tempz; \
|
||||
\
|
||||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
|
||||
uint32_t temp2 = readmeml(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
|
||||
else { DEST_REG += 4; SRC_REG += 4; } \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 7 : 9; \
|
||||
reads += 2; total_cycles += is486 ? 7 : 9; \
|
||||
setsub32(temp, temp2); \
|
||||
tempz = (ZF_SET()) ? 1 : 0; \
|
||||
} \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
\
|
||||
static int opREP_SCASB_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0, tempz; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
tempz = FV; \
|
||||
while ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint8_t temp = readmemb(es, DEST_REG); if (cpu_state.abrt) break;\
|
||||
setsub8(AL, temp); \
|
||||
tempz = (ZF_SET()) ? 1 : 0; \
|
||||
if (flags & D_FLAG) DEST_REG--; \
|
||||
else DEST_REG++; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 5 : 8; \
|
||||
reads++; total_cycles += is486 ? 5 : 8; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
ins--; \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_SCASW_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0, tempz; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
tempz = FV; \
|
||||
while ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
|
||||
setsub16(AX, temp); \
|
||||
tempz = (ZF_SET()) ? 1 : 0; \
|
||||
if (flags & D_FLAG) DEST_REG -= 2; \
|
||||
else DEST_REG += 2; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 5 : 8; \
|
||||
reads++; total_cycles += is486 ? 5 : 8; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
ins--; \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opREP_SCASL_ ## size(uint32_t fetchdat) \
|
||||
{ \
|
||||
int reads = 0, total_cycles = 0, tempz; \
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
tempz = FV; \
|
||||
while ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
|
||||
setsub32(EAX, temp); \
|
||||
tempz = (ZF_SET()) ? 1 : 0; \
|
||||
if (flags & D_FLAG) DEST_REG -= 4; \
|
||||
else DEST_REG += 4; \
|
||||
CNT_REG--; \
|
||||
cycles -= is486 ? 5 : 8; \
|
||||
reads++; total_cycles += is486 ? 5 : 8; \
|
||||
ins++; \
|
||||
if (cycles < cycles_end) \
|
||||
break; \
|
||||
} \
|
||||
ins--; \
|
||||
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
CPU_BLOCK_END(); \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
return 1; \
|
||||
} \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
REP_OPS(a16, CX, SI, DI)
|
||||
REP_OPS(a32, ECX, ESI, EDI)
|
||||
REP_OPS_CMPS_SCAS(a16_NE, CX, SI, DI, 0)
|
||||
REP_OPS_CMPS_SCAS(a16_E, CX, SI, DI, 1)
|
||||
REP_OPS_CMPS_SCAS(a32_NE, ECX, ESI, EDI, 0)
|
||||
REP_OPS_CMPS_SCAS(a32_E, ECX, ESI, EDI, 1)
|
||||
|
||||
static int opREPNE(uint32_t fetchdat)
|
||||
{
|
||||
return rep386(0);
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
PREFETCH_PREFIX();
|
||||
if (x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32])
|
||||
return x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
static int opREPE(uint32_t fetchdat)
|
||||
{
|
||||
return rep386(1);
|
||||
}
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
PREFETCH_PREFIX();
|
||||
if (x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32])
|
||||
return x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
|
||||
149
src/CPU/x86seg.c
149
src/CPU/x86seg.c
@@ -2133,7 +2133,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
|
||||
base=segdat[1]|((segdat[2]&0xFF)<<16);
|
||||
limit=segdat[0];
|
||||
|
||||
if(is386)
|
||||
{
|
||||
base |= (segdat[3]>>8)<<24;
|
||||
@@ -2144,7 +2143,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
{
|
||||
if (limit < 103)
|
||||
{
|
||||
pclog("32-bit TSS %04X limit less than 103.\n", seg);
|
||||
x86ts(NULL, seg);
|
||||
return;
|
||||
}
|
||||
@@ -2161,7 +2159,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
if (cpu_state.abrt) return;
|
||||
|
||||
if (optype==IRET) flags&=~NT_FLAG;
|
||||
|
||||
|
||||
cpu_386_flags_rebuild();
|
||||
writememl(tr.base,0x1C,cr3);
|
||||
writememl(tr.base,0x20,cpu_state.pc);
|
||||
@@ -2200,14 +2198,14 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
if (cpu_state.abrt)
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
new_cr3=readmeml(base,0x1C);
|
||||
new_pc=readmeml(base,0x20);
|
||||
new_flags=readmeml(base,0x24);
|
||||
|
||||
if (optype == OPTYPE_INT || optype == CALL)
|
||||
new_flags |= NT_FLAG;
|
||||
|
||||
|
||||
new_eax=readmeml(base,0x28);
|
||||
new_ecx=readmeml(base,0x2C);
|
||||
new_edx=readmeml(base,0x30);
|
||||
@@ -2245,70 +2243,72 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
}
|
||||
ldt.base=(readmemw(0,templ+2))|(readmemb(0,templ+4)<<16)|(readmemb(0,templ+7)<<24);
|
||||
|
||||
if (eflags&VM_FLAG)
|
||||
if (eflags & VM_FLAG)
|
||||
{
|
||||
x86gpf(NULL,0);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!(new_cs&~3))
|
||||
{
|
||||
x86ts(NULL,0);
|
||||
return;
|
||||
}
|
||||
addr=new_cs&~7;
|
||||
if (new_cs&4)
|
||||
{
|
||||
if (addr>=ldt.limit)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
addr+=ldt.base;
|
||||
loadcs(new_cs);
|
||||
set_use32(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (addr>=gdt.limit)
|
||||
if (!(new_cs&~3))
|
||||
{
|
||||
x86ts(NULL,0);
|
||||
return;
|
||||
}
|
||||
addr=new_cs&~7;
|
||||
if (new_cs&4)
|
||||
{
|
||||
if (addr>=ldt.limit)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
addr+=ldt.base;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (addr>=gdt.limit)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
addr+=gdt.base;
|
||||
}
|
||||
segdat2[0]=readmemw(0,addr);
|
||||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6);
|
||||
if (!(segdat2[2]&0x8000))
|
||||
{
|
||||
x86np("TS loading CS not present\n", new_cs & 0xfffc);
|
||||
return;
|
||||
}
|
||||
switch (segdat2[2]&0x1F00)
|
||||
{
|
||||
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
|
||||
if ((new_cs&3) != DPL2)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
|
||||
if ((new_cs&3) < DPL2)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
addr+=gdt.base;
|
||||
}
|
||||
segdat2[0]=readmemw(0,addr);
|
||||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6);
|
||||
if (!(segdat2[2]&0x8000))
|
||||
{
|
||||
x86np("TS loading CS not present\n", new_cs & 0xfffc);
|
||||
return;
|
||||
}
|
||||
switch (segdat2[2]&0x1F00)
|
||||
{
|
||||
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
|
||||
if ((new_cs&3) != DPL2)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
|
||||
if ((new_cs&3) < DPL2)
|
||||
{
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
|
||||
CS=new_cs;
|
||||
do_seg_load(&_cs, segdat2);
|
||||
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
|
||||
set_use32(segdat2[3] & 0x40);
|
||||
CS=new_cs;
|
||||
do_seg_load(&_cs, segdat2);
|
||||
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
|
||||
set_use32(segdat2[3] & 0x40);
|
||||
}
|
||||
|
||||
EAX=new_eax;
|
||||
ECX=new_ecx;
|
||||
@@ -2319,28 +2319,20 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
ESI=new_esi;
|
||||
EDI=new_edi;
|
||||
|
||||
if (output) pclog("Load ES %04X\n",new_es);
|
||||
loadseg(new_es,&_es);
|
||||
if (output) pclog("Load SS %04X\n",new_ss);
|
||||
loadseg(new_ss,&_ss);
|
||||
if (output) pclog("Load DS %04X\n",new_ds);
|
||||
loadseg(new_ds,&_ds);
|
||||
if (output) pclog("Load FS %04X\n",new_fs);
|
||||
loadseg(new_fs,&_fs);
|
||||
if (output) pclog("Load GS %04X\n",new_gs);
|
||||
loadseg(new_gs,&_gs);
|
||||
|
||||
if (output) pclog("Resuming at %04X:%08X\n",CS,cpu_state.pc);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (limit < 43)
|
||||
{
|
||||
pclog("16-bit TSS %04X limit less than 43.\n", seg);
|
||||
x86ts(NULL, seg);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (optype==JMP || optype==CALL || optype==OPTYPE_INT)
|
||||
{
|
||||
if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
|
||||
@@ -2353,7 +2345,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
if (cpu_state.abrt) return;
|
||||
|
||||
if (optype==IRET) flags&=~NT_FLAG;
|
||||
|
||||
|
||||
cpu_386_flags_rebuild();
|
||||
writememw(tr.base,0x0E,cpu_state.pc);
|
||||
writememw(tr.base,0x10,flags);
|
||||
@@ -2392,15 +2384,13 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
|
||||
new_pc=readmemw(base,0x0E);
|
||||
new_flags=readmemw(base,0x10);
|
||||
|
||||
if (optype == OPTYPE_INT || optype == CALL)
|
||||
new_flags |= NT_FLAG;
|
||||
|
||||
|
||||
new_eax=readmemw(base,0x12);
|
||||
new_ecx=readmemw(base,0x14);
|
||||
new_edx=readmemw(base,0x16);
|
||||
new_ebx=readmemw(base,0x18);
|
||||
|
||||
new_esp=readmemw(base,0x1A);
|
||||
new_ebp=readmemw(base,0x1C);
|
||||
new_esi=readmemw(base,0x1E);
|
||||
@@ -2434,7 +2424,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
|
||||
if (!(new_cs&~3))
|
||||
{
|
||||
pclog("TS loading null CS\n");
|
||||
x86ts(NULL,0);
|
||||
return;
|
||||
}
|
||||
@@ -2443,7 +2432,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
{
|
||||
if (addr>=ldt.limit)
|
||||
{
|
||||
pclog("Bigger than LDT limit %04X %04X %04X TS\n",new_cs,ldt.limit,addr);
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
@@ -2453,7 +2441,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
{
|
||||
if (addr>=gdt.limit)
|
||||
{
|
||||
pclog("Bigger than GDT limit %04X %04X TS\n",new_cs,gdt.limit);
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
@@ -2465,7 +2452,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
segdat2[3]=readmemw(0,addr+6);
|
||||
if (!(segdat2[2]&0x8000))
|
||||
{
|
||||
pclog("TS loading CS not present\n");
|
||||
x86np("TS loading CS not present\n", new_cs & 0xfffc);
|
||||
return;
|
||||
}
|
||||
@@ -2474,7 +2460,6 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
|
||||
if ((new_cs&3) != DPL2)
|
||||
{
|
||||
pclog("TS load CS non-conforming RPL != DPL");
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
@@ -2482,13 +2467,11 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
|
||||
if ((new_cs&3) < DPL2)
|
||||
{
|
||||
pclog("TS load CS non-conforming RPL < DPL");
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
pclog("TS load CS not code segment\n");
|
||||
x86ts(NULL,new_cs&~3);
|
||||
return;
|
||||
}
|
||||
@@ -2507,19 +2490,14 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
ESI=new_esi | 0xFFFF0000;
|
||||
EDI=new_edi | 0xFFFF0000;
|
||||
|
||||
if (output) pclog("Load ES %04X\n",new_es);
|
||||
loadseg(new_es,&_es);
|
||||
if (output) pclog("Load SS %04X\n",new_ss);
|
||||
loadseg(new_ss,&_ss);
|
||||
if (output) pclog("Load DS %04X\n",new_ds);
|
||||
loadseg(new_ds,&_ds);
|
||||
if (is386)
|
||||
{
|
||||
loadseg(0,&_fs);
|
||||
loadseg(0,&_gs);
|
||||
}
|
||||
|
||||
if (output) pclog("Resuming at %04X:%08X\n",CS,cpu_state.pc);
|
||||
}
|
||||
|
||||
tr.seg=seg;
|
||||
@@ -2527,4 +2505,3 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
||||
tr.limit=limit;
|
||||
tr.access=segdat[2]>>8;
|
||||
}
|
||||
|
||||
|
||||
@@ -130,6 +130,7 @@ endif
|
||||
|
||||
|
||||
ifeq ($(WALTJE), y)
|
||||
OPENDIR = win_opendir.o
|
||||
SERIAL = serial.o
|
||||
WSERIAL = win_serial.o
|
||||
WFLAGS = -DWALTJE
|
||||
@@ -143,7 +144,8 @@ MAINOBJ = pc.o config.o device.o timer.o dma.o io.o nmi.o pic.o \
|
||||
memregs.o intel_flash.o rtc.o nvr.o ps2_nvr.o
|
||||
CPUOBJ = cpu.o 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o \
|
||||
codegen.o \
|
||||
codegen_ops.o codegen_timing_486.o \
|
||||
codegen_ops.o \
|
||||
codegen_timing_common.o codegen_timing_486.o \
|
||||
codegen_timing_686.o codegen_timing_pentium.o \
|
||||
codegen_timing_winchip.o $(PLATCG) \
|
||||
x86seg.o x87.o
|
||||
@@ -156,7 +158,7 @@ SYSOBJ = model.o \
|
||||
scat.o \
|
||||
sis496.o \
|
||||
wd76c10.o \
|
||||
acer386sx.o acerm3a.o amstrad.o \
|
||||
acer386sx.o amstrad.o \
|
||||
compaq.o laserxt.o jim.o \
|
||||
olivetti_m24.o ps1.o ps2.o ps2_mca.o \
|
||||
tandy_eeprom.o tandy_rom.o
|
||||
@@ -240,7 +242,7 @@ VIDOBJ = video.o \
|
||||
WINOBJ = win.o \
|
||||
win_ddraw.o win_ddraw_fs.o win_ddraw_screenshot.o \
|
||||
win_d3d.o win_d3d_fs.o \
|
||||
win_language.o win_status.o win_opendir.o win_dynld.o \
|
||||
win_language.o win_status.o $(OPENDIR) win_dynld.o \
|
||||
win_video.o $(WSERIAL) win_keyboard.o win_mouse.o \
|
||||
win_iodev.o win_joystick.o win_midi.o \
|
||||
win_settings.o win_deviceconfig.o win_joystickconfig.o \
|
||||
|
||||
@@ -111,7 +111,7 @@ network_attach(void *dev, uint8_t *mac, NETRXCB rx)
|
||||
case NET_TYPE_PCAP:
|
||||
ret = network_pcap_setup(mac, rx, dev);
|
||||
if (ret < 0) {
|
||||
plat_msgbox_error(IDS_2219);
|
||||
plat_msgbox_error(IDS_2139);
|
||||
network_type = NET_TYPE_NONE;
|
||||
}
|
||||
break;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,69 +1,300 @@
|
||||
/* All these defines are in samples, not in bytes. */
|
||||
#define EMU8K_MEM_ADDRESS_MASK 0xFFFFFF
|
||||
#define EMU8K_RAM_MEM_START 0x200000
|
||||
#define EMU8K_ROM_MEM_1MB_END 0x80000
|
||||
#define EMU8K_FM_MEM_ADDRESS 0xFFFFE0
|
||||
#define EMU8K_RAM_POINTERS_MASK 0x3F
|
||||
|
||||
/*
|
||||
Everything in this file assumes little endian
|
||||
|
||||
used for the increment of oscillator position */
|
||||
typedef struct emu8k_mem_internal_t {
|
||||
union {
|
||||
uint64_t addr;
|
||||
struct {
|
||||
uint16_t fract_lw_address;
|
||||
uint16_t fract_address;
|
||||
uint32_t int_address;
|
||||
};
|
||||
};
|
||||
} emu8k_mem_internal_t;
|
||||
|
||||
/* used for access to ram pointers from oscillator position. */
|
||||
typedef struct emu8k_mem_pointers_t {
|
||||
union {
|
||||
uint32_t addr;
|
||||
struct {
|
||||
uint16_t lw_address;
|
||||
uint8_t hb_address;
|
||||
uint8_t unused_address;
|
||||
};
|
||||
};
|
||||
} emu8k_mem_pointers_t;
|
||||
|
||||
/*
|
||||
* From the Soundfount 2.0 fileformat Spec.:
|
||||
*
|
||||
An envelope generates a control signal in six phases.
|
||||
When key-on occurs, a delay period begins during which the envelope value is zero.
|
||||
The envelope then rises in a convex curve to a value of one during the attack phase.
|
||||
" Note that the attack is convex; the curve is nominally such that when applied to a
|
||||
decibel or semitone parameter, the result is linear in amplitude or Hz respectively"
|
||||
|
||||
When a value of one is reached, the envelope enters a hold phase during which it remains at one.
|
||||
When the hold phase ends, the envelope enters a decay phase during which its value decreases linearly to a sustain level.
|
||||
" For the Volume Envelope, the decay phase linearly ramps toward the sustain level, causing a constant dB change for each time unit. "
|
||||
When the sustain level is reached, the envelope enters sustain phase, during which the envelope stays at the sustain level.
|
||||
|
||||
Whenever a key-off occurs, the envelope immediately enters a release phase during which the value linearly ramps from the current value to zero.
|
||||
" For the Volume Envelope, the release phase linearly ramps toward zero from the current level, causing a constant dB change for each time unit"
|
||||
|
||||
When zero is reached, the envelope value remains at zero.
|
||||
|
||||
Modulation of pitch and filter cutoff are in octaves, semitones, and cents.
|
||||
These parameters can be modulated to varying degree, either positively or negatively, by the modulation envelope.
|
||||
The degree of modulation is specified in cents for the full-scale attack peak.
|
||||
|
||||
The volume envelope operates in dB, with the attack peak providing a full scale output, appropriately scaled by the initial volume.
|
||||
The zero value, however, is actually zero gain.
|
||||
The implementation in the EMU8000 provides for 96 dB of amplitude control.
|
||||
When 96 dB of attenuation is reached in the final gain amplifier, an abrupt jump to zero gain (infinite dB of attenuation) occurs. In a 16-bit system, this jump is inaudible
|
||||
*/
|
||||
/* It seems that the envelopes don't really have a decay/release stage,
|
||||
but instead they have a volume ramper that can be triggered
|
||||
automatically (after hold period), or manually (by activating release)
|
||||
and the "sustain" value is the target of any of both cases.
|
||||
Some programs like cubic player and AWEAmp use this, and it was
|
||||
described in the following way in Vince Vu/Judge Dredd's awe32p10.txt:
|
||||
If the MSB (most significant bit or bit 15) of this register is set,
|
||||
the Decay/Release will begin immediately, overriding the Delay, Attack,
|
||||
and Hold. Otherwise the Decay/Release will wait until the Delay, Attack,
|
||||
and Hold are finished. If you set the MSB of this register, you can use
|
||||
it as a volume ramper, as on the GUS. The upper byte (except the MSB),
|
||||
contains the destination volume, and the lower byte contains the ramp time. */
|
||||
|
||||
/* attack_amount is linear amplitude (added directly to value). ramp_amount_db is linear dB (added directly to value too, but needs conversion to get linear amplitude).
|
||||
value range is 21bits for both, linear amplitude being 1<<21 = 0dBFS and 0 = -96dBFS (which is shortcut to silence), and db amplutide being 0 = 0dBFS and -(1<<21) = -96dBFS (which is shortcut to silence). This allows to operate db values by simply adding them. */
|
||||
typedef struct emu8k_envelope_t {
|
||||
int state;
|
||||
int32_t delay_samples, hold_samples, attack_samples;
|
||||
int32_t value_amp_hz, value_db_oct;
|
||||
int32_t sustain_value_db_oct;
|
||||
int32_t attack_amount_amp_hz, ramp_amount_db_oct;
|
||||
} emu8k_envelope_t;
|
||||
|
||||
|
||||
|
||||
/* Chorus Params */
|
||||
typedef struct {
|
||||
uint16_t FbkLevReg; /* Feedback Level (0xE600-0xE6FF) */
|
||||
uint16_t Delay; /* Delay (0-0x0DA3) [1/44100 sec] */
|
||||
uint16_t LfoDepReg; /* LFO Depth (0xBC00-0xBCFF) */
|
||||
uint32_t DelayR; /* Right Delay (0-0xFFFFFFFF) [1/256/44100 sec] */
|
||||
uint32_t LfoFreq; /* LFO Frequency (0-0xFFFFFFFF) */
|
||||
} emu8k_chorus_t;
|
||||
|
||||
typedef struct {
|
||||
int32_t write;
|
||||
int32_t feedback;
|
||||
int32_t delay_samples_central;
|
||||
int32_t lfodepth_samples;
|
||||
emu8k_mem_internal_t delay_offset_samples_right;
|
||||
emu8k_mem_internal_t lfo_inc;
|
||||
emu8k_mem_internal_t lfo_pos;
|
||||
|
||||
int32_t chorus_left_buffer[SOUNDBUFLEN];
|
||||
int32_t chorus_right_buffer[SOUNDBUFLEN];
|
||||
|
||||
} emu8k_chorus_eng_t;
|
||||
|
||||
typedef struct emu8k_voice_t
|
||||
{
|
||||
union {
|
||||
uint32_t cpf;
|
||||
struct {
|
||||
uint16_t cpf_curr_frac_addr; /* fractional part of the playing cursor. */
|
||||
uint16_t cpf_curr_pitch; /* 0x4000 = no shift. Linear increment */
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint32_t ptrx;
|
||||
struct {
|
||||
uint8_t ptrx_pan_aux;
|
||||
uint8_t ptrx_revb_send;
|
||||
uint16_t ptrx_pit_target; /* target pitch to which slide at curr_pitch speed. */
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint32_t cvcf;
|
||||
struct {
|
||||
uint16_t cvcf_curr_filt_ctoff;
|
||||
uint16_t cvcf_curr_volume;
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint32_t vtft;
|
||||
struct {
|
||||
uint16_t vtft_filter_target;
|
||||
uint16_t vtft_vol_target; /* written to by the envelope engine. */
|
||||
};
|
||||
};
|
||||
/* These registers are used at least by the Windows drivers, and seem to be resetting
|
||||
something, similarly to targets and current, but... of what?
|
||||
what is curious is that if they are already zero, they are not written to, so it really
|
||||
looks like they are information about the status of the channel. (lfo position maybe?) */
|
||||
uint32_t unknown_data0_4;
|
||||
uint32_t unknown_data0_5;
|
||||
union {
|
||||
uint32_t psst;
|
||||
struct {
|
||||
uint16_t psst_lw_address;
|
||||
uint8_t psst_hw_address;
|
||||
uint8_t psst_pan;
|
||||
};
|
||||
#define PSST_LOOP_START_MASK 0x00FFFFFF /* In samples, i.e. uint16_t array[BOARD_RAM/2]; */
|
||||
};
|
||||
union {
|
||||
uint32_t csl;
|
||||
struct {
|
||||
uint16_t csl_lw_address;
|
||||
uint8_t csl_hw_address;
|
||||
uint8_t csl_chor_send;
|
||||
};
|
||||
#define CSL_LOOP_END_MASK 0x00FFFFFF /* In samples, i.e. uint16_t array[BOARD_RAM/2]; */
|
||||
};
|
||||
union {
|
||||
uint32_t ccca;
|
||||
struct {
|
||||
uint16_t ccca_lw_addr;
|
||||
uint8_t ccca_hb_addr;
|
||||
uint8_t ccca_qcontrol;
|
||||
};
|
||||
};
|
||||
#define CCCA_FILTQ_GET(ccca) (ccca>>28)
|
||||
#define CCCA_FILTQ_SET(ccca,q) ccca = (ccca&0x0FFFFFFF) | (q<<28)
|
||||
/* Bit 27 should always be zero */
|
||||
#define CCCA_DMA_ACTIVE(ccca) (ccca&0x04000000)
|
||||
#define CCCA_DMA_WRITE_MODE(ccca) (ccca&0x02000000)
|
||||
#define CCCA_DMA_WRITE_RIGHT(ccca) (ccca&0x01000000)
|
||||
|
||||
uint16_t envvol;
|
||||
#define ENVVOL_NODELAY(envol) (envvol&0x8000)
|
||||
/* Verified with a soundfont bank. 7FFF is the minimum delay time, and 0 is the max delay time */
|
||||
#define ENVVOL_TO_EMU_SAMPLES(envvol) (envvol&0x8000) ? 0 : ((0x8000-(envvol&0x7FFF)) <<5)
|
||||
|
||||
uint16_t dcysusv;
|
||||
#define DCYSUSV_IS_RELEASE(dcysusv) (dcysusv&0x8000)
|
||||
#define DCYSUSV_GENERATOR_ENGINE_ON(dcysusv) !(dcysusv&0x0080)
|
||||
#define DCYSUSV_SUSVALUE_GET(dcysusv) ((dcysusv>>8)&0x7F)
|
||||
/* Inverting the range compared to documentation because the envelope runs from 0dBFS = 0 to -96dBFS = (1 <<21) */
|
||||
#define DCYSUSV_SUS_TO_ENV_RANGE(susvalue) (((0x7F-susvalue) << 21)/0x7F)
|
||||
#define DCYSUSV_DECAYRELEASE_GET(dcysusv) (dcysusv&0x7F)
|
||||
|
||||
uint16_t envval;
|
||||
#define ENVVAL_NODELAY(enval) (envval&0x8000)
|
||||
/* Verified with a soundfont bank. 7FFF is the minimum delay time, and 0 is the max delay time */
|
||||
#define ENVVAL_TO_EMU_SAMPLES(envval)(envval&0x8000) ? 0 : ((0x8000-(envval&0x7FFF)) <<5)
|
||||
|
||||
uint16_t dcysus;
|
||||
#define DCYSUS_IS_RELEASE(dcysus) (dcysus&0x8000)
|
||||
#define DCYSUS_SUSVALUE_GET(dcysus) ((dcysus>>8)&0x7F)
|
||||
#define DCYSUS_SUS_TO_ENV_RANGE(susvalue) ((susvalue << 21)/0x7F)
|
||||
#define DCYSUS_DECAYRELEASE_GET(dcysus) (dcysus&0x7F)
|
||||
|
||||
uint16_t atkhldv;
|
||||
#define ATKHLDV_TRIGGER(atkhldv) !(atkhldv&0x8000)
|
||||
#define ATKHLDV_HOLD(atkhldv) ((atkhldv>>8)&0x7F)
|
||||
#define ATKHLDV_HOLD_TO_EMU_SAMPLES(atkhldv) (4096*(0x7F-((atkhldv>>8)&0x7F)))
|
||||
#define ATKHLDV_ATTACK(atkhldv) (atkhldv&0x7F)
|
||||
|
||||
uint16_t lfo1val, lfo2val;
|
||||
#define LFOxVAL_NODELAY(lfoxval) (lfoxval&0x8000)
|
||||
#define LFOxVAL_TO_EMU_SAMPLES(lfoxval) (lfoxval&0x8000) ? 0 : ((0x8000-(lfoxval&0x7FFF)) <<5)
|
||||
|
||||
uint16_t atkhld;
|
||||
#define ATKHLD_TRIGGER(atkhld) !(atkhld&0x8000)
|
||||
#define ATKHLD_HOLD(atkhld) ((atkhld>>8)&0x7F)
|
||||
#define ATKHLD_HOLD_TO_EMU_SAMPLES(atkhld) (4096*(0x7F-((atkhld>>8)&0x7F)))
|
||||
#define ATKHLD_ATTACK(atkhld) (atkhld&0x7F)
|
||||
|
||||
|
||||
uint16_t ip;
|
||||
#define INTIAL_PITCH_CENTER 0xE000
|
||||
#define INTIAL_PITCH_OCTAVE 0x1000
|
||||
|
||||
union {
|
||||
uint16_t ifatn;
|
||||
struct{
|
||||
uint8_t ifatn_attenuation;
|
||||
uint8_t ifatn_init_filter;
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint16_t pefe;
|
||||
struct {
|
||||
int8_t pefe_modenv_filter_height;
|
||||
int8_t pefe_modenv_pitch_height;
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint16_t fmmod;
|
||||
struct {
|
||||
int8_t fmmod_lfo1_filt_mod;
|
||||
int8_t fmmod_lfo1_vibrato;
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint16_t tremfrq;
|
||||
struct {
|
||||
uint8_t tremfrq_lfo1_freq;
|
||||
int8_t tremfrq_lfo1_tremolo;
|
||||
};
|
||||
};
|
||||
union {
|
||||
uint16_t fm2frq2;
|
||||
struct {
|
||||
uint8_t fm2frq2_lfo2_freq;
|
||||
int8_t fm2frq2_lfo2_vibrato;
|
||||
};
|
||||
};
|
||||
|
||||
int env_engine_on;
|
||||
|
||||
emu8k_mem_internal_t addr, loop_start, loop_end;
|
||||
|
||||
int32_t initial_att;
|
||||
int32_t initial_filter;
|
||||
|
||||
emu8k_envelope_t vol_envelope;
|
||||
emu8k_envelope_t mod_envelope;
|
||||
|
||||
int64_t lfo1_speed, lfo2_speed;
|
||||
emu8k_mem_internal_t lfo1_count, lfo2_count;
|
||||
int32_t lfo1_delay_samples, lfo2_delay_samples;
|
||||
int vol_l, vol_r;
|
||||
|
||||
int16_t fixed_modenv_filter_height;
|
||||
int16_t fixed_modenv_pitch_height;
|
||||
int16_t fixed_lfo1_filt_mod;
|
||||
int16_t fixed_lfo1_vibrato;
|
||||
int16_t fixed_lfo1_tremolo;
|
||||
int16_t fixed_lfo2_vibrato;
|
||||
|
||||
/* filter internal data. */
|
||||
int filterq_idx;
|
||||
int32_t filt_att;
|
||||
int64_t filt_buffer[5];
|
||||
|
||||
} emu8k_voice_t;
|
||||
|
||||
typedef struct emu8k_t
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t cpf;
|
||||
uint32_t ptrx;
|
||||
uint32_t cvcf;
|
||||
uint32_t vtft;
|
||||
uint32_t psst;
|
||||
uint32_t csl;
|
||||
|
||||
uint32_t ccca;
|
||||
emu8k_voice_t voice[32];
|
||||
|
||||
uint16_t init1, init2, init3, init4;
|
||||
|
||||
uint16_t envvol;
|
||||
uint16_t dcysusv;
|
||||
uint16_t envval;
|
||||
uint16_t dcysus;
|
||||
uint16_t atkhldv;
|
||||
uint16_t lfo1val, lfo2val;
|
||||
uint16_t atkhld;
|
||||
uint16_t ip;
|
||||
uint16_t ifatn;
|
||||
uint16_t pefe;
|
||||
uint16_t fmmod;
|
||||
uint16_t tremfrq;
|
||||
uint16_t fm2frq2;
|
||||
|
||||
int voice_on;
|
||||
|
||||
uint64_t addr;
|
||||
uint64_t loop_start, loop_end;
|
||||
|
||||
uint16_t pitch;
|
||||
int attenuation;
|
||||
int env_state, env_vol;
|
||||
int env_attack, env_decay, env_sustain, env_release;
|
||||
uint16_t hwcf1, hwcf2, hwcf3;
|
||||
uint32_t hwcf4, hwcf5, hwcf6, hwcf7;
|
||||
|
||||
int menv_state, menv_vol;
|
||||
int menv_attack, menv_decay, menv_sustain, menv_release;
|
||||
|
||||
int lfo1_count, lfo2_count;
|
||||
int8_t lfo1_fmmod, lfo2_fmmod;
|
||||
int8_t lfo1_trem;
|
||||
int vol_l, vol_r;
|
||||
|
||||
int8_t fe_height;
|
||||
|
||||
int64_t vlp, vbp, vhp;
|
||||
int32_t q;
|
||||
|
||||
int filter_offset;
|
||||
|
||||
/* float vlp, vbp, vhp;
|
||||
float q;*/
|
||||
|
||||
int cutoff;
|
||||
} voice[32];
|
||||
|
||||
uint32_t hwcf1, hwcf2, hwcf3;
|
||||
uint32_t hwcf4, hwcf5, hwcf6;
|
||||
uint16_t init1[32], init2[32], init3[32], init4[32];
|
||||
|
||||
uint32_t smalr, smarr, smalw, smarw;
|
||||
uint16_t smld_buffer, smrd_buffer;
|
||||
@@ -72,22 +303,32 @@ typedef struct emu8k_t
|
||||
|
||||
uint16_t c02_read;
|
||||
|
||||
uint16_t id;
|
||||
|
||||
int16_t *ram, *rom;
|
||||
|
||||
uint16_t id;
|
||||
|
||||
/* The empty block is used to act as an unallocated memory returning zero. */
|
||||
int16_t *ram, *rom, *empty;
|
||||
|
||||
/* RAM pointers are a way to avoid checking ram boundaries on read */
|
||||
int16_t *ram_pointers[0x100];
|
||||
uint32_t ram_end_addr;
|
||||
|
||||
|
||||
int cur_reg, cur_voice;
|
||||
|
||||
int timer_count;
|
||||
|
||||
int16_t out_l, out_r;
|
||||
|
||||
emu8k_chorus_eng_t chorus_engine;
|
||||
int32_t chorus_in_buffer[SOUNDBUFLEN];
|
||||
int32_t reverb_in_buffer[SOUNDBUFLEN];
|
||||
int32_t reverb_out_buffer[SOUNDBUFLEN * 2];
|
||||
|
||||
int pos;
|
||||
int32_t buffer[SOUNDBUFLEN * 2];
|
||||
} emu8k_t;
|
||||
|
||||
|
||||
|
||||
void emu8k_init(emu8k_t *emu8k, int onboard_ram);
|
||||
void emu8k_close(emu8k_t *emu8k);
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
* Emulation of the EGA, Chips & Technologies SuperEGA, and
|
||||
* AX JEGA graphics cards.
|
||||
*
|
||||
* Version: @(#)vid_ega.c 1.0.2 2017/06/05
|
||||
* Version: @(#)vid_ega.c 1.0.3 2017/07/21
|
||||
*
|
||||
* Author: Sarah Walker, <http://pcem-emulator.co.uk/>
|
||||
* Miran Grca, <mgrca8@gmail.com>
|
||||
@@ -454,7 +454,7 @@ void ega_recalctimings(ega_t *ega)
|
||||
|
||||
if (ega->crtc[7] & 1) ega->vtotal |= 0x100;
|
||||
if (ega->crtc[7] & 32) ega->vtotal |= 0x200;
|
||||
ega->vtotal++;
|
||||
ega->vtotal += 2;
|
||||
|
||||
if (ega->crtc[7] & 2) ega->dispend |= 0x100;
|
||||
if (ega->crtc[7] & 64) ega->dispend |= 0x200;
|
||||
@@ -466,7 +466,7 @@ void ega_recalctimings(ega_t *ega)
|
||||
|
||||
if (ega->crtc[7] & 0x10) ega->split |= 0x100;
|
||||
if (ega->crtc[9] & 0x40) ega->split |= 0x200;
|
||||
ega->split+=2;
|
||||
ega->split++;
|
||||
|
||||
ega->hdisp = ega->crtc[1];
|
||||
ega->hdisp++;
|
||||
@@ -532,13 +532,16 @@ void ega_poll(void *p)
|
||||
}
|
||||
else if (!(ega->gdcreg[6] & 1))
|
||||
{
|
||||
if (ega_jega_enabled(ega))
|
||||
if (fullchange)
|
||||
{
|
||||
ega_render_text_jega(ega, drawcursor);
|
||||
}
|
||||
else
|
||||
{
|
||||
ega_render_text_standard(ega, drawcursor);
|
||||
if (ega_jega_enabled(ega))
|
||||
{
|
||||
ega_render_text_jega(ega, drawcursor);
|
||||
}
|
||||
else
|
||||
{
|
||||
ega_render_text_standard(ega, drawcursor);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
@@ -572,6 +575,8 @@ void ega_poll(void *p)
|
||||
}
|
||||
|
||||
ega->displine++;
|
||||
if (ega->interlace)
|
||||
ega->displine++;
|
||||
if ((ega->stat & 8) && ((ega->displine & 15) == (ega->crtc[0x11] & 15)) && ega->vslines)
|
||||
ega->stat &= ~8;
|
||||
ega->vslines++;
|
||||
@@ -595,6 +600,8 @@ void ega_poll(void *p)
|
||||
ega->con = 0;
|
||||
|
||||
ega->maback += (ega->rowoffset << 3);
|
||||
if (ega->interlace)
|
||||
ega->maback += (ega->rowoffset << 3);
|
||||
ega->maback &= ega->vrammask;
|
||||
ega->ma = ega->maback;
|
||||
}
|
||||
@@ -631,10 +638,14 @@ void ega_poll(void *p)
|
||||
ega->stat |= 8;
|
||||
if (ega->seqregs[1] & 8) x = ega->hdisp * ((ega->seqregs[1] & 1) ? 8 : 9) * 2;
|
||||
else x = ega->hdisp * ((ega->seqregs[1] & 1) ? 8 : 9);
|
||||
if ((x != xsize || (ega->lastline - ega->firstline) != ysize) || update_overscan)
|
||||
|
||||
if (ega->interlace && !ega->oddeven) ega->lastline++;
|
||||
if (ega->interlace && ega->oddeven) ega->firstline--;
|
||||
|
||||
if ((x != xsize || (ega->lastline - ega->firstline + 1) != ysize) || update_overscan)
|
||||
{
|
||||
xsize = x;
|
||||
ysize = ega->lastline - ega->firstline;
|
||||
ysize = ega->lastline - ega->firstline + 1;
|
||||
if (xsize < 64) xsize = 640;
|
||||
if (ysize < 32) ysize = 200;
|
||||
y_add = enable_overscan ? 14 : 0;
|
||||
@@ -714,7 +725,7 @@ void ega_poll(void *p)
|
||||
}
|
||||
}
|
||||
|
||||
video_blit_memtoscreen(32, 0, ega->firstline, ega->lastline + y_add_ex, xsize + x_add_ex, ega->lastline - ega->firstline + y_add_ex);
|
||||
video_blit_memtoscreen(32, 0, ega->firstline, ega->lastline + 1 + y_add_ex, xsize + x_add_ex, ega->lastline - ega->firstline + 1 + y_add_ex);
|
||||
|
||||
frames++;
|
||||
|
||||
@@ -754,7 +765,7 @@ void ega_poll(void *p)
|
||||
ega->vc = 0;
|
||||
ega->sc = 0;
|
||||
ega->dispon = 1;
|
||||
ega->displine = 0;
|
||||
ega->displine = (ega->interlace && ega->oddeven) ? 1 : 0;
|
||||
ega->scrollcache = ega->attrregs[0x13] & 7;
|
||||
}
|
||||
if (ega->sc == (ega->crtc[10] & 31))
|
||||
|
||||
@@ -1610,7 +1610,7 @@ void svga_doblit(int y1, int y2, int wx, int wy, svga_t *svga)
|
||||
return;
|
||||
}
|
||||
|
||||
if ((wx!=xsize || wy!=ysize) && !vid_resize)
|
||||
if (((wx!=xsize) || ((wy + 1)!=ysize)) && !vid_resize)
|
||||
{
|
||||
xsize=wx;
|
||||
ysize=wy+1;
|
||||
|
||||
200
src/WIN/86Box.rc
200
src/WIN/86Box.rc
@@ -83,11 +83,11 @@ BEGIN
|
||||
MENUITEM "E&GA/(S)VGA overscan", IDM_VID_OVERSCAN
|
||||
POPUP "VGA screen &type"
|
||||
BEGIN
|
||||
MENUITEM "RGB &Color", IDM_VID_GRAY_RGB
|
||||
MENUITEM "&RGB Grayscale", IDM_VID_GRAY_MONO
|
||||
MENUITEM "&Amber monitor", IDM_VID_GRAY_AMBER
|
||||
MENUITEM "&Green monitor", IDM_VID_GRAY_GREEN
|
||||
MENUITEM "&White monitor", IDM_VID_GRAY_WHITE
|
||||
MENUITEM "RGB &Color", IDM_VID_GRAY_RGB
|
||||
MENUITEM "&RGB Grayscale", IDM_VID_GRAY_MONO
|
||||
MENUITEM "&Amber monitor", IDM_VID_GRAY_AMBER
|
||||
MENUITEM "&Green monitor", IDM_VID_GRAY_GREEN
|
||||
MENUITEM "&White monitor", IDM_VID_GRAY_WHITE
|
||||
END
|
||||
POPUP "Grayscale &conversion type"
|
||||
BEGIN
|
||||
@@ -703,12 +703,12 @@ BEGIN
|
||||
IDS_2053 "Invalid number of sectors (valid values are between 1 and 63)"
|
||||
IDS_2054 "Invalid number of heads (valid values are between 1 and 16)"
|
||||
IDS_2055 "Invalid number of cylinders (valid values are between 1 and 266305)"
|
||||
IDS_2056 "Please enter a valid file name"
|
||||
IDS_2057 "Unable to open the file for write"
|
||||
IDS_2058 "Attempting to create a HDI image larger than 4 GB"
|
||||
IDS_2059 "Remember to partition and format the new drive"
|
||||
IDS_2060 "Unable to open the file for read"
|
||||
IDS_2061 "HDI or HDX image with a sector size that is not 512 are not supported"
|
||||
IDS_2056 "Specify the NVR Path"
|
||||
IDS_2057 "(empty)"
|
||||
IDS_2058 "(host drive %c:)"
|
||||
IDS_2059 "Turbo"
|
||||
IDS_2060 "On"
|
||||
IDS_2061 "Off"
|
||||
IDS_2062 "86Box was unable to find any ROMs.\nAt least one ROM set is required to use 86Box."
|
||||
IDS_2063 "Configured ROM set not available.\nDefaulting to an available ROM set."
|
||||
END
|
||||
@@ -724,9 +724,9 @@ BEGIN
|
||||
IDS_2070 "Other peripherals"
|
||||
IDS_2071 "Hard disks"
|
||||
IDS_2072 "Removable devices"
|
||||
IDS_2073 "%i"" floppy drive: %s"
|
||||
IDS_2074 "Disabled CD-ROM drive"
|
||||
IDS_2075 "%s CD-ROM drive: %s"
|
||||
IDS_2073 "Unable to create bitmap file: %s"
|
||||
IDS_2074 "Use CTRL+ALT+PAGE DOWN to return to windowed mode"
|
||||
IDS_2075 "CD-ROM images (*.ISO;*.CUE)\0*.ISO;*.CUE\0All files (*.*)\0*.*\0"
|
||||
IDS_2076 "Host CD/DVD Drive (%c:)"
|
||||
IDS_2077 "Click to capture mouse"
|
||||
IDS_2078 "Press F12-F8 to release mouse"
|
||||
@@ -743,14 +743,12 @@ BEGIN
|
||||
IDS_2085 "H"
|
||||
IDS_2086 "S"
|
||||
IDS_2087 "MB"
|
||||
IDS_2088 "%i"
|
||||
IDS_2089 "Enabled"
|
||||
IDS_2090 "Mute"
|
||||
IDS_2091 "Type"
|
||||
IDS_2092 "Bus"
|
||||
IDS_2093 "DMA"
|
||||
IDS_2094 "KB"
|
||||
IDS_2095 "MFM, RLL, or ESDI CD-ROM drives never existed"
|
||||
END
|
||||
|
||||
STRINGTABLE DISCARDABLE
|
||||
@@ -766,7 +764,6 @@ BEGIN
|
||||
IDS_2104 "Network Type"
|
||||
IDS_2105 "Surround Module"
|
||||
IDS_2106 "MPU-401 Base Address"
|
||||
IDS_2107 "No PCap devices found"
|
||||
IDS_2108 "On-board RAM"
|
||||
IDS_2109 "Memory Size"
|
||||
IDS_2110 "Display Type"
|
||||
@@ -806,15 +803,15 @@ BEGIN
|
||||
IDS_2136 "Slow VLB/PCI"
|
||||
IDS_2137 "Mid VLB/PCI"
|
||||
IDS_2138 "Fast VLB/PCI"
|
||||
IDS_2139 "Microsoft 2-button mouse (serial)"
|
||||
IDS_2140 "Mouse Systems mouse (serial)"
|
||||
IDS_2141 "2-button mouse (PS/2)"
|
||||
IDS_2142 "Microsoft Intellimouse (PS/2)"
|
||||
IDS_2143 "Bus mouse"
|
||||
END
|
||||
|
||||
STRINGTABLE DISCARDABLE
|
||||
BEGIN
|
||||
IDS_2139 "PCap failed to set up because it may not be initialized"
|
||||
IDS_2140 "No PCap devices found"
|
||||
IDS_2141 "Invalid PCap device"
|
||||
IDS_2142 "&Notify disk change"
|
||||
IDS_2143 "Type"
|
||||
IDS_2144 "Standard 2-button joystick(s)"
|
||||
IDS_2145 "Standard 4-button joystick"
|
||||
IDS_2146 "Standard 6-button joystick"
|
||||
@@ -827,80 +824,91 @@ BEGIN
|
||||
IDS_2153 "AT Fixed Disk Adapter"
|
||||
IDS_2154 "Internal IDE"
|
||||
IDS_2155 "IRQ %i"
|
||||
IDS_2156 "MFM (%01i:%01i)"
|
||||
IDS_2157 "IDE (PIO+DMA) (%01i:%01i)"
|
||||
IDS_2158 "SCSI (%02i:%02i)"
|
||||
IDS_2159 "Invalid number of cylinders (valid values are between 1 and 1023)"
|
||||
IDS_2160 "%" PRIu64
|
||||
IDS_2161 "Genius Bus mouse"
|
||||
IDS_2162 "Amstrad mouse"
|
||||
IDS_2163 "Attempting to create a spuriously large hard disk image"
|
||||
IDS_2164 "Invalid number of sectors (valid values are between 1 and 99)"
|
||||
IDS_2165 "MFM"
|
||||
IDS_2166 "XT IDE"
|
||||
IDS_2167 "RLL"
|
||||
IDS_2168 "IDE (PIO-only)"
|
||||
IDS_2169 "%01i:%01i"
|
||||
IDS_2170 "Custom..."
|
||||
IDS_2171 "%" PRIu64 " MB (CHS: %" PRIu64 ", %" PRIu64 ", %" PRIu64 ")"
|
||||
IDS_2172 "Hard disk images (*.HDI;*.HDX;*.IMA;*.IMG)\0*.HDI;*.HDX;*.IMA;*.IMG\0All files (*.*)\0*.*\0"
|
||||
IDS_2173"All floppy images (*.0??;*.12;*.144;*.360;*.720;*.86F;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMD;*.IMG;*.TD0;*.VFD;*.XDF)\0*.0??;*.12;*.144;*.360;*.720;*.86F;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMD;*.IMG;*.TD0;*.VFD;*.XDF\0Advanced sector-based images (*.IMD;*.TD0)\0*.IMD;*.TD0\0Basic sector-based images (*.0??;*.12;*.144;*.360;*.720;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMG;*.VFD;*.XDF)\0*.0??;*.12;*.144;*.360;*.720;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMG;*.VFD;*.XDF\0Flux images (*.FDI)\0*.FDI\0Surface-based images (*.86F)\0*.86F\0All files (*.*)\0*.*\0"
|
||||
IDS_2174 "Configuration files (*.CFG)\0*.CFG\0All files (*.*)\0*.*\0"
|
||||
IDS_2175 "CD-ROM image (*.ISO;*.CUE)\0*.ISO;*.CUE\0All files (*.*)\0*.*\0"
|
||||
IDS_2176 "Use CTRL+ALT+PAGE DOWN to return to windowed mode"
|
||||
IDS_2177 "Olivetti M24 mouse"
|
||||
IDS_2178 "This image exists and will be overwritten.\nAre you sure you want to use it?"
|
||||
IDS_2179 "Floppy %i (%s): %ws"
|
||||
IDS_2180 "CD-ROM %i: %ws"
|
||||
IDS_2181 "MFM hard disk"
|
||||
IDS_2182 "IDE hard disk (PIO-only)"
|
||||
IDS_2183 "IDE hard disk (PIO and DMA)"
|
||||
IDS_2184 "SCSI hard disk"
|
||||
IDS_2185 "(empty)"
|
||||
IDS_2186 "(host drive %c:)"
|
||||
IDS_2187 "Custom (large)..."
|
||||
IDS_2188 "Type"
|
||||
IDS_2189 "ATAPI (PIO-only)"
|
||||
IDS_2190 "ATAPI (PIO and DMA)"
|
||||
IDS_2191 "ATAPI (PIO-only) (%01i:%01i)"
|
||||
IDS_2192 "ATAPI (PIO and DMA) (%01i:%01i)"
|
||||
IDS_2193 "Use CTRL+ALT+PAGE DOWN to return to windowed mode"
|
||||
IDS_2194 "Unable to create bitmap file: %s"
|
||||
IDS_2195 "IDE (PIO-only) (%01i:%01i)"
|
||||
IDS_2196 "Add New Hard Disk"
|
||||
IDS_2197 "Add Existing Hard Disk"
|
||||
IDS_2198 "SCSI removable disk %i: %s"
|
||||
IDS_2199 "USB is not yet supported"
|
||||
IDS_2200 "Invalid PCap device"
|
||||
IDS_2201 "&Notify disk change"
|
||||
IDS_2202 "SCSI (removable)"
|
||||
IDS_2203 "SCSI (removable) (%02i:%02i)"
|
||||
IDS_2204 "Pcap Library Not Available"
|
||||
IDS_2205 "RLL (%01i:%01i)"
|
||||
IDS_2206 "XT IDE (%01i:%01i)"
|
||||
IDS_2207 "RLL hard disk"
|
||||
IDS_2208 "XT IDE hard disk"
|
||||
IDS_2209 "IDE (PIO and DMA)"
|
||||
IDS_2210 "SCSI"
|
||||
IDS_2211 "&New image..."
|
||||
IDS_2212 "Existing image..."
|
||||
IDS_2213 "Existing image (&Write-protected)..."
|
||||
IDS_2214 "E&ject"
|
||||
IDS_2215 "&Mute"
|
||||
IDS_2216 "E&mpty"
|
||||
IDS_2217 "&Reload previous image"
|
||||
IDS_2218 "&Image..."
|
||||
IDS_2219 "PCap failed to set up because it may not be initialized"
|
||||
IDS_2220 "Image (&Write-protected)..."
|
||||
IDS_2221 "Turbo"
|
||||
IDS_2222 "On"
|
||||
IDS_2223 "Off"
|
||||
IDS_2224 "Logitech 3-button mouse (serial)"
|
||||
IDS_2225 "Specify the NVR Path"
|
||||
IDS_2226 "<Placeholder string>"
|
||||
IDS_2227 "English (United States)"
|
||||
IDS_2156 "%" PRIu64
|
||||
IDS_2157 "%" PRIu64 " MB (CHS: %" PRIu64 ", %" PRIu64 ", %" PRIu64 ")"
|
||||
IDS_2158 "Floppy %i (%s): %ws"
|
||||
IDS_2159"All floppy images (*.0??;*.12;*.144;*.360;*.720;*.86F;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMD;*.IMG;*.TD0;*.VFD;*.XDF)\0*.0??;*.12;*.144;*.360;*.720;*.86F;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMD;*.IMG;*.TD0;*.VFD;*.XDF\0Advanced sector-based images (*.IMD;*.TD0)\0*.IMD;*.TD0\0Basic sector-based images (*.0??;*.12;*.144;*.360;*.720;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMG;*.VFD;*.XDF)\0*.0??;*.12;*.144;*.360;*.720;*.BIN;*.CQ;*.CQM;*.DSK;*.FDI;*.FDF;*.FLP;*.HDM;*.IMA;*.IMG;*.VFD;*.XDF\0Flux images (*.FDI)\0*.FDI\0Surface-based images (*.86F)\0*.86F\0All files (*.*)\0*.*\0"
|
||||
IDS_2160 "Configuration files (*.CFG)\0*.CFG\0All files (*.*)\0*.*\0"
|
||||
IDS_2161 "&New image..."
|
||||
IDS_2162 "Existing image..."
|
||||
IDS_2163 "Existing image (&Write-protected)..."
|
||||
IDS_2164 "E&ject"
|
||||
IDS_2165 "&Mute"
|
||||
IDS_2166 "E&mpty"
|
||||
IDS_2167 "&Reload previous image"
|
||||
IDS_2168 "&Image..."
|
||||
IDS_2169 "Image (&Write-protected)..."
|
||||
|
||||
IDS_3072 "None"
|
||||
IDS_3073 "[Bus] Bus mouse"
|
||||
IDS_3074 "[Bus] InPort mouse"
|
||||
IDS_3075 "[Serial] Mouse Systems mouse"
|
||||
IDS_3076 "[Serial] Microsoft 2-button mouse"
|
||||
IDS_3077 "[Serial] Logitech 3-button mouse"
|
||||
IDS_3078 "[Serial] Microsoft wheel mouse"
|
||||
IDS_3079 "[PS/2] 2-button mouse"
|
||||
IDS_3080 "[PS/2] Microsoft Intellimouse"
|
||||
IDS_3081 "[Proprietary] Amstrad mouse"
|
||||
IDS_3082 "[Proprietary] Olivetti M24 mouse"
|
||||
|
||||
IDS_4096 "Hard disk (%s)"
|
||||
IDS_4097 "%01i:%01i"
|
||||
IDS_4098 "%i"
|
||||
IDS_4099 "Disabled"
|
||||
IDS_4100 "Custom..."
|
||||
IDS_4101 "Custom (large)..."
|
||||
IDS_4102 "Add New Hard Disk"
|
||||
IDS_4103 "Add Existing Hard Disk"
|
||||
IDS_4104 "Attempting to create a HDI image larger than 4 GB"
|
||||
IDS_4105 "Attempting to create a spuriously large hard disk image"
|
||||
IDS_4106 "Hard disk images (*.HDI;*.HDX;*.IMA;*.IMG)\0*.HDI;*.HDX;*.IMA;*.IMG\0All files (*.*)\0*.*\0"
|
||||
IDS_4107 "Unable to open the file for read"
|
||||
IDS_4108 "Unable to open the file for write"
|
||||
IDS_4109 "HDI or HDX image with a sector size that is not 512 are not supported"
|
||||
IDS_4110 "USB is not yet supported"
|
||||
IDS_4111 "This image exists and will be overwritten.\nAre you sure you want to use it?"
|
||||
IDS_4112 "Please enter a valid file name"
|
||||
IDS_4113 "Remember to partition and format the new drive"
|
||||
IDS_4114 "MFM or ESDI CD-ROM drives never existed"
|
||||
IDS_4115 "Removable disk %i (SCSI): %ws"
|
||||
|
||||
IDS_4352 "MFM"
|
||||
IDS_4353 "XT IDE"
|
||||
IDS_4354 "ESDI"
|
||||
IDS_4355 "IDE (PIO-only)"
|
||||
IDS_4356 "IDE (PIO+DMA)"
|
||||
IDS_4357 "SCSI"
|
||||
IDS_4358 "SCSI (removable)"
|
||||
|
||||
IDS_4608 "MFM (%01i:%01i)"
|
||||
IDS_4609 "XT IDE (%01i:%01i)"
|
||||
IDS_4610 "ESDI (%01i:%01i)"
|
||||
IDS_4611 "IDE (PIO-only) (%01i:%01i)"
|
||||
IDS_4612 "IDE (PIO+DMA) (%01i:%01i)"
|
||||
IDS_4613 "SCSI (%02i:%02i)"
|
||||
IDS_4614 "SCSI (removable) (%02i:%02i)"
|
||||
|
||||
IDS_5120 "CD-ROM %i (%s): %s"
|
||||
|
||||
IDS_5376 "Disabled"
|
||||
IDS_5377 "<Reserved>"
|
||||
IDS_5378 "<Reserved>"
|
||||
IDS_5379 "<Reserved>"
|
||||
IDS_5380 "ATAPI (PIO-only)"
|
||||
IDS_5381 "ATAPI (PIO and DMA)"
|
||||
IDS_5382 "SCSI"
|
||||
|
||||
IDS_5632 "Disabled"
|
||||
IDS_5633 "<Reserved>"
|
||||
IDS_5634 "<Reserved>"
|
||||
IDS_5635 "<Reserved>"
|
||||
IDS_5636 "ATAPI (PIO-only) (%01i:%01i)"
|
||||
IDS_5637 "ATAPI (PIO and DMA) (%01i:%01i)"
|
||||
IDS_5638 "SCSI (%02i:%02i)"
|
||||
|
||||
IDS_6144 "English (United States)"
|
||||
END
|
||||
#define IDS_LANG_ENUS IDS_2227
|
||||
#define IDS_LANG_ENUS IDS_6144
|
||||
|
||||
|
||||
#ifndef _MAC
|
||||
@@ -931,7 +939,7 @@ BEGIN
|
||||
VALUE "FileDescription", "86Box - an emulator for X86-based systems\0"
|
||||
VALUE "FileVersion", "2.00\0"
|
||||
VALUE "InternalName", "86Box\0"
|
||||
VALUE "LegalCopyright", "Copyright <EFBFBD> SoftHistory, Sarah Walker, 2007-2017, Released under the GNU GPL v2\0"
|
||||
VALUE "LegalCopyright", "Copyright (C)SoftHistory, Sarah Walker, 2007-2017, Released under the GNU GPL v2\0"
|
||||
VALUE "LegalTrademarks", "\0"
|
||||
VALUE "OriginalFilename", "86Box.exe\0"
|
||||
VALUE "PrivateBuild", "\0"
|
||||
|
||||
@@ -17,6 +17,10 @@ extern wchar_t *plat_get_string_from_id(int i);
|
||||
#ifndef IDS_2079
|
||||
#define IDS_2079 2079
|
||||
#endif
|
||||
|
||||
#ifndef IDS_2139
|
||||
#define IDS_2139 2139
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern void plat_msgbox_fatal(char *string);
|
||||
|
||||
@@ -288,11 +288,11 @@
|
||||
#define IDS_2136 2136 // "Slow VLB/PCI"
|
||||
#define IDS_2137 2137 // "Mid VLB/PCI"
|
||||
#define IDS_2138 2138 // "Fast VLB/PCI"
|
||||
#define IDS_2139 2139 // "Microsoft 2-button mouse (serial)"
|
||||
#define IDS_2140 2140 // "Mouse Systems mouse (serial)"
|
||||
#define IDS_2141 2141 // "2-button mouse (PS/2)"
|
||||
#define IDS_2142 2142 // "Microsoft Intellimouse (PS/2)"
|
||||
#define IDS_2143 2143 // "Bus mouse"
|
||||
#define IDS_2139 2139
|
||||
#define IDS_2140 2140
|
||||
#define IDS_2141 2141
|
||||
#define IDS_2142 2142
|
||||
#define IDS_2143 2143
|
||||
#define IDS_2144 2144 // "Standard 2-button joystick(s)"
|
||||
#define IDS_2145 2145 // "Standard 4-button joystick"
|
||||
#define IDS_2146 2146 // "Standard 6-button joystick"
|
||||
@@ -310,8 +310,8 @@
|
||||
#define IDS_2158 2158 // "SCSI (%02i:%02i)"
|
||||
#define IDS_2159 2159 // "Invalid number of cylinders.."
|
||||
#define IDS_2160 2160 // "%" PRIu64
|
||||
#define IDS_2161 2161 // "Genius Bus mouse"
|
||||
#define IDS_2162 2162 // "Amstrad mouse"
|
||||
#define IDS_2161 2161
|
||||
#define IDS_2162 2162
|
||||
#define IDS_2163 2163 // "Attempting to create a spuriously.."
|
||||
#define IDS_2164 2164 // "Invalid number of sectors.."
|
||||
#define IDS_2165 2165 // "MFM"
|
||||
@@ -319,67 +319,87 @@
|
||||
#define IDS_2167 2167 // "RLL"
|
||||
#define IDS_2168 2168 // "IDE (PIO-only)"
|
||||
#define IDS_2169 2169 // "%01i:%01i"
|
||||
#define IDS_2170 2170 // "Custom..."
|
||||
#define IDS_2171 2171 // "%" PRIu64 " MB (CHS: %" ..
|
||||
#define IDS_2172 2172 // "Hard disk images .."
|
||||
#define IDS_2173 2173 // "All floppy images .."
|
||||
#define IDS_2174 2174 // "Configuration files .."
|
||||
#define IDS_2175 2175 // "CD-ROM image .."
|
||||
#define IDS_2176 2176 // "Use CTRL+ALT+PAGE DOWN .."
|
||||
#define IDS_2177 2177 // "Olivetti M24 mouse"
|
||||
#define IDS_2178 2178 // "This image exists and will.."
|
||||
#define IDS_2179 2179 // "Floppy %i (%s): %ws"
|
||||
#define IDS_2180 2180 // "CD-ROM %i: %ws"
|
||||
#define IDS_2181 2181 // "MFM hard disk"
|
||||
#define IDS_2182 2182 // "IDE hard disk (PIO-only)"
|
||||
#define IDS_2183 2183 // "IDE hard disk (PIO and DMA)"
|
||||
#define IDS_2184 2184 // "SCSI hard disk"
|
||||
#define IDS_2185 2185 // "(empty)"
|
||||
#define IDS_2186 2186 // "(host drive %c:)"
|
||||
#define IDS_2187 2187 // "Custom (large)..."
|
||||
#define IDS_2188 2188 // "Type"
|
||||
#define IDS_2189 2189 // "ATAPI (PIO-only)"
|
||||
#define IDS_2190 2190 // "ATAPI (PIO and DMA)"
|
||||
#define IDS_2191 2191 // "ATAPI (PIO-only) (%01i:%01i)"
|
||||
#define IDS_2192 2192 // "ATAPI (PIO and DMA) (%01i:%01i)"
|
||||
#define IDS_2193 2193 // "Use CTRL+ALT+PAGE DOWN to .."
|
||||
#define IDS_2194 2194 // "Unable to create bitmap file: %s"
|
||||
#define IDS_2195 2195 // "IDE (PIO-only) (%01i:%01i)"
|
||||
#define IDS_2196 2196 // "Add New Hard Disk"
|
||||
#define IDS_2197 2197 // "Add Existing Hard Disk"
|
||||
#define IDS_2198 2198 // "SCSI removable disk %i: %s"
|
||||
#define IDS_2199 2199 // "USB is not yet supported"
|
||||
#define IDS_2200 2200 // "Invalid PCap device"
|
||||
#define IDS_2201 2201 // "&Notify disk change"
|
||||
#define IDS_2202 2202 // "SCSI (removable)"
|
||||
#define IDS_2203 2203 // "SCSI (removable) (%02i:%02i)"
|
||||
#define IDS_2204 2204 // "Pcap Library Not Available"
|
||||
#define IDS_2205 2205 // "RLL (%01i:%01i)"
|
||||
#define IDS_2206 2206 // "XT IDE (%01i:%01i)"
|
||||
#define IDS_2207 2207 // "RLL hard disk"
|
||||
#define IDS_2208 2208 // "XT IDE hard disk"
|
||||
#define IDS_2209 2209 // "IDE (PIO and DMA)"
|
||||
#define IDS_2210 2210 // "SCSI"
|
||||
#define IDS_2211 2211 // "&New image..."
|
||||
#define IDS_2212 2212 // "Existing image..."
|
||||
#define IDS_2213 2213 // "Existing image (&Write-.."
|
||||
#define IDS_2214 2214 // "E&ject"
|
||||
#define IDS_2215 2215 // "&Mute"
|
||||
#define IDS_2216 2216 // "E&mpty"
|
||||
#define IDS_2217 2217 // "&Reload previous image"
|
||||
#define IDS_2218 2218 // "&Image..."
|
||||
#define IDS_2219 2219 // "PCap failed to set up .."
|
||||
#define IDS_2220 2220 // "Image (&Write-protected)..."
|
||||
#define IDS_2221 2221 // "Turbo"
|
||||
#define IDS_2222 2222 // "On"
|
||||
#define IDS_2223 2223 // "Off"
|
||||
#define IDS_2224 2224 // "Logitech 3-button mouse (serial)"
|
||||
#define IDS_2225 2225 // "Specify the NVR Path"
|
||||
#define IDS_2226 2226 // "<Placeholder string>"
|
||||
#define IDS_2227 2227 // "English (United States)"
|
||||
|
||||
#define IDS_LANG_ENUS IDS_2227
|
||||
#define STRINGS_NUM 180
|
||||
#define IDS_3072 3072
|
||||
#define IDS_3073 3073
|
||||
#define IDS_3074 3074
|
||||
#define IDS_3075 3075
|
||||
#define IDS_3076 3076
|
||||
#define IDS_3077 3077
|
||||
#define IDS_3078 3078
|
||||
#define IDS_3079 3079
|
||||
#define IDS_3080 3080
|
||||
#define IDS_3081 3081
|
||||
#define IDS_3082 3082
|
||||
|
||||
#define IDS_4096 4096
|
||||
#define IDS_4097 4097
|
||||
#define IDS_4098 4098
|
||||
#define IDS_4099 4099
|
||||
#define IDS_4100 4100
|
||||
#define IDS_4101 4101
|
||||
#define IDS_4102 4102
|
||||
#define IDS_4103 4103
|
||||
#define IDS_4104 4104
|
||||
#define IDS_4105 4105
|
||||
#define IDS_4106 4106
|
||||
#define IDS_4107 4107
|
||||
#define IDS_4108 4108
|
||||
#define IDS_4109 4109
|
||||
#define IDS_4110 4110
|
||||
#define IDS_4111 4111
|
||||
#define IDS_4112 4112
|
||||
#define IDS_4113 4113
|
||||
#define IDS_4114 4114
|
||||
#define IDS_4115 4115
|
||||
|
||||
#define IDS_4352 4352
|
||||
#define IDS_4353 4353
|
||||
#define IDS_4354 4354
|
||||
#define IDS_4355 4355
|
||||
#define IDS_4356 4356
|
||||
#define IDS_4357 4357
|
||||
#define IDS_4358 4358
|
||||
|
||||
#define IDS_4608 4608
|
||||
#define IDS_4609 4609
|
||||
#define IDS_4610 4610
|
||||
#define IDS_4611 4611
|
||||
#define IDS_4612 4612
|
||||
#define IDS_4613 4613
|
||||
#define IDS_4614 4614
|
||||
|
||||
#define IDS_5120 5120
|
||||
|
||||
#define IDS_5376 5376
|
||||
#define IDS_5377 5377
|
||||
#define IDS_5378 5378
|
||||
#define IDS_5379 5379
|
||||
#define IDS_5380 5380
|
||||
#define IDS_5381 5381
|
||||
#define IDS_5382 5382
|
||||
|
||||
#define IDS_5632 5632
|
||||
#define IDS_5633 5633
|
||||
#define IDS_5634 5634
|
||||
#define IDS_5635 5635
|
||||
#define IDS_5636 5636
|
||||
#define IDS_5637 5637
|
||||
#define IDS_5638 5638
|
||||
|
||||
#define IDS_6144 6144
|
||||
|
||||
#define IDS_LANG_ENUS IDS_6144
|
||||
|
||||
#define STRINGS_NUM_2048 122
|
||||
#define STRINGS_NUM_3072 11
|
||||
#define STRINGS_NUM_4096 20
|
||||
#define STRINGS_NUM_4352 7
|
||||
#define STRINGS_NUM_4608 7
|
||||
#define STRINGS_NUM_5120 1
|
||||
#define STRINGS_NUM_5376 7
|
||||
#define STRINGS_NUM_5632 7
|
||||
#define STRINGS_NUM_6144 1
|
||||
|
||||
|
||||
#define IDM_ABOUT 40001
|
||||
|
||||
114
src/WIN/win.c
114
src/WIN/win.c
@@ -165,6 +165,8 @@ void updatewindowsize(int x, int y)
|
||||
int temp_overscan_x = overscan_x;
|
||||
int temp_overscan_y = overscan_y;
|
||||
|
||||
double dx, dy, dtx, dty;
|
||||
|
||||
if (vid_resize) return;
|
||||
|
||||
if (x < 160) x = 160;
|
||||
@@ -182,30 +184,37 @@ void updatewindowsize(int x, int y)
|
||||
|
||||
if (force_43)
|
||||
{
|
||||
dx = (double) x;
|
||||
dtx = (double) temp_overscan_x;
|
||||
|
||||
dy = (double) y;
|
||||
dty = (double) temp_overscan_y;
|
||||
|
||||
/* Account for possible overscan. */
|
||||
if (temp_overscan_y == 16)
|
||||
{
|
||||
/* CGA */
|
||||
unscaled_size_y = ((int) (((double) (x - temp_overscan_x) / 4.0) * 3.0)) + temp_overscan_y;
|
||||
dy = (((dx - dtx) / 4.0) * 3.0) + dty;
|
||||
}
|
||||
else if (temp_overscan_y < 16)
|
||||
{
|
||||
/* MDA/Hercules */
|
||||
unscaled_size_y = ((int) (((double) (x) / 4.0) * 3.0));
|
||||
dy = (x / 4.0) * 3.0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (enable_overscan)
|
||||
{
|
||||
/* EGA/(S)VGA with overscan */
|
||||
unscaled_size_y = ((int) (((double) (x - temp_overscan_x) / 4.0) * 3.0)) + temp_overscan_y;
|
||||
dy = (((dx - dtx) / 4.0) * 3.0) + dty;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* EGA/(S)VGA without overscan */
|
||||
unscaled_size_y = ((int) (((double) (x) / 4.0) * 3.0));
|
||||
dy = (x / 4.0) * 3.0;
|
||||
}
|
||||
}
|
||||
unscaled_size_y = (int) dy;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -325,7 +334,6 @@ void mainthread(LPVOID param)
|
||||
|
||||
if (!video_fullscreen && win_doresize && (winsizex > 0) && (winsizey > 0))
|
||||
{
|
||||
video_wait_for_blit();
|
||||
SendMessage(hwndStatus, SB_GETBORDERS, 0, (LPARAM) sb_borders);
|
||||
GetWindowRect(ghwnd, &r);
|
||||
MoveWindow(hwndRender, 0, 0, winsizex, winsizey, TRUE);
|
||||
@@ -454,12 +462,12 @@ HMENU create_popup_menu(int part)
|
||||
|
||||
void create_floppy_submenu(HMENU m, int id)
|
||||
{
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_IMAGE_NEW | id, win_language_get_string_from_id(2211));
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_IMAGE_NEW | id, win_language_get_string_from_id(IDS_2161));
|
||||
AppendMenu(m, MF_SEPARATOR, 0, 0);
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_IMAGE_EXISTING | id, win_language_get_string_from_id(2212));
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_IMAGE_EXISTING_WP | id, win_language_get_string_from_id(2213));
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_IMAGE_EXISTING | id, win_language_get_string_from_id(IDS_2162));
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_IMAGE_EXISTING_WP | id, win_language_get_string_from_id(IDS_2163));
|
||||
AppendMenu(m, MF_SEPARATOR, 0, 0);
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_EJECT | id, win_language_get_string_from_id(2214));
|
||||
AppendMenu(m, MF_STRING, IDM_FLOPPY_EJECT | id, win_language_get_string_from_id(IDS_2164));
|
||||
}
|
||||
|
||||
void create_cdrom_submenu(HMENU m, int id)
|
||||
@@ -467,12 +475,12 @@ void create_cdrom_submenu(HMENU m, int id)
|
||||
int i = 0;
|
||||
WCHAR s[64];
|
||||
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_MUTE | id, win_language_get_string_from_id(2215));
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_MUTE | id, win_language_get_string_from_id(IDS_2165));
|
||||
AppendMenu(m, MF_SEPARATOR, 0, 0);
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_EMPTY | id, win_language_get_string_from_id(2216));
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_RELOAD | id, win_language_get_string_from_id(2217));
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_EMPTY | id, win_language_get_string_from_id(IDS_2166));
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_RELOAD | id, win_language_get_string_from_id(IDS_2167));
|
||||
AppendMenu(m, MF_SEPARATOR, 0, 0);
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_IMAGE | id, win_language_get_string_from_id(2218));
|
||||
AppendMenu(m, MF_STRING, IDM_CDROM_IMAGE | id, win_language_get_string_from_id(IDS_2168));
|
||||
|
||||
if (host_cdrom_drive_available_num == 0)
|
||||
{
|
||||
@@ -528,13 +536,13 @@ check_menu_items:
|
||||
|
||||
void create_removable_disk_submenu(HMENU m, int id)
|
||||
{
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_EJECT | id, win_language_get_string_from_id(2216));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_RELOAD | id, win_language_get_string_from_id(2217));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_EJECT | id, win_language_get_string_from_id(IDS_2166));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_RELOAD | id, win_language_get_string_from_id(IDS_2167));
|
||||
AppendMenu(m, MF_SEPARATOR, 0, 0);
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_SEND_CHANGE | id, win_language_get_string_from_id(2201));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_SEND_CHANGE | id, win_language_get_string_from_id(IDS_2142));
|
||||
AppendMenu(m, MF_SEPARATOR, 0, 0);
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_IMAGE | id, win_language_get_string_from_id(2218));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_IMAGE_WP | id, win_language_get_string_from_id(2220));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_IMAGE | id, win_language_get_string_from_id(IDS_2168));
|
||||
AppendMenu(m, MF_STRING, IDM_RDISK_IMAGE_WP | id, win_language_get_string_from_id(IDS_2169));
|
||||
}
|
||||
|
||||
void get_executable_name(wchar_t *s, int size)
|
||||
@@ -781,7 +789,7 @@ void create_floppy_tip(int part)
|
||||
mbstowcs(wtext, fdd_getname(fdd_get_type(drive)), strlen(fdd_getname(fdd_get_type(drive))) + 1);
|
||||
if (wcslen(discfns[drive]) == 0)
|
||||
{
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2179), drive + 1, wtext, win_language_get_string_from_id(2185));
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_2158), drive + 1, wtext, win_language_get_string_from_id(IDS_2057));
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -801,27 +809,36 @@ void create_cdrom_tip(int part)
|
||||
WCHAR wtext[512];
|
||||
WCHAR tempTip[512];
|
||||
|
||||
WCHAR *szText;
|
||||
int id;
|
||||
|
||||
int drive = sb_part_meanings[part] & 0xf;
|
||||
|
||||
int bus = cdrom_drives[drive].bus_type;
|
||||
|
||||
id = IDS_4352 + (bus - 1);
|
||||
|
||||
szText = (WCHAR *) win_language_get_string_from_id(id);
|
||||
|
||||
if (cdrom_drives[drive].host_drive == 200)
|
||||
{
|
||||
if (wcslen(cdrom_image[drive].image_path) == 0)
|
||||
{
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2180), drive + 1, win_language_get_string_from_id(2185));
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_5120), drive + 1, szText, win_language_get_string_from_id(IDS_2057));
|
||||
}
|
||||
else
|
||||
{
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2180), drive + 1, cdrom_image[drive].image_path);
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_5120), drive + 1, szText, cdrom_image[drive].image_path);
|
||||
}
|
||||
}
|
||||
else if (cdrom_drives[drive].host_drive < 0x41)
|
||||
else if ((cdrom_drives[drive].host_drive >= 'A') && (cdrom_drives[drive].host_drive <= 'Z'))
|
||||
{
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2180), drive + 1, win_language_get_string_from_id(2185));
|
||||
_swprintf(wtext, win_language_get_string_from_id(IDS_2058), cdrom_drives[drive].host_drive & ~0x20);
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_5120), drive + 1, szText, wtext);
|
||||
}
|
||||
else
|
||||
{
|
||||
_swprintf(wtext, win_language_get_string_from_id(2186), cdrom_drives[drive].host_drive & ~0x20);
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2180), drive + 1, wtext);
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_5120), drive + 1, szText, win_language_get_string_from_id(IDS_2057));
|
||||
}
|
||||
|
||||
if (sbTips[part] != NULL)
|
||||
@@ -840,11 +857,11 @@ void create_removable_hd_tip(int part)
|
||||
|
||||
if (wcslen(hdc[drive].fn) == 0)
|
||||
{
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2198), drive, win_language_get_string_from_id(2185));
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_4115), drive, win_language_get_string_from_id(IDS_2057));
|
||||
}
|
||||
else
|
||||
{
|
||||
_swprintf(tempTip, win_language_get_string_from_id(2198), drive, hdc[drive].fn);
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_4115), drive, hdc[drive].fn);
|
||||
}
|
||||
|
||||
if (sbTips[part] != NULL)
|
||||
@@ -857,41 +874,24 @@ void create_removable_hd_tip(int part)
|
||||
|
||||
void create_hd_tip(int part)
|
||||
{
|
||||
WCHAR tempTip[512];
|
||||
WCHAR *szText;
|
||||
int id = 2181;
|
||||
int id;
|
||||
|
||||
int bus = sb_part_meanings[part] & 0xf;
|
||||
|
||||
switch(bus)
|
||||
{
|
||||
case HDD_BUS_MFM:
|
||||
id = 2181;
|
||||
break;
|
||||
case HDD_BUS_RLL:
|
||||
id = 2207;
|
||||
break;
|
||||
case HDD_BUS_XTIDE:
|
||||
id = 2208;
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_ONLY:
|
||||
id = 2182;
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_AND_DMA:
|
||||
id = 2183;
|
||||
break;
|
||||
case HDD_BUS_SCSI:
|
||||
id = 2184;
|
||||
break;
|
||||
}
|
||||
id = IDS_4352 + (bus - 1);
|
||||
|
||||
szText = (WCHAR *) win_language_get_string_from_id(id);
|
||||
|
||||
_swprintf(tempTip, win_language_get_string_from_id(IDS_4096), szText);
|
||||
|
||||
if (sbTips[part] != NULL)
|
||||
{
|
||||
free(sbTips[part]);
|
||||
}
|
||||
sbTips[part] = (WCHAR *) malloc((wcslen(szText) << 1) + 2);
|
||||
wcscpy(sbTips[part], szText);
|
||||
sbTips[part] = (WCHAR *) malloc((wcslen(tempTip) << 1) + 2);
|
||||
wcscpy(sbTips[part], tempTip);
|
||||
}
|
||||
|
||||
void update_tip(int meaning)
|
||||
@@ -1912,7 +1912,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
|
||||
if (video_fullscreen_first)
|
||||
{
|
||||
video_fullscreen_first = 0;
|
||||
msgbox_info(ghwnd, IDS_2193);
|
||||
msgbox_info(ghwnd, IDS_2074);
|
||||
}
|
||||
|
||||
startblit();
|
||||
@@ -2060,7 +2060,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
|
||||
|
||||
case IDM_CONFIG_LOAD:
|
||||
pause = 1;
|
||||
if (!file_dlg_st(hwnd, IDS_2174, "", 0))
|
||||
if (!file_dlg_st(hwnd, IDS_2160, "", 0))
|
||||
{
|
||||
if (msgbox_reset_yn(ghwnd) == IDYES)
|
||||
{
|
||||
@@ -2125,7 +2125,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
|
||||
|
||||
case IDM_CONFIG_SAVE:
|
||||
pause = 1;
|
||||
if (!file_dlg_st(hwnd, IDS_2174, "", 1))
|
||||
if (!file_dlg_st(hwnd, IDS_2160, "", 1))
|
||||
{
|
||||
config_save(wopenfilestring);
|
||||
}
|
||||
@@ -2361,7 +2361,7 @@ LRESULT CALLBACK StatusBarProcedure(HWND hwnd, UINT message, WPARAM wParam, LPAR
|
||||
break;
|
||||
}
|
||||
|
||||
ret = file_dlg_w_st(hwnd, IDS_2173, discfns[id], 0);
|
||||
ret = file_dlg_w_st(hwnd, IDS_2159, discfns[id], 0);
|
||||
if (!ret)
|
||||
{
|
||||
disc_close(id);
|
||||
@@ -2417,7 +2417,7 @@ LRESULT CALLBACK StatusBarProcedure(HWND hwnd, UINT message, WPARAM wParam, LPAR
|
||||
break;
|
||||
}
|
||||
|
||||
if (!file_dlg_w_st(hwnd, IDS_2175, cdrom_image[id].image_path, 0))
|
||||
if (!file_dlg_w_st(hwnd, IDS_2075, cdrom_image[id].image_path, 0))
|
||||
{
|
||||
cdrom_drives[id].prev_host_drive = cdrom_drives[id].host_drive;
|
||||
wcscpy(temp_image_path, wopenfilestring);
|
||||
@@ -2506,7 +2506,7 @@ LRESULT CALLBACK StatusBarProcedure(HWND hwnd, UINT message, WPARAM wParam, LPAR
|
||||
case IDM_RDISK_IMAGE:
|
||||
case IDM_RDISK_IMAGE_WP:
|
||||
id = item_params & 0x001f;
|
||||
ret = file_dlg_w_st(hwnd, IDS_2172, hdc[id].fn, id);
|
||||
ret = file_dlg_w_st(hwnd, IDS_4106, hdc[id].fn, id);
|
||||
if (!ret)
|
||||
{
|
||||
removable_disk_unload(id);
|
||||
|
||||
@@ -118,7 +118,7 @@ void SaveBitmap(wchar_t *szFilename,HBITMAP hBitmap)
|
||||
|
||||
if((fp = _wfopen(szFilename,L"wb"))==NULL)
|
||||
{
|
||||
_swprintf(szMessage, win_language_get_string_from_id(2194), szFilename);
|
||||
_swprintf(szMessage, win_language_get_string_from_id(IDS_2073), szFilename);
|
||||
msgbox_error_wstr(ghwnd, szMessage);
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -37,7 +37,20 @@ LCID dwLanguage;
|
||||
|
||||
uint32_t dwLangID, dwSubLangID;
|
||||
|
||||
WCHAR lpResourceString[STRINGS_NUM][512];
|
||||
typedef struct
|
||||
{
|
||||
WCHAR lpString[512];
|
||||
} resource_string_t;
|
||||
|
||||
resource_string_t *lpResourceString2048;
|
||||
resource_string_t *lpResourceString3072;
|
||||
resource_string_t *lpResourceString4096;
|
||||
resource_string_t *lpResourceString4352;
|
||||
resource_string_t *lpResourceString4608;
|
||||
resource_string_t *lpResourceString5120;
|
||||
resource_string_t *lpResourceString5376;
|
||||
resource_string_t *lpResourceString5632;
|
||||
resource_string_t *lpResourceString6144;
|
||||
|
||||
char openfilestring[260];
|
||||
WCHAR wopenfilestring[260];
|
||||
@@ -51,15 +64,65 @@ void win_language_load_common_strings()
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < STRINGS_NUM; i++)
|
||||
lpResourceString2048 = (resource_string_t *) malloc(STRINGS_NUM_2048 * sizeof(resource_string_t));
|
||||
lpResourceString3072 = (resource_string_t *) malloc(STRINGS_NUM_3072 * sizeof(resource_string_t));
|
||||
lpResourceString4096 = (resource_string_t *) malloc(STRINGS_NUM_4096 * sizeof(resource_string_t));
|
||||
lpResourceString4352 = (resource_string_t *) malloc(STRINGS_NUM_4352 * sizeof(resource_string_t));
|
||||
lpResourceString4608 = (resource_string_t *) malloc(STRINGS_NUM_4608 * sizeof(resource_string_t));
|
||||
lpResourceString5120 = (resource_string_t *) malloc(STRINGS_NUM_5120 * sizeof(resource_string_t));
|
||||
lpResourceString5376 = (resource_string_t *) malloc(STRINGS_NUM_5376 * sizeof(resource_string_t));
|
||||
lpResourceString5632 = (resource_string_t *) malloc(STRINGS_NUM_5632 * sizeof(resource_string_t));
|
||||
lpResourceString6144 = (resource_string_t *) malloc(STRINGS_NUM_6144 * sizeof(resource_string_t));
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_2048; i++)
|
||||
{
|
||||
LoadString(hinstance, 2048 + i, lpResourceString[i], 512);
|
||||
LoadString(hinstance, 2048 + i, lpResourceString2048[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_3072; i++)
|
||||
{
|
||||
LoadString(hinstance, 3072 + i, lpResourceString3072[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_4096; i++)
|
||||
{
|
||||
LoadString(hinstance, 4096 + i, lpResourceString4096[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_4352; i++)
|
||||
{
|
||||
LoadString(hinstance, 4352 + i, lpResourceString4352[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_4608; i++)
|
||||
{
|
||||
LoadString(hinstance, 4608 + i, lpResourceString4608[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_5120; i++)
|
||||
{
|
||||
LoadString(hinstance, 5120 + i, lpResourceString5120[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_5376; i++)
|
||||
{
|
||||
LoadString(hinstance, 5376 + i, lpResourceString5376[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_5632; i++)
|
||||
{
|
||||
LoadString(hinstance, 5632 + i, lpResourceString5632[i].lpString, 512);
|
||||
}
|
||||
|
||||
for (i = 0; i < STRINGS_NUM_6144; i++)
|
||||
{
|
||||
LoadString(hinstance, 6144 + i, lpResourceString6144[i].lpString, 512);
|
||||
}
|
||||
}
|
||||
|
||||
LPTSTR win_language_get_settings_category(int i)
|
||||
{
|
||||
return lpResourceString[17 + i];
|
||||
return lpResourceString2048[17 + i].lpString;
|
||||
}
|
||||
|
||||
void win_language_update()
|
||||
@@ -81,7 +144,42 @@ void win_language_check()
|
||||
|
||||
LPTSTR win_language_get_string_from_id(int i)
|
||||
{
|
||||
return lpResourceString[i - 2048];
|
||||
if ((i >= 2048) && (i <= 3071))
|
||||
{
|
||||
return lpResourceString2048[i - 2048].lpString;
|
||||
}
|
||||
else if ((i >= 3072) && (i <= 4095))
|
||||
{
|
||||
return lpResourceString3072[i - 3072].lpString;
|
||||
}
|
||||
else if ((i >= 4096) && (i <= 4351))
|
||||
{
|
||||
return lpResourceString4096[i - 4096].lpString;
|
||||
}
|
||||
else if ((i >= 4352) && (i <= 4607))
|
||||
{
|
||||
return lpResourceString4352[i - 4352].lpString;
|
||||
}
|
||||
else if ((i >= 4608) && (i <= 5119))
|
||||
{
|
||||
return lpResourceString4608[i - 4608].lpString;
|
||||
}
|
||||
else if ((i >= 5120) && (i <= 5375))
|
||||
{
|
||||
return lpResourceString5120[i - 5120].lpString;
|
||||
}
|
||||
else if ((i >= 5376) && (i <= 5631))
|
||||
{
|
||||
return lpResourceString5376[i - 5376].lpString;
|
||||
}
|
||||
else if ((i >= 5632) && (i <= 6143))
|
||||
{
|
||||
return lpResourceString5632[i - 5632].lpString;
|
||||
}
|
||||
else
|
||||
{
|
||||
return lpResourceString6144[i - 6144].lpString;
|
||||
}
|
||||
}
|
||||
|
||||
wchar_t *plat_get_string_from_id(int i)
|
||||
@@ -91,37 +189,37 @@ wchar_t *plat_get_string_from_id(int i)
|
||||
|
||||
LPTSTR win_language_get_string_from_string(char *str)
|
||||
{
|
||||
return lpResourceString[atoi(str) - 2048];
|
||||
return win_language_get_string_from_id(atoi(str));
|
||||
}
|
||||
|
||||
int msgbox_reset(HWND hwndParent)
|
||||
{
|
||||
return MessageBox(hwndParent, lpResourceString[3], lpResourceString[0], MB_YESNOCANCEL | MB_ICONQUESTION);
|
||||
return MessageBox(hwndParent, lpResourceString2048[3].lpString, lpResourceString2048[0].lpString, MB_YESNOCANCEL | MB_ICONQUESTION);
|
||||
}
|
||||
|
||||
int msgbox_reset_yn(HWND hwndParent)
|
||||
{
|
||||
return MessageBox(hwndParent, lpResourceString[3], lpResourceString[0], MB_YESNO | MB_ICONQUESTION);
|
||||
return MessageBox(hwndParent, lpResourceString2048[3].lpString, lpResourceString2048[0].lpString, MB_YESNO | MB_ICONQUESTION);
|
||||
}
|
||||
|
||||
int msgbox_question(HWND hwndParent, int i)
|
||||
{
|
||||
return MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString[0], MB_YESNO | MB_ICONQUESTION);
|
||||
return MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString2048[0].lpString, MB_YESNO | MB_ICONQUESTION);
|
||||
}
|
||||
|
||||
void msgbox_info(HWND hwndParent, int i)
|
||||
{
|
||||
MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString[0], MB_OK | MB_ICONINFORMATION);
|
||||
MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString2048[0].lpString, MB_OK | MB_ICONINFORMATION);
|
||||
}
|
||||
|
||||
void msgbox_info_wstr(HWND hwndParent, WCHAR *wstr)
|
||||
{
|
||||
MessageBox(hwndParent, wstr, lpResourceString[0], MB_OK | MB_ICONINFORMATION);
|
||||
MessageBox(hwndParent, wstr, lpResourceString2048[0].lpString, MB_OK | MB_ICONINFORMATION);
|
||||
}
|
||||
|
||||
void msgbox_error(HWND hwndParent, int i)
|
||||
{
|
||||
MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString[1], MB_OK | MB_ICONWARNING);
|
||||
MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString2048[1].lpString, MB_OK | MB_ICONWARNING);
|
||||
}
|
||||
|
||||
void plat_msgbox_error(int i)
|
||||
@@ -131,12 +229,12 @@ void plat_msgbox_error(int i)
|
||||
|
||||
void msgbox_error_wstr(HWND hwndParent, WCHAR *wstr)
|
||||
{
|
||||
MessageBox(hwndParent, wstr, lpResourceString[1], MB_OK | MB_ICONWARNING);
|
||||
MessageBox(hwndParent, wstr, lpResourceString2048[1].lpString, MB_OK | MB_ICONWARNING);
|
||||
}
|
||||
|
||||
void msgbox_critical(HWND hwndParent, int i)
|
||||
{
|
||||
MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString[2], MB_OK | MB_ICONERROR);
|
||||
MessageBox(hwndParent, win_language_get_string_from_id(i), lpResourceString2048[2].lpString, MB_OK | MB_ICONERROR);
|
||||
}
|
||||
|
||||
void msgbox_fatal(HWND hwndParent, char *string)
|
||||
@@ -146,7 +244,7 @@ void msgbox_fatal(HWND hwndParent, char *string)
|
||||
|
||||
mbstowcs(lptsTemp, string, strlen(string) + 1);
|
||||
|
||||
MessageBox(hwndParent, lptsTemp, lpResourceString[2], MB_OK | MB_ICONERROR);
|
||||
MessageBox(hwndParent, lptsTemp, lpResourceString2048[2].lpString, MB_OK | MB_ICONERROR);
|
||||
|
||||
free(lptsTemp);
|
||||
}
|
||||
@@ -198,7 +296,7 @@ int file_dlg_w(HWND hwnd, WCHAR *f, WCHAR *fn, int save)
|
||||
}
|
||||
if (r)
|
||||
{
|
||||
wcstombs(openfilestring, wopenfilestring, 520);
|
||||
wcstombs(openfilestring, wopenfilestring, sizeof(openfilestring));
|
||||
pclog("File dialog return true\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -624,7 +624,7 @@ static BOOL CALLBACK win_settings_machine_proc(HWND hdlg, UINT message, WPARAM w
|
||||
deviceconfig_open(hdlg, (void *)model_getdevice(temp_model));
|
||||
break;
|
||||
case IDC_BUTTON_NVR_PATH:
|
||||
p = BrowseFolder(temp_nvr_path, win_language_get_string_from_id(IDS_2225));
|
||||
p = BrowseFolder(temp_nvr_path, win_language_get_string_from_id(IDS_2056));
|
||||
if (wcscmp(p, L""))
|
||||
{
|
||||
memset(temp_nvr_path, 0, sizeof(temp_nvr_path));
|
||||
@@ -663,7 +663,7 @@ static BOOL CALLBACK win_settings_machine_proc(HWND hdlg, UINT message, WPARAM w
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_MEMTEXT);
|
||||
SendMessage(h, WM_GETTEXT, 255, (LPARAM) lptsTemp);
|
||||
wcstombs(stransi, lptsTemp, (wcslen(lptsTemp) * 2) + 2);
|
||||
wcstombs(stransi, lptsTemp, 512);
|
||||
sscanf(stransi, "%i", &temp_mem_size);
|
||||
temp_mem_size &= ~(models[temp_model].ram_granularity - 1);
|
||||
if (temp_mem_size < models[temp_model].min_ram)
|
||||
@@ -765,7 +765,7 @@ static BOOL CALLBACK win_settings_video_proc(HWND hdlg, UINT message, WPARAM wPa
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_VIDEO);
|
||||
SendMessage(h, CB_GETLBTEXT, SendMessage(h, CB_GETCURSEL, 0, 0), (LPARAM) lptsTemp);
|
||||
wcstombs(stransi, lptsTemp, (wcslen(lptsTemp) * 2) + 2);
|
||||
wcstombs(stransi, lptsTemp, 512);
|
||||
gfx = video_card_getid(stransi);
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_CONFIGURE_VID);
|
||||
@@ -792,7 +792,7 @@ static BOOL CALLBACK win_settings_video_proc(HWND hdlg, UINT message, WPARAM wPa
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_VIDEO);
|
||||
SendMessage(h, CB_GETLBTEXT, SendMessage(h, CB_GETCURSEL, 0, 0), (LPARAM) lptsTemp);
|
||||
wcstombs(stransi, lptsTemp, (wcslen(lptsTemp) * 2) + 2);
|
||||
wcstombs(stransi, lptsTemp, 512);
|
||||
gfx = video_card_getid(stransi);
|
||||
temp_gfxcard = video_new_to_old(gfx);
|
||||
|
||||
@@ -828,7 +828,7 @@ static BOOL CALLBACK win_settings_video_proc(HWND hdlg, UINT message, WPARAM wPa
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_VIDEO);
|
||||
SendMessage(h, CB_GETLBTEXT, SendMessage(h, CB_GETCURSEL, 0, 0), (LPARAM) lptsTemp);
|
||||
wcstombs(stransi, lptsTemp, (wcslen(lptsTemp) * 2) + 2);
|
||||
wcstombs(stransi, lptsTemp, 512);
|
||||
deviceconfig_open(hdlg, (void *)video_card_getdevice(video_card_getid(stransi)));
|
||||
|
||||
free(stransi);
|
||||
@@ -843,7 +843,7 @@ static BOOL CALLBACK win_settings_video_proc(HWND hdlg, UINT message, WPARAM wPa
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_VIDEO);
|
||||
SendMessage(h, CB_GETLBTEXT, SendMessage(h, CB_GETCURSEL, 0, 0), (LPARAM) lptsTemp);
|
||||
wcstombs(stransi, lptsTemp, (wcslen(lptsTemp) * 2) + 2);
|
||||
wcstombs(stransi, lptsTemp, 512);
|
||||
temp_gfxcard = video_new_to_old(video_card_getid(stransi));
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_VIDEO_SPEED);
|
||||
@@ -900,40 +900,7 @@ static BOOL CALLBACK win_settings_input_proc(HWND hdlg, UINT message, WPARAM wPa
|
||||
|
||||
if (mouse_valid(type, temp_model))
|
||||
{
|
||||
switch(c)
|
||||
{
|
||||
case MOUSE_TYPE_NONE:
|
||||
str_id = IDS_2151;
|
||||
break;
|
||||
case MOUSE_TYPE_SERIAL:
|
||||
default:
|
||||
str_id = IDS_2139;
|
||||
break;
|
||||
case MOUSE_TYPE_PS2:
|
||||
str_id = IDS_2141;
|
||||
break;
|
||||
case MOUSE_TYPE_PS2_MS:
|
||||
str_id = IDS_2142;
|
||||
break;
|
||||
case MOUSE_TYPE_BUS:
|
||||
str_id = IDS_2143;
|
||||
break;
|
||||
case MOUSE_TYPE_AMSTRAD:
|
||||
str_id = IDS_2162;
|
||||
break;
|
||||
case MOUSE_TYPE_OLIM24:
|
||||
str_id = IDS_2177;
|
||||
break;
|
||||
case MOUSE_TYPE_MSYSTEMS:
|
||||
str_id = IDS_2140;
|
||||
break;
|
||||
case MOUSE_TYPE_LOGITECH:
|
||||
str_id = IDS_2224;
|
||||
break;
|
||||
case MOUSE_TYPE_GENIUS:
|
||||
str_id = IDS_2161;
|
||||
break;
|
||||
}
|
||||
str_id = IDS_3072 + c;
|
||||
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(str_id));
|
||||
|
||||
@@ -1498,7 +1465,7 @@ static BOOL CALLBACK win_settings_peripherals_proc(HWND hdlg, UINT message, WPAR
|
||||
recalc_hdd_list(hdlg, temp_model, 0);
|
||||
|
||||
h=GetDlgItem(hdlg, IDC_COMBO_IDE_TER);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2151));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_5376));
|
||||
|
||||
for (c = 0; c < 11; c++)
|
||||
{
|
||||
@@ -1516,7 +1483,7 @@ static BOOL CALLBACK win_settings_peripherals_proc(HWND hdlg, UINT message, WPAR
|
||||
}
|
||||
|
||||
h=GetDlgItem(hdlg, IDC_COMBO_IDE_QUA);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_2151));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_5376));
|
||||
|
||||
for (c = 0; c < 11; c++)
|
||||
{
|
||||
@@ -1921,41 +1888,36 @@ static void add_locations(HWND hdlg)
|
||||
lptsTemp = (LPTSTR) malloc(512);
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_BUS);
|
||||
for (i = 0; i < 4; i++)
|
||||
for (i = 0; i < 7; i++)
|
||||
{
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2165 + i));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_4352 + i));
|
||||
}
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2209 + i));
|
||||
}
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2202));
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_CHANNEL);
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(2169), i >> 1, i & 1);
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(IDS_4097), i >> 1, i & 1);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) lptsTemp);
|
||||
}
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_ID);
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(2088), i);
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(IDS_4098), i);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) lptsTemp);
|
||||
}
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_LUN);
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(2088), i);
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(IDS_4098), i);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) lptsTemp);
|
||||
}
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_CHANNEL_IDE);
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(2169), i >> 1, i & 1);
|
||||
wsprintf(lptsTemp, win_language_get_string_from_id(IDS_4097), i >> 1, i & 1);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) lptsTemp);
|
||||
}
|
||||
|
||||
@@ -2010,16 +1972,6 @@ static void recalc_location_controls(HWND hdlg, int is_add_dlg)
|
||||
EnableWindow(h, TRUE);
|
||||
SendMessage(h, CB_SETCURSEL, is_add_dlg ? new_hdc.mfm_channel : temp_hdc[hdlv_current_sel].mfm_channel, 0);
|
||||
break;
|
||||
case HDD_BUS_RLL: /* RLL */
|
||||
h = GetDlgItem(hdlg, IDT_1722);
|
||||
ShowWindow(h, SW_SHOW);
|
||||
EnableWindow(h, TRUE);
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_CHANNEL);
|
||||
ShowWindow(h, SW_SHOW);
|
||||
EnableWindow(h, TRUE);
|
||||
SendMessage(h, CB_SETCURSEL, is_add_dlg ? new_hdc.rll_channel : temp_hdc[hdlv_current_sel].rll_channel, 0);
|
||||
break;
|
||||
case HDD_BUS_XTIDE: /* XT IDE */
|
||||
h = GetDlgItem(hdlg, IDT_1722);
|
||||
ShowWindow(h, SW_SHOW);
|
||||
@@ -2030,6 +1982,16 @@ static void recalc_location_controls(HWND hdlg, int is_add_dlg)
|
||||
EnableWindow(h, TRUE);
|
||||
SendMessage(h, CB_SETCURSEL, is_add_dlg ? new_hdc.xtide_channel : temp_hdc[hdlv_current_sel].xtide_channel, 0);
|
||||
break;
|
||||
case HDD_BUS_RLL: /* RLL */
|
||||
h = GetDlgItem(hdlg, IDT_1722);
|
||||
ShowWindow(h, SW_SHOW);
|
||||
EnableWindow(h, TRUE);
|
||||
|
||||
h = GetDlgItem(hdlg, IDC_COMBO_HD_CHANNEL);
|
||||
ShowWindow(h, SW_SHOW);
|
||||
EnableWindow(h, TRUE);
|
||||
SendMessage(h, CB_SETCURSEL, is_add_dlg ? new_hdc.rll_channel : temp_hdc[hdlv_current_sel].rll_channel, 0);
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_ONLY: /* IDE (PIO-only) */
|
||||
case HDD_BUS_IDE_PIO_AND_DMA: /* IDE (PIO and DMA) */
|
||||
h = GetDlgItem(hdlg, IDT_1722);
|
||||
@@ -2197,25 +2159,25 @@ static void win_settings_hard_disks_update_item(HWND hwndList, int i, int column
|
||||
switch(temp_hdc[i].bus)
|
||||
{
|
||||
case HDD_BUS_MFM:
|
||||
wsprintf(szText, win_language_get_string_from_id(2156), temp_hdc[i].mfm_channel >> 1, temp_hdc[i].mfm_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_RLL:
|
||||
wsprintf(szText, win_language_get_string_from_id(2205), temp_hdc[i].rll_channel >> 1, temp_hdc[i].rll_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4608), temp_hdc[i].mfm_channel >> 1, temp_hdc[i].mfm_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_XTIDE:
|
||||
wsprintf(szText, win_language_get_string_from_id(2206), temp_hdc[i].xtide_channel >> 1, temp_hdc[i].xtide_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4609), temp_hdc[i].xtide_channel >> 1, temp_hdc[i].xtide_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_RLL:
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4610), temp_hdc[i].rll_channel >> 1, temp_hdc[i].rll_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_ONLY:
|
||||
wsprintf(szText, win_language_get_string_from_id(2195), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4611), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_AND_DMA:
|
||||
wsprintf(szText, win_language_get_string_from_id(2157), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4612), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_SCSI:
|
||||
wsprintf(szText, win_language_get_string_from_id(2158), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4613), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
break;
|
||||
case HDD_BUS_SCSI_REMOVABLE:
|
||||
wsprintf(szText, win_language_get_string_from_id(2203), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4614), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
break;
|
||||
}
|
||||
lvI.pszText = szText;
|
||||
@@ -2228,25 +2190,25 @@ static void win_settings_hard_disks_update_item(HWND hwndList, int i, int column
|
||||
}
|
||||
else if (column == 2)
|
||||
{
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), temp_hdc[i].tracks);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), temp_hdc[i].tracks);
|
||||
lvI.pszText = szText;
|
||||
lvI.iImage = 0;
|
||||
}
|
||||
else if (column == 3)
|
||||
{
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), temp_hdc[i].hpc);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), temp_hdc[i].hpc);
|
||||
lvI.pszText = szText;
|
||||
lvI.iImage = 0;
|
||||
}
|
||||
else if (column == 4)
|
||||
{
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), temp_hdc[i].spt);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), temp_hdc[i].spt);
|
||||
lvI.pszText = szText;
|
||||
lvI.iImage = 0;
|
||||
}
|
||||
else if (column == 5)
|
||||
{
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), (temp_hdc[i].tracks * temp_hdc[i].hpc * temp_hdc[i].spt) >> 11);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), (temp_hdc[i].tracks * temp_hdc[i].hpc * temp_hdc[i].spt) >> 11);
|
||||
lvI.pszText = szText;
|
||||
lvI.iImage = 0;
|
||||
}
|
||||
@@ -2281,25 +2243,25 @@ static BOOL win_settings_hard_disks_recalc_list(HWND hwndList)
|
||||
switch(temp_hdc[i].bus)
|
||||
{
|
||||
case HDD_BUS_MFM:
|
||||
wsprintf(szText, win_language_get_string_from_id(2156), temp_hdc[i].mfm_channel >> 1, temp_hdc[i].mfm_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_RLL:
|
||||
wsprintf(szText, win_language_get_string_from_id(2205), temp_hdc[i].rll_channel >> 1, temp_hdc[i].rll_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4608), temp_hdc[i].mfm_channel >> 1, temp_hdc[i].mfm_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_XTIDE:
|
||||
wsprintf(szText, win_language_get_string_from_id(2206), temp_hdc[i].xtide_channel >> 1, temp_hdc[i].xtide_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4609), temp_hdc[i].xtide_channel >> 1, temp_hdc[i].xtide_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_RLL:
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4610), temp_hdc[i].rll_channel >> 1, temp_hdc[i].rll_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_ONLY:
|
||||
wsprintf(szText, win_language_get_string_from_id(2195), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4611), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_IDE_PIO_AND_DMA:
|
||||
wsprintf(szText, win_language_get_string_from_id(2157), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4612), temp_hdc[i].ide_channel >> 1, temp_hdc[i].ide_channel & 1);
|
||||
break;
|
||||
case HDD_BUS_SCSI:
|
||||
wsprintf(szText, win_language_get_string_from_id(2158), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4613), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
break;
|
||||
case HDD_BUS_SCSI_REMOVABLE:
|
||||
wsprintf(szText, win_language_get_string_from_id(2203), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4614), temp_hdc[i].scsi_id, temp_hdc[i].scsi_lun);
|
||||
break;
|
||||
}
|
||||
lvI.pszText = szText;
|
||||
@@ -2322,7 +2284,7 @@ static BOOL win_settings_hard_disks_recalc_list(HWND hwndList)
|
||||
}
|
||||
|
||||
lvI.iSubItem = 2;
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), temp_hdc[i].tracks);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), temp_hdc[i].tracks);
|
||||
lvI.pszText = szText;
|
||||
lvI.iItem = j;
|
||||
lvI.iImage = 0;
|
||||
@@ -2333,7 +2295,7 @@ static BOOL win_settings_hard_disks_recalc_list(HWND hwndList)
|
||||
}
|
||||
|
||||
lvI.iSubItem = 3;
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), temp_hdc[i].hpc);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), temp_hdc[i].hpc);
|
||||
lvI.pszText = szText;
|
||||
lvI.iItem = j;
|
||||
lvI.iImage = 0;
|
||||
@@ -2344,7 +2306,7 @@ static BOOL win_settings_hard_disks_recalc_list(HWND hwndList)
|
||||
}
|
||||
|
||||
lvI.iSubItem = 4;
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), temp_hdc[i].spt);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), temp_hdc[i].spt);
|
||||
lvI.pszText = szText;
|
||||
lvI.iItem = j;
|
||||
lvI.iImage = 0;
|
||||
@@ -2355,7 +2317,7 @@ static BOOL win_settings_hard_disks_recalc_list(HWND hwndList)
|
||||
}
|
||||
|
||||
lvI.iSubItem = 5;
|
||||
wsprintf(szText, win_language_get_string_from_id(2088), (temp_hdc[i].tracks * temp_hdc[i].hpc * temp_hdc[i].spt) >> 11);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_4098), (temp_hdc[i].tracks * temp_hdc[i].hpc * temp_hdc[i].spt) >> 11);
|
||||
lvI.pszText = szText;
|
||||
lvI.iItem = j;
|
||||
lvI.iImage = 0;
|
||||
@@ -2436,7 +2398,7 @@ static void get_edit_box_contents(HWND hdlg, int id, uint64_t *val)
|
||||
|
||||
h = GetDlgItem(hdlg, id);
|
||||
SendMessage(h, WM_GETTEXT, 255, (LPARAM) szText);
|
||||
wcstombs(stransi, szText, (wcslen(szText) * 2) + 2);
|
||||
wcstombs(stransi, szText, 256);
|
||||
sscanf(stransi, "%" PRIu64, val);
|
||||
}
|
||||
|
||||
@@ -2454,7 +2416,7 @@ static void set_edit_box_contents(HWND hdlg, int id, uint64_t val)
|
||||
WCHAR szText[256];
|
||||
|
||||
h = GetDlgItem(hdlg, id);
|
||||
wsprintf(szText, win_language_get_string_from_id(2160), val);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_2156), val);
|
||||
SendMessage(h, WM_SETTEXT, (WPARAM) wcslen(szText), (LPARAM) szText);
|
||||
}
|
||||
|
||||
@@ -2488,15 +2450,15 @@ static int hdconf_initialize_hdt_combo(HWND hdlg)
|
||||
{
|
||||
temp_size = hdt[i][0] * hdt[i][1] * hdt[i][2];
|
||||
size_mb = temp_size >> 11;
|
||||
wsprintf(szText, win_language_get_string_from_id(2171), size_mb, hdt[i][0], hdt[i][1], hdt[i][2]);
|
||||
wsprintf(szText, win_language_get_string_from_id(IDS_2157), size_mb, hdt[i][0], hdt[i][1], hdt[i][2]);
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) szText);
|
||||
if ((tracks == hdt[i][0]) && (hpc == hdt[i][1]) && (spt == hdt[i][2]))
|
||||
{
|
||||
selection = i;
|
||||
}
|
||||
}
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2170));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2187));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_4100));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_4101));
|
||||
SendMessage(h, CB_SETCURSEL, selection, 0);
|
||||
return selection;
|
||||
}
|
||||
@@ -2555,7 +2517,7 @@ static BOOL CALLBACK win_settings_hard_disks_add_proc(HWND hdlg, UINT message, W
|
||||
hdc_ptr = &(temp_hdc[next_free_id]);
|
||||
}
|
||||
|
||||
SetWindowText(hdlg, win_language_get_string_from_id((existing & 1) ? 2197 : 2196));
|
||||
SetWindowText(hdlg, win_language_get_string_from_id((existing & 1) ? IDS_4103 : IDS_4102));
|
||||
|
||||
no_update = 1;
|
||||
spt = (existing & 1) ? 0 : 17;
|
||||
@@ -2656,7 +2618,7 @@ static BOOL CALLBACK win_settings_hard_disks_add_proc(HWND hdlg, UINT message, W
|
||||
if ((wcslen(hd_file_name) == 0) && (hdc_ptr->bus != HDD_BUS_SCSI_REMOVABLE))
|
||||
{
|
||||
hdc_ptr->bus = HDD_BUS_DISABLED;
|
||||
msgbox_error(hwndParentDialog, IDS_2056);
|
||||
msgbox_error(hwndParentDialog, IDS_4112);
|
||||
return TRUE;
|
||||
}
|
||||
else if ((wcslen(hd_file_name) == 0) && (hdc_ptr->bus == HDD_BUS_SCSI_REMOVABLE))
|
||||
@@ -2728,7 +2690,7 @@ static BOOL CALLBACK win_settings_hard_disks_add_proc(HWND hdlg, UINT message, W
|
||||
if (size >= 0x100000000ll)
|
||||
{
|
||||
fclose(f);
|
||||
msgbox_error(hwndParentDialog, IDS_2058);
|
||||
msgbox_error(hwndParentDialog, IDS_4104);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@@ -2751,7 +2713,7 @@ static BOOL CALLBACK win_settings_hard_disks_add_proc(HWND hdlg, UINT message, W
|
||||
if (size > 0xffffffffffffffffll)
|
||||
{
|
||||
fclose(f);
|
||||
msgbox_error(hwndParentDialog, IDS_2163);
|
||||
msgbox_error(hwndParentDialog, IDS_4105);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@@ -2791,7 +2753,7 @@ static BOOL CALLBACK win_settings_hard_disks_add_proc(HWND hdlg, UINT message, W
|
||||
}
|
||||
|
||||
fclose(f);
|
||||
msgbox_info(hwndParentDialog, IDS_2059);
|
||||
msgbox_info(hwndParentDialog, IDS_4113);
|
||||
}
|
||||
|
||||
hd_add_ok_common:
|
||||
@@ -2809,7 +2771,7 @@ hd_add_ok_common:
|
||||
return TRUE;
|
||||
|
||||
case IDC_CFILE:
|
||||
if (!file_dlg_w(hdlg, win_language_get_string_from_id(2172), L"", !(existing & 1)))
|
||||
if (!file_dlg_w(hdlg, win_language_get_string_from_id(IDS_4106), L"", !(existing & 1)))
|
||||
{
|
||||
if (!(existing & 1))
|
||||
{
|
||||
@@ -2817,7 +2779,7 @@ hd_add_ok_common:
|
||||
if (f != NULL)
|
||||
{
|
||||
fclose(f);
|
||||
if (msgbox_question(ghwnd, IDS_2178) != IDYES)
|
||||
if (msgbox_question(ghwnd, IDS_4111) != IDYES)
|
||||
{
|
||||
return FALSE;
|
||||
}
|
||||
@@ -2828,7 +2790,7 @@ hd_add_ok_common:
|
||||
if (f == NULL)
|
||||
{
|
||||
hdd_add_file_open_error:
|
||||
msgbox_error(hwndParentDialog, (existing & 1) ? 2060 : 2057);
|
||||
msgbox_error(hwndParentDialog, (existing & 1) ? IDS_4107 : IDS_4108);
|
||||
return TRUE;
|
||||
}
|
||||
if (existing & 1)
|
||||
@@ -2839,7 +2801,7 @@ hdd_add_file_open_error:
|
||||
fread(§or_size, 1, 4, f);
|
||||
if (sector_size != 512)
|
||||
{
|
||||
msgbox_error(hwndParentDialog, IDS_2061);
|
||||
msgbox_error(hwndParentDialog, IDS_4109);
|
||||
fclose(f);
|
||||
return TRUE;
|
||||
}
|
||||
@@ -3471,42 +3433,12 @@ int cdlv_current_sel;
|
||||
|
||||
static int combo_id_to_string_id(int combo_id)
|
||||
{
|
||||
switch (combo_id)
|
||||
{
|
||||
case CDROM_BUS_DISABLED: /* Disabled */
|
||||
default:
|
||||
return 2151;
|
||||
break;
|
||||
case CDROM_BUS_ATAPI_PIO_ONLY: /* Atapi (PIO-only) */
|
||||
return 2189;
|
||||
break;
|
||||
case CDROM_BUS_ATAPI_PIO_AND_DMA: /* Atapi (PIA and DMA) */
|
||||
return 2190;
|
||||
break;
|
||||
case CDROM_BUS_SCSI: /* SCSI */
|
||||
return 2210;
|
||||
break;
|
||||
}
|
||||
return IDS_5376 + combo_id;
|
||||
}
|
||||
|
||||
static int combo_id_to_format_string_id(int combo_id)
|
||||
{
|
||||
switch (combo_id)
|
||||
{
|
||||
case CDROM_BUS_DISABLED: /* Disabled */
|
||||
default:
|
||||
return 2151;
|
||||
break;
|
||||
case CDROM_BUS_ATAPI_PIO_ONLY: /* Atapi (PIO-only) */
|
||||
return 2191;
|
||||
break;
|
||||
case CDROM_BUS_ATAPI_PIO_AND_DMA: /* Atapi (PIA and DMA) */
|
||||
return 2192;
|
||||
break;
|
||||
case CDROM_BUS_SCSI: /* SCSI */
|
||||
return 2158;
|
||||
break;
|
||||
}
|
||||
return IDS_5632 + combo_id;
|
||||
}
|
||||
|
||||
static BOOL win_settings_floppy_drives_image_list_init(HWND hwndList)
|
||||
@@ -3583,7 +3515,7 @@ static BOOL win_settings_floppy_drives_recalc_list(HWND hwndList)
|
||||
}
|
||||
else
|
||||
{
|
||||
lvI.pszText = win_language_get_string_from_id(2151);
|
||||
lvI.pszText = win_language_get_string_from_id(IDS_5376);
|
||||
}
|
||||
lvI.iItem = i;
|
||||
lvI.iImage = temp_fdd_types[i];
|
||||
@@ -3592,7 +3524,7 @@ static BOOL win_settings_floppy_drives_recalc_list(HWND hwndList)
|
||||
return FALSE;
|
||||
|
||||
lvI.iSubItem = 1;
|
||||
lvI.pszText = win_language_get_string_from_id(temp_fdd_turbo[i] ? 2222 : 2223);
|
||||
lvI.pszText = win_language_get_string_from_id(temp_fdd_turbo[i] ? IDS_2060 : IDS_2061);
|
||||
lvI.iItem = i;
|
||||
lvI.iImage = 0;
|
||||
|
||||
@@ -3659,7 +3591,7 @@ static BOOL win_settings_floppy_drives_init_columns(HWND hwndList)
|
||||
lvc.mask = LVCF_FMT | LVCF_WIDTH | LVCF_TEXT | LVCF_SUBITEM;
|
||||
|
||||
lvc.iSubItem = 0;
|
||||
lvc.pszText = win_language_get_string_from_id(2188);
|
||||
lvc.pszText = win_language_get_string_from_id(IDS_2143);
|
||||
|
||||
lvc.cx = 292;
|
||||
lvc.fmt = LVCFMT_LEFT;
|
||||
@@ -3670,7 +3602,7 @@ static BOOL win_settings_floppy_drives_init_columns(HWND hwndList)
|
||||
}
|
||||
|
||||
lvc.iSubItem = 1;
|
||||
lvc.pszText = win_language_get_string_from_id(2221);
|
||||
lvc.pszText = win_language_get_string_from_id(IDS_2059);
|
||||
|
||||
lvc.cx = 100;
|
||||
lvc.fmt = LVCFMT_LEFT;
|
||||
@@ -3761,7 +3693,7 @@ static void win_settings_floppy_drives_update_item(HWND hwndList, int i)
|
||||
}
|
||||
else
|
||||
{
|
||||
lvI.pszText = win_language_get_string_from_id(2151);
|
||||
lvI.pszText = win_language_get_string_from_id(IDS_5376);
|
||||
}
|
||||
lvI.iImage = temp_fdd_types[i];
|
||||
|
||||
@@ -3771,7 +3703,7 @@ static void win_settings_floppy_drives_update_item(HWND hwndList, int i)
|
||||
}
|
||||
|
||||
lvI.iSubItem = 1;
|
||||
lvI.pszText = win_language_get_string_from_id(temp_fdd_turbo[i] ? 2222 : 2223);
|
||||
lvI.pszText = win_language_get_string_from_id(temp_fdd_turbo[i] ? IDS_2060 : IDS_2061);
|
||||
lvI.iItem = i;
|
||||
lvI.iImage = 0;
|
||||
|
||||
@@ -3953,7 +3885,7 @@ static BOOL CALLBACK win_settings_removable_devices_proc(HWND hdlg, UINT message
|
||||
{
|
||||
if (i == 0)
|
||||
{
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(2151));
|
||||
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) win_language_get_string_from_id(IDS_5376));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@@ -1,38 +0,0 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#include "ibm.h"
|
||||
#include "cpu/cpu.h"
|
||||
#include "io.h"
|
||||
#include "device.h"
|
||||
#include "model.h"
|
||||
|
||||
|
||||
static int acerm3a_index;
|
||||
|
||||
|
||||
static void acerm3a_write(uint16_t port, uint8_t val, void *p)
|
||||
{
|
||||
if (port == 0xea)
|
||||
acerm3a_index = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t acerm3a_read(uint16_t port, void *p)
|
||||
{
|
||||
if (port == 0xeb)
|
||||
{
|
||||
switch (acerm3a_index)
|
||||
{
|
||||
case 2:
|
||||
return 0xfd;
|
||||
}
|
||||
}
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
|
||||
void acerm3a_io_init(void)
|
||||
{
|
||||
io_sethandler(0x00ea, 0x0002, acerm3a_read, NULL, NULL, acerm3a_write, NULL, NULL, NULL);
|
||||
}
|
||||
@@ -247,7 +247,11 @@ bool CDROM_Interface_Image::LoadIsoFile(char* filename)
|
||||
} else if (CanReadPVD(track.file, RAW_SECTOR_SIZE, true)) {
|
||||
track.sectorSize = RAW_SECTOR_SIZE;
|
||||
track.mode2 = true;
|
||||
} else return false;
|
||||
} else {
|
||||
/* Unknown mode: Assume regular 2048-byte sectors, this is needed so Apple Rhapsody ISO's can be mounted. */
|
||||
track.sectorSize = COOKED_SECTOR_SIZE;
|
||||
track.mode2 = false;
|
||||
}
|
||||
|
||||
track.length = track.file->getLength() / track.sectorSize;
|
||||
tracks.push_back(track);
|
||||
|
||||
@@ -171,4 +171,6 @@ typedef std::vector<Track>::iterator track_it;
|
||||
std::string mcn;
|
||||
};
|
||||
|
||||
void cdrom_image_log(const char *format, ...);
|
||||
|
||||
#endif /* __CDROM_INTERFACE__ */
|
||||
|
||||
@@ -985,9 +985,10 @@ int image_open(uint8_t id, wchar_t *fn)
|
||||
}
|
||||
|
||||
cdimg[id] = new CDROM_Interface_Image();
|
||||
wcstombs(afn, fn, (wcslen(fn) << 1) + 2);
|
||||
wcstombs(afn, fn, sizeof(afn));
|
||||
if (!cdimg[id]->SetDevice(afn, false))
|
||||
{
|
||||
pclog("Image failed to load\n");
|
||||
image_close(id);
|
||||
cdrom_set_null_handler(id);
|
||||
return 1;
|
||||
|
||||
18
src/config.c
18
src/config.c
@@ -225,7 +225,7 @@ int config_load(wchar_t *fn)
|
||||
strncpy(new_entry->name, ename, 256);
|
||||
memcpy(new_entry->wdata, &cfgbuffer[data_pos], 512);
|
||||
new_entry->wdata[255] = L'\0';
|
||||
wcstombs(new_entry->data, new_entry->wdata, 512);
|
||||
wcstombs(new_entry->data, new_entry->wdata, sizeof(new_entry->data));
|
||||
new_entry->data[255] = '\0';
|
||||
list_add(&new_entry->list, ¤t_section->entry_head);
|
||||
}
|
||||
@@ -471,7 +471,8 @@ void config_delete_var(char *head, char *name)
|
||||
if (!entry)
|
||||
return;
|
||||
|
||||
memset(entry->name, 0, strlen(entry->name));
|
||||
/* memset(entry->name, 0, strlen(entry->name)); */
|
||||
entry->name[0] = 0;
|
||||
|
||||
return;
|
||||
}
|
||||
@@ -488,7 +489,8 @@ void config_delete_section_if_empty(char *head)
|
||||
|
||||
if (entries_num(section) == 0)
|
||||
{
|
||||
memset(section->name, 0, strlen(section->name));
|
||||
/* memset(section->name, 0, strlen(section->name)); */
|
||||
section->name[0] = 0;
|
||||
}
|
||||
|
||||
return;
|
||||
@@ -742,7 +744,7 @@ void config_save(wchar_t *fn)
|
||||
|
||||
while (current_entry)
|
||||
{
|
||||
if(strlen(current_entry->name) > 0)
|
||||
if(current_entry->name[0])
|
||||
{
|
||||
mbstowcs(wname, current_entry->name, strlen(current_entry->name) + 1);
|
||||
if (current_entry->wdata[0] == L'\0')
|
||||
@@ -1056,11 +1058,11 @@ static void loadconfig_network(void)
|
||||
{
|
||||
if ((network_ndev == 1) && strcmp(network_pcap, "none"))
|
||||
{
|
||||
msgbox_error(ghwnd, IDS_2107);
|
||||
msgbox_error(ghwnd, IDS_2140);
|
||||
}
|
||||
else if (network_dev_to_id(p) == -1)
|
||||
{
|
||||
msgbox_error(ghwnd, IDS_2200);
|
||||
msgbox_error(ghwnd, IDS_2141);
|
||||
}
|
||||
|
||||
strcpy(network_pcap, "none");
|
||||
@@ -1218,14 +1220,14 @@ static int config_string_to_bus(char *str, int cdrom)
|
||||
|
||||
if (!strcmp(str, "usb"))
|
||||
{
|
||||
msgbox_error(ghwnd, IDS_2199);
|
||||
msgbox_error(ghwnd, IDS_4110);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
no_mfm_cdrom:
|
||||
msgbox_error(ghwnd, IDS_2095);
|
||||
msgbox_error(ghwnd, IDS_4114);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -488,6 +488,9 @@ void fdc37c932fr_reset(void)
|
||||
fdc_update_drvrate(3, 0);
|
||||
fdc_update_max_track(79);
|
||||
|
||||
memset(fdc37c932fr_gpio_regs, 0, sizeof(fdc37c932fr_gpio_regs));
|
||||
fdc37c932fr_gpio_regs[2] = 0xfd;
|
||||
|
||||
fdc37c932fr_locked = 0;
|
||||
}
|
||||
|
||||
@@ -498,6 +501,8 @@ void fdc37c932fr_init()
|
||||
fdc37c932fr_reset();
|
||||
|
||||
io_sethandler(0xe0, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
||||
io_sethandler(0xe2, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
||||
io_sethandler(0xe4, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
||||
io_sethandler(0xea, 0x0002, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
||||
io_sethandler(0x3f0, 0x0002, fdc37c932fr_read, NULL, NULL, fdc37c932fr_write, NULL, NULL, NULL);
|
||||
|
||||
|
||||
15
src/ibm.h
15
src/ibm.h
@@ -428,10 +428,12 @@ enum
|
||||
ROM_REVENGE,
|
||||
ROM_IBMPS1_2011,
|
||||
ROM_DESKPRO_386,
|
||||
ROM_PORTABLE,
|
||||
ROM_PORTABLEII,
|
||||
ROM_PORTABLEIII,
|
||||
ROM_PORTABLEIII386, /* The original Compaq Portable III shipped with an Intel 80286 CPU, but later switched to a 386DX. */
|
||||
ROM_PORTABLE,
|
||||
#if 0
|
||||
ROM_PORTABLEII,
|
||||
ROM_PORTABLEIII,
|
||||
ROM_PORTABLEIII386, /* The original Compaq Portable III shipped with an Intel 80286 CPU, but later switched to a 386DX. */
|
||||
#endif
|
||||
ROM_IBMPS1_2121,
|
||||
|
||||
ROM_AMI386DX_OPTI495,
|
||||
@@ -469,6 +471,10 @@ enum
|
||||
ROM_SPC4200P, /*Samsung SPC-4200P / SCAT / Phoenix BIOS*/
|
||||
ROM_SUPER286TR, /*Hyundai Super-286TR / SCAT / Award BIOS*/
|
||||
|
||||
ROM_AWARD386SX_OPTI495,
|
||||
ROM_AWARD386DX_OPTI495,
|
||||
ROM_AWARD486_OPTI495,
|
||||
|
||||
ROM_MEGAPCDX, /*386DX mdoel of the Mega PC - Note by Tohka: The documentation (that I have in German) clearly says such a model exists.*/
|
||||
ROM_ZAPPA, /*Intel Advanced/ZP / 430FX / AMI BIOS / National Semiconductors PC87306*/
|
||||
|
||||
@@ -769,7 +775,6 @@ extern void pmodeiret(int is32);
|
||||
extern void port_92_clear_reset(void);
|
||||
extern uint8_t readdacfifo(void);
|
||||
extern void refreshread(void);
|
||||
extern int rep386(int fv);
|
||||
extern void resetmcr(void);
|
||||
extern void resetpchard_close(void);
|
||||
extern void resetpchard_init(void);
|
||||
|
||||
11
src/mem.c
11
src/mem.c
@@ -216,6 +216,7 @@ int loadbios()
|
||||
fclose(f);
|
||||
return 1;
|
||||
|
||||
#if 0
|
||||
case ROM_PORTABLEII:
|
||||
f = romfopen(L"roms/machines/portableii/106438-001.BIN", L"rb");
|
||||
ff =romfopen(L"roms/machines/portableii/106437-001.BIN", L"rb");
|
||||
@@ -243,6 +244,7 @@ int loadbios()
|
||||
fclose(ff);
|
||||
fclose(f);
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
case ROM_GENXT:
|
||||
f=romfopen(L"roms/machines/genxt/pcxt.rom",L"rb");
|
||||
@@ -346,6 +348,15 @@ int loadbios()
|
||||
fclose(f);
|
||||
return 1;
|
||||
|
||||
case ROM_AWARD386SX_OPTI495: /*This uses the OPTi 82C495 chipset*/
|
||||
case ROM_AWARD386DX_OPTI495: /*This uses the OPTi 82C495 chipset*/
|
||||
case ROM_AWARD486_OPTI495: /*This uses the OPTi 82C495 chipset*/
|
||||
f=romfopen(L"roms/machines/award495/OPT495S.AWA",L"rb");
|
||||
if (!f) break;
|
||||
fread(rom,65536,1,f);
|
||||
fclose(f);
|
||||
return 1;
|
||||
|
||||
case ROM_AMI286:
|
||||
f=romfopen(L"roms/machines/ami286/amic206.bin",L"rb");
|
||||
if (!f) break;
|
||||
|
||||
18
src/model.c
18
src/model.c
@@ -165,8 +165,10 @@ MODEL models[] =
|
||||
|
||||
{"[286] AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL },
|
||||
{"[286] Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
|
||||
#if 0
|
||||
{"[286] Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
|
||||
{"[286] Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
|
||||
#endif
|
||||
{"[286] Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 640,16384, 128, 127, cmdpc30_init, NULL },
|
||||
{"[286] Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
|
||||
{"[286] IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 256,15872, 128, 63, ibm_at_init, NULL },
|
||||
@@ -177,6 +179,7 @@ MODEL models[] =
|
||||
|
||||
{"[386SX] AMI 386SX clone", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_headland_init, NULL },
|
||||
{"[386SX] Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL },
|
||||
{"[386SX] Award 386SX clone", ROM_AWARD386SX_OPTI495, "award386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
|
||||
{"[386SX] DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL },
|
||||
{"[386SX] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL },
|
||||
{"[386SX] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL },
|
||||
@@ -184,13 +187,17 @@ MODEL models[] =
|
||||
|
||||
{"[386DX] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
|
||||
{"[386DX] Amstrad MegaPC 386DX",ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL },
|
||||
{"[386DX] Award 386DX clone", ROM_AWARD386DX_OPTI495, "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
|
||||
{"[386DX] Compaq Deskpro 386", ROM_DESKPRO_386, "dekspro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, deskpro386_init, NULL },
|
||||
#if 0
|
||||
{"[386DX] Compaq Portable III 386",ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
|
||||
#endif
|
||||
{"[386DX] IBM PS/2 Model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 12, 1, 63, ps2_model_80_init, NULL },
|
||||
{"[386DX] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
|
||||
|
||||
{"[486] AMI 486 clone", ROM_AMI486, "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL },
|
||||
{"[486] AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL },
|
||||
{"[486] Award 486 clone", ROM_AWARD486_OPTI495, "award486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
|
||||
{"[486] DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_dtk486_init, NULL },
|
||||
{"[486] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 64, 1, 127, ps1_m2133_init, NULL },
|
||||
{"[486] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 64, 1, 127, at_r418_init, NULL },
|
||||
@@ -770,9 +777,8 @@ void at_ap53_init(void)
|
||||
pci_slot(0x13);
|
||||
pci_slot(0x14);
|
||||
i430hx_init();
|
||||
piix_init(7, 0x11, 0x12, 0x13, 0x14);
|
||||
piix3_init(7, 0x11, 0x12, 0x13, 0x14);
|
||||
fdc37c669_init();
|
||||
acerm3a_io_init();
|
||||
device_add(&intel_flash_bxt_device);
|
||||
}
|
||||
|
||||
@@ -787,16 +793,14 @@ void at_p55t2s_init(void)
|
||||
pci_slot(0x14);
|
||||
pci_slot(0x13);
|
||||
i430hx_init();
|
||||
piix_init(7, 0x12, 0x11, 0x14, 0x13);
|
||||
piix3_init(7, 0x12, 0x11, 0x14, 0x13);
|
||||
pc87306_init();
|
||||
acerm3a_io_init();
|
||||
device_add(&intel_flash_bxt_device);
|
||||
}
|
||||
|
||||
void at_acerm3a_init(void)
|
||||
{
|
||||
at_ide_init();
|
||||
memregs_init();
|
||||
powermate_memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_slot(0xc);
|
||||
@@ -806,14 +810,12 @@ void at_acerm3a_init(void)
|
||||
i430hx_init();
|
||||
piix3_init(7, 0xc, 0xd, 0xe, 0xf);
|
||||
fdc37c932fr_init();
|
||||
acerm3a_io_init();
|
||||
device_add(&intel_flash_bxb_device);
|
||||
}
|
||||
|
||||
void at_acerv35n_init(void)
|
||||
{
|
||||
at_ide_init();
|
||||
memregs_init();
|
||||
powermate_memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_slot(0x11);
|
||||
@@ -823,7 +825,6 @@ void at_acerv35n_init(void)
|
||||
i430hx_init();
|
||||
piix3_init(7, 0x11, 0x12, 0x13, 0x14);
|
||||
fdc37c932fr_init();
|
||||
acerm3a_io_init();
|
||||
device_add(&intel_flash_bxb_device);
|
||||
}
|
||||
|
||||
@@ -877,7 +878,6 @@ void at_p55tvp4_init(void)
|
||||
void at_p55va_init(void)
|
||||
{
|
||||
at_ide_init();
|
||||
memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_slot(8);
|
||||
pci_slot(9);
|
||||
|
||||
23
src/mouse.c
23
src/mouse.c
@@ -8,10 +8,11 @@
|
||||
*
|
||||
* Common driver module for MOUSE devices.
|
||||
*
|
||||
* Version: @(#)mouse.c 1.0.3 2017/06/21
|
||||
* Version: @(#)mouse.c 1.0.4 2017/07/24
|
||||
*
|
||||
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
|
||||
* Miran Grca, <mgrca8@gmail.com>
|
||||
* TheCollector1995,
|
||||
* Fred N. van Kempen, <decwiz@yahoo.com>
|
||||
* Copyright 2008-2017 Sarah Walker.
|
||||
* Copyright 2016-2017 Miran Grca.
|
||||
@@ -35,16 +36,18 @@ static mouse_t mouse_none = {
|
||||
|
||||
static mouse_t *mouse_list[] = {
|
||||
&mouse_none,
|
||||
&mouse_serial_microsoft, /* 1 Microsoft Serial Mouse */
|
||||
&mouse_ps2_2_button, /* 2 PS/2 Mouse 2-button */
|
||||
&mouse_intellimouse, /* 3 PS/2 Intellimouse 3-button */
|
||||
&mouse_bus, /* 4 Logitech Bus Mouse 2-button */
|
||||
&mouse_amstrad, /* 5 Amstrad PC System Mouse */
|
||||
&mouse_olim24, /* 6 Olivetti M24 System Mouse */
|
||||
&mouse_msystems, /* 7 Mouse Systems */
|
||||
&mouse_serial_logitech, /* 1 Logitech 3-button Serial Mouse */
|
||||
&mouse_bus, /* 1 Microsoft/Logitech Bus Mouse 2-button */
|
||||
&mouse_inport, /* 2 Microsoft InPort Mouse */
|
||||
&mouse_msystems, /* 3 Mouse Systems */
|
||||
&mouse_serial_microsoft, /* 4 Microsoft Serial Mouse */
|
||||
&mouse_serial_logitech, /* 5 Logitech 3-button Serial Mouse */
|
||||
&mouse_serial_mswheel, /* 6 Microsoft Serial Wheel Mouse */
|
||||
&mouse_ps2_2_button, /* 7 PS/2 Mouse 2-button */
|
||||
&mouse_intellimouse, /* 8 PS/2 Intellimouse 3-button */
|
||||
&mouse_amstrad, /* 9 Amstrad PC System Mouse */
|
||||
&mouse_olim24, /* 10 Olivetti M24 System Mouse */
|
||||
#if 0
|
||||
&mouse_genius, /* 8 Genius Bus Mouse */
|
||||
&mouse_genius, /* 11 Genius Bus Mouse */
|
||||
#endif
|
||||
NULL
|
||||
};
|
||||
|
||||
24
src/mouse.h
24
src/mouse.h
@@ -20,16 +20,20 @@
|
||||
# define EMU_MOUSE_H
|
||||
|
||||
|
||||
#define MOUSE_TYPE_NONE 0
|
||||
#define MOUSE_TYPE_SERIAL 1 /* Serial Mouse */
|
||||
#define MOUSE_TYPE_PS2 2 /* IBM PS/2 series Bus Mouse */
|
||||
#define MOUSE_TYPE_PS2_MS 3 /* Microsoft Intellimouse PS/2 */
|
||||
#define MOUSE_TYPE_BUS 4 /* Logitech/ATI Bus Mouse */
|
||||
#define MOUSE_TYPE_AMSTRAD 5 /* Amstrad PC system mouse */
|
||||
#define MOUSE_TYPE_OLIM24 6 /* Olivetti M24 system mouse */
|
||||
#define MOUSE_TYPE_MSYSTEMS 7 /* Mouse Systems mouse */
|
||||
#define MOUSE_TYPE_LOGITECH 8 /* Logitech Serial Mouse */
|
||||
#define MOUSE_TYPE_GENIUS 9 /* Genius Bus Mouse */
|
||||
#define MOUSE_TYPE_NONE 0
|
||||
#if 0
|
||||
#define MOUSE_TYPE_GENIUS 11 /* Genius Bus Mouse */
|
||||
#endif
|
||||
#define MOUSE_TYPE_BUS 1 /* Logitech/ATI Bus Mouse */
|
||||
#define MOUSE_TYPE_INPORT 2 /* Microsoft InPort Mouse */
|
||||
#define MOUSE_TYPE_MSYSTEMS 3 /* Mouse Systems mouse */
|
||||
#define MOUSE_TYPE_SERIAL 4 /* Serial Mouse */
|
||||
#define MOUSE_TYPE_LOGITECH 5 /* Logitech Serial Mouse */
|
||||
#define MOUSE_TYPE_MSWHEEL 6 /* Serial Wheel Mouse */
|
||||
#define MOUSE_TYPE_PS2 7 /* IBM PS/2 series Bus Mouse */
|
||||
#define MOUSE_TYPE_PS2_MS 8 /* Microsoft Intellimouse PS/2 */
|
||||
#define MOUSE_TYPE_AMSTRAD 9 /* Amstrad PC system mouse */
|
||||
#define MOUSE_TYPE_OLIM24 10 /* Olivetti M24 system mouse */
|
||||
|
||||
#define MOUSE_TYPE_MASK 0x0f
|
||||
#define MOUSE_TYPE_3BUTTON (1<<7) /* device has 3+ buttons */
|
||||
|
||||
777
src/mouse_bus.c
777
src/mouse_bus.c
@@ -32,462 +32,455 @@
|
||||
* Based on an early driver for MINIX 1.5.
|
||||
* Based on the 86Box PS/2 mouse driver as a framework.
|
||||
*
|
||||
* Version: @(#)mouse_bus.c 1.0.5 2017/06/02
|
||||
* Version: @(#)mouse_bus.c 1.0.6 2017/07/24
|
||||
*
|
||||
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
|
||||
* Copyright 1989-2017 Fred N. van Kempen.
|
||||
* TheCollector1995,
|
||||
* Copyright 1989-2017 Fred N. van Kempen, TheCollector1995.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "ibm.h"
|
||||
#include "io.h"
|
||||
#include "pic.h"
|
||||
#include "timer.h"
|
||||
#include "mouse.h"
|
||||
#include "mouse_bus.h"
|
||||
#include "plat_mouse.h"
|
||||
|
||||
#define BUS_MOUSE_IRQ 5
|
||||
#define IRQ_MASK ((1<<5) >> BUS_MOUSE_IRQ)
|
||||
|
||||
#define ENABLE_3BTN 1 /* enable 3-button mode */
|
||||
// MS Inport Bus Mouse Adapter
|
||||
#define INP_PORT_CONTROL 0x023C
|
||||
#define INP_PORT_DATA 0x023D
|
||||
#define INP_PORT_SIGNATURE 0x023E
|
||||
#define INP_PORT_CONFIG 0x023F
|
||||
|
||||
#define INP_CTRL_READ_BUTTONS 0x00
|
||||
#define INP_CTRL_READ_X 0x01
|
||||
#define INP_CTRL_READ_Y 0x02
|
||||
#define INP_CTRL_COMMAND 0x07
|
||||
#define INP_CTRL_RAISE_IRQ 0x16
|
||||
#define INP_CTRL_RESET 0x80
|
||||
|
||||
/* Register definitions for Logitech mode. */
|
||||
#define LTMOUSE_DATA 0 /* DATA register */
|
||||
#define LTMOUSE_MAGIC 1 /* signature magic register */
|
||||
# define MAGIC_BYTE1 0xa5 /* most drivers use this */
|
||||
# define MAGIC_BYTE2 0x5a /* some drivers use this */
|
||||
#define LTMOUSE_CTRL 2 /* CTRL register */
|
||||
# define CTRL_FREEZE 0x80 /* do not sample when set */
|
||||
# define CTRL_RD_Y_HI 0x60 /* plus FREEZE */
|
||||
# define CTRL_RD_Y_LO 0x40 /* plus FREEZE */
|
||||
# define CTRL_RD_X_HI 0x20 /* plus FREEZE */
|
||||
# define CTRL_RD_X_LO 0x00 /* plus FREEZE */
|
||||
# define CTRL_RD_MASK 0x60
|
||||
# define CTRL_IDIS 0x10
|
||||
# define CTRL_IENB 0x00
|
||||
# define CTRL_DFLT (CTRL_IDIS)
|
||||
#define LTMOUSE_CONFIG 3 /* CONFIG register */
|
||||
# define CONFIG_DFLT 0x91 /* 8255 controller config */
|
||||
#define INP_HOLD_COUNTER (1 << 5)
|
||||
#define INP_ENABLE_IRQ (1 << 0)
|
||||
|
||||
/* Register definitions for Microsoft mode. */
|
||||
#define MSMOUSE_CTRL 0 /* CTRL register */
|
||||
# define MSCTRL_RESET 0x80
|
||||
# define MSCTRL_MODE 0x07
|
||||
# define MSCTRL_RD_Y 0x02
|
||||
# define MSCTRL_RD_X 0x01
|
||||
# define MSCTRL_RD_BUT 0x00
|
||||
#define MSMOUSE_DATA 1 /* DATA register */
|
||||
# define MSDATA_BASE 0x10
|
||||
# define MSDATA_IRQ 0x01
|
||||
#define MSMOUSE_MAGIC 2 /* MAGIC register */
|
||||
# define MAGIC_MSBYTE1 0xde /* indicates MS InPort */
|
||||
# define MAGIC_MSBYTE2 0xad
|
||||
#define MSMOUSE_CONFIG 3 /* CONFIG register */
|
||||
// MS/Logictech Standard Bus Mouse Adapter
|
||||
#define BUSM_PORT_DATA 0x023C
|
||||
#define BUSM_PORT_SIGNATURE 0x023D
|
||||
#define BUSM_PORT_CONTROL 0x023E
|
||||
#define BUSM_PORT_CONFIG 0x023F
|
||||
|
||||
#define HOLD_COUNTER (1 << 7)
|
||||
#define READ_X (0 << 6)
|
||||
#define READ_Y (1 << 6)
|
||||
#define READ_LOW (0 << 5)
|
||||
#define READ_HIGH (1 << 5)
|
||||
#define DISABLE_IRQ (1 << 4)
|
||||
|
||||
#define READ_X_LOW (READ_X | READ_LOW)
|
||||
#define READ_X_HIGH (READ_X | READ_HIGH)
|
||||
#define READ_Y_LOW (READ_Y | READ_LOW)
|
||||
#define READ_Y_HIGH (READ_Y | READ_HIGH)
|
||||
|
||||
|
||||
/* Our mouse device. */
|
||||
typedef struct {
|
||||
uint16_t port; /* I/O port range start */
|
||||
uint16_t portlen; /* length of I/O port range */
|
||||
int8_t irq; /* IRQ channel to use */
|
||||
uint8_t flags; /* device flags */
|
||||
|
||||
uint8_t r_magic; /* MAGIC register */
|
||||
uint8_t r_ctrl; /* CONTROL register (WR) */
|
||||
uint8_t r_intr; /* INTSTAT register (RO) */
|
||||
uint8_t r_conf; /* CONFIG register */
|
||||
|
||||
int8_t x, y; /* current mouse status */
|
||||
uint8_t but;
|
||||
typedef struct mouse_bus_t
|
||||
{
|
||||
int irq;
|
||||
int timer_index;
|
||||
int x_delay;
|
||||
int y_delay;
|
||||
uint8_t mouse_buttons;
|
||||
uint8_t mouse_buttons_last;
|
||||
uint8_t x, y, but;
|
||||
uint8_t command_val;
|
||||
uint8_t control_val;
|
||||
uint8_t config_val;
|
||||
uint8_t sig_val;
|
||||
uint16_t toggle_counter;
|
||||
int interrupts;
|
||||
int is_inport;
|
||||
} mouse_bus_t;
|
||||
#define MOUSE_ENABLED 0x80 /* device is enabled for use */
|
||||
#define MOUSE_LOGITECH 0x40 /* running in Logitech mode */
|
||||
#define MOUSE_MICROSOFT 0x20 /* running in Microsoft mode */
|
||||
|
||||
|
||||
/* Handle a WRITE to a Microsoft-mode register. */
|
||||
static void
|
||||
ms_write(mouse_bus_t *ms, uint16_t port, uint8_t val)
|
||||
{
|
||||
#if 0
|
||||
pclog("BUSMOUSE: ms_write(%d,%02x)\n", port, val);
|
||||
#endif
|
||||
|
||||
switch (port) {
|
||||
case MSMOUSE_CTRL: /* [00] control register */
|
||||
if (val & MSCTRL_RESET) {
|
||||
/* Reset the interface. */
|
||||
ms->r_magic = MAGIC_MSBYTE1;
|
||||
ms->r_conf = 0x00;
|
||||
}
|
||||
|
||||
/* Save new register value. */
|
||||
ms->r_ctrl = val;
|
||||
break;
|
||||
|
||||
case MSMOUSE_DATA: /* [01] data register */
|
||||
if (ms->r_ctrl == MSCTRL_MODE) {
|
||||
ms->r_conf = val;
|
||||
}
|
||||
break;
|
||||
|
||||
case MSMOUSE_MAGIC: /* [02] magic data register */
|
||||
break;
|
||||
|
||||
case MSMOUSE_CONFIG: /* [03] config register */
|
||||
ms->r_conf = val;
|
||||
ms->flags &= ~MOUSE_MICROSOFT;
|
||||
ms->flags |= MOUSE_LOGITECH;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Handle a WRITE to a LOGITECH-mode register. */
|
||||
static void
|
||||
lt_write(mouse_bus_t *ms, uint16_t port, uint8_t val)
|
||||
{
|
||||
uint8_t b = (ms->r_ctrl ^ val);
|
||||
|
||||
#if 0
|
||||
pclog("BUSMOUSE: lt_write(%d,%02x)\n", port, val);
|
||||
#endif
|
||||
|
||||
switch (port) {
|
||||
case LTMOUSE_DATA: /* [00] data register */
|
||||
break;
|
||||
|
||||
case LTMOUSE_MAGIC: /* [01] magic data register */
|
||||
if (val == MAGIC_BYTE1 || val == MAGIC_BYTE2) {
|
||||
ms->flags |= MOUSE_LOGITECH;
|
||||
ms->r_magic = val;
|
||||
}
|
||||
break;
|
||||
|
||||
case LTMOUSE_CTRL: /* [02] control register */
|
||||
if (b & CTRL_FREEZE) {
|
||||
/* Hold the sampling while we do something. */
|
||||
if (! (val & CTRL_FREEZE)) {
|
||||
/* Reset current state. */
|
||||
ms->x = ms->y = 0;
|
||||
if (ms->but)
|
||||
/* One more POLL for button-release. */
|
||||
ms->but = 0x80;
|
||||
}
|
||||
}
|
||||
|
||||
if (b & CTRL_IDIS) {
|
||||
/* Disable or enable interrupts. */
|
||||
/* (we don't do anything for that here..) */
|
||||
}
|
||||
|
||||
/* Save new register value. */
|
||||
ms->r_ctrl = val;
|
||||
break;
|
||||
|
||||
case LTMOUSE_CONFIG: /* [03] config register */
|
||||
ms->r_conf = val;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Handle a WRITE operation to one of our registers. */
|
||||
static void
|
||||
bm_write(uint16_t port, uint8_t val, void *priv)
|
||||
static void busmouse_write(uint16_t port, uint8_t val, void *priv)
|
||||
{
|
||||
mouse_bus_t *ms = (mouse_bus_t *)priv;
|
||||
mouse_bus_t *busmouse = (mouse_bus_t *)priv;
|
||||
|
||||
if (ms->flags & MOUSE_LOGITECH)
|
||||
lt_write(ms, port - ms->port, val);
|
||||
|
||||
if (ms->flags & MOUSE_MICROSOFT)
|
||||
ms_write(ms, port - ms->port, val);
|
||||
}
|
||||
|
||||
|
||||
/* Handle a READ from a Microsoft-mode register. */
|
||||
static uint8_t
|
||||
ms_read(mouse_bus_t *ms, uint16_t port)
|
||||
{
|
||||
uint8_t r = 0xff;
|
||||
|
||||
switch (port) {
|
||||
case MSMOUSE_CTRL: /* [00] control register */
|
||||
r = ms->r_ctrl;
|
||||
switch (port)
|
||||
{
|
||||
case BUSM_PORT_CONTROL:
|
||||
busmouse->control_val = val | 0x0f;
|
||||
busmouse->interrupts = (val & DISABLE_IRQ) == 0;
|
||||
picintc(1 << busmouse->irq);
|
||||
break;
|
||||
|
||||
case MSMOUSE_DATA: /* [01] data register */
|
||||
|
||||
case BUSM_PORT_CONFIG:
|
||||
busmouse->config_val = val;
|
||||
break;
|
||||
|
||||
case MSMOUSE_MAGIC: /* [02] magic data register */
|
||||
/*
|
||||
* Drivers for the InPort controllers usually start
|
||||
* by reading this register. If they find 0xDE here,
|
||||
* they will continue their probe, otherwise no go.
|
||||
*/
|
||||
r = ms->r_magic;
|
||||
|
||||
/* For the InPort, switch magic bytes. */
|
||||
if (ms->r_magic == MAGIC_MSBYTE1)
|
||||
ms->r_magic = MAGIC_MSBYTE2;
|
||||
else
|
||||
ms->r_magic = MAGIC_MSBYTE1;
|
||||
|
||||
case BUSM_PORT_SIGNATURE:
|
||||
busmouse->sig_val = val;
|
||||
break;
|
||||
|
||||
case MSMOUSE_CONFIG: /* [03] config register */
|
||||
r = ms->r_conf;
|
||||
|
||||
case BUSM_PORT_DATA:
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
#if 0
|
||||
pclog("BUSMOUSE: ms_read(%d): %02x\n", port, r);
|
||||
#endif
|
||||
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
/* Handle a READ from a LOGITECH-mode register. */
|
||||
static uint8_t
|
||||
lt_read(mouse_bus_t *ms, uint16_t port)
|
||||
{
|
||||
uint8_t r = 0xff;
|
||||
|
||||
switch (port) {
|
||||
case LTMOUSE_DATA: /* [00] data register */
|
||||
if (! (ms->r_ctrl & CTRL_FREEZE)) {
|
||||
r = 0x00;
|
||||
} else switch(ms->r_ctrl & CTRL_RD_MASK) {
|
||||
case CTRL_RD_X_LO: /* X, low bits */
|
||||
/*
|
||||
* Some drivers expect the buttons to
|
||||
* be in this byte. Others want it in
|
||||
* the Y-LO byte. --FvK
|
||||
*/
|
||||
r = 0x07;
|
||||
if (ms->but & 0x01) /*LEFT*/
|
||||
r &= ~0x04;
|
||||
if (ms->but & 0x02) /*RIGHT*/
|
||||
r &= ~0x01;
|
||||
#if ENABLE_3BTN
|
||||
if (ms->but & 0x04) /*MIDDLE*/
|
||||
r &= ~0x02;
|
||||
#endif
|
||||
r <<= 5;
|
||||
r |= (ms->x & 0x0f);
|
||||
break;
|
||||
|
||||
case CTRL_RD_X_HI: /* X, high bits */
|
||||
r = (ms->x >> 4) & 0x0f;
|
||||
break;
|
||||
|
||||
case CTRL_RD_Y_LO: /* Y, low bits */
|
||||
r = (ms->y & 0x0f);
|
||||
break;
|
||||
|
||||
case CTRL_RD_Y_HI: /* Y, high bits */
|
||||
/*
|
||||
* Some drivers expect the buttons to
|
||||
* be in this byte. Others want it in
|
||||
* the X-LO byte. --FvK
|
||||
*/
|
||||
r = 0x07;
|
||||
if (ms->but & 0x01) /*LEFT*/
|
||||
r &= ~0x04;
|
||||
if (ms->but & 0x02) /*RIGHT*/
|
||||
r &= ~0x01;
|
||||
#if ENABLE_3BTN
|
||||
if (ms->but & 0x04) /*MIDDLE*/
|
||||
r &= ~0x02;
|
||||
#endif
|
||||
r <<= 5;
|
||||
r |= (ms->y >> 4) & 0x0f;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case LTMOUSE_MAGIC: /* [01] magic data register */
|
||||
/*
|
||||
* Logitech drivers start out by blasting their magic
|
||||
* value (0xA5) into this register, and then read it
|
||||
* back to see if that worked. If it did (and we do
|
||||
* support this) the controller is assumed to be a
|
||||
* Logitech-protocol one, and not InPort.
|
||||
*/
|
||||
r = ms->r_magic;
|
||||
break;
|
||||
|
||||
case LTMOUSE_CTRL: /* [02] control register */
|
||||
/*
|
||||
* This is the weird stuff mentioned in the file header
|
||||
* above. Microsoft's "mouse.exe" does some whacky stuff
|
||||
* to extract the configured IRQ channel from the board.
|
||||
*
|
||||
* First, it reads the current value, and then re-reads
|
||||
* it another 10,000 (yes, really) times. It keeps track
|
||||
* of whether or not the data has changed, most likely
|
||||
* to de-bounce reading of a DIP switch for example. This
|
||||
* first value is assumed to be the 2's complement of the
|
||||
* actual IRQ value.
|
||||
* Next, it does this a second time, but now with the
|
||||
* IDIS bit clear (so, interrupts enabled), which is
|
||||
* our cue to return the regular (not complemented) value
|
||||
* to them.
|
||||
*
|
||||
* Since we have to fake the initial value and the settling
|
||||
* of the data a bit later on, we first return a bunch of
|
||||
* invalid ("random") data, and then the real value.
|
||||
*
|
||||
* Yes, this is weird. --FvK
|
||||
*/
|
||||
if (ms->r_intr++ < 250)
|
||||
/* Still settling, return invalid data. */
|
||||
r = (ms->r_ctrl&CTRL_IDIS)?0xff:0x00;
|
||||
else {
|
||||
/* OK, all good, return correct data. */
|
||||
r = (ms->r_ctrl&CTRL_IDIS)?-ms->irq:ms->irq;
|
||||
ms->r_intr = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case LTMOUSE_CONFIG: /* [03] config register */
|
||||
r = ms->r_conf;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
#if 0
|
||||
pclog("BUSMOUSE: lt_read(%d): %02x\n", port, r);
|
||||
#endif
|
||||
|
||||
return(r);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Handle a READ operation from one of our registers. */
|
||||
static uint8_t
|
||||
bm_read(uint16_t port, void *priv)
|
||||
static uint8_t busmouse_read(uint16_t port, void *priv)
|
||||
{
|
||||
mouse_bus_t *ms = (mouse_bus_t *)priv;
|
||||
uint8_t r = 0xff;
|
||||
|
||||
if (ms->flags & MOUSE_LOGITECH)
|
||||
r = lt_read(ms, port - ms->port);
|
||||
|
||||
if (ms->flags & MOUSE_MICROSOFT)
|
||||
r = ms_read(ms, port - ms->port);
|
||||
|
||||
mouse_bus_t *busmouse = (mouse_bus_t *)priv;
|
||||
uint8_t r = 0;
|
||||
|
||||
switch (port)
|
||||
{
|
||||
case BUSM_PORT_CONTROL:
|
||||
r = busmouse->control_val;
|
||||
/* This is to allow the driver to see which IRQ the card has "jumpered"
|
||||
only happens if IRQ's are enabled */
|
||||
busmouse->control_val |= 0x0f;
|
||||
|
||||
busmouse->control_val &= ~IRQ_MASK;
|
||||
busmouse->toggle_counter = (busmouse->toggle_counter + 1) & 0x7ff;
|
||||
break;
|
||||
|
||||
case BUSM_PORT_DATA:
|
||||
switch (busmouse->control_val & 0x60)
|
||||
{
|
||||
case READ_X_LOW:
|
||||
r = busmouse->x & 0x0f;
|
||||
break;
|
||||
|
||||
case READ_X_HIGH:
|
||||
r = (busmouse->x >> 4) & 0x0f;
|
||||
break;
|
||||
|
||||
case READ_Y_LOW:
|
||||
r = busmouse->y & 0x0f;
|
||||
break;
|
||||
|
||||
case READ_Y_HIGH:
|
||||
r = ((busmouse->but ^ 7) << 5) | ((busmouse->y >> 4) & 0x0f);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case BUSM_PORT_CONFIG:
|
||||
r = busmouse->config_val;
|
||||
break;
|
||||
|
||||
case BUSM_PORT_SIGNATURE:
|
||||
r = busmouse->sig_val;
|
||||
break;
|
||||
}
|
||||
|
||||
return(r);
|
||||
}
|
||||
|
||||
static void inport_write(uint16_t port, uint8_t val, void *priv)
|
||||
{
|
||||
mouse_bus_t *inport = (mouse_bus_t *)priv;
|
||||
|
||||
switch (port)
|
||||
{
|
||||
case INP_PORT_CONTROL:
|
||||
switch (val)
|
||||
{
|
||||
case INP_CTRL_RESET:
|
||||
inport->control_val = 0;
|
||||
inport->command_val = 0;
|
||||
break;
|
||||
|
||||
case INP_CTRL_COMMAND:
|
||||
case INP_CTRL_READ_BUTTONS:
|
||||
case INP_CTRL_READ_X:
|
||||
case INP_CTRL_READ_Y:
|
||||
inport->command_val = val;
|
||||
break;
|
||||
|
||||
case 0x87:
|
||||
inport->control_val = 0;
|
||||
inport->command_val = 0x07;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case INP_PORT_DATA:
|
||||
picintc(1 << inport->irq);
|
||||
if (val == INP_CTRL_RAISE_IRQ)
|
||||
{
|
||||
picint(1 << inport->irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (inport->command_val)
|
||||
{
|
||||
case INP_CTRL_COMMAND:
|
||||
inport->control_val = val;
|
||||
inport->interrupts = (val & INP_ENABLE_IRQ) > 0;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case INP_PORT_SIGNATURE:
|
||||
case INP_PORT_CONFIG:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t inport_read(uint16_t port, void *priv)
|
||||
{
|
||||
mouse_bus_t *inport = (mouse_bus_t *)priv;
|
||||
uint8_t r = 0;
|
||||
|
||||
switch (port)
|
||||
{
|
||||
case INP_PORT_CONTROL:
|
||||
r = inport->control_val;
|
||||
break;
|
||||
|
||||
case INP_PORT_DATA:
|
||||
switch (inport->command_val)
|
||||
{
|
||||
case INP_CTRL_READ_BUTTONS:
|
||||
r = inport->but;
|
||||
r |= 0x40;
|
||||
break;
|
||||
|
||||
case INP_CTRL_READ_X:
|
||||
r = inport->x;
|
||||
break;
|
||||
|
||||
case INP_CTRL_READ_Y:
|
||||
r = inport->y;
|
||||
break;
|
||||
|
||||
case INP_CTRL_COMMAND:
|
||||
r = inport->control_val;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case INP_PORT_SIGNATURE:
|
||||
if (!inport->toggle_counter)
|
||||
{
|
||||
r = 0xde;
|
||||
}
|
||||
else
|
||||
{
|
||||
r = 0x12;
|
||||
}
|
||||
inport->toggle_counter ^= 1;
|
||||
break;
|
||||
|
||||
case INP_PORT_CONFIG:
|
||||
break;
|
||||
}
|
||||
|
||||
return(r);
|
||||
}
|
||||
|
||||
void busmouse_update_mouse_data(void *priv)
|
||||
{
|
||||
mouse_bus_t *busmouse = (mouse_bus_t *)priv;
|
||||
|
||||
int delta_x, delta_y;
|
||||
int hold;
|
||||
|
||||
if (busmouse->x_delay > 127) {
|
||||
delta_x = 127;
|
||||
busmouse->x_delay -= 127;
|
||||
} else if (busmouse->x_delay < -128) {
|
||||
delta_x = -128;
|
||||
busmouse->x_delay += 128;
|
||||
} else {
|
||||
delta_x = busmouse->x_delay;
|
||||
busmouse->x_delay = 0;
|
||||
}
|
||||
if (busmouse->y_delay > 127) {
|
||||
delta_y = 127;
|
||||
busmouse->y_delay -= 127;
|
||||
} else if (busmouse->y_delay < -128) {
|
||||
delta_y = -128;
|
||||
busmouse->y_delay += 128;
|
||||
} else {
|
||||
delta_y = busmouse->y_delay;
|
||||
busmouse->y_delay = 0;
|
||||
}
|
||||
|
||||
if (busmouse->is_inport) {
|
||||
hold = (busmouse->control_val & INP_HOLD_COUNTER) > 0;
|
||||
} else {
|
||||
hold = (busmouse->control_val & HOLD_COUNTER) > 0;
|
||||
}
|
||||
if (!hold) {
|
||||
busmouse->x = (uint8_t) delta_x;
|
||||
busmouse->y = (uint8_t) delta_y;
|
||||
busmouse->but = busmouse->mouse_buttons;
|
||||
}
|
||||
}
|
||||
|
||||
/* Called at 30hz */
|
||||
void busmouse_timer_handler(void *priv)
|
||||
{
|
||||
mouse_bus_t *busmouse = (mouse_bus_t *)priv;
|
||||
|
||||
busmouse->timer_index += ((1000000.0 / 30.0) * TIMER_USEC);
|
||||
|
||||
/* The controller updates the data on every interrupt
|
||||
We just don't copy it to the current_X if the 'hold' bit is set */
|
||||
busmouse_update_mouse_data(busmouse);
|
||||
}
|
||||
|
||||
/* The emulator calls us with an update on the host mouse device. */
|
||||
static uint8_t
|
||||
bm_poll(int x, int y, int z, int b, void *priv)
|
||||
static uint8_t busmouse_poll(int x, int y, int z, int b, void *priv)
|
||||
{
|
||||
mouse_bus_t *ms = (mouse_bus_t *)priv;
|
||||
mouse_bus_t *busmouse = (mouse_bus_t *)priv;
|
||||
|
||||
/* Return early if nothing to do. */
|
||||
if (!x && !y && !z && (ms->but == b)) return(1);
|
||||
if (!x && !y && !z && (busmouse->mouse_buttons == b)) return(1);
|
||||
|
||||
/* If we are not interested, return. */
|
||||
if (!(ms->flags & MOUSE_ENABLED) ||
|
||||
(ms->r_ctrl & CTRL_FREEZE)) return(0);
|
||||
|
||||
#if 0
|
||||
#if 1
|
||||
pclog("BUSMOUSE: poll(%d,%d,%d, %02x)\n", x, y, z, b);
|
||||
#endif
|
||||
|
||||
// scale down the motion
|
||||
if ((x < -1) || (x > 1))
|
||||
x /= 2;
|
||||
if ((y < -1) || (y > 1))
|
||||
y /= 2;
|
||||
|
||||
if (x > 127) x =127;
|
||||
if (y > 127) y =127;
|
||||
if (x < -128) x = -128;
|
||||
if (y < -128) y = -128;
|
||||
|
||||
busmouse->x_delay += x;
|
||||
busmouse->y_delay += y;
|
||||
|
||||
busmouse->mouse_buttons = (uint8_t)(((b & 1) << 2) |
|
||||
((b & 4) >> 1) | ((b & 2) >> 1));
|
||||
|
||||
if (busmouse->is_inport)
|
||||
{
|
||||
if ((busmouse->mouse_buttons & (1<<2)) ||
|
||||
((busmouse->mouse_buttons_last & (1<<2)) && !(busmouse->mouse_buttons & (1<<2))))
|
||||
busmouse->mouse_buttons |= (1<<5);
|
||||
if ((busmouse->mouse_buttons & (1<<1)) ||
|
||||
((busmouse->mouse_buttons_last & (1<<1)) && !(busmouse->mouse_buttons & (1<<1))))
|
||||
busmouse->mouse_buttons |= (1<<4);
|
||||
if ((busmouse->mouse_buttons & (1<<0)) ||
|
||||
((busmouse->mouse_buttons_last & (1<<0)) && !(busmouse->mouse_buttons & (1<<0))))
|
||||
busmouse->mouse_buttons |= (1<<3);
|
||||
busmouse->mouse_buttons_last = busmouse->mouse_buttons;
|
||||
}
|
||||
|
||||
/* Add the delta to our state. */
|
||||
x += ms->x;
|
||||
if (x > 127)
|
||||
x = 127;
|
||||
if (x < -128)
|
||||
x = -128;
|
||||
ms->x = (int8_t)x;
|
||||
|
||||
y += ms->y;
|
||||
if (y > 127)
|
||||
y = 127;
|
||||
if (y < -128)
|
||||
y = -128;
|
||||
ms->y = (int8_t)y;
|
||||
|
||||
ms->but = b;
|
||||
|
||||
/* All set, generate an interrupt. */
|
||||
if (! (ms->r_ctrl & CTRL_IDIS))
|
||||
picint(1 << ms->irq);
|
||||
|
||||
/* if interrupts are on, fire the interrupt */
|
||||
if (busmouse->interrupts)
|
||||
{
|
||||
picint(1 << busmouse->irq);
|
||||
}
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
/* Release all resources held by the device. */
|
||||
static void
|
||||
bm_close(void *priv)
|
||||
static void busmouse_close(void *priv)
|
||||
{
|
||||
mouse_bus_t *ms = (mouse_bus_t *)priv;
|
||||
mouse_bus_t *busmouse = (mouse_bus_t *)priv;
|
||||
|
||||
/* Release our I/O range. */
|
||||
io_removehandler(ms->port, ms->portlen,
|
||||
bm_read, NULL, NULL, bm_write, NULL, NULL, ms);
|
||||
io_removehandler(0x023C, 0x0004, busmouse_read, NULL, NULL, busmouse_write, NULL, NULL, busmouse);
|
||||
|
||||
free(ms);
|
||||
free(busmouse);
|
||||
}
|
||||
|
||||
|
||||
/* Initialize the device for use by the user. */
|
||||
static void *
|
||||
bm_init(void)
|
||||
static void *busmouse_init(void)
|
||||
{
|
||||
mouse_bus_t *ms;
|
||||
|
||||
ms = (mouse_bus_t *)malloc(sizeof(mouse_bus_t));
|
||||
memset(ms, 0x00, sizeof(mouse_bus_t));
|
||||
ms->port = BUSMOUSE_PORT;
|
||||
ms->portlen = BUSMOUSE_PORTLEN;
|
||||
#if BUSMOUSE_IRQ
|
||||
ms->irq = BUSMOUSE_IRQ;
|
||||
#else
|
||||
ms->irq = -1;
|
||||
#endif
|
||||
|
||||
pclog("Logitech/Microsoft Bus Mouse, I/O=%04x, IRQ=%d\n",
|
||||
ms->port, ms->irq);
|
||||
mouse_bus_t *busmouse;
|
||||
|
||||
busmouse = (mouse_bus_t *)malloc(sizeof(mouse_bus_t));
|
||||
memset(busmouse, 0x00, sizeof(mouse_bus_t));
|
||||
|
||||
busmouse->is_inport = 0;
|
||||
busmouse->irq = BUS_MOUSE_IRQ;
|
||||
|
||||
/* Initialize registers. */
|
||||
ms->r_magic = MAGIC_MSBYTE1;
|
||||
ms->r_conf = CONFIG_DFLT;
|
||||
ms->r_ctrl = CTRL_DFLT;
|
||||
|
||||
/* Initialize with Microsoft-mode being default. */
|
||||
ms->flags = (MOUSE_ENABLED | MOUSE_MICROSOFT);
|
||||
|
||||
busmouse->control_val = 0x1f; /* The control port value */
|
||||
busmouse->config_val = 0x0e; /* The config port value */
|
||||
|
||||
/* Common. */
|
||||
busmouse->command_val = 0;
|
||||
busmouse->toggle_counter = 0;
|
||||
busmouse->interrupts = 0;
|
||||
|
||||
/* Request an I/O range. */
|
||||
io_sethandler(ms->port, ms->portlen,
|
||||
bm_read, NULL, NULL, bm_write, NULL, NULL, ms);
|
||||
|
||||
io_sethandler(0x023C, 0x0004, busmouse_read, NULL, NULL, busmouse_write, NULL, NULL, busmouse);
|
||||
timer_add(busmouse_timer_handler, &busmouse->timer_index, TIMER_ALWAYS_ENABLED, busmouse);
|
||||
|
||||
/* Return our private data to the I/O layer. */
|
||||
return(ms);
|
||||
return(busmouse);
|
||||
}
|
||||
|
||||
/* Initialize the device for use by the user. */
|
||||
static void *inport_init(void)
|
||||
{
|
||||
mouse_bus_t *inport;
|
||||
|
||||
inport = (mouse_bus_t *)malloc(sizeof(mouse_bus_t));
|
||||
memset(inport, 0x00, sizeof(mouse_bus_t));
|
||||
|
||||
inport->is_inport = 1;
|
||||
inport->irq = BUS_MOUSE_IRQ;
|
||||
|
||||
/* Initialize registers. */
|
||||
inport->control_val = 0x00; /* The control port value */
|
||||
inport->config_val = 0x00; /* The config port value */
|
||||
|
||||
/* Common. */
|
||||
inport->command_val = 0;
|
||||
inport->toggle_counter = 0;
|
||||
inport->interrupts = 0;
|
||||
|
||||
/* Request an I/O range. */
|
||||
io_sethandler(0x023C, 0x0004, inport_read, NULL, NULL, inport_write, NULL, NULL, inport);
|
||||
timer_add(busmouse_timer_handler, &inport->timer_index, TIMER_ALWAYS_ENABLED, inport);
|
||||
|
||||
/* Return our private data to the I/O layer. */
|
||||
return(inport);
|
||||
}
|
||||
|
||||
|
||||
mouse_t mouse_bus = {
|
||||
mouse_t mouse_bus =
|
||||
{
|
||||
"Bus Mouse",
|
||||
"msbus",
|
||||
MOUSE_TYPE_BUS,
|
||||
bm_init,
|
||||
bm_close,
|
||||
bm_poll
|
||||
busmouse_init,
|
||||
busmouse_close,
|
||||
busmouse_poll
|
||||
};
|
||||
|
||||
mouse_t mouse_inport =
|
||||
{
|
||||
"InPort Mouse",
|
||||
"inport",
|
||||
MOUSE_TYPE_INPORT,
|
||||
inport_init,
|
||||
busmouse_close,
|
||||
busmouse_poll
|
||||
};
|
||||
|
||||
@@ -23,12 +23,8 @@
|
||||
# define MOUSE_BUS_H
|
||||
|
||||
|
||||
#define BUSMOUSE_PORT 0x023c
|
||||
#define BUSMOUSE_PORTLEN 4
|
||||
#define BUSMOUSE_IRQ 5
|
||||
|
||||
|
||||
extern mouse_t mouse_bus;
|
||||
extern mouse_t mouse_inport;
|
||||
|
||||
|
||||
#endif /*MOUSE_BUS_H*/
|
||||
|
||||
@@ -273,9 +273,18 @@ uint8_t mouse_serial_poll(int x, int y, int z, int b, void *p)
|
||||
serial_write_fifo(mouse->serial, mousedat[0]);
|
||||
serial_write_fifo(mouse->serial, mousedat[1]);
|
||||
serial_write_fifo(mouse->serial, mousedat[2]);
|
||||
if ((b&0x04) && mouse->type)
|
||||
if (mouse->type == 2)
|
||||
{
|
||||
serial_write_fifo(mouse->serial, 0x20);
|
||||
if (b&0x04)
|
||||
{
|
||||
serial_write_fifo(mouse->serial, 0x20);
|
||||
}
|
||||
}
|
||||
else if (mouse->type == 3)
|
||||
{
|
||||
mousedat[3] = z & 0xf;
|
||||
if (b&4) mousedat[3] |= 0x10;
|
||||
serial_write_fifo(mouse->serial, mousedat[3]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -286,10 +295,8 @@ uint8_t mouse_serial_msystems_poll(int x, int y, int z, int b, void *p)
|
||||
{
|
||||
mouse_serial_t *mouse = (mouse_serial_t *)p;
|
||||
SERIAL *serial = mouse->serial;
|
||||
uint8_t mousedat[4];
|
||||
uint8_t mousedat[5];
|
||||
|
||||
if (!(serial->ier & 1))
|
||||
return 0xff;
|
||||
if (!x && !y && b == mouse->oldb)
|
||||
return 0xff;
|
||||
|
||||
@@ -339,13 +346,23 @@ void mousecallback(void *p)
|
||||
if (mouse->mousepos == -1)
|
||||
{
|
||||
mouse->mousepos = 0;
|
||||
if (mouse->type < 2)
|
||||
switch(mouse->type)
|
||||
{
|
||||
serial_write_fifo(mouse->serial, 'M');
|
||||
if (mouse->type == 1)
|
||||
{
|
||||
case 0:
|
||||
serial_write_fifo(mouse->serial, 'H');
|
||||
break;
|
||||
case 1:
|
||||
default:
|
||||
serial_write_fifo(mouse->serial, 'M');
|
||||
break;
|
||||
case 2:
|
||||
serial_write_fifo(mouse->serial, 'M');
|
||||
serial_write_fifo(mouse->serial, '3');
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
serial_write_fifo(mouse->serial, 'M');
|
||||
serial_write_fifo(mouse->serial, 'Z');
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -365,21 +382,26 @@ void *mouse_serial_common_init(int type)
|
||||
return mouse;
|
||||
}
|
||||
|
||||
void *mouse_serial_init()
|
||||
void *mouse_serial_msystems_init()
|
||||
{
|
||||
return mouse_serial_common_init(0);
|
||||
}
|
||||
|
||||
void *mouse_serial_logitech_init()
|
||||
void *mouse_serial_init()
|
||||
{
|
||||
return mouse_serial_common_init(1);
|
||||
}
|
||||
|
||||
void *mouse_serial_msystems_init()
|
||||
void *mouse_serial_logitech_init()
|
||||
{
|
||||
return mouse_serial_common_init(2);
|
||||
}
|
||||
|
||||
void *mouse_serial_mswheel_init()
|
||||
{
|
||||
return mouse_serial_common_init(3);
|
||||
}
|
||||
|
||||
void mouse_serial_close(void *p)
|
||||
{
|
||||
mouse_serial_t *mouse = (mouse_serial_t *)p;
|
||||
@@ -389,6 +411,16 @@ void mouse_serial_close(void *p)
|
||||
serial1.rcr_callback = NULL;
|
||||
}
|
||||
|
||||
mouse_t mouse_msystems =
|
||||
{
|
||||
"Mouse Systems Mouse (serial)",
|
||||
"mssystems",
|
||||
MOUSE_TYPE_MSYSTEMS | MOUSE_TYPE_3BUTTON,
|
||||
mouse_serial_msystems_init,
|
||||
mouse_serial_close,
|
||||
mouse_serial_msystems_poll
|
||||
};
|
||||
|
||||
mouse_t mouse_serial_microsoft =
|
||||
{
|
||||
"Microsoft 2-button mouse (serial)",
|
||||
@@ -403,20 +435,20 @@ mouse_t mouse_serial_logitech =
|
||||
{
|
||||
"Logitech 3-button mouse (serial)",
|
||||
"lserial",
|
||||
MOUSE_TYPE_SERIAL | MOUSE_TYPE_3BUTTON,
|
||||
MOUSE_TYPE_LOGITECH | MOUSE_TYPE_3BUTTON,
|
||||
mouse_serial_logitech_init,
|
||||
mouse_serial_close,
|
||||
mouse_serial_poll
|
||||
};
|
||||
|
||||
mouse_t mouse_msystems =
|
||||
mouse_t mouse_serial_mswheel =
|
||||
{
|
||||
"Mouse Systems Mouse (serial)",
|
||||
"Microsoft wheel mouse (serial)",
|
||||
"mssystems",
|
||||
MOUSE_TYPE_MSYSTEMS,
|
||||
mouse_serial_msystems_init,
|
||||
MOUSE_TYPE_MSWHEEL | MOUSE_TYPE_3BUTTON,
|
||||
mouse_serial_mswheel_init,
|
||||
mouse_serial_close,
|
||||
mouse_serial_msystems_poll
|
||||
mouse_serial_poll
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -21,9 +21,10 @@
|
||||
#define SERMOUSE_PORT 1 /* attach to Serial1 */
|
||||
|
||||
|
||||
extern mouse_t mouse_msystems;
|
||||
extern mouse_t mouse_serial_microsoft;
|
||||
extern mouse_t mouse_serial_logitech;
|
||||
extern mouse_t mouse_msystems;
|
||||
extern mouse_t mouse_serial_mswheel;
|
||||
|
||||
|
||||
#endif /*MOUSE_SERIAL_H*/
|
||||
|
||||
Reference in New Issue
Block a user