From 138059ff45a4b9ed78113a7b73a96b81b51504a6 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Fri, 5 Jul 2024 16:28:01 +0600 Subject: [PATCH 01/36] libsndfile support --- src/cdrom/CMakeLists.txt | 8 +++ src/cdrom/cdrom_image_backend.c | 95 +++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/src/cdrom/CMakeLists.txt b/src/cdrom/CMakeLists.txt index d3b38095e..f2acce4e2 100644 --- a/src/cdrom/CMakeLists.txt +++ b/src/cdrom/CMakeLists.txt @@ -13,4 +13,12 @@ # Copyright 2020-2021 David Hrdlička. # +find_package(PkgConfig REQUIRED) + +pkg_check_modules(SNDFILE REQUIRED IMPORTED_TARGET sndfile) + add_library(cdrom OBJECT cdrom.c cdrom_image_backend.c cdrom_image_viso.c cdrom_image.c cdrom_ioctl.c cdrom_mitsumi.c) +target_link_libraries(86Box PkgConfig::SNDFILE) +if (WIN32) + target_link_libraries(86Box -static ${SNDFILE_STATIC_LIBRARIES}) +endif() diff --git a/src/cdrom/cdrom_image_backend.c b/src/cdrom/cdrom_image_backend.c index 9ce78e5b4..e7373a319 100644 --- a/src/cdrom/cdrom_image_backend.c +++ b/src/cdrom/cdrom_image_backend.c @@ -40,6 +40,8 @@ #include <86box/plat.h> #include <86box/cdrom_image_backend.h> +#include + #define CDROM_BCD(x) (((x) % 10) | (((x) / 10) << 4)) #define MAX_LINE_LENGTH 512 @@ -66,6 +68,96 @@ cdrom_image_backend_log(const char *fmt, ...) # define cdrom_image_backend_log(fmt, ...) #endif +typedef struct audio_file { + SNDFILE *file; + SF_INFO info; +} audio_file; + +/* Audio file functions */ +static int +audio_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count) +{ + track_file_t *tf = (track_file_t*)priv; + audio_file *audio = (audio_file*)tf->priv; + uint64_t samples_seek = seek / 4; + uint64_t samples_count = count / 4; + + if ((seek & 3) || (count & 3)) { + pclog("Reading on non-4-aligned boundaries\n"); + } + + sf_count_t res = sf_seek(audio->file, seek, SEEK_SET); + + if (res == -1) + return 0; + + return !!sf_readf_short(audio->file, (short*)buffer, samples_count); +} + +static uint64_t +audio_get_length(void *priv) +{ + track_file_t *tf = (track_file_t*)priv; + audio_file *audio = (audio_file*)tf->priv; + + return audio->info.frames * 4ull; +} + +static void +audio_close(void *priv) +{ + track_file_t *tf = (track_file_t*)priv; + audio_file *audio = (audio_file*)tf->priv; + + memset(tf->fn, 0x00, sizeof(tf->fn)); + if (audio && audio->file) + sf_close(audio->file); + free(audio); + free(tf); +} + +static track_file_t * +audio_init(const char *filename, int *error) +{ + track_file_t *tf = (track_file_t *) calloc(sizeof(track_file_t), 1); + audio_file *audio = (audio_file*) calloc(sizeof(audio_file), 1); +#ifdef _WIN32 + wchar_t filename_w[4096]; +#endif + + if (tf == NULL || audio == NULL) { + free(tf); + free(audio); + *error = 1; + return NULL; + } + + memset(tf->fn, 0x00, sizeof(tf->fn)); + strncpy(tf->fn, filename, sizeof(tf->fn) - 1); +#ifdef _WIN32 + mbstowcs(filename_w, filename, 4096); + audio->file = sf_wchar_open(filename_w, SFM_READ, &audio->info); +#else + audio->file = sf_open(filename, SFM_READ, &audio->info); +#endif + + if (!audio->file) { + goto cleanup_error; + } + + if (audio->info.channels != 2 || audio->info.samplerate != 44100) { + sf_close(audio->file); + goto cleanup_error; + } + + return tf; +cleanup_error: + free(tf); + free(audio); + *error = 1; + return NULL; +} + /* Binary file functions. */ static int bin_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count) @@ -995,6 +1087,9 @@ cdi_load_cue(cd_img_t *cdi, const char *cuefile) if (!strcmp(type, "BINARY")) { path_append_filename(filename, pathname, ansi); trk.file = track_file_init(filename, &error); + } else if (!strcmp(type, "WAVE")) { + path_append_filename(filename, pathname, ansi); + trk.file = audio_init(filename, &error); } if (error) { #ifdef ENABLE_CDROM_IMAGE_BACKEND_LOG From 4dd4d2e6e1584e56533af8cc0af6ad47bdf7ae09 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Fri, 5 Jul 2024 23:44:45 +0600 Subject: [PATCH 02/36] A bit of more fixes --- src/cdrom/cdrom_image_backend.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/src/cdrom/cdrom_image_backend.c b/src/cdrom/cdrom_image_backend.c index e7373a319..9e50d6503 100644 --- a/src/cdrom/cdrom_image_backend.c +++ b/src/cdrom/cdrom_image_backend.c @@ -68,17 +68,17 @@ cdrom_image_backend_log(const char *fmt, ...) # define cdrom_image_backend_log(fmt, ...) #endif -typedef struct audio_file { +typedef struct audio_file_t { SNDFILE *file; SF_INFO info; -} audio_file; +} audio_file_t; /* Audio file functions */ static int audio_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count) { track_file_t *tf = (track_file_t*)priv; - audio_file *audio = (audio_file*)tf->priv; + audio_file_t *audio = (audio_file_t*)tf->priv; uint64_t samples_seek = seek / 4; uint64_t samples_count = count / 4; @@ -98,7 +98,7 @@ static uint64_t audio_get_length(void *priv) { track_file_t *tf = (track_file_t*)priv; - audio_file *audio = (audio_file*)tf->priv; + audio_file_t *audio = (audio_file_t*)tf->priv; return audio->info.frames * 4ull; } @@ -107,7 +107,7 @@ static void audio_close(void *priv) { track_file_t *tf = (track_file_t*)priv; - audio_file *audio = (audio_file*)tf->priv; + audio_file_t *audio = (audio_file_t*)tf->priv; memset(tf->fn, 0x00, sizeof(tf->fn)); if (audio && audio->file) @@ -120,16 +120,13 @@ static track_file_t * audio_init(const char *filename, int *error) { track_file_t *tf = (track_file_t *) calloc(sizeof(track_file_t), 1); - audio_file *audio = (audio_file*) calloc(sizeof(audio_file), 1); + audio_file_t *audio = (audio_file_t*) calloc(sizeof(audio_file_t), 1); #ifdef _WIN32 wchar_t filename_w[4096]; #endif if (tf == NULL || audio == NULL) { - free(tf); - free(audio); - *error = 1; - return NULL; + goto cleanup_error; } memset(tf->fn, 0x00, sizeof(tf->fn)); @@ -145,7 +142,7 @@ audio_init(const char *filename, int *error) goto cleanup_error; } - if (audio->info.channels != 2 || audio->info.samplerate != 44100) { + if (audio->info.channels != 2 || audio->info.samplerate != 44100 || !audio->info.seekable) { sf_close(audio->file); goto cleanup_error; } @@ -1087,7 +1084,7 @@ cdi_load_cue(cd_img_t *cdi, const char *cuefile) if (!strcmp(type, "BINARY")) { path_append_filename(filename, pathname, ansi); trk.file = track_file_init(filename, &error); - } else if (!strcmp(type, "WAVE")) { + } else if (!strcmp(type, "WAVE") || !strcmp(type, "AIFF") || !strcmp(type, "MP3")) { path_append_filename(filename, pathname, ansi); trk.file = audio_init(filename, &error); } From 94c44da4d13c10436bb5cb11f53cb480c0d4805a Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Sat, 6 Jul 2024 14:46:45 +0600 Subject: [PATCH 03/36] Add support for using directories and .iso files within CUE sheets Add support for big-endian binary files Remove unused is_dir member --- src/cdrom/CMakeLists.txt | 1 + src/cdrom/cdrom_image.c | 1 - src/cdrom/cdrom_image_backend.c | 438 ++++++++++++++---------- src/cdrom/cdrom_ioctl.c | 1 - src/include/86box/cdrom.h | 1 - src/include/86box/cdrom_image_backend.h | 4 +- src/qt/qt_settingsfloppycdrom.cpp | 1 - 7 files changed, 258 insertions(+), 189 deletions(-) diff --git a/src/cdrom/CMakeLists.txt b/src/cdrom/CMakeLists.txt index f2acce4e2..897b353cb 100644 --- a/src/cdrom/CMakeLists.txt +++ b/src/cdrom/CMakeLists.txt @@ -20,5 +20,6 @@ pkg_check_modules(SNDFILE REQUIRED IMPORTED_TARGET sndfile) add_library(cdrom OBJECT cdrom.c cdrom_image_backend.c cdrom_image_viso.c cdrom_image.c cdrom_ioctl.c cdrom_mitsumi.c) target_link_libraries(86Box PkgConfig::SNDFILE) if (WIN32) + # MSYS2 target_link_libraries(86Box -static ${SNDFILE_STATIC_LIBRARIES}) endif() diff --git a/src/cdrom/cdrom_image.c b/src/cdrom/cdrom_image.c index 2203674cd..113d426c6 100644 --- a/src/cdrom/cdrom_image.c +++ b/src/cdrom/cdrom_image.c @@ -294,7 +294,6 @@ cdrom_image_open(cdrom_t *dev, const char *fn) dev->cd_status = CD_STATUS_DATA_ONLY; else dev->cd_status = CD_STATUS_STOPPED; - dev->is_dir = (i == 3); dev->seek_pos = 0; dev->cd_buflen = 0; dev->cdrom_capacity = image_get_capacity(dev); diff --git a/src/cdrom/cdrom_image_backend.c b/src/cdrom/cdrom_image_backend.c index 9e50d6503..e588a1938 100644 --- a/src/cdrom/cdrom_image_backend.c +++ b/src/cdrom/cdrom_image_backend.c @@ -14,10 +14,12 @@ * Authors: Miran Grca, * Fred N. van Kempen, * The DOSBox Team, + * Cacodemon345 * * Copyright 2016-2020 Miran Grca. * Copyright 2017-2020 Fred N. van Kempen. * Copyright 2002-2020 The DOSBox Team. + * Copyright 2024 Cacodemon345. */ #define __STDC_FORMAT_MACROS #include @@ -77,37 +79,38 @@ typedef struct audio_file_t { static int audio_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count) { - track_file_t *tf = (track_file_t*)priv; - audio_file_t *audio = (audio_file_t*)tf->priv; - uint64_t samples_seek = seek / 4; - uint64_t samples_count = count / 4; + track_file_t *tf = (track_file_t *) priv; + audio_file_t *audio = (audio_file_t *) tf->priv; + uint64_t samples_seek = seek / 4; + uint64_t samples_count = count / 4; if ((seek & 3) || (count & 3)) { - pclog("Reading on non-4-aligned boundaries\n"); + cdrom_image_backend_log("CD Audio file: Reading on non-4-aligned boundaries.\n"); } - sf_count_t res = sf_seek(audio->file, seek, SEEK_SET); + sf_count_t res = sf_seek(audio->file, samples_seek, SEEK_SET); if (res == -1) return 0; - - return !!sf_readf_short(audio->file, (short*)buffer, samples_count); + + return !!sf_readf_short(audio->file, (short *) buffer, samples_count); } static uint64_t audio_get_length(void *priv) { - track_file_t *tf = (track_file_t*)priv; - audio_file_t *audio = (audio_file_t*)tf->priv; + track_file_t *tf = (track_file_t *) priv; + audio_file_t *audio = (audio_file_t *) tf->priv; + /* Assume 16-bit audio, 2 channel. */ return audio->info.frames * 4ull; } static void audio_close(void *priv) { - track_file_t *tf = (track_file_t*)priv; - audio_file_t *audio = (audio_file_t*)tf->priv; + track_file_t *tf = (track_file_t *) priv; + audio_file_t *audio = (audio_file_t *) tf->priv; memset(tf->fn, 0x00, sizeof(tf->fn)); if (audio && audio->file) @@ -119,8 +122,8 @@ audio_close(void *priv) static track_file_t * audio_init(const char *filename, int *error) { - track_file_t *tf = (track_file_t *) calloc(sizeof(track_file_t), 1); - audio_file_t *audio = (audio_file_t*) calloc(sizeof(audio_file_t), 1); + track_file_t *tf = (track_file_t *) calloc(sizeof(track_file_t), 1); + audio_file_t *audio = (audio_file_t *) calloc(sizeof(audio_file_t), 1); #ifdef _WIN32 wchar_t filename_w[4096]; #endif @@ -139,14 +142,22 @@ audio_init(const char *filename, int *error) #endif if (!audio->file) { + cdrom_image_backend_log("Audio file open error!"); goto cleanup_error; } if (audio->info.channels != 2 || audio->info.samplerate != 44100 || !audio->info.seekable) { + cdrom_image_backend_log("Audio file not seekable or in non-CD format!"); sf_close(audio->file); goto cleanup_error; } + *error = 0; + tf->priv = audio; + tf->fp = NULL; + tf->close = audio_close; + tf->get_length = audio_get_length; + tf->read = audio_read; return tf; cleanup_error: free(tf); @@ -161,7 +172,7 @@ bin_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count) { track_file_t *tf; - cdrom_image_backend_log("CDROM: binary_read(%08lx, pos=%" PRIu64 " count=%lu\n", + cdrom_image_backend_log("CDROM: binary_read(%08lx, pos=%" PRIu64 " count=%lu)\n", tf->fp, seek, count); if ((tf = (track_file_t *) priv)->fp == NULL) @@ -181,6 +192,15 @@ bin_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count) return 0; } + if (UNLIKELY(tf->motorola)) { + for (uint64_t i = 0; i < count; i += 2) { + uint8_t buffer0 = buffer[i]; + uint8_t buffer1 = buffer[i + 1]; + buffer[i] = buffer1; + buffer[i + 1] = buffer0; + } + } + return 1; } @@ -368,12 +388,11 @@ int cdi_get_audio_track_info(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, TMSF *start, uint8_t *attr) { const track_t *trk = &cdi->tracks[track - 1]; + const int pos = trk->start + 150; if ((track < 1) || (track > cdi->tracks_num)) return 0; - const int pos = trk->start + 150; - FRAMES_TO_MSF(pos, &start->min, &start->sec, &start->fr); *track_num = trk->track_number; @@ -449,20 +468,20 @@ cdi_read_sector(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector) { const int track = cdi_get_track(cdi, sector) - 1; const uint64_t sect = (uint64_t) sector; - int raw_size; - int cooked_size; - uint64_t offset; - int m = 0; - int s = 0; - int f = 0; + int raw_size; + int cooked_size; + uint64_t offset; + int m = 0; + int s = 0; + int f = 0; if (track < 0) return 0; - const track_t *trk = &cdi->tracks[track]; - const int track_is_raw = ((trk->sector_size == RAW_SECTOR_SIZE) || (trk->sector_size == 2448)); + const track_t *trk = &cdi->tracks[track]; + const int track_is_raw = ((trk->sector_size == RAW_SECTOR_SIZE) || (trk->sector_size == 2448)); - const uint64_t seek = trk->skip + ((sect - trk->start) * trk->sector_size); + const uint64_t seek = trk->skip + ((sect - trk->start) * trk->sector_size); if (track_is_raw) raw_size = trk->sector_size; @@ -509,13 +528,13 @@ cdi_read_sector(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector) int cdi_read_sectors(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector, uint32_t num) { - int success = 1; + int success = 1; /* TODO: This fails to account for Mode 2. Shouldn't we have a function to get sector size? */ - const int sector_size = raw ? RAW_SECTOR_SIZE : COOKED_SECTOR_SIZE; - const uint32_t buf_len = num * sector_size; - uint8_t *buf = (uint8_t *) malloc(buf_len * sizeof(uint8_t)); + const int sector_size = raw ? RAW_SECTOR_SIZE : COOKED_SECTOR_SIZE; + const uint32_t buf_len = num * sector_size; + uint8_t *buf = (uint8_t *) malloc(buf_len * sizeof(uint8_t)); for (uint32_t i = 0; i < num; i++) { success = cdi_read_sector(cdi, &buf[i * sector_size], raw, sector + i); @@ -523,9 +542,7 @@ cdi_read_sectors(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector, uint3 break; /* Based on the DOSBox patch, but check all 8 bytes and makes sure it's not an audio track. */ - if (raw && (sector < cdi->tracks[0].length) && - !cdi->tracks[0].mode2 && (cdi->tracks[0].attr != AUDIO_TRACK) && - *(uint64_t *) &(buf[(i * sector_size) + 2068])) + if (raw && (sector < cdi->tracks[0].length) && !cdi->tracks[0].mode2 && (cdi->tracks[0].attr != AUDIO_TRACK) && *(uint64_t *) &(buf[(i * sector_size) + 2068])) return 0; } @@ -626,81 +643,94 @@ cdi_track_push_back(cd_img_t *cdi, track_t *trk) cdi->tracks_num++; } +int +cdi_get_iso_track(cd_img_t *cdi, track_t *trk, const char *filename) +{ + int error; + int ret = 2; + memset(trk, 0, sizeof(track_t)); + + /* Data track (shouldn't there be a lead in track?). */ + trk->file = bin_init(filename, &error); + if (error) { + if ((trk->file != NULL) && (trk->file->close != NULL)) + trk->file->close(trk->file); + ret = 3; + trk->file = viso_init(filename, &error); + if (error) { + if ((trk->file != NULL) && (trk->file->close != NULL)) + trk->file->close(trk->file); + return 0; + } + } + trk->number = 1; + trk->track_number = 1; + trk->attr = DATA_TRACK; + + /* Try to detect ISO type. */ + trk->form = 0; + trk->mode2 = 0; + + if (cdi_can_read_pvd(trk->file, RAW_SECTOR_SIZE, 0, 0)) + trk->sector_size = RAW_SECTOR_SIZE; + else if (cdi_can_read_pvd(trk->file, 2336, 1, 0)) { + trk->sector_size = 2336; + trk->mode2 = 1; + } else if (cdi_can_read_pvd(trk->file, 2324, 1, 2)) { + trk->sector_size = 2324; + trk->mode2 = 1; + trk->form = 2; + trk->noskip = 1; + } else if (cdi_can_read_pvd(trk->file, 2328, 1, 2)) { + trk->sector_size = 2328; + trk->mode2 = 1; + trk->form = 2; + trk->noskip = 1; + } else if (cdi_can_read_pvd(trk->file, 2336, 1, 1)) { + trk->sector_size = 2336; + trk->mode2 = 1; + trk->form = 1; + trk->skip = 8; + } else if (cdi_can_read_pvd(trk->file, RAW_SECTOR_SIZE, 1, 0)) { + trk->sector_size = RAW_SECTOR_SIZE; + trk->mode2 = 1; + } else if (cdi_can_read_pvd(trk->file, RAW_SECTOR_SIZE, 1, 1)) { + trk->sector_size = RAW_SECTOR_SIZE; + trk->mode2 = 1; + trk->form = 1; + } else { + /* We use 2048 mode 1 as the default. */ + trk->sector_size = COOKED_SECTOR_SIZE; + } + + trk->length = trk->file->get_length(trk->file) / trk->sector_size; + cdrom_image_backend_log("ISO: Data track: length = %" PRIu64 ", sector_size = %i\n", trk->length, trk->sector_size); + return ret; +} + int cdi_load_iso(cd_img_t *cdi, const char *filename) { - int error; int ret = 2; track_t trk; cdi->tracks = NULL; cdi->tracks_num = 0; - memset(&trk, 0, sizeof(track_t)); + ret = cdi_get_iso_track(cdi, &trk, filename); - /* Data track (shouldn't there be a lead in track?). */ - trk.file = bin_init(filename, &error); - if (error) { - if ((trk.file != NULL) && (trk.file->close != NULL)) - trk.file->close(trk.file); - ret = 3; - trk.file = viso_init(filename, &error); - if (error) { - if ((trk.file != NULL) && (trk.file->close != NULL)) - trk.file->close(trk.file); - return 0; - } + if (ret >= 1) { + cdi_track_push_back(cdi, &trk); + + /* Lead out track. */ + trk.number = 2; + trk.track_number = 0xAA; + trk.attr = 0x16; /* Was originally 0x00, but I believe 0x16 is appropriate. */ + trk.start = trk.length; + trk.length = 0; + trk.file = NULL; + cdi_track_push_back(cdi, &trk); } - trk.number = 1; - trk.track_number = 1; - trk.attr = DATA_TRACK; - - /* Try to detect ISO type. */ - trk.form = 0; - trk.mode2 = 0; - - if (cdi_can_read_pvd(trk.file, RAW_SECTOR_SIZE, 0, 0)) - trk.sector_size = RAW_SECTOR_SIZE; - else if (cdi_can_read_pvd(trk.file, 2336, 1, 0)) { - trk.sector_size = 2336; - trk.mode2 = 1; - } else if (cdi_can_read_pvd(trk.file, 2324, 1, 2)) { - trk.sector_size = 2324; - trk.mode2 = 1; - trk.form = 2; - } else if (cdi_can_read_pvd(trk.file, 2328, 1, 2)) { - trk.sector_size = 2328; - trk.mode2 = 1; - trk.form = 2; - } else if (cdi_can_read_pvd(trk.file, 2336, 1, 1)) { - trk.sector_size = 2336; - trk.mode2 = 1; - trk.form = 1; - trk.skip = 8; - } else if (cdi_can_read_pvd(trk.file, RAW_SECTOR_SIZE, 1, 0)) { - trk.sector_size = RAW_SECTOR_SIZE; - trk.mode2 = 1; - } else if (cdi_can_read_pvd(trk.file, RAW_SECTOR_SIZE, 1, 1)) { - trk.sector_size = RAW_SECTOR_SIZE; - trk.mode2 = 1; - trk.form = 1; - } else { - /* We use 2048 mode 1 as the default. */ - trk.sector_size = COOKED_SECTOR_SIZE; - } - - trk.length = trk.file->get_length(trk.file) / trk.sector_size; - cdrom_image_backend_log("ISO: Data track: length = %" PRIu64 ", sector_size = %i\n", trk.length, trk.sector_size); - cdi_track_push_back(cdi, &trk); - - /* Lead out track. */ - trk.number = 2; - trk.track_number = 0xAA; - trk.attr = 0x16; /* Was originally 0x00, but I believe 0x16 is appropriate. */ - trk.start = trk.length; - trk.length = 0; - trk.file = NULL; - cdi_track_push_back(cdi, &trk); return ret; } @@ -793,7 +823,7 @@ cdi_cue_get_frame(uint64_t *frames, char **line) char temp[128]; int min = 0; int sec = 0; - int fr = 0; + int fr = 0; int success; success = cdi_cue_get_buffer(temp, line, 0); @@ -854,7 +884,7 @@ cdi_add_track(cd_img_t *cdi, track_t *cur, uint64_t *shift, uint64_t prestart, u if (cur->number != 1) return 0; cur->skip = skip * cur->sector_size; - if ((cur->sector_size != RAW_SECTOR_SIZE) && (cur->form > 0)) + if ((cur->sector_size != RAW_SECTOR_SIZE) && (cur->form > 0) && !cur->noskip) cur->skip += 8; cur->start += cur_pregap; *total_pregap = cur_pregap; @@ -871,14 +901,14 @@ cdi_add_track(cd_img_t *cdi, track_t *cur, uint64_t *shift, uint64_t prestart, u cur->start += *total_pregap; } else { const uint64_t temp = prev->file->get_length(prev->file) - (prev->skip); - prev->length = temp / ((uint64_t) prev->sector_size); + prev->length = temp / ((uint64_t) prev->sector_size); if ((temp % prev->sector_size) != 0) prev->length++; /* Padding. */ cur->start += prev->start + prev->length + cur_pregap; cur->skip = skip * cur->sector_size; - if ((cur->sector_size != RAW_SECTOR_SIZE) && (cur->form > 0)) + if ((cur->sector_size != RAW_SECTOR_SIZE) && (cur->form > 0) && !cur->noskip) cur->skip += 8; *shift += prev->start + prev->length; *total_pregap = cur_pregap; @@ -902,12 +932,13 @@ cdi_load_cue(cd_img_t *cdi, const char *cuefile) { track_t trk; char pathname[MAX_FILENAME_LENGTH]; - uint64_t shift = 0ULL; - uint64_t prestart = 0ULL; - uint64_t cur_pregap = 0ULL; + uint64_t shift = 0ULL; + uint64_t prestart = 0ULL; + uint64_t cur_pregap = 0ULL; uint64_t total_pregap = 0ULL; - uint64_t frame = 0ULL; + uint64_t frame = 0ULL; uint64_t index; + int iso_file_used = 0; int success; int error; int can_add_track = 0; @@ -963,82 +994,97 @@ cdi_load_cue(cd_img_t *cdi, const char *cuefile) if (!success) break; - trk.start = 0; - trk.skip = 0; - cur_pregap = 0; - prestart = 0; + if (iso_file_used) { + /* We don't alter anything of the detected track type with the one specified in the CUE file, except its numbers. */ + cur_pregap = 0; + prestart = 0; - trk.number = cdi_cue_get_number(&line); - trk.track_number = trk.number; - success = cdi_cue_get_keyword(&type, &line); - if (!success) - break; + trk.number = cdi_cue_get_number(&line); + trk.track_number = trk.number; + success = cdi_cue_get_keyword(&type, &line); + if (!success) + break; + can_add_track = 1; - trk.form = 0; - trk.mode2 = 0; + iso_file_used = 0; + } else { + trk.start = 0; + trk.skip = 0; + cur_pregap = 0; + prestart = 0; - trk.pre = 0; + trk.number = cdi_cue_get_number(&line); + trk.track_number = trk.number; + success = cdi_cue_get_keyword(&type, &line); + if (!success) + break; - if (!strcmp(type, "AUDIO")) { - trk.sector_size = RAW_SECTOR_SIZE; - trk.attr = AUDIO_TRACK; - } else if (!strcmp(type, "MODE1/2048")) { - trk.sector_size = COOKED_SECTOR_SIZE; - trk.attr = DATA_TRACK; - } else if (!strcmp(type, "MODE1/2352")) { - trk.sector_size = RAW_SECTOR_SIZE; - trk.attr = DATA_TRACK; - } else if (!strcmp(type, "MODE1/2448")) { - trk.sector_size = 2448; - trk.attr = DATA_TRACK; - } else if (!strcmp(type, "MODE2/2048")) { - trk.form = 1; - trk.sector_size = COOKED_SECTOR_SIZE; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "MODE2/2324")) { - trk.form = 2; - trk.sector_size = 2324; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "MODE2/2328")) { - trk.form = 2; - trk.sector_size = 2328; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "MODE2/2336")) { - trk.form = 1; - trk.sector_size = 2336; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "MODE2/2352")) { - /* Assume this is XA Mode 2 Form 1. */ - trk.form = 1; - trk.sector_size = RAW_SECTOR_SIZE; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "MODE2/2448")) { - /* Assume this is XA Mode 2 Form 1. */ - trk.form = 1; - trk.sector_size = 2448; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "CDG/2448")) { - trk.sector_size = 2448; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "CDI/2336")) { - trk.sector_size = 2336; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else if (!strcmp(type, "CDI/2352")) { - trk.sector_size = RAW_SECTOR_SIZE; - trk.attr = DATA_TRACK; - trk.mode2 = 1; - } else - success = 0; + trk.form = 0; + trk.mode2 = 0; - can_add_track = 1; + trk.pre = 0; + + if (!strcmp(type, "AUDIO")) { + trk.sector_size = RAW_SECTOR_SIZE; + trk.attr = AUDIO_TRACK; + } else if (!strcmp(type, "MODE1/2048")) { + trk.sector_size = COOKED_SECTOR_SIZE; + trk.attr = DATA_TRACK; + } else if (!strcmp(type, "MODE1/2352")) { + trk.sector_size = RAW_SECTOR_SIZE; + trk.attr = DATA_TRACK; + } else if (!strcmp(type, "MODE1/2448")) { + trk.sector_size = 2448; + trk.attr = DATA_TRACK; + } else if (!strcmp(type, "MODE2/2048")) { + trk.form = 1; + trk.sector_size = COOKED_SECTOR_SIZE; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "MODE2/2324")) { + trk.form = 2; + trk.sector_size = 2324; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "MODE2/2328")) { + trk.form = 2; + trk.sector_size = 2328; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "MODE2/2336")) { + trk.form = 1; + trk.sector_size = 2336; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "MODE2/2352")) { + /* Assume this is XA Mode 2 Form 1. */ + trk.form = 1; + trk.sector_size = RAW_SECTOR_SIZE; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "MODE2/2448")) { + /* Assume this is XA Mode 2 Form 1. */ + trk.form = 1; + trk.sector_size = 2448; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "CDG/2448")) { + trk.sector_size = 2448; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "CDI/2336")) { + trk.sector_size = 2336; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else if (!strcmp(type, "CDI/2352")) { + trk.sector_size = RAW_SECTOR_SIZE; + trk.attr = DATA_TRACK; + trk.mode2 = 1; + } else + success = 0; + + can_add_track = 1; + } } else if (!strcmp(command, "INDEX")) { index = cdi_cue_get_number(&line); success = cdi_cue_get_frame(&frame, &line); @@ -1057,8 +1103,8 @@ cdi_load_cue(cd_img_t *cdi, const char *cuefile) break; } } else if (!strcmp(command, "FILE")) { - char filename[MAX_FILENAME_LENGTH]; - char ansi[MAX_FILENAME_LENGTH]; + char filename[MAX_FILENAME_LENGTH]; + char ansi[MAX_FILENAME_LENGTH]; if (can_add_track) success = cdi_add_track(cdi, &trk, &shift, prestart, &total_pregap, cur_pregap); @@ -1081,16 +1127,40 @@ cdi_load_cue(cd_img_t *cdi, const char *cuefile) trk.file = NULL; error = 1; - if (!strcmp(type, "BINARY")) { - path_append_filename(filename, pathname, ansi); - trk.file = track_file_init(filename, &error); + if (!strcmp(type, "BINARY") || !strcmp(type, "MOTOROLA")) { + int fn_len = 0; + if (!path_abs(ansi)) { + path_append_filename(filename, pathname, ansi); + } else { + strcpy(filename, ansi); + } + fn_len = strlen(filename); + if ((tolower((int) filename[fn_len - 1]) == 'o' + && tolower((int) filename[fn_len - 2]) == 's' + && tolower((int) filename[fn_len - 3]) == 'i' + && filename[fn_len - 4] == '.') + || plat_dir_check(filename)) { + error = !cdi_get_iso_track(cdi, &trk, filename); + if (!error) { + iso_file_used = 1; + } + } else + trk.file = track_file_init(filename, &error); + + if (trk.file) { + trk.file->motorola = !strcmp(type, "MOTOROLA"); + } } else if (!strcmp(type, "WAVE") || !strcmp(type, "AIFF") || !strcmp(type, "MP3")) { - path_append_filename(filename, pathname, ansi); + if (!path_abs(ansi)) { + path_append_filename(filename, pathname, ansi); + } else { + strcpy(filename, ansi); + } trk.file = audio_init(filename, &error); } if (error) { #ifdef ENABLE_CDROM_IMAGE_BACKEND_LOG - cdrom_image_backend_log("CUE: cannot open fille '%s' in cue sheet!\n", + cdrom_image_backend_log("CUE: cannot open file '%s' in cue sheet!\n", filename); #endif if (trk.file != NULL) { @@ -1159,7 +1229,7 @@ cdi_has_audio_track(cd_img_t *cdi) if ((cdi == NULL) || (cdi->tracks == NULL)) return 0; - /* Audio track has attribute 0x14. */ + /* Audio track has attribute 0x10. */ for (int i = 0; i < cdi->tracks_num; i++) { if (cdi->tracks[i].attr == AUDIO_TRACK) return 1; diff --git a/src/cdrom/cdrom_ioctl.c b/src/cdrom/cdrom_ioctl.c index a204fad0f..13df2d965 100644 --- a/src/cdrom/cdrom_ioctl.c +++ b/src/cdrom/cdrom_ioctl.c @@ -254,7 +254,6 @@ cdrom_ioctl_open(cdrom_t *dev, const char *drv) /* All good, reset state. */ dev->cd_status = CD_STATUS_STOPPED; - dev->is_dir = 0; dev->seek_pos = 0; dev->cd_buflen = 0; dev->cdrom_capacity = ioctl_get_capacity(dev); diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index b3f5a5ea5..b97693560 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -226,7 +226,6 @@ typedef struct cdrom { uint8_t speed; uint8_t cur_speed; - int is_dir; void *priv; char image_path[1024]; diff --git a/src/include/86box/cdrom_image_backend.h b/src/include/86box/cdrom_image_backend.h index 5222e8aa0..cf4fe95c3 100644 --- a/src/include/86box/cdrom_image_backend.h +++ b/src/include/86box/cdrom_image_backend.h @@ -53,6 +53,8 @@ typedef struct track_file_t { char fn[260]; FILE *fp; void *priv; + + int motorola; } track_file_t; typedef struct track_t { @@ -63,7 +65,7 @@ typedef struct track_t { int mode2; int form; int pre; - int pad; + int noskip; /* Do not skip by 8 bytes.*/ uint64_t start; uint64_t length; uint64_t skip; diff --git a/src/qt/qt_settingsfloppycdrom.cpp b/src/qt/qt_settingsfloppycdrom.cpp index 8f0ac81a9..190dbc2e1 100644 --- a/src/qt/qt_settingsfloppycdrom.cpp +++ b/src/qt/qt_settingsfloppycdrom.cpp @@ -218,7 +218,6 @@ SettingsFloppyCDROM::save() /* Removable devices category */ model = ui->tableViewCDROM->model(); for (int i = 0; i < CDROM_NUM; i++) { - cdrom[i].is_dir = 0; cdrom[i].priv = NULL; cdrom[i].ops = NULL; cdrom[i].image = NULL; From fe9817d379b9255838deb7907697596df438d7b9 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Jul 2024 00:01:54 +0200 Subject: [PATCH 04/36] The Alaris Cougar now allows the IBM 486BL CPU's as well. --- src/machine/machine_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index e09707008..c9e3b1dd6 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -6418,7 +6418,7 @@ const machine_t machines[] = { .available_flag = MACHINE_AVAILABLE, .gpio_acpi_handler = NULL, .cpu = { - .package = CPU_PKG_SOCKET3, + .package = CPU_PKG_SOCKET3 | CPU_PKG_486BL, .block = CPU_BLOCK_NONE, .min_bus = 0, .max_bus = 0, From 3d5093481256411bedefae41620950280775f5a4 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Jul 2024 00:07:21 +0200 Subject: [PATCH 05/36] Fixed the IBM 486BL EDX reset values and the Tandy 1000 CPU's. --- src/cpu/cpu_table.c | 8 ++++---- src/machine/machine_table.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 34832762f..2541c5875 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -1855,7 +1855,7 @@ const cpu_family_t cpu_families[] = { .rspeed = 50000000, .multi = 2, .voltage = 5000, - .edx_reset = 0xA439, + .edx_reset = 0x8439, .cpuid_model = 0, .cyrix_id = 0, .cpu_flags = 0, @@ -1872,7 +1872,7 @@ const cpu_family_t cpu_families[] = { .rspeed = 66666666, .multi = 2, .voltage = 5000, - .edx_reset = 0xA439, + .edx_reset = 0x8439, .cpuid_model = 0, .cyrix_id = 0, .cpu_flags = 0, @@ -1898,7 +1898,7 @@ const cpu_family_t cpu_families[] = { .rspeed = 75000000, .multi = 3, .voltage = 5000, - .edx_reset = 0xA439, + .edx_reset = 0x8439, .cpuid_model = 0, .cyrix_id = 0, .cpu_flags = 0, @@ -1915,7 +1915,7 @@ const cpu_family_t cpu_families[] = { .rspeed = 100000000, .multi = 3, .voltage = 5000, - .edx_reset = 0xA439, + .edx_reset = 0x8439, .cpuid_model = 0, .cyrix_id = 0, .cpu_flags = 0, diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index c9e3b1dd6..a7c5d1cbf 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -1509,7 +1509,7 @@ const machine_t machines[] = { .available_flag = MACHINE_AVAILABLE, .gpio_acpi_handler = NULL, .cpu = { - .package = CPU_PKG_8088_EUROPC, + .package = CPU_PKG_8088, .block = CPU_BLOCK_NONE, .min_bus = 0, .max_bus = 0, From 30390da91cd1a8a3f76577e0972476eaf7fb9c68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Jul 2024 02:18:54 +0200 Subject: [PATCH 06/36] Update control --- debian/control | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/debian/control b/debian/control index d67f5965b..a718aee33 100644 --- a/debian/control +++ b/debian/control @@ -13,6 +13,7 @@ Build-Depends: cmake (>= 3.21), libsdl2-dev, libslirp-dev, libxkbcommon-x11-dev, + libsndfile-dev, ninja-build, qttools5-dev, qtbase5-private-dev @@ -31,4 +32,4 @@ Recommends: libpcap0.8-dev Description: An emulator for classic IBM PC clones 86Box is a low level x86 emulator that runs older operating systems and software designed for IBM PC systems and compatibles from 1981 through - fairly recent system designs based on the PCI bus. \ No newline at end of file + fairly recent system designs based on the PCI bus. From d72b2ca4ff9c1519cfb225536a7e3e86207105df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Jul 2024 02:19:58 +0200 Subject: [PATCH 07/36] Update dependencies_macports.txt --- .ci/dependencies_macports.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/.ci/dependencies_macports.txt b/.ci/dependencies_macports.txt index 5ec71d07c..b23ac441d 100644 --- a/.ci/dependencies_macports.txt +++ b/.ci/dependencies_macports.txt @@ -15,3 +15,4 @@ fluidsynth ghostscript libslirp vde2 +libsndfile From ff68e08f57efedd77d5e8808c7d1b721f577820b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Jul 2024 02:20:12 +0200 Subject: [PATCH 08/36] Update dependencies_msys.txt --- .ci/dependencies_msys.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/.ci/dependencies_msys.txt b/.ci/dependencies_msys.txt index 694fe3e28..eacdb8b36 100644 --- a/.ci/dependencies_msys.txt +++ b/.ci/dependencies_msys.txt @@ -13,3 +13,4 @@ fluidsynth qt5-static qt5-translations vulkan-headers +libsndfile From 74ba3a897a6702527799e04fcf31d01ca7dbced7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Jul 2024 02:21:22 +0200 Subject: [PATCH 09/36] Update AppImageBuilder.yml --- .ci/AppImageBuilder.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.ci/AppImageBuilder.yml b/.ci/AppImageBuilder.yml index 22db9f151..f6e04ab9f 100644 --- a/.ci/AppImageBuilder.yml +++ b/.ci/AppImageBuilder.yml @@ -59,6 +59,7 @@ AppDir: - libqt5widgets5 # if QT:BOOL=ON - libsixel1 # if CLI:BOOL=ON - libslirp0 + - libsndfile-dev - libsndio7.0 # if OPENAL:BOOL=ON - libvdeplug-dev # -dev also pulls in libvdeplug2. -dev is required to get the proper .so symlink to the library - libx11-6 # if QT:BOOL=ON From 0fedbf9b469595fb7bd7fa23b5d6f409b1566e57 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 21:46:13 -0400 Subject: [PATCH 10/36] Named initializers for socket 5's and 7's --- src/cpu/cpu_table.c | 2718 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 2566 insertions(+), 152 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 2541c5875..d9b5247ea 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -3562,15 +3562,159 @@ const cpu_family_t cpu_families[] = { .name = "Pentium", .internal_name = "pentium_p54c", .cpus = (const CPU[]) { - {"75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 3520, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, - {"100/66", CPU_PENTIUM, fpus_internal, 100000000, 1.5, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"120", CPU_PENTIUM, fpus_internal, 120000000, 2.0, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"133", CPU_PENTIUM, fpus_internal, 133333333, 2.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUM, fpus_internal, 200000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + { + .name = "75", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x522, + .cpuid_model = 0x522, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { + .name = "90", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 21/2 + }, + { + .name = "100/50", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 12 + }, + { + .name = "100/66", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x526, + .cpuid_model = 0x526, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x526, + .cpuid_model = 0x526, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -3580,9 +3724,57 @@ const cpu_family_t cpu_families[] = { .name = "Pentium MMX", .internal_name = "pentium_p55c", .cpus = (const CPU[]) { - {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + { + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, { .name = "", 0 } } }, @@ -3592,14 +3784,142 @@ const cpu_family_t cpu_families[] = { .name = "Mobile Pentium MMX", .internal_name = "pentium_tillamook", .cpus = (const CPU[]) { - {"120", CPU_PENTIUMMMX, fpus_internal, 120000000, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133", CPU_PENTIUMMMX, fpus_internal, 133333333, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_PENTIUMMMX, fpus_internal, 266666666, 4.0, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUMMMX, fpus_internal, 300000000, 4.5, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + { + .name = "120", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x544, + .cpuid_model = 0x544, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x544, + .cpuid_model = 0x544, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x581, + .cpuid_model = 0x581, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x581, + .cpuid_model = 0x581, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2800, + .edx_reset = 0x582, + .cpuid_model = 0x582, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2800, + .edx_reset = 0x582, + .cpuid_model = 0x582, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, { .name = "", 0 } } }, @@ -3609,9 +3929,57 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive", .internal_name = "pentium_p54c_od3v", .cpus = (const CPU[]) { - {"125", CPU_PENTIUM, fpus_internal, 125000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, - {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, - {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, + { + .name = "125", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 125000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 15 + }, + { + .name = "150", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, { .name = "", 0 } } }, @@ -3621,12 +3989,98 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive MMX", .internal_name = "pentium_p55c_od", .cpus = (const CPU[]) { - {"75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 7, 7,4,4, 9}, - {"125", CPU_PENTIUMMMX, fpus_internal, 125000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, - {"150/60", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, - {"166", CPU_PENTIUMMMX, fpus_internal, 166000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, - {"180", CPU_PENTIUMMMX, fpus_internal, 180000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 21}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 24}, + { + .name = "75", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, .edx_reset = 0x1542, .cpuid_model = 0x1542, .cyrix_id = 0, .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, .mem_read_cycles = 7, .mem_write_cycles = 7,.cache_read_cycles = 4,.cache_write_cycles = 4, .atclk_div = 9}, + { + .name = "125", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 125000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 15 + }, + { + .name = "150/60", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "180", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 21 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -3636,17 +4090,193 @@ const cpu_family_t cpu_families[] = { .name = "WinChip", .internal_name = "winchip", .cpus = (const CPU[]) { - {"75", CPU_WINCHIP, fpus_internal, 75000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"90", CPU_WINCHIP, fpus_internal, 90000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"100", CPU_WINCHIP, fpus_internal, 100000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"120", CPU_WINCHIP, fpus_internal, 120000000, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"133", CPU_WINCHIP, fpus_internal, 133333333, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"150", CPU_WINCHIP, fpus_internal, 150000000, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"166", CPU_WINCHIP, fpus_internal, 166666666, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"180", CPU_WINCHIP, fpus_internal, 180000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"200", CPU_WINCHIP, fpus_internal, 200000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"225", CPU_WINCHIP, fpus_internal, 225000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"240", CPU_WINCHIP, fpus_internal, 240000000, 4.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, + { + .name = "75", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { + .name = "90", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 21/2 + }, + { + .name = "100", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 40 + }, + { + .name = "180", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 21 + }, + { + .name = "200", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "225", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 225000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 27 + }, + { + .name = "240", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 240000000, + .multi = 4.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 28 + }, { .name = "", 0 } } }, @@ -3656,10 +4286,74 @@ const cpu_family_t cpu_families[] = { .name = "WinChip 2", .internal_name = "winchip2", .cpus = (const CPU[]) { - {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"225", CPU_WINCHIP2, fpus_internal, 225000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, - {"240", CPU_WINCHIP2, fpus_internal, 240000000, 4.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"250", CPU_WINCHIP2, fpus_internal, 250000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + { + .name = "200", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 3*8 + }, + { + .name = "225", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 225000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 3*9 + }, + { + .name = "240", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 240000000, + .multi = 4.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 30 + }, + { + .name = "250", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 30 + }, { .name = "", 0 } } }, @@ -3669,10 +4363,74 @@ const cpu_family_t cpu_families[] = { .name = "WinChip 2A", .internal_name = "winchip2a", .cpus = (const CPU[]) { - {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"233", CPU_WINCHIP2, fpus_internal, 233333333, 3.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, - {"266", CPU_WINCHIP2, fpus_internal, 233333333, 7.0/3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, - {"300", CPU_WINCHIP2, fpus_internal, 250000000, 2.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, + { + .name = "200", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 3*8 + }, + { + .name = "233", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = (7*8)/2 + }, + { + .name = "266", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 7.0/3.0, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 28 + }, + { + .name = "300", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 30 + }, { .name = "", 0 } } }, @@ -3683,9 +4441,57 @@ const cpu_family_t cpu_families[] = { .name = "K5 (Model 0)", .internal_name = "k5_ssa5", .cpus = (const CPU[]) { - {"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"90 (PR90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + { + .name = "75 (PR75)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { + .name = "90 (PR90)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 21/2 + }, + { + .name = "100 (PR100)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, { .name = "", 0 } } }, @@ -3695,11 +4501,91 @@ const cpu_family_t cpu_families[] = { .name = "K5 (Model 1/2/3)", .internal_name = "k5_5k86", .cpus = (const CPU[]) { - {"90 (PR120)", CPU_5K86, fpus_internal, 120000000, 2.0, 3520, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"100 (PR133)", CPU_5K86, fpus_internal, 133333333, 2.0, 3520, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"105 (PR150)", CPU_5K86, fpus_internal, 150000000, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"116.7 (PR166)", CPU_5K86, fpus_internal, 166666666, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"133 (PR200)", CPU_5K86, fpus_internal, 200000000, 3.0, 3520, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + { + .name = "90 (PR120)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x511, + .cpuid_model = 0x511, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "100 (PR133)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x514, + .cpuid_model = 0x514, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "105 (PR150)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "116.7 (PR166)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "133 (PR200)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x534, + .cpuid_model = 0x534, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -3710,12 +4596,108 @@ const cpu_family_t cpu_families[] = { .name = "K6 (Model 6)", .internal_name = "k6_m6", .cpus = (const CPU[]) { - {"66", CPU_K6, fpus_internal, 66666666, 1.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "166", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3200, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, { .name = "", 0 } } }, { @@ -3724,13 +4706,117 @@ const cpu_family_t cpu_families[] = { .name = "K6 (Model 7)", .internal_name = "k6_m7", .cpus = (const CPU[]) { - {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_K6, fpus_internal, 233333333, 3.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_K6, fpus_internal, 266666666, 4.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_K6, fpus_internal, 300000000, 4.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 166666666, .multi = 2.5, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 200000000, .multi = 3.0, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 233333333, .multi = 3.5, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, { .name = "", 0 } } }, @@ -3740,24 +4826,312 @@ const cpu_family_t cpu_families[] = { .name = "K6-2", .internal_name = "k6_2", .cpus = (const CPU[]) { - {"100", CPU_K6_2, fpus_internal, 100000000, 1.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_2, fpus_internal, 133333333, 2.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_2, fpus_internal, 166666666, 2.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_2, fpus_internal, 200000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_2, fpus_internal, 233333333, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, - {"266", CPU_K6_2, fpus_internal, 266666666, 4.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, - {"300", CPU_K6_2, fpus_internal, 300000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, - {"333", CPU_K6_2, fpus_internal, 332500000, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, - {"350", CPU_K6_2C, fpus_internal, 350000000, 3.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, - {"366", CPU_K6_2C, fpus_internal, 366666666, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, - {"380", CPU_K6_2C, fpus_internal, 380000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, - {"400/66", CPU_K6_2C, fpus_internal, 400000000, 6.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"400/100", CPU_K6_2C, fpus_internal, 400000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_2C, fpus_internal, 450000000, 4.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_2C, fpus_internal, 475000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_2C, fpus_internal, 500000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"533", CPU_K6_2C, fpus_internal, 533333333, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"550", CPU_K6_2C, fpus_internal, 550000000, 5.5, 2300, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { + .name = "333", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { + .name = "350", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { + .name = "366", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { + .name = "380", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { + .name = "400/66", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "400/100", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { + .name = "475", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2400, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 57 + }, + { + .name = "500", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2400, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { + .name = "533", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 64 + }, + { + .name = "550", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2300, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, { .name = "", 0 } } }, { @@ -3766,24 +5140,312 @@ const cpu_family_t cpu_families[] = { .name = "K6-2+", .internal_name = "k6_2p", .cpus = (const CPU[]) { - {"100", CPU_K6_2P, fpus_internal, 100000000, 1.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_2P, fpus_internal, 133333333, 2.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_2P, fpus_internal, 166666666, 2.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_2P, fpus_internal, 200000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_2P, fpus_internal, 233333333, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_2P, fpus_internal, 266666666, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_2P, fpus_internal, 300000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_2P, fpus_internal, 332500000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_2P, fpus_internal, 350000000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_2P, fpus_internal, 366666666, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_2P, fpus_internal, 380000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400/66", CPU_K6_2P, fpus_internal, 400000000, 6.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ - {"400/100", CPU_K6_2P, fpus_internal, 400000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ - {"450", CPU_K6_2P, fpus_internal, 450000000, 4.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_2P, fpus_internal, 475000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_2P, fpus_internal, 500000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"533", CPU_K6_2P, fpus_internal, 533333333, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"550", CPU_K6_2P, fpus_internal, 550000000, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { /* out of spec */ + .name = "380", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { /* out of spec */ + .name = "400/66", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { /* out of spec */ + .name = "400/100", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { + .name = "475", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 57 + }, + { + .name = "500", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { + .name = "533", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 64 + }, + { + .name = "550", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, { .name = "", 0 } } }, { @@ -3792,19 +5454,227 @@ const cpu_family_t cpu_families[] = { .name = "K6-III", .internal_name = "k6_3", .cpus = (const CPU[]) { - {"100", CPU_K6_3, fpus_internal, 100000000, 1.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_3, fpus_internal, 133333333, 2.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_3, fpus_internal, 166666666, 2.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_3, fpus_internal, 200000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_3, fpus_internal, 233333333, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_3, fpus_internal, 266666666, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_3, fpus_internal, 300000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_3, fpus_internal, 332500000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_3, fpus_internal, 350000000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_3, fpus_internal, 366666666, 5.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_3, fpus_internal, 380000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400", CPU_K6_3, fpus_internal, 400000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_3, fpus_internal, 450000000, 4.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { /* out of spec */ + .name = "380", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { + .name = "400", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, { .name = "", 0 } } }, @@ -3814,21 +5684,261 @@ const cpu_family_t cpu_families[] = { .name = "K6-III+", .internal_name = "k6_3p", .cpus = (const CPU[]) { - {"100", CPU_K6_3P, fpus_internal, 100000000, 1.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, /* out of spec */ - {"133", CPU_K6_3P, fpus_internal, 133333333, 2.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_3P, fpus_internal, 166666666, 2.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_3P, fpus_internal, 200000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_3P, fpus_internal, 233333333, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_3P, fpus_internal, 266666666, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_3P, fpus_internal, 300000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_3P, fpus_internal, 332500000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_3P, fpus_internal, 350000000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_3P, fpus_internal, 366666666, 5.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_3P, fpus_internal, 380000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400", CPU_K6_3P, fpus_internal, 400000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_3P, fpus_internal, 450000000, 4.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_3P, fpus_internal, 475000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_3P, fpus_internal, 500000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { /* out of spec */ + .name = "380", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { + .name = "400", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { + .name = "475", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 57 + }, + { + .name = "500", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, { .name = "", 0 } } }, @@ -3839,12 +5949,108 @@ const cpu_family_t cpu_families[] = { .name = "Cx6x86", .internal_name = "cx6x86", .cpus = (const CPU[]) { - {"80 (PR90+)", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"100 (PR120+)", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"110 (PR133+)", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"120 (PR150+)", CPU_Cx6x86, fpus_internal, 120000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133 (PR166+)", CPU_Cx6x86, fpus_internal, 133333333, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150 (PR200+)", CPU_Cx6x86, fpus_internal, 150000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + { + .name = "80 (PR90+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, + { + .name = "100 (PR120+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 12 + }, + { + .name = "110 (PR133+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 110000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "120 (PR150+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133 (PR166+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150 (PR200+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 18 + }, { .name = "", 0 } } }, @@ -3854,10 +6060,74 @@ const cpu_family_t cpu_families[] = { .name = "Cx6x86L", .internal_name = "cx6x86l", .cpus = (const CPU[]) { - {"110 (PR133+)", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"120 (PR150+)", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133 (PR166+)", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150 (PR200+)", CPU_Cx6x86L, fpus_internal, 150000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + { + .name = "110 (PR133+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 110000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "120 (PR150+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133 (PR166+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150 (PR200+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 18 + }, { .name = "", 0 } } }, @@ -3867,10 +6137,74 @@ const cpu_family_t cpu_families[] = { .name = "Cx6x86MX", .internal_name = "cx6x86mx", .cpus = (const CPU[]) { - {"133 (PR166)", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"166 (PR200)", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"187.5 (PR233)", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"208.3 (PR266)", CPU_Cx6x86MX, fpus_internal, 208333333, 2.5, 2700, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + { + .name = "133 (PR166)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0451, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "166 (PR200)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "187.5 (PR233)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 187500000, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 45/2 + }, + { + .name = "208.3 (PR266)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 208333333, + .multi = 2.5, + .voltage = 2700, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 17, + .mem_write_cycles = 17, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 25 + }, { .name = "", 0 } } }, @@ -3880,11 +6214,91 @@ const cpu_family_t cpu_families[] = { .name = "MII", .internal_name = "mii", .cpus = (const CPU[]) { - {"233 (PR300)", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"250/83 (PR333)", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"250/100 (PR366)", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, - {"285 (PR400)", CPU_Cx6x86MX, fpus_internal, 285000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, - {"300 (PR433)", CPU_Cx6x86MX, fpus_internal, 300000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, + { + .name = "233 (PR300)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0852, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 28 + }, + { + .name = "250/83 (PR333)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 23, + .mem_write_cycles = 23, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 30 + }, + { + .name = "250/100 (PR366)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 23, + .mem_write_cycles = 23, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 30 + }, + { + .name = "285 (PR400)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 285000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 34 + }, + { + .name = "300 (PR433)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, { .name = "", 0 } } }, From 6141577347109391f4889b32a1ca668afe58d978 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 07:53:11 -0400 Subject: [PATCH 11/36] Named initializers for socket 8's --- src/cpu/cpu_table.c | 342 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 323 insertions(+), 19 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index d9b5247ea..c2b7e1ce7 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -6309,16 +6309,176 @@ const cpu_family_t cpu_families[] = { .name = "Pentium Pro", .internal_name = "pentiumpro", .cpus = (const CPU[]) { - {"60", CPU_PENTIUMPRO, fpus_internal, 60000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 1, 1, 7}, /* out of spec */ - {"66", CPU_PENTIUMPRO, fpus_internal, 66666666, 1.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 1, 1, 8}, /* out of spec */ - {"90", CPU_PENTIUMPRO, fpus_internal, 90000000, 1.5, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 11}, /* out of spec */ - {"100", CPU_PENTIUMPRO, fpus_internal, 100000000, 1.5, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 12}, /* out of spec */ - {"120", CPU_PENTIUMPRO, fpus_internal, 120000000, 2.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 5, 5, 14}, /* out of spec */ - {"133", CPU_PENTIUMPRO, fpus_internal, 133333333, 2.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 5, 5, 16}, /* out of spec */ - {"150", CPU_PENTIUMPRO, fpus_internal, 150000000, 2.5, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUMPRO, fpus_internal, 166666666, 2.5, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"180", CPU_PENTIUMPRO, fpus_internal, 180000000, 3.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"200", CPU_PENTIUMPRO, fpus_internal, 200000000, 3.0, 3300, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + { /* out of spec */ + .name = "60", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 60000000, + .multi = 1.0, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 1, + .cache_write_cycles = 1, + .atclk_div = 7 + }, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 1, + .cache_write_cycles = 1, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "90", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 11 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "120", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 5, + .cache_write_cycles = 5, + .atclk_div = 14 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 5, + .cache_write_cycles = 5, + .atclk_div = 16 + }, /* out of spec */ + { + .name = "150", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "180", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 21 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -6328,15 +6488,159 @@ const cpu_family_t cpu_families[] = { .name = "Pentium II OverDrive", .internal_name = "pentium2_od", .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18, 9, 9, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 21,21,10,10, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 24,24,12,12, 32}, /* out of spec */ - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 5.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 36}, - {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 40}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 5.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, + { + .name = "333", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 40 + }, { .name = "", 0 } } }, From a880c9a020eb408d3db53a05011483752b04272e Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 08:39:30 -0400 Subject: [PATCH 12/36] Named initializers for Slot 1's --- src/cpu/cpu_table.c | 504 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 476 insertions(+), 28 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index c2b7e1ce7..0c11b08c6 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -6650,14 +6650,142 @@ const cpu_family_t cpu_families[] = { .name = "Pentium II (Klamath)", .internal_name = "pentium2_klamath", .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2, fpus_internal, 66666666, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2, fpus_internal, 100000000, 1.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_PENTIUM2, fpus_internal, 133333333, 2.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_PENTIUM2, fpus_internal, 166666666, 2.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2, fpus_internal, 200000000, 3.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, /* out of spec */ - {"233", CPU_PENTIUM2, fpus_internal, 233333333, 3.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_PENTIUM2, fpus_internal, 266666666, 4.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUM2, fpus_internal, 300000000, 4.5, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 36 + }, { .name = "", 0 } } }, { @@ -6666,18 +6794,210 @@ const cpu_family_t cpu_families[] = { .name = "Pentium II (Deschutes)", .internal_name = "pentium2_deschutes", .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 5, 5, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"350", CPU_PENTIUM2D, fpus_internal, 350000000, 3.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, - {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 5, + .cache_write_cycles = 5, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 36 + }, + { + .name = "333", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 40 + }, + { + .name = "350", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { + .name = "400", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, { .name = "", 0 } } }, @@ -6687,14 +7007,142 @@ const cpu_family_t cpu_families[] = { .name = "Celeron (Covington)", .internal_name = "celeron_covington", .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 6, 6, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 9, 9, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,12,12, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,15,15, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,18,18, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,21,21, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,24,24, 32}, - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,25,25, 36}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 21, + .cache_write_cycles = 21, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x650, + .cpuid_model = 0x650, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 24, + .cache_write_cycles = 24, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 25, + .cache_write_cycles = 25, + .atclk_div = 36 + }, { .name = "", 0 } } }, { From 8af310e0a2983976c291a09e1d4c693dc6c55296 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 18:00:21 -0400 Subject: [PATCH 13/36] Named initializers for Slot 2's --- src/cpu/cpu_table.c | 144 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 136 insertions(+), 8 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 0c11b08c6..bc626492f 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -7151,14 +7151,142 @@ const cpu_family_t cpu_families[] = { .name = "Pentium II Xeon", .internal_name = "pentium2_xeon", .cpus = (const CPU[]) { - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 3, 3, 12}, /* out of spec */ - {"150", CPU_PENTIUM2D, fpus_internal, 150000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 14,14, 4, 4, 18}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 6, 6, 24}, /* out of spec */ - {"250", CPU_PENTIUM2D, fpus_internal, 250000000, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 22,22, 7, 7, 30}, /* out of spec */ - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, /* out of spec */ - {"350", CPU_PENTIUM2D, fpus_internal, 350000000, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,10,10, 42}, /* out of spec */ - {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 4.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "150", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 18 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "250", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 22, + .mem_write_cycles = 22, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 30 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 42 + }, + { + .name = "400", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, { .name = "", 0 } } }, From decce7720483edab212c7fac19940f48d4893cd4 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 18:47:11 -0400 Subject: [PATCH 14/36] Named initializers for Socket 370's --- src/cpu/cpu_table.c | 684 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 646 insertions(+), 38 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index bc626492f..e461ed7b5 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -7296,21 +7296,261 @@ const cpu_family_t cpu_families[] = { .name = "Celeron (Mendocino)", .internal_name = "celeron_mendocino", .cpus = (const CPU[]) { - {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8, 4, 4, 12}, /* out of spec */ - {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 11,11, 5, 5, 16}, /* out of spec */ - {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 14,14, 7, 7, 20}, /* out of spec */ - {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 17,17, 8, 8, 24}, /* out of spec */ - {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 19,19, 9, 9, 28}, /* out of spec */ - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 22,22,11,11, 32}, /* out of spec */ - {"300A", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 25,25,12,12, 36}, - {"333", CPU_PENTIUM2D, fpus_internal, 333333333, 5.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 27,27,13,13, 40}, - {"366", CPU_PENTIUM2D, fpus_internal, 366666666, 5.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 33,33,17,17, 44}, - {"400", CPU_PENTIUM2D, fpus_internal, 400000000, 6.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 36,36,12,12, 48}, - {"433", CPU_PENTIUM2D, fpus_internal, 433333333, 6.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 39,39,13,13, 51}, - {"466", CPU_PENTIUM2D, fpus_internal, 466666666, 7.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 42,42,14,14, 56}, - {"500", CPU_PENTIUM2D, fpus_internal, 500000000, 7.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 45,45,15,15, 60}, - {"533", CPU_PENTIUM2D, fpus_internal, 533333333, 8.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 48,48,17,17, 64}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 11, + .mem_write_cycles = 11, + .cache_read_cycles = 5, + .cache_write_cycles = 5, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 17, + .mem_write_cycles = 17, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 19, + .mem_write_cycles = 19, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 22, + .mem_write_cycles = 22, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 32 + }, + { + .name = "300A", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 36 + }, + { + .name = "333", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 40 + }, + { + .name = "366", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { + .name = "400", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "433", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 433333333, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 39, + .mem_write_cycles = 39, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 51 + }, + { + .name = "466", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 466666666, + .multi = 7.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 42, + .mem_write_cycles = 42, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 56 + }, + { + .name = "500", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 7.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { + .name = "533", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 8.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 64 + }, { .name = "", 0 } } }, @@ -7320,29 +7560,397 @@ const cpu_family_t cpu_families[] = { .name = "Cyrix III", .internal_name = "c3_samuel", .cpus = (const CPU[]) { - {"66", CPU_CYRIX3S, fpus_internal, 66666666, 1.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* out of multiplier range */ - {"100", CPU_CYRIX3S, fpus_internal, 100000000, 1.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 9, 9, 4, 4, 12}, /* out of multiplier range */ - {"133", CPU_CYRIX3S, fpus_internal, 133333333, 2.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 12, 12, 6, 6, 16}, /* out of multiplier range */ - {"166", CPU_CYRIX3S, fpus_internal, 166666666, 2.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 15, 15, 7, 7, 20}, /* out of multiplier range */ - {"200", CPU_CYRIX3S, fpus_internal, 200000000, 3.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 18, 18, 8, 8, 24}, /* out of multiplier range */ - {"233", CPU_CYRIX3S, fpus_internal, 233333333, 3.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 21, 21, 9, 9, 28}, /* out of multiplier range */ - {"266", CPU_CYRIX3S, fpus_internal, 266666666, 4.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 24, 24, 12, 12, 32}, /* out of multiplier range */ - {"300", CPU_CYRIX3S, fpus_internal, 300000000, 4.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 27, 27, 13, 13, 36}, /* out of spec */ - {"333", CPU_CYRIX3S, fpus_internal, 333333333, 5.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 30, 30, 15, 15, 40}, /* out of spec */ - {"366", CPU_CYRIX3S, fpus_internal, 366666666, 5.5, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 33, 33, 16, 16, 44}, /* out of spec */ - {"400", CPU_CYRIX3S, fpus_internal, 400000000, 6.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 36, 36, 17, 17, 48}, - {"433", CPU_CYRIX3S, fpus_internal, 433333333, 6.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 39, 39, 18, 18, 52}, /* out of spec */ - {"450", CPU_CYRIX3S, fpus_internal, 450000000, 4.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 41, 41, 14, 14, 54}, - {"466", CPU_CYRIX3S, fpus_internal, 466666666, 6.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 42, 42, 14, 14, 56}, /* out of spec */ - {"500", CPU_CYRIX3S, fpus_internal, 500000000, 5.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 45, 45, 15, 15, 60}, - {"533", CPU_CYRIX3S, fpus_internal, 533333333, 8.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 48, 48, 15, 15, 64}, /* out of spec */ - {"550", CPU_CYRIX3S, fpus_internal, 550000000, 5.5, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 50, 50, 17, 17, 66}, - {"600/100", CPU_CYRIX3S, fpus_internal, 600000000, 6.0, 2050, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 54, 54, 18, 18, 72}, - {"600/133", CPU_CYRIX3S, fpus_internal, 600000000, 4.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 54, 54, 13, 13, 72}, - {"650", CPU_CYRIX3S, fpus_internal, 650000000, 6.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 58, 58, 20, 20, 78}, - {"667", CPU_CYRIX3S, fpus_internal, 666666667, 5.0, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 60, 60, 16, 16, 80}, - {"700", CPU_CYRIX3S, fpus_internal, 700000000, 7.0, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 63, 63, 21, 21, 84}, - {"733", CPU_CYRIX3S, fpus_internal, 733333333, 5.5, 2050, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 66, 66, 18, 18, 88}, + { /* out of multiplier range */ + .name = "66", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of multiplier range */ + .name = "100", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of multiplier range */ + .name = "133", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of multiplier range */ + .name = "166", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of multiplier range */ + .name = "200", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 24 + }, + { /* out of multiplier range */ + .name = "233", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 28 + }, + { /* out of multiplier range */ + .name = "266", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 16, + .cache_write_cycles = 16, + .atclk_div = 44 + }, + { + .name = "400", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 48 + }, + { /* out of spec */ + .name = "433", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 433333333, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 39, + .mem_write_cycles = 39, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 52 + }, + { + .name = "450", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { /* out of spec */ + .name = "466", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 466666666, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 42, + .mem_write_cycles = 42, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 56 + }, + { + .name = "500", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { /* out of spec */ + .name = "533", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 8.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 64 + }, + { + .name = "550", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, + { + .name = "600/100", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 600000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 54, + .mem_write_cycles = 54, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 72 + }, + { + .name = "600/133", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 600000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 54, + .mem_write_cycles = 54, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 72 + }, + { + .name = "650", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 650000000, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 58, + .mem_write_cycles = 58, + .cache_read_cycles = 20, + .cache_write_cycles = 20, + .atclk_div = 78 + }, + { + .name = "667", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 666666667, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 60, + .mem_write_cycles = 60, + .cache_read_cycles = 16, + .cache_write_cycles = 16, + .atclk_div = 80 + }, + { + .name = "700", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 700000000, + .multi = 7.0, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 63, + .mem_write_cycles = 63, + .cache_read_cycles = 21, + .cache_write_cycles = 21, + .atclk_div = 84 + }, + { + .name = "733", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 733333333, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 66, + .mem_write_cycles = 66, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 88 + }, { .name = "", 0 } } }, From cb6cc140d2a01d3bd694cb27b4cb891180399dcd Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 19:39:32 -0400 Subject: [PATCH 15/36] Bits of cpu_table formatting which escaped --- src/cpu/cpu_table.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index e461ed7b5..e363f3983 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -80,7 +80,7 @@ const cpu_family_t cpu_families[] = { .name = "4.77", .cpu_type = CPU_8088, .fpus = fpus_8088, - .rspeed = 4772728, + .rspeed = 4772728, .multi = 1, .voltage = 5000, .edx_reset = 0, @@ -97,7 +97,7 @@ const cpu_family_t cpu_families[] = { .name = "7.16", .cpu_type = CPU_8088, .fpus = fpus_8088, - .rspeed = 7159092, + .rspeed = 7159092, .multi = 1, .voltage = 5000, .edx_reset = 0, @@ -114,7 +114,7 @@ const cpu_family_t cpu_families[] = { .name = "8", .cpu_type = CPU_8088, .fpus = fpus_8088, - .rspeed = 8000000, + .rspeed = 8000000, .multi = 1, .voltage = 5000, .edx_reset = 0, @@ -132,7 +132,7 @@ const cpu_family_t cpu_families[] = { .name = "9.54", .cpu_type = CPU_8088, .fpus = fpus_8088, - .rspeed = 9545456, + .rspeed = 9545456, .multi = 1, .voltage = 5000, .edx_reset = 0, @@ -3282,10 +3282,38 @@ const cpu_family_t cpu_families[] = { .internal_name = "cx486dx4", .cpus = (const CPU[]) { { - .name = "75", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 75000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 12,.mem_write_cycles = 12, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 9 + .name = "75", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x361f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 }, { - .name = "100", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 100000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 15,.mem_write_cycles = 15, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 12 + .name = "100", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x361f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 }, { .name = "", 0 } } From 56cc182e61ce05b13c02ef07d03a3b6f82cb8a32 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 19:53:27 -0400 Subject: [PATCH 16/36] Align assignments in cpu_table --- src/cpu/cpu_table.c | 12636 +++++++++++++++++++++--------------------- 1 file changed, 6323 insertions(+), 6313 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index e363f3983..199e197df 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -71,7914 +71,7924 @@ FPU fpus_internal[] = { const cpu_family_t cpu_families[] = { // clang-format off { - .package = CPU_PKG_8088, - .manufacturer = "Intel", - .name = "8088", + .package = CPU_PKG_8088, + .manufacturer = "Intel", + .name = "8088", .internal_name = "8088", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "4.77", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 4772728, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "4.77", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 4772728, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "7.16", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "7.16", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "8", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "8", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, #if 0 { - .name = "9.54", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "9.54", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, #endif { - .name = "10", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "10", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "12", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "16", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "16", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { .name = "", 0 } } }, { - .package = CPU_PKG_8088_EUROPC, - .manufacturer = "Intel", - .name = "8088", + .package = CPU_PKG_8088_EUROPC, + .manufacturer = "Intel", + .name = "8088", .internal_name = "8088_europc", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "4.77", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 4772728, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "4.77", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 4772728, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "7.16", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "7.16", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "9.54", - .cpu_type = CPU_8088, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "9.54", + .cpu_type = CPU_8088, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { .name = "", 0 } } }, { - .package = CPU_PKG_8086, - .manufacturer = "Intel", - .name = "8086", + .package = CPU_PKG_8086, + .manufacturer = "Intel", + .name = "8086", .internal_name = "8086", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "7.16", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "7.16", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "8", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "8", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "9.54", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "9.54", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "10", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "10", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "12", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "16", - .cpu_type = CPU_8086, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "16", + .cpu_type = CPU_8086, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 2 + .atclk_div = 2 }, { .name = "", 0 } } }, { - .package = CPU_PKG_188, - .manufacturer = "Intel", - .name = "80188", + .package = CPU_PKG_188, + .manufacturer = "Intel", + .name = "80188", .internal_name = "80188", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "6", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 6000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "6", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 6000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "7.16", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "7.16", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "8", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "8", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "9.54", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 9545456, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "9.54", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 9545456, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "10", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "10", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "12", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "16", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "16", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "20", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_188, - .fpus = fpus_8088, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "25", + .cpu_type = CPU_188, + .fpus = fpus_8088, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 3 + .atclk_div = 3 }, { .name = "", 0 } } }, { - .package = CPU_PKG_8088, - .manufacturer = "NEC", - .name = "V20", + .package = CPU_PKG_8088, + .manufacturer = "NEC", + .name = "V20", .internal_name = "necv20", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "4.77", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 4772728, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "4.77", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 4772728, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "7.16", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 7159092, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "7.16", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 7159092, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "10", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "10", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "12", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "16", - .cpu_type = CPU_V20, - .fpus = fpus_8088, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "16", + .cpu_type = CPU_V20, + .fpus = fpus_8088, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 2 + .atclk_div = 2 }, { .name = "", 0 } } }, { - .package = CPU_PKG_186, - .manufacturer = "Intel", - .name = "80186", + .package = CPU_PKG_186, + .manufacturer = "Intel", + .name = "80186", .internal_name = "80186", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "6", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 6000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "6", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 6000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "7.16", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 7159092, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "7.16", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 7159092, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "8", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 8000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "8", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 8000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "9.54", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 9545456, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_ALTERNATE_XTAL, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "9.54", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 9545456, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_ALTERNATE_XTAL, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "10", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 10000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "10", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 10000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 12000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "12", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 12000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "16", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 16000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "16", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 16000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 20000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "20", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 20000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_186, - .fpus = fpus_80186, - .rspeed = 25000000, - .multi = 1, - .voltage = 0, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "25", + .cpu_type = CPU_186, + .fpus = fpus_80186, + .rspeed = 25000000, + .multi = 1, + .voltage = 0, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 3 + .atclk_div = 3 }, { .name = "", 0 } } }, { - .package = CPU_PKG_8086, - .manufacturer = "NEC", - .name = "V30", + .package = CPU_PKG_8086, + .manufacturer = "NEC", + .name = "V30", .internal_name = "necv30", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "5", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 5000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "5", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 5000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "8", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "8", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "10", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "10", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 12000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "12", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 12000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "16", - .cpu_type = CPU_V30, - .fpus = fpus_80186, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 0, - .mem_write_cycles = 0, - .cache_read_cycles = 0, + .name = "16", + .cpu_type = CPU_V30, + .fpus = fpus_80186, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 0, + .mem_write_cycles = 0, + .cache_read_cycles = 0, .cache_write_cycles = 0, - .atclk_div = 2 + .atclk_div = 2 }, { .name = "", 0 } } }, { - .package = CPU_PKG_286, - .manufacturer = "Intel", - .name = "80286", + .package = CPU_PKG_286, + .manufacturer = "Intel", + .name = "80286", .internal_name = "286", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "6", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 6000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 2, - .mem_write_cycles = 2, - .cache_read_cycles = 2, + .name = "6", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 6000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 2, + .mem_write_cycles = 2, + .cache_read_cycles = 2, .cache_write_cycles = 2, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "8", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 8000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 2, - .mem_write_cycles = 2, - .cache_read_cycles = 2, + .name = "8", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 8000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 2, + .mem_write_cycles = 2, + .cache_read_cycles = 2, .cache_write_cycles = 2, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "10", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 10000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 2, - .mem_write_cycles = 2, - .cache_read_cycles = 2, + .name = "10", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 10000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 2, + .mem_write_cycles = 2, + .cache_read_cycles = 2, .cache_write_cycles = 2, - .atclk_div = 1 + .atclk_div = 1 }, { - .name = "12", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 12500000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "12", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 12500000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "16", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 4, + .name = "20", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_286, - .fpus = fpus_80286, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 4, + .name = "25", + .cpu_type = CPU_286, + .fpus = fpus_80286, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 3 + .atclk_div = 3 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386SX, - .manufacturer = "Intel", - .name = "i386SX", + .package = CPU_PKG_386SX, + .manufacturer = "Intel", + .name = "i386SX", .internal_name = "i386sx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "16", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386SX, - .manufacturer = "AMD", - .name = "Am386SX", + .package = CPU_PKG_386SX, + .manufacturer = "AMD", + .name = "Am386SX", .internal_name = "am386sx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "16", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_386SX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_386SX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386DX, - .manufacturer = "Intel", - .name = "i386DX", + .package = CPU_PKG_386DX, + .manufacturer = "Intel", + .name = "i386DX", .internal_name = "i386dx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "16", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386DX_DESKPRO386, - .manufacturer = "Intel", - .name = "i386DX", + .package = CPU_PKG_386DX_DESKPRO386, + .manufacturer = "Intel", + .name = "i386DX", .internal_name = "i386dx_deskpro386", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "16", - .cpu_type = CPU_386DX, - .fpus = fpus_80286, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_386DX, + .fpus = fpus_80286, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386DX, - .manufacturer = "Intel", - .name = "RapidCAD", + .package = CPU_PKG_386DX, + .manufacturer = "Intel", + .name = "RapidCAD", .internal_name = "rapidcad", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "25", - .cpu_type = CPU_RAPIDCAD, - .fpus = fpus_internal, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0340, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_RAPIDCAD, + .fpus = fpus_internal, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0340, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_RAPIDCAD, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0340, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_RAPIDCAD, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0340, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_RAPIDCAD, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0340, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_RAPIDCAD, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0340, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386DX, - .manufacturer = "AMD", - .name = "Am386DX", + .package = CPU_PKG_386DX, + .manufacturer = "AMD", + .name = "Am386DX", .internal_name = "am386dx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "25", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_386DX, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x0308, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_386DX, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x0308, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_M6117, - .manufacturer = "ALi", - .name = "M6117", + .package = CPU_PKG_M6117, + .manufacturer = "ALi", + .name = "M6117", .internal_name = "m6117", - .cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */ + .cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */ { - .name = "33", - .cpu_type = CPU_386SX, - .fpus = fpus_none, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2309, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_386SX, + .fpus = fpus_none, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2309, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_386SX, - .fpus = fpus_none, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x2309, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_386SX, + .fpus = fpus_none, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x2309, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386SLC_IBM, - .manufacturer = "IBM", - .name = "386SLC", + .package = CPU_PKG_386SLC_IBM, + .manufacturer = "IBM", + .name = "386SLC", .internal_name = "ibm386slc", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "16", - .cpu_type = CPU_IBM386SLC, - .fpus = fpus_80386, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA301, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_IBM386SLC, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA301, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_IBM386SLC, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA301, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_IBM386SLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA301, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386SX, - .manufacturer = "Cyrix", - .name = "Cx486SLC", + .package = CPU_PKG_386SX, + .manufacturer = "Cyrix", + .name = "Cx486SLC", .internal_name = "cx486slc", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "20", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x400, - .cpuid_model = 0, - .cyrix_id = 0x0000, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x400, - .cpuid_model = 0, - .cyrix_id = 0x0000, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x400, - .cpuid_model = 0, - .cyrix_id = 0x0000, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x400, + .cpuid_model = 0, + .cyrix_id = 0x0000, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386SX, - .manufacturer = "Cyrix", - .name = "Cx486SRx2", + .package = CPU_PKG_386SX, + .manufacturer = "Cyrix", + .name = "Cx486SRx2", .internal_name = "cx486srx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "32", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 32000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x406, - .cpuid_model = 0, - .cyrix_id = 0x0006, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 6, + .name = "32", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 32000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x406, - .cpuid_model = 0, - .cyrix_id = 0x0006, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "40", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "50", - .cpu_type = CPU_486SLC, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x406, - .cpuid_model = 0, - .cyrix_id = 0x0006, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_486SLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x406, + .cpuid_model = 0, + .cyrix_id = 0x0006, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { .name = "", 0 } } }, { - .package = CPU_PKG_486SLC_IBM, - .manufacturer = "IBM", - .name = "486SLC", + .package = CPU_PKG_486SLC_IBM, + .manufacturer = "IBM", + .name = "486SLC", .internal_name = "ibm486slc", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "33", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0xA401, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0xA401, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { .name = "", 0 } } }, { - .package = CPU_PKG_486SLC_IBM, - .manufacturer = "IBM", - .name = "486SLC2", + .package = CPU_PKG_486SLC_IBM, + .manufacturer = "IBM", + .name = "486SLC2", .internal_name = "ibm486slc2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "40", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA421, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 6, + .name = "40", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 5 + .atclk_div = 5 }, { - .name = "50", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA421, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0xA421, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0xA421, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_486SLC_IBM, - .manufacturer = "IBM", - .name = "486SLC3", + .package = CPU_PKG_486SLC_IBM, + .manufacturer = "IBM", + .name = "486SLC3", .internal_name = "ibm486slc3", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "60", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 60000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, + .name = "60", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 60000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 7 + .atclk_div = 7 }, { - .name = "75", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 75000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, + .name = "75", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 75000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "100", - .cpu_type = CPU_IBM486SLC, - .fpus = fpus_80386, - .rspeed = 100000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0xA439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_IBM486SLC, + .fpus = fpus_80386, + .rspeed = 100000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0xA439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { .name = "", 0 } } }, { - .package = CPU_PKG_486BL, - .manufacturer = "IBM", - .name = "486BL2", + .package = CPU_PKG_486BL, + .manufacturer = "IBM", + .name = "486BL2", .internal_name = "ibm486bl2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x8439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x8439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x8439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x8439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_486BL, - .manufacturer = "IBM", - .name = "486BL3", + .package = CPU_PKG_486BL, + .manufacturer = "IBM", + .name = "486BL3", .internal_name = "ibm486bl3", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 75000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0x8439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, + .name = "75", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 75000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0x8439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "100", - .cpu_type = CPU_IBM486BL, - .fpus = fpus_80386, - .rspeed = 100000000, - .multi = 3, - .voltage = 5000, - .edx_reset = 0x8439, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = 0, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_IBM486BL, + .fpus = fpus_80386, + .rspeed = 100000000, + .multi = 3, + .voltage = 5000, + .edx_reset = 0x8439, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = 0, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386DX, - .manufacturer = "Cyrix", - .name = "Cx486DLC", + .package = CPU_PKG_386DX, + .manufacturer = "Cyrix", + .name = "Cx486DLC", .internal_name = "cx486dlc", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "25", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x401, - .cpuid_model = 0, - .cyrix_id = 0x0001, - .cpu_flags = 0, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x401, + .cpuid_model = 0, + .cyrix_id = 0x0001, + .cpu_flags = 0, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x401, - .cpuid_model = 0, - .cyrix_id = 0x0001, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x401, + .cpuid_model = 0, + .cyrix_id = 0x0001, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x401, - .cpuid_model = 0, - .cyrix_id = 0x0001, - .cpu_flags = 0, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x401, + .cpuid_model = 0, + .cyrix_id = 0x0001, + .cpu_flags = 0, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_386DX, - .manufacturer = "Cyrix", - .name = "Cx486DRx2", + .package = CPU_PKG_386DX, + .manufacturer = "Cyrix", + .name = "Cx486DRx2", .internal_name = "cx486drx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "32", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 32000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 6, + .name = "32", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 32000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "40", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "50", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_486DLC, - .fpus = fpus_80386, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x407, - .cpuid_model = 0, - .cyrix_id = 0x0007, - .cpu_flags = 0, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_486DLC, + .fpus = fpus_80386, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x407, + .cpuid_model = 0, + .cyrix_id = 0x0007, + .cpu_flags = 0, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486SX", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX", .internal_name = "i486sx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "16", - .cpu_type = CPU_i486SX, - .fpus = fpus_486sx, - .rspeed = 16000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x420, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 3, - .mem_write_cycles = 3, - .cache_read_cycles = 3, + .name = "16", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 2 + .atclk_div = 2 }, { - .name = "20", - .cpu_type = CPU_i486SX, - .fpus = fpus_486sx, - .rspeed = 20000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x420, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "20", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "25", - .cpu_type = CPU_i486SX, - .fpus = fpus_486sx, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x422, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_i486SX, - .fpus = fpus_486sx, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x422, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486SX-S", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX-S", .internal_name = "i486sx_slenh", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "25", - .cpu_type = CPU_i486SX_SLENH, - .fpus = fpus_486sx, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x423, - .cpuid_model = 0x423, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x423, + .cpuid_model = 0x423, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_i486SX_SLENH, - .fpus = fpus_486sx, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x42a, - .cpuid_model = 0x42a, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x42a, + .cpuid_model = 0x42a, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486SX2", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX2", .internal_name = "i486sx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_i486SX_SLENH, - .fpus = fpus_486sx, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x45b, - .cpuid_model = 0x45b, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0x45b, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66 (Q0569)", - .cpu_type = CPU_i486SX_SLENH, - .fpus = fpus_486sx, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x45b, - .cpuid_model = 0x45b, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "66 (Q0569)", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0x45b, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX", .internal_name = "i486dx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "25", - .cpu_type = CPU_i486DX, - .fpus = fpus_internal, - .rspeed = 25000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x404, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x404, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_i486DX, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x404, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x404, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "50", - .cpu_type = CPU_i486DX, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x411, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 4, + .name = "50", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x411, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 6 + .atclk_div = 6 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX-S", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX-S", .internal_name = "i486dx_slenh", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "33", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x414, - .cpuid_model = 0x414, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x414, + .cpuid_model = 0x414, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "50", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x414, - .cpuid_model = 0x414, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 4, + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x414, + .cpuid_model = 0x414, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 6 + .atclk_div = 6 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX2", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX2", .internal_name = "i486dx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "40", - .cpu_type = CPU_i486DX, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 6, + .name = "40", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 5 + .atclk_div = 5 }, { - .name = "50", - .cpu_type = CPU_i486DX, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x433, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x433, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_i486DX, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x433, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x433, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "i486DX2-S", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX2-S", .internal_name = "i486dx2_slenh", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "40", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x435, - .cpuid_model = 0x435, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 6, + .name = "40", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 5 + .atclk_div = 5 }, { - .name = "50", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x435, - .cpuid_model = 0x435, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x435, - .cpuid_model = 0x435, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, - .manufacturer = "Intel", - .name = "i486DX2 WB", + .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, + .manufacturer = "Intel", + .name = "i486DX2 WB", .internal_name = "i486dx2_pc330", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x436, - .cpuid_model = 0x436, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x436, + .cpuid_model = 0x436, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x436, - .cpuid_model = 0x436, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x436, + .cpuid_model = 0x436, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, - { - .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. They are functionally identical*/ - .manufacturer = "Intel", - .name = "iDX4", + { /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. They are functionally identical*/ + .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, + .manufacturer = "Intel", + .name = "iDX4", .internal_name = "idx4", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0x480, - .cyrix_id = 0x0000, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, + .name = "75", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0x480, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "100", - .cpu_type = CPU_i486DX_SLENH, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x483, - .cpuid_model = 0x483, - .cyrix_id = 0x0000, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x483, + .cpuid_model = 0x483, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3 | CPU_PKG_SOCKET3_PC330, - .manufacturer = "Intel", - .name = "Pentium OverDrive", + .package = CPU_PKG_SOCKET3 | CPU_PKG_SOCKET3_PC330, + .manufacturer = "Intel", + .name = "Pentium OverDrive", .internal_name = "pentium_p24t", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "63", - .cpu_type = CPU_P24T, - .fpus = fpus_internal, - .rspeed = 62500000, - .multi = 2.5, - .voltage = 5000, - .edx_reset = 0x1531, - .cpuid_model = 0x1531, - .cyrix_id = 0x0000, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 10, - .mem_write_cycles = 10, - .cache_read_cycles = 7, + .name = "63", + .cpu_type = CPU_P24T, + .fpus = fpus_internal, + .rspeed = 62500000, + .multi = 2.5, + .voltage = 5000, + .edx_reset = 0x1531, + .cpuid_model = 0x1531, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 15/2 + .atclk_div = 15/2 }, { - .name = "83", - .cpu_type = CPU_P24T, - .fpus = fpus_internal, - .rspeed = 83333333, - .multi = 2.5, - .voltage = 5000, - .edx_reset = 0x1532, - .cpuid_model = 0x1532, - .cyrix_id = 0x0000, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 8, + .name = "83", + .cpu_type = CPU_P24T, + .fpus = fpus_internal, + .rspeed = 83333333, + .multi = 2.5, + .voltage = 5000, + .edx_reset = 0x1532, + .cpuid_model = 0x1532, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 8, .cache_write_cycles = 8, - .atclk_div = 10 + .atclk_div = 10 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486SX", + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486SX", .internal_name = "am486sx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "33", - .cpu_type = CPU_Am486SX, - .fpus = fpus_486sx, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x422, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_Am486SX, - .fpus = fpus_486sx, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x422, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486SX2", + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486SX2", .internal_name = "am486sx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_Am486SX, - .fpus = fpus_486sx, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x45b, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_Am486SX, - .fpus = fpus_486sx, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x45b, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DX", + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DX", .internal_name = "am486dx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "33", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x412, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x412, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x412, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x412, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DX2", + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DX2", .internal_name = "am486dx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { - .name = "80", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 80000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 6, + .name = "80", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DXL", + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DXL", .internal_name = "am486dxl", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "33", - .cpu_type = CPU_Am486DXL, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x422, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_Am486DXL, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x422, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "AMD", - .name = "Am486DXL2", + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DXL2", .internal_name = "am486dxl2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_Am486DXL, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_Am486DXL, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { - .name = "80", - .cpu_type = CPU_Am486DXL, - .fpus = fpus_internal, - .rspeed = 80000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 6, + .name = "80", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am486DX4", + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX4", .internal_name = "am486dx4", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, + .name = "75", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "90", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 90000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 9, + .name = "90", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "100", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "120", - .cpu_type = CPU_Am486DX, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x432, - .cpuid_model = 0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 9, + .name = "120", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 15 + .atclk_div = 15 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am486DX2 (Enhanced)", + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX2 (Enhanced)", .internal_name = "am486dx2_slenh", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "66", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x435, - .cpuid_model = 0x435, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { - .name = "80", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 80000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x435, - .cpuid_model = 0x435, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 6, + .name = "80", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am486DX4 (Enhanced)", + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX4 (Enhanced)", .internal_name = "am486dx4_slenh", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x482, - .cpuid_model = 0x482, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, + .name = "75", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "100", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x482, - .cpuid_model = 0x482, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "120", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x482, - .cpuid_model = 0x482, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 9, + .name = "120", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 15 + .atclk_div = 15 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "AMD", - .name = "Am5x86", + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am5x86", .internal_name = "am5x86", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "133 (P75)", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 4.0, - .voltage = 5000, - .edx_reset = 0x4e0, - .cpuid_model = 0x4e0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "133 (P75)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x4e0, + .cpuid_model = 0x4e0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 16 + .atclk_div = 16 }, { /*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - .name = "150 (P75+)", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x482, - .cpuid_model = 0x482, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 28, - .mem_write_cycles = 28, - .cache_read_cycles = 12, + .name = "150 (P75+)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 28, + .mem_write_cycles = 28, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 20 + .atclk_div = 20 }, { /*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ - .name = "160 (P90)", - .cpu_type = CPU_ENH_Am486DX, - .fpus = fpus_internal, - .rspeed = 160000000, - .multi = 4.0, - .voltage = 5000, - .edx_reset = 0x4e0, - .cpuid_model = 0x4e0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 28, - .mem_write_cycles = 28, - .cache_read_cycles = 12, + .name = "160 (P90)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 160000000, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x4e0, + .cpuid_model = 0x4e0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 28, + .mem_write_cycles = 28, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 20 + .atclk_div = 20 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Cyrix", - .name = "Cx486S", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Cyrix", + .name = "Cx486S", .internal_name = "cx486s", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "25", - .cpu_type = CPU_Cx486S, - .fpus = fpus_486sx, - .rspeed = 25000000, - .multi = 1.0, - .voltage = 5000, - .edx_reset = 0x420, - .cpuid_model = 0, - .cyrix_id = 0x0010, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "25", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 3 + .atclk_div = 3 }, { - .name = "33", - .cpu_type = CPU_Cx486S, - .fpus = fpus_486sx, - .rspeed = 33333333, - .multi = 1.0, - .voltage = 5000, - .edx_reset = 0x420, - .cpuid_model = 0, - .cyrix_id = 0x0010, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_Cx486S, - .fpus = fpus_486sx, - .rspeed = 40000000, - .multi = 1.0, - .voltage = 5000, - .edx_reset = 0x420, - .cpuid_model = 0, - .cyrix_id = 0x0010, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 40000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Cyrix", - .name = "Cx486DX", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Cyrix", + .name = "Cx486DX", .internal_name = "cx486dx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "33", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 33333333, - .multi = 1.0, - .voltage = 5000, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x051a, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "33", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 4 + .atclk_div = 4 }, { - .name = "40", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 40000000, - .multi = 1.0, - .voltage = 5000, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x051a, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "40", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Cyrix", - .name = "Cx486DX2", + .package = CPU_PKG_SOCKET1, + .manufacturer = "Cyrix", + .name = "Cx486DX2", .internal_name = "cx486dx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 2.0, - .voltage = 5000, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x081b, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "50", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x081b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "66", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 2.0, - .voltage = 5000, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x0b1b, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x0b1b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { - .name = "80", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 80000000, - .multi = 2.0, - .voltage = 5000, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x311b, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 6, + .name = "80", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x311b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "Cyrix", - .name = "Cx486DX4", + .package = CPU_PKG_SOCKET3, + .manufacturer = "Cyrix", + .name = "Cx486DX4", .internal_name = "cx486dx4", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0, - .cyrix_id = 0x361f, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 9 + .name = "75", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x361f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 }, { - .name = "100", - .cpu_type = CPU_Cx486DX, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0, - .cyrix_id = 0x361f, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 12 + .name = "100", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x361f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET3, - .manufacturer = "Cyrix", - .name = "Cx5x86", + .package = CPU_PKG_SOCKET3, + .manufacturer = "Cyrix", + .name = "Cx5x86", .internal_name = "cx5x86", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /*If we're including the Pentium 50, might as well include this*/ - .name = "80", - .cpu_type = CPU_Cx5x86, - .fpus = fpus_internal, - .rspeed = 80000000, - .multi = 2.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0, - .cyrix_id = 0x002f, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 6, + .name = "80", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { - .name = "100", - .cpu_type = CPU_Cx5x86, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0, - .cyrix_id = 0x002f, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "120", - .cpu_type = CPU_Cx5x86, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 3.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0, - .cyrix_id = 0x002f, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 9, + .name = "120", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 15 + .atclk_div = 15 }, { - .name = "133", - .cpu_type = CPU_Cx5x86, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 4.0, - .voltage = 5000, - .edx_reset = 0x480, - .cpuid_model = 0, - .cyrix_id = 0x002f, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "133", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 16 + .atclk_div = 16 }, { .name = "", 0 } } }, { - .package = CPU_PKG_STPC, - .manufacturer = "ST", - .name = "STPC-DX", + .package = CPU_PKG_STPC, + .manufacturer = "ST", + .name = "STPC-DX", .internal_name = "stpc_dx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "66", - .cpu_type = CPU_STPC, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 3300, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x051a, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "66", + .cpu_type = CPU_STPC, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { - .name = "75", - .cpu_type = CPU_STPC, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 1.0, - .voltage = 3300, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x051a, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 3, + .name = "75", + .cpu_type = CPU_STPC, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 5 + .atclk_div = 5 }, { .name = "", 0 } } }, { - .package = CPU_PKG_STPC, - .manufacturer = "ST", - .name = "STPC-DX2", + .package = CPU_PKG_STPC, + .manufacturer = "ST", + .name = "STPC-DX2", .internal_name = "stpc_dx2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "133", - .cpu_type = CPU_STPC, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3300, - .edx_reset = 0x430, - .cpuid_model = 0, - .cyrix_id = 0x0b1b, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_STPC, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3300, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x0b1b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET4, - .manufacturer = "Intel", - .name = "Pentium", + .package = CPU_PKG_SOCKET4, + .manufacturer = "Intel", + .name = "Pentium", .internal_name = "pentium_p5", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "50 (Q0399)", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 50000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x513, - .cpuid_model = 0x513, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 4, - .mem_write_cycles = 4, - .cache_read_cycles = 3, + .name = "50 (Q0399)", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x513, + .cpuid_model = 0x513, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 6 + .atclk_div = 6 }, { - .name = "60", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 60000000, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x517, - .cpuid_model = 0x517, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "60", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 60000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x517, + .cpuid_model = 0x517, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 7 + .atclk_div = 7 }, { - .name = "66", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1, - .voltage = 5000, - .edx_reset = 0x517, - .cpuid_model = 0x517, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "66", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x517, + .cpuid_model = 0x517, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 8 + .atclk_div = 8 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET4, - .manufacturer = "Intel", - .name = "Pentium OverDrive", + .package = CPU_PKG_SOCKET4, + .manufacturer = "Intel", + .name = "Pentium OverDrive", .internal_name = "pentium_p54c_od5v", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "100", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x51A, - .cpuid_model = 0x51A, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "100", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x51A, + .cpuid_model = 0x51A, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "120", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x51A, - .cpuid_model = 0x51A, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "120", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x51A, + .cpuid_model = 0x51A, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "133", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2, - .voltage = 5000, - .edx_reset = 0x51A, - .cpuid_model = 0x51A, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x51A, + .cpuid_model = 0x51A, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium", .internal_name = "pentium_p54c", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x522, - .cpuid_model = 0x522, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 4, + .name = "75", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x522, + .cpuid_model = 0x522, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "90", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 90000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x524, - .cpuid_model = 0x524, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "90", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 21/2 + .atclk_div = 21/2 }, { - .name = "100/50", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x524, - .cpuid_model = 0x524, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 10, - .mem_write_cycles = 10, - .cache_read_cycles = 6, + .name = "100/50", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "100/66", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x526, - .cpuid_model = 0x526, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100/66", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x526, + .cpuid_model = 0x526, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "120", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x526, - .cpuid_model = 0x526, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "120", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x526, + .cpuid_model = 0x526, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "133", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "150", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "150", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "166", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "200", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium MMX", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium MMX", .internal_name = "pentium_p55c", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "166", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2800, - .edx_reset = 0x543, - .cpuid_model = 0x543, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "200", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2800, - .edx_reset = 0x543, - .cpuid_model = 0x543, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "233", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2800, - .edx_reset = 0x543, - .cpuid_model = 0x543, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Mobile Pentium MMX", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Mobile Pentium MMX", .internal_name = "pentium_tillamook", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "120", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x543, - .cpuid_model = 0x543, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "120", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "133", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x543, - .cpuid_model = 0x543, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "150", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 2800, - .edx_reset = 0x544, - .cpuid_model = 0x544, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "150", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x544, + .cpuid_model = 0x544, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "166", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2800, - .edx_reset = 0x544, - .cpuid_model = 0x544, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x544, + .cpuid_model = 0x544, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "200", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2800, - .edx_reset = 0x581, - .cpuid_model = 0x581, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x581, + .cpuid_model = 0x581, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "233", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2800, - .edx_reset = 0x581, - .cpuid_model = 0x581, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x581, + .cpuid_model = 0x581, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "266", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2800, - .edx_reset = 0x582, - .cpuid_model = 0x582, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2800, + .edx_reset = 0x582, + .cpuid_model = 0x582, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2800, - .edx_reset = 0x582, - .cpuid_model = 0x582, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, + .name = "300", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2800, + .edx_reset = 0x582, + .cpuid_model = 0x582, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, .cache_write_cycles = 13, - .atclk_div = 36 + .atclk_div = 36 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium OverDrive", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium OverDrive", .internal_name = "pentium_p54c_od3v", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "125", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 125000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 7, + .name = "125", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 125000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 15 + .atclk_div = 15 }, { - .name = "150", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "150", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "166", - .cpu_type = CPU_PENTIUM, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x52c, - .cpuid_model = 0x52c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Intel", - .name = "Pentium OverDrive MMX", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Intel", + .name = "Pentium OverDrive MMX", .internal_name = "pentium_p55c_od", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 1.5, - .voltage = 3520, .edx_reset = 0x1542, .cpuid_model = 0x1542, .cyrix_id = 0, .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, .mem_read_cycles = 7, .mem_write_cycles = 7,.cache_read_cycles = 4,.cache_write_cycles = 4, .atclk_div = 9}, + .name = "75", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, { - .name = "125", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 125000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x1542, - .cpuid_model = 0x1542, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 7, + .name = "125", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 125000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 15 + .atclk_div = 15 }, { - .name = "150/60", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x1542, - .cpuid_model = 0x1542, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "150/60", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "166", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 166000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x1542, - .cpuid_model = 0x1542, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "180", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 180000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x1542, - .cpuid_model = 0x1542, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "180", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 21 + .atclk_div = 21 }, { - .name = "200", - .cpu_type = CPU_PENTIUMMMX, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x1542, - .cpuid_model = 0x1542, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "IDT", - .name = "WinChip", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "IDT", + .name = "WinChip", .internal_name = "winchip", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 4, + .name = "75", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "90", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 90000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "90", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 21/2 + .atclk_div = 21/2 }, { - .name = "100", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "120", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "120", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "133", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "150", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "150", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "166", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 40 + .atclk_div = 40 }, { - .name = "180", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 180000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "180", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 21 + .atclk_div = 21 }, { - .name = "200", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "225", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 225000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "225", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 225000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 27 + .atclk_div = 27 }, { - .name = "240", - .cpu_type = CPU_WINCHIP, - .fpus = fpus_internal, - .rspeed = 240000000, - .multi = 4.0, - .voltage = 3520, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "240", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 240000000, + .multi = 4.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 28 + .atclk_div = 28 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "IDT", - .name = "WinChip 2", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "IDT", + .name = "WinChip 2", .internal_name = "winchip2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "200", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 3*8 + .atclk_div = 3*8 }, { - .name = "225", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 225000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "225", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 225000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 3*9 + .atclk_div = 3*9 }, { - .name = "240", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 240000000, - .multi = 4.0, - .voltage = 3520, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "240", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 240000000, + .multi = 4.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 30 + .atclk_div = 30 }, { - .name = "250", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 250000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "250", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 30 + .atclk_div = 30 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "IDT", - .name = "WinChip 2A", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "IDT", + .name = "WinChip 2A", .internal_name = "winchip2a", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "200", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x587, - .cpuid_model = 0x587, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 3*8 + .atclk_div = 3*8 }, { - .name = "233", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 3520, - .edx_reset = 0x587, - .cpuid_model = 0x587, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 9, + .name = "233", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = (7*8)/2 + .atclk_div = (7*8)/2 }, { - .name = "266", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 7.0/3.0, - .voltage = 3520, - .edx_reset = 0x587, - .cpuid_model = 0x587, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 7, + .name = "266", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 7.0/3.0, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "300", - .cpu_type = CPU_WINCHIP2, - .fpus = fpus_internal, - .rspeed = 250000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x587, - .cpuid_model = 0x587, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 8, + .name = "300", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 8, .cache_write_cycles = 8, - .atclk_div = 30 + .atclk_div = 30 }, { .name = "", 0 } } }, #if defined(DEV_BRANCH) && defined(USE_AMD_K5) { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K5 (Model 0)", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K5 (Model 0)", .internal_name = "k5_ssa5", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "75 (PR75)", - .cpu_type = CPU_K5, - .fpus = fpus_internal, - .rspeed = 75000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x501, - .cpuid_model = 0x501, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 4, + .name = "75 (PR75)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 9 + .atclk_div = 9 }, { - .name = "90 (PR90)", - .cpu_type = CPU_K5, - .fpus = fpus_internal, - .rspeed = 90000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x501, - .cpuid_model = 0x501, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "90 (PR90)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 21/2 + .atclk_div = 21/2 }, { - .name = "100 (PR100)", - .cpu_type = CPU_K5, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 3520, - .edx_reset = 0x501, - .cpuid_model = 0x501, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100 (PR100)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K5 (Model 1/2/3)", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K5 (Model 1/2/3)", .internal_name = "k5_5k86", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "90 (PR120)", - .cpu_type = CPU_5K86, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x511, - .cpuid_model = 0x511, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "90 (PR120)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x511, + .cpuid_model = 0x511, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "100 (PR133)", - .cpu_type = CPU_5K86, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x514, - .cpuid_model = 0x514, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "100 (PR133)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x514, + .cpuid_model = 0x514, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "105 (PR150)", - .cpu_type = CPU_5K86, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x524, - .cpuid_model = 0x524, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "105 (PR150)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "116.7 (PR166)", - .cpu_type = CPU_5K86, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 3520, - .edx_reset = 0x524, - .cpuid_model = 0x524, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "116.7 (PR166)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "133 (PR200)", - .cpu_type = CPU_5K86, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3520, - .edx_reset = 0x534, - .cpuid_model = 0x534, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "133 (PR200)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x534, + .cpuid_model = 0x534, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { .name = "", 0 } } }, #endif { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6 (Model 6)", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6 (Model 6)", .internal_name = "k6_m6", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "66", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 2900, - .edx_reset = 0x561, - .cpuid_model = 0x561, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "66", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 8 + .atclk_div = 8 }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2900, - .edx_reset = 0x561, - .cpuid_model = 0x561, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2900, - .edx_reset = 0x561, - .cpuid_model = 0x561, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "166", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2900, - .edx_reset = 0x561, - .cpuid_model = 0x561, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "200", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2900, - .edx_reset = 0x561, - .cpuid_model = 0x561, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "233", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 3200, - .edx_reset = 0x561, - .cpuid_model = 0x561, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3200, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6 (Model 7)", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6 (Model 7)", .internal_name = "k6_m7", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "100", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2200, - .edx_reset = 0x570, - .cpuid_model = 0x570, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2200, - .edx_reset = 0x570, - .cpuid_model = 0x570, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 166666666, .multi = 2.5, - .voltage = 2200, .edx_reset = 0x570, - .cpuid_model = 0x570, .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 166666666, .multi = 2.5, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "200", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 200000000, .multi = 3.0, - .voltage = 2200, .edx_reset = 0x570, - .cpuid_model = 0x570, .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 200000000, .multi = 3.0, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "233", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 233333333, .multi = 3.5, - .voltage = 2200, .edx_reset = 0x570, - .cpuid_model = 0x570, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 233333333, .multi = 3.5, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "266", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x570, - .cpuid_model = 0x570, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_K6, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2200, - .edx_reset = 0x570, - .cpuid_model = 0x570, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, + .name = "300", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, .cache_write_cycles = 13, - .atclk_div = 36 + .atclk_div = 36 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-2", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-2", .internal_name = "k6_2", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "100", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "233", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "266", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 3.0, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "300", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 36 + .atclk_div = 36 }, { - .name = "333", - .cpu_type = CPU_K6_2, - .fpus = fpus_internal, - .rspeed = 332500000, - .multi = 3.5, - .voltage = 2200, - .edx_reset = 0x580, - .cpuid_model = 0x580, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 30, - .mem_write_cycles = 30, - .cache_read_cycles = 11, + .name = "333", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 40 + .atclk_div = 40 }, { - .name = "350", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 350000000, - .multi = 3.5, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 32, - .mem_write_cycles = 32, - .cache_read_cycles = 11, + .name = "350", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 42 + .atclk_div = 42 }, { - .name = "366", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 366666666, - .multi = 5.5, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 33, - .mem_write_cycles = 33, - .cache_read_cycles = 17, + .name = "366", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 44 + .atclk_div = 44 }, { - .name = "380", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 380000000, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 34, - .mem_write_cycles = 34, - .cache_read_cycles = 12, + .name = "380", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 46 + .atclk_div = 46 }, { - .name = "400/66", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 6.0, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400/66", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "400/100", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400/100", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "450", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, + .name = "450", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, .cache_write_cycles = 14, - .atclk_div = 54 + .atclk_div = 54 }, { - .name = "475", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 475000000, - .multi = 5.0, - .voltage = 2400, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 43, - .mem_write_cycles = 43, - .cache_read_cycles = 15, + .name = "475", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2400, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 57 + .atclk_div = 57 }, { - .name = "500", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 500000000, - .multi = 5.0, - .voltage = 2400, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 45, - .mem_write_cycles = 45, - .cache_read_cycles = 15, + .name = "500", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2400, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 60 + .atclk_div = 60 }, { - .name = "533", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 533333333, - .multi = 5.5, - .voltage = 2200, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 48, - .mem_write_cycles = 48, - .cache_read_cycles = 17, + .name = "533", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 64 + .atclk_div = 64 }, { - .name = "550", - .cpu_type = CPU_K6_2C, - .fpus = fpus_internal, - .rspeed = 550000000, - .multi = 5.5, - .voltage = 2300, - .edx_reset = 0x58c, - .cpuid_model = 0x58c, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 50, - .mem_write_cycles = 50, - .cache_read_cycles = 17, + .name = "550", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2300, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 66 + .atclk_div = 66 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-2+", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-2+", .internal_name = "k6_2p", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "100", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { /* out of spec */ - .name = "266", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { /* out of spec */ - .name = "300", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 3.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "300", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 36 + .atclk_div = 36 }, { /* out of spec */ - .name = "333", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 332500000, - .multi = 3.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 30, - .mem_write_cycles = 30, - .cache_read_cycles = 11, + .name = "333", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 40 + .atclk_div = 40 }, { /* out of spec */ - .name = "350", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 350000000, - .multi = 3.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 32, - .mem_write_cycles = 32, - .cache_read_cycles = 11, + .name = "350", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 42 + .atclk_div = 42 }, { /* out of spec */ - .name = "366", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 366666666, - .multi = 5.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 33, - .mem_write_cycles = 33, - .cache_read_cycles = 17, + .name = "366", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 44 + .atclk_div = 44 }, { /* out of spec */ - .name = "380", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 380000000, - .multi = 4.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 34, - .mem_write_cycles = 34, - .cache_read_cycles = 12, + .name = "380", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 46 + .atclk_div = 46 }, { /* out of spec */ - .name = "400/66", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 6.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400/66", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { /* out of spec */ - .name = "400/100", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 4.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400/100", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "450", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, + .name = "450", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, .cache_write_cycles = 14, - .atclk_div = 54 + .atclk_div = 54 }, { - .name = "475", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 475000000, - .multi = 5.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 43, - .mem_write_cycles = 43, - .cache_read_cycles = 15, + .name = "475", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 57 + .atclk_div = 57 }, { - .name = "500", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 500000000, - .multi = 5.0, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 45, - .mem_write_cycles = 45, - .cache_read_cycles = 15, + .name = "500", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 60 + .atclk_div = 60 }, { - .name = "533", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 533333333, - .multi = 5.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 48, - .mem_write_cycles = 48, - .cache_read_cycles = 17, + .name = "533", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 64 + .atclk_div = 64 }, { - .name = "550", - .cpu_type = CPU_K6_2P, - .fpus = fpus_internal, - .rspeed = 550000000, - .multi = 5.5, - .voltage = 2000, - .edx_reset = 0x5d4, - .cpuid_model = 0x5d4, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 50, - .mem_write_cycles = 50, - .cache_read_cycles = 17, + .name = "550", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 66 + .atclk_div = 66 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-III", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-III", .internal_name = "k6_3", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "100", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { /* out of spec */ - .name = "266", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { /* out of spec */ - .name = "300", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 3.0, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "300", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 36 + .atclk_div = 36 }, { /* out of spec */ - .name = "333", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 332500000, - .multi = 3.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 30, - .mem_write_cycles = 30, - .cache_read_cycles = 11, + .name = "333", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 40 + .atclk_div = 40 }, { /* out of spec */ - .name = "350", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 350000000, - .multi = 3.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 32, - .mem_write_cycles = 32, - .cache_read_cycles = 11, + .name = "350", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 42 + .atclk_div = 42 }, { /* out of spec */ - .name = "366", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 366666666, - .multi = 5.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 33, - .mem_write_cycles = 33, - .cache_read_cycles = 17, + .name = "366", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 44 + .atclk_div = 44 }, { /* out of spec */ - .name = "380", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 380000000, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 34, - .mem_write_cycles = 34, - .cache_read_cycles = 12, + .name = "380", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 46 + .atclk_div = 46 }, { - .name = "400", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 4.0, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "450", - .cpu_type = CPU_K6_3, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2200, - .edx_reset = 0x591, - .cpuid_model = 0x591, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, + .name = "450", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, .cache_write_cycles = 14, - .atclk_div = 54 + .atclk_div = 54 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "AMD", - .name = "K6-III+", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "AMD", + .name = "K6-III+", .internal_name = "k6_3p", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "100", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 7, - .mem_write_cycles = 7, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 9 + .atclk_div = 9 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { /* out of spec */ - .name = "266", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { /* out of spec */ - .name = "300", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 3.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "300", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 36 + .atclk_div = 36 }, { /* out of spec */ - .name = "333", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 332500000, - .multi = 3.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 30, - .mem_write_cycles = 30, - .cache_read_cycles = 11, + .name = "333", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 40 + .atclk_div = 40 }, { /* out of spec */ - .name = "350", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 350000000, - .multi = 3.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 32, - .mem_write_cycles = 32, - .cache_read_cycles = 11, + .name = "350", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 42 + .atclk_div = 42 }, { /* out of spec */ - .name = "366", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 366666666, - .multi = 5.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 33, - .mem_write_cycles = 33, - .cache_read_cycles = 17, + .name = "366", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, .cache_write_cycles = 17, - .atclk_div = 44 + .atclk_div = 44 }, { /* out of spec */ - .name = "380", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 380000000, - .multi = 4.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 34, - .mem_write_cycles = 34, - .cache_read_cycles = 12, + .name = "380", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 46 + .atclk_div = 46 }, { - .name = "400", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 4.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "450", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, + .name = "450", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, .cache_write_cycles = 14, - .atclk_div = 54 + .atclk_div = 54 }, { - .name = "475", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 475000000, - .multi = 5.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 43, - .mem_write_cycles = 43, - .cache_read_cycles = 15, + .name = "475", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 57 + .atclk_div = 57 }, { - .name = "500", - .cpu_type = CPU_K6_3P, - .fpus = fpus_internal, - .rspeed = 500000000, - .multi = 5.0, - .voltage = 2000, - .edx_reset = 0x5d0, - .cpuid_model = 0x5d0, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 45, - .mem_write_cycles = 45, - .cache_read_cycles = 15, + .name = "500", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 60 + .atclk_div = 60 }, { .name = "", 0 } } }, #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "Cx6x86", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "Cx6x86", .internal_name = "cx6x86", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "80 (PR90+)", - .cpu_type = CPU_Cx6x86, - .fpus = fpus_internal, - .rspeed = 80000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x520, - .cpuid_model = 0x520, - .cyrix_id = 0x1731, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 6, + .name = "80 (PR90+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 10 + .atclk_div = 10 }, { - .name = "100 (PR120+)", - .cpu_type = CPU_Cx6x86, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x520, - .cpuid_model = 0x520, - .cyrix_id = 0x1731, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 10, - .mem_write_cycles = 10, - .cache_read_cycles = 6, + .name = "100 (PR120+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 12 + .atclk_div = 12 }, { - .name = "110 (PR133+)", - .cpu_type = CPU_Cx6x86, - .fpus = fpus_internal, - .rspeed = 110000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x520, - .cpuid_model = 0x520, - .cyrix_id = 0x1731, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 10, - .mem_write_cycles = 10, - .cache_read_cycles = 6, + .name = "110 (PR133+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 110000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "120 (PR150+)", - .cpu_type = CPU_Cx6x86, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x520, - .cpuid_model = 0x520, - .cyrix_id = 0x1731, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "120 (PR150+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "133 (PR166+)", - .cpu_type = CPU_Cx6x86, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x520, - .cpuid_model = 0x520, - .cyrix_id = 0x1731, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133 (PR166+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "150 (PR200+)", - .cpu_type = CPU_Cx6x86, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.0, - .voltage = 3520, - .edx_reset = 0x520, - .cpuid_model = 0x520, - .cyrix_id = 0x1731, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "150 (PR200+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 18 + .atclk_div = 18 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "Cx6x86L", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "Cx6x86L", .internal_name = "cx6x86l", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "110 (PR133+)", - .cpu_type = CPU_Cx6x86L, - .fpus = fpus_internal, - .rspeed = 110000000, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0x2231, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 10, - .mem_write_cycles = 10, - .cache_read_cycles = 6, + .name = "110 (PR133+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 110000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "120 (PR150+)", - .cpu_type = CPU_Cx6x86L, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0x2231, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "120 (PR150+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 14 + .atclk_div = 14 }, { - .name = "133 (PR166+)", - .cpu_type = CPU_Cx6x86L, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0x2231, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133 (PR166+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "150 (PR200+)", - .cpu_type = CPU_Cx6x86L, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x540, - .cpuid_model = 0x540, - .cyrix_id = 0x2231, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "150 (PR200+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 18 + .atclk_div = 18 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "Cx6x86MX", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "Cx6x86MX", .internal_name = "cx6x86mx", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "133 (PR166)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2900, - .edx_reset = 0x600, - .cpuid_model = 0x600, - .cyrix_id = 0x0451, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133 (PR166)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0451, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { - .name = "166 (PR200)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2900, - .edx_reset = 0x600, - .cpuid_model = 0x600, - .cyrix_id = 0x0452, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166 (PR200)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "187.5 (PR233)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 187500000, - .multi = 2.5, - .voltage = 2900, - .edx_reset = 0x600, - .cpuid_model = 0x600, - .cyrix_id = 0x0452, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "187.5 (PR233)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 187500000, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 45/2 + .atclk_div = 45/2 }, { - .name = "208.3 (PR266)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 208333333, - .multi = 2.5, - .voltage = 2700, - .edx_reset = 0x600, - .cpuid_model = 0x600, - .cyrix_id = 0x0452, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 17, - .mem_write_cycles = 17, - .cache_read_cycles = 7, + .name = "208.3 (PR266)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 208333333, + .multi = 2.5, + .voltage = 2700, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 17, + .mem_write_cycles = 17, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 25 + .atclk_div = 25 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET5_7, - .manufacturer = "Cyrix", - .name = "MII", + .package = CPU_PKG_SOCKET5_7, + .manufacturer = "Cyrix", + .name = "MII", .internal_name = "mii", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { - .name = "233 (PR300)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2900, - .edx_reset = 0x601, - .cpuid_model = 0x601, - .cyrix_id = 0x0852, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 11, + .name = "233 (PR300)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0852, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "250/83 (PR333)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 250000000, - .multi = 3.0, - .voltage = 2900, - .edx_reset = 0x601, - .cpuid_model = 0x601, - .cyrix_id = 0x0853, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 23, - .mem_write_cycles = 23, - .cache_read_cycles = 9, + .name = "250/83 (PR333)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 23, + .mem_write_cycles = 23, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 30 + .atclk_div = 30 }, { - .name = "250/100 (PR366)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 250000000, - .multi = 2.5, - .voltage = 2900, - .edx_reset = 0x601, - .cpuid_model = 0x601, - .cyrix_id = 0x0853, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 23, - .mem_write_cycles = 23, - .cache_read_cycles = 7, + .name = "250/100 (PR366)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 23, + .mem_write_cycles = 23, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 30 + .atclk_div = 30 }, { - .name = "285 (PR400)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 285000000, - .multi = 3.0, - .voltage = 2900, - .edx_reset = 0x601, - .cpuid_model = 0x601, - .cyrix_id = 0x0853, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "285 (PR400)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 285000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 34 + .atclk_div = 34 }, { - .name = "300 (PR433)", - .cpu_type = CPU_Cx6x86MX, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 3.0, - .voltage = 2900, - .edx_reset = 0x601, - .cpuid_model = 0x601, - .cyrix_id = 0x0853, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "300 (PR433)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 36 + .atclk_div = 36 }, { .name = "", 0 } } }, #endif { - .package = CPU_PKG_SOCKET8, - .manufacturer = "Intel", - .name = "Pentium Pro", + .package = CPU_PKG_SOCKET8, + .manufacturer = "Intel", + .name = "Pentium Pro", .internal_name = "pentiumpro", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "60", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 60000000, - .multi = 1.0, - .voltage = 3100, - .edx_reset = 0x612, - .cpuid_model = 0x612, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 1, + .name = "60", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 60000000, + .multi = 1.0, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 1, .cache_write_cycles = 1, - .atclk_div = 7 + .atclk_div = 7 }, { /* out of spec */ - .name = "66", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 3300, - .edx_reset = 0x617, - .cpuid_model = 0x617, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 1, + .name = "66", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 1, .cache_write_cycles = 1, - .atclk_div = 8 + .atclk_div = 8 }, { /* out of spec */ - .name = "90", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 90000000, - .multi = 1.5, - .voltage = 3100, - .edx_reset = 0x612, - .cpuid_model = 0x612, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 3, + .name = "90", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 11 + .atclk_div = 11 }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 3300, - .edx_reset = 0x617, - .cpuid_model = 0x617, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 3, + .name = "100", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "120", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 120000000, - .multi = 2.0, - .voltage = 3100, - .edx_reset = 0x612, - .cpuid_model = 0x612, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 5, + .name = "120", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 5, .cache_write_cycles = 5, - .atclk_div = 14 + .atclk_div = 14 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3300, - .edx_reset = 0x617, - .cpuid_model = 0x617, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 5, + .name = "133", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 5, .cache_write_cycles = 5, - .atclk_div = 16 + .atclk_div = 16 }, /* out of spec */ { - .name = "150", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 2.5, - .voltage = 3100, - .edx_reset = 0x612, - .cpuid_model = 0x612, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "150", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3100, + .edx_reset = 0x612, + .cpuid_model = 0x612, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 35/2 + .atclk_div = 35/2 }, { - .name = "166", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 3300, - .edx_reset = 0x617, - .cpuid_model = 0x617, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { - .name = "180", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 180000000, - .multi = 3.0, - .voltage = 3300, - .edx_reset = 0x617, - .cpuid_model = 0x617, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "180", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 21 + .atclk_div = 21 }, { - .name = "200", - .cpu_type = CPU_PENTIUMPRO, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3300, - .edx_reset = 0x617, - .cpuid_model = 0x617, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUMPRO, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3300, + .edx_reset = 0x617, + .cpuid_model = 0x617, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET8, - .manufacturer = "Intel", - .name = "Pentium II OverDrive", + .package = CPU_PKG_SOCKET8, + .manufacturer = "Intel", + .name = "Pentium II OverDrive", .internal_name = "pentium2_od", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "66", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 8 + .atclk_div = 8 }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { /* out of spec */ - .name = "266", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 5.0, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 5.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, .cache_write_cycles = 13, - .atclk_div = 36 + .atclk_div = 36 }, { - .name = "333", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 333333333, - .multi = 5.0, - .voltage = 3300, - .edx_reset = 0x1632, - .cpuid_model = 0x1632, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, + .name = "333", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 3300, + .edx_reset = 0x1632, + .cpuid_model = 0x1632, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, .cache_write_cycles = 13, - .atclk_div = 40 + .atclk_div = 40 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SLOT1, - .manufacturer = "Intel", - .name = "Pentium II (Klamath)", + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Pentium II (Klamath)", .internal_name = "pentium2_klamath", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "66", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "66", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 8 + .atclk_div = 8 }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, + .name = "100", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { - .name = "233", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 10, + .name = "233", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "266", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_PENTIUM2, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2800, - .edx_reset = 0x634, - .cpuid_model = 0x634, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 25, - .mem_write_cycles = 25, - .cache_read_cycles = 12, + .name = "300", + .cpu_type = CPU_PENTIUM2, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2800, + .edx_reset = 0x634, + .cpuid_model = 0x634, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 36 + .atclk_div = 36 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SLOT1, - .manufacturer = "Intel", - .name = "Pentium II (Deschutes)", + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Pentium II (Deschutes)", .internal_name = "pentium2_deschutes", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "66", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 8 + .atclk_div = 8 }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 5, + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 5, .cache_write_cycles = 5, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 9, + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 11, + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "266", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x651, - .cpuid_model = 0x651, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 25, - .mem_write_cycles = 25, - .cache_read_cycles = 12, + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 36 + .atclk_div = 36 }, { - .name = "333", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 333333333, - .multi = 5.0, - .voltage = 2050, - .edx_reset = 0x651, - .cpuid_model = 0x651, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, + .name = "333", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, .cache_write_cycles = 13, - .atclk_div = 40 + .atclk_div = 40 }, { - .name = "350", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 350000000, - .multi = 3.5, - .voltage = 2050, - .edx_reset = 0x651, - .cpuid_model = 0x651, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 32, - .mem_write_cycles = 32, - .cache_read_cycles = 11, + .name = "350", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, .cache_write_cycles = 11, - .atclk_div = 42 + .atclk_div = 42 }, { - .name = "400", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 4.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "450", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, + .name = "450", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, .cache_write_cycles = 14, - .atclk_div = 54 + .atclk_div = 54 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SLOT1, - .manufacturer = "Intel", - .name = "Celeron (Covington)", + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Celeron (Covington)", .internal_name = "celeron_covington", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "66", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 6, + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 8 + .atclk_div = 8 }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 9, + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 12, + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 16 + .atclk_div = 16 }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 15, + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 15, .cache_write_cycles = 15, - .atclk_div = 20 + .atclk_div = 20 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 18, + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 18, .cache_write_cycles = 18, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 21, + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 21, .cache_write_cycles = 21, - .atclk_div = 28 + .atclk_div = 28 }, { - .name = "266", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2050, - .edx_reset = 0x650, - .cpuid_model = 0x650, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 24, + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x650, + .cpuid_model = 0x650, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 24, .cache_write_cycles = 24, - .atclk_div = 32 + .atclk_div = 32 }, { - .name = "300", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x651, - .cpuid_model = 0x651, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 25, - .mem_write_cycles = 25, - .cache_read_cycles = 25, + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x651, + .cpuid_model = 0x651, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 25, .cache_write_cycles = 25, - .atclk_div = 36 + .atclk_div = 36 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SLOT2, - .manufacturer = "Intel", - .name = "Pentium II Xeon", + .package = CPU_PKG_SLOT2, + .manufacturer = "Intel", + .name = "Pentium II Xeon", .internal_name = "pentium2_xeon", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 3, + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 3, .cache_write_cycles = 3, - .atclk_div = 12 + .atclk_div = 12 }, { /* out of spec */ - .name = "150", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 150000000, - .multi = 1.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 4, + .name = "150", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 4, .cache_write_cycles = 4, - .atclk_div = 18 + .atclk_div = 18 }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 2.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 6, + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 6, .cache_write_cycles = 6, - .atclk_div = 24 + .atclk_div = 24 }, { /* out of spec */ - .name = "250", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 250000000, - .multi = 2.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 22, - .mem_write_cycles = 22, - .cache_read_cycles = 7, + .name = "250", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 22, + .mem_write_cycles = 22, + .cache_read_cycles = 7, .cache_write_cycles = 7, - .atclk_div = 30 + .atclk_div = 30 }, { /* out of spec */ - .name = "300", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 3.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 9, + .name = "300", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, .cache_write_cycles = 9, - .atclk_div = 36 + .atclk_div = 36 }, { /* out of spec */ - .name = "350", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 350000000, - .multi = 3.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 32, - .mem_write_cycles = 32, - .cache_read_cycles = 10, + .name = "350", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 10, .cache_write_cycles = 10, - .atclk_div = 42 + .atclk_div = 42 }, { - .name = "400", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 4.0, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, + .name = "400", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, .cache_write_cycles = 12, - .atclk_div = 48 + .atclk_div = 48 }, { - .name = "450", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x652, - .cpuid_model = 0x652, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, + .name = "450", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, .cache_write_cycles = 14, - .atclk_div = 54 + .atclk_div = 54 }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET370, - .manufacturer = "Intel", - .name = "Celeron (Mendocino)", + .package = CPU_PKG_SOCKET370, + .manufacturer = "Intel", + .name = "Celeron (Mendocino)", .internal_name = "celeron_mendocino", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of spec */ - .name = "66", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 8 - }, + .name = "66", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, { /* out of spec */ - .name = "100", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 8, - .mem_write_cycles = 8, - .cache_read_cycles = 4, - .cache_write_cycles = 4, - .atclk_div = 12 - }, + .name = "100", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, { /* out of spec */ - .name = "133", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 11, - .mem_write_cycles = 11, - .cache_read_cycles = 5, - .cache_write_cycles = 5, - .atclk_div = 16 - }, + .name = "133", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 11, + .mem_write_cycles = 11, + .cache_read_cycles = 5, + .cache_write_cycles = 5, + .atclk_div = 16 + }, { /* out of spec */ - .name = "166", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 14, - .mem_write_cycles = 14, - .cache_read_cycles = 7, - .cache_write_cycles = 7, - .atclk_div = 20 - }, + .name = "166", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, { /* out of spec */ - .name = "200", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 17, - .mem_write_cycles = 17, - .cache_read_cycles = 8, - .cache_write_cycles = 8, - .atclk_div = 24 - }, + .name = "200", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 17, + .mem_write_cycles = 17, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 24 + }, { /* out of spec */ - .name = "233", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 19, - .mem_write_cycles = 19, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 28 - }, + .name = "233", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 19, + .mem_write_cycles = 19, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 28 + }, { /* out of spec */ - .name = "266", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 22, - .mem_write_cycles = 22, - .cache_read_cycles = 11, - .cache_write_cycles = 11, - .atclk_div = 32 - }, + .name = "266", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 22, + .mem_write_cycles = 22, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 32 + }, { - .name = "300A", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 25, - .mem_write_cycles = 25, - .cache_read_cycles = 12, - .cache_write_cycles = 12, - .atclk_div = 36 - }, + .name = "300A", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 25, + .mem_write_cycles = 25, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 36 + }, { - .name = "333", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 333333333, - .multi = 5.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, - .cache_write_cycles = 13, - .atclk_div = 40 - }, + .name = "333", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 40 + }, { - .name = "366", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 366666666, - .multi = 5.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 33, - .mem_write_cycles = 33, - .cache_read_cycles = 17, - .cache_write_cycles = 17, - .atclk_div = 44 - }, + .name = "366", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, { - .name = "400", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 6.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 12, - .cache_write_cycles = 12, - .atclk_div = 48 - }, + .name = "400", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, { - .name = "433", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 433333333, - .multi = 6.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 39, - .mem_write_cycles = 39, - .cache_read_cycles = 13, - .cache_write_cycles = 13, - .atclk_div = 51 - }, + .name = "433", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 433333333, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 39, + .mem_write_cycles = 39, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 51 + }, { - .name = "466", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 466666666, - .multi = 7.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 42, - .mem_write_cycles = 42, - .cache_read_cycles = 14, - .cache_write_cycles = 14, - .atclk_div = 56 - }, + .name = "466", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 466666666, + .multi = 7.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 42, + .mem_write_cycles = 42, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 56 + }, { - .name = "500", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 500000000, - .multi = 7.5, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 45, - .mem_write_cycles = 45, - .cache_read_cycles = 15, - .cache_write_cycles = 15, - .atclk_div = 60 - }, + .name = "500", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 7.5, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, { - .name = "533", - .cpu_type = CPU_PENTIUM2D, - .fpus = fpus_internal, - .rspeed = 533333333, - .multi = 8.0, - .voltage = 2050, - .edx_reset = 0x665, - .cpuid_model = 0x665, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 48, - .mem_write_cycles = 48, - .cache_read_cycles = 17, - .cache_write_cycles = 17, - .atclk_div = 64 - }, + .name = "533", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 8.0, + .voltage = 2050, + .edx_reset = 0x665, + .cpuid_model = 0x665, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 64 + }, { .name = "", 0 } } }, { - .package = CPU_PKG_SOCKET370, - .manufacturer = "VIA", - .name = "Cyrix III", + .package = CPU_PKG_SOCKET370, + .manufacturer = "VIA", + .name = "Cyrix III", .internal_name = "c3_samuel", - .cpus = (const CPU[]) { + .cpus = (const CPU[]) { { /* out of multiplier range */ - .name = "66", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 66666666, - .multi = 1.0, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 6, - .mem_write_cycles = 6, - .cache_read_cycles = 3, - .cache_write_cycles = 3, - .atclk_div = 8 - }, + .name = "66", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, { /* out of multiplier range */ - .name = "100", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 100000000, - .multi = 1.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 9, - .mem_write_cycles = 9, - .cache_read_cycles = 4, - .cache_write_cycles = 4, - .atclk_div = 12 - }, + .name = "100", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, { /* out of multiplier range */ - .name = "133", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 133333333, - .multi = 2.0, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 12, - .mem_write_cycles = 12, - .cache_read_cycles = 6, - .cache_write_cycles = 6, - .atclk_div = 16 - }, + .name = "133", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, { /* out of multiplier range */ - .name = "166", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 166666666, - .multi = 2.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 15, - .mem_write_cycles = 15, - .cache_read_cycles = 7, - .cache_write_cycles = 7, - .atclk_div = 20 - }, + .name = "166", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, { /* out of multiplier range */ - .name = "200", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 200000000, - .multi = 3.0, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 18, - .mem_write_cycles = 18, - .cache_read_cycles = 8, - .cache_write_cycles = 8, - .atclk_div = 24 - }, + .name = "200", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 24 + }, { /* out of multiplier range */ - .name = "233", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 233333333, - .multi = 3.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 21, - .mem_write_cycles = 21, - .cache_read_cycles = 9, - .cache_write_cycles = 9, - .atclk_div = 28 - }, + .name = "233", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 28 + }, { /* out of multiplier range */ - .name = "266", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 266666666, - .multi = 4.0, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 24, - .mem_write_cycles = 24, - .cache_read_cycles = 12, - .cache_write_cycles = 12, - .atclk_div = 32 - }, + .name = "266", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, { /* out of spec */ - .name = "300", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 300000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 27, - .mem_write_cycles = 27, - .cache_read_cycles = 13, - .cache_write_cycles = 13, - .atclk_div = 36 - }, + .name = "300", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, { /* out of spec */ - .name = "333", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 333333333, - .multi = 5.0, - .voltage = 2050, - .edx_reset = 0x662, - .cpuid_model = 0x662, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 30, - .mem_write_cycles = 30, - .cache_read_cycles = 15, - .cache_write_cycles = 15, - .atclk_div = 40 - }, + .name = "333", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 333333333, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 40 + }, { /* out of spec */ - .name = "366", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 366666666, - .multi = 5.5, - .voltage = 2050, - .edx_reset = 0x662, - .cpuid_model = 0x662, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 33, - .mem_write_cycles = 33, - .cache_read_cycles = 16, - .cache_write_cycles = 16, - .atclk_div = 44 - }, + .name = "366", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 16, + .cache_write_cycles = 16, + .atclk_div = 44 + }, { - .name = "400", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 400000000, - .multi = 6.0, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 36, - .mem_write_cycles = 36, - .cache_read_cycles = 17, - .cache_write_cycles = 17, - .atclk_div = 48 - }, + .name = "400", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 48 + }, { /* out of spec */ - .name = "433", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 433333333, - .multi = 6.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 39, - .mem_write_cycles = 39, - .cache_read_cycles = 18, - .cache_write_cycles = 18, - .atclk_div = 52 - }, + .name = "433", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 433333333, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 39, + .mem_write_cycles = 39, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 52 + }, { - .name = "450", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 450000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 41, - .mem_write_cycles = 41, - .cache_read_cycles = 14, - .cache_write_cycles = 14, - .atclk_div = 54 - }, + .name = "450", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, { /* out of spec */ - .name = "466", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 466666666, - .multi = 6.5, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 42, - .mem_write_cycles = 42, - .cache_read_cycles = 14, - .cache_write_cycles = 14, - .atclk_div = 56 - }, + .name = "466", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 466666666, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 42, + .mem_write_cycles = 42, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 56 + }, { - .name = "500", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 500000000, - .multi = 5.0, - .voltage = 2050, - .edx_reset = 0x662, - .cpuid_model = 0x662, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 45, - .mem_write_cycles = 45, - .cache_read_cycles = 15, - .cache_write_cycles = 15, - .atclk_div = 60 - }, + .name = "500", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, { /* out of spec */ - .name = "533", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 533333333, - .multi = 8.0, - .voltage = 2050, - .edx_reset = 0x660, - .cpuid_model = 0x660, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 48, - .mem_write_cycles = 48, - .cache_read_cycles = 15, - .cache_write_cycles = 15, - .atclk_div = 64 - }, + .name = "533", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 8.0, + .voltage = 2050, + .edx_reset = 0x660, + .cpuid_model = 0x660, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 64 + }, { - .name = "550", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 550000000, - .multi = 5.5, - .voltage = 2050, - .edx_reset = 0x662, - .cpuid_model = 0x662, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 50, - .mem_write_cycles = 50, - .cache_read_cycles = 17, - .cache_write_cycles = 17, - .atclk_div = 66 - }, + .name = "550", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, { - .name = "600/100", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 600000000, - .multi = 6.0, - .voltage = 2050, - .edx_reset = 0x662, - .cpuid_model = 0x662, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 54, - .mem_write_cycles = 54, - .cache_read_cycles = 18, - .cache_write_cycles = 18, - .atclk_div = 72 - }, + .name = "600/100", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 600000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x662, + .cpuid_model = 0x662, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 54, + .mem_write_cycles = 54, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 72 + }, { - .name = "600/133", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 600000000, - .multi = 4.5, - .voltage = 2050, - .edx_reset = 0x663, - .cpuid_model = 0x663, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 54, - .mem_write_cycles = 54, - .cache_read_cycles = 13, - .cache_write_cycles = 13, - .atclk_div = 72 - }, + .name = "600/133", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 600000000, + .multi = 4.5, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 54, + .mem_write_cycles = 54, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 72 + }, { - .name = "650", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 650000000, - .multi = 6.5, - .voltage = 2050, - .edx_reset = 0x663, - .cpuid_model = 0x663, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 58, - .mem_write_cycles = 58, - .cache_read_cycles = 20, - .cache_write_cycles = 20, - .atclk_div = 78 - }, + .name = "650", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 650000000, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 58, + .mem_write_cycles = 58, + .cache_read_cycles = 20, + .cache_write_cycles = 20, + .atclk_div = 78 + }, { - .name = "667", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 666666667, - .multi = 5.0, - .voltage = 2050, - .edx_reset = 0x663, - .cpuid_model = 0x663, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 60, - .mem_write_cycles = 60, - .cache_read_cycles = 16, - .cache_write_cycles = 16, - .atclk_div = 80 - }, + .name = "667", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 666666667, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 60, + .mem_write_cycles = 60, + .cache_read_cycles = 16, + .cache_write_cycles = 16, + .atclk_div = 80 + }, { - .name = "700", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 700000000, - .multi = 7.0, - .voltage = 2050, - .edx_reset = 0x663, - .cpuid_model = 0x663, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 63, - .mem_write_cycles = 63, - .cache_read_cycles = 21, - .cache_write_cycles = 21, - .atclk_div = 84 - }, + .name = "700", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 700000000, + .multi = 7.0, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 63, + .mem_write_cycles = 63, + .cache_read_cycles = 21, + .cache_write_cycles = 21, + .atclk_div = 84 + }, { - .name = "733", - .cpu_type = CPU_CYRIX3S, - .fpus = fpus_internal, - .rspeed = 733333333, - .multi = 5.5, - .voltage = 2050, - .edx_reset = 0x663, - .cpuid_model = 0x663, - .cyrix_id = 0, - .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, - .mem_read_cycles = 66, - .mem_write_cycles = 66, - .cache_read_cycles = 18, - .cache_write_cycles = 18, - .atclk_div = 88 - }, + .name = "733", + .cpu_type = CPU_CYRIX3S, + .fpus = fpus_internal, + .rspeed = 733333333, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x663, + .cpuid_model = 0x663, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 66, + .mem_write_cycles = 66, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 88 + }, { .name = "", 0 } } }, From 60be3e786e75dce514c81f7ea049d362a570ccbe Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 20:03:24 -0400 Subject: [PATCH 17/36] Update cpu_table copyright --- src/cpu/cpu_table.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 199e197df..574cf3fd5 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -16,13 +16,15 @@ * Fred N. van Kempen, * RichardG, * dob205, + * Jasmine Iwanek, * * Copyright 2008-2019 Sarah Walker. * Copyright 2016-2019 leilei. - * Copyright 2016-2019 Miran Grca. + * Copyright 2016-2024 Miran Grca. * Copyright 2017-2020 Fred N. van Kempen. * Copyright 2020 RichardG. * Copyright 2021 dob205. + * Copyright 2022-2024 Jasmine Iwanek. */ #include #include From 963a92cfcc245518e8f9de35408e6c32b0524750 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Jul 2024 02:21:59 +0200 Subject: [PATCH 18/36] Update AppImageBuilder.yml --- .ci/AppImageBuilder.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.ci/AppImageBuilder.yml b/.ci/AppImageBuilder.yml index f6e04ab9f..64f8f91ed 100644 --- a/.ci/AppImageBuilder.yml +++ b/.ci/AppImageBuilder.yml @@ -59,7 +59,7 @@ AppDir: - libqt5widgets5 # if QT:BOOL=ON - libsixel1 # if CLI:BOOL=ON - libslirp0 - - libsndfile-dev + - libsndfile1 - libsndio7.0 # if OPENAL:BOOL=ON - libvdeplug-dev # -dev also pulls in libvdeplug2. -dev is required to get the proper .so symlink to the library - libx11-6 # if QT:BOOL=ON From 47e462648bc6fad8770b73990663a41de264c44c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Jul 2024 02:22:33 +0200 Subject: [PATCH 19/36] Update build.sh --- .ci/build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.ci/build.sh b/.ci/build.sh index 1b1e5825e..a53ea0671 100755 --- a/.ci/build.sh +++ b/.ci/build.sh @@ -605,7 +605,7 @@ else # ...and the ones we do want listed. Non-dev packages fill missing spots on the list. libpkgs="" longest_libpkg=0 - for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libxkbcommon-x11-dev libglib2.0-dev libslirp-dev libfaudio-dev libaudio-dev libjack-jackd2-dev libpipewire-0.3-dev libsamplerate0-dev libsndio-dev libvdeplug-dev libfluidsynth-dev + for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libxkbcommon-x11-dev libglib2.0-dev libslirp-dev libfaudio-dev libaudio-dev libjack-jackd2-dev libpipewire-0.3-dev libsamplerate0-dev libsndio-dev libvdeplug-dev libfluidsynth-dev libsndfile1-dev do libpkgs="$libpkgs $pkg:$arch_deb" length=$(echo -n $pkg | sed 's/-dev$//' | sed "s/qtdeclarative/qt/" | wc -c) From fc409288f863157dbca3ccedd3cd20a4e4c60038 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 20:25:54 -0400 Subject: [PATCH 20/36] Fixed the Tandy 1000HX CPU's. --- src/machine/machine_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index a7c5d1cbf..29bafb65b 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -1548,7 +1548,7 @@ const machine_t machines[] = { .available_flag = MACHINE_AVAILABLE, .gpio_acpi_handler = NULL, .cpu = { - .package = CPU_PKG_8088_EUROPC, + .package = CPU_PKG_8088, .block = CPU_BLOCK_NONE, .min_bus = 0, .max_bus = 0, From cf26ed11bfa5b242b98f3cb35bb8d808a68eb14d Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 23 Jul 2024 21:11:09 -0400 Subject: [PATCH 21/36] experimental preset renamed to dev_debug --- .github/workflows/cmake_linux.yml | 4 ++-- .github/workflows/cmake_macos.yml | 8 ++++---- .github/workflows/cmake_windows_msys2.yml | 4 ++-- .github/workflows/codeql_linux.yml | 2 +- .github/workflows/codeql_macos.yml | 2 +- .github/workflows/codeql_windows_msys2.yml | 2 +- CMakePresets.json | 8 +++----- 7 files changed, 14 insertions(+), 16 deletions(-) diff --git a/.github/workflows/cmake_linux.yml b/.github/workflows/cmake_linux.yml index f1ef973c4..ed0f055a2 100644 --- a/.github/workflows/cmake_linux.yml +++ b/.github/workflows/cmake_linux.yml @@ -40,10 +40,10 @@ jobs: # - name: Regular # preset: regular - name: Debug - preset: debug + preset: dev_debug slug: -Debug - name: Dev - preset: experimental + preset: development slug: -Dev dynarec: - name: ODR diff --git a/.github/workflows/cmake_macos.yml b/.github/workflows/cmake_macos.yml index 045626cd1..dc45312f5 100644 --- a/.github/workflows/cmake_macos.yml +++ b/.github/workflows/cmake_macos.yml @@ -40,10 +40,10 @@ jobs: # - name: Regular # preset: regular - name: Debug - preset: debug + preset: dev_debug slug: -Debug - name: Dev - preset: experimental + preset: development slug: -Dev dynarec: - name: ODR @@ -138,10 +138,10 @@ jobs: # - name: Regular # preset: regular - name: Debug - preset: debug + preset: dev_debug slug: -Debug - name: Dev - preset: experimental + preset: development slug: -Dev dynarec: # - name: ODR diff --git a/.github/workflows/cmake_windows_msys2.yml b/.github/workflows/cmake_windows_msys2.yml index d415c7821..91442eafd 100644 --- a/.github/workflows/cmake_windows_msys2.yml +++ b/.github/workflows/cmake_windows_msys2.yml @@ -44,10 +44,10 @@ jobs: # - name: Regular # preset: regular - name: Debug - preset: debug + preset: dev_debug slug: -Debug - name: Dev - preset: experimental + preset: development slug: -Dev dynarec: - name: ODR diff --git a/.github/workflows/codeql_linux.yml b/.github/workflows/codeql_linux.yml index 73ccfb214..fee26a0a6 100644 --- a/.github/workflows/codeql_linux.yml +++ b/.github/workflows/codeql_linux.yml @@ -47,7 +47,7 @@ jobs: # preset: debug # slug: -Debug - name: Dev - preset: experimental + preset: dev_debug slug: -Dev dynarec: - name: ODR diff --git a/.github/workflows/codeql_macos.yml b/.github/workflows/codeql_macos.yml index adf34cb54..266a1f051 100644 --- a/.github/workflows/codeql_macos.yml +++ b/.github/workflows/codeql_macos.yml @@ -47,7 +47,7 @@ jobs: # preset: debug # slug: -Debug - name: Dev - preset: experimental + preset: dev_debug slug: -Dev dynarec: - name: ODR diff --git a/.github/workflows/codeql_windows_msys2.yml b/.github/workflows/codeql_windows_msys2.yml index 2b468f996..652a1986a 100644 --- a/.github/workflows/codeql_windows_msys2.yml +++ b/.github/workflows/codeql_windows_msys2.yml @@ -51,7 +51,7 @@ jobs: # preset: debug # slug: -Debug - name: Dev - preset: experimental + preset: dev_debug slug: -Dev dynarec: - name: ODR diff --git a/CMakePresets.json b/CMakePresets.json index 0dbaf1988..c19a7abc0 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -43,17 +43,15 @@ "name": "development", "cacheVariables": { "CMAKE_BUILD_TYPE": "Release", - "DEV_BRANCH": "ON", - "NEW_DYNAREC": "OFF" + "DEV_BRANCH": "ON" }, "inherits": "base" }, { - "name": "experimental", + "name": "dev_debug", "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug", - "DEV_BRANCH": "ON", - "NEW_DYNAREC": "ON" + "DEV_BRANCH": "ON" }, "inherits": "base" }, From ad9009bfe9de29a0905154894f9ce0994adbfc95 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Jul 2024 05:36:44 +0200 Subject: [PATCH 22/36] Removed an excess timer_process() call from src/game/joystick_sw_pad.c. --- src/game/joystick_sw_pad.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/game/joystick_sw_pad.c b/src/game/joystick_sw_pad.c index 7962c38e3..ba862d1e6 100644 --- a/src/game/joystick_sw_pad.c +++ b/src/game/joystick_sw_pad.c @@ -173,8 +173,6 @@ sw_write(void *priv) if (!JOYSTICK_PRESENT(0)) return; - timer_process(); - if (!sw->poll_left) { sw->poll_clock = 1; timer_set_delay_u64(&sw->poll_timer, TIMER_USEC * 50); From be944a15e69736f3c8dd1cd286195ca85986ff06 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Jul 2024 17:43:12 +0200 Subject: [PATCH 23/36] Ported more Sidewinder Pad changes from PCem. --- src/game/joystick_sw_pad.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/game/joystick_sw_pad.c b/src/game/joystick_sw_pad.c index ba862d1e6..cab008d0a 100644 --- a/src/game/joystick_sw_pad.c +++ b/src/game/joystick_sw_pad.c @@ -92,9 +92,7 @@ sw_timer_over(void *priv) if (sw->poll_left == 1 && !sw->poll_clock) timer_advance_u64(&sw->poll_timer, TIMER_USEC * 160); else if (sw->poll_left) - timer_advance_u64(&sw->poll_timer, TIMER_USEC * 5); - else - timer_disable(&sw->poll_timer); + timer_set_delay_u64(&sw->poll_timer, TIMER_USEC * 5); } static void @@ -175,7 +173,7 @@ sw_write(void *priv) if (!sw->poll_left) { sw->poll_clock = 1; - timer_set_delay_u64(&sw->poll_timer, TIMER_USEC * 50); + timer_set_delay_u64(&sw->poll_timer, TIMER_USEC * 40); if (time_since_last > 9900 && time_since_last < 9940) { sw->poll_mode = 0; From 81ae79c3cac46b5003dd5da764fe691723213170 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Wed, 24 Jul 2024 13:11:41 -0400 Subject: [PATCH 24/36] Remove dead code in scsi_ncr5380.h --- src/include/86box/scsi_ncr5380.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/include/86box/scsi_ncr5380.h b/src/include/86box/scsi_ncr5380.h index 8baa4f9d8..55692075b 100644 --- a/src/include/86box/scsi_ncr5380.h +++ b/src/include/86box/scsi_ncr5380.h @@ -138,9 +138,6 @@ extern const device_t scsi_t128_device; extern const device_t scsi_t228_device; extern const device_t scsi_t130b_device; extern const device_t scsi_ls2000_device; -#if defined(DEV_BRANCH) && defined(USE_SUMO) -extern const device_t scsi_scsiat_device; -#endif #endif #endif /*SCSI_NCR5380_H*/ From f36c813ca57571cab8f5357ce4d96123f6301b81 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 00:46:33 +0200 Subject: [PATCH 25/36] HxC MFM format: Add heuristic to default to a sane RPM when the RPM in the image is set to 0, fixes #4357. --- src/floppy/fdd_mfm.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/floppy/fdd_mfm.c b/src/floppy/fdd_mfm.c index b4c859d5d..f998a6201 100644 --- a/src/floppy/fdd_mfm.c +++ b/src/floppy/fdd_mfm.c @@ -450,13 +450,20 @@ mfm_load(int drive, char *fn) } if (!(dev->hdr.if_type & 0x80)) { + pclog("Bit rate = %i\n", dev->hdr.bit_rate); dbr = round(((double) dev->hdr.bit_rate) / 50.0) * 50.0; dev->br_rounded = (int) dbr; mfm_log("Rounded bit rate: %i kbps\n", dev->br_rounded); + pclog("Rounded bit rate: %i kbps\n", dev->br_rounded); - dbr = round(((double) dev->hdr.rpm) / 60.0) * 60.0; + pclog("RPM = %i\n", dev->hdr.rpm); + if (dev->hdr.rpm != 0) + dbr = round(((double) dev->hdr.rpm) / 60.0) * 60.0; + else + dbr = (dev->br_rounded == 300) ? 360 : 300; dev->rpm_rounded = (int) dbr; mfm_log("Rounded RPM: %i kbps\n", dev->rpm_rounded); + pclog("Rounded RPM: %i kbps\n", dev->rpm_rounded); } /* Set up the drive unit. */ From 0af09b05786f095a5f2d1e5efa7aa3829db0f63e Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 00:48:46 +0200 Subject: [PATCH 26/36] Removed the excess logging from fdd_mfm.c. --- src/floppy/fdd_mfm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/floppy/fdd_mfm.c b/src/floppy/fdd_mfm.c index f998a6201..a332d25c9 100644 --- a/src/floppy/fdd_mfm.c +++ b/src/floppy/fdd_mfm.c @@ -450,20 +450,16 @@ mfm_load(int drive, char *fn) } if (!(dev->hdr.if_type & 0x80)) { - pclog("Bit rate = %i\n", dev->hdr.bit_rate); dbr = round(((double) dev->hdr.bit_rate) / 50.0) * 50.0; dev->br_rounded = (int) dbr; mfm_log("Rounded bit rate: %i kbps\n", dev->br_rounded); - pclog("Rounded bit rate: %i kbps\n", dev->br_rounded); - pclog("RPM = %i\n", dev->hdr.rpm); if (dev->hdr.rpm != 0) dbr = round(((double) dev->hdr.rpm) / 60.0) * 60.0; else - dbr = (dev->br_rounded == 300) ? 360 : 300; + dbr = (dev->br_rounded == 300) ? 360.0 : 300.0; dev->rpm_rounded = (int) dbr; - mfm_log("Rounded RPM: %i kbps\n", dev->rpm_rounded); - pclog("Rounded RPM: %i kbps\n", dev->rpm_rounded); + mfm_log("Rounded RPM: %i rpm\n", dev->rpm_rounded); } /* Set up the drive unit. */ From 3ea7f2ad928fbf4830ad168142d3fe8e085d78f4 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 06:54:26 +0200 Subject: [PATCH 27/36] OPTi chipset mask and CPU fixes, fixes #895. --- src/chipset/opti283.c | 35 +++++++++++++++++++------- src/chipset/opti391.c | 32 ++++++++++++++++-------- src/chipset/opti495.c | 55 ++++++++++++++++++++++++++++++++--------- src/chipset/opti499.c | 41 ++++++++++++++++-------------- src/chipset/opti895.c | 14 ++++++++--- src/cpu/x86_ops_pmode.h | 21 +++++++++++----- 6 files changed, 139 insertions(+), 59 deletions(-) diff --git a/src/chipset/opti283.c b/src/chipset/opti283.c index 1fa59f2f0..63976985b 100644 --- a/src/chipset/opti283.c +++ b/src/chipset/opti283.c @@ -31,6 +31,7 @@ #include <86box/mem.h> #include <86box/plat_fallthrough.h> #include <86box/plat_unused.h> +#include <86box/port_92.h> #include <86box/chipset.h> #ifdef ENABLE_OPTI283_LOG @@ -215,16 +216,27 @@ opti283_write(uint16_t addr, uint8_t val, void *priv) opti283_t *dev = (opti283_t *) priv; switch (addr) { + default: + break; + case 0x22: dev->index = val; break; + case 0x23: + if (dev->index == 0x01) + dev->regs[dev->index] = val; + break; + case 0x24: opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); switch (dev->index) { + default: + break; + case 0x10: - dev->regs[dev->index] = val; + dev->regs[dev->index] = (dev->regs[dev->index] & 0x80) | (val & 0x7f); break; case 0x14: @@ -236,13 +248,9 @@ opti283_write(uint16_t addr, uint8_t val, void *priv) dev->regs[dev->index] = val; opti283_shadow_recalc(dev); break; - - default: - break; } - break; - default: + dev->index = 0xff; break; } } @@ -250,11 +258,17 @@ opti283_write(uint16_t addr, uint8_t val, void *priv) static uint8_t opti283_read(uint16_t addr, void *priv) { - const opti283_t *dev = (opti283_t *) priv; - uint8_t ret = 0xff; + opti283_t *dev = (opti283_t *) priv; + uint8_t ret = 0xff; - if (addr == 0x24) + if ((addr == 0x23) && (dev->index == 0x01)) ret = dev->regs[dev->index]; + else if (addr == 0x24) { + if ((dev->index >= 0x10) && (dev->index <= 0x14)) + ret = dev->regs[dev->index]; + + dev->index = 0xff; + } return ret; } @@ -274,6 +288,7 @@ opti283_init(UNUSED(const device_t *info)) memset(dev, 0x00, sizeof(opti283_t)); io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev); + io_sethandler(0x0023, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev); io_sethandler(0x0024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev); dev->regs[0x10] = 0x3f; @@ -296,6 +311,8 @@ opti283_init(UNUSED(const device_t *info)) opti283_shadow_recalc(dev); + device_add(&port_92_device); + return dev; } diff --git a/src/chipset/opti391.c b/src/chipset/opti391.c index c4c5534f8..c22c2a04b 100644 --- a/src/chipset/opti391.c +++ b/src/chipset/opti391.c @@ -178,6 +178,9 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) opti391_log("[W] %04X = %02X\n", addr, val); switch (addr) { + default: + break; + case 0x22: dev->index = val; break; @@ -200,6 +203,9 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) reset_on_hlt = !!(val & 0x02); break; } else switch (dev->index - dev->reg_base) { + default: + break; + case 0x00: if (dev->type == 2) { reset_on_hlt = !!(val & 0x02); @@ -222,8 +228,14 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) opti391_recalcremap(dev); break; - case 0x04: case 0x05: + if (dev->type == 2) + dev->regs[dev->index - dev->reg_base] = val & 0xf8; + else + dev->regs[dev->index - dev->reg_base] = val; + break; + + case 0x04: case 0x09: case 0x0a: case 0x0b: @@ -238,8 +250,10 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) } break; case 0x08: - dev->regs[dev->index - dev->reg_base] = val; - if (dev->type < 2) { + if (dev->type == 2) + dev->regs[dev->index - dev->reg_base] = val & 0xe3; + else { + dev->regs[dev->index - dev->reg_base] = val; cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x40); cpu_update_waitstates(); } @@ -257,13 +271,9 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) dev->regs[dev->index - dev->reg_base] = val; opti391_shadow_recalc(dev); break; - - default: - break; } - break; - default: + dev->index = 0xff; break; } } @@ -271,14 +281,16 @@ opti391_write(uint16_t addr, uint8_t val, void *priv) static uint8_t opti391_read(uint16_t addr, void *priv) { - const opti391_t *dev = (opti391_t *) priv; - uint8_t ret = 0xff; + opti391_t *dev = (opti391_t *) priv; + uint8_t ret = 0xff; if (addr == 0x24) { if ((dev->index <= 0x01) && (dev->type < 2)) ret = dev->regs[dev->index + 0x10]; else if ((dev->index >= dev->min_reg) && (dev->index <= dev->max_reg)) ret = dev->regs[dev->index - dev->reg_base]; + + dev->index = 0xff; } opti391_log("[R] %04X = %02X\n", addr, ret); diff --git a/src/chipset/opti495.c b/src/chipset/opti495.c index 13bc2a124..84ef6a202 100644 --- a/src/chipset/opti495.c +++ b/src/chipset/opti495.c @@ -32,6 +32,8 @@ #include <86box/chipset.h> typedef struct opti495_t { + uint8_t type; + uint8_t max; uint8_t idx; uint8_t regs[256]; uint8_t scratch[2]; @@ -55,6 +57,22 @@ opti495_log(const char *fmt, ...) # define opti495_log(fmt, ...) #endif +enum { + OPTI493 = 0, + OPTI495, + OPTI495SLC, + OPTI495SX, + OPTI495XLC, + TMAX +}; + +/* OPTi 82C493: According to The Last Byte, bit 1 of register 22h, while unused, must still be writable. */ +static uint8_t masks[TMAX][0x1c] = { { 0x3f, 0xff, 0xff, 0xff, 0xf7, 0xfb, 0x7f, 0x9f, 0xe3, 0xff, 0xe3, 0xff }, + { 0x3a, 0x7f, 0xff, 0xff, 0xf0, 0xfb, 0x7f, 0xbf, 0xe3, 0xff, 0x00, 0x00 }, + { 0x3a, 0x7f, 0xfc, 0xff, 0xf0, 0xfb, 0xff, 0xbf, 0xe3, 0xff, 0x00, 0x00 }, + { 0x3a, 0xff, 0xfd, 0xff, 0xf0, 0xfb, 0x7f, 0xbf, 0xe3, 0xff, 0x00, 0x00 }, + { 0x3a, 0xff, 0xfc, 0xff, 0xf0, 0xfb, 0xff, 0xbf, 0xe3, 0xff, 0x00, 0x00 } }; + static void opti495_recalc(opti495_t *dev) { @@ -119,16 +137,25 @@ opti495_write(uint16_t addr, uint8_t val, void *priv) opti495_t *dev = (opti495_t *) priv; switch (addr) { + default: + break; + case 0x22: opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); dev->idx = val; break; case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - dev->regs[dev->idx] = val; + if ((dev->idx >= 0x20) && (dev->idx <= dev->max)) { opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); + dev->regs[dev->idx] = val & masks[dev->type][dev->idx - 0x20]; + if ((dev->type == OPTI493) && (dev->idx == 0x20)) + val |= 0x40; + switch (dev->idx) { + default: + break; + case 0x21: cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); cpu_update_waitstates(); @@ -139,36 +166,36 @@ opti495_write(uint16_t addr, uint8_t val, void *priv) case 0x26: opti495_recalc(dev); break; - default: - break; } } + + dev->idx = 0xff; break; case 0xe1: case 0xe2: dev->scratch[~addr & 0x01] = val; break; - default: - break; } } static uint8_t opti495_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; - const opti495_t *dev = (opti495_t *) priv; + uint8_t ret = 0xff; + opti495_t *dev = (opti495_t *) priv; switch (addr) { case 0x22: opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); break; case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { + if ((dev->idx >= 0x20) && (dev->idx <= dev->max)) { ret = dev->regs[dev->idx]; opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); } + + dev->idx = 0xff; break; case 0xe1: case 0xe2: @@ -202,8 +229,11 @@ opti495_init(const device_t *info) dev->scratch[0] = dev->scratch[1] = 0xff; - if (info->local == 1) { + dev->type = info->local; + + if (info->local >= OPTI495) { /* 85C495 */ + dev->max = 0x29; dev->regs[0x20] = 0x02; dev->regs[0x21] = 0x20; dev->regs[0x22] = 0xe4; @@ -214,6 +244,7 @@ opti495_init(const device_t *info) dev->regs[0x29] = 0x10; } else { /* 85C493 */ + dev->max = 0x2b; dev->regs[0x20] = 0x40; dev->regs[0x22] = 0x84; dev->regs[0x24] = 0x87; @@ -236,7 +267,7 @@ const device_t opti493_device = { .name = "OPTi 82C493", .internal_name = "opti493", .flags = 0, - .local = 0, + .local = OPTI493, .init = opti495_init, .close = opti495_close, .reset = NULL, @@ -250,7 +281,7 @@ const device_t opti495_device = { .name = "OPTi 82C495", .internal_name = "opti495", .flags = 0, - .local = 1, + .local = OPTI495XLC, .init = opti495_init, .close = opti495_close, .reset = NULL, diff --git a/src/chipset/opti499.c b/src/chipset/opti499.c index d976e0198..ecadd2224 100644 --- a/src/chipset/opti499.c +++ b/src/chipset/opti499.c @@ -38,6 +38,9 @@ typedef struct opti499_t { uint8_t scratch[2]; } opti499_t; +/* According to The Last Byte, register 2Dh bit 7 must still be writable, even if it is unused. */ +static uint8_t masks[0x0e] = { 0x3f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xe3, 0xff, 0xfb, 0xff, 0x00, 0xff }; + #ifdef ENABLE_OPTI499_LOG int opti499_do_log = ENABLE_OPTI499_LOG; @@ -126,19 +129,25 @@ opti499_write(uint16_t addr, uint8_t val, void *priv) opti499_t *dev = (opti499_t *) priv; switch (addr) { + default: + break; + case 0x22: opti499_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); dev->idx = val; break; case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - if (dev->idx == 0x20) - dev->regs[dev->idx] = (dev->regs[dev->idx] & 0xc0) | (val & 0x3f); - else - dev->regs[dev->idx] = val; + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d) && (dev->idx != 0x2c)) { opti499_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); + dev->regs[dev->idx] = val & masks[dev->idx - 0x20]; + if (dev->idx == 0x2a) + dev->regs[dev->idx] |= 0x04; + switch (dev->idx) { + default: + break; + case 0x20: reset_on_hlt = !(val & 0x02); break; @@ -154,20 +163,16 @@ opti499_write(uint16_t addr, uint8_t val, void *priv) case 0x2d: opti499_recalc(dev); break; - - default: - break; } } + + dev->idx = 0xff; break; case 0xe1: case 0xe2: dev->scratch[~addr & 0x01] = val; break; - - default: - break; } } @@ -178,25 +183,23 @@ opti499_read(uint16_t addr, void *priv) opti499_t *dev = (opti499_t *) priv; switch (addr) { + default: + break; + case 0x22: opti499_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); break; case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - if (dev->idx == 0x2d) - ret = dev->regs[dev->idx] & 0xbf; - else - ret = dev->regs[dev->idx]; + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d) && (dev->idx != 0x2c)) { + ret = dev->regs[dev->idx]; opti499_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); } + dev->idx = 0xff; break; case 0xe1: case 0xe2: ret = dev->scratch[~addr & 0x01]; break; - - default: - break; } return ret; diff --git a/src/chipset/opti895.c b/src/chipset/opti895.c index 77297ae95..f1878a51b 100644 --- a/src/chipset/opti895.c +++ b/src/chipset/opti895.c @@ -42,6 +42,9 @@ typedef struct opti895_t { smram_t *smram; } opti895_t; +static uint8_t masks[0x10] = { 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xe3, 0xff, 0xe3, 0xff, 0x00, 0xff, 0xff, 0xff }; + #ifdef ENABLE_OPTI895_LOG int opti895_do_log = ENABLE_OPTI895_LOG; @@ -153,8 +156,12 @@ opti895_write(uint16_t addr, uint8_t val, void *priv) } break; case 0x24: - if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) || ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { - dev->regs[dev->idx] = val; + if (((dev->idx >= 0x20) && (dev->idx <= 0x2f) && (dev->idx != 0x2c)) || + ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { + if (dev->idx > 0x2f) + dev->regs[dev->idx] = val; + else + dev->regs[dev->idx] = val & masks[dev->idx - 0x20]; opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val); /* TODO: Registers 0x30-0x3F for OPTi 802GP and 898. */ @@ -217,7 +224,8 @@ opti895_read(uint16_t addr, void *priv) break; case 0x24: /* TODO: Registers 0x30-0x3F for OPTi 802GP and 898. */ - if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) || ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { + if (((dev->idx >= 0x20) && (dev->idx <= 0x2f) && (dev->idx != 0x2c)) || + ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { ret = dev->regs[dev->idx]; if (dev->idx == 0xe0) ret = (ret & 0xf6) | (in_smm ? 0x00 : 0x08) | !!dev->forced_green; diff --git a/src/cpu/x86_ops_pmode.h b/src/cpu/x86_ops_pmode.h index e84847a7b..4f32b0e37 100644 --- a/src/cpu/x86_ops_pmode.h +++ b/src/cpu/x86_ops_pmode.h @@ -430,12 +430,21 @@ op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) case 0x20: /*SMSW*/ if (cpu_mod != 3) SEG_CHECK_WRITE(cpu_state.ea_seg); - if (is486 || isibm486) - seteaw(msw); - else if (is386) - seteaw(msw | /* 0xFF00 */ 0xFFE0); - else - seteaw(msw | 0xFFF0); + if (is386 && is32 && (cpu_mod == 3)) { + if (is486 || isibm486) + seteaw(cr0); + else if (is386 && !cpu_16bitbus) + seteaw(cr0 | /* 0x7FFFFF00 */ 0x7FFFFFE0); + else + seteaw(cr0 | 0x7FFFFFF0); + } else { + if (is486 || isibm486) + seteaw(msw); + else if (is386 && !cpu_16bitbus) + seteaw(msw | /* 0xFF00 */ 0xFFE0); + else + seteaw(msw | 0xFFF0); + } CLOCK_CYCLES(2); PREFETCH_RUN(2, 2, rmdat, 0, 0, (cpu_mod == 3) ? 0 : 1, 0, ea32); break; From 8264b70825dc7754182bc7f52905dd2ef37cf1a2 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 06:56:24 +0200 Subject: [PATCH 28/36] Removed an excess line from Compaq Genoa init. --- src/chipset/compaq_386.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/chipset/compaq_386.c b/src/chipset/compaq_386.c index 3b40734aa..8c241e087 100644 --- a/src/chipset/compaq_386.c +++ b/src/chipset/compaq_386.c @@ -759,8 +759,6 @@ compaq_genoa_init(UNUSED(const device_t *info)) { void *cpq = device_add(&compaq_386_device); - pclog_toggle_suppr(); - io_sethandler(0x0c02, 2, NULL, NULL, NULL, NULL, compaq_genoa_outw, NULL, cpq); return ram; From 5912a88a1b9a4f38a1ee91010d2481c37e31b683 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 19:05:05 +0200 Subject: [PATCH 29/36] Fixed initializations in the CD-ROM code, fixes #4653. --- src/cdrom/cdrom_image_backend.c | 8 ++++---- src/cpu/x87_ops_sf.h | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/cdrom/cdrom_image_backend.c b/src/cdrom/cdrom_image_backend.c index e588a1938..25085285c 100644 --- a/src/cdrom/cdrom_image_backend.c +++ b/src/cdrom/cdrom_image_backend.c @@ -242,7 +242,7 @@ bin_close(void *priv) static track_file_t * bin_init(const char *filename, int *error) { - track_file_t *tf = (track_file_t *) malloc(sizeof(track_file_t)); + track_file_t *tf = (track_file_t *) calloc(1, sizeof(track_file_t)); struct stat stats; if (tf == NULL) { @@ -534,7 +534,7 @@ cdi_read_sectors(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector, uint3 to get sector size? */ const int sector_size = raw ? RAW_SECTOR_SIZE : COOKED_SECTOR_SIZE; const uint32_t buf_len = num * sector_size; - uint8_t *buf = (uint8_t *) malloc(buf_len * sizeof(uint8_t)); + uint8_t *buf = (uint8_t *) calloc(1, buf_len * sizeof(uint8_t)); for (uint32_t i = 0; i < num; i++) { success = cdi_read_sector(cdi, &buf[i * sector_size], raw, sector + i); @@ -646,7 +646,7 @@ cdi_track_push_back(cd_img_t *cdi, track_t *trk) int cdi_get_iso_track(cd_img_t *cdi, track_t *trk, const char *filename) { - int error; + int error = 0; int ret = 2; memset(trk, 0, sizeof(track_t)); @@ -712,7 +712,7 @@ int cdi_load_iso(cd_img_t *cdi, const char *filename) { int ret = 2; - track_t trk; + track_t trk = { 0 }; cdi->tracks = NULL; cdi->tracks_num = 0; diff --git a/src/cpu/x87_ops_sf.h b/src/cpu/x87_ops_sf.h index ea3715c41..af94897c9 100644 --- a/src/cpu/x87_ops_sf.h +++ b/src/cpu/x87_ops_sf.h @@ -606,7 +606,6 @@ static int sf_FNOP(uint32_t fetchdat) { FP_ENTER(); - pclog("FNOP.\n"); FPU_check_pending_exceptions(); cpu_state.pc++; CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi)); From a94f9d8381980d79e2b238a796b522c24500b6b3 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 19:13:38 +0200 Subject: [PATCH 30/36] All the requested machine table corrections except for the 486's. --- src/machine/machine_table.c | 310 ++++++++++++++++-------------------- 1 file changed, 135 insertions(+), 175 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 29bafb65b..673c9997d 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -57,7 +57,7 @@ extern const device_t compaq_plasma_device; extern const device_t ps1_2011_device; const machine_filter_t machine_types[] = { - { "None", MACHINE_TYPE_NONE }, + { "None", MACHINE_TYPE_NONE }, { "[1979] 8088", MACHINE_TYPE_8088 }, { "[1978] 8086", MACHINE_TYPE_8086 }, { "[1982] 80286", MACHINE_TYPE_286 }, @@ -72,15 +72,15 @@ const machine_filter_t machine_types[] = { { "[1993] Socket 4", MACHINE_TYPE_SOCKET4 }, { "[1994] Socket 5", MACHINE_TYPE_SOCKET5 }, { "[1995] Socket 7 (Single Voltage)", MACHINE_TYPE_SOCKET7_3V }, - { "[1995] Socket 7 (Dual Voltage)", MACHINE_TYPE_SOCKET7 }, + { "[1996] Socket 7 (Dual Voltage)", MACHINE_TYPE_SOCKET7 }, { "[1998] Super Socket 7", MACHINE_TYPE_SOCKETS7 }, { "[1995] Socket 8", MACHINE_TYPE_SOCKET8 }, - { "[1996] Slot 1", MACHINE_TYPE_SLOT1 }, + { "[1997] Slot 1", MACHINE_TYPE_SLOT1 }, { "[1998] Slot 1/2", MACHINE_TYPE_SLOT1_2 }, { "[1998] Slot 1/Socket 370", MACHINE_TYPE_SLOT1_370 }, { "[1998] Slot 2", MACHINE_TYPE_SLOT2 }, { "[1998] Socket 370", MACHINE_TYPE_SOCKET370 }, - { "Miscellaneous", MACHINE_TYPE_MISC } + { "Miscellaneous", MACHINE_TYPE_MISC } }; const machine_filter_t machine_chipsets[] = { @@ -10767,6 +10767,48 @@ const machine_t machines[] = { }, /* 430HX */ + /* Has SST Flash. */ + /* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix + MultiKey/42 (version 1.38) KBC firmware. */ + { + .name = "[i430HX] Acer V35N", + .internal_name = "acerv35n", + .type = MACHINE_TYPE_SOCKET7_3V, + .chipset = MACHINE_CHIPSET_INTEL_430HX, + .init = machine_at_acerv35n_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET5_7, + .block = CPU_BLOCK_NONE, + .min_bus = 50000000, + .max_bus = 66666667, + .min_voltage = 3450, + .max_voltage = 3520, + .min_multi = 1.5, + .max_multi = 3.0 + }, + .bus_flags = MACHINE_PS2_PCI, + .flags = MACHINE_IDE_DUAL | MACHINE_APM, + .ram = { + .min = 8192, + .max = 196608, + .step = 8192 + }, + .nvrmask = 511, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* Has AMIKey-2 or VIA VT82C42N KBC (depending on the revision) with AMIKEY 'F' KBC firmware. */ { .name = "[i430HX] AOpen AP53", @@ -10847,89 +10889,8 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* [TEST] The board doesn't seem to have a KBC at all, which probably means it's an on-chip one on the PC87306 SIO. - A list on a Danish site shows the BIOS as having a -0 string, indicating non-AMI KBC firmware. */ - { - .name = "[i430HX] Supermicro P55T2S", - .internal_name = "p55t2s", - .type = MACHINE_TYPE_SOCKET7_3V, - .chipset = MACHINE_CHIPSET_INTEL_430HX, - .init = machine_at_p55t2s_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET5_7, - .block = CPU_BLOCK_NONE, - .min_bus = 50000000, - .max_bus = 66666667, - .min_voltage = 3300, - .max_voltage = 3520, - .min_multi = 1.5, - .max_multi = 3.0 - }, - .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, - .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, - .ram = { - .min = 8192, - .max = 786432, - .step = 8192 - }, - .nvrmask = 255, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, /* 430VX */ - /* Has AMIKey H KBC firmware (AMIKey-2). */ - { - .name = "[i430VX] ECS P5VX-B", - .internal_name = "p5vxb", - .type = MACHINE_TYPE_SOCKET7_3V, - .chipset = MACHINE_CHIPSET_INTEL_430VX, - .init = machine_at_p5vxb_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET5_7, - .block = CPU_BLOCK_NONE, - .min_bus = 50000000, - .max_bus = 66666667, - .min_voltage = 3380, - .max_voltage = 3520, - .min_multi = 1.5, - .max_multi = 3.0 - }, - .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, - .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, - .ram = { - .min = 8192, - .max = 131072, - .step = 8192 - }, - .nvrmask = 127, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, /* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI MegaKey (revision '5') KBC firmware. */ { @@ -11219,48 +11180,6 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* Has SST Flash. */ - /* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix - MultiKey/42 (version 1.38) KBC firmware. */ - { - .name = "[i430HX] Acer V35N", - .internal_name = "acerv35n", - .type = MACHINE_TYPE_SOCKET7, - .chipset = MACHINE_CHIPSET_INTEL_430HX, - .init = machine_at_acerv35n_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET5_7, - .block = CPU_BLOCK(CPU_Cx6x86MX), - .min_bus = 50000000, - .max_bus = 66666667, - .min_voltage = 2800, - .max_voltage = 3520, - .min_multi = 1.5, - .max_multi = 3.0 - }, - .bus_flags = MACHINE_PS2_PCI, - .flags = MACHINE_IDE_DUAL | MACHINE_APM, - .ram = { - .min = 8192, - .max = 196608, - .step = 8192 - }, - .nvrmask = 511, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, /* Has AMIKey H KBC firmware (AMIKey-2). */ { .name = "[i430HX] ASUS P/I-P55T2P4", @@ -11301,6 +11220,46 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* The base board has a Holtek HT6542B with the AMIKey-2 (updated 'H') KBC firmware. */ + { + .name = "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)", + .internal_name = "p65up5_cp55t2d", + .type = MACHINE_TYPE_SOCKET7, + .chipset = MACHINE_CHIPSET_INTEL_430HX, + .init = machine_at_p65up5_cp55t2d_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET5_7, + .block = CPU_BLOCK_NONE, + .min_bus = 50000000, + .max_bus = 66666667, + .min_voltage = 2500, + .max_voltage = 3520, + .min_multi = 1.5, + .max_multi = 3.0 + }, + .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Machine has AMB */ + .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, + .ram = { + .min = 8192, + .max = 524288, + .step = 8192 + }, + .nvrmask = 127, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix MultiKey/42 (version 1.38) KBC firmware. */ { @@ -11547,13 +11506,14 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* The base board has a Holtek HT6542B with the AMIKey-2 (updated 'H') KBC firmware. */ + /* [TEST] The board doesn't seem to have a KBC at all, which probably means it's an on-chip one on the PC87306 SIO. + A list on a Danish site shows the BIOS as having a -0 string, indicating non-AMI KBC firmware. */ { - .name = "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)", - .internal_name = "p65up5_cp55t2d", + .name = "[i430HX] Supermicro P55T2S", + .internal_name = "p55t2s", .type = MACHINE_TYPE_SOCKET7, .chipset = MACHINE_CHIPSET_INTEL_430HX, - .init = machine_at_p65up5_cp55t2d_init, + .init = machine_at_p55t2s_init, .p1_handler = NULL, .gpio_handler = NULL, .available_flag = MACHINE_AVAILABLE, @@ -11563,59 +11523,19 @@ const machine_t machines[] = { .block = CPU_BLOCK_NONE, .min_bus = 50000000, .max_bus = 66666667, - .min_voltage = 2500, + .min_voltage = 2800, .max_voltage = 3520, .min_multi = 1.5, .max_multi = 3.0 }, - .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Machine has AMB */ + .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, .ram = { .min = 8192, - .max = 524288, + .max = 786432, .step = 8192 }, - .nvrmask = 127, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, - /* Unknown PS/2 KBC. */ - { - .name = "[i430HX] Radisys EPC-2102", - .internal_name = "epc2102", - .type = MACHINE_TYPE_SOCKET7, - .chipset = MACHINE_CHIPSET_INTEL_430HX, - .init = machine_at_epc2102_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET5_7, - .block = CPU_BLOCK_NONE, - .min_bus = 50000000, - .max_bus = 83333333, - .min_voltage = 2500, - .max_voltage = 3520, - .min_multi = 1.5, - .max_multi = 3.0 - }, - .bus_flags = MACHINE_PS2_PCI, - .flags = MACHINE_IDE_DUAL | MACHINE_APM, - .ram = { - .min = 8192, - .max = 262144, - .step = 8192 - }, - .nvrmask = 127, + .nvrmask = 255, .kbc_device = NULL, .kbc_p1 = 0xff, .gpio = 0xffffffff, @@ -11913,6 +11833,46 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* Has AMIKey H KBC firmware (AMIKey-2). */ + { + .name = "[i430VX] ECS P5VX-B", + .internal_name = "p5vxb", + .type = MACHINE_TYPE_SOCKET7, + .chipset = MACHINE_CHIPSET_INTEL_430VX, + .init = machine_at_p5vxb_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET5_7, + .block = CPU_BLOCK_NONE, + .min_bus = 50000000, + .max_bus = 66666667, + .min_voltage = 2500, + .max_voltage = 3520, + .min_multi = 1.5, + .max_multi = 3.0 + }, + .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, + .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, + .ram = { + .min = 8192, + .max = 131072, + .step = 8192 + }, + .nvrmask = 127, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI MegaKey (revision '5') KBC firmware. */ { From 9cee5b41af81496e3c61bc37cc9c54e1d8e04673 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 19:20:00 +0200 Subject: [PATCH 31/36] And the 486's. --- src/machine/machine_table.c | 248 ++++++++++++++++++------------------ 1 file changed, 124 insertions(+), 124 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 673c9997d..b154437e4 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -5752,50 +5752,6 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. - It also has those Ex commands also seen on the VIA VT82C42N (the BIOS - supposedly sends command EF. - The board was also seen in 2003 with a -H string - perhaps someone swapped - the KBC? */ - { - .name = "[ALi M1429] Olystar LIL1429", - .internal_name = "ali1429", - .type = MACHINE_TYPE_486, - .chipset = MACHINE_CHIPSET_ALI_M1429, - .init = machine_at_ali1429_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET1, - .block = CPU_BLOCK_NONE, - .min_bus = 0, - .max_bus = 0, - .min_voltage = 0, - .max_voltage = 0, - .min_multi = 0, - .max_multi = 0 - }, - .bus_flags = MACHINE_VLB, - .flags = MACHINE_APM, - .ram = { - .min = 1024, - .max = 32768, - .step = 1024 - }, - .nvrmask = 127, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, /* Has JetKey 5 KBC Firmware - but the BIOS string ends in a hardcoded -F, and the BIOS also explicitly expects command A1 to return a 'F', so it looks like the JetKey 5 is a clone of AMIKey type F. */ @@ -6000,86 +5956,6 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* Uses an NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware. */ - { - .name = "[SiS 461] Acer V10", - .internal_name = "acerv10", - .type = MACHINE_TYPE_486, - .chipset = MACHINE_CHIPSET_SIS_461, - .init = machine_at_acerv10_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET1, - .block = CPU_BLOCK_NONE, - .min_bus = 0, - .max_bus = 0, - .min_voltage = 0, - .max_voltage = 0, - .min_multi = 0, - .max_multi = 0 - }, - .bus_flags = MACHINE_PS2_VLB, - .flags = MACHINE_IDE | MACHINE_APM, /* Machine has internal SCSI: Adaptec AIC-6360 */ - .ram = { - .min = 1024, - .max = 32768, - .step = 1024 - }, - .nvrmask = 127, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, - /* Has MR (!) KBC firmware, which is a clone of the standard IBM PS/2 KBC firmware. */ - { - .name = "[SiS 471] SiS VL-BUS 471 REV. A1", - .internal_name = "px471", - .type = MACHINE_TYPE_486, - .chipset = MACHINE_CHIPSET_SIS_471, - .init = machine_at_px471_init, - .p1_handler = NULL, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET1, - .block = CPU_BLOCK_NONE, - .min_bus = 0, - .max_bus = 0, - .min_voltage = 0, - .max_voltage = 0, - .min_multi = 0, - .max_multi = 0 - }, - .bus_flags = MACHINE_VLB, - .flags = MACHINE_IDE | MACHINE_APM, - .ram = { - .min = 1024, - .max = 131072, - .step = 1024 - }, - .nvrmask = 127, - .kbc_device = NULL, - .kbc_p1 = 0xff, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = NULL, - .net_device = NULL - }, /* The chip is a Lance LT38C41, a clone of the Intel 8041, and the BIOS sends commands BC, BD, and C9 which exist on both AMIKey and Phoenix MultiKey/42, but it does not write a byte after C9, which is consistent with AMIKey, so @@ -6366,6 +6242,50 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. + It also has those Ex commands also seen on the VIA VT82C42N (the BIOS + supposedly sends command EF. + The board was also seen in 2003 with a -H string - perhaps someone swapped + the KBC? */ + { + .name = "[ALi M1429] Olystar LIL1429", + .internal_name = "ali1429", + .type = MACHINE_TYPE_486_S2, + .chipset = MACHINE_CHIPSET_ALI_M1429, + .init = machine_at_ali1429_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET3, + .block = CPU_BLOCK_NONE, + .min_bus = 0, + .max_bus = 0, + .min_voltage = 0, + .max_voltage = 0, + .min_multi = 0, + .max_multi = 0 + }, + .bus_flags = MACHINE_VLB, + .flags = MACHINE_APM, + .ram = { + .min = 1024, + .max = 32768, + .step = 1024 + }, + .nvrmask = 127, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* This has a standalone AMI Megakey 1993, which is type 'P'. */ { .name = "[IMS 8848] Tekram G486IP", @@ -6811,6 +6731,46 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* Uses an NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware. */ + { + .name = "[SiS 461] Acer V10", + .internal_name = "acerv10", + .type = MACHINE_TYPE_486_S3, + .chipset = MACHINE_CHIPSET_SIS_461, + .init = machine_at_acerv10_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET3, + .block = CPU_BLOCK_NONE, + .min_bus = 0, + .max_bus = 0, + .min_voltage = 0, + .max_voltage = 0, + .min_multi = 0, + .max_multi = 0 + }, + .bus_flags = MACHINE_PS2_VLB, + .flags = MACHINE_IDE | MACHINE_APM, /* Machine has internal SCSI: Adaptec AIC-6360 */ + .ram = { + .min = 1024, + .max = 32768, + .step = 1024 + }, + .nvrmask = 127, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* The BIOS string ends in -U, unless command 0xA1 (AMIKey get version) returns an 'F', in which case, it ends in -F, so it has an AMIKey F KBC firmware. The photo of the board shows an AMIKey KBC which is indeed F. */ @@ -7013,6 +6973,46 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* Has MR (!) KBC firmware, which is a clone of the standard IBM PS/2 KBC firmware. */ + { + .name = "[SiS 471] SiS VL-BUS 471 REV. A1", + .internal_name = "px471", + .type = MACHINE_TYPE_486_S3, + .chipset = MACHINE_CHIPSET_SIS_471, + .init = machine_at_px471_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET3, + .block = CPU_BLOCK_NONE, + .min_bus = 0, + .max_bus = 0, + .min_voltage = 0, + .max_voltage = 0, + .min_multi = 0, + .max_multi = 0 + }, + .bus_flags = MACHINE_VLB, + .flags = MACHINE_IDE | MACHINE_APM, + .ram = { + .min = 1024, + .max = 131072, + .step = 1024 + }, + .nvrmask = 127, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* TriGem AMIBIOS Pre-Color with TriGem AMI 'Z' keyboard controller */ { .name = "[SiS 471] TriGem 486G", From 06877f97c7731487f58a01804d8b3c79d71a7754 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 19:53:45 +0200 Subject: [PATCH 32/36] Reverted the accidental removal of the RadiSys. --- src/machine/machine_table.c | 44 +++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index b154437e4..5710ac283 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -12079,6 +12079,50 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* Unknown PS/2 KBC. */ + { + .name = "[i430HX] Radisys EPC-2102", + .internal_name = "epc2102", + .type = MACHINE_TYPE_SOCKET7, + .chipset = MACHINE_CHIPSET_INTEL_430HX, + .init = machine_at_epc2102_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET5_7, + .block = CPU_BLOCK_NONE, + .min_bus = 50000000, + .max_bus = 83333333, + .min_voltage = 2500, + .max_voltage = 3520, + .min_multi = 1.5, + .max_multi = 3.0 + }, + .bus_flags = MACHINE_PS2_PCI, + .flags = MACHINE_IDE_DUAL | MACHINE_APM, + .ram = { + .min = 8192, + .max = 262144, + .max = 786432, + .step = 8192 + }, + .nvrmask = 127, + .nvrmask = 255, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .snd_device = NULL, + .net_device = NULL + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* This has a Holtek KBC and the BIOS does not send a single non-standard KBC command, so it must be an ASIC that clones the standard IBM PS/2 KBC. */ { From 5453f2c3b72edbe8fbb6e32a09830d4ece58f0b7 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 19:58:21 +0200 Subject: [PATCH 33/36] Fixed a compile-breaking mistake in machine_table.c. --- src/machine/machine_table.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 5710ac283..c02d67886 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -12113,8 +12113,6 @@ const machine_t machines[] = { .kbc_device = NULL, .kbc_p1 = 0xff, .gpio = 0xffffffff, - .snd_device = NULL, - .net_device = NULL .gpio_acpi = 0xffffffff, .device = NULL, .fdc_device = NULL, From 93b5c2f5d44e57c9336a108965921b92bd9e4809 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Jul 2024 20:03:43 +0200 Subject: [PATCH 34/36] RadiSys EPC-2012: Give it a different keyboard controllers, fixes CMOS settings saving. --- src/machine/m_at_socket7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/m_at_socket7.c b/src/machine/m_at_socket7.c index d13f0039a..b921b9a4e 100644 --- a/src/machine/m_at_socket7.c +++ b/src/machine/m_at_socket7.c @@ -454,7 +454,7 @@ machine_at_epc2102_init(const machine_t *model) pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); device_add(&i430hx_device); device_add(&piix3_device); - device_add(&keyboard_ps2_pci_device); + device_add(&keyboard_ps2_intel_ami_pci_device); device_add(&i82091aa_device); device_add(&intel_flash_bxt_device); From ec6cb0091868a1a98fee63a11bae6dad46c81b11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Thu, 25 Jul 2024 20:21:11 +0200 Subject: [PATCH 35/36] Update machine_table.c --- src/machine/machine_table.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index c02d67886..ba3c6ca88 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -5486,8 +5486,8 @@ const machine_t machines[] = { .block = CPU_BLOCK_NONE, .min_bus = 0, .max_bus = 0, - .min_voltage = 0, - .max_voltage = 0, + .min_voltage = 5000, + .max_voltage = 5000, .min_multi = 0, .max_multi = 0 }, From ae01932e3b160a5daf1f4c13170acaad0f1b7c76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Thu, 25 Jul 2024 20:25:42 +0200 Subject: [PATCH 36/36] Update machine_table.c --- src/machine/machine_table.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index ba3c6ca88..9b13c9234 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -5484,8 +5484,8 @@ const machine_t machines[] = { .cpu = { .package = CPU_PKG_386DX | CPU_PKG_SOCKET1, .block = CPU_BLOCK_NONE, - .min_bus = 0, - .max_bus = 0, + .min_bus = 25000000, + .max_bus = 66666667, .min_voltage = 5000, .max_voltage = 5000, .min_multi = 0,