diff --git a/src/86box.c b/src/86box.c index fdfdcf1e8..2825535fd 100644 --- a/src/86box.c +++ b/src/86box.c @@ -408,84 +408,6 @@ pclog_ex_cyclic(const char* fmt, va_list ap) cyclic_last_line++; - /* - This version sucks - bool is_cycle = false; - - uint32_t repeat_order = 0; - - for (int32_t log_line = 0; log_line < (LOG_SIZE_BUFFER_CYCLIC); log_line++) - { - for (int32_t check_size = 1; check_size < (LOG_SIZE_BUFFER_CYCLIC / 2); check_size++) - { - uint32_t log_to_check = log_line + check_size; - - // Loop around - if (log_to_check >= LOG_SIZE_BUFFER_CYCLIC) - log_to_check %= LOG_SIZE_BUFFER_CYCLIC; - - // find an initial repeat - if (cyclic_buff[log_line][0] != '\0' - || cyclic_buff[log_to_check][0] != '\0') - { - if (!strncmp(cyclic_buff[log_line], cyclic_buff[log_to_check], LOG_SIZE_BUFFER)) - { - // now see if there are actually repeats (loop over to the start of the log...) - - int32_t highest_real_loop = 1; - - for (int32_t loop_chk = 1; loop_chk < check_size; loop_chk++) - { - uint32_t log_to_check_1 = log_line + loop_chk; - uint32_t log_to_check_2 = (log_line + loop_chk) + check_size; - - if (log_to_check_1 >= LOG_SIZE_BUFFER_CYCLIC) - log_to_check_1 %= LOG_SIZE_BUFFER_CYCLIC; - - if (log_to_check_2 >= LOG_SIZE_BUFFER_CYCLIC) - log_to_check_2 %= LOG_SIZE_BUFFER_CYCLIC; - - if (!strncmp(cyclic_buff[log_to_check_1], cyclic_buff[log_to_check_2], LOG_SIZE_BUFFER)) - { - is_cycle = true; - repeat_order = check_size; - break; - } - } - - - } - - } - - if (is_cycle) break; - } - - if (is_cycle) break; - } - - if (is_cycle - && cyclic_last_line % repeat_order == 0) - { - log_cycles++; - } - else if (!is_cycle) - log_cycles = 0; - - - if (log_cycles <= 1) - { - strcpy(buff, temp); - fprintf(stdlog, "%s", temp); - } - else - { - if (cyclic_last_line % repeat_order == 0) - fprintf(stdlog, "***** Cyclical Log Repeat %d *****\n", log_cycles); - } - - fflush(stdlog); -*/ #endif } diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 0e80eb23b..f2d28eaf9 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -199,9 +199,26 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CONFIG_0 0x2200 #define NV3_PFIFO_CONFIG_0_DMA_FETCH 8 + #define NV3_PFIFO_CONFIG_RAMHT 0x2210 // Hashtable for graphics objects config -#define NV3_PFIFO_CONFIG_RAMRO 0x2214 -#define NV3_PFIFO_CONFIG_RAMFC 0x2218 +#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 +#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS_DEFAULT 0x0 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 +#define NV3_PFIFO_CONFIG_RAMHT_4K 0x0 +#define NV3_PFIFO_CONFIG_RAMHT_8K 0x1 +#define NV3_PFIFO_CONFIG_RAMHT_16K 0x2 +#define NV3_PFIFO_CONFIG_RAMHT_32K 0x3 + +#define NV3_PFIFO_CONFIG_RAMFC 0x2214 +#define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS 9 +#define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS_DEFAULT 0x1C00 // Hardcoded in silicon? + +#define NV3_PFIFO_CONFIG_RAMRO 0x2218 +#define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS 9 +#define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS_DEFAULT 0x1E00 // Hardcoded in silicon? +#define NV3_PFIFO_CONFIG_RAMRO_SIZE 16 +#define NV3_PFIFO_CONFIG_RAMRO_SIZE_512B 0x0 +#define NV3_PFIFO_CONFIG_RAMRO_SIZE_8K 0x1 #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem @@ -1001,8 +1018,8 @@ uint32_t nv3_user_read(uint32_t address); void nv3_user_write(uint32_t address, uint32_t value); #define nv3_object_submit_start nv3_user_read #define nv3_object_submit_end nv3_user_write -uint32_t nv3_pramin_read(uint32_t address); -void nv3_pramin_write(uint32_t address, uint32_t value); +uint32_t nv3_pramin_arbitrate_read(uint32_t address); +void nv3_pramin_arbitrate_write(uint32_t address, uint32_t value); // TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* // GPU subsystems diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index ee8fe048d..22da49b20 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -104,7 +104,7 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - ret = nv3_pramin_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function + ret = nv3_pramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); @@ -167,7 +167,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) else if (address >= NV3_USER_START && address <= NV3_USER_END) nv3_user_write(address, value); else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - nv3_pramin_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions + nv3_pramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions else { nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); @@ -201,6 +201,4 @@ uint32_t nv3_vram_read(uint32_t address) { return 0; }; void nv3_vram_write(uint32_t address, uint32_t value) {}; uint32_t nv3_user_read(uint32_t address) { return 0; }; -void nv3_user_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_pramin_read(uint32_t address) { return 0; }; -void nv3_pramin_write(uint32_t address, uint32_t value) {}; \ No newline at end of file +void nv3_user_write(uint32_t address, uint32_t value) {}; \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 97d5e6f0e..931244b20 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -37,6 +37,9 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL}, { NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,}, + { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, + { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, + { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -90,6 +93,16 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_INTR_EN: ret = nv3->pfifo.interrupt_enable; break; + // These may need to become functions. + case NV3_PFIFO_CONFIG_RAMFC: + ret = nv3->pfifo.ramfc_config; + break; + case NV3_PFIFO_CONFIG_RAMHT: + ret = nv3->pfifo.ramht_config; + break; + case NV3_PFIFO_CONFIG_RAMRO: + ret = nv3->pfifo.ramro_config; + break; } } @@ -149,6 +162,46 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_INTR_EN: nv3->pbus.interrupt_enable = value & 0x00001111; break; + case NV3_PFIFO_CONFIG_RAMHT: + nv3->pfifo.ramht_config = value; +// This code sucks a bit fix it later +#ifdef ENABLE_NV_LOG + uint32_t new_size_ramht = ((value >> 16) & 0x03); + + if (new_size_ramht == 0) + new_size_ramht = 0x1000; + else if (new_size_ramht == 1) + new_size_ramht = 0x2000; + else if (new_size_ramht == 2) + new_size_ramht = 0x4000; + else if (new_size_ramht == 3) + new_size_ramht = 0x8000; + + nv_log("NV3: RAMHT Reconfiguration\n" + "Base Address in RAMIN: %d\n" + "Size: 0x%08x bytes\n", (value >> 12) & 0x1f, new_size_ramht); +#endif + break; + case NV3_PFIFO_CONFIG_RAMFC: + nv3->pfifo.ramfc_config = value; + + nv_log("NV3: RAMFC Reconfiguration\n" + "Base Address in RAMIN: %d\n", (value >> 12) & 0x1f); + break; + case NV3_PFIFO_CONFIG_RAMRO: + nv3->pfifo.ramro_config = value; + + uint32_t new_size_ramro = ((value >> 16) & 0x01); + + if (new_size_ramro == 0) + new_size_ramro = 0x200; + else if (new_size_ramro == 1) + new_size_ramro = 0x2000; + + nv_log("NV3: RAMRO Reconfiguration\n" + "Base Address in RAMIN: %d\n" + "Size: 0x%08x bytes\n", (value >> 12) & 0x1f, new_size_ramro); + break; } } } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index a6561be9d..c5093a175 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -147,3 +147,16 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) nv_log("NV3: Write dword to RAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } + +/* +Arbitrates reads and writes to RAMFC, RAMRO, RAMHT and generic RAMIN +*/ +uint32_t nv3_pramin_arbitrate_read(uint32_t address) +{ + return 0; +} + +void nv3_pramin_arbitrate_write(uint32_t address, uint32_t value) +{ + +} \ No newline at end of file