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Add the AMI Excalibur, a VLB OPTi 596/597 machine.

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Also adds emulation of the OPTi 5x7 chipset, and introduces a clock divider for VLB on 64-bit bus systems.
This commit is contained in:
nerd73
2020-06-05 10:22:59 -06:00
parent 9fb12c323e
commit 3f0adb5211
12 changed files with 175 additions and 15 deletions
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15
src/cpu_common/cpu.c
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@@ -141,7 +141,7 @@ CPU *cpu_s;
int cpu_effective;
int cpu_multi;
double cpu_dmulti;
int cpu_16bitbus;
int cpu_16bitbus, cpu_64bitbus;
int cpu_busspeed;
int cpu_cyrix_alignment;
int CPUID;
@@ -309,7 +309,7 @@ cpu_set(void)
isdx4 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP);
is_am486 = (cpu_s->cpu_type == CPU_Am486SX) || (cpu_s->cpu_type == CPU_Am486SX2) || (cpu_s->cpu_type == CPU_Am486DX) ||
(cpu_s->cpu_type == CPU_Am486DX2) || (cpu_s->cpu_type == CPU_Am486DX4) || (cpu_s->cpu_type == CPU_Am5x86);
is_pentium = (cpu_s->cpu_type == CPU_PENTIUM) || (cpu_s->cpu_type == CPU_PENTIUMMMX);
is_pentium = (cpu_s->cpu_type == CPU_P24T) || (cpu_s->cpu_type == CPU_PENTIUM) || (cpu_s->cpu_type == CPU_PENTIUMMMX);
/* Not Pentiums, but they share the same SMM save state table layout. */
is_pentium |= (cpu_s->cpu_type == CPU_i486DX2) || (cpu_s->cpu_type == CPU_iDX4);
/* The WinChip datasheet claims these are Pentium-compatible. */
@@ -335,7 +335,8 @@ cpu_set(void)
#endif
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC );
cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP);
if (cpu_s->multi)
cpu_busspeed = cpu_s->rspeed / cpu_s->multi;
else
@@ -995,6 +996,7 @@ cpu_set(void)
#endif
break;
case CPU_P24T:
case CPU_PENTIUM:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
@@ -1787,7 +1789,8 @@ cpu_CPUID(void)
break;
}
break;
case CPU_P24T:
case CPU_PENTIUM:
if (!EAX)
{
@@ -2697,6 +2700,7 @@ void cpu_RDMSR()
}
break;
case CPU_P24T:
case CPU_PENTIUM:
case CPU_PENTIUMMMX:
EAX = EDX = 0;
@@ -3175,7 +3179,8 @@ void cpu_WRMSR()
break;
}
break;
case CPU_P24T:
case CPU_PENTIUM:
case CPU_PENTIUMMMX:
switch (ECX)

7
src/cpu_common/cpu.h
View File

@@ -52,6 +52,7 @@ enum {
CPU_Cx486DX4,
CPU_Am5x86,
CPU_Cx5x86,
CPU_P24T,
CPU_WINCHIP, /* 586 class CPUs */
CPU_WINCHIP2,
CPU_PENTIUM,
@@ -370,7 +371,7 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128)
/* Global variables. */
extern int cpu_iscyrix;
extern int cpu_16bitbus;
extern int cpu_16bitbus, cpu_64bitbus;
extern int cpu_busspeed, cpu_pci_speed;
extern int cpu_multi;
extern double cpu_dmulti;
@@ -379,8 +380,8 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4;
extern int is_am486, is_pentium, is_k5, is_k6, is_p6;
extern int hascache;
extern int isibm486;
extern int hascache;
extern int isibm486;
extern int is_rapidcad;
extern int hasfpu;
#define CPU_FEATURE_RDTSC (1 << 0)

4
src/cpu_common/cpu_table.c
View File

@@ -288,8 +288,8 @@ CPU cpus_i486[] = {
{"iDX4/100", CPU_iDX4, 100000000, 3.0, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12},
{"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"Pentium OverDrive 63", CPU_P24T, 62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_P24T, 83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0}
};