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More newline and whitespace cleanups

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This commit is contained in:
Jasmine Iwanek
2022-02-20 02:26:27 -05:00
parent a66e392b26
commit 4674756664
401 changed files with 6985 additions and 6985 deletions
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30
src/codegen/codegen.h
View File

@@ -56,18 +56,18 @@
added to the page_lookup for this purpose. When in the page_lookup, each write
will go through the mem_write_ram*_page() functions and set the dirty mask
appropriately.
Each codeblock also contains a code mask (actually two masks, one for each
page the block is/may be in), again with each bit representing 64 bytes.
Each page has a list of codeblocks present in it. As each codeblock can span
up to two pages, two lists are present.
When a codeblock is about to be executed, the code masks are compared with the
dirty masks for the relevant pages. If either intersect, then
codegen_check_flush() is called on the affected page(s), and all affected
blocks are evicted.
The 64 byte granularity appears to work reasonably well for most cases,
avoiding most unnecessary evictions (eg when code & data are stored in the
same page).
@@ -78,17 +78,17 @@ typedef struct codeblock_t
uint64_t page_mask, page_mask2;
uint64_t *dirty_mask, *dirty_mask2;
uint64_t cmp;
/*Previous and next pointers, for the codeblock list associated with
each physical page. Two sets of pointers, as a codeblock can be
present in two pages.*/
struct codeblock_t *prev, *next;
struct codeblock_t *prev_2, *next_2;
/*Pointers for codeblock tree, used to search for blocks when hash lookup
fails.*/
struct codeblock_t *parent, *left, *right;
int pnt;
int ins;
@@ -116,7 +116,7 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
{
codeblock_t *block = pages[phys >> 12].head;
uint64_t a = _cs | ((uint64_t)phys << 32);
while (block)
{
if (a == block->cmp)
@@ -130,7 +130,7 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
else
block = block->right;
}
return block;
}
@@ -139,7 +139,7 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
codeblock_t *block = pages[new_block->phys >> 12].head;
uint64_t a = new_block->_cs | ((uint64_t)new_block->phys << 32);
new_block->cmp = a;
if (!block)
{
pages[new_block->phys >> 12].head = new_block;
@@ -148,7 +148,7 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
else
{
codeblock_t *old_block = NULL;
while (block)
{
old_block = block;
@@ -157,12 +157,12 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
else
block = block->right;
}
if (a < old_block->cmp)
old_block->left = new_block;
else
old_block->right = new_block;
new_block->parent = old_block;
new_block->left = new_block->right = NULL;
}
@@ -237,7 +237,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
/*Difficult case - node has two children. Walk right child to find lowest node*/
codeblock_t *lowest = block->right, *highest;
codeblock_t *old_parent;
while (lowest->left)
lowest = lowest->left;
@@ -260,7 +260,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
lowest->left->parent = lowest;
old_parent->left = NULL;
highest = lowest->right;
if (!highest)
{

2
src/codegen/codegen_accumulate.h
View File

@@ -1,7 +1,7 @@
enum
{
ACCREG_cycles = 0,
ACCREG_COUNT
};

48
src/codegen/codegen_ops.c
View File

@@ -35,7 +35,7 @@
RecompOpFn recomp_opcodes[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_w_rmw, ropADD_b_rm, ropADD_w_rm, ropADD_AL_imm, ropADD_AX_imm, ropPUSH_ES_16, ropPOP_ES_16, ropOR_b_rmw, ropOR_w_rmw, ropOR_b_rm, ropOR_w_rm, ropOR_AL_imm, ropOR_AX_imm, ropPUSH_CS_16, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_16, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_16, ropPOP_DS_16,
/*20*/ ropAND_b_rmw, ropAND_w_rmw, ropAND_b_rm, ropAND_w_rm, ropAND_AL_imm, ropAND_AX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_w_rmw, ropSUB_b_rm, ropSUB_w_rm, ropSUB_AL_imm, ropSUB_AX_imm, NULL, NULL,
@@ -57,7 +57,7 @@ RecompOpFn recomp_opcodes[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropF6, ropF7_w, NULL, NULL, ropCLI, ropSTI, ropCLD, ropSTD, ropFE, ropFF_16,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_l_rmw, ropADD_b_rm, ropADD_l_rm, ropADD_AL_imm, ropADD_EAX_imm, ropPUSH_ES_32, ropPOP_ES_32, ropOR_b_rmw, ropOR_l_rmw, ropOR_b_rm, ropOR_l_rm, ropOR_AL_imm, ropOR_EAX_imm, ropPUSH_CS_32, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_32, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_32, ropPOP_DS_32,
/*20*/ ropAND_b_rmw, ropAND_l_rmw, ropAND_b_rm, ropAND_l_rm, ropAND_AL_imm, ropAND_EAX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_l_rmw, ropSUB_b_rm, ropSUB_l_rm, ropSUB_AL_imm, ropSUB_EAX_imm, NULL, NULL,
@@ -82,7 +82,7 @@ RecompOpFn recomp_opcodes[512] =
RecompOpFn recomp_opcodes_0f[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -104,7 +104,7 @@ RecompOpFn recomp_opcodes_0f[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -130,7 +130,7 @@ RecompOpFn recomp_opcodes_0f[512] =
RecompOpFn recomp_opcodes_d8[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*10*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*20*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
@@ -152,7 +152,7 @@ RecompOpFn recomp_opcodes_d8[512] =
/*f0*/ ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*10*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*20*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
@@ -177,7 +177,7 @@ RecompOpFn recomp_opcodes_d8[512] =
RecompOpFn recomp_opcodes_d9[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
@@ -199,7 +199,7 @@ RecompOpFn recomp_opcodes_d9[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
@@ -224,7 +224,7 @@ RecompOpFn recomp_opcodes_d9[512] =
RecompOpFn recomp_opcodes_da[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*10*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*20*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
@@ -246,7 +246,7 @@ RecompOpFn recomp_opcodes_da[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*10*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*20*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
@@ -271,7 +271,7 @@ RecompOpFn recomp_opcodes_da[512] =
RecompOpFn recomp_opcodes_db[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -293,7 +293,7 @@ RecompOpFn recomp_opcodes_db[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*80*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -318,7 +318,7 @@ RecompOpFn recomp_opcodes_db[512] =
RecompOpFn recomp_opcodes_dc[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*10*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*20*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
@@ -340,7 +340,7 @@ RecompOpFn recomp_opcodes_dc[512] =
/*f0*/ ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*10*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*20*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
@@ -365,7 +365,7 @@ RecompOpFn recomp_opcodes_dc[512] =
RecompOpFn recomp_opcodes_dd[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -387,7 +387,7 @@ RecompOpFn recomp_opcodes_dd[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -412,7 +412,7 @@ RecompOpFn recomp_opcodes_dd[512] =
RecompOpFn recomp_opcodes_de[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*10*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*20*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
@@ -434,7 +434,7 @@ RecompOpFn recomp_opcodes_de[512] =
/*f0*/ ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*10*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*20*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
@@ -459,7 +459,7 @@ RecompOpFn recomp_opcodes_de[512] =
RecompOpFn recomp_opcodes_df[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
@@ -481,7 +481,7 @@ RecompOpFn recomp_opcodes_df[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
@@ -506,7 +506,7 @@ RecompOpFn recomp_opcodes_df[512] =
RecompOpFn recomp_opcodes_REPE[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -528,7 +528,7 @@ RecompOpFn recomp_opcodes_REPE[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -553,7 +553,7 @@ RecompOpFn recomp_opcodes_REPE[512] =
RecompOpFn recomp_opcodes_REPNE[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -575,7 +575,7 @@ RecompOpFn recomp_opcodes_REPNE[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

112
src/codegen/codegen_ops_arith.h
View File

@@ -1,11 +1,11 @@
static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
// ADD_HOST_REG_IMM_W(host_reg, 1);
INC_HOST_REG_W(host_reg);
@@ -13,7 +13,7 @@ static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc;
@@ -23,9 +23,9 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
// ADD_HOST_REG_IMM(host_reg, 1);
INC_HOST_REG(host_reg);
@@ -41,11 +41,11 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
// SUB_HOST_REG_IMM_W(host_reg, 1);
DEC_HOST_REG_W(host_reg);
@@ -61,11 +61,11 @@ static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
// SUB_HOST_REG_IMM(host_reg, 1);
DEC_HOST_REG(host_reg);
@@ -474,10 +474,10 @@ static uint32_t ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -488,9 +488,9 @@ static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -503,9 +503,9 @@ static uint32_t ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
ADD_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
@@ -518,23 +518,23 @@ static uint32_t ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -547,9 +547,9 @@ static uint32_t ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
@@ -562,9 +562,9 @@ static uint32_t ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
@@ -576,9 +576,9 @@ static uint32_t ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -591,9 +591,9 @@ static uint32_t ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
SUB_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
@@ -603,7 +603,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -629,7 +629,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
host_reg = LOAD_REG_B(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -663,8 +663,8 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
break;
}
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -679,7 +679,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -689,10 +689,10 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -715,7 +715,7 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xffff;
}
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -749,8 +749,8 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -765,7 +765,7 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 3;
}
@@ -774,10 +774,10 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -799,7 +799,7 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
host_reg = LOAD_REG_L(fetchdat & 7);
}
imm = fastreadl(cs + op_pc + 1);
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -833,8 +833,8 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -849,7 +849,7 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 5;
}
@@ -859,10 +859,10 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -888,7 +888,7 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if (imm & 0x80)
imm |= 0xff80;
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -922,8 +922,8 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -938,7 +938,7 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -950,7 +950,7 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -976,7 +976,7 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if (imm & 0x80)
imm |= 0xffffff80;
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -1010,8 +1010,8 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)

132
src/codegen/codegen_ops_fpu.h
View File

@@ -3,7 +3,7 @@ static uint32_t ropFXCH(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
FP_ENTER();
FP_FXCH(opcode & 7);
return op_pc;
}
@@ -12,7 +12,7 @@ static uint32_t ropFLD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
FP_ENTER();
FP_FLD(opcode & 7);
return op_pc;
}
@@ -21,7 +21,7 @@ static uint32_t ropFST(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
FP_ENTER();
FP_FST(opcode & 7);
return op_pc;
}
static uint32_t ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -30,7 +30,7 @@ static uint32_t ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
FP_FST(opcode & 7);
FP_POP();
return op_pc;
}
@@ -38,13 +38,13 @@ static uint32_t ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -55,13 +55,13 @@ static uint32_t ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
@@ -73,13 +73,13 @@ static uint32_t ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
@@ -90,13 +90,13 @@ static uint32_t ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -107,20 +107,20 @@ static uint32_t ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
FP_LOAD_IQ();
codegen_fpu_loaded_iq[(cpu_state.TOP - 1) & 7] = 1;
return op_pc + 1;
}
@@ -128,7 +128,7 @@ static uint32_t ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
x86seg *target_seg;
int host_reg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -138,7 +138,7 @@ static uint32_t ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
return op_pc + 1;
@@ -147,7 +147,7 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
x86seg *target_seg;
int host_reg1, host_reg2 = 0;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -158,7 +158,7 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 7);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
return op_pc + 1;
@@ -167,17 +167,17 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFSTPs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFSTs(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t ropFSTPd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFSTd(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
@@ -260,13 +260,13 @@ ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
/*static uint32_t ropFADDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -277,13 +277,13 @@ ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
static uint32_t ropFDIVs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -294,13 +294,13 @@ static uint32_t ropFDIVs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFMULs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -311,13 +311,13 @@ static uint32_t ropFMULs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFSUBs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -331,49 +331,49 @@ static uint32_t ropFADD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
FP_ENTER();
FP_OP_REG(FPU_ADD, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFCOM(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
return op_pc;
}
static uint32_t ropFDIV(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFDIVR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFMUL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFSUB(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFSUBR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, 0, opcode & 7);
return op_pc;
}
@@ -381,42 +381,42 @@ static uint32_t ropFADDr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
{
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFDIVr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFDIVRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFMULr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFSUBr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFSUBRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
return op_pc;
}
@@ -425,7 +425,7 @@ static uint32_t ropFADDP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -433,7 +433,7 @@ static uint32_t ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
FP_POP();
return op_pc;
}
static uint32_t ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -441,7 +441,7 @@ static uint32_t ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -449,7 +449,7 @@ static uint32_t ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -457,7 +457,7 @@ static uint32_t ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -465,7 +465,7 @@ static uint32_t ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -473,7 +473,7 @@ static uint32_t ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
FP_POP();
return op_pc;
}
@@ -482,18 +482,18 @@ static uint32_t ropFCOMPP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
FP_ENTER();
FP_COMPARE_REG(0, 1);
FP_POP2();
return op_pc;
}
static uint32_t ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
FP_ENTER();
host_reg = LOAD_VAR_W((uintptr_t)&cpu_state.npxs);
STORE_REG_TARGET_W_RELEASE(host_reg, REG_AX);
return op_pc;
}
@@ -512,7 +512,7 @@ static uint32_t ropFISTw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
return op_pc + 1;
@@ -531,7 +531,7 @@ static uint32_t ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
return op_pc + 1;
@@ -540,17 +540,17 @@ static uint32_t ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFISTPw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFISTw(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t ropFISTPl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFISTl(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -567,11 +567,11 @@ static uint32_t ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
FP_POP();
return op_pc + 1;
}
@@ -585,11 +585,11 @@ static uint32_t ropFLDCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.npxc, 0);
UPDATE_NPXC(0);
return op_pc + 1;
}
static uint32_t ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -605,7 +605,7 @@ static uint32_t ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
host_reg = LOAD_VAR_W((uintptr_t)&cpu_state.npxc);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
return op_pc + 1;
}
@@ -614,7 +614,7 @@ static uint32_t ropFCHS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
FP_ENTER();
FP_FCHS();
return op_pc;
}

28
src/codegen/codegen_ops_jump.h
View File

@@ -6,7 +6,7 @@ static uint32_t ropJMP_r8(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
offset |= 0xffffff00;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+1+offset);
return -1;
}
@@ -15,7 +15,7 @@ static uint32_t ropJMP_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
uint16_t offset = fetchdat & 0xffff;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
return -1;
}
@@ -24,7 +24,7 @@ static uint32_t ropJMP_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
uint32_t offset = fastreadl(cs + op_pc);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
return -1;
}
@@ -42,11 +42,11 @@ static uint32_t ropJCXZ(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
TEST_ZERO_JUMP_L(host_reg, op_pc+1+offset, 0);
}
else
{
{
int host_reg = LOAD_REG_W(REG_CX);
TEST_ZERO_JUMP_W(host_reg, op_pc+1+offset, 0);
}
return op_pc+1;
}
@@ -56,7 +56,7 @@ static uint32_t ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if (offset & 0x80)
offset |= 0xffffff00;
if (op_32 & 0x200)
{
int host_reg = LOAD_REG_L(REG_ECX);
@@ -71,7 +71,7 @@ static uint32_t ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_REG_W_RELEASE(host_reg);
TEST_NONZERO_JUMP_W(host_reg, op_pc+1+offset, 0);
}
return op_pc+1;
}
@@ -87,10 +87,10 @@ static void BRANCH_COND_B(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
int host_reg;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
case FLAGS_ADD8:
@@ -120,7 +120,7 @@ static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int no
else
TEST_ZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
break;
case FLAGS_UNKNOWN:
CALL_FUNC((uintptr_t)ZF_SET);
if (not)
@@ -152,10 +152,10 @@ static void BRANCH_COND_P(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
int host_reg;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:
case FLAGS_ZN8:
case FLAGS_ADD8:
case FLAGS_SUB8:
case FLAGS_SHL8:
@@ -186,7 +186,7 @@ static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int no
else
TEST_NONZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
break;
case FLAGS_ZN32:
case FLAGS_ADD32:
case FLAGS_SUB32:
@@ -202,7 +202,7 @@ static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int no
else
TEST_NONZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
break;
case FLAGS_UNKNOWN:
CALL_FUNC((uintptr_t)NF_SET);
if (not)

72
src/codegen/codegen_ops_logic.h
View File

@@ -275,9 +275,9 @@ static uint32_t ropAND_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xff) | 0xffffff00);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -286,9 +286,9 @@ static uint32_t ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xffff) | 0xffff0000);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -298,9 +298,9 @@ static uint32_t ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
fetchdat = fastreadl(cs + op_pc);
AND_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
@@ -310,9 +310,9 @@ static uint32_t ropOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
OR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -321,9 +321,9 @@ static uint32_t ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
OR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -333,9 +333,9 @@ static uint32_t ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
fetchdat = fastreadl(cs + op_pc);
OR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
@@ -345,9 +345,9 @@ static uint32_t ropTEST_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 1;
}
static uint32_t ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -356,9 +356,9 @@ static uint32_t ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
}
static uint32_t ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -368,9 +368,9 @@ static uint32_t ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
fetchdat = fastreadl(cs + op_pc);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 4;
}
@@ -380,9 +380,9 @@ static uint32_t ropXOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -391,9 +391,9 @@ static uint32_t ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -403,9 +403,9 @@ static uint32_t ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
fetchdat = fastreadl(cs + op_pc);
XOR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
@@ -414,7 +414,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
x86seg *target_seg;
int host_reg;
uint8_t imm;
switch (fetchdat & 0x38)
{
case 0x00: /*TEST b,#8*/
@@ -433,7 +433,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
@@ -457,7 +457,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -465,7 +465,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
x86seg *target_seg;
int host_reg;
uint16_t imm;
switch (fetchdat & 0x38)
{
case 0x00: /*TEST w,#*/
@@ -484,7 +484,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 3;
@@ -508,7 +508,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -516,7 +516,7 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
x86seg *target_seg;
int host_reg;
uint32_t imm;
switch (fetchdat & 0x38)
{
case 0x00: /*TEST l,#*/
@@ -535,7 +535,7 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 5;
@@ -559,6 +559,6 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}

20
src/codegen/codegen_ops_misc.h
View File

@@ -41,7 +41,7 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
return 0;
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_B(fetchdat & 7);
else
@@ -53,7 +53,7 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
MEM_CHECK_WRITE(target_seg);
host_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg);
}
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
@@ -80,7 +80,7 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t codegen_temp;
@@ -88,7 +88,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
@@ -114,7 +114,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
}
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
@@ -159,7 +159,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-2);
host_reg = LOAD_VAR_W((uintptr_t)&codegen_temp);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.pc, host_reg);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/
@@ -181,13 +181,13 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
if ((fetchdat & 0x30) == 0x00)
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_L(fetchdat & 7);
else
@@ -207,7 +207,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
}
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
@@ -252,7 +252,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-4);
host_reg = LOAD_VAR_L((uintptr_t)&codegen_temp);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/

42
src/codegen/codegen_ops_mmx.h
View File

@@ -3,9 +3,9 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg1, host_reg2 = 0;
MMX_ENTER();
LOAD_MMX_Q((fetchdat >> 3) & 7, &host_reg1, &host_reg2);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_MMX_Q(fetchdat & 7, host_reg1, host_reg2);
@@ -15,10 +15,10 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 7);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
}
@@ -28,11 +28,11 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropMOVQ_mm_q(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
MMX_ENTER();
if ((fetchdat & 0xc0) == 0xc0)
{
int host_reg1, host_reg2;
LOAD_MMX_Q(fetchdat & 7, &host_reg1, &host_reg2);
STORE_MMX_Q((fetchdat >> 3) & 7, host_reg1, host_reg2);
}
@@ -56,9 +56,9 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg;
MMX_ENTER();
host_reg = LOAD_MMX_D((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
@@ -68,10 +68,10 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 3);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
}
@@ -80,7 +80,7 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropMOVD_mm_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
MMX_ENTER();
if ((fetchdat & 0xc0) == 0xc0)
{
int host_reg = LOAD_REG_L(fetchdat & 7);
@@ -192,9 +192,9 @@ static uint32_t ropPSxxW_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38)
{
@@ -209,7 +209,7 @@ static uint32_t ropPSxxW_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -220,9 +220,9 @@ static uint32_t ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38)
{
@@ -237,7 +237,7 @@ static uint32_t ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -248,9 +248,9 @@ static uint32_t ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38)
{
@@ -265,13 +265,13 @@ static uint32_t ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t ropEMMS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
codegen_mmx_entered = 0;
return 0;
}

104
src/codegen/codegen_ops_mov.h
View File

@@ -1,7 +1,7 @@
static uint32_t ropMOV_rb_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_REG_B(opcode & 7, fetchdat & 0xff);
return op_pc + 1;
}
static uint32_t ropMOV_rw_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -15,7 +15,7 @@ static uint32_t ropMOV_rl_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
fetchdat = fastreadl(cs + op_pc);
STORE_IMM_REG_L(opcode & 7, fetchdat);
return op_pc + 4;
}
@@ -23,7 +23,7 @@ static uint32_t ropMOV_rl_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropMOV_b_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_B_RELEASE(host_reg, fetchdat & 7);
@@ -33,20 +33,20 @@ static uint32_t ropMOV_b_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 0);
MEM_STORE_ADDR_EA_B(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t ropMOV_w_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_W_RELEASE(host_reg, fetchdat & 7);
@@ -56,23 +56,23 @@ static uint32_t ropMOV_w_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 1);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t ropMOV_l_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
host_reg = LOAD_REG_L((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
@@ -82,13 +82,13 @@ static uint32_t ropMOV_l_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 3);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
@@ -106,13 +106,13 @@ static uint32_t ropMOV_r_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
STORE_REG_TARGET_B_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOV_r_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -133,7 +133,7 @@ static uint32_t ropMOV_r_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
MEM_LOAD_ADDR_EA_W(target_seg);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOV_r_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -154,7 +154,7 @@ static uint32_t ropMOV_r_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
MEM_LOAD_ADDR_EA_L(target_seg);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
@@ -220,7 +220,7 @@ static uint32_t ropMOV_l_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 5;
}
@@ -239,7 +239,7 @@ static uint32_t ropMOV_AL_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_LOAD_ADDR_IMM_B(op_ea_seg, addr);
STORE_REG_TARGET_B_RELEASE(0, REG_AL);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_AX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -256,7 +256,7 @@ static uint32_t ropMOV_AX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_LOAD_ADDR_IMM_W(op_ea_seg, addr);
STORE_REG_TARGET_W_RELEASE(0, REG_AX);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_EAX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -273,7 +273,7 @@ static uint32_t ropMOV_EAX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_LOAD_ADDR_IMM_L(op_ea_seg, addr);
STORE_REG_TARGET_L_RELEASE(0, REG_EAX);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
@@ -289,12 +289,12 @@ static uint32_t ropMOV_a_AL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_B(REG_AL);
MEM_STORE_ADDR_IMM_B(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_a_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -309,12 +309,12 @@ static uint32_t ropMOV_a_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_W(REG_AX);
MEM_STORE_ADDR_IMM_W(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_a_EAX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -329,24 +329,24 @@ static uint32_t ropMOV_a_EAX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_L(REG_EAX);
MEM_STORE_ADDR_IMM_L(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropLEA_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_REG_TARGET_W_RELEASE(0, dest_reg);
return op_pc + 1;
@@ -354,12 +354,12 @@ static uint32_t ropLEA_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropLEA_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_REG_TARGET_L_RELEASE(0, dest_reg);
return op_pc + 1;
@@ -378,14 +378,14 @@ static uint32_t ropMOVZX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
ZERO_EXTEND_W_B(0);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVZX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -401,14 +401,14 @@ static uint32_t ropMOVZX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
ZERO_EXTEND_L_B(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVZX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -424,14 +424,14 @@ static uint32_t ropMOVZX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
ZERO_EXTEND_L_W(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
@@ -448,14 +448,14 @@ static uint32_t ropMOVSX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
SIGN_EXTEND_W_B(0);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVSX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -471,14 +471,14 @@ static uint32_t ropMOVSX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
SIGN_EXTEND_L_B(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -494,14 +494,14 @@ static uint32_t ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
SIGN_EXTEND_L_W(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
@@ -532,7 +532,7 @@ static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0)
{
if (op_32 & 0x100)
@@ -545,14 +545,14 @@ static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 1);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -572,7 +572,7 @@ static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_W(fetchdat & 7);
else
@@ -581,10 +581,10 @@ static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
switch (fetchdat & 0x38)
{
case 0x00: /*ES*/
@@ -600,7 +600,7 @@ static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
LOAD_SEG(host_reg, &cpu_state.seg_gs);
break;
}
return op_pc + 1;
}

8
src/codegen/codegen_ops_shift.h
View File

@@ -67,7 +67,7 @@ static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 1);
return op_pc + 2;
}
static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -80,7 +80,7 @@ static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(L, 32, STORE_HOST_REG_ADDR, 1);
return op_pc + 2;
}
@@ -107,7 +107,7 @@ static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 0);
return op_pc + 1;
}
static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -120,6 +120,6 @@ static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(L, 32, STORE_HOST_REG_ADDR, 0);
return op_pc + 1;
}

28
src/codegen/codegen_ops_stack.h
View File

@@ -7,7 +7,7 @@ static uint32_t ropPUSH_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
host_reg = LOAD_REG_W(opcode & 7);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc;
}
static uint32_t ropPUSH_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -33,7 +33,7 @@ static uint32_t ropPUSH_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc+2;
}
static uint32_t ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -46,7 +46,7 @@ static uint32_t ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc+4;
}
@@ -63,7 +63,7 @@ static uint32_t ropPUSH_imm_b16(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc+1;
}
static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -79,7 +79,7 @@ static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc+1;
}
@@ -90,7 +90,7 @@ static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
SP_MODIFY(2);
STORE_REG_TARGET_W_RELEASE(0, opcode & 7);
return op_pc;
}
static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -100,7 +100,7 @@ static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
SP_MODIFY(4);
STORE_REG_TARGET_L_RELEASE(0, opcode & 7);
return op_pc;
}
@@ -111,7 +111,7 @@ static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(2);
return -1;
}
static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -121,7 +121,7 @@ static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(4);
return -1;
}
@@ -134,7 +134,7 @@ static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(2+offset);
return -1;
}
static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -146,7 +146,7 @@ static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(4+offset);
return -1;
}
@@ -161,7 +161,7 @@ static uint32_t ropCALL_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
return -1;
}
static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -175,7 +175,7 @@ static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
return -1;
}
@@ -204,7 +204,7 @@ static uint32_t ropLEAVE_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
ADD_HOST_REG_IMM(host_reg, 4);
STORE_REG_TARGET_L_RELEASE(host_reg, REG_ESP);
STORE_REG_TARGET_L_RELEASE(0, REG_EBP); /*EBP = POP_L()*/
return op_pc;
}

250
src/codegen/codegen_ops_x86-64.h
View File

@@ -16,7 +16,7 @@ static inline int find_host_xmm_reg()
if (host_reg_xmm_mapping[c] == -1)
break;
}
if (c == HOST_REG_XMM_END)
fatal("Out of host XMM regs!\n");
return c;
@@ -236,10 +236,10 @@ static inline int LOAD_REG_B(int reg)
}
codegen_reg_loaded[reg & 3] = 1;
if (reg & 4)
return host_reg | 0x18;
return host_reg | 8;
}
static inline int LOAD_REG_W(int reg)
@@ -255,7 +255,7 @@ static inline int LOAD_REG_W(int reg)
}
codegen_reg_loaded[reg & 7] = 1;
return host_reg | 8;
}
static inline int LOAD_REG_L(int reg)
@@ -271,7 +271,7 @@ static inline int LOAD_REG_L(int reg)
}
codegen_reg_loaded[reg & 7] = 1;
return host_reg | 8;
}
@@ -281,14 +281,14 @@ static inline int LOAD_REG_IMM(uint32_t imm)
addbyte(0xb8 | REG_EBX); /*MOVL EBX, imm*/
addlong(imm);
return host_reg;
}
static inline void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
{
int dest_reg = LOAD_REG_L(guest_reg & 3) & 7;
if (guest_reg & 4)
{
if (host_reg & 8)
@@ -305,7 +305,7 @@ static inline void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0xc0 | ((host_reg & 3) << 3));
}
if (host_reg & 0x10)
{
{
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
@@ -382,7 +382,7 @@ static inline void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
static inline void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
{
int dest_reg = LOAD_REG_L(guest_reg & 7) & 7;
if (host_reg & 8)
{
addbyte(0x66); /*MOVW guest_reg, host_reg*/
@@ -555,8 +555,8 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (!mod && rm == 6)
{
if (!mod && rm == 6)
{
addbyte(0xb8); /*MOVL EAX, imm*/
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
@@ -564,7 +564,7 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
else
{
int base_reg = 0, index_reg = 0;
switch (rm)
{
case 0: case 1: case 7:
@@ -589,7 +589,7 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
base_reg &= 7;
index_reg &= 7;
switch (mod)
{
case 0:
@@ -658,7 +658,7 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
(*op_pc) += 2;
break;
}
if (mod || !(rm & 4))
{
@@ -745,7 +745,7 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
}
else
{
{
switch (mod)
{
case 0:
@@ -823,7 +823,7 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
int base_reg;
if (!mod && rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, new_eaaddr*/
addlong(new_eaaddr);
@@ -831,20 +831,20 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
return op_ea_seg;
}
base_reg = LOAD_REG_L(rm) & 7;
if (mod)
if (mod)
{
if (rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (mod == 1)
if (mod == 1)
{
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
(*op_pc)++;
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, base_reg+imm32*/
@@ -907,7 +907,7 @@ static inline void CHECK_SEG_READ(x86seg *seg)
addbyte(0x0f); /*JE GPF_BLOCK_OFFSET*/
addbyte(0x84);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static inline void CHECK_SEG_WRITE(x86seg *seg)
@@ -922,7 +922,7 @@ static inline void CHECK_SEG_WRITE(x86seg *seg)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
if (IS_32_ADDR(&seg->base))
{
addbyte(0x83); /*CMP seg->base, -1*/
@@ -1740,14 +1740,14 @@ static inline void MEM_STORE_ADDR_IMM_L(x86seg *seg, uint32_t addr, int host_reg
static inline void STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
{
int temp_reg = REG_ECX;
if (host_reg_mapping[REG_ECX] != -1)
temp_reg = REG_EBX;
if (host_reg & 0x10)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
@@ -1758,7 +1758,7 @@ static inline void STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
else
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb6);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
@@ -1788,12 +1788,12 @@ static inline void STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
static inline void STORE_HOST_REG_ADDR_WL(uintptr_t addr, int host_reg)
{
int temp_reg = REG_ECX;
if (host_reg_mapping[REG_ECX] != -1)
temp_reg = REG_EBX;
if (host_reg & 8)
addbyte(0x41);
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
@@ -1980,7 +1980,7 @@ static inline void AND_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*ANDB dst_reg, src_reg*/
addbyte(0x20);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2005,7 +2005,7 @@ static inline void AND_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x20); /*ANDB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void AND_HOST_REG_W(int dst_reg, int src_reg)
@@ -2092,12 +2092,12 @@ static inline int TEST_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = (dst_reg & 0x10) | REG_EDX;
}
AND_HOST_REG_B(dst_reg, src_reg);
return dst_reg & ~0x10;
}
static inline int TEST_HOST_REG_W(int dst_reg, int src_reg)
@@ -2107,12 +2107,12 @@ static inline int TEST_HOST_REG_W(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
AND_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_L(int dst_reg, int src_reg)
@@ -2122,12 +2122,12 @@ static inline int TEST_HOST_REG_L(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
AND_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
@@ -2152,7 +2152,7 @@ static inline int TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
addbyte(0xe0 | (host_reg & 7));
addlong(imm);
}
return host_reg;
}
@@ -2250,7 +2250,7 @@ static inline void OR_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*ORB dst_reg, src_reg*/
addbyte(0x08);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2275,7 +2275,7 @@ static inline void OR_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x08); /*ORB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void OR_HOST_REG_W(int dst_reg, int src_reg)
@@ -2453,7 +2453,7 @@ static inline void XOR_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*XORB dst_reg, src_reg*/
addbyte(0x30);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2478,7 +2478,7 @@ static inline void XOR_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x30); /*XORB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void XOR_HOST_REG_W(int dst_reg, int src_reg)
@@ -2800,7 +2800,7 @@ static inline void SUB_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*SUBB dst_reg, src_reg*/
addbyte(0x28);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2825,7 +2825,7 @@ static inline void SUB_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x28); /*SUBB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void SUB_HOST_REG_W(int dst_reg, int src_reg)
@@ -2892,12 +2892,12 @@ static inline int CMP_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = (dst_reg & 0x10) | REG_EDX;
}
SUB_HOST_REG_B(dst_reg, src_reg);
return dst_reg & ~0x10;
}
static inline int CMP_HOST_REG_W(int dst_reg, int src_reg)
@@ -2907,12 +2907,12 @@ static inline int CMP_HOST_REG_W(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
SUB_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_L(int dst_reg, int src_reg)
@@ -2922,12 +2922,12 @@ static inline int CMP_HOST_REG_L(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
SUB_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
@@ -3045,12 +3045,12 @@ static inline int CMP_HOST_REG_IMM_B(int host_reg, uint8_t imm)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = (host_reg & 0x10) | REG_EDX;
}
SUB_HOST_REG_IMM_B(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
@@ -3060,12 +3060,12 @@ static inline int CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = REG_EDX;
}
SUB_HOST_REG_IMM_W(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
@@ -3075,12 +3075,12 @@ static inline int CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = REG_EDX;
}
SUB_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
@@ -3280,7 +3280,7 @@ static inline void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_
static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
uint8_t *jump1;
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
addbyte(0x83); /*CMP flags_res, 0*/
@@ -3305,7 +3305,7 @@ static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
if (!not)
*jump1 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump1 - 1;
@@ -3346,7 +3346,7 @@ static inline void BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset,
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(pc));
@@ -3400,7 +3400,7 @@ static inline void BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
if (!not)
*jump1 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump1 - 1;
addbyte(0xC7); /*MOVL [pc], new_pc*/
@@ -3490,7 +3490,7 @@ static inline int COPY_REG(int src_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | REG_ECX | ((src_reg & 7) << 3));
return REG_ECX | (src_reg & 0x10);
}
@@ -3500,7 +3500,7 @@ static inline int LOAD_HOST_REG(int host_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | REG_EBX | ((host_reg & 7) << 3));
return REG_EBX | (host_reg & 0x10);
}
@@ -3514,16 +3514,16 @@ static inline int ZERO_EXTEND_W_B(int reg)
addbyte(0x0f); /*MOVZX EAX, AH*/
addbyte(0xb6);
addbyte(0xc4);
return REG_EAX;
}
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int ZERO_EXTEND_L_B(int reg)
@@ -3536,7 +3536,7 @@ static inline int ZERO_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVZX EAX, AH*/
addbyte(0xb6);
addbyte(0xc4);
return REG_EAX;
}
@@ -3545,7 +3545,7 @@ static inline int ZERO_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int ZERO_EXTEND_L_W(int reg)
@@ -3555,7 +3555,7 @@ static inline int ZERO_EXTEND_L_W(int reg)
addbyte(0x0f); /*MOVZX regl, regw*/
addbyte(0xb7);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
@@ -3569,7 +3569,7 @@ static inline int SIGN_EXTEND_W_B(int reg)
addbyte(0x0f); /*MOVSX EAX, AH*/
addbyte(0xbe);
addbyte(0xc4);
return REG_EAX;
}
@@ -3578,7 +3578,7 @@ static inline int SIGN_EXTEND_W_B(int reg)
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int SIGN_EXTEND_L_B(int reg)
@@ -3591,7 +3591,7 @@ static inline int SIGN_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVSX EAX, AH*/
addbyte(0xbe);
addbyte(0xc4);
return REG_EAX;
}
@@ -3600,7 +3600,7 @@ static inline int SIGN_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int SIGN_EXTEND_L_W(int reg)
@@ -3610,7 +3610,7 @@ static inline int SIGN_EXTEND_L_W(int reg)
addbyte(0x0f); /*MOVSX regl, regw*/
addbyte(0xbf);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
@@ -3773,7 +3773,7 @@ static inline void NEG_HOST_REG_L(int reg)
addbyte(0xf7);
addbyte(0xd8 | (reg & 7));
}
static inline void FP_ENTER()
{
@@ -3806,7 +3806,7 @@ static inline void FP_ENTER()
CALL_FUNC((uintptr_t)x86_int);
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
codegen_fpu_entered = 1;
}
@@ -3844,7 +3844,7 @@ static inline void FP_FXCH(int reg)
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
addbyte(0x8a); /*MOV CL, tag[EAX]*/
addbyte(0x4c);
addbyte(0x05);
@@ -3910,7 +3910,7 @@ static inline void FP_FLD(int reg)
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
}
}
addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
addbyte(0x8b);
@@ -4288,8 +4288,8 @@ static inline int FP_LOAD_REG(int reg)
addbyte(0x66); /*MOVD EBX, XMM0*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0xc0 | REG_EBX);
addbyte(0xc0 | REG_EBX);
return REG_EBX;
}
static inline void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
@@ -4311,13 +4311,13 @@ static inline void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
*host_reg1 = REG_EBX;
}
static inline int64_t x87_fround16_64(double b)
{
int16_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -4336,13 +4336,13 @@ static inline int64_t x87_fround16_64(double b)
case 3: /*Chop*/
return (int64_t)((int16_t)b);
}
return 0;
}
static inline int64_t x87_fround32_64(double b)
{
int32_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -4361,13 +4361,13 @@ static inline int64_t x87_fround32_64(double b)
case 3: /*Chop*/
return (int64_t)((int32_t)b);
}
return 0;
}
static inline int64_t x87_fround(double b)
{
int64_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -4386,7 +4386,7 @@ static inline int64_t x87_fround(double b)
case 3: /*Chop*/
return (int64_t)b;
}
return 0;
}
static inline int FP_LOAD_REG_INT_W(int reg)
@@ -4414,9 +4414,9 @@ static inline int FP_LOAD_REG_INT_W(int reg)
addbyte((uint8_t)cpu_state_offset(ST));
CALL_FUNC((uintptr_t)x87_fround16_64);
addbyte(0x93); /*XCHG EBX, EAX*/
return REG_EBX;
}
static inline int FP_LOAD_REG_INT(int reg)
@@ -4444,9 +4444,9 @@ static inline int FP_LOAD_REG_INT(int reg)
addbyte((uint8_t)cpu_state_offset(ST));
CALL_FUNC((uintptr_t)x87_fround32_64);
addbyte(0x93); /*XCHG EBX, EAX*/
return REG_EBX;
}
static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
@@ -4482,16 +4482,16 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x93);
*host_reg1 = REG_EBX;
return;
}
addbyte(0xf6); /*TEST TAG[EAX], TAG_UINT64*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t)cpu_state_offset(tag));
addbyte(TAG_UINT64);
addbyte(0x74); /*JZ +*/
addbyte(5+2);
@@ -4500,7 +4500,7 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t)cpu_state_offset(MM));
addbyte(0xeb); /*JMP done*/
addbyte(6+12);
@@ -4512,10 +4512,10 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte((uint8_t)cpu_state_offset(ST));
CALL_FUNC((uintptr_t)x87_fround);
addbyte(0x48); /*XCHG RBX, RAX*/
addbyte(0x93);
*host_reg1 = REG_EBX;
}
@@ -5015,7 +5015,7 @@ static inline void MMX_ENTER()
{
if (codegen_mmx_entered)
return;
if (IS_32_ADDR(&cr0))
{
addbyte(0xf6); /*TEST cr0, 0xc*/
@@ -5044,7 +5044,7 @@ static inline void MMX_ENTER()
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
addbyte(0x31); /*XOR EAX, EAX*/
addbyte(0xc0);
addbyte(0xc6); /*MOV ISMMX, 1*/
@@ -5054,7 +5054,7 @@ static inline void MMX_ENTER()
addbyte(0x89); /*MOV TOP, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(TOP));
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV tag+4, EAX*/
@@ -5074,7 +5074,7 @@ static inline int LOAD_MMX_D(int guest_reg)
addbyte(0x44 | (host_reg << 3));
addbyte(0x25);
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].l[0]));
return host_reg;
}
static inline void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
@@ -5089,7 +5089,7 @@ static inline void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
addbyte(0x44 | ((host_reg & 7) << 3));
addbyte(0x25);
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].q));
*host_reg1 = host_reg;
}
static inline int LOAD_MMX_Q_MMX(int guest_reg)
@@ -5103,7 +5103,7 @@ static inline int LOAD_MMX_Q_MMX(int guest_reg)
addbyte(0x44 | ((dst_reg & 7) << 3));
addbyte(0x25);
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].q));
return dst_reg;
}
@@ -5111,7 +5111,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0x66); /*MOVQ host_reg, src_reg1*/
if (src_reg1 & 8)
addbyte(0x49);
@@ -5120,7 +5120,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc0 | (dst_reg << 3) | (src_reg1 & 7));
return dst_reg;
}
@@ -5382,7 +5382,7 @@ static inline void LOAD_EA()
static inline void MEM_CHECK_WRITE(x86seg *seg)
{
uint8_t *jump1, *jump2, *jump3 = NULL;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5408,7 +5408,7 @@ static inline void MEM_CHECK_WRITE(x86seg *seg)
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0))
{
addbyte(0x83); /*CMP cr0, 0*/
@@ -5468,7 +5468,7 @@ static inline void MEM_CHECK_WRITE(x86seg *seg)
addbyte(0);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
*jump3 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump3 - 1;
*jump3 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump3 - 1;
/*slowpath:*/
addbyte(0x67); /*LEA EDI, [EAX+ESI]*/
addbyte(0x8d);
@@ -5497,7 +5497,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
{
uint8_t *jump1, *jump2, *jump3, *jump4 = NULL;
int jump_pos;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5523,7 +5523,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0))
{
addbyte(0x83); /*CMP cr0, 0*/
@@ -5610,7 +5610,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
addbyte(0x75); /*JNE +*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
/*slowpath:*/
*jump2 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump2 - 1;
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5646,7 +5646,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
{
uint8_t *jump1, *jump2, *jump3, *jump4 = NULL;
int jump_pos;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5672,7 +5672,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0))
{
addbyte(0x83); /*CMP cr0, 0*/
@@ -5759,7 +5759,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
addbyte(0x75); /*JNE +*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
/*slowpath:*/
*jump2 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump2 - 1;
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5861,7 +5861,7 @@ static inline int MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
@@ -5940,7 +5940,7 @@ static inline int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
@@ -6018,7 +6018,7 @@ static inline int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}

108
src/codegen/codegen_ops_x86.h
View File

@@ -16,7 +16,7 @@ static inline int find_host_reg()
if (host_reg_mapping[c] == -1)
break;
}
if (c == NR_HOST_REGS)
fatal("Out of host regs!\n");
return c;
@@ -29,7 +29,7 @@ static inline int find_host_xmm_reg()
if (host_reg_xmm_mapping[c] == -1)
break;
}
if (c == HOST_REG_XMM_END)
fatal("Out of host XMM regs!\n");
return c;
@@ -151,12 +151,12 @@ static inline int LOAD_VAR_WL(uintptr_t addr)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0x0f); /*MOVZX host_reg, [addr]*/
addbyte(0xb7);
addbyte(0x05 | (host_reg << 3));
addlong((uint32_t)addr);
return host_reg;
}
static inline int LOAD_VAR_L(uintptr_t addr)
@@ -175,11 +175,11 @@ static inline int LOAD_REG_IMM(uint32_t imm)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0xc7); /*MOVL host_reg, imm*/
addbyte(0xc0 | host_reg);
addlong(imm);
return host_reg;
}
@@ -187,10 +187,10 @@ static inline int LOAD_HOST_REG(int host_reg)
{
int new_host_reg = find_host_reg();
host_reg_mapping[new_host_reg] = 0;
addbyte(0x89); /*MOV new_host_reg, host_reg*/
addbyte(0xc0 | (host_reg << 3) | new_host_reg);
return new_host_reg;
}
@@ -366,25 +366,25 @@ static inline void AND_HOST_REG_IMM(int host_reg, uint32_t imm)
static inline int TEST_HOST_REG_B(int dst_reg, int src_reg)
{
AND_HOST_REG_B(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_W(int dst_reg, int src_reg)
{
AND_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_L(int dst_reg, int src_reg)
{
AND_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
{
AND_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
@@ -505,37 +505,37 @@ static inline void DEC_HOST_REG(int host_reg)
static inline int CMP_HOST_REG_B(int dst_reg, int src_reg)
{
SUB_HOST_REG_B(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_W(int dst_reg, int src_reg)
{
SUB_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_L(int dst_reg, int src_reg)
{
SUB_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
SUB_HOST_REG_IMM_B(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
SUB_HOST_REG_IMM_W(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
{
SUB_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
@@ -647,7 +647,7 @@ static inline void CHECK_SEG_READ(x86seg *seg)
addbyte(0x0f);
addbyte(0x84); /*JE BLOCK_GPF_OFFSET*/
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static inline void CHECK_SEG_WRITE(x86seg *seg)
@@ -662,7 +662,7 @@ static inline void CHECK_SEG_WRITE(x86seg *seg)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
addbyte(0x83); /*CMP seg->base, -1*/
addbyte(0x05|0x38);
addlong((uint32_t)&seg->base);
@@ -736,7 +736,7 @@ static inline int MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
addlong(mem_load_addr_ea_b_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline void MEM_LOAD_ADDR_EA_W(x86seg *seg)
@@ -795,7 +795,7 @@ static inline int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
addlong(mem_load_addr_ea_w_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline void MEM_LOAD_ADDR_EA_L(x86seg *seg)
@@ -834,7 +834,7 @@ static inline int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
addlong(mem_load_addr_ea_l_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
@@ -1053,8 +1053,8 @@ static inline x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
{
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (!mod && rm == 6)
{
if (!mod && rm == 6)
{
addbyte(0xb8); /*MOVL EAX, imm16*/
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
@@ -1121,7 +1121,7 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
{
uint8_t sib = fetchdat >> 8;
(*op_pc)++;
switch (mod)
{
case 0:
@@ -1139,7 +1139,7 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
case 1:
addbyte(0x8b); /*MOVL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
@@ -1204,7 +1204,7 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
else
{
if (!mod && rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, imm32*/
addlong(new_eaaddr);
@@ -1215,22 +1215,22 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(regs[rm].l));
cpu_state.eaaddr = cpu_state.regs[rm].l;
if (mod)
if (mod)
{
if (rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (mod == 1)
if (mod == 1)
{
addbyte(0x83); /*ADD EAX, imm8*/
addbyte(0xc0 | REG_EAX);
addbyte((int8_t)(fetchdat >> 8));
(*op_pc)++;
addbyte((int8_t)(fetchdat >> 8));
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x05); /*ADD EAX, imm32*/
addlong(new_eaaddr);
addlong(new_eaaddr);
(*op_pc) += 4;
}
}
@@ -1475,7 +1475,7 @@ static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset
else
addbyte(0x77); /*JNBE*/
break;
default:
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
@@ -1505,7 +1505,7 @@ static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset
addbyte(0x74); /*JZ +*/
break;
}
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(pc));
@@ -1706,7 +1706,7 @@ static inline void FP_ENTER()
{
if (codegen_fpu_entered)
return;
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x05);
addlong((uintptr_t)&cr0);
@@ -1725,7 +1725,7 @@ static inline void FP_ENTER()
addlong((uint32_t)x86_int - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
codegen_fpu_entered = 1;
}
@@ -1788,7 +1788,7 @@ static inline void FP_FLD(int reg)
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
}
}
addbyte(0xdd); /*FLD [ST+EAX*8]*/
addbyte(0x44);
@@ -2425,7 +2425,7 @@ static inline int FP_LOAD_REG(int reg)
addbyte(0x8b); /*MOV EAX, [ESP]*/
addbyte(0x04 | (REG_EBX << 3));
addbyte(0x24);
return REG_EBX;
}
@@ -2466,7 +2466,7 @@ static inline void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
addbyte(0x44 | (REG_ECX << 3));
addbyte(0x24);
addbyte(0x04);
*host_reg1 = REG_EBX;
*host_reg2 = REG_ECX;
}
@@ -2489,7 +2489,7 @@ static inline int FP_LOAD_REG_INT_W(int reg)
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(new_npxc));
@@ -2566,10 +2566,10 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(MM));
return;
}
addbyte(0xf6); /*TEST TAG[EBX], TAG_UINT64*/
addbyte(0x44);
addbyte(0x1d);
@@ -2586,10 +2586,10 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(MM));
addbyte(0xeb); /*JMP done*/
addbyte(4+3+3+3+3+4);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
@@ -2816,7 +2816,7 @@ static inline void FP_OP_D(int op)
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(old_npxc));
}
}
}
}
static inline void FP_OP_IW(int op)
{
@@ -3576,7 +3576,7 @@ static inline void MMX_ENTER()
{
if (codegen_mmx_entered)
return;
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x05);
addlong((uintptr_t)&cr0);
@@ -3595,7 +3595,7 @@ static inline void MMX_ENTER()
addlong((uint32_t)x86_int - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
addbyte(0x31); /*XOR EAX, EAX*/
addbyte(0xc0);
addbyte(0xc6); /*MOV ISMMX, 1*/
@@ -3605,7 +3605,7 @@ static inline void MMX_ENTER()
addbyte(0x89); /*MOV TOP, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(TOP));
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV tag+4, EAX*/
@@ -3625,7 +3625,7 @@ static inline int LOAD_MMX_D(int guest_reg)
addbyte(0x8b); /*MOV EBX, reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].l[0]));
return host_reg;
}
static inline void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
@@ -3659,7 +3659,7 @@ static inline int LOAD_MMX_Q_MMX(int guest_reg)
addbyte(0x7e);
addbyte(0x45 | (dst_reg << 3));
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].q));
return dst_reg;
}
@@ -3667,7 +3667,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0x66); /*MOVD dst_reg, src_reg1*/
addbyte(0x0f);
addbyte(0x6e);
@@ -3680,7 +3680,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
addbyte(0x0f);
addbyte(0x62);
addbyte(0xc0 | 7 | (dst_reg << 3));
return dst_reg;
}

6
src/codegen/codegen_ops_xchg.h
View File

@@ -54,7 +54,7 @@ static uint32_t ropXCHG_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_B_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_B_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
static uint32_t ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -69,7 +69,7 @@ static uint32_t ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_W_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_W_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
static uint32_t ropXCHG_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -84,6 +84,6 @@ static uint32_t ropXCHG_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_L_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_L_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}

82
src/codegen/codegen_x86-64.c
View File

@@ -63,7 +63,7 @@ static int last_ssegs;
void codegen_init()
{
int c;
#if _WIN64
codeblock = VirtualAlloc(NULL, BLOCK_SIZE * sizeof(codeblock_t), MEM_COMMIT, PAGE_EXECUTE_READWRITE);
#elif defined(__unix__) || defined(__APPLE__)
@@ -83,7 +83,7 @@ void codegen_init()
void codegen_reset()
{
int c;
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
mem_reset_page_blocks();
@@ -120,7 +120,7 @@ static void add_to_block_list(codeblock_t *block)
if (block->next->valid == 0)
fatal("block->next->valid=0 %p %p %x %x\n", (void *)block->next, (void *)codeblock, block_current, block_pos);
}
if (block->page_mask2)
{
block_prev = pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3];
@@ -212,7 +212,7 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
}
block = page->block_2[(phys_addr >> 10) & 3];
while (block)
{
if (mask & block->page_mask2)
@@ -229,7 +229,7 @@ void codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
@@ -256,18 +256,18 @@ void codegen_block_init(uint32_t phys_addr)
block->page_mask = 0;
block->flags = 0;
block->status = cpu_cur_status;
block->was_recompiled = 0;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
void codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
if (!page->block[(block->phys >> 10) & 3])
mem_flush_write_page(block->phys, cs+cpu_state.pc);
@@ -278,7 +278,7 @@ void codegen_block_start_recompile(codeblock_t *block)
fatal("Recompile to used block!\n");
block->status = cpu_cur_status;
block_pos = BLOCK_GPF_OFFSET;
#ifdef OLD_GPF
#if _WIN64
@@ -351,22 +351,22 @@ void codegen_block_start_recompile(codeblock_t *block)
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] =
codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] =
@@ -426,7 +426,7 @@ void codegen_block_generate_end_mask()
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t)1 << start_pc);
page_2->code_present_mask[(block->phys_2 >> 10) & 3] |= block->page_mask2;
if (!pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3])
mem_flush_write_page(block->phys_2, block->endpc);
@@ -437,7 +437,7 @@ void codegen_block_generate_end_mask()
if (block->next_2->valid == 0)
fatal("block->next_2->valid=0 %p\n", (void *)block->next_2);
}
block->dirty_mask2 = &page_2->dirty_mask[(block->phys_2 >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK];
}
}
@@ -477,7 +477,7 @@ void codegen_block_end_recompile(codeblock_t *block)
addbyte(0x5d); /*POP RBP*/
addbyte(0x5b); /*POP RDX*/
addbyte(0xC3); /*RET*/
if (block_pos > BLOCK_GPF_OFFSET)
fatal("Over limit!\n");
@@ -537,15 +537,15 @@ int opcode_0f_modrm[256] =
0, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*e0*/
0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0 /*f0*/
};
void codegen_debug()
{
}
static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
if (!cpu_mod && cpu_rm == 6)
{
if (!cpu_mod && cpu_rm == 6)
{
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(eaaddr));
@@ -555,7 +555,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
else
{
int base_reg = 0, index_reg = 0;
switch (cpu_rm)
{
case 0: case 1: case 7:
@@ -580,7 +580,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
base_reg &= 7;
index_reg &= 7;
switch (cpu_mod)
{
case 0:
@@ -649,7 +649,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
(*op_pc) += 2;
break;
}
if (cpu_mod || !(cpu_rm & 4))
{
@@ -738,7 +738,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
}
else
{
{
switch (cpu_mod)
{
case 0:
@@ -820,7 +820,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
int base_reg;
if (!cpu_mod && cpu_rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
@@ -830,20 +830,20 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
return op_ea_seg;
}
base_reg = LOAD_REG_L(cpu_rm) & 7;
if (cpu_mod)
if (cpu_mod)
{
if (cpu_rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (cpu_mod == 1)
if (cpu_mod == 1)
{
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
(*op_pc)++;
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, base_reg+imm32*/
@@ -881,16 +881,16 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
int pc_off = 0;
int test_modrm = 1;
int c;
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
for (c = 0; c < NR_HOST_REGS; c++)
host_reg_mapping[c] = -1;
for (c = 0; c < NR_HOST_XMM_REGS; c++)
host_reg_xmm_mapping[c] = -1;
codegen_timing_start();
while (!over)
@@ -902,7 +902,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
recomp_op_table = recomp_opcodes_0f;
over = 1;
break;
case 0x26: /*ES:*/
op_ea_seg = &cpu_state.seg_es;
op_ssegs = 1;
@@ -927,14 +927,14 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
op_ea_seg = &cpu_state.seg_gs;
op_ssegs = 1;
break;
case 0x66: /*Data size select*/
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
break;
case 0x67: /*Address size select*/
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
break;
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = recomp_opcodes_d8;
@@ -1009,7 +1009,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xf0: /*LOCK*/
break;
@@ -1034,13 +1034,13 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
fetchdat >>= 8;
op_pc++;
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
codegen_accumulate(ACCREG_cycles, -codegen_block_cycles);
codegen_block_cycles = 0;
if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
(opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 ||
@@ -1112,7 +1112,7 @@ generate_call:
(op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode]))/* && !(op_32 & 0x200)*/)
{
int stack_offset = 0;
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
stack_offset = (op_32 & 0x100) ? 4 : 2;
@@ -1160,10 +1160,10 @@ generate_call:
}
load_param_1_32(block, fetchdat);
call(block, (uintptr_t)op);
call(block, (uintptr_t)op);
codegen_block_ins++;
block->ins++;
#ifdef CHECK_INT

134
src/codegen/codegen_x86.c
View File

@@ -167,7 +167,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
@@ -223,7 +223,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
@@ -275,14 +275,14 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
@@ -331,14 +331,14 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t gen_MEM_STORE_ADDR_EA_B()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -387,7 +387,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B()
static uint32_t gen_MEM_STORE_ADDR_EA_W()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -442,7 +442,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W()
static uint32_t gen_MEM_STORE_ADDR_EA_L()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -496,7 +496,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L()
static uint32_t gen_MEM_STORE_ADDR_EA_Q()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = EBX/ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EDX, ESI*/
addbyte(0xf2);
@@ -605,7 +605,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
addbyte(1);
#endif
addbyte(0xc3); /*RET*/
#ifndef RELEASE_BUILD
#ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
@@ -613,7 +613,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
#endif
#endif
return addr;
}
@@ -752,7 +752,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
#endif
#endif
return addr;
}
@@ -762,7 +762,7 @@ static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_
static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -805,7 +805,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
addbyte(1);
#endif
addbyte(0xc3); /*RET*/
#ifndef RELEASE_BUILD
#ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
@@ -823,7 +823,7 @@ static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_
static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -890,7 +890,7 @@ static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_
static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -953,9 +953,9 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
static uint32_t gen_MEM_CHECK_WRITE()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
@@ -982,7 +982,7 @@ static uint32_t gen_MEM_CHECK_WRITE()
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
@@ -1010,9 +1010,9 @@ static uint32_t gen_MEM_CHECK_WRITE()
static uint32_t gen_MEM_CHECK_WRITE_W()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
@@ -1054,7 +1054,7 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
@@ -1092,9 +1092,9 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
static uint32_t gen_MEM_CHECK_WRITE_L()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
@@ -1136,7 +1136,7 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
@@ -1187,7 +1187,7 @@ void codegen_init()
block_current = BLOCK_SIZE;
block_pos = 0;
mem_abrt_rout = (uint32_t)&codeblock[block_current].data[block_pos];
mem_abrt_rout = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x83); /*ADDL $16+4,%esp*/
addbyte(0xC4);
addbyte(0x10+4);
@@ -1230,7 +1230,7 @@ void codegen_init()
mem_check_write_w = (uint32_t)gen_MEM_CHECK_WRITE_W();
block_pos = (block_pos + 15) & ~15;
mem_check_write_l = (uint32_t)gen_MEM_CHECK_WRITE_L();
#ifndef _MSC_VER
asm(
"fstcw %0\n"
@@ -1279,7 +1279,7 @@ static void add_to_block_list(codeblock_t *block)
if (!block->next->valid)
fatal("block->next->valid=0 %p %p %x %x\n", (void *)block->next, (void *)codeblock, block_current, block_pos);
}
if (block->page_mask2)
{
block_prev = pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3];
@@ -1371,7 +1371,7 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
}
block = page->block_2[(phys_addr >> 10) & 3];
while (block)
{
if (mask & block->page_mask2)
@@ -1388,7 +1388,7 @@ void codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
@@ -1415,18 +1415,18 @@ void codegen_block_init(uint32_t phys_addr)
block->page_mask = 0;
block->flags = CODEBLOCK_STATIC_TOP;
block->status = cpu_cur_status;
block->was_recompiled = 0;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
void codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
if (!page->block[(block->phys >> 10) & 3])
mem_flush_write_page(block->phys, cs+cpu_state.pc);
@@ -1485,29 +1485,29 @@ void codegen_block_start_recompile(codeblock_t *block)
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] =
codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
block->TOP = cpu_state.TOP & 7;
block->was_recompiled = 1;
codegen_flat_ds = !(cpu_cur_status & CPU_STATUS_NOTFLATDS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
codegen_accumulate_reset();
}
@@ -1539,12 +1539,12 @@ void codegen_block_generate_end_mask()
end_pc = 0x3ff;
start_pc >>= PAGE_MASK_SHIFT;
end_pc >>= PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++)
{
{
block->page_mask |= ((uint64_t)1 << start_pc);
}
pages[block->phys >> 12].code_present_mask[(block->phys >> 10) & 3] |= block->page_mask;
block->phys_2 = -1;
@@ -1562,7 +1562,7 @@ void codegen_block_generate_end_mask()
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t)1 << start_pc);
page_2->code_present_mask[(block->phys_2 >> 10) & 3] |= block->page_mask2;
if (!pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3])
mem_flush_write_page(block->phys_2, block->endpc);
@@ -1604,7 +1604,7 @@ void codegen_block_end_recompile(codeblock_t *block)
addbyte(0x5d); /*POP EBP*/
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
if (block_pos > BLOCK_GPF_OFFSET)
fatal("Over limit!\n");
@@ -1674,8 +1674,8 @@ void codegen_debug()
static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
if (!cpu_mod && cpu_rm == 6)
{
if (!cpu_mod && cpu_rm == 6)
{
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(eaaddr));
@@ -1735,7 +1735,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
{
uint8_t sib = fetchdat >> 8;
(*op_pc)++;
switch (cpu_mod)
{
case 0:
@@ -1753,7 +1753,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
case 1:
new_eaaddr = (uint32_t)(int8_t)((fetchdat >> 16) & 0xff);
addbyte(0xb8); /*MOVL new_eaaddr, %eax*/
addlong(new_eaaddr);
@@ -1811,7 +1811,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
else
{
if (!cpu_mod && cpu_rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
@@ -1824,21 +1824,21 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(regs[cpu_rm].l));
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
if (cpu_mod)
if (cpu_mod)
{
if (cpu_rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (cpu_mod == 1)
if (cpu_mod == 1)
{
addbyte(0x05);
addlong((uint32_t)(int8_t)(fetchdat >> 8));
(*op_pc)++;
addlong((uint32_t)(int8_t)(fetchdat >> 8));
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x05);
addlong(new_eaaddr);
addlong(new_eaaddr);
(*op_pc) += 4;
}
}
@@ -1865,13 +1865,13 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
for (c = 0; c < NR_HOST_REGS; c++)
host_reg_mapping[c] = -1;
mmx_ebx_ecx_loaded = 0;
for (c = 0; c < NR_HOST_XMM_REGS; c++)
host_reg_xmm_mapping[c] = -1;
codegen_timing_start();
while (!over)
@@ -1883,7 +1883,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
recomp_op_table = recomp_opcodes_0f;
over = 1;
break;
case 0x26: /*ES:*/
op_ea_seg = &cpu_state.seg_es;
op_ssegs = 1;
@@ -1908,14 +1908,14 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
op_ea_seg = &cpu_state.seg_gs;
op_ssegs = 1;
break;
case 0x66: /*Data size select*/
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
break;
case 0x67: /*Address size select*/
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
break;
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = recomp_opcodes_d8;
@@ -1990,10 +1990,10 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xf0: /*LOCK*/
break;
case 0xf2: /*REPNE*/
op_table = x86_dynarec_opcodes_REPNE;
recomp_op_table = recomp_opcodes_REPNE;
@@ -2013,10 +2013,10 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
opcode = fetchdat & 0xff;
if (!pc_off)
fetchdat >>= 8;
op_pc++;
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
@@ -2078,7 +2078,7 @@ generate_call:
return;
}
}
op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
if (op_ssegs != last_ssegs)
{
@@ -2095,7 +2095,7 @@ generate_call:
(op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode]))
{
int stack_offset = 0;
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
stack_offset = (op_32 & 0x100) ? 4 : 2;
@@ -2150,12 +2150,12 @@ generate_call:
addbyte(0x04);
addbyte(0x24);
addlong(fetchdat);
addbyte(0xE8); /*CALL*/
addlong(((uint8_t *)op - (uint8_t *)(&block->data[block_pos + 4])));
codegen_block_ins++;
block->ins++;
#ifdef CHECK_INT