mirror of
https://github.com/86Box/86Box.git
synced 2026-02-26 05:53:15 -07:00
SM(S)C FDC37C669 Super I/O chip rewrite and proper FDC power down behavior, fixes floppy drive errors on the new Daeweoo machine.
This commit is contained in:
OBattler
@@ -12,13 +12,15 @@
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2016-2018 Miran Grca.
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* Copyright 2016-2024 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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@@ -45,35 +47,67 @@ typedef struct fdc37c669_t {
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static int next_id = 0;
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static uint16_t
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make_port(fdc37c669_t *dev, uint8_t reg)
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#ifdef ENABLE_FDC37C669_LOG
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int fdc37c669_do_log = ENABLE_FDC37C669_LOG;
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static void
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fdc37c669_log(const char *fmt, ...)
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{
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uint16_t p = 0;
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uint16_t mask = 0;
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va_list ap;
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switch (reg) {
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case 0x20:
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case 0x21:
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case 0x22:
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mask = 0xfc;
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break;
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case 0x23:
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mask = 0xff;
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break;
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case 0x24:
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case 0x25:
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mask = 0xfe;
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break;
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default:
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break;
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if (fdc37c669_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define fdc37c669_log(fmt, ...)
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#endif
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p = ((uint16_t) (dev->regs[reg] & mask)) << 2;
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if (reg == 0x22)
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p |= 6;
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static void
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fdc37c669_fdc_handler(fdc37c669_t *dev)
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{
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fdc_remove(dev->fdc);
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if (dev->regs[0x20] & 0xc0)
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fdc_set_base(dev->fdc, ((uint16_t) dev->regs[0x20]) << 2);
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}
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return p;
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static void
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fdc37c669_uart_handler(fdc37c669_t *dev, uint8_t uart)
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{
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uint8_t uart_reg = 0x24 + uart;
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uint8_t pwrdn_mask = 0x08 << (uart << 2);
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uint8_t uart_shift = ((uart ^ 1) << 2);
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serial_remove(dev->uart[uart]);
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if ((dev->regs[0x02] & pwrdn_mask) && (dev->regs[uart_reg] & 0xc0))
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serial_setup(dev->uart[0], ((uint16_t) dev->regs[0x24]) << 2,
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(dev->regs[0x28] >> uart_shift) & 0x0f);
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}
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static double
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fdc37c669_uart_get_clock_src(fdc37c669_t *dev, uint8_t uart)
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{
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double clock_srcs[4] = { 24000000.0 / 13.0, 24000000.0 / 12.0, 24000000.0 / 3.0, 24000000.0 / 3.0 };
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double ret;
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uint8_t clock_src_0 = !!(dev->regs[0x04] & (0x10 << uart));
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uint8_t clock_src_1 = !!(dev->regs[0x0c] & (0x40 << uart));
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uint8_t clock_src = clock_src_0 | (clock_src_1 << 1);
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ret = clock_srcs[clock_src];
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return ret;
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}
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static void
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fdc37c669_lpt_handler(fdc37c669_t *dev)
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{
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uint8_t mask = ~(dev->regs[0x04] & 0x01);
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lpt_port_remove(dev->id);
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if ((dev->regs[0x01] & 0x04) && (dev->regs[0x23] >= 0x40))
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lpt_port_init(dev->id, ((uint16_t) (dev->regs[0x23] & mask)) << 2);
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}
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static void
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@@ -81,149 +115,153 @@ fdc37c669_write(uint16_t port, uint8_t val, void *priv)
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{
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fdc37c669_t *dev = (fdc37c669_t *) priv;
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t valxor = 0;
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uint8_t max = 42;
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uint8_t valxor = val ^ dev->regs[dev->cur_reg];
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fdc37c669_log("[%04X:%08X] [W] %04X = %02X (%i, %i)\n", CS, cpu_state.pc, port, val,
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dev->tries, dev->locked);
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if (index) {
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if ((val == 0x55) && !dev->locked) {
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if (dev->tries) {
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dev->tries = (dev->tries + 1) & 1;
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if (!dev->tries)
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dev->locked = 1;
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dev->tries = 0;
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} else
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dev->tries++;
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} else {
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if (dev->locked) {
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if (val < max)
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dev->cur_reg = val;
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if (val == 0xaa)
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dev->locked = 0;
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} else {
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if (dev->tries)
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dev->tries = 0;
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}
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else
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dev->cur_reg = val;
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} else
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dev->tries = 0;
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}
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return;
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} else {
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if (dev->locked) {
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if ((dev->cur_reg < 0x18) && (dev->rw_locked))
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return;
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if ((dev->cur_reg >= 0x26) && (dev->cur_reg <= 0x27))
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return;
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if (dev->cur_reg == 0x29)
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return;
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valxor = val ^ dev->regs[dev->cur_reg];
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} else if (!dev->rw_locked || (dev->cur_reg > 0x0f)) switch (dev->cur_reg) {
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case 0x00:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x74) | (val & 0x8b);
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if (!dev->id && (valxor & 8))
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fdc_set_power_down(dev->fdc, !(val & 0x08));
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break;
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case 0x01:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x73) | (val & 0x8c);
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if (valxor & 0x04)
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fdc37c669_lpt_handler(dev);
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if (valxor & 0x80)
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dev->rw_locked = !(val & 0x80);
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break;
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case 0x02:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x77) | (val & 0x88);
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if (valxor & 0x08)
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fdc37c669_uart_handler(dev, 0);
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if (valxor & 0x80)
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fdc37c669_uart_handler(dev, 1);
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break;
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case 0x03:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x08) | (val & 0xf7);
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if (!dev->id && (valxor & 0x02))
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fdc_update_enh_mode(dev->fdc, !!(val & 0x02));
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break;
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case 0x04:
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dev->regs[dev->cur_reg] = val;
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} else
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return;
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}
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switch (dev->cur_reg) {
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case 0:
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if (!dev->id && (valxor & 8)) {
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fdc_remove(dev->fdc);
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if ((dev->regs[0] & 8) && (dev->regs[0x20] & 0xc0))
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fdc_set_base(dev->fdc, make_port(dev, 0x20));
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}
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if (valxor & 0x03)
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fdc37c669_lpt_handler(dev);
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if (valxor & 0x10)
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serial_set_clock_src(dev->uart[0], fdc37c669_uart_get_clock_src(dev, 0));
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if (valxor & 0x20)
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serial_set_clock_src(dev->uart[1], fdc37c669_uart_get_clock_src(dev, 1));
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break;
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case 1:
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if (valxor & 4) {
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if (dev->id) {
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lpt2_remove();
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if ((dev->regs[1] & 4) && (dev->regs[0x23] >= 0x40))
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lpt2_init(make_port(dev, 0x23));
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} else {
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lpt1_remove();
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if ((dev->regs[1] & 4) && (dev->regs[0x23] >= 0x40))
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lpt1_init(make_port(dev, 0x23));
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}
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}
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if (valxor & 7)
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dev->rw_locked = (val & 8) ? 0 : 1;
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break;
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case 2:
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if (valxor & 8) {
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serial_remove(dev->uart[0]);
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if ((dev->regs[2] & 8) && (dev->regs[0x24] >= 0x40))
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serial_setup(dev->uart[0], make_port(dev, 0x24), (dev->regs[0x28] & 0xf0) >> 4);
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}
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if (valxor & 0x80) {
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serial_remove(dev->uart[1]);
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if ((dev->regs[2] & 0x80) && (dev->regs[0x25] >= 0x40))
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serial_setup(dev->uart[1], make_port(dev, 0x25), dev->regs[0x28] & 0x0f);
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}
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break;
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case 3:
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if (!dev->id && (valxor & 2))
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fdc_update_enh_mode(dev->fdc, (val & 2) ? 1 : 0);
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break;
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case 5:
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case 0x05:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x83) | (val & 0x7c);
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if (!dev->id && (valxor & 0x18))
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fdc_update_densel_force(dev->fdc, (val & 0x18) >> 3);
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if (!dev->id && (valxor & 0x20))
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fdc_set_swap(dev->fdc, (val & 0x20) >> 5);
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break;
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case 0xB:
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if (!dev->id && (valxor & 3))
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fdc_update_rwc(dev->fdc, 0, val & 3);
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if (!dev->id && (valxor & 0xC))
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fdc_update_rwc(dev->fdc, 1, (val & 0xC) >> 2);
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case 0x06:
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dev->regs[dev->cur_reg] = val;
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break;
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case 0x07:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x06) | (val & 0xf9);
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break;
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case 0x08:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x0f) | (val & 0xf0);
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break;
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case 0x09:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x38) | (val & 0xc7);
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break;
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case 0x0a:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0xf0) | (val & 0x0f);
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break;
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case 0x0b:
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dev->regs[dev->cur_reg] = val;
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if (!dev->id && (valxor & 0x03))
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fdc_update_rwc(dev->fdc, 0, val & 0x03);
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if (!dev->id && (valxor & 0x0c))
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fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
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break;
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case 0x0c:
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dev->regs[dev->cur_reg] = val;
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if (valxor & 0x40)
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serial_set_clock_src(dev->uart[0], fdc37c669_uart_get_clock_src(dev, 0));
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if (valxor & 0x80)
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serial_set_clock_src(dev->uart[1], fdc37c669_uart_get_clock_src(dev, 1));
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break;
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case 0x0f:
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case 0x12 ... 0x1f:
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dev->regs[dev->cur_reg] = val;
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break;
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case 0x10:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x07) | (val & 0xf8);
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break;
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case 0x11:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0xfc) | (val & 0x03);
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break;
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case 0x20:
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if (!dev->id && (valxor & 0xfc)) {
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fdc_remove(dev->fdc);
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if ((dev->regs[0] & 8) && (dev->regs[0x20] & 0xc0))
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fdc_set_base(dev->fdc, make_port(dev, 0x20));
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}
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dev->regs[dev->cur_reg] = val & 0xfc;
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if (!dev->id && (valxor & 0xfc))
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fdc37c669_fdc_handler(dev);
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break;
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case 0x21:
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dev->regs[dev->cur_reg] = val & 0xfc;
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break;
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case 0x22:
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dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x03) | (val & 0xfc);
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break;
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case 0x23:
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if (valxor) {
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if (dev->id) {
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lpt2_remove();
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if ((dev->regs[1] & 4) && (dev->regs[0x23] >= 0x40))
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lpt2_init(make_port(dev, 0x23));
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} else {
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lpt1_remove();
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if ((dev->regs[1] & 4) && (dev->regs[0x23] >= 0x40))
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lpt1_init(make_port(dev, 0x23));
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}
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}
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dev->regs[dev->cur_reg] = val;
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if (valxor)
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fdc37c669_lpt_handler(dev);
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break;
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case 0x24:
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if (valxor & 0xfe) {
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serial_remove(dev->uart[0]);
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if ((dev->regs[2] & 8) && (dev->regs[0x24] >= 0x40))
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serial_setup(dev->uart[0], make_port(dev, 0x24), (dev->regs[0x28] & 0xf0) >> 4);
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}
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dev->regs[dev->cur_reg] = val & 0xfe;
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if (valxor & 0xfe)
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fdc37c669_uart_handler(dev, 0);
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break;
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case 0x25:
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if (valxor & 0xfe) {
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serial_remove(dev->uart[1]);
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if ((dev->regs[2] & 0x80) && (dev->regs[0x25] >= 0x40))
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serial_setup(dev->uart[1], make_port(dev, 0x25), dev->regs[0x28] & 0x0f);
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}
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dev->regs[dev->cur_reg] = val & 0xfe;
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if (valxor & 0xfe)
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fdc37c669_uart_handler(dev, 1);
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break;
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case 0x26:
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dev->regs[dev->cur_reg] = val;
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if (valxor & 0xf0)
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fdc_set_dma_ch(dev->fdc, val >> 4);
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break;
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case 0x27:
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if (valxor & 0xf) {
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if (dev->id)
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lpt2_irq(val & 0xf);
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else
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lpt1_irq(val & 0xf);
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}
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dev->regs[dev->cur_reg] = val;
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if (valxor & 0xf0)
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fdc_set_irq(dev->fdc, val >> 4);
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if (valxor & 0x0f)
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lpt_port_irq(dev->id, val & 0x0f);
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break;
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case 0x28:
|
||||
if (valxor & 0xf) {
|
||||
serial_remove(dev->uart[1]);
|
||||
if ((dev->regs[2] & 0x80) && (dev->regs[0x25] >= 0x40))
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serial_setup(dev->uart[1], make_port(dev, 0x25), dev->regs[0x28] & 0x0f);
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}
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if (valxor & 0xf0) {
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serial_remove(dev->uart[0]);
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if ((dev->regs[2] & 8) && (dev->regs[0x24] >= 0x40))
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serial_setup(dev->uart[0], make_port(dev, 0x24), (dev->regs[0x28] & 0xf0) >> 4);
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}
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dev->regs[dev->cur_reg] = val;
|
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if (valxor & 0xf0)
|
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fdc37c669_uart_handler(dev, 0);
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if (valxor & 0x0f)
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fdc37c669_uart_handler(dev, 1);
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break;
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default:
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case 0x29:
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dev->regs[dev->cur_reg] = val & 0x0f;
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break;
|
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}
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}
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@@ -238,23 +276,23 @@ fdc37c669_read(uint16_t port, void *priv)
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if (dev->locked) {
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if (index)
|
||||
ret = dev->cur_reg;
|
||||
else if ((dev->cur_reg >= 0x18) || !dev->rw_locked)
|
||||
else if (!dev->rw_locked || (dev->cur_reg > 0x0f))
|
||||
ret = dev->regs[dev->cur_reg];
|
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}
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||||
|
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fdc37c669_log("[%04X:%08X] [R] %04X = %02X (%i, %i)\n", CS, cpu_state.pc, port, ret,
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||||
dev->tries, dev->locked);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
fdc37c669_reset(fdc37c669_t *dev)
|
||||
fdc37c669_reset(void *priv)
|
||||
{
|
||||
serial_remove(dev->uart[0]);
|
||||
serial_setup(dev->uart[0], COM1_ADDR, COM1_IRQ);
|
||||
fdc37c669_t *dev = (fdc37c669_t *) priv;
|
||||
|
||||
serial_remove(dev->uart[1]);
|
||||
serial_setup(dev->uart[1], COM2_ADDR, COM2_IRQ);
|
||||
memset(dev->regs, 0x00, 42);
|
||||
|
||||
memset(dev->regs, 0, 42);
|
||||
dev->regs[0x00] = 0x28;
|
||||
dev->regs[0x01] = 0x9c;
|
||||
dev->regs[0x02] = 0x88;
|
||||
@@ -262,32 +300,23 @@ fdc37c669_reset(fdc37c669_t *dev)
|
||||
dev->regs[0x06] = 0xff;
|
||||
dev->regs[0x0d] = 0x03;
|
||||
dev->regs[0x0e] = 0x02;
|
||||
dev->regs[0x1e] = 0x80; /* Gameport controller. */
|
||||
dev->regs[0x20] = (FDC_PRIMARY_ADDR >> 2) & 0xfc;
|
||||
dev->regs[0x21] = (0x1f0 >> 2) & 0xfc;
|
||||
dev->regs[0x22] = ((0x3f6 >> 2) & 0xfc) | 1;
|
||||
dev->regs[0x1e] = 0x3c; /* Gameport controller. */
|
||||
dev->regs[0x20] = 0x3c;
|
||||
dev->regs[0x21] = 0x3c;
|
||||
dev->regs[0x22] = 0x3d;
|
||||
|
||||
if (dev->id == 1) {
|
||||
dev->regs[0x23] = (LPT2_ADDR >> 2);
|
||||
|
||||
lpt2_remove();
|
||||
lpt2_init(LPT2_ADDR);
|
||||
|
||||
dev->regs[0x24] = (COM3_ADDR >> 2) & 0xfe;
|
||||
dev->regs[0x25] = (COM4_ADDR >> 2) & 0xfe;
|
||||
} else {
|
||||
fdc_reset(dev->fdc);
|
||||
|
||||
lpt1_remove();
|
||||
lpt1_init(LPT1_ADDR);
|
||||
|
||||
dev->regs[0x23] = (LPT1_ADDR >> 2);
|
||||
|
||||
dev->regs[0x24] = (COM1_ADDR >> 2) & 0xfe;
|
||||
dev->regs[0x25] = (COM2_ADDR >> 2) & 0xfe;
|
||||
fdc37c669_fdc_handler(dev);
|
||||
}
|
||||
dev->regs[0x26] = (2 << 4) | 3;
|
||||
dev->regs[0x27] = (6 << 4) | (dev->id ? 5 : 7);
|
||||
dev->regs[0x28] = (4 << 4) | 3;
|
||||
|
||||
fdc37c669_uart_handler(dev, 0);
|
||||
serial_set_clock_src(dev->uart[0], fdc37c669_uart_get_clock_src(dev, 0));
|
||||
|
||||
fdc37c669_uart_handler(dev, 1);
|
||||
serial_set_clock_src(dev->uart[1], fdc37c669_uart_get_clock_src(dev, 1));
|
||||
|
||||
fdc37c669_lpt_handler(dev);
|
||||
|
||||
dev->locked = 0;
|
||||
dev->rw_locked = 0;
|
||||
@@ -317,8 +346,8 @@ fdc37c669_init(const device_t *info)
|
||||
dev->uart[0] = device_add_inst(&ns16550_device, (next_id << 1) + 1);
|
||||
dev->uart[1] = device_add_inst(&ns16550_device, (next_id << 1) + 2);
|
||||
|
||||
io_sethandler(info->local ? FDC_SECONDARY_ADDR : (next_id ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR), 0x0002,
|
||||
fdc37c669_read, NULL, NULL, fdc37c669_write, NULL, NULL, dev);
|
||||
io_sethandler(info->local ? FDC_SECONDARY_ADDR : (next_id ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR),
|
||||
0x0002, fdc37c669_read, NULL, NULL, fdc37c669_write, NULL, NULL, dev);
|
||||
|
||||
fdc37c669_reset(dev);
|
||||
|
||||
@@ -334,7 +363,7 @@ const device_t fdc37c669_device = {
|
||||
.local = 0,
|
||||
.init = fdc37c669_init,
|
||||
.close = fdc37c669_close,
|
||||
.reset = NULL,
|
||||
.reset = fdc37c669_reset,
|
||||
{ .available = NULL },
|
||||
.speed_changed = NULL,
|
||||
.force_redraw = NULL,
|
||||
@@ -348,7 +377,7 @@ const device_t fdc37c669_370_device = {
|
||||
.local = 1,
|
||||
.init = fdc37c669_init,
|
||||
.close = fdc37c669_close,
|
||||
.reset = NULL,
|
||||
.reset = fdc37c669_reset,
|
||||
{ .available = NULL },
|
||||
.speed_changed = NULL,
|
||||
.force_redraw = NULL,
|
||||
|
||||
Reference in New Issue
Block a user