From 5d2a6070a47102ea851eb70b5954fb79e9a58a8e Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 6 Nov 2022 20:33:18 -0500 Subject: [PATCH] Remove DDR support from this branch, it's not used here --- src/include/86box/spd.h | 26 ------------------ src/mem/spd.c | 59 ----------------------------------------- 2 files changed, 85 deletions(-) diff --git a/src/include/86box/spd.h b/src/include/86box/spd.h index 470e96bcd..9575278df 100644 --- a/src/include/86box/spd.h +++ b/src/include/86box/spd.h @@ -25,11 +25,9 @@ #define SPD_TYPE_FPM 0x01 #define SPD_TYPE_EDO 0x02 #define SPD_TYPE_SDRAM 0x04 -#define SPD_TYPE_DDR 0x07 #define SPD_MIN_SIZE_EDO 8 #define SPD_MIN_SIZE_SDRAM 8 -#define SPD_MIN_SIZE_DDR 8 #define SPD_SIGNAL_LVTTL 0x01 @@ -90,29 +88,6 @@ typedef struct { checksum2; } spd_sdram_t; -typedef struct { - uint8_t bytes_used, spd_size, mem_type, - row_bits, col_bits, rows, - data_width_lsb, data_width_msb, - signal_level, tclk, tac, - config, refresh_rate, - sdram_width, ecc_width, - tccd, burst, banks, cas, cslat, we, - mod_attr, dev_attr, - tclk2, tac2, tclk3, tac3, - trp, trrd, trcd, tras, - bank_density, - ca_setup, ca_hold, data_setup, data_hold, - reserved[26], - spd_rev, checksum, - mfg_jedec[8], mfg_loc; - char part_no[18]; - uint8_t rev_code[2], - mfg_year, mfg_week, serial[4], mfg_specific[27], - other_data[127], - checksum2; -} spd_ddr_t; - typedef struct { uint8_t slot; uint16_t size; @@ -123,7 +98,6 @@ typedef struct { uint8_t data[SPD_DATA_SIZE]; spd_edo_t edo_data; spd_sdram_t sdram_data; - spd_ddr_t ddr_data; }; void *eeprom; } spd_t; diff --git a/src/mem/spd.c b/src/mem/spd.c index 92d53bf27..1e95c27d7 100644 --- a/src/mem/spd.c +++ b/src/mem/spd.c @@ -180,7 +180,6 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) uint16_t min_module_size, rows[SPD_MAX_SLOTS], asym; spd_edo_t *edo_data; spd_sdram_t *sdram_data; - spd_ddr_t *ddr_data; /* Determine the minimum module size for this RAM type. */ switch (ram_type) { @@ -193,10 +192,6 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) min_module_size = SPD_MIN_SIZE_SDRAM; break; - case SPD_TYPE_DDR: - min_module_size = SPD_MIN_SIZE_DDR; - break; - default: spd_log("SPD: unknown RAM type %02X\n", ram_type); return; @@ -330,60 +325,6 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) for (i = 0; i < 129; i++) sdram_data->checksum2 += spd_modules[slot]->data[i]; break; - - case SPD_TYPE_DDR: - ddr_data = &spd_modules[slot]->ddr_data; - - ddr_data->bytes_used = 0x80; - ddr_data->spd_size = 0x08; - ddr_data->mem_type = ram_type; - ddr_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */ - ddr_data->col_bits = 9; - if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */ - ddr_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */ - ddr_data->col_bits |= 9 << 4; /* same as first row, but just in case */ - } - ddr_data->rows = 2; - ddr_data->data_width_lsb = 64; - ddr_data->signal_level = SPD_SIGNAL_LVTTL; - ddr_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */ - ddr_data->tac = 0x10; - ddr_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL; - ddr_data->sdram_width = 8; - ddr_data->tccd = 1; - ddr_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8; - ddr_data->banks = 4; - ddr_data->cas = 0x7f; /* CAS Latency */ - ddr_data->cslat = ddr_data->we = 0x7f; - ddr_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST; - ddr_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */ - ddr_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */ - ddr_data->tac2 = ddr_data->tac3 = 0x10; - ddr_data->trp = ddr_data->trrd = ddr_data->trcd = ddr_data->tras = 1; - if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { - /* Utilities interpret bank_density a bit differently on asymmetric modules. */ - ddr_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */ - ddr_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */ - } else { - ddr_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */ - } - ddr_data->ca_setup = ddr_data->data_setup = 0x15; - ddr_data->ca_hold = ddr_data->data_hold = 0x08; - - ddr_data->spd_rev = 0x10; - for (i = spd_write_part_no(ddr_data->part_no, "DDR", rows[row]); - i < sizeof(ddr_data->part_no); i++) - ddr_data->part_no[i] = ' '; /* part number should be space-padded */ - ddr_data->rev_code[0] = BCD8(EMU_VERSION_MAJ); - ddr_data->rev_code[1] = BCD8(EMU_VERSION_MIN); - ddr_data->mfg_year = 20; - ddr_data->mfg_week = 13; - - for (i = 0; i < 63; i++) - ddr_data->checksum += spd_modules[slot]->data[i]; - for (i = 0; i < 129; i++) - ddr_data->checksum2 += spd_modules[slot]->data[i]; - break; } row++;