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Changes to logging - nothing (other than some parts of pc.c) uses the global pclog anymore (and logs will be almost empty (until the base set logging flags is agreed upon);

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Fixes to various hard disk controllers;
Added the Packard Bell PB640;
Fixed the InPort mouse emulation - now it works correctly on Windows NT 3.1;
Removed the status window and the associated variables;
Completely removed the Green B 486 machine;
Fixed the MDSI Genius;
Fixed the single-sided 5.25" floppy drive;
Ported a CPU-related commit from VARCem.
This commit is contained in:
OBattler
2018-05-21 19:04:05 +02:00
parent 534ed6ea32
commit 5d8deea63b
130 changed files with 5062 additions and 3262 deletions
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4
src/video/vid_ati18800.c
View File

@@ -8,7 +8,7 @@
*
* ATI 18800 emulation (VGA Edge-16)
*
* Version: @(#)vid_ati18800.c 1.0.11 2018/04/26
* Version: @(#)vid_ati18800.c 1.0.12 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -80,7 +80,6 @@ static void ati18800_out(uint16_t addr, uint8_t val, void *p)
break;
case 0x1cf:
ati18800->regs[ati18800->index] = val;
/* pclog("ATI 18800 ATI register write %02x %02x\n", ati18800->index, val); */
switch (ati18800->index)
{
case 0xb0:
@@ -161,7 +160,6 @@ static uint8_t ati18800_in(uint16_t addr, void *p)
temp = svga_in(addr, svga);
break;
}
/* if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,cpu_state.pc); */
return temp;
}

43
src/video/vid_ati28800.c
View File

@@ -8,7 +8,7 @@
*
* ATI 28800 emulation (VGA Charger and Korean VGA)
*
* Version: @(#)vid_ati28800.c 1.0.17 2018/04/26
* Version: @(#)vid_ati28800.c 1.0.19 2018/05/20
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -18,11 +18,13 @@
* Copyright 2016-2018 Miran Grca.
* Copyright 2018 greatpsycho.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../io.h"
@@ -39,6 +41,7 @@
#define BIOS_ATIKOR_PATH L"roms/video/ati28800/atikorvga.bin"
#define FONT_ATIKOR_PATH L"roms/video/ati28800/ati_ksc5601.rom"
#define BIOS_VGAXL_EVEN_PATH L"roms/video/ati28800/xleven.bin"
#define BIOS_VGAXL_ODD_PATH L"roms/video/ati28800/xlodd.bin"
@@ -73,14 +76,34 @@ typedef struct ati28800_t
} ati28800_t;
#ifdef ENABLE_ATI28800_LOG
int ati28800_do_log = ENABLE_ATI28800_LOG;
#endif
static void
ati28800_log(const char *fmt, ...)
{
#ifdef ENABLE_ATI28800_LOG
va_list ap;
if (ati28800_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
#endif
}
static void ati28800_out(uint16_t addr, uint8_t val, void *p)
{
ati28800_t *ati28800 = (ati28800_t *)p;
svga_t *svga = &ati28800->svga;
uint8_t old;
/* pclog("ati28800_out : %04X %02X %04X:%04X\n", addr, val, CS,pc); */
ati28800_log("ati28800_out : %04X %02X %04X:%04X\n", addr, val, CS, cpu_state.pc);
if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout&1))
addr ^= 0x60;
@@ -212,7 +235,7 @@ static uint8_t ati28800_in(uint16_t addr, void *p)
svga_t *svga = &ati28800->svga;
uint8_t temp;
/* if (addr != 0x3da) pclog("ati28800_in : %04X ", addr); */
if (addr != 0x3da) ati28800_log("ati28800_in : %04X ", addr);
if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout&1)) addr ^= 0x60;
@@ -261,7 +284,7 @@ static uint8_t ati28800_in(uint16_t addr, void *p)
temp = svga_in(addr, svga);
break;
}
/* if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,cpu_state.pc); */
if (addr != 0x3da) ati28800_log("%02X %04X:%04X\n", temp, CS,cpu_state.pc);
return temp;
}
@@ -272,8 +295,8 @@ uint8_t ati28800k_in(uint16_t addr, void *p)
uint16_t oldaddr = addr;
uint8_t temp = 0xFF;
// if (addr != 0x3da) pclog("ati28800_in : %04X ", addr);
if (addr != 0x3da) ati28800_log("ati28800k_in : %04X ", addr);
if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout&1)) addr ^= 0x60;
switch (addr)
@@ -303,7 +326,7 @@ uint8_t ati28800k_in(uint16_t addr, void *p)
temp = ati28800_in(oldaddr, p);
break;
}
if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,cpu_state.pc);
if (addr != 0x3da) ati28800_log("%02X %04X:%04X\n", temp, CS,cpu_state.pc);
return temp;
}
@@ -387,7 +410,7 @@ ati28800k_init(const device_t *info)
ati28800->ksc5601_mode_enabled = 0;
rom_init(&ati28800->bios_rom, BIOS_ATIKOR_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
loadfont(FONT_ATIKOR_PATH, 6);
loadfont(FONT_ATIKOR_PATH, 6);
svga_init(&ati28800->svga, ati28800, ati28800->memory << 10, /*Memory size, default 512KB*/
ati28800k_recalctimings,

264
src/video/vid_ati_mach64.c
View File

@@ -8,7 +8,7 @@
*
* ATi Mach64 graphics card emulation.
*
* Version: @(#)vid_ati_mach64.c 1.0.20 2018/04/26
* Version: @(#)vid_ati_mach64.c 1.0.21 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -16,12 +16,15 @@
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../machine/machine.h"
#include "../device.h"
#include "../io.h"
@@ -339,6 +342,27 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv);
void mach64_ext_writew(uint32_t addr, uint16_t val, void *priv);
void mach64_ext_writel(uint32_t addr, uint32_t val, void *priv);
#ifdef ENABLE_MACH64_LOG
int mach64_do_log = ENABLE_MACH64_LOG;
#endif
static void
mach64_log(const char *fmt, ...)
{
#ifdef ENABLE_MACH64_LOG
va_list ap;
if (mach64_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
#endif
}
void mach64_out(uint16_t addr, uint8_t val, void *p)
{
mach64_t *mach64 = p;
@@ -505,7 +529,7 @@ void mach64_updatemapping(mach64_t *mach64)
if (!(mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
{
/* pclog("Update mapping - PCI disabled\n"); */
mach64_log("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_mapping);
@@ -647,11 +671,9 @@ static void mach64_accel_write_fifo(mach64_t *mach64, uint32_t addr, uint8_t val
(addr & 0x3ff) == 0x113) && !(val & 0x80))
{
mach64_start_fill(mach64);
#ifdef MACH64_DEBUG
pclog("%i %i %i %i %i %08x\n", (mach64->dst_height_width & 0x7ff), (mach64->dst_height_width & 0x7ff0000),
mach64_log("%i %i %i %i %i %08x\n", (mach64->dst_height_width & 0x7ff), (mach64->dst_height_width & 0x7ff0000),
((mach64->dp_src & 7) != SRC_HOST), (((mach64->dp_src >> 8) & 7) != SRC_HOST),
(((mach64->dp_src >> 16) & 3) != MONO_SRC_HOST), mach64->dp_src);
#endif
if ((mach64->dst_height_width & 0x7ff) && (mach64->dst_height_width & 0x7ff0000) &&
((mach64->dp_src & 7) != SRC_HOST) && (((mach64->dp_src >> 8) & 7) != SRC_HOST) &&
(((mach64->dp_src >> 16) & 3) != MONO_SRC_HOST))
@@ -839,13 +861,7 @@ static void mach64_accel_write_fifo_w(mach64_t *mach64, uint32_t addr, uint16_t
break;
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_accel_write_fifo(mach64, addr, val);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_accel_write_fifo(mach64, addr + 1, val >> 8);
break;
}
@@ -871,13 +887,7 @@ static void mach64_accel_write_fifo_l(mach64_t *mach64, uint32_t addr, uint32_t
break;
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_accel_write_fifo_w(mach64, addr, val);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_accel_write_fifo_w(mach64, addr + 2, val >> 16);
break;
}
@@ -990,14 +1000,12 @@ void mach64_start_fill(mach64_t *mach64)
mach64->accel.src_width2 = (mach64->src_height2_width2 >> 16) & 0x7fff;
mach64->accel.src_height2 = mach64->src_height2_width2 & 0x1fff;
#ifdef MACH64_DEBUG
pclog("src %i %i %i %i %08X %08X\n", mach64->accel.src_x_count,
mach64_log("src %i %i %i %i %08X %08X\n", mach64->accel.src_x_count,
mach64->accel.src_y_count,
mach64->accel.src_width1,
mach64->accel.src_height1,
mach64->src_height1_width1,
mach64->src_height2_width2);
#endif
mach64->accel.src_pitch = (mach64->src_off_pitch >> 22) * 8;
mach64->accel.src_offset = (mach64->src_off_pitch & 0xfffff) * 8;
@@ -1050,9 +1058,6 @@ void mach64_start_fill(mach64_t *mach64)
mach64->accel.sc_top = mach64->sc_top_bottom & 0x7fff;
mach64->accel.sc_bottom = (mach64->sc_top_bottom >> 16) & 0x7fff;
/* mach64->accel.sc_left *= mach64_inc[mach64->accel.dst_pix_width];
mach64->accel.sc_right *= mach64_inc[mach64->accel.dst_pix_width];*/
mach64->accel.dp_frgd_clr = mach64->dp_frgd_clr;
mach64->accel.dp_bkgd_clr = mach64->dp_bkgd_clr;
@@ -1064,9 +1069,8 @@ void mach64_start_fill(mach64_t *mach64)
mach64->accel.poly_draw = 0;
mach64->accel.busy = 1;
#ifdef MACH64_DEBUG
pclog("mach64_start_fill : dst %i, %i src %i, %i size %i, %i src pitch %i offset %X dst pitch %i offset %X scissor %i %i %i %i src_fg %i mix %02X %02X\n", mach64->accel.dst_x_start, mach64->accel.dst_y_start, mach64->accel.src_x_start, mach64->accel.src_y_start, mach64->accel.dst_width, mach64->accel.dst_height, mach64->accel.src_pitch, mach64->accel.src_offset, mach64->accel.dst_pitch, mach64->accel.dst_offset, mach64->accel.sc_left, mach64->accel.sc_right, mach64->accel.sc_top, mach64->accel.sc_bottom, mach64->accel.source_fg, mach64->accel.mix_fg, mach64->accel.mix_bg);
#endif
mach64_log("mach64_start_fill : dst %i, %i src %i, %i size %i, %i src pitch %i offset %X dst pitch %i offset %X scissor %i %i %i %i src_fg %i mix %02X %02X\n", mach64->accel.dst_x_start, mach64->accel.dst_y_start, mach64->accel.src_x_start, mach64->accel.src_y_start, mach64->accel.dst_width, mach64->accel.dst_height, mach64->accel.src_pitch, mach64->accel.src_offset, mach64->accel.dst_pitch, mach64->accel.dst_offset, mach64->accel.sc_left, mach64->accel.sc_right, mach64->accel.sc_top, mach64->accel.sc_bottom, mach64->accel.source_fg, mach64->accel.mix_fg, mach64->accel.mix_bg);
mach64->accel.op = OP_RECT;
}
@@ -1142,9 +1146,8 @@ void mach64_start_line(mach64_t *mach64)
mach64->accel.clr_cmp_src = mach64->clr_cmp_cntl & (1 << 24);
mach64->accel.busy = 1;
#ifdef MACH64_DEBUG
pclog("mach64_start_line\n");
#endif
mach64_log("mach64_start_line\n");
mach64->accel.op = OP_LINE;
}
@@ -1212,9 +1215,7 @@ void mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
if (!mach64->accel.busy)
{
#ifdef MACH64_DEBUG
pclog("mach64_blit : return as not busy\n");
#endif
mach64_log("mach64_blit : return as not busy\n");
return;
}
switch (mach64->accel.op)
@@ -1399,9 +1400,7 @@ void mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
if (mach64->accel.dst_height <= 0)
{
/*Blit finished*/
#ifdef MACH64_DEBUG
pclog("mach64 blit finished\n");
#endif
mach64_log("mach64 blit finished\n");
mach64->accel.busy = 0;
if (mach64->dst_cntl & DST_X_TILE)
mach64->dst_y_x = (mach64->dst_y_x & 0xfff) | ((mach64->dst_y_x + (mach64->accel.dst_width << 16)) & 0xfff0000);
@@ -1528,9 +1527,7 @@ void mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
if (mach64->accel.x_count <= 0)
{
/*Blit finished*/
#ifdef MACH64_DEBUG
pclog("mach64 blit finished\n");
#endif
mach64_log("mach64 blit finished\n");
mach64->accel.busy = 0;
return;
}
@@ -1554,9 +1551,7 @@ void mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
mach64->accel.dst_y++;
break;
}
#ifdef MACH64_DEBUG
pclog("x %i y %i err %i inc %i dec %i\n", mach64->accel.dst_x, mach64->accel.dst_y, mach64->accel.err, mach64->dst_bres_inc, mach64->dst_bres_dec);
#endif
mach64_log("x %i y %i err %i inc %i dec %i\n", mach64->accel.dst_x, mach64->accel.dst_y, mach64->accel.err, mach64->dst_bres_inc, mach64->dst_bres_dec);
if (mach64->accel.err >= 0)
{
mach64->accel.err += mach64->dst_bres_dec;
@@ -1597,10 +1592,8 @@ void mach64_load_context(mach64_t *mach64)
{
addr = ((0x3fff - (mach64->context_load_cntl & 0x3fff)) * 256) & mach64->vram_mask;
mach64->context_mask = *(uint32_t *)&svga->vram[addr];
#ifdef MACH64_DEBUG
pclog("mach64_load_context %08X from %08X : mask %08X\n", mach64->context_load_cntl, addr, mach64->context_mask);
#endif
mach64_log("mach64_load_context %08X from %08X : mask %08X\n", mach64->context_load_cntl, addr, mach64->context_mask);
if (mach64->context_mask & (1 << 2))
mach64_accel_write_fifo_l(mach64, 0x100, *(uint32_t *)&svga->vram[addr + 0x08]);
if (mach64->context_mask & (1 << 3))
@@ -1675,8 +1668,8 @@ static void pll_write(mach64_t *mach64, uint32_t addr, uint8_t val)
break;
case 2: /*Data*/
mach64->pll_regs[mach64->pll_addr] = val;
/* pclog("pll_write %02x,%02x\n", mach64->pll_addr, val); */
mach64_log("pll_write %02x,%02x\n", mach64->pll_addr, val);
for (c = 0; c < 4; c++)
{
double m = (double)mach64->pll_regs[PLL_REF_DIV];
@@ -1684,9 +1677,9 @@ static void pll_write(mach64_t *mach64, uint32_t addr, uint8_t val)
double r = 14318184.0;
double p = (double)(1 << ((mach64->pll_regs[VCLK_POST_DIV] >> (c*2)) & 3));
/* pclog("PLLfreq %i = %g %g m=%02x n=%02x p=%02x\n", c, (2.0 * r * n) / (m * p), p, mach64->pll_regs[PLL_REF_DIV], mach64->pll_regs[VCLK0_FB_DIV+c], mach64->pll_regs[VCLK_POST_DIV]); */
mach64_log("PLLfreq %i = %g %g m=%02x n=%02x p=%02x\n", c, (2.0 * r * n) / (m * p), p, mach64->pll_regs[PLL_REF_DIV], mach64->pll_regs[VCLK0_FB_DIV+c], mach64->pll_regs[VCLK_POST_DIV]);
mach64->pll_freq[c] = (2.0 * r * n) / (m * p);
/* pclog(" %g\n", mach64->pll_freq[c]); */
mach64_log(" %g\n", mach64->pll_freq[c]);
}
break;
}
@@ -1722,9 +1715,7 @@ uint8_t mach64_ext_readb(uint32_t addr, void *p)
uint8_t ret;
if (!(addr & 0x400))
{
#ifdef MACH64_DEBUG
pclog("nmach64_ext_readb: addr=%04x %04x(%08x):%08x\n", addr, CS, cs, cpu_state.pc);
#endif
mach64_log("nmach64_ext_readb: addr=%04x %04x(%08x):%08x\n", addr, CS, cs, cpu_state.pc);
switch (addr & 0x3ff)
{
case 0x00: case 0x01: case 0x02: case 0x03:
@@ -2076,8 +2067,6 @@ uint8_t mach64_ext_readb(uint32_t addr, void *p)
break;
case 0x338:
/* if (!FIFO_EMPTY)
wake_fifo_thread(mach64);*/
ret = FIFO_EMPTY ? 0 : 1;
break;
@@ -2085,9 +2074,7 @@ uint8_t mach64_ext_readb(uint32_t addr, void *p)
ret = 0;
break;
}
#ifdef MACH64_DEBUG
if ((addr & 0x3fc) != 0x018) pclog("mach64_ext_readb : addr %08X ret %02X\n", addr, ret);
#endif
if ((addr & 0x3fc) != 0x018) mach64_log("mach64_ext_readb : addr %08X ret %02X\n", addr, ret);
return ret;
}
uint16_t mach64_ext_readw(uint32_t addr, void *p)
@@ -2095,27 +2082,17 @@ uint16_t mach64_ext_readw(uint32_t addr, void *p)
uint16_t ret;
if (!(addr & 0x400))
{
#ifdef MACH64_DEBUG
pclog("nmach64_ext_readw: addr=%04x %04x(%08x):%08x\n", addr, CS, cs, cpu_state.pc);
#endif
mach64_log("nmach64_ext_readw: addr=%04x %04x(%08x):%08x\n", addr, CS, cs, cpu_state.pc);
ret = 0xffff;
}
else switch (addr & 0x3ff)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret = mach64_ext_readb(addr, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret |= mach64_ext_readb(addr + 1, p) << 8;
break;
}
#ifdef MACH64_DEBUG
if ((addr & 0x3fc) != 0x018) pclog("mach64_ext_readw : addr %08X ret %04X\n", addr, ret);
#endif
if ((addr & 0x3fc) != 0x018) mach64_log("mach64_ext_readw : addr %08X ret %04X\n", addr, ret);
return ret;
}
uint32_t mach64_ext_readl(uint32_t addr, void *p)
@@ -2124,9 +2101,7 @@ uint32_t mach64_ext_readl(uint32_t addr, void *p)
uint32_t ret;
if (!(addr & 0x400))
{
#ifdef MACH64_DEBUG
pclog("nmach64_ext_readl: addr=%04x %04x(%08x):%08x\n", addr, CS, cs, cpu_state.pc);
#endif
mach64_log("nmach64_ext_readl: addr=%04x %04x(%08x):%08x\n", addr, CS, cs, cpu_state.pc);
ret = 0xffffffff;
}
else switch (addr & 0x3ff)
@@ -2145,19 +2120,11 @@ uint32_t mach64_ext_readl(uint32_t addr, void *p)
break;
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret = mach64_ext_readw(addr, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret |= mach64_ext_readw(addr + 2, p) << 16;
break;
}
#ifdef MACH64_DEBUG
if ((addr & 0x3fc) != 0x018) pclog("mach64_ext_readl : addr %08X ret %08X\n", addr, ret);
#endif
if ((addr & 0x3fc) != 0x018) mach64_log("mach64_ext_readl : addr %08X ret %08X\n", addr, ret);
return ret;
}
@@ -2165,9 +2132,9 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
svga_t *svga = &mach64->svga;
#ifdef MACH64_DEBUG
pclog("mach64_ext_writeb : addr %08X val %02X %04x(%08x):%08x\n", addr, val, CS,cs,cpu_state.pc);
#endif
mach64_log("mach64_ext_writeb : addr %08X val %02X %04x(%08x):%08x\n", addr, val, CS,cs,cpu_state.pc);
if (!(addr & 0x400))
{
switch (addr & 0x3ff)
@@ -2224,9 +2191,8 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
WRITE8(addr, mach64->buf_pitch[1], val);
break;
}
#ifdef MACH64_DEBUG
pclog("nmach64_ext_writeb: addr=%04x val=%02x\n", addr, val);
#endif
mach64_log("nmach64_ext_writeb: addr=%04x val=%02x\n", addr, val);
}
else if (addr & 0x300)
{
@@ -2332,27 +2298,19 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
case 0xb4:
mach64->bank_w[0] = val * 32768;
#ifdef MACH64_DEBUG
pclog("mach64 : write bank A0000-A7FFF set to %08X\n", mach64->bank_w[0]);
#endif
mach64_log("mach64 : write bank A0000-A7FFF set to %08X\n", mach64->bank_w[0]);
break;
case 0xb5: case 0xb6:
mach64->bank_w[1] = val * 32768;
#ifdef MACH64_DEBUG
pclog("mach64 : write bank A8000-AFFFF set to %08X\n", mach64->bank_w[1]);
#endif
mach64_log("mach64 : write bank A8000-AFFFF set to %08X\n", mach64->bank_w[1]);
break;
case 0xb8:
mach64->bank_r[0] = val * 32768;
#ifdef MACH64_DEBUG
pclog("mach64 : read bank A0000-A7FFF set to %08X\n", mach64->bank_r[0]);
#endif
mach64_log("mach64 : read bank A0000-A7FFF set to %08X\n", mach64->bank_r[0]);
break;
case 0xb9: case 0xba:
mach64->bank_r[1] = val * 32768;
#ifdef MACH64_DEBUG
pclog("mach64 : read bank A8000-AFFFF set to %08X\n", mach64->bank_r[1]);
#endif
mach64_log("mach64 : read bank A8000-AFFFF set to %08X\n", mach64->bank_r[1]);
break;
case 0xc0: case 0xc1: case 0xc2: case 0xc3:
@@ -2389,14 +2347,11 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
void mach64_ext_writew(uint32_t addr, uint16_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
#ifdef MACH64_DEBUG
pclog("mach64_ext_writew : addr %08X val %04X\n", addr, val);
#endif
mach64_log("mach64_ext_writew : addr %08X val %04X\n", addr, val);
if (!(addr & 0x400))
{
#ifdef MACH64_DEBUG
pclog("nmach64_ext_writew: addr=%04x val=%04x %04x(%08x):%08x\n", addr, val, CS, cs, cpu_state.pc);
#endif
mach64_log("nmach64_ext_writew: addr=%04x val=%04x %04x(%08x):%08x\n", addr, val, CS, cs, cpu_state.pc);
mach64_ext_writeb(addr, val, p);
mach64_ext_writeb(addr + 1, val >> 8, p);
}
@@ -2407,13 +2362,7 @@ void mach64_ext_writew(uint32_t addr, uint16_t val, void *p)
else switch (addr & 0x3fe)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_writeb(addr, val, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_writeb(addr + 1, val >> 8, p);
break;
}
@@ -2421,15 +2370,12 @@ void mach64_ext_writew(uint32_t addr, uint16_t val, void *p)
void mach64_ext_writel(uint32_t addr, uint32_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
#ifdef MACH64_DEBUG
if ((addr & 0x3c0) != 0x200)
pclog("mach64_ext_writel : addr %08X val %08X\n", addr, val);
#endif
mach64_log("mach64_ext_writel : addr %08X val %08X\n", addr, val);
if (!(addr & 0x400))
{
#ifdef MACH64_DEBUG
pclog("nmach64_ext_writel: addr=%04x val=%08x %04x(%08x):%08x\n", addr, val, CS, cs, cpu_state.pc);
#endif
mach64_log("nmach64_ext_writel: addr=%04x val=%08x %04x(%08x):%08x\n", addr, val, CS, cs, cpu_state.pc);
mach64_ext_writew(addr, val, p);
mach64_ext_writew(addr + 2, val >> 16, p);
}
@@ -2440,13 +2386,7 @@ void mach64_ext_writel(uint32_t addr, uint32_t val, void *p)
else switch (addr & 0x3fc)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_writew(addr, val, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_writew(addr + 2, val >> 16, p);
break;
}
@@ -2570,9 +2510,7 @@ uint8_t mach64_ext_inb(uint16_t port, void *p)
ret = 0;
break;
}
#ifdef MACH64_DEBUG
pclog("mach64_ext_inb : port %04X ret %02X %04X:%04X\n", port, ret, CS,cpu_state.pc);
#endif
mach64_log("mach64_ext_inb : port %04X ret %02X %04X:%04X\n", port, ret, CS,cpu_state.pc);
return ret;
}
uint16_t mach64_ext_inw(uint16_t port, void *p)
@@ -2581,19 +2519,11 @@ uint16_t mach64_ext_inw(uint16_t port, void *p)
switch (port)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret = mach64_ext_inb(port, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret |= (mach64_ext_inb(port + 1, p) << 8);
break;
}
#ifdef MACH64_DEBUG
pclog("mach64_ext_inw : port %04X ret %04X\n", port, ret);
#endif
mach64_log("mach64_ext_inw : port %04X ret %04X\n", port, ret);
return ret;
}
uint32_t mach64_ext_inl(uint16_t port, void *p)
@@ -2609,28 +2539,18 @@ uint32_t mach64_ext_inl(uint16_t port, void *p)
break;
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret = mach64_ext_inw(port, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret |= (mach64_ext_inw(port + 2, p) << 16);
break;
}
#ifdef MACH64_DEBUG
pclog("mach64_ext_inl : port %04X ret %08X\n", port, ret);
#endif
mach64_log("mach64_ext_inl : port %04X ret %08X\n", port, ret);
return ret;
}
void mach64_ext_outb(uint16_t port, uint8_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
#ifdef MACH64_DEBUG
pclog("mach64_ext_outb : port %04X val %02X %04X:%04X\n", port, val, CS,cpu_state.pc);
#endif
mach64_log("mach64_ext_outb : port %04X val %02X %04X:%04X\n", port, val, CS,cpu_state.pc);
switch (port)
{
case 0x02ec: case 0x02ed: case 0x02ee: case 0x02ef:
@@ -2732,36 +2652,22 @@ void mach64_ext_outb(uint16_t port, uint8_t val, void *p)
}
void mach64_ext_outw(uint16_t port, uint16_t val, void *p)
{
#ifdef MACH64_DEBUG
pclog("mach64_ext_outw : port %04X val %04X\n", port, val);
#endif
mach64_log("mach64_ext_outw : port %04X val %04X\n", port, val);
switch (port)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_outb(port, val, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_outb(port + 1, val >> 8, p);
break;
}
}
void mach64_ext_outl(uint16_t port, uint32_t val, void *p)
{
/* pclog("mach64_ext_outl : port %04X val %08X\n", port, val); */
mach64_log("mach64_ext_outl : port %04X val %08X\n", port, val);
switch (port)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_outw(port, val, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
mach64_ext_outw(port + 2, val >> 16, p);
break;
}
@@ -2773,9 +2679,7 @@ static uint8_t mach64_block_inb(uint16_t port, void *p)
uint8_t ret;
ret = mach64_ext_readb(0x400 | (port & 0x3ff), mach64);
#ifdef MACH64_DEBUG
pclog("mach64_block_inb : port %04X ret %02X %04x:%04x\n", port, ret, CS,cpu_state.pc);
#endif
mach64_log("mach64_block_inb : port %04X ret %02X %04x:%04x\n", port, ret, CS,cpu_state.pc);
return ret;
}
static uint16_t mach64_block_inw(uint16_t port, void *p)
@@ -2784,9 +2688,7 @@ static uint16_t mach64_block_inw(uint16_t port, void *p)
uint16_t ret;
ret = mach64_ext_readw(0x400 | (port & 0x3ff), mach64);
#ifdef MACH64_DEBUG
pclog("mach64_block_inw : port %04X ret %04X\n", port, ret);
#endif
mach64_log("mach64_block_inw : port %04X ret %04X\n", port, ret);
return ret;
}
static uint32_t mach64_block_inl(uint16_t port, void *p)
@@ -2795,9 +2697,7 @@ static uint32_t mach64_block_inl(uint16_t port, void *p)
uint32_t ret;
ret = mach64_ext_readl(0x400 | (port & 0x3ff), mach64);
#ifdef MACH64_DEBUG
pclog("mach64_block_inl : port %04X ret %08X\n", port, ret);
#endif
mach64_log("mach64_block_inl : port %04X ret %08X\n", port, ret);
return ret;
}
@@ -2805,27 +2705,21 @@ static void mach64_block_outb(uint16_t port, uint8_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
#ifdef MACH64_DEBUG
pclog("mach64_block_outb : port %04X val %02X\n ", port, val);
#endif
mach64_log("mach64_block_outb : port %04X val %02X\n ", port, val);
mach64_ext_writeb(0x400 | (port & 0x3ff), val, mach64);
}
static void mach64_block_outw(uint16_t port, uint16_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
#ifdef MACH64_DEBUG
pclog("mach64_block_outw : port %04X val %04X\n ", port, val);
#endif
mach64_log("mach64_block_outw : port %04X val %04X\n ", port, val);
mach64_ext_writew(0x400 | (port & 0x3ff), val, mach64);
}
static void mach64_block_outl(uint16_t port, uint32_t val, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
#ifdef MACH64_DEBUG
pclog("mach64_block_outl : port %04X val %08X\n ", port, val);
#endif
mach64_log("mach64_block_outl : port %04X val %08X\n ", port, val);
mach64_ext_writel(0x400 | (port & 0x3ff), val, mach64);
}
@@ -3085,7 +2979,7 @@ void mach64_overlay_draw(svga_t *svga, int displine)
break;
default:
/* pclog("Unknown Mach64 scaler format %x\n", mach64->scaler_format); */
mach64_log("Unknown Mach64 scaler format %x\n", mach64->scaler_format);
/*Fill buffer with something recognisably wrong*/
for (x = 0; x < mach64->svga.overlay_latch.xsize; x++)
mach64->overlay_dat[x] = 0xff00ff;
@@ -3361,12 +3255,12 @@ void mach64_pci_write(int func, int addr, uint8_t val, void *p)
if (mach64->pci_regs[0x30] & 0x01)
{
uint32_t addr = (mach64->pci_regs[0x32] << 16) | (mach64->pci_regs[0x33] << 24);
/* pclog("Mach64 bios_rom enabled at %08x\n", addr); */
mach64_log("Mach64 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&mach64->bios_rom.mapping, addr, 0x8000);
}
else
{
/* pclog("Mach64 bios_rom disabled\n"); */
mach64_log("Mach64 bios_rom disabled\n");
mem_mapping_disable(&mach64->bios_rom.mapping);
}
return;

3
src/video/vid_cga.c
View File

@@ -8,7 +8,7 @@
*
* Emulation of the old and new IBM CGA graphics cards.
*
* Version: @(#)vid_cga.c 1.0.15 2018/04/26
* Version: @(#)vid_cga.c 1.0.16 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -151,7 +151,6 @@ void cga_recalctimings(cga_t *cga)
{
double disptime;
double _dispontime, _dispofftime;
/* pclog("Recalc - %i %i %i\n", cga->crtc[0], cga->crtc[1], cga->cgamode & 1); */
if (cga->cgamode & 1)
{
disptime = (double) (cga->crtc[0] + 1);

179
src/video/vid_cl54xx.c
View File

@@ -9,7 +9,7 @@
* Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported).
*
* Version: @(#)vid_cl_54xx.c 1.0.18 2018/04/26
* Version: @(#)vid_cl_54xx.c 1.0.19 2018/05/08
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Barry Rodewald,
@@ -47,6 +47,7 @@
#define BIOS_GD5430_PCI_PATH L"roms/video/cirruslogic/pci.bin"
#define BIOS_GD5434_PATH L"roms/video/cirruslogic/gd5434.bin"
#define BIOS_GD5436_PATH L"roms/video/cirruslogic/5436.vbi"
#define BIOS_GD5440_PATH L"roms/video/cirruslogic/BIOS.BIN"
#define BIOS_GD5446_PATH L"roms/video/cirruslogic/5446BV.VBI"
#define BIOS_GD5446_STB_PATH L"roms/video/cirruslogic/stb nitro64v.BIN"
#define BIOS_GD5480_PATH L"roms/video/cirruslogic/clgd5480.rom"
@@ -57,6 +58,7 @@
#define CIRRUS_ID_CLGD5430 0xa0
#define CIRRUS_ID_CLGD5434 0xa8
#define CIRRUS_ID_CLGD5436 0xac
#define CIRRUS_ID_CLGD5440 0xa0 /* Yes, the 5440 has the same ID as the 5430. */
#define CIRRUS_ID_CLGD5446 0xb8
#define CIRRUS_ID_CLGD5480 0xbc
@@ -128,7 +130,7 @@ typedef struct gd54xx_t
svga_t svga;
int has_bios;
int has_bios, rev;
rom_t bios_rom;
uint32_t vram_size;
@@ -201,6 +203,18 @@ gd543x_recalc_mapping(gd54xx_t *gd54xx);
static void
gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga);
/* Returns 1 if the card is a 5434, 5436/46, or 5480. */
static int
gd54xx_is_5434(svga_t *svga)
{
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
return 1;
else
return 0;
}
static void
gd54xx_out(uint16_t addr, uint8_t val, void *p)
{
@@ -622,8 +636,8 @@ gd54xx_in(uint16_t addr, void *p)
case 0x27: /*ID*/
return svga->crtc[0x27]; /*GD542x/GD543x*/
case 0x28: /*Class ID*/
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5430)
return 0xff; /*Standard CL-GD5430*/
if ((svga->crtc[0x27] == CIRRUS_ID_CLGD5430) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5440))
return 0xff; /*Standard CL-GD5430/40*/
break;
}
return svga->crtc[svga->crtcreg];
@@ -767,7 +781,7 @@ gd54xx_recalctimings(svga_t *svga)
break;
case 5:
if ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5434) && (svga->seqregs[7] & CIRRUS_SR7_BPP_32)) {
if (gd54xx_is_5434(svga) && (svga->seqregs[7] & CIRRUS_SR7_BPP_32)) {
svga->bpp = 32;
svga->render = svga_render_32bpp_highres;
if (svga->crtc[0x27] < CIRRUS_ID_CLGD5436)
@@ -819,19 +833,18 @@ gd54xx_recalctimings(svga_t *svga)
int d = (gd54xx->vclk_d[clocksel] & 0x3e) >> 1;
int m = gd54xx->vclk_d[clocksel] & 0x01 ? 2 : 1;
float freq = (14318184.0 * ((float)n / ((float)d * m)));
switch (svga->seqregs[7] & ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5434) ? 0xe : 6))
{
case 2:
freq /= 2.0;
break;
case 4:
if (svga->crtc[0x27] <= CIRRUS_ID_CLGD5434)
switch (svga->seqregs[7] & (gd54xx_is_5434(svga) ? 0xe : 6)) {
case 2:
freq /= 2.0;
break;
case 4:
if (!gd54xx_is_5434(svga))
freq /= 3.0;
break;
break;
}
svga->clock = cpuclock / freq;
}
svga->vram_display_mask = (svga->crtc[0x1b] & 2) ? gd54xx->vram_mask : 0x3ffff;
}
@@ -1550,44 +1563,44 @@ gd543x_mmio_write(uint32_t addr, uint8_t val, void *p)
if (gd543x_do_mmio(svga, addr)) {
switch (addr & 0xff) {
case 0x00:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xffffff00) | val;
else
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xff00) | val;
break;
case 0x01:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xffff00ff) | (val << 8);
else
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0x00ff) | (val << 8);
break;
case 0x02:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xff00ffff) | (val << 16);
break;
case 0x03:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0x00ffffff) | (val << 24);
break;
case 0x04:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xffffff00) | val;
else
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xff00) | val;
break;
case 0x05:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xffff00ff) | (val << 8);
else
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0x00ff) | (val << 8);
break;
case 0x06:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xff00ffff) | (val << 16);
break;
case 0x07:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0x00ffffff) | (val << 24);
break;
@@ -1596,7 +1609,7 @@ gd543x_mmio_write(uint32_t addr, uint8_t val, void *p)
break;
case 0x09:
gd54xx->blt.width = (gd54xx->blt.width & 0x00ff) | (val << 8);
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.width &= 0x1fff;
else
gd54xx->blt.width &= 0x07ff;
@@ -1629,7 +1642,7 @@ gd543x_mmio_write(uint32_t addr, uint8_t val, void *p)
break;
case 0x12:
gd54xx->blt.dst_addr = (gd54xx->blt.dst_addr & 0x00ffff) | (val << 16);
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.dst_addr &= 0x3fffff;
else
gd54xx->blt.dst_addr &= 0x1fffff;
@@ -1655,7 +1668,7 @@ gd543x_mmio_write(uint32_t addr, uint8_t val, void *p)
break;
case 0x16:
gd54xx->blt.src_addr = (gd54xx->blt.src_addr & 0x00ffff) | (val << 16);
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
if (gd54xx_is_5434(svga))
gd54xx->blt.src_addr &= 0x3fffff;
else
gd54xx->blt.src_addr &= 0x1fffff;
@@ -1838,7 +1851,7 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
else
gd54xx->blt.y_count = 0;
if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) == (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) {
if (!(svga->seqregs[7] & 0xf0)) {
mem_mapping_set_handler(&svga->mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l);
mem_mapping_set_p(&svga->mapping, gd54xx);
@@ -1848,7 +1861,7 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
}
gd543x_recalc_mapping(gd54xx);
return;
} else if (gd54xx->blt.mode != CIRRUS_BLTMODE_MEMSYSSRC) {
} else {
if (!(svga->seqregs[7] & 0xf0)) {
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel);
mem_mapping_set_p(&gd54xx->svga.mapping, gd54xx);
@@ -1894,6 +1907,12 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
cpu_dat <<= 1;
count--;
}
} else {
/*This must stay for general purpose Cirrus drivers to render fine in WinNT 3.5x*/
src = cpu_dat & 0xff;
cpu_dat >>= 8;
count -= 8;
mask = 1;
}
} else {
switch (gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) {
@@ -2076,6 +2095,9 @@ cl_pci_read(int func, int addr, void *p)
gd54xx_t *gd54xx = (gd54xx_t *)p;
svga_t *svga = &gd54xx->svga;
if ((addr >= 0x30) && (addr <= 0x33) && (!gd54xx->has_bios))
return 0;
switch (addr) {
case 0x00: return 0x13; /*Cirrus Logic*/
case 0x01: return 0x10;
@@ -2087,10 +2109,11 @@ cl_pci_read(int func, int addr, void *p)
case PCI_REG_COMMAND:
return gd54xx->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
case 0x07: return 0 << 1; /*Fast DEVSEL timing*/
// case 0x07: return 0 << 1; /*Fast DEVSEL timing*/
case 0x07: return 0x02; /*Fast DEVSEL timing*/
case 0x08: return 0; /*Revision ID*/
case 0x09: return 0; /*Programming interface*/
case 0x08: return gd54xx->rev; /*Revision ID*/
case 0x09: return 0x00; /*Programming interface*/
case 0x0a: return 0x00; /*Supports VGA interface*/
case 0x0b: return 0x03;
@@ -2117,6 +2140,9 @@ cl_pci_write(int func, int addr, uint8_t val, void *p)
{
gd54xx_t *gd54xx = (gd54xx_t *)p;
if ((addr >= 0x30) && (addr <= 0x33) && (!gd54xx->has_bios))
return;
switch (addr) {
case PCI_REG_COMMAND:
gd54xx->pci_regs[PCI_REG_COMMAND] = val & 0x23;
@@ -2159,6 +2185,8 @@ static void
gd54xx->pci = !!(info->flags & DEVICE_PCI);
gd54xx->vlb = !!(info->flags & DEVICE_VLB);
gd54xx->rev = 0;
gd54xx->has_bios = 1;
switch (id) {
case CIRRUS_ID_CLGD5426:
romfn = BIOS_GD5426_PATH;
@@ -2175,13 +2203,6 @@ static void
romfn = BIOS_GD5429_PATH;
break;
case CIRRUS_ID_CLGD5430:
if (gd54xx->pci)
romfn = BIOS_GD5430_PCI_PATH;
else
romfn = BIOS_GD5430_VLB_PATH;
break;
case CIRRUS_ID_CLGD5434:
romfn = BIOS_GD5434_PATH;
break;
@@ -2190,6 +2211,24 @@ static void
romfn = BIOS_GD5436_PATH;
break;
case CIRRUS_ID_CLGD5430:
if (info->local & 0x400) {
/* CL-GD 5440 */
gd54xx->rev = 0x47;
if (info->local & 0x200) {
romfn = NULL;
gd54xx->has_bios = 0;
} else
romfn = BIOS_GD5440_PATH;
} else {
/* CL-GD 5430 */
if (gd54xx->pci)
romfn = BIOS_GD5430_PCI_PATH;
else
romfn = BIOS_GD5430_VLB_PATH;
}
break;
case CIRRUS_ID_CLGD5446:
if (info->local & 0x100)
romfn = BIOS_GD5446_STB_PATH;
@@ -2205,7 +2244,8 @@ static void
gd54xx->vram_size = device_get_config_int("memory");
gd54xx->vram_mask = (gd54xx->vram_size << 20) - 1;
rom_init(&gd54xx->bios_rom, romfn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (romfn)
rom_init(&gd54xx->bios_rom, romfn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
svga_init(&gd54xx->svga, gd54xx, gd54xx->vram_size << 20,
gd54xx_recalctimings, gd54xx_in, gd54xx_out,
@@ -2292,6 +2332,12 @@ gd5436_available(void)
return rom_present(BIOS_GD5436_PATH);
}
static int
gd5440_available(void)
{
return rom_present(BIOS_GD5440_PATH);
}
static int
gd5446_available(void)
{
@@ -2366,6 +2412,33 @@ static const device_config_t gd5428_config[] =
}
};
static const device_config_t gd5440_onboard_config[] =
{
{
.name = "memory",
.description = "Video memory size",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = ""
}
},
.default_int = 2
},
{
.type = -1
}
};
static const device_config_t gd5434_config[] =
{
{
@@ -2547,6 +2620,34 @@ const device_t gd5436_pci_device =
gd5434_config
};
const device_t gd5440_onboard_pci_device =
{
"Cirrus Logic CL-GD 5440 (On-Board PCI)",
DEVICE_PCI,
CIRRUS_ID_CLGD5440 | 0x600,
gd54xx_init,
gd54xx_close,
NULL,
NULL,
gd54xx_speed_changed,
gd54xx_force_redraw,
gd5440_onboard_config
};
const device_t gd5440_pci_device =
{
"Cirrus Logic CL-GD 5440 (PCI)",
DEVICE_PCI,
CIRRUS_ID_CLGD5440 | 0x400,
gd54xx_init,
gd54xx_close,
NULL,
gd5440_available,
gd54xx_speed_changed,
gd54xx_force_redraw,
gd5428_config
};
const device_t gd5446_pci_device =
{
"Cirrus Logic CL-GD 5446 (PCI)",
@@ -2565,7 +2666,7 @@ const device_t gd5446_stb_pci_device =
{
"STB Nitro 64V (PCI)",
DEVICE_PCI,
CIRRUS_ID_CLGD5446,
CIRRUS_ID_CLGD5446 | 0x100,
gd54xx_init,
gd54xx_close,
NULL,

2
src/video/vid_cl54xx.h
View File

@@ -12,6 +12,8 @@ extern const device_t gd5434_isa_device;
extern const device_t gd5434_vlb_device;
extern const device_t gd5434_pci_device;
extern const device_t gd5436_pci_device;
extern const device_t gd5440_onboard_pci_device;
extern const device_t gd5440_pci_device;
extern const device_t gd5446_pci_device;
extern const device_t gd5446_stb_pci_device;
extern const device_t gd5480_pci_device;

53
src/video/vid_et4000w32.c
View File

@@ -10,7 +10,7 @@
*
* Known bugs: Accelerator doesn't work in planar modes
*
* Version: @(#)vid_et4000w32.c 1.0.9 2018/04/26
* Version: @(#)vid_et4000w32.c 1.0.10 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -18,11 +18,13 @@
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../io.h"
@@ -155,6 +157,27 @@ void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p);
void et4000w32_blit_start(et4000w32p_t *et4000);
void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000);
#ifdef ENABLE_ET4000W32_LOG
int et4000w32_do_log = ENABLE_ET4000W32_LOG;
#endif
static void
et4000w32_log(const char *format, ...)
{
#ifdef ENABLE_ET4000W32_LOG
va_list ap;
if (et4000w32_do_log) {
va_start(ap, format);
pclog_ex(format, ap);
va_end(ap);
}
#endif
}
void et4000w32p_out(uint16_t addr, uint8_t val, void *p)
{
et4000w32p_t *et4000 = (et4000w32p_t *)p;
@@ -847,10 +870,10 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
{
while (count--)
{
/* if (bltout) pclog("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y); */
et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff];
/* if (bltout) pclog("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff); */
et4000w32_log("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff);
if (cpu_input == 2)
{
source = sdat & 0xff;
@@ -858,11 +881,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
}
dest = svga->vram[et4000->acl.dest_addr & 0x1fffff];
out = 0;
/* if (bltout) pclog("%06X ", et4000->acl.dest_addr); */
et4000w32_log("%06X ", et4000->acl.dest_addr);
if ((et4000->acl.internal.ctrl_routing & 0xa) == 8)
{
mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff] & (1 << (et4000->acl.mix_addr & 7));
/* if (bltout) pclog("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]); */
et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]);
}
else
{
@@ -879,7 +902,7 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
if (pattern & (1 << c)) d |= 4;
if (rop & (1 << d)) out |= (1 << c);
}
/* if (bltout) pclog("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out); */
et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out);
if (!(et4000->acl.internal.ctrl_routing & 0x40))
{
svga->vram[et4000->acl.dest_addr & 0x1fffff] = out;
@@ -962,11 +985,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
{
while (count--)
{
/* if (bltout) pclog("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y); */
et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff];
/* if (bltout) pclog("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff, pattern, source); */
et4000w32_log("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff, pattern, source);
if (cpu_input == 2)
{
@@ -975,11 +998,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
}
dest = svga->vram[et4000->acl.dest_addr & 0x1fffff];
out = 0;
/* if (bltout) pclog("%06X %02X %i %08X %08X ", dest, et4000->acl.dest_addr, mix & 1, mix, et4000->acl.mix_addr); */
et4000w32_log("%06X %02X %i %08X %08X ", dest, et4000->acl.dest_addr, mix & 1, mix, et4000->acl.mix_addr);
if ((et4000->acl.internal.ctrl_routing & 0xa) == 8)
{
mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff] & (1 << (et4000->acl.mix_addr & 7));
/* if (bltout) pclog("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]); */
et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]);
}
else
{
@@ -996,7 +1019,7 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
if (pattern & (1 << c)) d |= 4;
if (rop & (1 << d)) out |= (1 << c);
}
/* if (bltout) pclog("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out); */
et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out);
if (!(et4000->acl.internal.ctrl_routing & 0x40))
{
svga->vram[et4000->acl.dest_addr & 0x1fffff] = out;
@@ -1186,12 +1209,12 @@ void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p)
{
addr = 0xC0000;
}
/* pclog("ET4000 bios_rom enabled at %08x\n", addr); */
et4000w32_log("ET4000 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&et4000->bios_rom.mapping, addr, 0x8000);
}
else
{
/* pclog("ET4000 bios_rom disabled\n"); */
et4000w32_log("ET4000 bios_rom disabled\n");
mem_mapping_disable(&et4000->bios_rom.mapping);
}
return;

99
src/video/vid_genius.c
View File

@@ -8,7 +8,7 @@
*
* MDSI Genius VHR emulation.
*
* Version: @(#)vid_genius.c 1.0.9 2018/04/26
* Version: @(#)vid_genius.c 1.0.10 2018/05/20
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -93,6 +93,7 @@ extern uint8_t fontdat8x12[256][16];
* in an 8x12 cell if necessary.
*/
typedef struct genius_t
{
@@ -134,6 +135,8 @@ typedef struct genius_t
uint8_t *vram;
} genius_t;
static uint32_t genius_pal[4];
/* Mapping of attributes to colours, in MDA emulation mode */
static int mdacols[256][2][2];
@@ -219,8 +222,6 @@ uint8_t genius_in(uint16_t addr, void *p)
return 0xff;
}
void genius_write(uint32_t addr, uint8_t val, void *p)
{
genius_t *genius = (genius_t *)p;
@@ -257,8 +258,6 @@ uint8_t genius_read(uint32_t addr, void *p)
return genius->vram[addr];
}
void genius_recalctimings(genius_t *genius)
{
double disptime;
@@ -269,8 +268,8 @@ void genius_recalctimings(genius_t *genius)
_dispofftime = disptime - _dispontime;
_dispontime *= MDACONST;
_dispofftime *= MDACONST;
genius->dispontime = (int64_t)(_dispontime * (1LL << TIMER_SHIFT));
genius->dispofftime = (int64_t)(_dispofftime * (1LL << TIMER_SHIFT));
genius->dispontime = (int)(_dispontime * (1 << TIMER_SHIFT));
genius->dispofftime = (int)(_dispofftime * (1 << TIMER_SHIFT));
}
@@ -290,7 +289,7 @@ void genius_textline(genius_t *genius, uint8_t background)
uint16_t ma = (genius->mda_crtc[13] | (genius->mda_crtc[12] << 8)) & 0x3fff;
uint16_t ca = (genius->mda_crtc[15] | (genius->mda_crtc[14] << 8)) & 0x3fff;
unsigned char *framebuf = genius->vram + 0x10000;
uint8_t col;
uint32_t col;
/* Character height is 12-15 */
charh = 15 - (genius->genius_charh & 3);
@@ -342,13 +341,13 @@ void genius_textline(genius_t *genius, uint8_t background)
if (genius->genius_control & 0x20)
{
col ^= 15;
col ^= 0xffffff;
}
for (c = 0; c < cw; c++)
{
if (col != background)
buffer->line[genius->displine][(x * cw) + c] = col;
((uint32_t *)buffer32->line[genius->displine])[(x * cw) + c] = col;
}
}
else /* Draw 8 pixels of character */
@@ -362,49 +361,50 @@ void genius_textline(genius_t *genius, uint8_t background)
if (genius->genius_control & 0x20)
{
col ^= 15;
col ^= 0xffffff;
}
if (col != background)
{
buffer->line[genius->displine][(x * cw) + c] = col;
((uint32_t *)buffer32->line[genius->displine])[(x * cw) + c] = col;
}
}
/* The ninth pixel column... */
if ((chr & ~0x1f) == 0xc0)
{
/* Echo column 8 for the graphics chars */
col = buffer->line[genius->displine][(x * cw) + 7];
if (col != background) buffer->line[genius->displine][(x * cw) + 8] = col;
col = ((uint32_t *)buffer32->line[genius->displine])[(x * cw) + 7];
if (col != background)
((uint32_t *)buffer32->line[genius->displine])[(x * cw) + 8] = col;
}
else /* Otherwise fill with background */
{
col = mdacols[attr][blink][0];
if (genius->genius_control & 0x20)
{
col ^= 15;
col ^= 0xffffff;
}
if (col != background) buffer->line[genius->displine][(x * cw) + 8] = col;
if (col != background)
((uint32_t *)buffer32->line[genius->displine])[(x * cw) + 8] = col;
}
if (drawcursor)
{
for (c = 0; c < cw; c++)
buffer->line[genius->displine][(x * cw) + c] ^= mdacols[attr][0][1];
((uint32_t *)buffer32->line[genius->displine])[(x * cw) + c] ^= mdacols[attr][0][1];
}
++ma;
}
}
}
/* Draw a line in the CGA 640x200 mode */
void genius_cgaline(genius_t *genius)
{
int x, c;
uint32_t dat;
uint8_t ink;
uint32_t ink;
uint32_t addr;
ink = (genius->genius_control & 0x20) ? 16 : 16+15;
ink = (genius->genius_control & 0x20) ? genius_pal[0] : genius_pal[3];
/* We draw the CGA at row 600 */
if (genius->displine < 600)
{
@@ -425,23 +425,22 @@ void genius_cgaline(genius_t *genius)
{
if (dat & 0x80)
{
buffer->line[genius->displine][x*8 + c] = ink;
((uint32_t *)buffer32->line[genius->displine])[x*8 + c] = ink;
}
dat = dat << 1;
}
}
}
/* Draw a line in the native high-resolution mode */
void genius_hiresline(genius_t *genius)
{
int x, c;
uint32_t dat;
uint8_t ink;
uint32_t ink;
uint32_t addr;
ink = (genius->genius_control & 0x20) ? 16 : 16+15;
ink = (genius->genius_control & 0x20) ? genius_pal[0] : genius_pal[3];
/* The first 512 lines live at A0000 */
if (genius->displine < 512)
{
@@ -461,14 +460,13 @@ void genius_hiresline(genius_t *genius)
{
if (dat & 0x80)
{
buffer->line[genius->displine][x*8 + c] = ink;
((uint32_t *)buffer32->line[genius->displine])[x*8 + c] = ink;
}
dat = dat << 1;
}
}
}
void genius_poll(void *p)
{
genius_t *genius = (genius_t *)p;
@@ -485,11 +483,11 @@ void genius_poll(void *p)
{
if (genius->genius_control & 0x20)
{
background = 16 + 15;
background = genius_pal[3];
}
else
{
background = 16;
background = genius_pal[0];
}
if (genius->displine == 0)
{
@@ -498,7 +496,7 @@ void genius_poll(void *p)
/* Start off with a blank line */
for (x = 0; x < GENIUS_XSIZE; x++)
{
buffer->line[genius->displine][x] = background;
((uint32_t *)buffer32->line[genius->displine])[x] = background;
}
/* If graphics display enabled, draw graphics on top
* of the blanked line */
@@ -547,7 +545,7 @@ void genius_poll(void *p)
if (genius->displine == 1008)
{
/* Hardcode GENIUS_XSIZE * GENIUS_YSIZE window size */
if ((GENIUS_XSIZE != xsize) || (GENIUS_YSIZE != ysize) || video_force_resize_get())
if (GENIUS_XSIZE != xsize || GENIUS_YSIZE != ysize)
{
xsize = GENIUS_XSIZE;
ysize = GENIUS_YSIZE;
@@ -558,7 +556,7 @@ void genius_poll(void *p)
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen_8(0, 0, 0, ysize, xsize, ysize);
video_blit_memtoscreen(0, 0, 0, ysize, xsize, ysize);
frames++;
/* Fixed 728x1008 resolution */
@@ -579,6 +577,8 @@ void *genius_init(const device_t *info)
/* 160k video RAM */
genius->vram = malloc(0x28000);
loadfont(BIOS_ROM_PATH, 4);
timer_add(genius_poll, &genius->vidtime, TIMER_ALWAYS_ENABLED, genius);
/* Occupy memory between 0xB0000 and 0xBFFFF (moves to 0xA0000 in
@@ -588,27 +588,32 @@ void *genius_init(const device_t *info)
io_sethandler(0x03b0, 0x000C, genius_in, NULL, NULL, genius_out, NULL, NULL, genius);
io_sethandler(0x03d0, 0x0010, genius_in, NULL, NULL, genius_out, NULL, NULL, genius);
genius_pal[0] = makecol(0x00, 0x00, 0x00);
genius_pal[1] = makecol(0x55, 0x55, 0x55);
genius_pal[2] = makecol(0xaa, 0xaa, 0xaa);
genius_pal[3] = makecol(0xff, 0xff, 0xff);
/* MDA attributes */
/* I don't know if the Genius's MDA emulation actually does
* emulate bright / non-bright. For the time being pretend it does. */
for (c = 0; c < 256; c++)
{
mdacols[c][0][0] = mdacols[c][1][0] = mdacols[c][1][1] = 16;
if (c & 8) mdacols[c][0][1] = 15 + 16;
else mdacols[c][0][1] = 7 + 16;
mdacols[c][0][0] = mdacols[c][1][0] = mdacols[c][1][1] = genius_pal[0];
if (c & 8) mdacols[c][0][1] = genius_pal[3];
else mdacols[c][0][1] = genius_pal[2];
}
mdacols[0x70][0][1] = 16;
mdacols[0x70][0][0] = mdacols[0x70][1][0] = mdacols[0x70][1][1] = 16 + 15;
mdacols[0xF0][0][1] = 16;
mdacols[0xF0][0][0] = mdacols[0xF0][1][0] = mdacols[0xF0][1][1] = 16 + 15;
mdacols[0x78][0][1] = 16 + 7;
mdacols[0x78][0][0] = mdacols[0x78][1][0] = mdacols[0x78][1][1] = 16 + 15;
mdacols[0xF8][0][1] = 16 + 7;
mdacols[0xF8][0][0] = mdacols[0xF8][1][0] = mdacols[0xF8][1][1] = 16 + 15;
mdacols[0x00][0][1] = mdacols[0x00][1][1] = 16;
mdacols[0x08][0][1] = mdacols[0x08][1][1] = 16;
mdacols[0x80][0][1] = mdacols[0x80][1][1] = 16;
mdacols[0x88][0][1] = mdacols[0x88][1][1] = 16;
mdacols[0x70][0][1] = genius_pal[0];
mdacols[0x70][0][0] = mdacols[0x70][1][0] = mdacols[0x70][1][1] = genius_pal[3];
mdacols[0xF0][0][1] = genius_pal[0];
mdacols[0xF0][0][0] = mdacols[0xF0][1][0] = mdacols[0xF0][1][1] = genius_pal[3];
mdacols[0x78][0][1] = genius_pal[2];
mdacols[0x78][0][0] = mdacols[0x78][1][0] = mdacols[0x78][1][1] = genius_pal[3];
mdacols[0xF8][0][1] = genius_pal[2];
mdacols[0xF8][0][0] = mdacols[0xF8][1][0] = mdacols[0xF8][1][1] = genius_pal[3];
mdacols[0x00][0][1] = mdacols[0x00][1][1] = genius_pal[0];
mdacols[0x08][0][1] = mdacols[0x08][1][1] = genius_pal[0];
mdacols[0x80][0][1] = mdacols[0x80][1][1] = genius_pal[0];
mdacols[0x88][0][1] = mdacols[0x88][1][1] = genius_pal[0];
/* Start off in 80x25 text mode */
genius->cga_stat = 0xF4;
@@ -626,7 +631,7 @@ void genius_close(void *p)
free(genius);
}
static int genius_available(void)
static int genius_available()
{
return rom_present(BIOS_ROM_PATH);
}

6
src/video/vid_hercules.c
View File

@@ -8,7 +8,7 @@
*
* Hercules emulation.
*
* Version: @(#)vid_hercules.c 1.0.10 2018/04/26
* Version: @(#)vid_hercules.c 1.0.11 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -68,7 +68,6 @@ uint8_t hercules_read(uint32_t addr, void *p);
void hercules_out(uint16_t addr, uint8_t val, void *p)
{
hercules_t *hercules = (hercules_t *)p;
// pclog("Herc out %04X %02X\n",addr,val);
switch (addr)
{
case 0x3b0: case 0x3b2: case 0x3b4: case 0x3b6:
@@ -99,7 +98,6 @@ void hercules_out(uint16_t addr, uint8_t val, void *p)
uint8_t hercules_in(uint16_t addr, void *p)
{
hercules_t *hercules = (hercules_t *)p;
// pclog("Herc in %04X %02X %04X:%04X %04X\n",addr,(hercules_stat & 0xF) | ((hercules_stat & 8) << 4),CS,pc,CX);
switch (addr)
{
case 0x3b0: case 0x3b2: case 0x3b4: case 0x3b6:
@@ -116,7 +114,6 @@ void hercules_write(uint32_t addr, uint8_t val, void *p)
{
hercules_t *hercules = (hercules_t *)p;
egawrites++;
// pclog("Herc write %08X %02X\n",addr,val);
hercules->vram[addr & 0xffff] = val;
}
@@ -153,7 +150,6 @@ void hercules_poll(void *p)
int blink;
if (!hercules->linepos)
{
//pclog("Poll %i %i\n",vc,sc);
hercules->vidtime += hercules->dispofftime;
hercules->stat |= 1;
hercules->linepos = 1;

4
src/video/vid_herculesplus.c
View File

@@ -8,7 +8,7 @@
*
* Hercules InColor emulation.
*
* Version: @(#)vid_herculesplus.c 1.0.8 2018/04/26
* Version: @(#)vid_herculesplus.c 1.0.9 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -97,7 +97,6 @@ static int mdacols[256][2][2];
void herculesplus_out(uint16_t addr, uint8_t val, void *p)
{
herculesplus_t *herculesplus = (herculesplus_t *)p;
/* pclog("InColor out %04X %02X\n",addr,val); */
switch (addr)
{
case 0x3b0: case 0x3b2: case 0x3b4: case 0x3b6:
@@ -129,7 +128,6 @@ void herculesplus_out(uint16_t addr, uint8_t val, void *p)
uint8_t herculesplus_in(uint16_t addr, void *p)
{
herculesplus_t *herculesplus = (herculesplus_t *)p;
/* pclog("InColor in %04X %02X %04X:%04X %04X\n",addr,(herculesplus->stat & 0xF) | ((herculesplus->stat & 8) << 4),CS,pc,CX); */
switch (addr)
{
case 0x3b0: case 0x3b2: case 0x3b4: case 0x3b6:

4
src/video/vid_incolor.c
View File

@@ -8,7 +8,7 @@
*
* Hercules InColor emulation.
*
* Version: @(#)vid_incolor.c 1.0.9 2018/04/26
* Version: @(#)vid_incolor.c 1.0.10 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -197,7 +197,6 @@ uint8_t incolor_read(uint32_t addr, void *p);
void incolor_out(uint16_t addr, uint8_t val, void *p)
{
incolor_t *incolor = (incolor_t *)p;
/* pclog("InColor out %04X %02X\n",addr,val); */
switch (addr)
{
case 0x3b0: case 0x3b2: case 0x3b4: case 0x3b6:
@@ -235,7 +234,6 @@ void incolor_out(uint16_t addr, uint8_t val, void *p)
uint8_t incolor_in(uint16_t addr, void *p)
{
incolor_t *incolor = (incolor_t *)p;
/* pclog("InColor in %04X %02X %04X:%04X %04X\n",addr,(incolor->stat & 0xF) | ((incolor->stat & 8) << 4),CS,pc,CX); */
switch (addr)
{
case 0x3b0: case 0x3b2: case 0x3b4: case 0x3b6:

128
src/video/vid_nv_riva128.c
View File

@@ -8,7 +8,7 @@
*
* nVidia RIVA 128 emulation.
*
* Version: @(#)vid_nv_riva128.c 1.0.6 2018/04/26
* Version: @(#)vid_nv_riva128.c 1.0.7 2018/04/29
*
* Author: Melissa Goad
* Miran Grca, <mgrca8@gmail.com>
@@ -16,11 +16,13 @@
* Copyright 2015-2018 Melissa Goad.
* Copyright 2015-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../machine/machine.h"
@@ -302,6 +304,26 @@ const char* riva128_pfifo_interrupts[32] =
void riva128_mmio_write_l(uint32_t addr, uint32_t val, void *p);
#ifdef ENABLE_NV_RIVA_LOG
int nv_riva_do_log = ENABLE_NV_RIVA_LOG;
#endif
static void
nv_riva_log(const char *fmt, ...)
{
#ifdef ENABLE_NV_RIVA_LOG
va_list ap;
if (nv_riva_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
#endif
}
/* riva128_color_t riva128_pgraph_expand_color(uint32_t ctx, uint32_t color)
{
riva128_color_t ret;
@@ -311,7 +333,7 @@ const char* riva128_pfifo_interrupts[32] =
switch(format)
{
default:
pclog("RIVA 128 Unknown color format %i found!\n", format);
nv_riva_log("RIVA 128 Unknown color format %i found!\n", format);
ret.a = 0x0;
break;
case 0:
@@ -376,7 +398,7 @@ const char* riva128_pfifo_interrupts[32] =
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PMC read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PMC read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
if(riva128->card_id == 0x03) switch(addr)
{
@@ -481,7 +503,7 @@ const char* riva128_pfifo_interrupts[32] =
void riva128_pmc_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
//pclog("RIVA 128 PMC write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PMC write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -503,7 +525,7 @@ const char* riva128_pfifo_interrupts[32] =
void riva128_pmc_interrupt(int num, void *p)
{
//pclog("RIVA 128 PMC interrupt #%d fired!\n", num);
//nv_riva_log("RIVA 128 PMC interrupt #%d fired!\n", num);
riva128_t *riva128 = (riva128_t *)p;
riva128->pmc.intr |= (1 << num);
@@ -519,7 +541,7 @@ const char* riva128_pfifo_interrupts[32] =
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PBUS read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PBUS read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -557,7 +579,7 @@ const char* riva128_pfifo_interrupts[32] =
void riva128_pbus_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
//pclog("RIVA 128 PBUS write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PBUS write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -647,7 +669,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
// pclog("RIVA 128 PFIFO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
// nv_riva_log("RIVA 128 PFIFO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -786,7 +808,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
void riva128_pfifo_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
// pclog("RIVA 128 PFIFO write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
// nv_riva_log("RIVA 128 PFIFO write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -852,7 +874,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PTIMER read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PTIMER read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -951,7 +973,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
void riva128_ptimer_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
pclog("RIVA 128 PTIMER write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
nv_riva_log("RIVA 128 PTIMER write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -985,7 +1007,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
void riva128_ptimer_interrupt(int num, void *p)
{
//pclog("RIVA 128 PTIMER interrupt #%d fired!\n", num);
//nv_riva_log("RIVA 128 PTIMER interrupt #%d fired!\n", num);
riva128_t *riva128 = (riva128_t *)p;
riva128->ptimer.intr |= (1 << num);
@@ -998,7 +1020,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PFB read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PFB read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -1065,7 +1087,7 @@ uint32_t riva128_pfifo_cache1_free(uint32_t chid, void* p)
void riva128_pfb_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
//pclog("RIVA 128 PFB write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PFB write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -1093,7 +1115,7 @@ uint8_t riva128_pextdev_read(uint32_t addr, void *p)
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PEXTDEV read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PEXTDEV read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//For NV3, we give it PCI 66MHz, card mode, PCI bus type, 13.5MHz crystal, no TV encoder, and PCI 2.1.
//For NV4, we give it normal PCI line polarity, card mode, 13.5 MHz crystal, no TV encoder, and PCI bus type
@@ -1132,7 +1154,7 @@ uint8_t riva128_pextdev_read(uint32_t addr, void *p)
void riva128_pextdev_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
//pclog("RIVA 128 PEXTDEV write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PEXTDEV write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -1198,7 +1220,7 @@ void rivatnt_pgraph_ctx_switch(void *p)
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
pclog("RIVA 128 PGRAPH read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
nv_riva_log("RIVA 128 PGRAPH read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -1595,7 +1617,7 @@ void rivatnt_pgraph_ctx_switch(void *p)
void riva128_pgraph_write(uint32_t addr, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
pclog("RIVA 128 PGRAPH write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
nv_riva_log("RIVA 128 PGRAPH write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -1794,7 +1816,7 @@ void riva128_pgraph_vblank_interrupt(void *p)
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PRAMDAC read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PRAMDAC read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -1867,7 +1889,7 @@ void riva128_pgraph_vblank_interrupt(void *p)
{
riva128_t *riva128 = (riva128_t *)p;
svga_t* svga = &riva128->svga;
//pclog("RIVA 128 PRAMDAC write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PRAMDAC write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -1934,7 +1956,7 @@ void riva128_pgraph_vblank_interrupt(void *p)
ret = riva128->pramin[ramht_base + (hash * 8)];
pclog("RIVA 128 RAMHT lookup with handle %08X returned %08X %04X:%08X\n", handle, ret, CS, cpu_state.pc);
nv_riva_log("RIVA 128 RAMHT lookup with handle %08X returned %08X %04X:%08X\n", handle, ret, CS, cpu_state.pc);
return ret;
}
@@ -1942,7 +1964,7 @@ void riva128_pgraph_vblank_interrupt(void *p)
void riva128_puller_exec_method(int chanid, int subchanid, int offset, uint32_t val, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
pclog("RIVA 128 Puller executing method %04X on channel %01X[%01X] param %08X %04X:%08X\n", offset, chanid, subchanid, val, CS, cpu_state.pc);
nv_riva_log("RIVA 128 Puller executing method %04X on channel %01X[%01X] param %08X %04X:%08X\n", offset, chanid, subchanid, val, CS, cpu_state.pc);
if(riva128->card_id == 0x03)
{
@@ -2020,7 +2042,7 @@ void riva128_pgraph_vblank_interrupt(void *p)
}
else
{
pclog("RIVA 128 PFIFO Invalid DMA pusher command %08x!\n", cmd);
nv_riva_log("RIVA 128 PFIFO Invalid DMA pusher command %08x!\n", cmd);
riva128_pfifo_interrupt(12, riva128);
}
riva128->pfifo.channels[chanid].dmaget += 4;
@@ -2035,7 +2057,7 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
int offset = addr & 0x1fff;
uint8_t ret = 0;
pclog("RIVA 128 USER read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
nv_riva_log("RIVA 128 USER read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
addr -= 0x800000;
@@ -2063,7 +2085,7 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
int subchanid = (addr >> 13) & 0x7;
int offset = addr & 0x1fff;
pclog("RIVA 128 USER write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
nv_riva_log("RIVA 128 USER write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
addr -= 0x800000;
@@ -2113,7 +2135,7 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
//This logging condition is necessary to prevent A CATASTROPHIC LOG BLOWUP when polling PTIMER or PFIFO. DO NOT REMOVE.
if(/*!((addr >= 0x009000) && (addr <= 0x009fff)) && !((addr >= 0x002000) && (addr <= 0x003fff)) && !((addr >= 0x000000)
&& (addr <= 0x000003)) && !((addr <= 0x680fff) && (addr >= 0x680000)) && !((addr >= 0x0c0000) && (addr <= 0x0cffff))
&& !((addr >= 0x110000) && (addr <= 0x11ffff)) && !(addr <= 0x000fff) && (addr >= 0x000000)*/1) pclog("RIVA 128 MMIO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
&& !((addr >= 0x110000) && (addr <= 0x11ffff)) && !(addr <= 0x000fff) && (addr >= 0x000000)*/1) nv_riva_log("RIVA 128 MMIO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
if((addr >= 0x000000) && (addr <= 0x000fff)) ret = riva128_pmc_read(addr, riva128);
if((addr >= 0x001000) && (addr <= 0x001fff)) ret = riva128_pbus_read(addr, riva128);
@@ -2143,21 +2165,21 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
uint16_t riva128_mmio_read_w(uint32_t addr, void *p)
{
addr &= 0xffffff;
//pclog("RIVA 128 MMIO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 MMIO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
return (riva128_mmio_read(addr+0,p) << 0) | (riva128_mmio_read(addr+1,p) << 8);
}
uint32_t riva128_mmio_read_l(uint32_t addr, void *p)
{
addr &= 0xffffff;
//pclog("RIVA 128 MMIO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 MMIO read %08X %04X:%08X\n", addr, CS, cpu_state.pc);
return (riva128_mmio_read(addr+0,p) << 0) | (riva128_mmio_read(addr+1,p) << 8) | (riva128_mmio_read(addr+2,p) << 16) | (riva128_mmio_read(addr+3,p) << 24);
}
void riva128_mmio_write(uint32_t addr, uint8_t val, void *p)
{
addr &= 0xffffff;
//pclog("RIVA 128 MMIO write %08X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 MMIO write %08X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
if(addr != 0x6013d4 && addr != 0x6013d5 && addr != 0x6013b4 && addr != 0x6013b5 && addr != 0x6013da && !((addr >= 0x6813c6) && (addr <= 0x6813cc)))
{
uint32_t tmp = riva128_mmio_read_l(addr,p);
@@ -2175,7 +2197,7 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
{
uint32_t tmp;
addr &= 0xffffff;
//pclog("RIVA 128 MMIO write %08X %04X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 MMIO write %08X %04X %04X:%08X\n", addr, val, CS, cpu_state.pc);
tmp = riva128_mmio_read_l(addr,p);
tmp &= ~(0xffff << ((addr & 2) << 4));
tmp |= val << ((addr & 2) << 4);
@@ -2189,7 +2211,7 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
addr &= 0xffffff;
//DO NOT REMOVE. This fixes a monstrous log blowup in win9x's drivers when accessing PFIFO.
if(/*!((addr >= 0x002000) && (addr <= 0x003fff)) && !((addr >= 0xc0000) && (addr <= 0xcffff)) && (addr != 0x000140)*/1) pclog("RIVA 128 MMIO write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
if(/*!((addr >= 0x002000) && (addr <= 0x003fff)) && !((addr >= 0xc0000) && (addr <= 0xcffff)) && (addr != 0x000140)*/1) nv_riva_log("RIVA 128 MMIO write %08X %08X %04X:%08X\n", addr, val, CS, cpu_state.pc);
if((addr >= 0x000000) && (addr <= 0x000fff)) riva128_pmc_write(addr, val, riva128);
@@ -2220,13 +2242,13 @@ uint8_t riva128_user_read(uint32_t addr, void *p)
void riva128_ptimer_tick(void *p)
{
riva128_t *riva128 = (riva128_t *)p;
//pclog("RIVA 128 PTIMER tick!\n");
//nv_riva_log("RIVA 128 PTIMER tick!\n");
double time = ((double)riva128->ptimer.clock_mul * 10000000.0f) / (double)riva128->ptimer.clock_div;
uint32_t tmp;
int alarm_check;
//if(cs == 0x0008 && !riva128->pgraph.beta) pclog("RIVA 128 PTIMER time elapsed %f alarm %08x, time_low %08x\n", time, riva128->ptimer.alarm, riva128->ptimer.time & 0xffffffff);
//if(cs == 0x0008 && !riva128->pgraph.beta) nv_riva_log("RIVA 128 PTIMER time elapsed %f alarm %08x, time_low %08x\n", time, riva128->ptimer.alarm, riva128->ptimer.time & 0xffffffff);
tmp = riva128->ptimer.time;
riva128->ptimer.time += (uint64_t)time;
@@ -2235,7 +2257,7 @@ void riva128_ptimer_tick(void *p)
if(alarm_check && (riva128->ptimer.intr_en & 1))
{
//pclog("RIVA 128 PTIMER ALARM interrupt fired!\n");
//nv_riva_log("RIVA 128 PTIMER ALARM interrupt fired!\n");
riva128_ptimer_interrupt(0, riva128);
}
}
@@ -2244,7 +2266,7 @@ void riva128_ptimer_tick(void *p)
{
riva128_t *riva128 = (riva128_t *)p;
//if(!riva128->pgraph.beta) pclog("RIVA 128 MCLK poll PMC enable %08x\n", riva128->pmc.enable);
//if(!riva128->pgraph.beta) nv_riva_log("RIVA 128 MCLK poll PMC enable %08x\n", riva128->pmc.enable);
if((riva128->pmc.enable & 0x00010000) && (riva128->card_id == 0x03)) riva128_ptimer_tick(riva128);
@@ -2275,7 +2297,7 @@ void riva128_ptimer_tick(void *p)
addr &= 0xff;
//pclog("RIVA 128 RMA read %04X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 RMA read %04X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -2310,7 +2332,7 @@ void riva128_ptimer_tick(void *p)
addr &= 0xff;
//pclog("RIVA 128 RMA write %04X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 RMA write %04X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -2373,7 +2395,7 @@ void riva128_ptimer_tick(void *p)
if((addr >= 0x3d0) && (addr <= 0x3d3))
{
//pclog("RIVA 128 RMA BAR Register read %04X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 RMA BAR Register read %04X %04X:%08X\n", addr, CS, cpu_state.pc);
if(!(riva128->rma.mode & 1)) return ret;
ret = riva128_rma_in(riva128->rma_addr + ((riva128->rma.mode & 0xe) << 1) + (addr & 3), riva128);
return ret;
@@ -2382,7 +2404,7 @@ void riva128_ptimer_tick(void *p)
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
// if (addr != 0x3da) pclog("S3 in %04X %04X:%08X ", addr, CS, cpu_state.pc);
// if (addr != 0x3da) nv_riva_log("S3 in %04X %04X:%08X ", addr, CS, cpu_state.pc);
switch (addr)
{
case 0x3D4:
@@ -2431,13 +2453,13 @@ void riva128_ptimer_tick(void *p)
break;
}
if(svga->crtcreg > 0x18)
pclog("RIVA 128 Extended CRTC read %02X %04X:%08X\n", svga->crtcreg, CS, cpu_state.pc);
nv_riva_log("RIVA 128 Extended CRTC read %02X %04X:%08X\n", svga->crtcreg, CS, cpu_state.pc);
break;
default:
ret = svga_in(addr, svga);
break;
}
// if (addr != 0x3da) pclog("%02X\n", ret);
// if (addr != 0x3da) nv_riva_log("%02X\n", ret);
return ret;
}
@@ -2450,7 +2472,7 @@ void riva128_ptimer_tick(void *p)
if((addr >= 0x3d0) && (addr <= 0x3d3))
{
//pclog("RIVA 128 RMA BAR Register write %04X %02x %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 RMA BAR Register write %04X %02x %04X:%08X\n", addr, val, CS, cpu_state.pc);
riva128->rma.access_reg[addr & 3] = val;
if(!(riva128->rma.mode & 1)) return;
riva128_rma_out(riva128->rma_addr + ((riva128->rma.mode & 0xe) << 1) + (addr & 3), riva128->rma.access_reg[addr & 3], riva128);
@@ -2544,7 +2566,7 @@ void riva128_ptimer_tick(void *p)
break;
}
//if(svga->crtcreg > 0x18)
// pclog("RIVA 128 Extended CRTC write %02X %02x %04X:%08X\n", svga->crtcreg, val, CS, cpu_state.pc);
// nv_riva_log("RIVA 128 Extended CRTC write %02X %02x %04X:%08X\n", svga->crtcreg, val, CS, cpu_state.pc);
if (old != val)
{
if (svga->crtcreg < 0xE || svga->crtcreg > 0x10)
@@ -2608,7 +2630,7 @@ void riva128_ptimer_tick(void *p)
{
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PCI read %02X %04X:%08X\n", addr, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PCI read %02X %04X:%08X\n", addr, CS, cpu_state.pc);
switch (addr)
{
case 0x00:
@@ -2698,7 +2720,7 @@ void riva128_ptimer_tick(void *p)
break;
}
// pclog("%02X\n", ret);
// nv_riva_log("%02X\n", ret);
return ret;
}
@@ -2727,7 +2749,7 @@ void riva128_ptimer_tick(void *p)
void riva128_pci_write(int func, int addr, uint8_t val, void *p)
{
//pclog("RIVA 128 PCI write %02X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PCI write %02X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
riva128_t *riva128 = (riva128_t *)p;
svga_t* svga = &riva128->svga;
switch (addr)
@@ -2821,7 +2843,7 @@ void riva128_ptimer_tick(void *p)
if (riva128->pci_regs[0x30] & 0x01)
{
uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24);
// pclog("RIVA 128 bios_rom enabled at %08x\n", addr);
// nv_riva_log("RIVA 128 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x8000);
}
return;
@@ -2841,7 +2863,7 @@ void riva128_ptimer_tick(void *p)
void rivatnt_pci_write(int func, int addr, uint8_t val, void *p)
{
//pclog("RIVA 128 PCI write %02X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nv_riva_log("RIVA 128 PCI write %02X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
riva128_t *riva128 = (riva128_t *)p;
svga_t *svga = &riva128->svga;
switch (addr)
@@ -2931,7 +2953,7 @@ void riva128_ptimer_tick(void *p)
if (riva128->pci_regs[0x30] & 0x01)
{
uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24);
// pclog("RIVA TNT bios_rom enabled at %08x\n", addr);
// nv_riva_log("RIVA TNT bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x10000);
}
return;
@@ -3000,7 +3022,7 @@ void riva128_ptimer_tick(void *p)
else
{
freq = (freq * riva128->pramdac.v_n) / (1 << riva128->pramdac.v_p) / riva128->pramdac.v_m;
//pclog("RIVA 128 Pixel clock is %f Hz\n", freq);
//nv_riva_log("RIVA 128 Pixel clock is %f Hz\n", freq);
}
svga->clock = cpuclock / freq;
@@ -3014,7 +3036,7 @@ void riva128_ptimer_tick(void *p)
else
{
freq = (freq * riva128->pramdac.m_n) / (1 << riva128->pramdac.m_p) / riva128->pramdac.m_m;
//pclog("RIVA 128 Memory clock is %f Hz\n", freq);
//nv_riva_log("RIVA 128 Memory clock is %f Hz\n", freq);
}
riva128->mfreq = freq;
@@ -3030,7 +3052,7 @@ void riva128_ptimer_tick(void *p)
else
{
freq = (freq * riva128->pramdac.nv_n) / (1 << riva128->pramdac.nv_p) / riva128->pramdac.nv_m;
//pclog("RIVA 128 Core clock is %f Hz\n", freq);
//nv_riva_log("RIVA 128 Core clock is %f Hz\n", freq);
}
riva128->nvfreq = freq;

56
src/video/vid_nvidia.c
View File

@@ -8,7 +8,7 @@
*
* nVidia RIVA 128 emulation.
*
* Version: @(#)vid_nv_riva128.c 1.0.6 2018/04/26
* Version: @(#)vid_nv_riva128.c 1.0.7 2018/04/29
*
* Author: Melissa Goad
* Miran Grca, <mgrca8@gmail.com>
@@ -16,12 +16,13 @@
* Copyright 2015-2018 Melissa Goad.
* Copyright 2015-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../machine/machine.h"
@@ -238,6 +239,27 @@ typedef struct riva128_t
int64_t mtime, mfreq;
} riva128_t;
#ifdef ENABLE_NVIDIA_LOG
int nvidia_do_log = ENABLE_NVIDIA_LOG;
#endif
static void
nvidia_log(const char *fmt, ...)
{
#ifdef ENABLE_NVIDIA_LOG
va_list ap;
if (nvidia_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
#endif
}
uint8_t riva128_rma_in(uint16_t addr, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
@@ -246,7 +268,7 @@ uint8_t riva128_rma_in(uint16_t addr, void *p)
addr &= 0xff;
//pclog("RIVA 128 RMA read %04X %04X:%08X\n", addr, CS, cpu_state.pc);
//nvidia_log("RIVA 128 RMA read %04X %04X:%08X\n", addr, CS, cpu_state.pc);
switch(addr)
{
@@ -266,7 +288,7 @@ uint8_t riva128_rma_in(uint16_t addr, void *p)
case 0x09:
case 0x0a:
case 0x0b:
if(riva128->rma.addr < 0x1000000) /*ret = riva128_mmio_read((riva128->rma.addr + (addr & 3)) & 0xffffff, riva128);*/pclog("RIVA 128 MMIO write %08x %08x\n", riva128->rma.addr & 0xffffff, riva128->rma.data);
if(riva128->rma.addr < 0x1000000) /*ret = riva128_mmio_read((riva128->rma.addr + (addr & 3)) & 0xffffff, riva128);*/nvidia_log("RIVA 128 MMIO write %08x %08x\n", riva128->rma.addr & 0xffffff, riva128->rma.data);
else ret = svga_read_linear((riva128->rma.addr - 0x1000000), svga);
break;
}
@@ -281,7 +303,7 @@ void riva128_rma_out(uint16_t addr, uint8_t val, void *p)
addr &= 0xff;
//pclog("RIVA 128 RMA write %04X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nvidia_log("RIVA 128 RMA write %04X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
switch(addr)
{
@@ -328,7 +350,7 @@ void riva128_rma_out(uint16_t addr, uint8_t val, void *p)
case 0x17:
riva128->rma.data &= ~0xff000000;
riva128->rma.data |= (val << 24);
if(riva128->rma.addr < 0x1000000) /*riva128_mmio_write_l(riva128->rma.addr & 0xffffff, riva128->rma.data, riva128);*/pclog("RIVA 128 MMIO write %08x %08x\n", riva128->rma.addr & 0xffffff, riva128->rma.data);
if(riva128->rma.addr < 0x1000000) /*riva128_mmio_write_l(riva128->rma.addr & 0xffffff, riva128->rma.data, riva128);*/nvidia_log("RIVA 128 MMIO write %08x %08x\n", riva128->rma.addr & 0xffffff, riva128->rma.data);
else svga_writel_linear((riva128->rma.addr - 0x1000000), riva128->rma.data, svga);
break;
}
@@ -345,7 +367,7 @@ uint8_t riva128_in(uint16_t addr, void *p)
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
// if (addr != 0x3da) pclog("S3 in %04X %04X:%08X ", addr, CS, cpu_state.pc);
// if (addr != 0x3da) nvidia_log("S3 in %04X %04X:%08X ", addr, CS, cpu_state.pc);
switch (addr)
{
case 0x3D4:
@@ -372,13 +394,13 @@ uint8_t riva128_in(uint16_t addr, void *p)
break;
}
//if(svga->crtcreg > 0x18)
// pclog("RIVA 128 Extended CRTC read %02X %04X:%08X\n", svga->crtcreg, CS, cpu_state.pc);
// nvidia_log("RIVA 128 Extended CRTC read %02X %04X:%08X\n", svga->crtcreg, CS, cpu_state.pc);
break;
default:
ret = svga_in(addr, svga);
break;
}
// if (addr != 0x3da) pclog("%02X\n", ret);
// if (addr != 0x3da) nvidia_log("%02X\n", ret);
return ret;
}
@@ -432,7 +454,7 @@ void riva128_out(uint16_t addr, uint8_t val, void *p)
break;
}
//if(svga->crtcreg > 0x18)
// pclog("RIVA 128 Extended CRTC write %02X %02x %04X:%08X\n", svga->crtcreg, val, CS, cpu_state.pc);
// nvidia_log("RIVA 128 Extended CRTC write %02X %02x %04X:%08X\n", svga->crtcreg, val, CS, cpu_state.pc);
if (old != val)
{
if (svga->crtcreg < 0xE || svga->crtcreg > 0x10)
@@ -451,7 +473,7 @@ uint8_t riva128_pci_read(int func, int addr, void *p)
{
riva128_t *riva128 = (riva128_t *)p;
uint8_t ret = 0;
//pclog("RIVA 128 PCI read %02X %04X:%08X\n", addr, CS, cpu_state.pc);
//nvidia_log("RIVA 128 PCI read %02X %04X:%08X\n", addr, CS, cpu_state.pc);
switch (addr)
{
case 0x00:
@@ -541,7 +563,7 @@ uint8_t riva128_pci_read(int func, int addr, void *p)
break;
}
// pclog("%02X\n", ret);
// nvidia_log("%02X\n", ret);
return ret;
}
@@ -570,7 +592,7 @@ void riva128_reenable_svga_mappings(svga_t *svga)
void riva128_pci_write(int func, int addr, uint8_t val, void *p)
{
//pclog("RIVA 128 PCI write %02X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
//nvidia_log("RIVA 128 PCI write %02X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
riva128_t *riva128 = (riva128_t *)p;
svga_t* svga = &riva128->svga;
switch (addr)
@@ -660,7 +682,7 @@ void riva128_pci_write(int func, int addr, uint8_t val, void *p)
if (riva128->pci_regs[0x30] & 0x01)
{
uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24);
// pclog("RIVA 128 bios_rom enabled at %08x\n", addr);
// nvidia_log("RIVA 128 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x8000);
}
return;
@@ -729,7 +751,7 @@ void riva128_recalctimings(svga_t *svga)
else
{
freq = (freq * riva128->pramdac.v_n) / (1 << riva128->pramdac.v_p) / riva128->pramdac.v_m;
//pclog("RIVA 128 Pixel clock is %f Hz\n", freq);
//nvidia_log("RIVA 128 Pixel clock is %f Hz\n", freq);
}
svga->clock = cpuclock / freq;
@@ -743,7 +765,7 @@ void riva128_recalctimings(svga_t *svga)
else
{
freq = (freq * riva128->pramdac.m_n) / (1 << riva128->pramdac.m_p) / riva128->pramdac.m_m;
//pclog("RIVA 128 Memory clock is %f Hz\n", freq);
//nvidia_log("RIVA 128 Memory clock is %f Hz\n", freq);
}
riva128->mfreq = freq;

49
src/video/vid_s3_virge.c
View File

@@ -8,7 +8,7 @@
*
* S3 ViRGE emulation.
*
* Version: @(#)vid_s3_virge.c 1.0.10 2018/04/26
* Version: @(#)vid_s3_virge.c 1.0.11 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -16,11 +16,13 @@
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../io.h"
#include "../mem.h"
@@ -318,6 +320,27 @@ enum
#define INT_3DF_EMP (1 << 6)
#define INT_MASK 0xff
#ifdef ENABLE_S3_VIRGE_LOG
int s3_virge_do_log = ENABLE_S3_VIRGE_LOG;
#endif
static void
s3_virge_log(const char *format, ...)
{
#ifdef ENABLE_S3_VIRGE_LOG
va_list ap;
if (s3_virge_do_log) {
va_start(ap, format);
pclog_ex(format, ap);
va_end(ap);
}
#endif
}
static void s3_virge_update_irqs(virge_t *virge)
{
if (!virge->pci)
@@ -658,7 +681,7 @@ static void s3_virge_updatemapping(virge_t *virge)
return;
}
//pclog("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc);
s3_virge_log("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc);
switch (svga->gdcreg[6] & 0xc) /*Banked framebuffer*/
{
case 0x0: /*128k at A0000*/
@@ -681,7 +704,7 @@ static void s3_virge_updatemapping(virge_t *virge)
virge->linear_base = (svga->crtc[0x5a] << 16) | (svga->crtc[0x59] << 24);
//pclog("Linear framebuffer %02X ", svga->crtc[0x58] & 0x10);
s3_virge_log("Linear framebuffer %02X ", svga->crtc[0x58] & 0x10);
if (svga->crtc[0x58] & 0x10) /*Linear framebuffer*/
{
switch (svga->crtc[0x58] & 3)
@@ -700,7 +723,7 @@ static void s3_virge_updatemapping(virge_t *virge)
break;
}
virge->linear_base &= ~(virge->linear_size - 1);
//pclog("Linear framebuffer at %08X size %08X\n", virge->linear_base, virge->linear_size);
s3_virge_log("Linear framebuffer at %08X size %08X\n", virge->linear_base, virge->linear_size);
if (virge->linear_base == 0xa0000)
{
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
@@ -716,7 +739,7 @@ static void s3_virge_updatemapping(virge_t *virge)
svga->fb_only = 0;
}
//pclog("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x18);
s3_virge_log("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x18);
if (svga->crtc[0x53] & 0x10) /*Old MMIO*/
{
if (svga->crtc[0x53] & 0x20)
@@ -1996,7 +2019,7 @@ static void s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat)
virge->s3d.rop = (virge->s3d.cmd_set >> 17) & 0xff;
virge->s3d.data_left_count = 0;
/* pclog("BitBlt start %i,%i %i,%i %i,%i %02X %x %x\n",
s3_virge_log("BitBlt start %i,%i %i,%i %i,%i %02X %x %x\n",
virge->s3d.src_x,
virge->s3d.src_y,
virge->s3d.dest_x,
@@ -2005,7 +2028,7 @@ static void s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat)
virge->s3d.h,
virge->s3d.rop,
virge->s3d.src_base,
virge->s3d.dest_base);*/
virge->s3d.dest_base);
if (virge->s3d.cmd_set & CMD_SET_IDS)
return;
@@ -2127,11 +2150,11 @@ static void s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat)
virge->s3d.h = virge->s3d.r_height;
virge->s3d.rop = (virge->s3d.cmd_set >> 17) & 0xff;
/* pclog("RctFll start %i,%i %i,%i %02X %08x\n", virge->s3d.dest_x,
s3_virge_log("RctFll start %i,%i %i,%i %02X %08x\n", virge->s3d.dest_x,
virge->s3d.dest_y,
virge->s3d.w,
virge->s3d.h,
virge->s3d.rop, virge->s3d.dest_base);*/
virge->s3d.rop, virge->s3d.dest_base);
}
while (count && virge->s3d.h)
@@ -3226,7 +3249,7 @@ static void s3_virge_triangle(virge_t *virge, s3d_t *s3d_tri)
dest_pixel = dest_pixel_lit_texture_decal;
break;
default:
/* pclog("bad triangle type %x\n", (s3d_tri->cmd_set >> 27) & 0xf); */
s3_virge_log("bad triangle type %x\n", (s3d_tri->cmd_set >> 27) & 0xf);
return;
}
break;
@@ -3235,7 +3258,7 @@ static void s3_virge_triangle(virge_t *virge, s3d_t *s3d_tri)
dest_pixel = dest_pixel_unlit_texture_triangle;
break;
default:
/* pclog("bad triangle type %x\n", (s3d_tri->cmd_set >> 27) & 0xf); */
s3_virge_log("bad triangle type %x\n", (s3d_tri->cmd_set >> 27) & 0xf);
return;
}
@@ -3291,7 +3314,7 @@ static void s3_virge_triangle(virge_t *virge, s3d_t *s3d_tri)
tex_read = (s3d_tri->cmd_set & CMD_SET_TWE) ? tex_ARGB1555 : tex_ARGB1555_nowrap;
break;
default:
/* pclog("bad texture type %i\n", (s3d_tri->cmd_set >> 5) & 7); */
s3_virge_log("bad texture type %i\n", (s3d_tri->cmd_set >> 5) & 7);
tex_read = (s3d_tri->cmd_set & CMD_SET_TWE) ? tex_ARGB1555 : tex_ARGB1555_nowrap;
break;
}

33
src/video/vid_table.c
View File

@@ -8,7 +8,7 @@
*
* Define all known video cards.
*
* Version: @(#)vid_table.c 1.0.27 2018/04/09
* Version: @(#)vid_table.c 1.0.29 2018/05/10
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -16,11 +16,13 @@
* Copyright 2016-2018 Miran Grca.
* Copyright 2017,2018 Fred N. van Kempen.
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../machine/machine.h"
#include "../mem.h"
@@ -112,7 +114,7 @@ video_cards[] = {
{ "[ISA] Hercules Plus", "hercules_plus", &herculesplus_device, GFX_HERCULESPLUS, VIDEO_FLAG_TYPE_MDA, {VIDEO_ISA, 8, 16, 32, 8, 16, 32}},
{ "[ISA] Hercules InColor", "incolor", &incolor_device, GFX_INCOLOR, VIDEO_FLAG_TYPE_MDA, {VIDEO_ISA, 8, 16, 32, 8, 16, 32}},
{ "[ISA] MDA", "mda", &mda_device, GFX_MDA, VIDEO_FLAG_TYPE_MDA, {VIDEO_ISA, 8, 16, 32, 8, 16, 32}},
{ "[ISA] MDSI Genius", "genius", &genius_device, GFX_GENIUS, VIDEO_FLAG_TYPE_CGA, {VIDEO_ISA, 8, 16, 32, 8, 16, 32}},
{ "[ISA] MDSI Genius", "genius", &genius_device, GFX_GENIUS, VIDEO_FLAG_TYPE_MDA, {VIDEO_ISA, 8, 16, 32, 8, 16, 32}},
{ "[ISA] OAK OTI-037C", "oti037c", &oti037c_device, GFX_OTI037C, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_ISA, 6, 8, 16, 6, 8, 16}},
{ "[ISA] OAK OTI-067", "oti067", &oti067_device, GFX_OTI067, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_ISA, 6, 8, 16, 6, 8, 16}},
{ "[ISA] OAK OTI-077", "oti077", &oti077_device, GFX_OTI077, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_ISA, 6, 8, 16, 6, 8, 16}},
@@ -133,6 +135,7 @@ video_cards[] = {
{"[PCI] Cirrus Logic CL-GD 5430", "cl_gd5430_pci", &gd5430_pci_device, GFX_CL_GD5430_PCI, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
{"[PCI] Cirrus Logic CL-GD 5434", "cl_gd5434_pci", &gd5434_pci_device, GFX_CL_GD5434_PCI, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
{"[PCI] Cirrus Logic CL-GD 5436", "cl_gd5436_pci", &gd5436_pci_device, GFX_CL_GD5436_PCI, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
{"[PCI] Cirrus Logic CL-GD 5440", "cl_gd5440_pci", &gd5440_pci_device, GFX_CL_GD5440_PCI, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
{"[PCI] Cirrus Logic CL-GD 5446", "cl_gd5446_pci", &gd5446_pci_device, GFX_CL_GD5446_PCI, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
{"[PCI] Cirrus Logic CL-GD 5480", "cl_gd5480_pci", &gd5480_pci_device, GFX_CL_GD5480_PCI, VIDEO_FLAG_TYPE_SPECIAL, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
@@ -181,10 +184,30 @@ video_cards[] = {
};
#ifdef ENABLE_VID_TABLE_LOG
int vid_table_do_log = ENABLE_VID_TABLE_LOG;
#endif
static void
vid_table_log(const char *fmt, ...)
{
#ifdef ENABLE_VID_TABLE_LOG
va_list ap;
if (vid_table_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
#endif
}
void
video_reset(int card)
{
pclog("VIDEO: reset (romset=%d, gfxcard=%d, internal=%d)\n",
vid_table_log("VIDEO: reset (romset=%d, gfxcard=%d, internal=%d)\n",
romset, card, (machines[machine].flags & MACHINE_VIDEO)?1:0);
/* Reset the CGA palette. */
@@ -199,7 +222,7 @@ video_reset(int card)
/* Do not initialize internal cards here. */
if (!(card == GFX_NONE) && \
!(card == GFX_INTERNAL) && !machines[machine].fixed_gfxcard) {
pclog("VIDEO: initializing '%s'\n", video_cards[video_old_to_new(card)].name);
vid_table_log("VIDEO: initializing '%s'\n", video_cards[video_old_to_new(card)].name);
/* Initialize the video card. */
device_add(video_cards[video_old_to_new(card)].device);

7
src/video/vid_ti_cf62011.c
View File

@@ -42,7 +42,7 @@
* which are the same as the XGA. It supports up to 1MB of VRAM,
* but we lock it down to 512K. The PS/1 2122 had 256K.
*
* Version: @(#)vid_ti_cf62011.c 1.0.6 2018/04/26
* Version: @(#)vid_ti_cf62011.c 1.0.7 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -95,7 +95,6 @@ vid_out(uint16_t addr, uint8_t val, void *priv)
if (((addr & 0xfff0) == 0x03d0 || (addr & 0xfff0) == 0x03b0) &&
!(svga->miscout & 1)) addr ^= 0x60;
#endif
// pclog("TISVGA_out(%04x, %02x)\n", addr, val);
switch (addr) {
case 0x0102:
@@ -199,8 +198,6 @@ vid_in(uint16_t addr, void *priv)
break;
}
// pclog("TISVGA_in(%04x) = %02x\n", addr, ret);
return(ret);
}
@@ -249,8 +246,6 @@ vid_init(const device_t *info)
else
ti->vram_size = info->local;
pclog("VIDEO: initializing %s, %dK VRAM\n", info->name, ti->vram_size);
svga_init(&ti->svga, ti,
ti->vram_size<<10,
NULL, vid_in, vid_out, NULL, NULL);

4
src/video/vid_wy700.c
View File

@@ -8,7 +8,7 @@
*
* Wyse-700 emulation.
*
* Version: @(#)vid_wy700.c 1.0.8 2018/04/26
* Version: @(#)vid_wy700.c 1.0.9 2018/05/20
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -906,6 +906,8 @@ void *wy700_init(const device_t *info)
/* 128k video RAM */
wy700->vram = malloc(0x20000);
loadfont(L"roms/video/wyse700/wy700.rom", 3);
timer_add(wy700_poll, &wy700->vidtime, TIMER_ALWAYS_ENABLED, wy700);
/* Occupy memory between 0xB0000 and 0xBFFFF (moves to 0xA0000 in

6
src/video/video.c
View File

@@ -40,7 +40,7 @@
* W = 3 bus clocks
* L = 4 bus clocks
*
* Version: @(#)video.c 1.0.21 2018/03/19
* Version: @(#)video.c 1.0.22 2018/04/29
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -691,10 +691,8 @@ loadfont(wchar_t *s, int format)
int c,d;
f = rom_fopen(s, L"rb");
if (f == NULL) {
pclog("VIDEO: cannot load font '%ls', fmt=%d\n", s, format);
if (f == NULL)
return;
}
switch (format) {
case 0: /* MDA */

6
src/video/video.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the video controller module.
*
* Version: @(#)video.h 1.0.26 2018/04/09
* Version: @(#)video.h 1.0.27 2018/05/20
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -22,9 +22,6 @@
# define EMU_VIDEO_H
#define FONT_ATIKOR_PATH L"roms/video/ati28800/ati_ksc5601.rom"
#define makecol(r, g, b) ((b) | ((g) << 8) | ((r) << 16))
#define makecol32(r, g, b) ((b) | ((g) << 8) | ((r) << 16))
@@ -89,6 +86,7 @@ enum {
GFX_CL_GD5434_VLB, /* Cirrus Logic CL-GD 5434 VLB */
GFX_CL_GD5434_PCI, /* Cirrus Logic CL-GD 5434 PCI */
GFX_CL_GD5436_PCI, /* Cirrus Logic CL-GD 5436 PCI */
GFX_CL_GD5440_PCI, /* Cirrus Logic CL-GD 5440 PCI */
GFX_CL_GD5446_PCI, /* Cirrus Logic CL-GD 5446 PCI */
GFX_CL_GD5446_STB_PCI, /* STB Nitro 64V (Cirrus Logic CL-GD 5446) PCI */
GFX_CL_GD5480_PCI, /* Cirrus Logic CL-GD 5480 PCI */