From 0f2301c9bf5eeea55a8d2c326319a3b32304acc0 Mon Sep 17 00:00:00 2001 From: OBattler Date: Fri, 28 Apr 2023 23:38:55 +0200 Subject: [PATCH 1/9] The SiS 50x now initializes the PS/2 keyboard and mouse IRQ latch if a PS/2 keyboard controller is present, needed for the AMI WinBIOS CMOS setup on the Excalibur PCI II. --- src/chipset/sis_85c50x.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/chipset/sis_85c50x.c b/src/chipset/sis_85c50x.c index 56d3a0a30..ebd166d60 100644 --- a/src/chipset/sis_85c50x.c +++ b/src/chipset/sis_85c50x.c @@ -29,6 +29,7 @@ #include <86box/timer.h> #include <86box/apm.h> +#include <86box/machine.h> #include <86box/mem.h> #include <86box/smram.h> #include <86box/pci.h> @@ -416,6 +417,11 @@ sis_85c50x_init(const device_t *info) sis_85c50x_reset(dev); + if (machine_has_bus(machine, MACHINE_BUS_PS2)) { + pic_kbd_latch(0x01); + pic_mouse_latch(0x01); + } + return dev; } From 310dbd1079d6023ef8a6a7128c07c36d2ac91134 Mon Sep 17 00:00:00 2001 From: cartifanwlr <109605173+cartifanwlr@users.noreply.github.com> Date: Sat, 29 Apr 2023 12:12:50 +0300 Subject: [PATCH 2/9] Fix build by adding pic.h include in sis_85c50x.c --- src/chipset/sis_85c50x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/chipset/sis_85c50x.c b/src/chipset/sis_85c50x.c index ebd166d60..ebb895db7 100644 --- a/src/chipset/sis_85c50x.c +++ b/src/chipset/sis_85c50x.c @@ -30,6 +30,7 @@ #include <86box/apm.h> #include <86box/machine.h> +#include <86box/pic.h> #include <86box/mem.h> #include <86box/smram.h> #include <86box/pci.h> From 19ce34787d30cc35848063c5d225de980106c8bd Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 29 Apr 2023 18:05:20 +0200 Subject: [PATCH 3/9] Implemented the x87 instruction FXTRACT. --- src/cpu/x87_ops.h | 21 ++++++++++++++++----- src/cpu/x87_ops_misc.h | 14 ++++++++++++++ 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/src/cpu/x87_ops.h b/src/cpu/x87_ops.h index c00cdff16..faac0ea60 100644 --- a/src/cpu/x87_ops.h +++ b/src/cpu/x87_ops.h @@ -46,6 +46,17 @@ static int rounding_modes[4] = { FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARD #define STATUS_ZERODIVIDE 4 +typedef union +{ + double d; + + struct { + unsigned int mantissa:52; + unsigned int exponent:11; + unsigned int negative:1; + }; +} double_decompose; + #if defined(_MSC_VER) && !defined(__clang__) # if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 # define X87_INLINE_ASM @@ -570,7 +581,7 @@ const OpFn OP_TABLE(fpu_8087_d9)[256] = { ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, /*Invalid*/ opFCHS, opFABS, ILLEGAL_a16, ILLEGAL_a16, opFTST, opFXAM, ILLEGAL_a16, ILLEGAL_a16, opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a16, - opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a16, ILLEGAL_a16, opFDECSTP, opFINCSTP, + opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP, opFPREM, opFYL2XP1, opFSQRT, ILLEGAL_a16, opFRNDINT, opFSCALE, ILLEGAL_a16, ILLEGAL_a16 // clang-format on }; @@ -839,7 +850,7 @@ const OpFn OP_TABLE(fpu_287_d9_a16)[256] = { ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, /*Invalid*/ opFCHS, opFABS, ILLEGAL_a16, ILLEGAL_a16, opFTST, opFXAM, ILLEGAL_a16, ILLEGAL_a16, opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a16, - opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a16, opFPREM1, opFDECSTP, opFINCSTP, + opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP, opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS // clang-format on }; @@ -879,7 +890,7 @@ const OpFn OP_TABLE(fpu_287_d9_a32)[256] = { ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, /*Invalid*/ opFCHS, opFABS, ILLEGAL_a32, ILLEGAL_a32, opFTST, opFXAM, ILLEGAL_a32, ILLEGAL_a32, opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a32, - opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a32, opFPREM1, opFDECSTP, opFINCSTP, + opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP, opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS // clang-format on }; @@ -919,7 +930,7 @@ const OpFn OP_TABLE(fpu_d9_a16)[256] = { opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, /*Invalid*/ opFCHS, opFABS, ILLEGAL_a16, ILLEGAL_a16, opFTST, opFXAM, ILLEGAL_a16, ILLEGAL_a16, opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a16, - opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a16, opFPREM1, opFDECSTP, opFINCSTP, + opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP, opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS // clang-format on }; @@ -959,7 +970,7 @@ const OpFn OP_TABLE(fpu_d9_a32)[256] = { opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, /*Invalid*/ opFCHS, opFABS, ILLEGAL_a32, ILLEGAL_a32, opFTST, opFXAM, ILLEGAL_a32, ILLEGAL_a32, opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a32, - opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a32, opFPREM1, opFDECSTP, opFINCSTP, + opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP, opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS // clang-format on }; diff --git a/src/cpu/x87_ops_misc.h b/src/cpu/x87_ops_misc.h index 091d7cc31..a7295b0a3 100644 --- a/src/cpu/x87_ops_misc.h +++ b/src/cpu/x87_ops_misc.h @@ -33,6 +33,20 @@ opFNOP(uint32_t fetchdat) return 0; } +static int +opFXTRACT(uint32_t fetchdat) +{ + double_decompose_t temp = (double_decompose_t) ST(0); + + FP_ENTER(); + cpu_state.pc++; + ST(0) = (double) temp.exponent; + x87_push((double) temp.mantissa); + CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fxtract) : (x87_timings.fxtract * cpu_multi)); + CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fxtract) : (x87_concurrency.fxtract * cpu_multi)); + return 0; +} + static int opFCLEX(uint32_t fetchdat) { From 4aedbc44be31d796645299a2c72655e4c9651a89 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 29 Apr 2023 18:08:36 +0200 Subject: [PATCH 4/9] Removed a now obsolete #ifdef. --- src/cpu/x87_ops_misc.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/cpu/x87_ops_misc.h b/src/cpu/x87_ops_misc.h index a7295b0a3..3a528f847 100644 --- a/src/cpu/x87_ops_misc.h +++ b/src/cpu/x87_ops_misc.h @@ -755,7 +755,6 @@ opFPREM(uint32_t fetchdat) CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fprem) : (x87_concurrency.fprem * cpu_multi)); return 0; } -#ifndef FPU_8087 static int opFPREM1(uint32_t fetchdat) { @@ -776,7 +775,6 @@ opFPREM1(uint32_t fetchdat) CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fprem1) : (x87_concurrency.fprem1 * cpu_multi)); return 0; } -#endif static int opFSQRT(uint32_t fetchdat) From 6e853aa7569d74569108508c3d5a399e514934dd Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 29 Apr 2023 18:14:44 +0200 Subject: [PATCH 5/9] Use uint64_t's, they can actually hold that many bits. --- src/cpu/x87_ops.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/x87_ops.h b/src/cpu/x87_ops.h index faac0ea60..1a729475c 100644 --- a/src/cpu/x87_ops.h +++ b/src/cpu/x87_ops.h @@ -51,9 +51,9 @@ typedef union double d; struct { - unsigned int mantissa:52; - unsigned int exponent:11; - unsigned int negative:1; + uint64_t mantissa:52; + uint64_t exponent:11; + uint64_t negative:1; }; } double_decompose; From 071c05e65fc300dd4c408ca28ee90ec4a15bfe00 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 29 Apr 2023 18:16:41 +0200 Subject: [PATCH 6/9] Fixed the typedef's name. --- src/cpu/x87_ops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x87_ops.h b/src/cpu/x87_ops.h index 1a729475c..b2b082107 100644 --- a/src/cpu/x87_ops.h +++ b/src/cpu/x87_ops.h @@ -55,7 +55,7 @@ typedef union uint64_t exponent:11; uint64_t negative:1; }; -} double_decompose; +} double_decompose_t; #if defined(_MSC_VER) && !defined(__clang__) # if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 From 61c0999d57a8dca08298c60d8d2fe07b9b040b6b Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Sat, 29 Apr 2023 22:43:29 +0600 Subject: [PATCH 7/9] OHCI: Replace magic numbers with named enums --- src/usb.c | 216 +++++++++++++++++++++++++++++------------------------- 1 file changed, 118 insertions(+), 98 deletions(-) diff --git a/src/usb.c b/src/usb.c index 75e60d438..eecb2902c 100644 --- a/src/usb.c +++ b/src/usb.c @@ -131,6 +131,35 @@ uhci_update_io_mapping(usb_t *dev, uint8_t base_l, uint8_t base_h, int enable) io_sethandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev); } +/* OHCI registers */ +enum +{ + OHCI_HcRevision = 0x00, + OHCI_HcControl = 0x04, + OHCI_HcCommandStatus = 0x08, + OHCI_HcInterruptStatus = 0x0C, + OHCI_HcInterruptEnable = 0x10, + OHCI_HcInterruptDisable = 0x14, + OHCI_HcHCCA = 0x18, + OHCI_HcPeriodCurrentED = 0x1C, + OHCI_HcControlHeadED = 0x20, + OHCI_HcControlCurrentED = 0x24, + OHCI_HcBulkHeadED = 0x28, + OHCI_HcBulkCurrentED = 0x2C, + OHCI_HcDoneHead = 0x30, + OHCI_HcFMInterval = 0x34, + OHCI_HcFmRemaining = 0x38, + OHCI_HcFmNumber = 0x3C, + OHCI_HcPeriodicStart = 0x40, + OHCI_HcLSThreshold = 0x44, + OHCI_HcRhDescriptorA = 0x48, + OHCI_HcRhDescriptorB = 0x4C, + OHCI_HcRhStatus = 0x50, + OHCI_HcRhPortStatus1 = 0x54, + OHCI_HcRhPortStatus2 = 0x58, + OHCI_HcRhPortStatus3 = 0x5C +}; + static uint8_t ohci_mmio_read(uint32_t addr, void *p) { @@ -156,132 +185,132 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p) addr &= 0x00000fff; switch (addr) { - case 0x04: + case OHCI_HcControl: if ((val & 0xc0) == 0x00) { /* UsbReset */ - dev->ohci_mmio[0x56] = dev->ohci_mmio[0x5a] = 0x16; + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 2] = dev->ohci_mmio[OHCI_HcRhPortStatus2 + 2] = 0x16; } break; - case 0x08: /* HCCOMMANDSTATUS */ + case OHCI_HcCommandStatus: /* bit OwnershipChangeRequest triggers an ownership change (SMM <-> OS) */ if (val & 0x08) { - dev->ohci_mmio[0x0f] = 0x40; - if ((dev->ohci_mmio[0x13] & 0xc0) == 0xc0) + dev->ohci_mmio[OHCI_HcInterruptStatus + 3] = 0x40; + if ((dev->ohci_mmio[OHCI_HcInterruptEnable + 3] & 0xc0) == 0xc0) smi_raise(); } /* bit HostControllerReset must be cleared for the controller to be seen as initialized */ if (val & 0x01) { memset(dev->ohci_mmio, 0x00, 4096); - dev->ohci_mmio[0x00] = 0x10; - dev->ohci_mmio[0x01] = 0x01; - dev->ohci_mmio[0x48] = 0x02; + dev->ohci_mmio[OHCI_HcRevision] = 0x10; + dev->ohci_mmio[OHCI_HcRevision + 1] = 0x01; + dev->ohci_mmio[OHCI_HcRhDescriptorA] = 0x02; val &= ~0x01; } break; - case 0x0c: + case OHCI_HcInterruptStatus: dev->ohci_mmio[addr] &= ~(val & 0x7f); return; - case 0x0d: - case 0x0e: + case OHCI_HcInterruptStatus + 1: + case OHCI_HcInterruptStatus + 2: return; - case 0x0f: + case OHCI_HcInterruptStatus + 3: dev->ohci_mmio[addr] &= ~(val & 0x40); return; - case 0x3b: + case OHCI_HcFmRemaining + 3: dev->ohci_mmio[addr] = (val & 0x80); return; - case 0x39: - case 0x41: + case OHCI_HcFmRemaining + 1: + case OHCI_HcPeriodicStart + 1: dev->ohci_mmio[addr] = (val & 0x3f); return; - case 0x45: + case OHCI_HcLSThreshold + 1: dev->ohci_mmio[addr] = (val & 0x0f); return; - case 0x3a: - case 0x3e: - case 0x3f: - case 0x42: - case 0x43: - case 0x46: - case 0x47: - case 0x48: - case 0x4a: + case OHCI_HcFmRemaining + 2: + case OHCI_HcFmNumber + 2: + case OHCI_HcFmNumber + 3: + case OHCI_HcPeriodicStart + 2: + case OHCI_HcPeriodicStart + 3: + case OHCI_HcLSThreshold + 2: + case OHCI_HcLSThreshold + 3: + case OHCI_HcRhDescriptorA: + case OHCI_HcRhDescriptorA + 2: return; - case 0x49: + case OHCI_HcRhDescriptorA + 1: dev->ohci_mmio[addr] = (val & 0x1b); if (val & 0x02) { - dev->ohci_mmio[0x55] |= 0x01; - dev->ohci_mmio[0x59] |= 0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 1] |= 0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 1] |= 0x01; } return; - case 0x4b: + case OHCI_HcRhDescriptorA + 3: dev->ohci_mmio[addr] = (val & 0x03); return; - case 0x4c: - case 0x4e: + case OHCI_HcRhDescriptorB: + case OHCI_HcRhDescriptorB + 2: dev->ohci_mmio[addr] = (val & 0x06); - if ((addr == 0x4c) && !(val & 0x04)) { - if (!(dev->ohci_mmio[0x58] & 0x01)) - dev->ohci_mmio[0x5a] |= 0x01; - dev->ohci_mmio[0x58] |= 0x01; + if ((addr == OHCI_HcRhDescriptorB) && !(val & 0x04)) { + if (!(dev->ohci_mmio[OHCI_HcRhPortStatus2] & 0x01)) + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 2] |= 0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus2] |= 0x01; } - if ((addr == 0x4c) && !(val & 0x02)) { - if (!(dev->ohci_mmio[0x54] & 0x01)) - dev->ohci_mmio[0x56] |= 0x01; - dev->ohci_mmio[0x54] |= 0x01; + if ((addr == OHCI_HcRhDescriptorB) && !(val & 0x02)) { + if (!(dev->ohci_mmio[OHCI_HcRhPortStatus1] & 0x01)) + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 2] |= 0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus1] |= 0x01; } return; - case 0x4d: - case 0x4f: + case OHCI_HcRhDescriptorB + 1: + case OHCI_HcRhDescriptorB + 3: return; - case 0x50: + case OHCI_HcRhStatus: if (val & 0x01) { - if ((dev->ohci_mmio[0x49] & 0x03) == 0x00) { - dev->ohci_mmio[0x55] &= ~0x01; - dev->ohci_mmio[0x54] &= ~0x17; - dev->ohci_mmio[0x56] &= ~0x17; - dev->ohci_mmio[0x59] &= ~0x01; - dev->ohci_mmio[0x58] &= ~0x17; - dev->ohci_mmio[0x5a] &= ~0x17; - } else if ((dev->ohci_mmio[0x49] & 0x03) == 0x01) { - if (!(dev->ohci_mmio[0x4e] & 0x02)) { - dev->ohci_mmio[0x55] &= ~0x01; - dev->ohci_mmio[0x54] &= ~0x17; - dev->ohci_mmio[0x56] &= ~0x17; + if ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x00) { + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 1] &= ~0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus1] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 2] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 1] &= ~0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus2] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 2] &= ~0x17; + } else if ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x01) { + if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x02)) { + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 1] &= ~0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus1] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 2] &= ~0x17; } - if (!(dev->ohci_mmio[0x4e] & 0x04)) { - dev->ohci_mmio[0x59] &= ~0x01; - dev->ohci_mmio[0x58] &= ~0x17; - dev->ohci_mmio[0x5a] &= ~0x17; + if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x04)) { + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 1] &= ~0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus2] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 2] &= ~0x17; } } } return; - case 0x51: + case OHCI_HcRhStatus + 1: if (val & 0x80) dev->ohci_mmio[addr] |= 0x80; return; - case 0x52: + case OHCI_HcRhStatus + 2: dev->ohci_mmio[addr] &= ~(val & 0x02); if (val & 0x01) { - if ((dev->ohci_mmio[0x49] & 0x03) == 0x00) { - dev->ohci_mmio[0x55] |= 0x01; - dev->ohci_mmio[0x59] |= 0x01; - } else if ((dev->ohci_mmio[0x49] & 0x03) == 0x01) { - if (!(dev->ohci_mmio[0x4e] & 0x02)) - dev->ohci_mmio[0x55] |= 0x01; - if (!(dev->ohci_mmio[0x4e] & 0x04)) - dev->ohci_mmio[0x59] |= 0x01; + if ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x00) { + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 1] |= 0x01; + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 1] |= 0x01; + } else if ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x01) { + if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x02)) + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 1] |= 0x01; + if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x04)) + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 1] |= 0x01; } } return; - case 0x53: + case OHCI_HcRhStatus + 3: if (val & 0x80) - dev->ohci_mmio[0x51] &= ~0x80; + dev->ohci_mmio[OHCI_HcRhStatus + 1] &= ~0x80; return; - case 0x54: - case 0x58: + case OHCI_HcRhPortStatus1: + case OHCI_HcRhPortStatus2: old = dev->ohci_mmio[addr]; if (val & 0x10) { @@ -315,30 +344,30 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p) /* if (!(dev->ohci_mmio[addr] & 0x02)) dev->ohci_mmio[addr + 2] |= 0x02; */ return; - case 0x55: - if ((val & 0x02) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x02)) { + case OHCI_HcRhPortStatus1 + 1: + if ((val & 0x02) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x02)) { dev->ohci_mmio[addr] &= ~0x01; - dev->ohci_mmio[0x54] &= ~0x17; - dev->ohci_mmio[0x56] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus1] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus1 + 2] &= ~0x17; } - if ((val & 0x01) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x02)) { + if ((val & 0x01) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x02)) { dev->ohci_mmio[addr] |= 0x01; - dev->ohci_mmio[0x58] &= ~0x17; - dev->ohci_mmio[0x5a] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus2] &= ~0x17; + dev->ohci_mmio[OHCI_HcRhPortStatus2 + 2] &= ~0x17; } return; - case 0x59: - if ((val & 0x02) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x04)) + case OHCI_HcRhPortStatus2 + 1: + if ((val & 0x02) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x04)) dev->ohci_mmio[addr] &= ~0x01; - if ((val & 0x01) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x04)) + if ((val & 0x01) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA + 1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB + 2] & 0x04)) dev->ohci_mmio[addr] |= 0x01; return; - case 0x56: - case 0x5a: + case OHCI_HcRhPortStatus1 + 2: + case OHCI_HcRhPortStatus2 + 2: dev->ohci_mmio[addr] &= ~(val & 0x1f); return; - case 0x57: - case 0x5b: + case OHCI_HcRhPortStatus1 + 3: + case OHCI_HcRhPortStatus2 + 3: return; } @@ -368,9 +397,9 @@ usb_reset(void *priv) dev->uhci_io[0x10] = dev->uhci_io[0x12] = 0x80; memset(dev->ohci_mmio, 0x00, 4096); - dev->ohci_mmio[0x00] = 0x10; - dev->ohci_mmio[0x01] = 0x01; - dev->ohci_mmio[0x48] = 0x02; + dev->ohci_mmio[OHCI_HcRevision] = 0x10; + dev->ohci_mmio[OHCI_HcRevision + 1] = 0x01; + dev->ohci_mmio[OHCI_HcRhDescriptorA] = 0x02; io_removehandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev); dev->uhci_enable = 0; @@ -397,15 +426,6 @@ usb_init(const device_t *info) return (NULL); memset(dev, 0x00, sizeof(usb_t)); - memset(dev->uhci_io, 0x00, 128); - dev->uhci_io[0x0c] = 0x40; - dev->uhci_io[0x10] = dev->uhci_io[0x12] = 0x80; - - memset(dev->ohci_mmio, 0x00, 4096); - dev->ohci_mmio[0x00] = 0x10; - dev->ohci_mmio[0x01] = 0x01; - dev->ohci_mmio[0x48] = 0x02; - mem_mapping_add(&dev->ohci_mmio_mapping, 0, 0, ohci_mmio_read, NULL, NULL, ohci_mmio_write, NULL, NULL, From 7e90e9215aebd3f87ed7d10c30179f21c96d2eef Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Sun, 30 Apr 2023 00:59:11 +0600 Subject: [PATCH 8/9] OHCI: HcHCCA's lower 8 bits are always zero Start of work on USB endpoint device infrastructure --- src/include/86box/usb.h | 8 ++++++++ src/usb.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/src/include/86box/usb.h b/src/include/86box/usb.h index d0b169b6c..ab0549844 100644 --- a/src/include/86box/usb.h +++ b/src/include/86box/usb.h @@ -22,6 +22,7 @@ extern "C" { #endif +/* USB Host Controller device struct */ typedef struct { uint8_t uhci_io[32], ohci_mmio[4096]; @@ -31,6 +32,13 @@ typedef struct mem_mapping_t ohci_mmio_mapping; } usb_t; +/* USB endpoint device struct. Incomplete and unused. */ +typedef struct +{ + uint16_t vendor_id; + uint16_t device_id; +} usb_device_t; + /* Global variables. */ extern const device_t usb_device; diff --git a/src/usb.c b/src/usb.c index eecb2902c..e9702afa7 100644 --- a/src/usb.c +++ b/src/usb.c @@ -208,6 +208,8 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p) val &= ~0x01; } break; + case OHCI_HcHCCA: + return; case OHCI_HcInterruptStatus: dev->ohci_mmio[addr] &= ~(val & 0x7f); return; From 3ea8a9607fdae391a81ba9da5848c728093a3420 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sun, 30 Apr 2023 00:32:50 +0200 Subject: [PATCH 9/9] Replaced my implmenetation of FXTRACT with TC1995's. --- src/cpu/x87_ops_misc.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/x87_ops_misc.h b/src/cpu/x87_ops_misc.h index 3a528f847..21fd4c084 100644 --- a/src/cpu/x87_ops_misc.h +++ b/src/cpu/x87_ops_misc.h @@ -36,12 +36,19 @@ opFNOP(uint32_t fetchdat) static int opFXTRACT(uint32_t fetchdat) { - double_decompose_t temp = (double_decompose_t) ST(0); + x87_conv_t test; + int64_t exp80, exp80final; + double mant; FP_ENTER(); cpu_state.pc++; - ST(0) = (double) temp.exponent; - x87_push((double) temp.mantissa); + test.eind.d = ST(0); + exp80 = test.eind.ll & (0x7ff0000000000000ll); + exp80final = (exp80 >> 52) - BIAS64; + mant = test.eind.d / (pow(2.0, (double)exp80final)); + ST(0) = (double)exp80final; + FP_TAG_VALID; + x87_push(mant); CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fxtract) : (x87_timings.fxtract * cpu_multi)); CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fxtract) : (x87_concurrency.fxtract * cpu_multi)); return 0;