diff --git a/src/include/86box/nv/vid_nv1.h b/src/include/86box/nv/vid_nv1.h index 98518e530..9d08bb186 100644 --- a/src/include/86box/nv/vid_nv1.h +++ b/src/include/86box/nv/vid_nv1.h @@ -17,6 +17,7 @@ #include #include +#include <86Box/nv/vid_nv.h> extern const device_config_t nv1_config[]; // Config for RIVA 128 (revision A/B) @@ -152,6 +153,12 @@ extern const device_config_t nv1_config[]; // Confi #define NV1_PROM 0x601000 #define NV1_PROM_SIZE 32768 +// Structures +typedef struct nv1_s +{ + nv_base_t nvbase; // Base Nvidia structure +} nv1_t; + // Device Core void nv1_init(); void nv1_close(void* priv); diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 8f2a20026..7fef843d4 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -16,121 +16,19 @@ #pragma once +#include +#include +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv4_defines.h> extern const device_config_t nv4_config[]; // Config for RIVA 128 (revision A/B) -// -// General -// -#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) -#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) -#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB -#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB -#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only -#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! -// -// VBIOS -// -#define NV4_VBIOS_STB_REVA "roms/video/nvidia/nv4/NV4_STB_velocity.rom" - -// -// PMC -// - -#define NV4_PMC_START 0x0 - -#define NV4_PMC_INTR 0x100 -#define NV4_PMC_INTR_PMEDIA_PENDING 4 -#define NV4_PMC_INTR_PFIFO_PENDING 8 -#define NV4_PMC_INTR_PGRAPH_PENDING 12 -#define NV4_PMC_INTR_PVIDEO_PENDING 16 -#define NV4_PMC_INTR_PTIMER_PENDING 20 -#define NV4_PMC_INTR_PCRTC_PENDING 24 -#define NV4_PMC_INTR_PBUS_PENDING 28 -#define NV4_PMC_INTR_SOFTWARE_PENDING 31 - -#define NV4_PMC_INTR_EN 0x140 -#define NV4_PMC_INTR_EN_DISABLED 0x0 -#define NV4_PMC_INTR_EN_SOFTWARE 0x1 -#define NV4_PMC_INTR_EN_HARDWARE 0x2 -#define NV4_PMC_INTR_EN_ALL 0x3 - -#define NV4_PMC_BOOT 0x0 -#define NV4_PMC_ENABLE 0x200 -#define NV4_PMC_ENABLE_PMEDIA 4 // Enable mediaport external MPEG decoder engine -#define NV4_PMC_ENABLE_PFIFO 8 // Enable FIFO -#define NV4_PMC_ENABLE_PGRAPH 12 -#define NV4_PMC_ENABLE_PPMI 16 -#define NV4_PMC_ENABLE_PFB 20 -#define NV4_PMC_ENABLE_PCRTC 24 -#define NV4_PMC_ENABLE_PVIDEO 28 - -// -// PFB -// - -#define NV4_PFB_START 0x100000 -#define NV4_PFB_BOOT 0x100000 -#define NV4_PFB_BOOT_RAM_AMOUNT 0 -#define NV4_PFB_BOOT_RAM_AMOUNT_2MB 0x0 -#define NV4_PFB_BOOT_RAM_AMOUNT_4MB 0x1 -#define NV4_PFB_BOOT_RAM_AMOUNT_8MB 0x2 -#define NV4_PFB_BOOT_RAM_AMOUNT_16MB 0x3 -#define NV5_PFB_BOOT_RAM_AMOUNT_32MB 0x0 - -#define NV4_PSTRAPS 0x101000 - -#define NV4_PSTRAPS_CRYSTAL 6 -#define NV4_PSTRAPS_CRYSTAL_13500K 0x0 -#define NV4_PSTRAPS_CRYSTAL_14318180 0x1 - -// -// PRAMDAC -// - -#define NV4_PRAMDAC_START 0x680300 -#define NV4_PRAMDAC_CURSOR_START_POSITION 0x680300 - -#define NV4_PRAMDAC_CURSOR_SIZE_X 32 -#define NV4_PRAMDAC_CURSOR_SIZE_Y 32 - -// Same for all 3 clocks -#define NV4_PRAMDAC_CLOCK_VDIV 0 -#define NV4_PRAMDAC_CLOCK_NDIV 8 -#define NV4_PRAMDAC_CLOCK_PDIV 16 - -#define NV4_PRAMDAC_CLOCK_CORE 0x680500 // NVPLL -#define NV4_PRAMDAC_CLOCK_MEMORY 0x680504 -#define NV4_PRAMDAC_CLOCK_PIXEL 0x680508 -#define NV4_PRAMDAC_COEFF_SELECT 0x68050C -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE 0 -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE_VIP 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_SOURCE 8 // Bit not set = hardware, otherwise software -#define NV4_PRAMDAC_COEFF_SELECT_MPLL_IS_SOFTWARE 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_IS_SOFTWARE 0x2 -#define NV4_PRAMDAC_COEFF_SELECT_NVPLL_IS_SOFTWARE 0x4 -#define NV4_PRAMDAC_COEFF_SELECT_ALL_SOFTWARE 0x7 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV 16 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_NONE 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_PCLK 0x2 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_BOTH 0x3 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE 20 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE_EXT 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE_VIP 0x1 // VIP = Video Interface Port / Mediaport -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO 24 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO_DB1 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO_DB2 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO 28 -#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO_DB1 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO_DB2 0x1 - -#define NV4_PRAMDAC_GENERAL_CONTROL 0x680600 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12 - -#define NV4_RAMIN_START 0x700000 // Nominal. In reality PROM is here on real NV4 +// Structures +typedef struct nv4_s +{ + nv_base_t nvbase; // Base Nvidia structure +} nv4_t; // Device Core void nv4_init(); diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h new file mode 100644 index 000000000..f7499e3a8 --- /dev/null +++ b/src/include/86box/nv/vid_nv4_defines.h @@ -0,0 +1,4314 @@ +#pragma once + +#include +#include + +// +// General +// +#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) +#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) +#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB +#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB +#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only + +#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! + +// +// VBIOS +// +#define NV4_VBIOS_STB_REVA "roms/video/nvidia/nv4/NV4_STB_velocity.rom" + +#define NV4_PRMIO_START 0x7000 +#define NV4_PRMIO_END 0x7FFF +#define NV4_PRMIO_RMA_ID 0x7100 +#define NV4_PRMIO_RMA_ID_CODE 0 +#define NV4_PRMIO_RMA_ID_CODE_VALID 0x2B16D065 +#define NV4_PRMIO_RMA_PTR 0x7104 +#define NV4_PRMIO_RMA_PTR_ADDRESS 2 +#define NV4_PRMIO_RMA_DATA 0x7108 +#define NV4_PRMIO_RMA_DATA_PORT 0 +#define NV4_PRMIO_RMA_DATA32 0x710C +#define NV4_PRMIO_RMA_DATA32_BYTE2 16 +#define NV4_PRMIO_RMA_DATA32_BYTE1 8 +#define NV4_PRMIO_RMA_DATA32_BYTE0 0 + +#define NV4_PRAMDAC_START 0x680300 +#define NV4_PRAMDAC_END 0x680FFF + +#define NV4_PRAMDAC_CU_START_POS 0x680300 +#define NV4_PRAMDAC_CU_START_POS_X 0 +#define NV4_PRAMDAC_CU_START_POS_Y 16 +#define NV4_PRAMDAC_NVPLL_COEFF 0x680500 +#define NV4_PRAMDAC_NVPLL_COEFF_MDIV 0 +#define NV4_PRAMDAC_NVPLL_COEFF_NDIV 8 +#define NV4_PRAMDAC_NVPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_MPLL_COEFF 0x680504 +#define NV4_PRAMDAC_MPLL_COEFF_MDIV 0 +#define NV4_PRAMDAC_MPLL_COEFF_NDIV 8 +#define NV4_PRAMDAC_MPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_VPLL_COEFF 0x680508 +#define NV4_PRAMDAC_VPLL_COEFF_MDIV 0 +#define NV4_PRAMDAC_VPLL_COEFF_NDIV 8 +#define NV4_PRAMDAC_VPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_PLL_COEFF_SELECT 0x68050C +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_VIP 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE 8 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_DEFAULT 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL 0x2 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL 0x4 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_ALL 0x7 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV 16 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_NONE 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_PCLK 0x2 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_BOTH 0x3 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE 20 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE_EXT 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE_VIP 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO 24 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB1 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB2 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x1 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL 0x680510 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_VALUE 0 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_VAL 0x44E +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN 12 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_ON 0x0 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_MPLL 0x1 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_VPLL 0x2 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_NVPLL 0x4 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_OFF 0x7 +#define NV4_PRAMDAC_PLL_TEST_COUNTER 0x680514 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NOOFIPCLKS 0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VALUE 0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE 16 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE_DEASSERTED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE_ASSERTED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET 20 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET_DEASSERTED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET_ASSERTED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE 24 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_MCLK 0x2 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_VCLK 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_NVCLK 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIV_RST 28 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_DEASSERTED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_ASSERTED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK 29 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_NOTLOCKED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCKED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK 30 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_NOTLOCKED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCKED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK 31 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_NOTLOCKED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCKED 0x1 +#define NV4_PRAMDAC_PALETTE_TEST 0x680518 +#define NV4_PRAMDAC_PALETTE_TEST_BLUE_DATA 0 +#define NV4_PRAMDAC_PALETTE_TEST_GREEN_DATA 8 +#define NV4_PRAMDAC_PALETTE_TEST_RED_DATA 16 +#define NV4_PRAMDAC_PALETTE_TEST_MODE 24 +#define NV4_PRAMDAC_PALETTE_TEST_MODE_8BIT 0x0 +#define NV4_PRAMDAC_PALETTE_TEST_MODE_24BIT 0x1 +#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC 28 +#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC_READWRITE 0x0 +#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC_WRITEONLY 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL 0x680600 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT 0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_24 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_31 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX 4 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_OFF 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_POS 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_NEG 0x2 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON 0x3 +#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8 +#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSEL 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_NOTSEL 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_15 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_16 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_24 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_30 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16 +#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION 17 +#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_BPC 20 +#define NV4_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24 +#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28 +#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x1 +#define NV4_PRAMDAC_PALETTE_RECOVERY 0x680604 +#define NV4_PRAMDAC_PALETTE_RECOVERY_ACTIVE_ADDRESS 0 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER 8 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_RED 0x1 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_GREEN 0x2 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_BLUE 0x4 +#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE 12 +#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_WRITE 0x0 +#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_READ 0x3 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RED_DATA 16 +#define NV4_PRAMDAC_PALETTE_RECOVERY_GREEN_DATA 24 +#define NV4_PRAMDAC_TEST_CONTROL 0x680608 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET 0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET_DEASSERTED 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET_ASSERTED 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE 4 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL 8 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_BLUE 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_GREEN 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_RED 0x2 +#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN 12 +#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN_DEASSERTED 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC 16 +#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_ON 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_DACTM 20 +#define NV4_PRAMDAC_TEST_CONTROL_DACTM_NORMAL 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_DACTM_TEST 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH1 24 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH1_CLEAR 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH1_SET 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH31 25 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH31_CLEAR 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH31_SET 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_SENSEB 28 +#define NV4_PRAMDAC_TEST_CONTROL_SENSEB_SOMELO 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI 0x1 +#define NV4_PRAMDAC_CHECKSUM 0x68060C +#define NV4_PRAMDAC_CHECKSUM_VALUE 0 +#define NV4_PRAMDAC_TESTPOINT_DATA 0x680610 +#define NV4_PRAMDAC_TESTPOINT_DATA_RED 0 +#define NV4_PRAMDAC_TESTPOINT_DATA_GREEN 10 +#define NV4_PRAMDAC_TESTPOINT_DATA_BLUE 20 +#define NV4_PRAMDAC_TESTPOINT_DATA_BLACK 30 +#define NV4_PRAMDAC_TESTPOINT_DATA_NOTBLANK 31 +#define NV4_PRAMDAC_TV_SETUP 0x680700 +#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE 0 +#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE_SLAVE 0x0 +#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE_MASTER 0x1 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT 4 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_555 0x0 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_565 0x1 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_888 0x2 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_101010 0x3 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_YUV 0x4 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC 8 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_COMP 0x0 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_SCALER 0x1 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_VIP 0x2 +#define NV4_PRAMDAC_TV_SETUP_COMP_SRC 12 +#define NV4_PRAMDAC_TV_SETUP_COMP_SRC_SCALER 0x0 +#define NV4_PRAMDAC_TV_SETUP_COMP_SRC_NO_SCALER 0x1 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL 16 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_NONE 0x0 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_HSYNC 0x1 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_VSYNC 0x2 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_BOTH 0x3 +#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC 20 +#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC_LEAD 0x0 +#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC_TRAIL 0x1 +#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS 24 +#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS_7_0 0x0 +#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS_11_4 0x1 +#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD 28 +#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD_0 0x0 +#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD_1 0x1 +#define NV4_PRAMDAC_TV_VBLANK_START 0x680704 +#define NV4_PRAMDAC_TV_VBLANK_START_VAL 0 +#define NV4_PRAMDAC_TV_VBLANK_END 0x680708 +#define NV4_PRAMDAC_TV_VBLANK_END_VAL 0 +#define NV4_PRAMDAC_TV_HBLANK_START 0x68070C +#define NV4_PRAMDAC_TV_HBLANK_START_VAL 0 +#define NV4_PRAMDAC_TV_HBLANK_END 0x680710 +#define NV4_PRAMDAC_TV_HBLANK_END_VAL 0 +#define NV4_PRAMDAC_BLANK_COLOR 0x680714 +#define NV4_PRAMDAC_BLANK_COLOR_VAL 0 +#define NV4_PRAMDAC_TV_CHECKSUM 0x680718 +#define NV4_PRAMDAC_TV_CHECKSUM_VAL 0 +#define NV4_PRAMDAC_TV_VSYNC 28 +#define NV4_PRAMDAC_TV_VSYNC_ACTIVE 0x0 +#define NV4_PRAMDAC_TV_VSYNC_INACTIVE 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL 0x68071c +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET 0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_DEASSERTED 0x0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_ASSERTED 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE 4 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL 8 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_7_0 0x0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_15_8 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_23_16 0x2 + +#define NV4_USER_DAC_START 0x681200 +#define NV4_USER_DAC_END 0x681FFF + +#define NV4_USER_DAC_PIXEL_MASK 0x6813C6 +#define NV4_USER_DAC_PIXEL_MASK_VALUE 0 +#define NV4_USER_DAC_PIXEL_MASK_MASK 0xFF +#define NV4_USER_DAC_READ_MODE_ADDRESS 0x6813C7 +#define NV4_USER_DAC_READ_MODE_ADDRESS_VALUE 0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_WO_VALUE 0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE 0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE_WRITE 0x0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE_READ 0x3 +#define NV4_USER_DAC_WRITE_MODE_ADDRESS 0x6813C8 +#define NV4_USER_DAC_WRITE_MODE_ADDRESS_VALUE 0 +#define NV4_USER_DAC_PALETTE_DATA 0x6813C9 +#define NV4_USER_DAC_PALETTE_DATA_VALUE 0 + +#define NV4_PRMDIO_START 0x681000 +#define NV4_PRMDIO_END 0x681FFF + +#define NV4_IO_MPU_401_DATA 0x330 +#define NV4_IO_MPU_401_DATA_ALIAS_1 0x300 +#define NV4_IO_MPU_401_DATA_ALIAS_2 0x230 +#define NV4_IO_MPU_401_DATA_VALUE 0 +#define NV4_IO_MPU_401_DATA_ACK 0xFE +#define NV4_IO_MPU_401_STATUS 0x331 +#define NV4_IO_MPU_401_STATUS_ALIAS_1 0x301 +#define NV4_IO_MPU_401_STATUS_ALIAS_2 0x231 +#define NV4_IO_MPU_401_STATUS_DATA 0 +#define NV4_IO_MPU_401_STATUS_WRITE 6 +#define NV4_IO_MPU_401_STATUS_WRITE_EMPTY 0x0 +#define NV4_IO_MPU_401_STATUS_WRITE_FULL 0x1 +#define NV4_IO_MPU_401_STATUS_READ 7 +#define NV4_IO_MPU_401_STATUS_READ_FULL 0x0 +#define NV4_IO_MPU_401_STATUS_READ_EMPTY 0x1 +#define NV4_IO_MPU_401_COM 0x331 +#define NV4_IO_MPU_401_COM_ALIAS_1 0x301 +#define NV4_IO_MPU_401_COM_ALIAS_2 0x231 +#define NV4_IO_MPU_401_COM_UART_MODE 0 +#define NV4_IO_MPU_401_COM_UART_MODE_COMPLEX 0xff +#define NV4_IO_MPU_401_COM_UART_MODE_SIMPLE 0x3f + +#define NV4_PMC_START 0x0 +#define NV4_PMC_END 0xFFF + +#define NV4_PMC_BOOT_0 0x0 +#define NV4_PMC_BOOT_0_MINOR_REVISION 0 +#define NV4_PMC_BOOT_0_MINOR_REVISION_0 0x0 +#define NV4_PMC_BOOT_0_MAJOR_REVISION 4 +#define NV4_PMC_BOOT_0_MAJOR_REVISION_A 0x0 +#define NV4_PMC_BOOT_0_MAJOR_REVISION_B 0x1 +#define NV4_PMC_BOOT_0_IMPLEMENTATION 8 +#define NV4_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x0 +#define NV4_PMC_BOOT_0_ARCHITECTURE 12 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV0 0x0 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV1 0x1 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV2 0x2 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV3 0x3 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV4 0x4 +#define NV4_PMC_BOOT_0_FIB_REVISION 16 +#define NV4_PMC_BOOT_0_FIB_REVISION_0 0x0 +#define NV4_PMC_BOOT_0_MASK_REVISION 20 +#define NV4_PMC_BOOT_0_MASK_REVISION_A 0x0 +#define NV4_PMC_BOOT_0_MASK_REVISION_B 0x1 +#define NV4_PMC_BOOT_0_MASK_REVISION_C 0x2 +#define NV4_PMC_BOOT_0_MANUFACTURER 24 +#define NV4_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x0 +#define NV4_PMC_BOOT_0_FOUNDRY 28 +#define NV4_PMC_BOOT_0_FOUNDRY_SGS 0x0 +#define NV4_PMC_BOOT_0_FOUNDRY_HELIOS 0x1 +#define NV4_PMC_BOOT_0_FOUNDRY_TSMC 0x2 +#define NV4_PMC_INTR_0 0x100 +#define NV4_PMC_INTR_0_PMEDIA 4 +#define NV4_PMC_INTR_0_PMEDIA_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PMEDIA_PENDING 0x1 +#define NV4_PMC_INTR_0_PFIFO 8 +#define NV4_PMC_INTR_0_PFIFO_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PFIFO_PENDING 0x1 +#define NV4_PMC_INTR_0_PGRAPH 12 +#define NV4_PMC_INTR_0_PGRAPH_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PGRAPH_PENDING 0x1 +#define NV4_PMC_INTR_0_PVIDEO 16 +#define NV4_PMC_INTR_0_PVIDEO_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PVIDEO_PENDING 0x1 +#define NV4_PMC_INTR_0_PTIMER 20 +#define NV4_PMC_INTR_0_PTIMER_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PTIMER_PENDING 0x1 +#define NV4_PMC_INTR_0_PCRTC 24 +#define NV4_PMC_INTR_0_PCRTC_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PCRTC_PENDING 0x1 +#define NV4_PMC_INTR_0_PBUS 28 +#define NV4_PMC_INTR_0_PBUS_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PBUS_PENDING 0x1 +#define NV4_PMC_INTR_0_SOFTWARE 31 +#define NV4_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_SOFTWARE_PENDING 0x1 +#define NV4_PMC_INTR_EN_0 0x140 +#define NV4_PMC_INTR_EN_0_INTA 0 +#define NV4_PMC_INTR_EN_0_INTA_DISABLED 0x0 +#define NV4_PMC_INTR_EN_0_INTA_HARDWARE 0x1 +#define NV4_PMC_INTR_EN_0_INTA_SOFTWARE 0x2 +#define NV4_PMC_INTR_READ_0 0x160 +#define NV4_PMC_INTR_READ_0_INTA 0 +#define NV4_PMC_INTR_READ_0_INTA_LOW 0x0 +#define NV4_PMC_INTR_READ_0_INTA_HIGH 0x1 +#define NV4_PMC_ENABLE 0x200 +#define NV4_PMC_ENABLE_PMEDIA 4 +#define NV4_PMC_ENABLE_PMEDIA_ENABLED 0x1 +#define NV4_PMC_ENABLE_PFIFO 8 +#define NV4_PMC_ENABLE_PFIFO_ENABLED 0x1 +#define NV4_PMC_ENABLE_PGRAPH 12 +#define NV4_PMC_ENABLE_PGRAPH_ENABLED 0x1 +#define NV4_PMC_ENABLE_PPMI 16 +#define NV4_PMC_ENABLE_PPMI_ENABLED 0x1 +#define NV4_PMC_ENABLE_PFB 20 +#define NV4_PMC_ENABLE_PFB_ENABLED 0x1 +#define NV4_PMC_ENABLE_PCRTC 24 +#define NV4_PMC_ENABLE_PCRTC_ENABLED 0x1 +#define NV4_PMC_ENABLE_PVIDEO 28 +#define NV4_PMC_ENABLE_PVIDEO_ENABLED 0x1 + +#define NV4_PBUS_START 0x1000 +#define NV4_PBUS_END 0x1FFF + +#define NV4_PBUS_DEBUG_0 0x1080 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_DELAY 0 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC 4 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_DELAY 8 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC 12 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_DELAY 16 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC 20 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_DELAY 24 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC 28 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_1 0x1084 +#define NV4_PBUS_DEBUG_1_PCIM_THROTTLE 0 +#define NV4_PBUS_DEBUG_1_PCIM_THROTTLE_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIM_CMD 1 +#define NV4_PBUS_DEBUG_1_PCIM_CMD_SIZE_BASED 0x0 +#define NV4_PBUS_DEBUG_1_PCIM_CMD_MRL_ONLY 0x1 +#define NV4_PBUS_DEBUG_1_HASH_DECODE 2 +#define NV4_PBUS_DEBUG_1_HASH_DECODE_1FF 0x0 +#define NV4_PBUS_DEBUG_1_HASH_DECODE_2FF 0x1 +#define NV4_PBUS_DEBUG_1_AGPM_CMD 3 +#define NV4_PBUS_DEBUG_1_AGPM_CMD_HP_ON_1ST 0x0 +#define NV4_PBUS_DEBUG_1_AGPM_CMD_LP_ONLY 0x1 +#define NV4_PBUS_DEBUG_1_AGPM_CMD_HP_ONLY 0x2 +#define NV4_PBUS_DEBUG_1_PCIS_WRITE 5 +#define NV4_PBUS_DEBUG_1_PCIS_WRITE_0_CYCLE 0x0 +#define NV4_PBUS_DEBUG_1_PCIS_WRITE_1_CYCLE 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_2_1 6 +#define NV4_PBUS_DEBUG_1_PCIS_2_1_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_RETRY 7 +#define NV4_PBUS_DEBUG_1_PCIS_RETRY_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_RD_BURST 8 +#define NV4_PBUS_DEBUG_1_PCIS_RD_BURST_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_WR_BURST 9 +#define NV4_PBUS_DEBUG_1_PCIS_WR_BURST_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_EARLY_RTY 10 +#define NV4_PBUS_DEBUG_1_PCIS_EARLY_RTY_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_CPUQ 12 +#define NV4_PBUS_DEBUG_1_PCIS_CPUQ_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_DPSH_DECODE 13 +#define NV4_PBUS_DEBUG_1_DPSH_DECODE_NV4 0x0 +#define NV4_PBUS_DEBUG_1_DPSH_DECODE_NV3 0x1 +#define NV4_PBUS_DEBUG_1_SPARE1 14 +#define NV4_PBUS_DEBUG_1_SPARE2 15 +#define NV4_PBUS_DEBUG_1_SPARE3 16 +#define NV4_PBUS_DEBUG_1_SPARE4 17 +#define NV4_PBUS_DEBUG_1_SPARE5 18 +#define NV4_PBUS_DEBUG_1_SPARE6 19 +#define NV4_PBUS_DEBUG_1_SPARE7 20 +#define NV4_PBUS_DEBUG_1_SPARE8 21 +#define NV4_PBUS_DEBUG_1_SPARE9 22 +#define NV4_PBUS_DEBUG_1_SPARE10 23 +#define NV4_PBUS_DEBUG_2 0x1088 +#define NV4_PBUS_DEBUG_2_AGP_DIFFERENTIAL 0 +#define NV4_PBUS_DEBUG_2_AGP_DIFFERENTIAL_ENABLED 0x1 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_DELAY 9:4 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_DELAY_34 0x22 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC 12 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_3 0x108C +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE 0 +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_UNLIMITED 0x0 +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_32_BYTES 0x1 +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_64_BYTES 0x2 +#define NV4_PBUS_DEBUG_CTL 0x1090 +#define NV4_PBUS_DEBUG_CTL_MODE 0 +#define NV4_PBUS_DEBUG_CTL_MODE_ENABLED 0x1 +#define NV4_PBUS_DEBUG_CTL_READ_SELECT 4 +#define NV4_PBUS_DEBUG_CTL_READ_SELECT_0 0x0 +#define NV4_PBUS_DEBUG_CTL_READ_SELECT_1 0x1 +#define NV4_PBUS_DEBUG_READ 0x1094 +#define NV4_PBUS_DEBUG_READ_DATA 0 +#define NV4_PBUS_DEBUG_HOST 0x109C +#define NV4_PBUS_DEBUG_HOST_SEL 0 +#define NV4_PBUS_DEBUG_SEL_0 0x10A0 +#define NV4_PBUS_DEBUG_SEL_0_X 0 +#define NV4_PBUS_DEBUG_SEL_1 0x10A4 +#define NV4_PBUS_DEBUG_SEL_1_X 0 +#define NV4_PBUS_DEBUG_SEL_2 0x10A8 +#define NV4_PBUS_DEBUG_SEL_2_X 0 +#define NV4_PBUS_DEBUG_SEL_3 0x10AC +#define NV4_PBUS_DEBUG_SEL_3_X 0 +#define NV4_PBUS_INTR_0 0x1100 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR 0 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_NOT_PENDING 0x0 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_PENDING 0x1 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_RESET 0x1 +#define NV4_PBUS_INTR_EN_0 0x1140 +#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR 0 +#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR_ENABLED 0x1 +#define NV4_PBUS_ROM_CONFIG 0x1200 +#define NV4_PBUS_ROM_CONFIG_TW1 0 +#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF +#define NV4_PBUS_ROM_CONFIG_TW0 4 +#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3 +#define NV4_PBUS_PCI_NV_0 0x1800 +#define NV4_PBUS_PCI_NV_0_VENDOR_ID 0 +#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA_SGS 0x12D2 +#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA 0x10DE +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC 16 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC_VGA 0x0 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP 3 19 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV0 0x0 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV1 0x1 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV2 0x2 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV3 0x3 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV4 0x4 +#define NV4_PBUS_PCI_NV_1 0x1804 +#define NV4_PBUS_PCI_NV_1_IO_SPACE 0 +#define NV4_PBUS_PCI_NV_1_IO_SPACE_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE 1 +#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_BUS_MASTER 2 +#define NV4_PBUS_PCI_NV_1_BUS_MASTER_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL 4 +#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP 5 +#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_CAPLIST 20 +#define NV4_PBUS_PCI_NV_1_CAPLIST_NOT_PRESENT 0x0 +#define NV4_PBUS_PCI_NV_1_CAPLIST_PRESENT 0x1 +#define NV4_PBUS_PCI_NV_1_66MHZ 21 +#define NV4_PBUS_PCI_NV_1_66MHZ_INCAPABLE 0x0 +#define NV4_PBUS_PCI_NV_1_66MHZ_CAPABLE 0x1 +#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK 23 +#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_INCAPABLE 0x0 +#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_CAPABLE 0x1 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING 25 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_FAST 0x0 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_MEDIUM 0x1 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_SLOW 0x2 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET 27 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_NO_ABORT 0x0 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_ABORT 0x1 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_CLEAR 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET 28 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_NO_ABORT 0x0 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_ABORT 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_CLEAR 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER 29 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_NO_ABORT 0x0 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_ABORT 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_CLEAR 0x1 +#define NV4_PBUS_PCI_NV_2 0x1808 +#define NV4_PBUS_PCI_NV_2_REVISION_ID 0 +#define NV4_PBUS_PCI_NV_2_REVISION_ID_A01 0x0 +#define NV4_PBUS_PCI_NV_2_REVISION_ID_B01 0x10 +#define NV4_PBUS_PCI_NV_2_CLASS_CODE 8 +#define NV4_PBUS_PCI_NV_2_CLASS_CODE_VGA 0x30000 +#define NV4_PBUS_PCI_NV_2_CLASS_CODE_MULTIMEDIA 0x48000 +#define NV4_PBUS_PCI_NV_3 0x180C +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER 11 +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x0 +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x1 +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x1E +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x1F +#define NV4_PBUS_PCI_NV_3_HEADER_TYPE 16 +#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_SINGLEFUNC 0x0 +#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_MULTIFUNC 0x80 +#define NV4_PBUS_PCI_NV_4 0x1810 +#define NV4_PBUS_PCI_NV_4_SPACE_TYPE 0 +#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_MEMORY 0x0 +#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_IO 0x1 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE 1 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_32_BIT 0x0 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_20_BIT 0x1 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_64_BIT 0x2 +#define NV4_PBUS_PCI_NV_4_PREFETCHABLE 3 +#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_NOT 0x0 +#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_MERGABLE 0x1 +#define NV4_PBUS_PCI_NV_4_BASE_ADDRESS 24 +#define NV4_PBUS_PCI_NV_5 0x1814 +#define NV4_PBUS_PCI_NV_5_SPACE_TYPE 0 +#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_MEMORY 0x0 +#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_IO 0x1 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE 2:1 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_32_BIT 0x0 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_20_BIT 0x1 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x2 +#define NV4_PBUS_PCI_NV_5_PREFETCHABLE 3 +#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_NOT 0x0 +#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_MERGABLE 0x1 +#define NV4_PBUS_PCI_NV_5_BASE_ADDRESS 24 +#define NV4_PBUS_PCI_NV_6(i) (0x1818+(i)*4) +#define NV4_PBUS_PCI_NV_6_SIZE_1 5 +#define NV4_PBUS_PCI_NV_6_RESERVED 0 +#define NV4_PBUS_PCI_NV_6_RESERVED_0 0x0 +#define NV4_PBUS_PCI_NV_11 0x182C +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID 0 +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID 16 +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_12 0x1830 +#define NV4_PBUS_PCI_NV_12_ROM_DECODE 0 +#define NV4_PBUS_PCI_NV_12_ROM_DECODE_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_12_ROM_BASE 16 +#define NV4_PBUS_PCI_NV_13 0x1834 +#define NV4_PBUS_PCI_NV_13_CAP_PTR 0 +#define NV4_PBUS_PCI_NV_13_CAP_PTR_AGP 0x44 +#define NV4_PBUS_PCI_NV_13_CAP_PTR_POWER_MGMT 0x60 +#define NV4_PBUS_PCI_NV_14 0x1838 +#define NV4_PBUS_PCI_NV_14_RESERVED 0 +#define NV4_PBUS_PCI_NV_14_RESERVED_0 0x0 +#define NV4_PBUS_PCI_NV_15 0x183C +#define NV4_PBUS_PCI_NV_15_INTR_LINE 0 +#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ0 0x0 +#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ1 0x1 +#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ15 0xF +#define NV4_PBUS_PCI_NV_15_INTR_LINE_UNKNOWN 0xFF +#define NV4_PBUS_PCI_NV_15_INTR_PIN 8 +#define NV4_PBUS_PCI_NV_15_INTR_PIN_INTA 0x1 +#define NV4_PBUS_PCI_NV_15_MIN_GNT 16 +#define NV4_PBUS_PCI_NV_15_MIN_GNT_NO_REQUIREMENTS 0x0 +#define NV4_PBUS_PCI_NV_15_MIN_GNT_750NS 0x3 +#define NV4_PBUS_PCI_NV_15_MIN_GNT_1250NS 0x5 +#define NV4_PBUS_PCI_NV_15_MAX_LAT 24 +#define NV4_PBUS_PCI_NV_15_MAX_LAT_NO_REQUIREMENTS 0x0 +#define NV4_PBUS_PCI_NV_15_MAX_LAT_250NS 0x1 +#define NV4_PBUS_PCI_NV_16 0x1840 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID 0 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID 16 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_17 0x1844 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR 20 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR_1 0x1 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR 16 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR_0 0x0 +#define NV4_PBUS_PCI_NV_17_NEXT_PTR 8 +#define NV4_PBUS_PCI_NV_17_NEXT_PTR_NULL 0x0 +#define NV4_PBUS_PCI_NV_17_CAP_ID 0 +#define NV4_PBUS_PCI_NV_17_CAP_ID_AGP 0x2 +#define NV4_PBUS_PCI_NV_18 0x1848 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ 24 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ_16 0xF +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA 9 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_NONE 0x0 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_CAPABLE 0x1 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE 0 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X 0x1 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_2X 0x2 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X_AND_2X 0x3 +#define NV4_PBUS_PCI_NV_19 0x184C +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH 24 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH_0 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE 9 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_OFF 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_ON 0x1 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE 8 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_OFF 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_ON 0x1 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE 0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_OFF 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_1X 0x1 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_2X 0x2 +#define NV4_PBUS_PCI_NV_20 0x1850 +#define NV4_PBUS_PCI_NV_20_ROM_SHADOW 0 +#define NV4_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_21 0x1854 +#define NV4_PBUS_PCI_NV_21_VGA 0 +#define NV4_PBUS_PCI_NV_21_VGA_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_22 0x1858 +#define NV4_PBUS_PCI_NV_22_SCRATCH 0 +#define NV4_PBUS_PCI_NV_22_SCRATCH_DEFAULT 0x23D6CE +#define NV4_PBUS_PCI_NV_23 0x185C +#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT 0 +#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT_16 0xF +#define NV4_PBUS_PCI_NV_24 0x1860 +#define NV4_PBUS_PCI_NV_24_PME_D3_COLD 31 +#define NV4_PBUS_PCI_NV_24_PME_D3_COLD_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D3_HOT 30 +#define NV4_PBUS_PCI_NV_24_PME_D3_HOT_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D2 29 +#define NV4_PBUS_PCI_NV_24_PME_D2_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D1 28 +#define NV4_PBUS_PCI_NV_24_PME_D1_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D0 27 +#define NV4_PBUS_PCI_NV_24_PME_D0_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_D2 26 +#define NV4_PBUS_PCI_NV_24_D2_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_D2_NOT_SUPPORTED 0x0 +#define NV4_PBUS_PCI_NV_24_D1 25 +#define NV4_PBUS_PCI_NV_24_D1_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_D1_NOT_SUPPORTED 0x0 +#define NV4_PBUS_PCI_NV_24_DSI 21 +#define NV4_PBUS_PCI_NV_24_DSI_NOT_REQUIRED 0x0 +#define NV4_PBUS_PCI_NV_24_PME_CLOCK 19 +#define NV4_PBUS_PCI_NV_24_PME_CLOCK_NOT_REQUIRED 0x0 +#define NV4_PBUS_PCI_NV_24_VERSION 16 +#define NV4_PBUS_PCI_NV_24_VERSION_1 0x1 +#define NV4_PBUS_PCI_NV_24_NEXT_PTR 8 +#define NV4_PBUS_PCI_NV_24_NEXT_PTR_NULL 0x0 +#define NV4_PBUS_PCI_NV_24_NEXT_PTR_AGP 0x44 +#define NV4_PBUS_PCI_NV_24_CAP_ID 0 +#define NV4_PBUS_PCI_NV_24_CAP_ID_POWER_MGMT 0x1 +#define NV4_PBUS_PCI_NV_25 0x1864 +#define NV4_PBUS_PCI_NV_25_POWER_STATE 0 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D3_HOT 0x3 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D2 0x2 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D1 0x1 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D0 0x0 +#define NV4_PBUS_PCI_NV_26(i) (0x1868+(i)*4) +#define NV4_PBUS_PCI_NV_26_SIZE_1 38 +#define NV4_PBUS_PCI_NV_26_RESERVED 0 +#define NV4_PBUS_PCI_NV_26_RESERVED_0 0x0 + +#define NV4_PFIFO_START 0x2000 +#define NV4_PFIFO_END 0x3FFF + +#define NV4_PFIFO_DELAY_0 0x2040 +#define NV4_PFIFO_DELAY_0_WAIT_RETRY 0 +#define NV4_PFIFO_DELAY_0_WAIT_RETRY_0 0x0 +#define NV4_PFIFO_DMA_TIMESLICE 0x2044 +#define NV4_PFIFO_DMA_TIMESLICE_SELECT 0 +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_1 0x0 +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_16K 0x3fff +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_32K 0x7fff +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_64K 0xffff +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_128K 0x1ffff +#define NV4_PFIFO_DMA_TIMESLICE_TIMEOUT 24 +#define NV4_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x1 +#define NV4_PFIFO_PIO_TIMESLICE 0x2048 +#define NV4_PFIFO_PIO_TIMESLICE_SELECT 0 +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_1 0x0 +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_16K 0x3fff +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_32K 0x7fff +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_64K 0xffff +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_128K 0x1ffff +#define NV4_PFIFO_PIO_TIMESLICE_TIMEOUT 24 +#define NV4_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x1 +#define NV4_PFIFO_TIMESLICE 0x204C +#define NV4_PFIFO_TIMESLICE_TIMER 0 +#define NV4_PFIFO_TIMESLICE_TIMER_EXPIRED 0x3FFFF +#define NV4_PFIFO_NEXT_CHANNEL 0x2050 +#define NV4_PFIFO_NEXT_CHANNEL_CHID 0 +#define NV4_PFIFO_NEXT_CHANNEL_MODE 8 +#define NV4_PFIFO_NEXT_CHANNEL_MODE_PIO 0x0 +#define NV4_PFIFO_NEXT_CHANNEL_MODE_DMA 0x1 +#define NV4_PFIFO_NEXT_CHANNEL_SWITCH 12 +#define NV4_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x0 +#define NV4_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x1 +#define NV4_PFIFO_DEBUG_0 0x2080 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0 0 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x0 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x1 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1 4 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x0 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x1 +#define NV4_PFIFO_INTR_0 0x2100 +#define NV4_PFIFO_INTR_0_CACHE_ERROR 0 +#define NV4_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x1 +#define NV4_PFIFO_INTR_0_CACHE_ERROR_RESET 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT 4 +#define NV4_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_RUNOUT_PENDING 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT_RESET 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW 8 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x1 +#define NV4_PFIFO_INTR_0_DMA_PUSHER 12 +#define NV4_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x1 +#define NV4_PFIFO_INTR_0_DMA_PUSHER_RESET 0x1 +#define NV4_PFIFO_INTR_0_DMA_PT 16 +#define NV4_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_DMA_PT_PENDING 0x1 +#define NV4_PFIFO_INTR_0_DMA_PT_RESET 0x1 +#define NV4_PFIFO_INTR_EN_0 0x2140 +#define NV4_PFIFO_INTR_EN_0_CACHE_ERROR 0 +#define NV4_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_RUNOUT 4 +#define NV4_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8 +#define NV4_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_DMA_PUSHER 12 +#define NV4_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_DMA_PT 16 +#define NV4_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x1 +#define NV4_PFIFO_RAMHT 0x2210 +#define NV4_PFIFO_RAMHT_BASE_ADDRESS 4 +#define NV4_PFIFO_RAMHT_BASE_ADDRESS_10000 0x10 +#define NV4_PFIFO_RAMHT_SIZE 16 +#define NV4_PFIFO_RAMHT_SIZE_4K 0x0 +#define NV4_PFIFO_RAMHT_SIZE_8K 0x1 +#define NV4_PFIFO_RAMHT_SIZE_16K 0x2 +#define NV4_PFIFO_RAMHT_SIZE_32K 0x3 +#define NV4_PFIFO_RAMHT_SEARCH 24 +#define NV4_PFIFO_RAMHT_SEARCH_16 0x0 +#define NV4_PFIFO_RAMHT_SEARCH_32 0x1 +#define NV4_PFIFO_RAMHT_SEARCH_64 0x2 +#define NV4_PFIFO_RAMHT_SEARCH_128 0x3 +#define NV4_PFIFO_RAMFC 0x2214 +#define NV4_PFIFO_RAMFC_BASE_ADDRESS 1 +#define NV4_PFIFO_RAMFC_BASE_ADDRESS_11000 0x88 +#define NV4_PFIFO_RAMRO 0x2218 +#define NV4_PFIFO_RAMRO_BASE_ADDRESS 1 +#define NV4_PFIFO_RAMRO_BASE_ADDRESS_11200 0x89 +#define NV4_PFIFO_RAMRO_BASE_ADDRESS_12000 0x90 +#define NV4_PFIFO_RAMRO_SIZE 16 +#define NV4_PFIFO_RAMRO_SIZE_512 0x0 +#define NV4_PFIFO_RAMRO_SIZE_8K 0x1 +#define NV4_PFIFO_CACHES 0x2500 +#define NV4_PFIFO_CACHES_REASSIGN 0 +#define NV4_PFIFO_CACHES_REASSIGN_ENABLED 0x1 +#define NV4_PFIFO_CACHES_DMA_SUSPEND 4 +#define NV4_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x0 +#define NV4_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x1 +#define NV4_PFIFO_MODE 0x2504 +// Valid for all 16 channels. Do we need thees at all? +#define NV4_PFIFO_MODE_CHANNEL_IS_PIO 0x0 +#define NV4_PFIFO_MODE_CHANNEL_IS_DMA 0x1 +#define NV4_PFIFO_MODE_CHANNEL_0 0 +#define NV4_PFIFO_MODE_CHANNEL_1 1 +#define NV4_PFIFO_MODE_CHANNEL_2 2 +#define NV4_PFIFO_MODE_CHANNEL_3 3 +#define NV4_PFIFO_MODE_CHANNEL_4 4 +#define NV4_PFIFO_MODE_CHANNEL_5 5 +#define NV4_PFIFO_MODE_CHANNEL_6 6 +#define NV4_PFIFO_MODE_CHANNEL_7 7 +#define NV4_PFIFO_MODE_CHANNEL_8 8 +#define NV4_PFIFO_MODE_CHANNEL_9 9 +#define NV4_PFIFO_MODE_CHANNEL_10 10 +#define NV4_PFIFO_MODE_CHANNEL_11 11 +#define NV4_PFIFO_MODE_CHANNEL_12 12 +#define NV4_PFIFO_MODE_CHANNEL_13 13 +#define NV4_PFIFO_MODE_CHANNEL_14 14 +#define NV4_PFIFO_MODE_CHANNEL_15 15 +#define NV4_PFIFO_DMA 0x2508 +// 0 = not pending (Valid for all channels) +#define NV4_PFIFO_DMA_CHANNEL_IS_PENDING 0x1 +#define NV4_PFIFO_DMA_CHANNEL_0 0 +#define NV4_PFIFO_DMA_CHANNEL_1 1 +#define NV4_PFIFO_DMA_CHANNEL_2 2 +#define NV4_PFIFO_DMA_CHANNEL_3 3 +#define NV4_PFIFO_DMA_CHANNEL_4 4 +#define NV4_PFIFO_DMA_CHANNEL_5 5 +#define NV4_PFIFO_DMA_CHANNEL_6 6 +#define NV4_PFIFO_DMA_CHANNEL_7 7 +#define NV4_PFIFO_DMA_CHANNEL_8 8 +#define NV4_PFIFO_DMA_CHANNEL_9 9 +#define NV4_PFIFO_DMA_CHANNEL_10 10 +#define NV4_PFIFO_DMA_CHANNEL_11 11 +#define NV4_PFIFO_DMA_CHANNEL_12 12 +#define NV4_PFIFO_DMA_CHANNEL_13 13 +#define NV4_PFIFO_DMA_CHANNEL_14 14 +#define NV4_PFIFO_DMA_CHANNEL_15 15 +#define NV4_PFIFO_SIZE 0x250C +// Valid for all channels +#define NV4_PFIFO_SIZE_CHANNEL_SIZE_IS_124_BYTES 0x0 +#define NV4_PFIFO_SIZE_CHANNEL_SIZE_IS_512_BYTES 0x1 +#define NV4_PFIFO_SIZE_CHANNEL_0 0 +#define NV4_PFIFO_SIZE_CHANNEL_1 1 +#define NV4_PFIFO_SIZE_CHANNEL_2 2 +#define NV4_PFIFO_SIZE_CHANNEL_3 3 +#define NV4_PFIFO_SIZE_CHANNEL_4 4 +#define NV4_PFIFO_SIZE_CHANNEL_5 5 +#define NV4_PFIFO_SIZE_CHANNEL_6 6 +#define NV4_PFIFO_SIZE_CHANNEL_7 7 +#define NV4_PFIFO_SIZE_CHANNEL_8 8 +#define NV4_PFIFO_SIZE_CHANNEL_9 9 +#define NV4_PFIFO_SIZE_CHANNEL_10 10 +#define NV4_PFIFO_SIZE_CHANNEL_11 11 +#define NV4_PFIFO_SIZE_CHANNEL_12 12 +#define NV4_PFIFO_SIZE_CHANNEL_13 13 +#define NV4_PFIFO_SIZE_CHANNEL_14 14 +#define NV4_PFIFO_SIZE_CHANNEL_15 15 +#define NV4_PFIFO_CACHE0_PUSH0 0x3000 +#define NV4_PFIFO_CACHE0_PUSH0_ACCESS 0 +#define NV4_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE1_PUSH0 0x3200 +#define NV4_PFIFO_CACHE1_PUSH0_ACCESS 0 +#define NV4_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE0_PUSH1 0x3004 +#define NV4_PFIFO_CACHE0_PUSH1_CHID 0 +#define NV4_PFIFO_CACHE1_PUSH1 0x3204 +#define NV4_PFIFO_CACHE1_PUSH1_CHID 0 +#define NV4_PFIFO_CACHE1_PUSH1_MODE 8 +#define NV4_PFIFO_CACHE1_PUSH1_MODE_PIO 0x0 +#define NV4_PFIFO_CACHE1_PUSH1_MODE_DMA 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH 0x3220 +#define NV4_PFIFO_CACHE1_DMA_PUSH_ACCESS 0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE 4 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER 8 +#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS 12 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x1 +#define NV4_PFIFO_CACHE1_DMA_FETCH 0x3224 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x0 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x1 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x2 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x3 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x4 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x5 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x6 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x7 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x8 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x9 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0xA +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0xB +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0xC +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0xD +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0xE +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0xF +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x10 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x11 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x12 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x13 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x14 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x15 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x16 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x17 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x18 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x19 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x1A +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x1B +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x1C +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x1D +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x1E +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x1F +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE 13 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x0 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x1 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x2 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x3 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x4 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x5 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x6 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x7 +// This is a count. 0x0-0xF = number of requests +#define NV4_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 16 +#define NV4_PFIFO_CACHE1_DMA_PUT 0x3240 +#define NV4_PFIFO_CACHE1_DMA_PUT_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_GET 0x3244 +#define NV4_PFIFO_CACHE1_DMA_GET_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_DCOUNT 0x32A0 +#define NV4_PFIFO_CACHE1_DMA_DCOUNT_VALUE 2 +#define NV4_PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x32A4 +#define NV4_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_RSVD_SHADOW 0x32A8 +#define NV4_PFIFO_CACHE1_DMA_RSVD_SHADOW_CMD 0 +#define NV4_PFIFO_CACHE1_DMA_DATA_SHADOW 0x32AC +#define NV4_PFIFO_CACHE1_DMA_DATA_SHADOW_VALUE 0 +#define NV4_PFIFO_CACHE1_DMA_STATE 0x3228 +#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD 2 +#define NV4_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 13 +#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 18 +#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x0 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR 30 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x0 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x1 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x2 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x3 +#define NV4_PFIFO_CACHE1_DMA_INSTANCE 0x322C +#define NV4_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0 +#define NV4_PFIFO_CACHE1_DMA_CTL 0x3230 +#define NV4_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x1 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x1 +#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 16 +#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x2 +#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x3 +#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO 31 +#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x0 +#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x1 +#define NV4_PFIFO_CACHE1_DMA_LIMIT 0x3234 +#define NV4_PFIFO_CACHE1_DMA_LIMIT_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG 0x3238 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x0 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x1 +#define NV4_PFIFO_CACHE1_DMA_TLB_PTE 0x323C +#define NV4_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 12 +#define NV4_PFIFO_CACHE0_PULL0 0x3050 +#define NV4_PFIFO_CACHE0_PULL0_ACCESS 0 +#define NV4_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE0_PULL0_HASH 4 +#define NV4_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x0 +#define NV4_PFIFO_CACHE0_PULL0_HASH_FAILED 0x1 +#define NV4_PFIFO_CACHE0_PULL0_DEVICE 8 +#define NV4_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x0 +#define NV4_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x1 +#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE 12 +#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x0 +#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x1 +#define NV4_PFIFO_CACHE1_PULL0 0x3250 +#define NV4_PFIFO_CACHE1_PULL0_ACCESS 0 +#define NV4_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE1_PULL0_HASH 4 +#define NV4_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x0 +#define NV4_PFIFO_CACHE1_PULL0_HASH_FAILED 0x1 +#define NV4_PFIFO_CACHE1_PULL0_DEVICE 8 +#define NV4_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x0 +#define NV4_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x1 +#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE 12 +#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x0 +#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x1 +#define NV4_PFIFO_CACHE0_PULL1 0x3054 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE 0 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE_SW 0x0 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x1 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x2 +#define NV4_PFIFO_CACHE1_PULL1 0x3254 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE 0 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE_SW 0x0 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x1 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x2 +#define NV4_PFIFO_CACHE0_HASH 0x3058 +#define NV4_PFIFO_CACHE0_HASH_INSTANCE 0 +#define NV4_PFIFO_CACHE0_HASH_VALID 16 +#define NV4_PFIFO_CACHE1_HASH 0x3258 +#define NV4_PFIFO_CACHE1_HASH_INSTANCE 0 +#define NV4_PFIFO_CACHE1_HASH_VALID 16 +#define NV4_PFIFO_CACHE0_STATUS 0x3014 +#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK 4 +#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x0 +#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x1 +#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK 8 +#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x0 +#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x1 +#define NV4_PFIFO_CACHE1_STATUS 0x3214 +#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK 4 +#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x0 +#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x1 +#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK 8 +#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x0 +#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x1 +#define NV4_PFIFO_CACHE1_STATUS1 0x3218 +#define NV4_PFIFO_CACHE1_STATUS1_RANOUT 0 +#define NV4_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x1 +#define NV4_PFIFO_CACHE0_PUT 0x3010 +#define NV4_PFIFO_CACHE0_PUT_ADDRESS 2 +#define NV4_PFIFO_CACHE1_PUT 0x3210 +#define NV4_PFIFO_CACHE1_PUT_ADDRESS 2 +#define NV4_PFIFO_CACHE0_GET 0x3070 +#define NV4_PFIFO_CACHE0_GET_ADDRESS 2 +#define NV4_PFIFO_CACHE1_GET 0x3270 +#define NV4_PFIFO_CACHE1_GET_ADDRESS 2 +#define NV4_PFIFO_ENGINE_SW 0x0 +#define NV4_PFIFO_ENGINE_GRAPHICS 0x1 +#define NV4_PFIFO_ENGINE_DVD 0x2 +#define NV4_PFIFO_CACHE0_ENGINE 0x3080 +// For these, see above +#define NV4_PFIFO_CACHE0_SUBCHANNEL_0_ENGINE 0 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_1_ENGINE 4 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_2_ENGINE 8 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_3_ENGINE 12 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_4_ENGINE 16 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_5_ENGINE 20 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_6_ENGINE 24 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_7_ENGINE 28 +#define NV4_PFIFO_CACHE1_ENGINE 0x3280 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_0_ENGINE 0 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_1_ENGINE 4 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_2_ENGINE 8 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_3_ENGINE 12 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_4_ENGINE 16 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_5_ENGINE 20 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_6_ENGINE 24 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_7_ENGINE 28 +#define NV4_PFIFO_CACHE0_METHOD(i) (0x3100+(i)*8) +#define NV4_PFIFO_CACHE0_METHOD_SIZE_1 1 +#define NV4_PFIFO_CACHE0_METHOD_ADDRESS 2 +#define NV4_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 +#define NV4_PFIFO_CACHE1_METHOD(i) (0x3800+(i)*8) +#define NV4_PFIFO_CACHE1_METHOD_SIZE_1 128 +#define NV4_PFIFO_CACHE1_METHOD_ADDRESS 2 +#define NV4_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 +#define NV4_PFIFO_CACHE1_METHOD_ALIAS(i) (0x3C00+(i)*8) +#define NV4_PFIFO_CACHE1_METHOD_ALIAS_SIZE_1 128 +#define NV4_PFIFO_CACHE0_DATA(i) (0x3104+(i)*8) +#define NV4_PFIFO_CACHE0_DATA_SIZE_1 1 +#define NV4_PFIFO_CACHE0_DATA_VALUE 0 +#define NV4_PFIFO_CACHE1_DATA(i) (0x3804+(i)*8) +#define NV4_PFIFO_CACHE1_DATA_SIZE_1 128 +#define NV4_PFIFO_CACHE1_DATA_VALUE 0 +#define NV4_PFIFO_CACHE1_DATA_ALIAS(i) (0x3C04+(i)*8) +#define NV4_PFIFO_CACHE1_DATA_ALIAS_SIZE_1 128 +#define NV4_PFIFO_DEVICE(i) (0x2800+(i)*4) +#define NV4_PFIFO_DEVICE_SIZE_1 128 +#define NV4_PFIFO_DEVICE_CHID 0 +#define NV4_PFIFO_DEVICE_SWITCH 24 +#define NV4_PFIFO_DEVICE_SWITCH_AVAILABLE 0x1 +#define NV4_PFIFO_RUNOUT_STATUS 0x2400 +#define NV4_PFIFO_RUNOUT_STATUS_RANOUT 0 +#define NV4_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x1 +#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK 4 +#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x0 +#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x1 +#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK 8 +#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x0 +#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x1 +#define NV4_PFIFO_RUNOUT_PUT 0x2410 +#define NV4_PFIFO_RUNOUT_PUT_ADDRESS 3 // if size=0, 8:3, otherwise 12:3 +#define NV4_PFIFO_RUNOUT_GET 0x2420 +#define NV4_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 + +#define NV4_PGRAPH_START 0x400000 +#define NV4_PGRAPH_END 0x401FFF + +#define NV4_PGRAPH_DEBUG_0 0x400080 +#define NV4_PGRAPH_DEBUG_0_STATE 0 +#define NV4_PGRAPH_DEBUG_0_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_FE_STATE 1 +#define NV4_PGRAPH_DEBUG_0_FE_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_FE_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_CACHE_STATE 2 +#define NV4_PGRAPH_DEBUG_0_CACHE_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_CACHE_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE 3 +#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_PREROP_STATE 4 +#define NV4_PGRAPH_DEBUG_0_PREROP_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_PREROP_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_ROP_STATE 5 +#define NV4_PGRAPH_DEBUG_0_ROP_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_ROP_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_RSTR_STATE 6 +#define NV4_PGRAPH_DEBUG_0_RSTR_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_RSTR_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE 7 +#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_DMA_STATE 8 +#define NV4_PGRAPH_DEBUG_0_DMA_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_DMA_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_SPARE1 12 +#define NV4_PGRAPH_DEBUG_0_SPARE2 13 +#define NV4_PGRAPH_DEBUG_0_MINUSD5 14 +#define NV4_PGRAPH_DEBUG_0_MINUSD5_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_BLIT_DST_LIMIT 15 +#define NV4_PGRAPH_DEBUG_0_BLIT_DST_LIMIT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_LIMIT_CHECK 16 +#define NV4_PGRAPH_DEBUG_0_LIMIT_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_LIMIT_INT 17 +#define NV4_PGRAPH_DEBUG_0_LIMIT_INT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_OVRFLW_INT 18 +#define NV4_PGRAPH_DEBUG_0_OVRFLW_INT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D 21 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_AUTO 24 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_AUTO_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y 25 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y_DECR 0x0 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y_INCR 0x1 +#define NV4_PGRAPH_DEBUG_0_ALPHA_ABORT 28 +#define NV4_PGRAPH_DEBUG_0_ALPHA_ABORT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1 0x400084 +#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET 0 +#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x0 +#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x1 +#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY 4 +#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY_IGNORE 0x0 +#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 0x1 +#define NV4_PGRAPH_DEBUG_1_PATCH_INV 8 +#define NV4_PGRAPH_DEBUG_1_PATCH_INV_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_ALT_RW_SEQ 10 +#define NV4_PGRAPH_DEBUG_1_ALT_RW_SEQ_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_TRI_OPTS 12 +#define NV4_PGRAPH_DEBUG_1_TRI_OPTS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_TRICLIP_OPTS 13 +#define NV4_PGRAPH_DEBUG_1_TRICLIP_OPTS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_INSTANCE 16 +#define NV4_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_ALOM_BURST 17 +#define NV4_PGRAPH_DEBUG_1_ALOM_BURST_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_BIDIR_DRAIN 18 +#define NV4_PGRAPH_DEBUG_1_BIDIR_DRAIN_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_EARLY_POST 19 +#define NV4_PGRAPH_DEBUG_1_EARLY_POST_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_CTX 20 +#define NV4_PGRAPH_DEBUG_1_CTX_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_FIXED_ADRS 21 +#define NV4_PGRAPH_DEBUG_1_FIXED_ADRS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_2D 22 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_3D 23 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_CACHE 24 +#define NV4_PGRAPH_DEBUG_1_CACHE_IGNORE 0x0 +#define NV4_PGRAPH_DEBUG_1_CACHE_FLUSH 0x1 +#define NV4_PGRAPH_DEBUG_1_CACHE_MODE 25 +#define NV4_PGRAPH_DEBUG_1_CACHE_MODE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_ZCLAMP 28 +#define NV4_PGRAPH_DEBUG_1_ZCLAMP_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_UCLAMP 29 +#define NV4_PGRAPH_DEBUG_1_UCLAMP_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_RCLAMP 30 +#define NV4_PGRAPH_DEBUG_1_RCLAMP_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_DX6_2PIXMODE 31 +#define NV4_PGRAPH_DEBUG_1_DX6_2PIXMODE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2 0x400088 +#define NV4_PGRAPH_DEBUG_2_HONOR_SRCFMT 0 +#define NV4_PGRAPH_DEBUG_2_HONOR_SRCFMT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_PINGPONG 0 +#define NV4_PGRAPH_DEBUG_2_PINGPONG_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_SPARE1 4 +#define NV4_PGRAPH_DEBUG_2_SPARE2 5 +#define NV4_PGRAPH_DEBUG_2_SPARE3 6 +#define NV4_PGRAPH_DEBUG_2_SPARE4 7 +#define NV4_PGRAPH_DEBUG_2_SPARE5 8 +#define NV4_PGRAPH_DEBUG_2_SPARE6 9 +#define NV4_PGRAPH_DEBUG_2_SPARE7 10 +#define NV4_PGRAPH_DEBUG_2_MCLK_RECTS 11 +#define NV4_PGRAPH_DEBUG_2_MCLK_RECTS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_BILINEAR_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_ANISOTROPIC_3D 13 +#define NV4_PGRAPH_DEBUG_2_ANISOTROPIC_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_FOG_3D 14 +#define NV4_PGRAPH_DEBUG_2_FOG_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_SPECULAR_3D 15 +#define NV4_PGRAPH_DEBUG_2_SPECULAR_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_ALPHA_3D 16 +#define NV4_PGRAPH_DEBUG_2_ALPHA_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ 17 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_CRZRWCW 0x0 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_ZRWCRW 0x1 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_AUTO 0x2 +#define NV4_PGRAPH_DEBUG_2_COELESCE_D3D 20 +#define NV4_PGRAPH_DEBUG_2_COELESCE_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_COELESCE_2D 22 +#define NV4_PGRAPH_DEBUG_2_COELESCE_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_FAST_VERTEX_LOAD 23 +#define NV4_PGRAPH_DEBUG_2_FAST_VERTEX_LOAD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_BLIT_MULTILINE 24 +#define NV4_PGRAPH_DEBUG_2_BLIT_MULTILINE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_VOLATILE_RESET 28 +#define NV4_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3 0x40008C +#define NV4_PGRAPH_DEBUG_3_CULLING 0 +#define NV4_PGRAPH_DEBUG_3_CULLING_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE 1 +#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE_DX3 0x0 +#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE_DX5 0x1 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_STRTCH 4 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_STRTCH_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_D3D 5 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_IMAGE 6 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_IMAGE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_ZFLUSH 7 +#define NV4_PGRAPH_DEBUG_3_ZFLUSH_IGNORE 0x0 +#define NV4_PGRAPH_DEBUG_3_ZFLUSH_ACTIVATE 0x1 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_PTZ 8 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_PTZ_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D 9 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_PTZ 10 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_PTZ_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D 11 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_2D 12 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_3D 13 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_2D 14 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_3D 15 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FORCE_CREAD 16 +#define NV4_PGRAPH_DEBUG_3_FORCE_CREAD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FORCE_ZREAD 17 +#define NV4_PGRAPH_DEBUG_3_FORCE_ZREAD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_EARLYZ_ABORT 18 +#define NV4_PGRAPH_DEBUG_3_EARLYZ_ABORT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_TRIEND_FLUSH 19 +#define NV4_PGRAPH_DEBUG_3_TRIEND_FLUSH_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK 20 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_FAIL_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FORMAT_CHECK 22 +#define NV4_PGRAPH_DEBUG_3_FORMAT_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_DMA_CHECK 23 +#define NV4_PGRAPH_DEBUG_3_DMA_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_RAMREADBACK 24 +#define NV4_PGRAPH_DEBUG_3_RAMREADBACK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_CLIP_METHODS 25 +#define NV4_PGRAPH_DEBUG_3_CLIP_METHODS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_EXCLUDE_ROP_IN_IDLE 27 +#define NV4_PGRAPH_DEBUG_3_EXCLUDE_ROP_IN_IDLE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_STATE_CHECK 28 +#define NV4_PGRAPH_DEBUG_3_STATE_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_CONTEXT_METHODS 29 +#define NV4_PGRAPH_DEBUG_3_CONTEXT_METHODS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_OPERATION_METHOD 30 +#define NV4_PGRAPH_DEBUG_3_OPERATION_METHOD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_IGNORE_PATCHVALID 31 +#define NV4_PGRAPH_DEBUG_3_IGNORE_PATCHVALID_ENABLED 0x1 +#define NV4_PGRAPH_INTR 0x400100 +#define NV4_PGRAPH_INTR_NOTIFY 0 +#define NV4_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_NOTIFY_PENDING 0x1 +#define NV4_PGRAPH_INTR_NOTIFY_RESET 0x1 +#define NV4_PGRAPH_INTR_MISSING_HW 4 +#define NV4_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_MISSING_HW_PENDING 0x1 +#define NV4_PGRAPH_INTR_MISSING_HW_RESET 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A 8 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B 9 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x1 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH 12 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x1 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x1 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY 16 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x1 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x1 +#define NV4_PGRAPH_NSTATUS 0x400104 +#define NV4_PGRAPH_NSTATUS_STATE_IN_USE 11 +#define NV4_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x1 +#define NV4_PGRAPH_NSTATUS_INVALID_STATE 12 +#define NV4_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x1 +#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT 13 +#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x1 +#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT 14 +#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE 0x400108 +#define NV4_PGRAPH_NSOURCE_NOTIFICATION 0 +#define NV4_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DATA_ERROR 1 +#define NV4_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR 2 +#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION 3 +#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR 4 +#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_ 5 +#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD 6 +#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION 7 +#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION 8 +#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9 +#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION 10 +#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_STATE_INVALID 11 +#define NV4_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12 +#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE 13 +#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_METHOD_CNT 14 +#define NV4_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION 15 +#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x1 +#define NV4_PGRAPH_INTR_EN 0x400140 +#define NV4_PGRAPH_INTR_EN_NOTIFY 0 +#define NV4_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_MISSING_HW 4 +#define NV4_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_A 8 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_B 9 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_CONTEXT_SWITCH 12 +#define NV4_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_BUFFER_NOTIFY 16 +#define NV4_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x1 +#define NV4_PGRAPH_CTX_SWITCH1 0x400160 +#define NV4_PGRAPH_CTX_SWITCH1_GRCLASS 0 +#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12 +#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP 13 +#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE 14 +#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x2 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x3 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x4 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x5 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE 20 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_COMPATIBILITY 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_DITHER 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_TRUNCATE 0x2 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_MS 0x3 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25 +#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31 +#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x1 +#define NV4_PGRAPH_CTX_SWITCH2 0x400164 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT 0 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 +#define NV4_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 16 +#define NV4_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH3 0x400168 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 0 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 16 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH4 0x40016C +#define NV4_PGRAPH_CTX_SWITCH4_USER_INSTANCE 0 +#define NV4_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x00 +#define NV4_PGRAPH_CTX_CACHE1(i) (0x400180+(i)*4) +#define NV4_PGRAPH_CTX_CACHE1_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE1_GRCLASS 0 +#define NV4_PGRAPH_CTX_CACHE1_CHROMA_KEY 12 +#define NV4_PGRAPH_CTX_CACHE1_USER_CLIP 13 +#define NV4_PGRAPH_CTX_CACHE1_SWIZZLE 14 +#define NV4_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 +#define NV4_PGRAPH_CTX_CACHE1_SPARE1 20 +#define NV4_PGRAPH_CTX_CACHE1_PATCH_STATUS 24 +#define NV4_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25 +#define NV4_PGRAPH_CTX_CACHE2(i) (0x4001a0+(i)*4) +#define NV4_PGRAPH_CTX_CACHE2_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE2_MONO_FORMAT 0 +#define NV4_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 +#define NV4_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 16 +#define NV4_PGRAPH_CTX_CACHE3(i) (0x4001c0+(i)*4) +#define NV4_PGRAPH_CTX_CACHE3_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 0 +#define NV4_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 16 +#define NV4_PGRAPH_CTX_CACHE4(i) (0x4001e0+(i)*4) +#define NV4_PGRAPH_CTX_CACHE4_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE4_USER_INSTANCE 0 +#define NV4_PGRAPH_CTX_CONTROL 0x400170 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME 0 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x0 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x1 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x2 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x3 +#define NV4_PGRAPH_CTX_CONTROL_TIME 8 +#define NV4_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x0 +#define NV4_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x1 +#define NV4_PGRAPH_CTX_CONTROL_CHID 16 +#define NV4_PGRAPH_CTX_CONTROL_CHID_INVALID 0x0 +#define NV4_PGRAPH_CTX_CONTROL_CHID_VALID 0x1 +#define NV4_PGRAPH_CTX_CONTROL_CHANGE 20 +#define NV4_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x0 +#define NV4_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x1 +#define NV4_PGRAPH_CTX_CONTROL_SWITCHING 24 +#define NV4_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x0 +#define NV4_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x1 +#define NV4_PGRAPH_CTX_CONTROL_DEVICE 28 +#define NV4_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x0 +#define NV4_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x1 +#define NV4_PGRAPH_CTX_USER 0x400174 +#define NV4_PGRAPH_CTX_USER_SUBCH 13 +#define NV4_PGRAPH_CTX_USER_SUBCH_0 0x0 +#define NV4_PGRAPH_CTX_USER_CHID 24 +#define NV4_PGRAPH_CTX_USER_CHID_0 0x0 +#define NV4_PGRAPH_FIFO 0x400720 +#define NV4_PGRAPH_FIFO_ACCESS 0 +#define NV4_PGRAPH_FIFO_ACCESS_DISABLED 0x0 +#define NV4_PGRAPH_FIFO_ACCESS_ENABLED 0x1 +#define NV4_PGRAPH_FFINTFC_FIFO_0(i) (0x400730+(i)*4) +#define NV4_PGRAPH_FFINTFC_FIFO_0_SIZE_1 4 +#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG 0 +#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x0 +#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x1 +// Note: shift left by 1 (3:1). Subch number = 0-7 +#define NV4_PGRAPH_FFINTFC_FIFO_0_SUBCH 1 +#define NV4_PGRAPH_FFINTFC_FIFO_0_MTHD 4 +#define NV4_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x0 +#define NV4_PGRAPH_FFINTFC_FIFO_1(i) (0x400740+(i)*4) +#define NV4_PGRAPH_FFINTFC_FIFO_1_SIZE_1 4 +#define NV4_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 0 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR 0x400750 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_WRITE 0 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x0 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_READ 4 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x0 +#define NV4_PGRAPH_FFINTFC_ST2 0x400754 +#define NV4_PGRAPH_FFINTFC_ST2_STATUS 0 +#define NV4_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_MTHD 1 +#define NV4_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH 12 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_0 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_1 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_2 0x2 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_3 0x3 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_4 0x4 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_5 0x5 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_6 0x6 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_7 0x7 +#define NV4_PGRAPH_FFINTFC_ST2_CHID 15 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_0 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_1 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_2 0x2 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_3 0x3 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_4 0x4 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_5 0x5 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_6 0x6 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_7 0x7 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_8 0x8 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_9 0x9 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_10 0xA +#define NV4_PGRAPH_FFINTFC_ST2_CHID_11 0xB +#define NV4_PGRAPH_FFINTFC_ST2_CHID_12 0xC +#define NV4_PGRAPH_FFINTFC_ST2_CHID_13 0xD +#define NV4_PGRAPH_FFINTFC_ST2_CHID_14 0xE +#define NV4_PGRAPH_FFINTFC_ST2_CHID_15 0xF +#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS 19 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT 20 +#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT_CLEAR 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT_SET 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD 21 +#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD_CLEAR 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD_SET 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_D 0x400758 +#define NV4_PGRAPH_FFINTFC_ST2_D_ARGUMENT 0 +#define NV4_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x0 +#define NV4_PGRAPH_STATUS 0x400700 +#define NV4_PGRAPH_STATUS_STATE 0 +#define NV4_PGRAPH_STATUS_STATE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_STATE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_XY_LOGIC 4 +#define NV4_PGRAPH_STATUS_XY_LOGIC_IDLE 0x0 +#define NV4_PGRAPH_STATUS_XY_LOGIC_BUSY 0x1 +#define NV4_PGRAPH_STATUS_FE 5 +#define NV4_PGRAPH_STATUS_FE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_FE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_RASTERIZER 6 +#define NV4_PGRAPH_STATUS_RASTERIZER_IDLE 0x0 +#define NV4_PGRAPH_STATUS_RASTERIZER_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_NOTIFY 8 +#define NV4_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_REGISTER 12 +#define NV4_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_DMA 16 +#define NV4_PGRAPH_STATUS_PORT_DMA_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_DMA_BUSY 0x1 +#define NV4_PGRAPH_STATUS_DMA_ENGINE 17 +#define NV4_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_DMA_NOTIFY 20 +#define NV4_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x0 +#define NV4_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x1 +#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21 +#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x0 +#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x1 +#define NV4_PGRAPH_STATUS_D3D 24 +#define NV4_PGRAPH_STATUS_D3D_IDLE 0x0 +#define NV4_PGRAPH_STATUS_D3D_BUSY 0x1 +#define NV4_PGRAPH_STATUS_CACHE 25 +#define NV4_PGRAPH_STATUS_CACHE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_CACHE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_LIGHTING 26 +#define NV4_PGRAPH_STATUS_LIGHTING_IDLE 0x0 +#define NV4_PGRAPH_STATUS_LIGHTING_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PREROP 27 +#define NV4_PGRAPH_STATUS_PREROP_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PREROP_BUSY 0x1 +#define NV4_PGRAPH_STATUS_ROP 28 +#define NV4_PGRAPH_STATUS_ROP_IDLE 0x0 +#define NV4_PGRAPH_STATUS_ROP_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_USER 29 +#define NV4_PGRAPH_STATUS_PORT_USER_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_USER_BUSY 0x1 +#define NV4_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV4_PGRAPH_TRAPPED_ADDR_MTHD 2 +#define NV4_PGRAPH_TRAPPED_ADDR_SUBCH 13 +#define NV4_PGRAPH_TRAPPED_ADDR_CHID 24 +#define NV4_PGRAPH_TRAPPED_DATA 0x400708 +#define NV4_PGRAPH_TRAPPED_DATA_VALUE 0 +#define NV4_PGRAPH_SURFACE 0x40070C +#define NV4_PGRAPH_SURFACE_TYPE 0 +#define NV4_PGRAPH_SURFACE_TYPE_INVALID 0x0 +#define NV4_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x1 +#define NV4_PGRAPH_SURFACE_TYPE_SWIZZLE 0x2 +#define NV4_PGRAPH_NOTIFY 0x400714 +#define NV4_PGRAPH_NOTIFY_BUFFER_REQ 0 +#define NV4_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x0 +#define NV4_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x1 +#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE 8 +#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x0 +#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x1 +#define NV4_PGRAPH_NOTIFY_REQ 16 +#define NV4_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x0 +#define NV4_PGRAPH_NOTIFY_REQ_PENDING 0x1 +#define NV4_PGRAPH_NOTIFY_STYLE 20 +#define NV4_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x0 +#define NV4_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x1 +#define NV4_PGRAPH_BOFFSET(i) (0x400640+(i)*4) +//used for all +#define NV4_PGRAPH_BOFFSET_LINADRS_DEFAULT 0x0 +#define NV4_PGRAPH_BOFFSET_SIZE_1 6 +#define NV4_PGRAPH_BOFFSET_LINADRS 0 +#define NV4_PGRAPH_BOFFSET_LINADRS_0 0x0 +#define NV4_PGRAPH_BOFFSET0 0x400640 +#define NV4_PGRAPH_BOFFSET0_ALIAS_1 NV_PGRAPH_BOFFSET(0) +#define NV4_PGRAPH_BOFFSET0_LINADRS 0 +#define NV4_PGRAPH_BOFFSET1 0x400644 +#define NV4_PGRAPH_BOFFSET1_ALIAS_1 NV_PGRAPH_BOFFSET(1) +#define NV4_PGRAPH_BOFFSET1_LINADRS 0 +#define NV4_PGRAPH_BOFFSET2 0x400648 +#define NV4_PGRAPH_BOFFSET2_ALIAS_1 NV_PGRAPH_BOFFSET(2) +#define NV4_PGRAPH_BOFFSET2_LINADRS 0 +#define NV4_PGRAPH_BOFFSET3 0x40064C +#define NV4_PGRAPH_BOFFSET3_ALIAS_1 NV_PGRAPH_BOFFSET(3) +#define NV4_PGRAPH_BOFFSET3_LINADRS 0 +#define NV4_PGRAPH_BOFFSET4 0x400650 +#define NV4_PGRAPH_BOFFSET4_ALIAS_1 NV_PGRAPH_BOFFSET(4) +#define NV4_PGRAPH_BOFFSET4_LINADRS 0 +#define NV4_PGRAPH_BOFFSET5 0x400654 +#define NV4_PGRAPH_BOFFSET5_ALIAS_1 NV_PGRAPH_BOFFSET(5) +#define NV4_PGRAPH_BOFFSET5_LINADRS 0 +#define NV4_PGRAPH_BBASE(i) (0x400658+(i)*4) +//used for all +#define NV4_PGRAPH_BBASE_LINADRS_DEFAULT 0x0 +#define NV4_PGRAPH_BBASE_SIZE_1 6 +#define NV4_PGRAPH_BBASE_LINADRS 0 +#define NV4_PGRAPH_BBASE0 0x400658 +#define NV4_PGRAPH_BBASE0_ALIAS_1 NV_PGRAPH_BBASE(0) +#define NV4_PGRAPH_BBASE0_LINADRS 0 +#define NV4_PGRAPH_BBASE1 0x40065c +#define NV4_PGRAPH_BBASE1_ALIAS_1 NV_PGRAPH_BBASE(1) +#define NV4_PGRAPH_BBASE1_LINADRS 0 +#define NV4_PGRAPH_BBASE2 0x400660 +#define NV4_PGRAPH_BBASE2_ALIAS_1 NV_PGRAPH_BBASE(2) +#define NV4_PGRAPH_BBASE2_LINADRS 0 +#define NV4_PGRAPH_BBASE3 0x400664 +#define NV4_PGRAPH_BBASE3_ALIAS_1 NV_PGRAPH_BBASE(3) +#define NV4_PGRAPH_BBASE3_LINADRS 0 +#define NV4_PGRAPH_BBASE4 0x400668 +#define NV4_PGRAPH_BBASE4_ALIAS_1 NV_PGRAPH_BBASE(4) +#define NV4_PGRAPH_BBASE4_LINADRS 0 +#define NV4_PGRAPH_BBASE5 0x40066C +#define NV4_PGRAPH_BBASE5_ALIAS_1 NV_PGRAPH_BBASE(5) +#define NV4_PGRAPH_BBASE5_LINADRS 0 +#define NV4_PGRAPH_BPITCH(i) (0x400670+(i)*4) +//used for all +#define NV4_PGRAPH_BPITCH_LINADRS_DEFAULT 0x0 +#define NV4_PGRAPH_BPITCH_SIZE_1 5 +#define NV4_PGRAPH_BPITCH_VALUE 0 // use bit 0 for all +#define NV4_PGRAPH_BPITCH_VALUE_0 0x0 +#define NV4_PGRAPH_BPITCH0 0x400670 +#define NV4_PGRAPH_BPITCH0_ALIAS_1 NV_PGRAPH_BPITCH(0) +#define NV4_PGRAPH_BPITCH1 0x400674 +#define NV4_PGRAPH_BPITCH1_ALIAS_1 NV_PGRAPH_BPITCH(1) +#define NV4_PGRAPH_BPITCH2 0x400678 +#define NV4_PGRAPH_BPITCH2_ALIAS_1 NV_PGRAPH_BPITCH(2) +#define NV4_PGRAPH_BPITCH3 0x40067C +#define NV4_PGRAPH_BPITCH3_ALIAS_1 NV_PGRAPH_BPITCH(3) +#define NV4_PGRAPH_BPITCH4 0x400680 +#define NV4_PGRAPH_BPITCH4_ALIAS_1 NV_PGRAPH_BPITCH(4) +#define NV4_PGRAPH_BLIMIT(i) (0x400684+(i)*4) +//following two used for all +#define NV4_PGRAPH_BLIMIT_SIZE_1 6 +#define NV4_PGRAPH_BLIMIT_VALUE 0 +#define NV4_PGRAPH_BLIMIT_TYPE 31 +#define NV4_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x0 +#define NV4_PGRAPH_BLIMIT_TYPE_NULL 0x1 +#define NV4_PGRAPH_BLIMIT0 0x400684 +#define NV4_PGRAPH_BLIMIT0_ALIAS_1 NV_PGRAPH_BLIMIT(0) +#define NV4_PGRAPH_BLIMIT1 0x400688 +#define NV4_PGRAPH_BLIMIT1_ALIAS_1 NV_PGRAPH_BLIMIT(1) +#define NV4_PGRAPH_BLIMIT2 0x40068c +#define NV4_PGRAPH_BLIMIT2_ALIAS_1 NV_PGRAPH_BLIMIT(2) +#define NV4_PGRAPH_BLIMIT3 0x400690 +#define NV4_PGRAPH_BLIMIT3_ALIAS_1 NV_PGRAPH_BLIMIT(3) +#define NV4_PGRAPH_BLIMIT4 0x400694 +#define NV4_PGRAPH_BLIMIT4_ALIAS_1 NV_PGRAPH_BLIMIT(4) +#define NV4_PGRAPH_BLIMIT5 0x400698 +#define NV4_PGRAPH_BLIMIT5_ALIAS_1 NV_PGRAPH_BLIMIT(5) +#define NV4_PGRAPH_BSWIZZLE2 0x40069c +#define NV4_PGRAPH_BSWIZZLE2_WIDTH 16 +#define NV4_PGRAPH_BSWIZZLE2_WIDTH_0 0x0 +#define NV4_PGRAPH_BSWIZZLE2_HEIGHT 24 +#define NV4_PGRAPH_BSWIZZLE2_HEIGHT_0 0x0 +#define NV4_PGRAPH_BSWIZZLE5 0x4006a0 +#define NV4_PGRAPH_BSWIZZLE5_WIDTH 16 +#define NV4_PGRAPH_BSWIZZLE5_WIDTH_0 0x0 +#define NV4_PGRAPH_BSWIZZLE5_HEIGHT 24 +#define NV4_PGRAPH_BSWIZZLE5_HEIGHT_0 0x0 +#define NV4_PGRAPH_BPIXEL 0x400724 +#define NV4_PGRAPH_BPIXEL_DEPTH0 0 +#define NV4_PGRAPH_BPIXEL_DEPTH1 4 +#define NV4_PGRAPH_BPIXEL_DEPTH2 8 +#define NV4_PGRAPH_BPIXEL_DEPTH3 12 +#define NV4_PGRAPH_BPIXEL_DEPTH4 16 +#define NV4_PGRAPH_BPIXEL_DEPTH5 20 + +// valid for depth0-depth5 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_INVALID 0x0 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y8 0x1 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1R5G5B5_Z1R5G5B5 0x2 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1R5G5B5_O1R5G5B5 0x3 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_A1R5G5B5 0x4 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_R5G6B5 0x5 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y16 0x6 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_Z8R8G8B8 0x7 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_O1Z7R8G8B8 0x8 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x9 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1A7R8G8B8_O1A7R8G8B8 0xA +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_O8R8G8B8 0xB +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_A8R8G8B8 0xC +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y32 0xD +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_V8YB8U8YA8 0xE +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_YB8V8YA8U8 0xF + +#define NV4_PGRAPH_LIMIT_VIOL_PIX 0x400610 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_ADRS 0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT 29 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_Z 0x400614 +#define NV4_PGRAPH_LIMIT_VIOL_Z_ADRS 0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT 30 +#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31 +#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x1 +#define NV4_PGRAPH_STATE 0x400710 +#define NV4_PGRAPH_STATE_BUFFER_0 0 +#define NV4_PGRAPH_STATE_BUFFER_0_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_0_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_1 1 +#define NV4_PGRAPH_STATE_BUFFER_1_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_1_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_2 2 +#define NV4_PGRAPH_STATE_BUFFER_2_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_2_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_3 3 +#define NV4_PGRAPH_STATE_BUFFER_3_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_3_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_4 4 +#define NV4_PGRAPH_STATE_BUFFER_4_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_4_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_5 5 +#define NV4_PGRAPH_STATE_BUFFER_5_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_5_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_0 8 +#define NV4_PGRAPH_STATE_PITCH_0_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_0_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_1 9 +#define NV4_PGRAPH_STATE_PITCH_1_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_1_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_2 10 +#define NV4_PGRAPH_STATE_PITCH_2_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_2_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_3 11 +#define NV4_PGRAPH_STATE_PITCH_3_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_3_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_4 12 +#define NV4_PGRAPH_STATE_PITCH_4_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_4_VALID 0x1 +#define NV4_PGRAPH_STATE_CHROMA_COLOR 16 +#define NV4_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x0 +#define NV4_PGRAPH_STATE_CHROMA_COLOR_VALID 0x1 +#define NV4_PGRAPH_STATE_CHROMA_COLORFMT 17 +#define NV4_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x1 +#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT 20 +#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x1 +#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT 21 +#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x1 +#define NV4_PGRAPH_STATE_CPATTERN_SELECT 22 +#define NV4_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_COLOR0 24 +#define NV4_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_COLOR1 25 +#define NV4_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_PATT0 26 +#define NV4_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_PATT0_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_PATT1 27 +#define NV4_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_PATT1_VALID 0x1 +#define NV4_PGRAPH_CACHE_INDEX 0x400728 +#define NV4_PGRAPH_CACHE_INDEX_BANK 2 +#define NV4_PGRAPH_CACHE_INDEX_BANK_10 0x0 +#define NV4_PGRAPH_CACHE_INDEX_BANK_32 0x1 +#define NV4_PGRAPH_CACHE_INDEX_ADRS 3 +#define NV4_PGRAPH_CACHE_INDEX_ADRS_0 0x0 +#define NV4_PGRAPH_CACHE_INDEX_ADRS_1024 0x400 +#define NV4_PGRAPH_CACHE_INDEX_OP 13 +#define NV4_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x0 +#define NV4_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x1 +#define NV4_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x2 +#define NV4_PGRAPH_CACHE_RAM 0x40072c +#define NV4_PGRAPH_CACHE_RAM_VALUE 0 +#define NV4_PGRAPH_DMA_PITCH 0x400760 +#define NV4_PGRAPH_DMA_PITCH_S0 0 +#define NV4_PGRAPH_DMA_PITCH_S1 16 +#define NV4_PGRAPH_DVD_COLORFMT 0x400764 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE 0 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY 8 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 +#define NV4_PGRAPH_SCALED_FORMAT 0x400768 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN 16 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x0 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x1 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x2 +#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24 +#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x0 +#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x1 +#define NV4_PGRAPH_PATT_COLOR0 0x400800 +#define NV4_PGRAPH_PATT_COLOR0_VALUE 0 +#define NV4_PGRAPH_PATT_COLOR1 0x400804 +#define NV4_PGRAPH_PATT_COLOR1_VALUE 0 +#define NV4_PGRAPH_PATT_COLORRAM(i) (0x400900+(i)*4) +#define NV4_PGRAPH_PATT_COLORRAM_SIZE_1 64 +#define NV4_PGRAPH_PATT_COLORRAM_VALUE 0 +#define NV4_PGRAPH_PATTERN(i) (0x400808+(i)*4) +#define NV4_PGRAPH_PATTERN_SIZE_1 2 +#define NV4_PGRAPH_PATTERN_BITMAP 0 +#define NV4_PGRAPH_PATTERN_SHAPE 0x400810 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE 0 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x0 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x1 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x2 +#define NV4_PGRAPH_PATTERN_SHAPE_SELECT 4 +#define NV4_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x0 +#define NV4_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x1 +#define NV4_PGRAPH_MONO_COLOR0 0x400600 +#define NV4_PGRAPH_MONO_COLOR0_VALUE 0 +#define NV4_PGRAPH_ROP3 0x400604 +#define NV4_PGRAPH_ROP3_VALUE 0 +#define NV4_PGRAPH_CHROMA 0x400814 +#define NV4_PGRAPH_CHROMA_VALUE 0 +#define NV4_PGRAPH_BETA_AND 0x400608 +#define NV4_PGRAPH_BETA_AND_VALUE_FRACTION 23 +#define NV4_PGRAPH_BETA_PREMULT 0x40060c +#define NV4_PGRAPH_BETA_PREMULT_VALUE 0 +#define NV4_PGRAPH_CONTROL0 0x400818 +#define NV4_PGRAPH_CONTROL0_ALPHAREF 0 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC 8 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_NEVER 0x1 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_LESS 0x2 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_EQUAL 0x3 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_LESSEQUAL 0x4 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_GREATER 0x5 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_NOTEQUAL 0x6 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_GREATEREQUAL 0x7 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_ALWAYS 0x8 +#define NV4_PGRAPH_CONTROL0_ALPHATESTENABLE 12 +#define NV4_PGRAPH_CONTROL0_ALPHATESTENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ZENABLE 14 +#define NV4_PGRAPH_CONTROL0_ZENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_ZENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ZFUNC 16 +#define NV4_PGRAPH_CONTROL0_ZFUNC_NEVER 0x1 +#define NV4_PGRAPH_CONTROL0_ZFUNC_LESS 0x2 +#define NV4_PGRAPH_CONTROL0_ZFUNC_EQUAL 0x3 +#define NV4_PGRAPH_CONTROL0_ZFUNC_LESSEQUAL 0x4 +#define NV4_PGRAPH_CONTROL0_ZFUNC_GREATER 0x5 +#define NV4_PGRAPH_CONTROL0_ZFUNC_NOTEQUAL 0x6 +#define NV4_PGRAPH_CONTROL0_ZFUNC_GREATEREQUAL 0x7 +#define NV4_PGRAPH_CONTROL0_ZFUNC_ALWAYS 0x8 +#define NV4_PGRAPH_CONTROL0_CULLMODE 20 +#define NV4_PGRAPH_CONTROL0_CULLMODE_NONE 0x1 +#define NV4_PGRAPH_CONTROL0_CULLMODE_CW 0x2 +#define NV4_PGRAPH_CONTROL0_CULLMODE_CCW 0x3 +#define NV4_PGRAPH_CONTROL0_DITHERENABLE 22 +#define NV4_PGRAPH_CONTROL0_DITHERENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_DITHERENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE 23 +#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE 24 +#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE 25 +#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE 26 +#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE 27 +#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE 28 +#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE 29 +#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_Z_FORMAT 30 +#define NV4_PGRAPH_CONTROL0_Z_FORMAT_FIXED 0x1 +#define NV4_PGRAPH_CONTROL0_Z_FORMAT_FLOAT 0x2 +#define NV4_PGRAPH_CONTROL1 0x40081c +#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE 0 +#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC 4 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_NEVER 0x1 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_LESS 0x2 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_EQUAL 0x3 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_LESSEQUAL 0x4 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_GREATER 0x5 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_NOTEQUAL 0x6 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_GREATEREQUAL 0x7 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_ALWAYS 0x8 +#define NV4_PGRAPH_CONTROL1_STENCIL_REF 8 +#define NV4_PGRAPH_CONTROL1_STENCIL_MASK_READ 16 +#define NV4_PGRAPH_CONTROL1_STENCIL_MASK_WRITE 24 +#define NV4_PGRAPH_CONTROL2 0x400820 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL 0 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_KEEP 0x1 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_ZERO 0x2 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_REPLACE 0x3 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INCRSAT 0x4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_DECRSAT 0x5 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INVERT 0x6 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INCR 0x7 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_DECR 0x8 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL 4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_KEEP 0x1 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_ZERO 0x2 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_REPLACE 0x3 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INCRSAT 0x4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_DECRSAT 0x5 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INVERT 0x6 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INCR 0x7 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_DECR 0x8 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS 8 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_KEEP 0x1 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_ZERO 0x2 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_REPLACE 0x3 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INCRSAT 0x4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_DECRSAT 0x5 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INVERT 0x6 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INCR 0x7 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_DECR 0x8 +#define NV4_PGRAPH_BLEND 0x400824 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND 0 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECAL 0x1 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATE 0x2 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x3 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x4 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECALMASK 0x5 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x6 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_COPY 0x7 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_ADD 0x8 +#define NV4_PGRAPH_BLEND_MASK_BIT 4 +#define NV4_PGRAPH_BLEND_MASK_BIT_LSB 0x1 +#define NV4_PGRAPH_BLEND_MASK_BIT_MSB 0x2 +#define NV4_PGRAPH_BLEND_SHADEMODE 6 +#define NV4_PGRAPH_BLEND_SHADEMODE_FLAT 0x1 +#define NV4_PGRAPH_BLEND_SHADEMODE_GOURAUD 0x2 +#define NV4_PGRAPH_BLEND_SHADEMODE_PHONG 0x3 +#define NV4_PGRAPH_BLEND_TEXTUREPERSPECTIVE 8 +#define NV4_PGRAPH_BLEND_TEXTUREPERSPECTIVE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_SPECULARENABLE 12 +#define NV4_PGRAPH_BLEND_SPECULARENABLE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_FOGENABLE 16 +#define NV4_PGRAPH_BLEND_FOGENABLE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_ALPHABLENDENABLE 20 +#define NV4_PGRAPH_BLEND_ALPHABLENDENABLE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_SRCBLEND 24 +#define NV4_PGRAPH_BLEND_SRCBLEND_ZERO 0x1 +#define NV4_PGRAPH_BLEND_SRCBLEND_ONE 0x2 +#define NV4_PGRAPH_BLEND_SRCBLEND_SRCCOLOR 0x3 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCCOLOR 0x4 +#define NV4_PGRAPH_BLEND_SRCBLEND_SRCALPHA 0x5 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCALPHA 0x6 +#define NV4_PGRAPH_BLEND_SRCBLEND_DESTALPHA 0x7 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVDESTALPHA 0x8 +#define NV4_PGRAPH_BLEND_SRCBLEND_DESTCOLOR 0x9 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVDESTCOLOR 0xA +#define NV4_PGRAPH_BLEND_SRCBLEND_SRCALPHASAT 0xB +#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCALPHASAT 0xC +#define NV4_PGRAPH_BLEND_SRCBLEND_BETA 0xD +#define NV4_PGRAPH_BLEND_DESTBLEND 28 +#define NV4_PGRAPH_BLEND_DESTBLEND_ZERO 0x1 +#define NV4_PGRAPH_BLEND_DESTBLEND_ONE 0x2 +#define NV4_PGRAPH_BLEND_DESTBLEND_SRCCOLOR 0x3 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVSRCCOLOR 0x4 +#define NV4_PGRAPH_BLEND_DESTBLEND_SRCALPHA 0x5 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVSRCALPHA 0x6 +#define NV4_PGRAPH_BLEND_DESTBLEND_DESTALPHA 0x7 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVDESTALPHA 0x8 +#define NV4_PGRAPH_BLEND_DESTBLEND_DESTCOLOR 0x9 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVDESTCOLOR 0xA +#define NV4_PGRAPH_BLEND_DESTBLEND_SRCALPHASAT 0xB +#define NV4_PGRAPH_DPRAM_INDEX 0x400828 +#define NV4_PGRAPH_DPRAM_INDEX_ADRS 0 +#define NV4_PGRAPH_DPRAM_INDEX_ADRS_0 0x0 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT 8 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x0 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x1 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x2 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x3 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x4 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x5 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x6 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x7 +#define NV4_PGRAPH_DPRAM_DATA 0x40082c +#define NV4_PGRAPH_DPRAM_DATA_VALUE 0 +#define NV4_PGRAPH_DPRAM_ADRS_0 0x40082c +#define NV4_PGRAPH_DPRAM_ADRS_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ADRS_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_ADRS_1 0x40082c +#define NV4_PGRAPH_DPRAM_ADRS_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ADRS_1_VALUE 0 +#define NV4_PGRAPH_DPRAM_DATA_0 0x40082c +#define NV4_PGRAPH_DPRAM_DATA_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_DATA_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_DATA_1 0x40082c +#define NV4_PGRAPH_DPRAM_DATA_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_DATA_1_VALUE 0 +#define NV4_PGRAPH_DPRAM_WE_0 0x40082c +#define NV4_PGRAPH_DPRAM_WE_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_WE_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_WE_1 0x40082c +#define NV4_PGRAPH_DPRAM_WE_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_WE_1_VALUE 0 +#define NV4_PGRAPH_DPRAM_ALPHA_0 0x40082c +#define NV4_PGRAPH_DPRAM_ALPHA_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ALPHA_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_ALPHA_1 0x40082c +#define NV4_PGRAPH_DPRAM_ALPHA_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ALPHA_1_VALUE 0 +#define NV4_PGRAPH_STORED_FMT 0x400830 +#define NV4_PGRAPH_STORED_FMT_MONO0 0 +#define NV4_PGRAPH_STORED_FMT_PATT0 8 +#define NV4_PGRAPH_STORED_FMT_PATT1 16 +#define NV4_PGRAPH_STORED_FMT_CHROMA 24 +#define NV4_PGRAPH_FORMATS 0x400618 +#define NV4_PGRAPH_FORMATS_ROP 0 +#define NV4_PGRAPH_FORMATS_ROP_Y8 0x0 +#define NV4_PGRAPH_FORMATS_ROP_RGB15 0x1 +#define NV4_PGRAPH_FORMATS_ROP_RGB16 0x2 +#define NV4_PGRAPH_FORMATS_ROP_Y16 0x3 +#define NV4_PGRAPH_FORMATS_ROP_INVALID 0x4 +#define NV4_PGRAPH_FORMATS_ROP_RGB24 0x5 +#define NV4_PGRAPH_FORMATS_ROP_RGB30 0x6 +#define NV4_PGRAPH_FORMATS_ROP_Y32 0x7 +#define NV4_PGRAPH_FORMATS_SRC 4 +#define NV4_PGRAPH_FORMATS_SRC_INVALID 0x0 +#define NV4_PGRAPH_FORMATS_SRC_LE_Y8 0x1 +#define NV4_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x2 +#define NV4_PGRAPH_FORMATS_SRC_LE_X24Y8 0x3 +#define NV4_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x6 +#define NV4_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x7 +#define NV4_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x8 +#define NV4_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x9 +#define NV4_PGRAPH_FORMATS_SRC_LE_R5G6B5 0xA +#define NV4_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0xB +#define NV4_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0xC +#define NV4_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0xD +#define NV4_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0xE +#define NV4_PGRAPH_FORMATS_SRC_LE_Y16 0xF +#define NV4_PGRAPH_FORMATS_SRC_LE_A16Y16 0x10 +#define NV4_PGRAPH_FORMATS_SRC_LE_X16Y16 0x11 +#define NV4_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x12 +#define NV4_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x13 +#define NV4_PGRAPH_FORMATS_SRC_LE_Y32 0x14 +#define NV4_PGRAPH_FORMATS_FB 12 +#define NV4_PGRAPH_FORMATS_FB_INVALID 0x0 +#define NV4_PGRAPH_FORMATS_FB_Y8 0x1 +#define NV4_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x2 +#define NV4_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x3 +#define NV4_PGRAPH_FORMATS_FB_A1R5G5B5 0x4 +#define NV4_PGRAPH_FORMATS_FB_R5G6B5 0x5 +#define NV4_PGRAPH_FORMATS_FB_Y16 0x6 +#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x7 +#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x8 +#define NV4_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x9 +#define NV4_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0xA +#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0xB +#define NV4_PGRAPH_FORMATS_FB_A8R8G8B8 0xC +#define NV4_PGRAPH_FORMATS_FB_Y32 0xD +#define NV4_PGRAPH_FORMATS_FB_V8YB8U8YA8 0xE +#define NV4_PGRAPH_FORMATS_FB_YB8V8YA8U8 0xF +#define NV4_PGRAPH_ABS_X_RAM(i) (0x400400+(i)*4) +#define NV4_PGRAPH_ABS_X_RAM_SIZE_1 32 +#define NV4_PGRAPH_ABS_X_RAM_VALUE 0 +#define NV4_PGRAPH_X_RAM_BPORT(i) (0x400c00+(i)*4) +#define NV4_PGRAPH_X_RAM_BPORT_SIZE_1 32 +#define NV4_PGRAPH_X_RAM_BPORT_VALUE 0 +#define NV4_PGRAPH_ABS_Y_RAM(i) (0x400480+(i)*4) +#define NV4_PGRAPH_ABS_Y_RAM_SIZE_1 32 +#define NV4_PGRAPH_ABS_Y_RAM_VALUE 0 +#define NV4_PGRAPH_Y_RAM_BPORT(i) (0x400c80+(i)*4) +#define NV4_PGRAPH_Y_RAM_BPORT_SIZE_1 32 +#define NV4_PGRAPH_Y_RAM_BPORT_VALUE 0 +#define NV4_PGRAPH_XY_LOGIC_MISC0 0x400514 +#define NV4_PGRAPH_XY_LOGIC_MISC0_COUNTER 0 +#define NV4_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20 +#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC0_INDEX 28 +#define NV4_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1 0x400518 +#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL 0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2 0x40051C +#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3 0x400520 +#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 16 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 24 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x0 +#define NV4_PGRAPH_X_MISC 0x400500 +#define NV4_PGRAPH_X_MISC_BIT33_0 0 +#define NV4_PGRAPH_X_MISC_BIT33_0_0 0x0 +#define NV4_PGRAPH_X_MISC_BIT33_1 1 +#define NV4_PGRAPH_X_MISC_BIT33_1_0 0x0 +#define NV4_PGRAPH_X_MISC_BIT33_2 2 +#define NV4_PGRAPH_X_MISC_BIT33_2_0 0x0 +#define NV4_PGRAPH_X_MISC_BIT33_3 3 +#define NV4_PGRAPH_X_MISC_BIT33_3_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_0 4 +#define NV4_PGRAPH_X_MISC_RANGE_0_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_1 5 +#define NV4_PGRAPH_X_MISC_RANGE_1_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_2 6 +#define NV4_PGRAPH_X_MISC_RANGE_2_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_3 7 +#define NV4_PGRAPH_X_MISC_RANGE_3_0 0x0 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT 28 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x0 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x1 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x2 +#define NV4_PGRAPH_Y_MISC 0x400504 +#define NV4_PGRAPH_Y_MISC_BIT33_0 0 +#define NV4_PGRAPH_Y_MISC_BIT33_0_0 0x0 +#define NV4_PGRAPH_Y_MISC_BIT33_1 1 +#define NV4_PGRAPH_Y_MISC_BIT33_1_0 0x0 +#define NV4_PGRAPH_Y_MISC_BIT33_2 2 +#define NV4_PGRAPH_Y_MISC_BIT33_2_0 0x0 +#define NV4_PGRAPH_Y_MISC_BIT33_3 3 +#define NV4_PGRAPH_Y_MISC_BIT33_3_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_0 4 +#define NV4_PGRAPH_Y_MISC_RANGE_0_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_1 5 +#define NV4_PGRAPH_Y_MISC_RANGE_1_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_2 6 +#define NV4_PGRAPH_Y_MISC_RANGE_2_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_3 7 +#define NV4_PGRAPH_Y_MISC_RANGE_3_0 0x0 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT 28 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x0 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x1 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x2 +#define NV4_PGRAPH_ABS_UCLIP_XMIN 0x40053C +#define NV4_PGRAPH_ABS_UCLIP_XMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIP_XMAX 0x400544 +#define NV4_PGRAPH_ABS_UCLIP_XMAX_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIP_YMIN 0x400540 +#define NV4_PGRAPH_ABS_UCLIP_YMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIP_YMAX 0x400548 +#define NV4_PGRAPH_ABS_UCLIP_YMAX_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_XMIN 0x400560 +#define NV4_PGRAPH_ABS_UCLIPA_XMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_XMAX 0x400568 +#define NV4_PGRAPH_ABS_UCLIPA_XMAX_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_YMIN 0x400564 +#define NV4_PGRAPH_ABS_UCLIPA_YMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_YMAX 0x40056C +#define NV4_PGRAPH_ABS_UCLIPA_YMAX_VALUE 0 +#define NV4_PGRAPH_SOURCE_COLOR 0x40050C +#define NV4_PGRAPH_SOURCE_COLOR_VALUE 0 +#define NV4_PGRAPH_SOURCE_COLOR_VALUE_0 0x0 +#define NV4_PGRAPH_VALID1 0x400508 +#define NV4_PGRAPH_VALID1_VLD 0 +#define NV4_PGRAPH_VALID1_VLD_0 0x0 +#define NV4_PGRAPH_VALID1_VLD_NOCLIP (0x1<<19) +#define NV4_PGRAPH_VALID1_VLD_SRCCOLOR (0x1<<16) +#define NV4_PGRAPH_VALID1_VLD_GOTMOVE (0x1<<21) +#define NV4_PGRAPH_VALID1_VLD_GOTX01 (0x3<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTX02 (0x7<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTX03 (0xF<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN01 (0x3<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN02 (0x7<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN03 (0xF<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTY01 (0x3<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTY02 (0x7<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTY03 (0xF<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN01 (0x3<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN02 (0x7<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN03 (0xF<<12) +#define NV4_PGRAPH_VALID1_VLD_X_OFFSET (0x1<<0) +#define NV4_PGRAPH_VALID1_VLD_XCHAIN_OFFSET (0x1<<4) +#define NV4_PGRAPH_VALID1_VLD_Y_OFFSET (0x1<<8) +#define NV4_PGRAPH_VALID1_VLD_YCHAIN_OFFSET (0x1<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTCOLOR0 (0x1<<17) +#define NV4_PGRAPH_VALID1_VLD_GOTCOLOR1 (0x1<<18) +#define NV4_PGRAPH_VALID1_VLD_GOTCLIP (0x1<<20) +#define NV4_PGRAPH_VALID1_VLD_GOTFONT (0x1<<22) +#define NV4_PGRAPH_VALID1_VLD_GOTOFFSET (0x1<<22) +#define NV4_PGRAPH_VALID1_VLD_GOTBPITCH (0x1<<2) +#define NV4_PGRAPH_VALID1_VLD_GOTBOFFSET (0x1<<3) +#define NV4_PGRAPH_VALID1_VLD_GOTDUDX (0x1<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTDVDY (0x1<<5) +#define NV4_PGRAPH_VALID1_VLD_GOTPOINT (0x1<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTSIZE (0x1<<9) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCH (0x1<<10) +#define NV4_PGRAPH_VALID1_VLD_GOTSTART (0x1<<11) +#define NV4_PGRAPH_VALID1_VLD_GOTDUDX2 (0x1<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTDVDY2 (0x1<<13) +#define NV4_PGRAPH_VALID1_VLD_GOTPOINT2 (0x1<<14) +#define NV4_PGRAPH_VALID1_VLD_GOTSIZE2 (0x1<<15) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCH2 (0x1<<16) +#define NV4_PGRAPH_VALID1_VLD_GOTSTART2 (0x1<<17) +#define NV4_PGRAPH_VALID1_VLD_GOTOFFSIN (0x1<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTOFFSOUT (0x1<<1) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCHIN (0x1<<2) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCHOUT (0x1<<3) +#define NV4_PGRAPH_VALID1_VLD_GOTLENGTH (0x1<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTCOUNT (0x1<<5) +#define NV4_PGRAPH_VALID1_VLD_GOTFORMAT (0x1<<6) +#define NV4_PGRAPH_VALID1_VLD_GOTNOTIFY (0x1<<7) +#define NV4_PGRAPH_VALID1_CLIP_MIN 28 +#define NV4_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIP_MIN_ONLY 0x1 +#define NV4_PGRAPH_VALID1_CLIPA_MIN 29 +#define NV4_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x1 +#define NV4_PGRAPH_VALID1_CLIP_MAX 30 +#define NV4_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIP_MAX_ONLY 0x1 +#define NV4_PGRAPH_VALID1_CLIPA_MAX 31 +#define NV4_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x1 +#define NV4_PGRAPH_VALID2 0x400578 +#define NV4_PGRAPH_VALID2_VLD2 0 +#define NV4_PGRAPH_VALID2_VLD2_0 0x0 +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE0A (1<<28) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE0C (1<<27) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE1A (1<<26) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE1C (1<<25) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBFACTOR (1<<24) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FILTER1 (1<<23) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_OFFSET1 (1<<22) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FORMAT1 (1<<21) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_BLEND (1<<20) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL2 (1<<19) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL1 (1<<18) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL0 (1<<17) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FILTER0 (1<<16) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FORMAT0 (1<<15) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_OFFSET0 (1<<14) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FOGCOLOR (1<<13) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COLORKEY (1<<12) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_V1 (1<<9) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_U1 (1<<8) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_V0 (1<<7) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_U0 (1<<6) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_X (1<<5) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_Y (1<<4) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_ZETA (1<<3) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_M (1<<2) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COLOR (1<<1) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_SPECULAR (1<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX3FULLVERTEX (0x7f<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX5FULLVERTEX (0x7f<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX6FULLVERTEX (0x1ff<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX3FULLSTATE (0x3f<<13) +#define NV4_PGRAPH_VALID2_VLD2_DX5FULLSTATE (0x1ff<<12) +#define NV4_PGRAPH_VALID2_VLD2_DX6FULLSTATE (0xFfff<<13) +#define NV4_PGRAPH_ABS_ICLIP_XMAX 0x400534 +#define NV4_PGRAPH_ABS_ICLIP_XMAX_VALUE 0 +#define NV4_PGRAPH_ABS_ICLIP_YMAX 0x400538 +#define NV4_PGRAPH_ABS_ICLIP_YMAX_VALUE 0 +#define NV4_PGRAPH_CLIPX_0 0x400524 +// Valid for all clips! +#define NV4_PGRAPH_CLIP_CONDITION_IS_GT 0x0 +#define NV4_PGRAPH_CLIP_CONDITION_IS_LT 0x1 +#define NV4_PGRAPH_CLIP_CONDITION_IS_EQ 0x2 +#define NV4_PGRAPH_CLIPX_0_CLIP0_MIN 0 +#define NV4_PGRAPH_CLIPX_0_CLIP0_MAX 2 +#define NV4_PGRAPH_CLIPX_0_CLIP1_MIN 4 +#define NV4_PGRAPH_CLIPX_0_CLIP1_MAX 6 +#define NV4_PGRAPH_CLIPX_0_CLIP2_MIN 8 +#define NV4_PGRAPH_CLIPX_0_CLIP2_MAX 10 +#define NV4_PGRAPH_CLIPX_0_CLIP3_MIN 12 +#define NV4_PGRAPH_CLIPX_0_CLIP3_MAX 14 +#define NV4_PGRAPH_CLIPX_0_CLIP4_MIN 16 +#define NV4_PGRAPH_CLIPX_0_CLIP4_MAX 18 +#define NV4_PGRAPH_CLIPX_0_CLIP5_MIN 20 +#define NV4_PGRAPH_CLIPX_0_CLIP5_MAX 22 +#define NV4_PGRAPH_CLIPX_0_CLIP6_MIN 24 +#define NV4_PGRAPH_CLIPX_0_CLIP6_MAX 26 +#define NV4_PGRAPH_CLIPX_0_CLIP7_MIN 28 +#define NV4_PGRAPH_CLIPX_0_CLIP7_MAX 30 +#define NV4_PGRAPH_CLIPX_1 0x400528 +#define NV4_PGRAPH_CLIPX_1_CLIP8_MIN 0 +#define NV4_PGRAPH_CLIPX_1_CLIP8_MAX 2 +#define NV4_PGRAPH_CLIPX_1_CLIP9_MIN 4 +#define NV4_PGRAPH_CLIPX_1_CLIP9_MAX 6 +#define NV4_PGRAPH_CLIPX_1_CLIP10_MIN 8 +#define NV4_PGRAPH_CLIPX_1_CLIP10_MAX 10 +#define NV4_PGRAPH_CLIPX_1_CLIP11_MIN 12 +#define NV4_PGRAPH_CLIPX_1_CLIP11_MAX 14 +#define NV4_PGRAPH_CLIPX_1_CLIP12_MIN 16 +#define NV4_PGRAPH_CLIPX_1_CLIP12_MAX 18 +#define NV4_PGRAPH_CLIPX_1_CLIP13_MIN 20 +#define NV4_PGRAPH_CLIPX_1_CLIP13_MAX 22 +#define NV4_PGRAPH_CLIPX_1_CLIP14_MIN 24 +#define NV4_PGRAPH_CLIPX_1_CLIP14_MAX 26 +#define NV4_PGRAPH_CLIPX_1_CLIP15_MIN 28 +#define NV4_PGRAPH_CLIPX_1_CLIP15_MAX 30 +#define NV4_PGRAPH_CLIPY_0 0x40052c +#define NV4_PGRAPH_CLIPY_0_CLIP0_MIN 0 +#define NV4_PGRAPH_CLIPY_0_CLIP0_MAX 2 +#define NV4_PGRAPH_CLIPY_0_CLIP1_MIN 4 +#define NV4_PGRAPH_CLIPY_0_CLIP1_MAX 6 +#define NV4_PGRAPH_CLIPY_0_CLIP2_MIN 8 +#define NV4_PGRAPH_CLIPY_0_CLIP2_MAX 10 +#define NV4_PGRAPH_CLIPY_0_CLIP3_MIN 12 +#define NV4_PGRAPH_CLIPY_0_CLIP3_MAX 14 +#define NV4_PGRAPH_CLIPY_0_CLIP4_MIN 16 +#define NV4_PGRAPH_CLIPY_0_CLIP4_MAX 18 +#define NV4_PGRAPH_CLIPY_0_CLIP5_MIN 20 +#define NV4_PGRAPH_CLIPY_0_CLIP5_MAX 22 +#define NV4_PGRAPH_CLIPY_0_CLIP6_MIN 24 +#define NV4_PGRAPH_CLIPY_0_CLIP6_MAX 26 +#define NV4_PGRAPH_CLIPY_0_CLIP7_MIN 28 +#define NV4_PGRAPH_CLIPY_0_CLIP7_MAX 30 +#define NV4_PGRAPH_CLIPY_1 0x400530 +#define NV4_PGRAPH_CLIPY_1_CLIP8_MIN 0 +#define NV4_PGRAPH_CLIPY_1_CLIP8_MAX 2 +#define NV4_PGRAPH_CLIPY_1_CLIP9_MIN 4 +#define NV4_PGRAPH_CLIPY_1_CLIP9_MAX 6 +#define NV4_PGRAPH_CLIPY_1_CLIP10_MIN 8 +#define NV4_PGRAPH_CLIPY_1_CLIP10_MAX 10 +#define NV4_PGRAPH_CLIPY_1_CLIP11_MIN 12 +#define NV4_PGRAPH_CLIPY_1_CLIP11_MAX 14 +#define NV4_PGRAPH_CLIPY_1_CLIP12_MIN 16 +#define NV4_PGRAPH_CLIPY_1_CLIP12_MAX 18 +#define NV4_PGRAPH_CLIPY_1_CLIP13_MIN 20 +#define NV4_PGRAPH_CLIPY_1_CLIP13_MAX 22 +#define NV4_PGRAPH_CLIPY_1_CLIP14_MIN 24 +#define NV4_PGRAPH_CLIPY_1_CLIP14_MAX 26 +#define NV4_PGRAPH_CLIPY_1_CLIP15_MIN 28 +#define NV4_PGRAPH_CLIPY_1_CLIP15_MAX 30 +#define NV4_PGRAPH_MISC24_0 0x400510 +#define NV4_PGRAPH_MISC24_0_VALUE 0 +#define NV4_PGRAPH_MISC24_1 0x400570 +#define NV4_PGRAPH_MISC24_1_VALUE 0 +#define NV4_PGRAPH_MISC24_2 0x400574 +#define NV4_PGRAPH_MISC24_2_VALUE 0 +#define NV4_PGRAPH_PASSTHRU_0 0x40057C +#define NV4_PGRAPH_PASSTHRU_0_VALUE 0 +#define NV4_PGRAPH_PASSTHRU_1 0x400580 +#define NV4_PGRAPH_PASSTHRU_1_VALUE 0 +#define NV4_PGRAPH_PASSTHRU_2 0x400584 +#define NV4_PGRAPH_PASSTHRU_2_VALUE 0 +#define NV4_PGRAPH_U_RAM(i) (0x400d00+(i)*4) +#define NV4_PGRAPH_U_RAM_SIZE_1 16 +#define NV4_PGRAPH_U_RAM_VALUE 6 +#define NV4_PGRAPH_V_RAM(i) (0x400d40+(i)*4) +#define NV4_PGRAPH_V_RAM_SIZE_1 16 +#define NV4_PGRAPH_V_RAM_VALUE 6 +#define NV4_PGRAPH_M_RAM(i) (0x400d80+(i)*4) +#define NV4_PGRAPH_M_RAM_SIZE_1 16 +#define NV4_PGRAPH_M_RAM_VALUE 6 +#define NV4_PGRAPH_D3D_XY 0x4005c0 +#define NV4_PGRAPH_D3D_XY_X_VALUE 0 +#define NV4_PGRAPH_D3D_XY_Y_VALUE 16 +#define NV4_PGRAPH_D3D_U0 0x4005c4 +#define NV4_PGRAPH_D3D_U0_VALUE 6 +#define NV4_PGRAPH_D3D_V0 0x4005c8 +#define NV4_PGRAPH_D3D_V0_VALUE 6 +#define NV4_PGRAPH_D3D_U1 0x4005cc +#define NV4_PGRAPH_D3D_U1_VALUE 6 +#define NV4_PGRAPH_D3D_V1 0x4005d0 +#define NV4_PGRAPH_D3D_V1_VALUE 6 +#define NV4_PGRAPH_D3D_ZETA 0x4005d4 +#define NV4_PGRAPH_D3D_ZETA_VALUE 0 +#define NV4_PGRAPH_D3D_RGB 0x4005d8 +#define NV4_PGRAPH_D3D_RGB_VALUE 0 +#define NV4_PGRAPH_D3D_S 0x4005dc +#define NV4_PGRAPH_D3D_S_VALUE 0 +#define NV4_PGRAPH_D3D_M 0x4005e0 +#define NV4_PGRAPH_D3D_M_VALUE 6 +#define NV4_PGRAPH_FORMAT0 0x4005A8 +#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA 1 +#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA_A 0x0 +#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA_B 0x1 +#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE 2 +#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE_FALSE 0x0 +#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE_TRUE 0x1 +#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH 5 +#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH 7 +#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT0_COLOR 8 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_Y8 0x0 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_AY8 0x1 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_A1R5G5B5 0x2 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_X1R5G5B5 0x3 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_A4R4G4B4 0x4 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_R5G6B5 0x5 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_A8R8G8B8 0x6 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_X8R8G8B8 0x7 +// 0x1-0Xf used for 1-16 mipmap levels +#define NV4_PGRAPH_FORMAT0_MIPMAP_LEVELS 12 +#define NV4_PGRAPH_FORMAT0_MIPMAP_LEVELS_INVALID 0x0 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U 16 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_1 0x0 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_2 0x1 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_4 0x2 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_8 0x3 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_16 0x4 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_32 0x5 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_64 0x6 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_128 0x7 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_256 0x8 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_512 0x9 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_1024 0xA +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_2048 0xB +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V 20 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_1 0x0 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_2 0x1 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_4 0x2 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_8 0x3 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_16 0x4 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_32 0x5 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_64 0x6 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_128 0x7 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_256 0x8 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_512 0x9 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_1024 0xA +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_2048 0xB +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU 24 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_WRAP 0x1 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_BORDER 0x4 +#define NV4_PGRAPH_FORMAT0_WRAPU 27 +#define NV4_PGRAPH_FORMAT0_WRAPU_FALSE 0x0 +#define NV4_PGRAPH_FORMAT0_WRAPU_TRUE 0x1 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV 28 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_WRAP 0x1 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_BORDER 0x4 +#define NV4_PGRAPH_FORMAT0_WRAPV 31 +#define NV4_PGRAPH_FORMAT0_WRAPV_FALSE 0x0 +#define NV4_PGRAPH_FORMAT0_WRAPV_TRUE 0x1 +#define NV4_PGRAPH_FORMAT1 0x4005AC +#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA 1 +#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA_A 0x0 +#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA_B 0x1 +#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE 2 +#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE_FALSE 0x0 +#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE_TRUE 0x1 +#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH 5 +#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH 7 +#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT1_COLOR 8 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_Y8 0x0 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_AY8 0x1 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_A1R5G5B5 0x2 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_X1R5G5B5 0x3 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_A4R4G4B4 0x4 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_R5G6B5 0x5 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_A8R8G8B8 0x6 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_X8R8G8B8 0x7 +// 15:12 = number of mipmap levels (1-15. 0 = invalid). Stupid defines removed here +#define NV4_PGRAPH_FORMAT1_MIPMAP_LEVELS 12 +#define NV4_PGRAPH_FORMAT1_MIPMAP_LEVELS_INVALID 0x0 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U 16 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_1 0x0 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_2 0x1 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_4 0x2 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_8 0x3 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_16 0x4 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_32 0x5 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_64 0x6 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_128 0x7 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_256 0x8 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_512 0x9 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_1024 0xA +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_2048 0xB +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V 20 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_1 0x0 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_2 0x1 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_4 0x2 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_8 0x3 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_16 0x4 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_32 0x5 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_64 0x6 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_128 0x7 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_256 0x8 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_512 0x9 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_1024 0xA +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_2048 0xB +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU 24 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_WRAP 0x1 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_BORDER 0x4 +#define NV4_PGRAPH_FORMAT1_WRAPU 27 +#define NV4_PGRAPH_FORMAT1_WRAPU_TRUE 0x1 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV 28 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_WRAP 0x1 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_BORDER 0x4 +#define NV4_PGRAPH_FORMAT1_WRAPV 31 +#define NV4_PGRAPH_FORMAT1_WRAPV_TRUE 0x1 +#define NV4_PGRAPH_FILTER0 0x4005B0 +#define NV4_PGRAPH_FILTER0_KERNEL_SIZE_X 1 +#define NV4_PGRAPH_FILTER0_KERNEL_SIZE_Y 9 +#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE 15 +#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER0_MIPMAPLODBIAS 16 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN 24 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_NEAREST 0x1 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEAR 0x2 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MIN_ENABLE 27 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MIN_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG 28 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_NEAREST 0x1 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEAR 0x2 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MAG_ENABLE 31 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MAG_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER1 0x4005B4 +#define NV4_PGRAPH_FILTER1_KERNEL_SIZE_X 1 +#define NV4_PGRAPH_FILTER1_KERNEL_SIZE_Y 9 +#define NV4_PGRAPH_FILTER1_MIPMAP_DITHER_ENABLE 15 +#define NV4_PGRAPH_FILTER1_MIPMAP_DITHER_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER1_MIPMAPLODBIAS 16 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN 24 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_NEAREST 0x1 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEAR 0x2 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MIN_ENABLE 27 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MIN_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG 28 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_NEAREST 0x1 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEAR 0x2 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MAG_ENABLE 31 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MAG_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA 0x400590 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION 29 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_COMBINE0COLOR 0x400594 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0 1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1 9 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2 17 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3 25 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION 29 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_COMBINE1ALPHA 0x400598 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION 29 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_COMBINE1COLOR 0x40059C +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0 1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1 9 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2 17 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3 25 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION 29 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_DMA_START_0 0x401000 +#define NV4_PGRAPH_DMA_START_0_VALUE 0 +#define NV4_PGRAPH_DMA_START_1 0x401004 +#define NV4_PGRAPH_DMA_START_1_VALUE 0 +#define NV4_PGRAPH_DMA_LENGTH 0x401008 +#define NV4_PGRAPH_DMA_LENGTH_VALUE 0 +#define NV4_PGRAPH_DMA_MISC 0x40100C +#define NV4_PGRAPH_DMA_MISC_COUNT 0 +#define NV4_PGRAPH_DMA_MISC_FMT_SRC 16 +#define NV4_PGRAPH_DMA_MISC_FMT_DST 20 +#define NV4_PGRAPH_DMA_DATA_0 0x401020 +#define NV4_PGRAPH_DMA_DATA_0_VALUE 0 +#define NV4_PGRAPH_DMA_DATA_1 0x401024 +#define NV4_PGRAPH_DMA_DATA_1_VALUE 0 +#define NV4_PGRAPH_DMA_RM 0x401030 +#define NV4_PGRAPH_DMA_RM_ASSIST_A 0 +#define NV4_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x0 +#define NV4_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x1 +#define NV4_PGRAPH_DMA_RM_ASSIST_A_RESET 0x1 +#define NV4_PGRAPH_DMA_RM_ASSIST_B 1 +#define NV4_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x0 +#define NV4_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x1 +#define NV4_PGRAPH_DMA_RM_ASSIST_B_RESET 0x1 +#define NV4_PGRAPH_DMA_RM_WRITE_REQ 4 +#define NV4_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x0 +#define NV4_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x1 +#define NV4_PGRAPH_DMA_A_XLATE_INST 0x401040 +#define NV4_PGRAPH_DMA_A_XLATE_INST_VALUE 0 +#define NV4_PGRAPH_DMA_A_CONTROL 0x401044 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x1 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x1 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE 16 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x0 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x2 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x3 +#define NV4_PGRAPH_DMA_A_CONTROL_ADJUST 20 +#define NV4_PGRAPH_DMA_A_LIMIT 0x401048 +#define NV4_PGRAPH_DMA_A_LIMIT_OFFSET 0 +#define NV4_PGRAPH_DMA_A_TLB_PTE 0x40104C +#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS 1 +#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x0 +#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x1 +#define NV4_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 12 +#define NV4_PGRAPH_DMA_A_TLB_TAG 0x401050 +#define NV4_PGRAPH_DMA_A_TLB_TAG_ADDRESS 12 +#define NV4_PGRAPH_DMA_A_ADJ_OFFSET 0x401054 +#define NV4_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_A_OFFSET 0x401058 +#define NV4_PGRAPH_DMA_A_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_A_SIZE 0x40105C +#define NV4_PGRAPH_DMA_A_SIZE_VALUE 0 +#define NV4_PGRAPH_DMA_A_Y_SIZE 0x401060 +#define NV4_PGRAPH_DMA_A_Y_SIZE_VALUE 0 +#define NV4_PGRAPH_DMA_B_XLATE_INST 0x401080 +#define NV4_PGRAPH_DMA_B_XLATE_INST_VALUE 0 +#define NV4_PGRAPH_DMA_B_CONTROL 0x401084 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x1 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x1 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE 16 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x0 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x2 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x3 +#define NV4_PGRAPH_DMA_B_CONTROL_ADJUST 20 +#define NV4_PGRAPH_DMA_B_LIMIT 0x401088 +#define NV4_PGRAPH_DMA_B_LIMIT_OFFSET 0 +#define NV4_PGRAPH_DMA_B_TLB_PTE 0x40108C +#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS 1 +#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x0 +#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x1 +#define NV4_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 12 +#define NV4_PGRAPH_DMA_B_TLB_TAG 0x401090 +#define NV4_PGRAPH_DMA_B_TLB_TAG_ADDRESS 12 +#define NV4_PGRAPH_DMA_B_ADJ_OFFSET 0x401094 +#define NV4_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_B_OFFSET 0x401098 +#define NV4_PGRAPH_DMA_B_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_B_SIZE 0x40109C +#define NV4_PGRAPH_DMA_B_SIZE_VALUE 0 +#define NV4_PGRAPH_DMA_B_Y_SIZE 0x4010A0 +#define NV4_PGRAPH_DMA_B_Y_SIZE_VALUE 0 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR 0 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_ZOH_MS 0x0 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_ZOH 0x1 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_FOH 0x2 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U 4 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_CYLINDRICAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_WRAP 0x1 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_MIRROR 0x2 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_CLAMP 0x3 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V 6 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_CYLINDRICAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_WRAP 0x1 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_MIRROR 0x2 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_CLAMP 0x3 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT 8 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT_LE_X8R8G8B8 0x0 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT_LE_A8R8G8B8 0x1 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR 10 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_NORMAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_COLOR_INVERSE 0x1 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_ALPHA_INVERSE 0x2 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_ALPHA_ONE 0x3 +#define NV4_PGRAPH_CONTROL_OUT_CULLING 12 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_ILLEGAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_NONE 0x1 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_COUNTERCLOCKWISE 0x2 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_CLOCKWISE 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER 15 +#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER_SCREEN 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER_LINEAR 0x1 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE 16 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_ILLEGAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_FALSE 0x1 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_LT 0x2 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_EQ 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_LE 0x4 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_GT 0x5 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_NE 0x6 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_GE 0x7 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_TRUE 0x8 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE 20 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_NEVER 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALPHA 0x1 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALPHA_ZETA 0x2 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ZETA 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALWAYS 0x4 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE 24 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_NEVER 0x0 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ALPHA 0x1 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ALPHA_ZETA 0x2 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ZETA 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ROP 28 +#define NV4_PGRAPH_CONTROL_OUT_ROP_BLEND_AND 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ROP_ADD_WITH_SATURATION 0x1 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA 29 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA_SRCALPHA 0x0 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA_DESTCOLOR 0x1 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0 30 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0_DESTCOLOR 0x0 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0_ZERO 0x1 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1 31 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1_SRCCOLOR 0x0 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1_ZERO 0x1 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_KEY 0 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE 8 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_ILLEGAL 0x0 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_FALSE 0x1 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_LT 0x2 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_EQ 0x3 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_LE 0x4 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_GT 0x5 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_NE 0x6 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_GE 0x7 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_TRUE 0x8 + +#define NV4_PVIDEO_START 0x680000 +#define NV4_PVIDEO_END 0x6802FF + +#define NV4_PVIDEO_INTR_0 0x680100 +#define NV4_PVIDEO_INTR_0_NOTIFY 0 +#define NV4_PVIDEO_INTR_0_NOTIFY_NOT_PENDING 0x0 +#define NV4_PVIDEO_INTR_0_NOTIFY_PENDING 0x1 +#define NV4_PVIDEO_INTR_0_NOTIFY_RESET 0x1 +#define NV4_PVIDEO_INTR_EN_0 0x680140 +#define NV4_PVIDEO_INTR_EN_0_NOTIFY 0 +#define NV4_PVIDEO_INTR_EN_0_NOTIFY_ENABLED 0x1 +#define NV4_PVIDEO_STEP_SIZE 0x680200 +#define NV4_PVIDEO_STEP_SIZE_X 0 +#define NV4_PVIDEO_STEP_SIZE_Y 16 +#define NV4_PVIDEO_CONTROL_Y 0x680204 +#define NV4_PVIDEO_CONTROL_Y_BLUR 0 +#define NV4_PVIDEO_CONTROL_Y_BLUR_OFF 0x0 +#define NV4_PVIDEO_CONTROL_Y_BLUR_ON 0x1 +#define NV4_PVIDEO_CONTROL_Y_LINE 4 +#define NV4_PVIDEO_CONTROL_Y_LINE_HALF 0x0 +#define NV4_PVIDEO_CONTROL_Y_LINE_FULL 0x1 +#define NV4_PVIDEO_CONTROL_X 0x680208 +#define NV4_PVIDEO_CONTROL_X_WEIGHT 0 +#define NV4_PVIDEO_CONTROL_X_WEIGHT_LIGHT 0x0 +#define NV4_PVIDEO_CONTROL_X_WEIGHT_HEAVY 0x1 +#define NV4_PVIDEO_CONTROL_X_SHARPENING 4 +#define NV4_PVIDEO_CONTROL_X_SHARPENING_OFF 0x0 +#define NV4_PVIDEO_CONTROL_X_SHARPENING_ON 0x1 +#define NV4_PVIDEO_CONTROL_X_SMOOTHING 8 +#define NV4_PVIDEO_CONTROL_X_SMOOTHING_OFF 0x0 +#define NV4_PVIDEO_CONTROL_X_SMOOTHING_ON 0x1 +#define NV4_PVIDEO_BUFF0_START 0x68020c +#define NV4_PVIDEO_BUFF0_START_ADDRESS 2 +#define NV4_PVIDEO_BUFF1_START 0x680210 +#define NV4_PVIDEO_BUFF1_START_ADDRESS 2 +#define NV4_PVIDEO_BUFF0_PITCH 0x680214 +#define NV4_PVIDEO_BUFF0_PITCH_LENGTH 4 +#define NV4_PVIDEO_BUFF1_PITCH 0x680218 +#define NV4_PVIDEO_BUFF1_PITCH_LENGTH 4 +#define NV4_PVIDEO_BUFF0_OFFSET 0x68021c +#define NV4_PVIDEO_BUFF0_OFFSET_X 0 +#define NV4_PVIDEO_BUFF0_OFFSET_Y 4 +#define NV4_PVIDEO_BUFF0_OFFSET_Y_OFF 0x0 +#define NV4_PVIDEO_BUFF0_OFFSET_Y_QUARTER 0x1 +#define NV4_PVIDEO_BUFF0_OFFSET_Y_HALF 0x2 +#define NV4_PVIDEO_BUFF1_OFFSET 0x680220 +#define NV4_PVIDEO_BUFF1_OFFSET_X 0 +#define NV4_PVIDEO_BUFF1_OFFSET_Y 4 +#define NV4_PVIDEO_BUFF1_OFFSET_Y_OFF 0x0 +#define NV4_PVIDEO_BUFF1_OFFSET_Y_QUARTER 0x1 +#define NV4_PVIDEO_BUFF1_OFFSET_Y_HALF 0x2 +#define NV4_PVIDEO_OE_STATE 0x680224 +#define NV4_PVIDEO_OE_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PVIDEO_OE_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PVIDEO_OE_STATE_BUFF0_ERROR 8 +#define NV4_PVIDEO_OE_STATE_BUFF1_ERROR 12 +#define NV4_PVIDEO_OE_STATE_BUFF0_IN_USE 16 +#define NV4_PVIDEO_OE_STATE_BUFF1_IN_USE 20 +#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER 24 +#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PVIDEO_SU_STATE 0x680228 +#define NV4_PVIDEO_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PVIDEO_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PVIDEO_RM_STATE 0x68022c +#define NV4_PVIDEO_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PVIDEO_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PVIDEO_WINDOW_START 0x680230 +#define NV4_PVIDEO_WINDOW_START_X 0 +#define NV4_PVIDEO_WINDOW_START_Y 16 +#define NV4_PVIDEO_WINDOW_SIZE 0x680234 +#define NV4_PVIDEO_WINDOW_SIZE_X 0 +#define NV4_PVIDEO_WINDOW_SIZE_Y 16 +#define NV4_PVIDEO_FIFO_THRES 0x680238 +#define NV4_PVIDEO_FIFO_THRES_SIZE 3 +#define NV4_PVIDEO_FIFO_BURST 0x68023c +#define NV4_PVIDEO_FIFO_BURST_LENGTH 0 +#define NV4_PVIDEO_FIFO_BURST_LENGTH_32 0x1 +#define NV4_PVIDEO_FIFO_BURST_LENGTH_64 0x2 +#define NV4_PVIDEO_FIFO_BURST_LENGTH_128 0x3 +#define NV4_PVIDEO_KEY 0x680240 +#define NV4_PVIDEO_KEY_INDEX 0 +#define NV4_PVIDEO_KEY_565 0 +#define NV4_PVIDEO_KEY_555 0 +#define NV4_PVIDEO_KEY_888 0 +#define NV4_PVIDEO_KEY_PACK 24 +#define NV4_PVIDEO_OVERLAY 0x680244 +#define NV4_PVIDEO_OVERLAY_VIDEO 0 +#define NV4_PVIDEO_OVERLAY_VIDEO_OFF 0x0 +#define NV4_PVIDEO_OVERLAY_VIDEO_ON 0x1 +#define NV4_PVIDEO_OVERLAY_KEY 4 +#define NV4_PVIDEO_OVERLAY_KEY_OFF 0x0 +#define NV4_PVIDEO_OVERLAY_KEY_ON 0x1 +#define NV4_PVIDEO_OVERLAY_FORMAT 8 +#define NV4_PVIDEO_OVERLAY_FORMAT_CCIR 0x0 +#define NV4_PVIDEO_OVERLAY_FORMAT_YUY2 0x1 +#define NV4_PVIDEO_RED_CSC 0x680280 +#define NV4_PVIDEO_RED_CSC_OFFSET 0 +#define NV4_PVIDEO_GREEN_CSC 0x680284 +#define NV4_PVIDEO_GREEN_CSC_OFFSET 0 +#define NV4_PVIDEO_BLUE_CSC 0x680288 +#define NV4_PVIDEO_BLUE_CSC_OFFSET 0 +#define NV4_PVIDEO_CSC_ADJUST 0x68028c +#define NV4_PVIDEO_CSC_ADJUST_B_FLAG 0 +#define NV4_PVIDEO_CSC_ADJUST_B_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_B_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_G_FLAG 4 +#define NV4_PVIDEO_CSC_ADJUST_G_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_G_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_R_FLAG 8 +#define NV4_PVIDEO_CSC_ADJUST_R_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_R_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_L_FLAG 12 +#define NV4_PVIDEO_CSC_ADJUST_L_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_L_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_CHROMA 16 +#define NV4_PVIDEO_CSC_ADJUST_CHROMA_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_CHROMA_ON 0x1 + +#define NV4_PRMCIO_START 0x601000 +#define NV4_PRMCIO_END 0x601FFF + +#define NV4_PRMCIO_INP0 0x6013c2 +#define NV4_PRMCIO_INP0_MONO 0x6013ba +#define NV4_PRMCIO_INP0_COLOR 0x6013da +#define NV4_PRMCIO_INP0_READ_MONO 0x6013ca +#define NV4_PRMCIO_INP0_WRITE_MONO 0x6013ba +#define NV4_PRMCIO_INP0_WRITE_COLOR 0x6013da +// DEFAULT = Palette +#define NV4_PRMCIO_ARX 0x6013c0 +#define NV4_PRMCIO_AR_WRITE 0x6013c0 // After ARX +#define NV4_PRMCIO_AR_READ 0x6013c1 +#define NV4_PRMCIO_AR_PALETTE_WRITE 0x6013c0 +#define NV4_PRMCIO_AR_PALETTE_READ 0x6013c1 +#define NV4_PRMCIO_AR_MODE_INDEX 0x10 +#define NV4_PRMCIO_AR_OSCAN_INDEX 0x11 +#define NV4_PRMCIO_AR_PLANE_INDEX 0x12 +#define NV4_PRMCIO_AR_HPP_INDEX 0x13 +#define NV4_PRMCIO_AR_CSEL_INDEX 0x14 +#define NV4_PRMCIO_CRX_MONO 0x6013b4 +#define NV4_PRMCIO_CRX_COLOR 0x6013d4 +#define NV4_PRMCIO_CR_MONO 0x6013b5 +#define NV4_PRMCIO_CR_COLOR 0x6013d5 +#define NV4_PRMCIO_CRE_MONO 0x6013b5 +#define NV4_PRMCIO_CRE_COLOR 0x6013d5 + +#define NV4_PCRTC_INTR_0 0x600100 +#define NV4_PCRTC_INTR_0_VBLANK 0 +#define NV4_PCRTC_INTR_0_VBLANK_NOT_PENDING 0x0 +#define NV4_PCRTC_INTR_0_VBLANK_PENDING 0x1 +#define NV4_PCRTC_INTR_0_VBLANK_RESET 0x1 +#define NV4_PCRTC_INTR_EN_0 0x600140 +#define NV4_PCRTC_INTR_EN_0_VBLANK 0 +#define NV4_PCRTC_INTR_EN_0_VBLANK_ENABLED 0x1 +#define NV4_PCRTC_START 0x600800 +#define NV4_PCRTC_START_ADDRESS 2 +#define NV4_PCRTC_CONFIG 0x600804 +#define NV4_PCRTC_CONFIG_START_ADDRESS 0 +#define NV4_PCRTC_CONFIG_START_ADDRESS_VGA 0x0 +#define NV4_PCRTC_CONFIG_START_ADDRESS_NON_VGA 0x1 +#define NV4_PCRTC_CONFIG_START_ADDRESS_HSYNC 0x2 +#define NV4_PCRTC_RASTER 0x600808 +#define NV4_PCRTC_RASTER_POSITION 0 +#define NV4_PCRTC_RASTER_SA_LOAD 12 +#define NV4_PCRTC_RASTER_SA_LOAD_DISPLAY 0x0 +#define NV4_PCRTC_RASTER_SA_LOAD_BEFORE 0x1 +#define NV4_PCRTC_RASTER_SA_LOAD_AFTER 0x2 +#define NV4_PCRTC_RASTER_VERT_BLANK 16 +#define NV4_PCRTC_RASTER_VERT_BLANK_ACTIVE 0x1 +#define NV4_PCRTC_RASTER_VERT_BLANK_INACTIVE 0x0 + +#define NV4_CIO_START 0x3B0 +#define NV4_CIO_END 0x3DF + + +#define NV4_CIO_INP0 0x3c2 +#define NV4_CIO_INP0_MONO 0x3ba +#define NV4_CIO_INP0_COLOR 0x3da +#define NV4_CIO_INP0_READ_MONO 0x3ca +#define NV4_CIO_INP0_WRITE_MONO 0x3ba +#define NV4_CIO_INP0_WRITE_COLOR 0x3da +#define NV4_CIO_ARX 0x3c0 // if index is not 0x10-0x13 write palette +#define NV4_CIO_AR_PALETTE_WRITE 0x3c0 +#define NV4_CIO_AR_PALETTE_READ 0x3c1 +#define NV4_CIO_AR_MODE_WRITE 0x3c0 +#define NV4_CIO_AR_MODE_READ 0x3c1 +#define NV4_CIO_AR_MODE_INDEX 0x10 +#define NV4_CIO_AR_OSCAN_WRITE 0x3c0 +#define NV4_CIO_AR_OSCAN_READ 0x3c1 +#define NV4_CIO_AR_OSCAN_INDEX 0x11 +#define NV4_CIO_AR_PLANE_WRITE 0x3c0 +#define NV4_CIO_AR_PLANE_READ 0x3c1 +#define NV4_CIO_AR_PLANE_INDEX 0x12 +#define NV4_CIO_AR_HPP_WRITE 0x3c0 +#define NV4_CIO_AR_HPP_READ 0x3c1 +#define NV4_CIO_AR_HPP_INDEX 0x13 +#define NV4_CIO_AR_CSEL_WRITE 0x3c0 +#define NV4_CIO_AR_CSEL_READ 0x3c1 +#define NV4_CIO_AR_CSEL_INDEX 0x14 +#define NV4_CIO_CRX_MONO 0x3b4 +#define NV4_CIO_CRX_COLOR 0x3d4 +#define NV4_CIO_CR_MONO 0x3b5 +#define NV4_CIO_CR_COLOR 0x3d5 +#define NV4_CIO_CR_HDT_INDEX 0x0 +#define NV4_CIO_CR_HDE_INDEX 0x1 +#define NV4_CIO_CR_HBS_INDEX 0x2 +#define NV4_CIO_CR_HBE_INDEX 0x3 +#define NV4_CIO_CR_HBE_4_0 0 +#define NV4_CIO_CR_HRS_INDEX 0x4 +#define NV4_CIO_CR_HRE_INDEX 0x5 +#define NV4_CIO_CR_HRE_HBE_5 7 +#define NV4_CIO_CR_HRE_4_0 0 +#define NV4_CIO_CR_VDT_INDEX 0x6 +#define NV4_CIO_CR_OVL_INDEX 0x7 +#define NV4_CIO_CR_OVL_VDE_8 1 +#define NV4_CIO_CR_OVL_VDE_9 6 +#define NV4_CIO_CR_OVL_VDT_8 0 +#define NV4_CIO_CR_OVL_VDT_9 5 +#define NV4_CIO_CR_OVL_VBS_8 3 +#define NV4_CIO_CR_OVL_VRS_8 2 +#define NV4_CIO_CR_OVL_VRS_9 7 +#define NV4_CIO_CR_RSAL_INDEX 0x8 +#define NV4_CIO_CR_RSAL_PANNING 5 +#define NV4_CIO_CR_CELL_HT_INDEX 0x9 +#define NV4_CIO_CR_CELL_HT_SCANDBL 7 +#define NV4_CIO_CR_CELL_HT_VBS_9 5 +#define NV4_CIO_CR_CURS_ST_INDEX 0xA +#define NV4_CIO_CR_CURS_END_INDEX 0xB +#define NV4_CIO_CR_SA_HI_INDEX 0xC +#define NV4_CIO_CR_SA_LO_INDEX 0xD +#define NV4_CIO_CR_TCOFF_HI_INDEX 0xE +#define NV4_CIO_CR_TCOFF_LO_INDEX 0xF +#define NV4_CIO_CR_VRS_INDEX 0x10 +#define NV4_CIO_CR_VRE_INDEX 0x11 +#define NV4_CIO_CR_VRE_3_0 0 +#define NV4_CIO_CR_VDE_INDEX 0x12 +#define NV4_CIO_CR_OFFSET_INDEX 0x13 +#define NV4_CIO_CR_ULINE_INDEX 0x14 +#define NV4_CIO_CR_VBS_INDEX 0x15 +#define NV4_CIO_CR_VBE_INDEX 0x16 +#define NV4_CIO_CR_MODE_INDEX 0x17 +#define NV4_CIO_CR_LCOMP_INDEX 0x18 +#define NV4_CIO_CR_GDATA_INDEX 0x22 +#define NV4_CIO_CR_ARFF_INDEX 0x24 +#define NV4_CIO_CR_ARX_INDEX 0x26 +#define NV4_CIO_CRE_MONO 0x3b5 +#define NV4_CIO_CRE_COLOR 0x3d5 +#define NV4_CIO_CRE_RPC0_INDEX 0x19 +#define NV4_CIO_CRE_RPC0_START 0 +#define NV4_CIO_CRE_RPC0_OFFSET_10_8 5 +#define NV4_CIO_CRE_RPC1_INDEX 0x1A +#define NV4_CIO_CRE_RPC1_LARGE 2 +#define NV4_CIO_CRE_FF_INDEX 0x1B +#define NV4_CIO_CRE_FF_BURST 0 +#define NV4_CIO_CRE_FF_BURST_8 0x0 +#define NV4_CIO_CRE_FF_BURST_32 0x1 +#define NV4_CIO_CRE_FF_BURST_64 0x2 +#define NV4_CIO_CRE_FF_BURST_128 0x3 +#define NV4_CIO_CRE_FF_BURST_256 0x4 +#define NV4_CIO_CRE_ENH_INDEX 0x1C +#define NV4_CIO_CRE_PAGE0_INDEX 0x1D +#define NV4_CIO_CRE_PAGE1_INDEX 0x1E +#define NV4_CIO_SR_LOCK_INDEX 0x1F +#define NV4_CIO_SR_UNLOCK_RW_VALUE 0x57 +#define NV4_CIO_SR_UNLOCK_RO_VALUE 0x75 +#define NV4_CIO_SR_LOCK_VALUE 0x99 +#define NV4_SR_UNLOCK_RW_VALUE 0x57 +#define NV4_SR_UNLOCK_RO_VALUE 0x75 +#define NV4_SR_LOCK_VALUE 0x99 +#define NV4_CIO_CRE_FFLWM_INDEX 0x20 +#define NV4_CIO_CRE_FFLWM_LWM 0 +#define NV4_CIO_CRE_FABID_INDEX 0x25 +#define NV4_CIO_CRE_LSR_INDEX 0x25 +#define NV4_CIO_CRE_LSR_VDE_10 1 +#define NV4_CIO_CRE_LSR_VDT_10 0 +#define NV4_CIO_CRE_LSR_HBE_6 4 +#define NV4_CIO_CRE_LSR_VBS_10 3 +#define NV4_CIO_CRE_LSR_VRS_10 2 +#define NV4_CIO_CRE_CHIP_ID_INDEX 0x27 +#define NV4_CIO_CRE_PIXEL_INDEX 0x28 +#define NV4_CIO_CRE_PIXEL_TV_ADJ 3 +#define NV4_CIO_CRE_PIXEL_FORMAT 0 +#define NV4_CIO_CRE_PIXEL_FORMAT_VGA 0x0 +#define NV4_CIO_CRE_PIXEL_FORMAT_8BPP 0x1 +#define NV4_CIO_CRE_PIXEL_FORMAT_16BPP 0x2 +#define NV4_CIO_CRE_PIXEL_FORMAT_32BPP 0x3 +#define NV4_CIO_CRE_PAGE_OVFL_INDEX 0x29 +#define NV4_CIO_CRE_OSCOL_INDEX 0x2A +#define NV4_CIO_CRE_SCRATCH0_INDEX 0x2B +#define NV4_CIO_CRE_SCRATCH1_INDEX 0x2C +#define NV4_CIO_CRE_HEB_INDEX 0x2D +#define NV4_CIO_CRE_HEB_SA_23 5 +#define NV4_CIO_CRE_HEB_ILC_8 4 +#define NV4_CIO_CRE_HEB_HRS_8 3 +#define NV4_CIO_CRE_HEB_HBS_8 2 +#define NV4_CIO_CRE_HEB_HDE_8 1 +#define NV4_CIO_CRE_HEB_HDT_8 0 +#define NV4_CIO_CRE_HCUR_ADDR2_INDEX 0x2f +#define NV4_CIO_CRE_HCUR_ADDR0_INDEX 0x30 +#define NV4_CIO_CRE_HCUR_ASI 7 +#define NV4_CIO_CRE_HCUR_ASI_FRAMEBUFFER 0x1 +#define NV4_CIO_CRE_HCUR_ASI_INSTMEM 0x0 +#define NV4_CIO_CRE_HCUR_ADDR0_ADR 0 +#define NV4_CIO_CRE_HCUR_ADDR1_INDEX 0x31 +#define NV4_CIO_CRE_HCUR_ADDR1_ADR 2 +#define NV4_CIO_CRE_HCUR_ADDR1_CUR_DBL 1 +#define NV4_CIO_CRE_HCUR_ADDR1_ENABLE 0 +#define NV4_CIO_CRE_VID_END0_INDEX 0x32 +#define NV4_CIO_CRE_VID_END_7_0 0 +#define NV4_CIO_CRE_VID_END1_INDEX 0x33 +#define NV4_CIO_CRE_VID_END_ENABLE 4 +#define NV4_CIO_CRE_VID_END_10_8 0 +#define NV4_CIO_CRE_RL0_INDEX 0x34 +#define NV4_CIO_CRE_RL1_INDEX 0x35 +#define NV4_CIO_CRE_RMA_INDEX 0x38 +#define NV4_CIO_CRE_ILACE_INDEX 0x39 +#define NV4_CIO_CRE_SCRATCH2_INDEX 0x3A +#define NV4_CIO_CRE_SCRATCH3_INDEX 0x3B +#define NV4_CIO_CRE_SCRATCH4_INDEX 0x3C +#define NV4_CIO_CRE_TREG_INDEX 0x3D +#define NV4_CIO_CRE_TREG_HCNT 6 +#define NV4_CIO_CRE_TREG_VCNT 4 +#define NV4_CIO_CRE_TREG_SHADOW 0 +#define NV4_CIO_CRE_TREG_HCNT_INDEX 0x0 +#define NV4_CIO_CRE_TREG_VCNTA_INDEX 0x6 +#define NV4_CIO_CRE_TREG_VCNTB_INDEX 0x7 +#define NV4_CIO_CRE_DDC_STATUS_INDEX 0x3E +#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F +#define NV4_CIO_CRE_PCI_TO_INDEX 0x40 +#define NV4_CIO_CRE_PCI_TO_DELAY 0 + +#define NV4_VIO_MBEN 0x94 +#define NV4_VIO_ADDEN 0x46e8 +#define NV4_VIO_VSE1 0x102 +#define NV4_VIO_VSE2 0x3c3 +#define NV4_VIO_MISC_READ 0x3cc +#define NV4_VIO_MISC_WRITE 0x3c2 +#define NV4_VIO_SRX 0x3c4 +#define NV4_VIO_SR 0x3c5 +#define NV4_VIO_SR_RESET_INDEX 0x0 +#define NV4_VIO_SR_CLOCK_INDEX 0x1 +#define NV4_VIO_SR_PLANE_MASK_INDEX 0x2 +#define NV4_VIO_SR_CHAR_MAP_INDEX 0x3 +#define NV4_VIO_SR_MEM_MODE_INDEX 0x4 +#define NV4_VIO_GRX 0x3ce +#define NV4_VIO_GX_SR 0x3cf +#define NV4_VIO_GX_SR_INDEX 0x0 +#define NV4_VIO_GX_SREN_INDEX 0x1 +#define NV4_VIO_GX_CCOMP_INDEX 0x2 +#define NV4_VIO_GX_ROP_INDEX 0x3 +#define NV4_VIO_GX_READ_MAP_INDEX 0x4 +#define NV4_VIO_GX_MODE_INDEX 0x5 +#define NV4_VIO_GX_MISC_INDEX 0x6 +#define NV4_VIO_GX_DONT_CARE_INDEX 0x7 +#define NV4_VIO_GX_BIT_MASK_INDEX 0x8 + +#define NV4_PRMVIO_START 0xC0000 +#define NV4_PRMVIO_END 0xC7FFF + +#define NV4_PRMVIO_MBEN 0xC0094 +#define NV4_PRMVIO_ADDEN 0xC46e8 +#define NV4_PRMVIO_VSE1 0xC0102 +#define NV4_PRMVIO_VSE2 0xC03c3 +#define NV4_PRMVIO_MISC_READ 0xC03cc +#define NV4_PRMVIO_MISC_WRITE 0xC03c2 +#define NV4_PRMVIO_SRX 0xC03c4 +#define NV4_PRMVIO_SR_RESET 0xC03c5 +#define NV4_PRMVIO_SR_RESET_INDEX 0x0 +#define NV4_PRMVIO_SR_CLOCK_INDEX 0x1 +#define NV4_PRMVIO_SR_PLANE_MASK_INDEX 0x2 +#define NV4_PRMVIO_SR_CHAR_MAP_INDEX 0x3 +#define NV4_PRMVIO_SR_MEM_MODE_INDEX 0x4 +#define NV4_PRMVIO_GX_SR 0xC03cf +#define NV4_PRMVIO_GX_SR_INDEX 0x0 +#define NV4_PRMVIO_GX_SREN_INDEX 0x1 +#define NV4_PRMVIO_GX_CCOMP_INDEX 0x2 +#define NV4_PRMVIO_GX_ROP_INDEX 0x3 +#define NV4_PRMVIO_GX_READ_MAP_INDEX 0x4 +#define NV4_PRMVIO_GX_MODE_INDEX 0x5 +#define NV4_PRMVIO_GX_MISC_INDEX 0x6 +#define NV4_PRMVIO_GX_DONT_CARE_INDEX 0x7 +#define NV4_PRMVIO_GX_BIT_MASK_INDEX 0x8 + +#define NV4_PRMVGA 0xA0000 +#define NV4_PRMVGA_END 0xBFFFF + +#define NV4_PME 0x200FFF:0x200000 +#define NV4_PME_DEBUG_0 0x200080 +#define NV4_PME_DEBUG_0_DET_FIELD_SWITCH 0 +#define NV4_PME_DEBUG_0_DET_FIELD_SWITCH_ENABLED 0x1 +#define NV4_PME_DEBUG_0_CAPTURE_00_FF 4 +#define NV4_PME_DEBUG_0_CAPTURE_00_FF_ENABLED 0x1 +#define NV4_PME_DEBUG_1 0x200084 +#define NV4_PME_DEBUG_1_SEL 0 +#define NV4_PME_DEBUG_1_SEL_VIPCLK 0x0 +#define NV4_PME_DEBUG_1_SEL_MCLK 0x1 +#define NV4_PME_DEBUG_1_SEL_GLOB 0x2 +#define NV4_PME_DEBUG_1_VIPCLK_SEL 4 +#define NV4_PME_DEBUG_1_VIPCLK_SEL_DEFAULT 0x0 +#define NV4_PME_DEBUG_1_MCLK_SEL 8 +#define NV4_PME_DEBUG_1_MCLK_SEL_DEFAULT 0x0 +#define NV4_PME_INTR_0 0x200100 +#define NV4_PME_INTR_0_IMAGE_NOTIFY 0 +#define NV4_PME_INTR_0_IMAGE_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_IMAGE_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_IMAGE_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_VBI_NOTIFY 4 +#define NV4_PME_INTR_0_VBI_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_VBI_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_VBI_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_VID_NOTIFY 8 +#define NV4_PME_INTR_0_VID_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_VID_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_VID_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_AUD_NOTIFY 12 +#define NV4_PME_INTR_0_AUD_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_AUD_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_AUD_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_VMI 16 +#define NV4_PME_INTR_0_VMI_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_VMI_PENDING 0x1 +#define NV4_PME_INTR_0_VMI_RESET 0x1 +#define NV4_PME_INTR_EN_0 0x200140 +#define NV4_PME_INTR_EN_0_IMAGE_NOTIFY 0 +#define NV4_PME_INTR_EN_0_IMAGE_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_VBI_NOTIFY 4 +#define NV4_PME_INTR_EN_0_VBI_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_VID_NOTIFY 8 +#define NV4_PME_INTR_EN_0_VID_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_AUD_NOTIFY 12 +#define NV4_PME_INTR_EN_0_AUD_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_VMI 16 +#define NV4_PME_INTR_EN_0_VMI_ENABLED 0x1 +#define NV4_PME_CONFIG_0 0x200200 +#define NV4_PME_CONFIG_0_BUS_MODE 0 +#define NV4_PME_CONFIG_0_BUS_MODE_DISABLED 0x0 +#define NV4_PME_CONFIG_0_BUS_MODE_VMI 0x1 +#define NV4_PME_CONFIG_0_BUS_MODE_CCIR656 0x2 +#define NV4_PME_CONFIG_0_IMAGE 4 +#define NV4_PME_CONFIG_0_IMAGE_ENABLED 0x1 +#define NV4_PME_CONFIG_0_VBI_MODE 8 +#define NV4_PME_CONFIG_0_VBI_MODE_DISABLED 0x0 +#define NV4_PME_CONFIG_0_VBI_MODE_1 0x1 +#define NV4_PME_CONFIG_0_VBI_MODE_2 0x2 +#define NV4_PME_CONFIG_0_VID_CD 12 +#define NV4_PME_CONFIG_0_VID_CD_ENABLED 0x1 +#define NV4_PME_CONFIG_0_AUD_CD 16 +#define NV4_PME_CONFIG_0_AUD_CD_ENABLED 0x1 +#define NV4_PME_CONFIG_1 0x200204 +#define NV4_PME_CONFIG_1_BUFFS 0 +#define NV4_PME_CONFIG_1_BUFFS_PNVM 0x0 +#define NV4_PME_CONFIG_1_BUFFS_SYS 0x1 +#define NV4_PME_CONFIG_1_HOST 4 +#define NV4_PME_CONFIG_1_HOST_PCI 0x0 +#define NV4_PME_CONFIG_1_HOST_AGP 0x1 +#define NV4_PME_NULL_DATA 0x200208 +#define NV4_PME_NULL_DATA_COMPARE 0 +#define NV4_PME_NULL_DATA_COMPARE_ENABLED 0x1 +#define NV4_PME_NULL_DATA_LINE_DETECT 4 +#define NV4_PME_NULL_DATA_LINE_DETECT_ENABLED 0x1 +#define NV4_PME_NULL_DATA_BYTE 24 +#define NV4_PME_VID_BUFF0_START_SYS 0x200300 +#define NV4_PME_VID_BUFF0_START_SYS_ADDRESS 4 +#define NV4_PME_VID_BUFF1_START_SYS 0x200304 +#define NV4_PME_VID_BUFF1_START_SYS_ADDRESS 4 +#define NV4_PME_VID_BUFF0_START_PNVM 0x200308 +#define NV4_PME_VID_BUFF0_START_PNVM_ADDRESS 4 +#define NV4_PME_VID_BUFF1_START_PNVM 0x20030c +#define NV4_PME_VID_BUFF1_START_PNVM_ADDRESS 4 +#define NV4_PME_VID_BUFF0_LENGTH 0x200310 +#define NV4_PME_VID_BUFF0_LENGTH_BITS 12 +#define NV4_PME_VID_BUFF1_LENGTH 0x200314 +#define NV4_PME_VID_BUFF1_LENGTH_BITS 12 +#define NV4_PME_VID_ME_STATE 0x200318 +#define NV4_PME_VID_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VID_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VID_ME_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_VID_ME_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_VID_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VID_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_VID_SU_STATE 0x20031c +#define NV4_PME_VID_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VID_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VID_RM_STATE 0x200320 +#define NV4_PME_VID_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VID_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VID_RM_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_VID_RM_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_VID_CURRENT 0x200324 +#define NV4_PME_VID_CURRENT_POS 2 +#define NV4_PME_AUD_BUFF0_START_SYS 0x200340 +#define NV4_PME_AUD_BUFF0_START_SYS_ADDRESS 4 +#define NV4_PME_AUD_BUFF1_START_SYS 0x200344 +#define NV4_PME_AUD_BUFF1_START_SYS_ADDRESS 4 +#define NV4_PME_AUD_BUFF0_START_PNVM 0x200348 +#define NV4_PME_AUD_BUFF0_START_PNVM_ADDRESS 4 +#define NV4_PME_AUD_BUFF1_START_PNVM 0x20034c +#define NV4_PME_AUD_BUFF1_START_PNVM_ADDRESS 4 +#define NV4_PME_AUD_BUFF0_LENGTH 0x200350 +#define NV4_PME_AUD_BUFF0_LENGTH_BITS 10 +#define NV4_PME_AUD_BUFF1_LENGTH 0x200354 +#define NV4_PME_AUD_BUFF1_LENGTH_BITS 10 +#define NV4_PME_AUD_ME_STATE 0x200358 +#define NV4_PME_AUD_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_AUD_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_AUD_ME_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_AUD_ME_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_AUD_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_AUD_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_AUD_SU_STATE 0x20035c +#define NV4_PME_AUD_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_AUD_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_AUD_RM_STATE 0x200360 +#define NV4_PME_AUD_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_AUD_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_AUD_RM_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_AUD_RM_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_AUD_CURRENT 0x200364 +#define NV4_PME_AUD_CURRENT_POS 2 +#define NV4_PME_VBI_BUFF0_START 0x200380 +#define NV4_PME_VBI_BUFF0_START_ADDRESS 4 +#define NV4_PME_VBI_BUFF1_START 0x200384 +#define NV4_PME_VBI_BUFF1_START_ADDRESS 4 +#define NV4_PME_VBI_BUFF0_PITCH 0x200388 +#define NV4_PME_VBI_BUFF0_PITCH_VALUE 4 +#define NV4_PME_VBI_BUFF1_PITCH 0x20038c +#define NV4_PME_VBI_BUFF1_PITCH_VALUE 4 +#define NV4_PME_VBI_BUFF0_LENGTH 0x200390 +#define NV4_PME_VBI_BUFF0_LENGTH_BITS 4 +#define NV4_PME_VBI_BUFF1_LENGTH 0x200394 +#define NV4_PME_VBI_BUFF1_LENGTH_BITS 4 +#define NV4_PME_VBI_ME_STATE 0x200398 +#define NV4_PME_VBI_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VBI_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VBI_ME_STATE_BUFF0_ERROR_CODE 8 +#define NV4_PME_VBI_ME_STATE_BUFF1_ERROR_CODE 12 +#define NV4_PME_VBI_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VBI_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_VBI_SU_STATE 0x20039c +#define NV4_PME_VBI_SU_STATE_BUFF0_FIELD 8 +#define NV4_PME_VBI_SU_STATE_BUFF1_FIELD 12 +#define NV4_PME_VBI_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VBI_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VBI_RM_STATE 0x2003a0 +#define NV4_PME_VBI_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VBI_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VBI 0x2003a4 +#define NV4_PME_VBI_START_LINE 0 +#define NV4_PME_VBI_NUM_LINES 16 +#define NV4_PME_IMAGE_BUFF0_START 0x200400 +#define NV4_PME_IMAGE_BUFF0_START_ADDRESS 4 +#define NV4_PME_IMAGE_BUFF1_START 0x200404 +#define NV4_PME_IMAGE_BUFF1_START_ADDRESS 4 +#define NV4_PME_IMAGE_BUFF0_PITCH 0x200408 +#define NV4_PME_IMAGE_BUFF0_PITCH_VALUE 4 +#define NV4_PME_IMAGE_BUFF1_PITCH 0x20040c +#define NV4_PME_IMAGE_BUFF1_PITCH_VALUE 4 +#define NV4_PME_IMAGE_BUFF0_LENGTH 0x200410 +#define NV4_PME_IMAGE_BUFF0_LENGTH_BITS 4 +#define NV4_PME_IMAGE_BUFF1_LENGTH 0x200414 +#define NV4_PME_IMAGE_BUFF1_LENGTH_BITS 4 +#define NV4_PME_IMAGE_ME_STATE 0x200418 +#define NV4_PME_IMAGE_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_IMAGE_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_IMAGE_ME_STATE_BUFF0_ERROR_CODE 8 +#define NV4_PME_IMAGE_ME_STATE_BUFF1_ERROR_CODE 12 +#define NV4_PME_IMAGE_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_IMAGE_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_IMAGE_SU_STATE 0x20041c +#define NV4_PME_IMAGE_SU_STATE_BUFF0_FIELD 8 +#define NV4_PME_IMAGE_SU_STATE_BUFF1_FIELD 12 +#define NV4_PME_IMAGE_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_IMAGE_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_IMAGE_RM_STATE 0x200420 +#define NV4_PME_IMAGE_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_IMAGE_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_IMAGE_BUFF0_SCALE_INCR 0x200424 +#define NV4_PME_IMAGE_BUFF0_SCALE_INCR_Y 16 +#define NV4_PME_IMAGE_BUFF0_SCALE_INCR_X 0 +#define NV4_PME_IMAGE_BUFF1_SCALE_INCR 0x200428 +#define NV4_PME_IMAGE_BUFF1_SCALE_INCR_Y 16 +#define NV4_PME_IMAGE_BUFF1_SCALE_INCR_X 0 +#define NV4_PME_IMAGE_Y_CROP 0x20042c +#define NV4_PME_IMAGE_Y_CROP_STARTLINE 0 +#define NV4_PME_FIFO_LINE_START 0x200480 +#define NV4_PME_FIFO_LINE_START_ADDRESS 4 +#define NV4_PME_FIFO_CURRENT 0x200484 +#define NV4_PME_FIFO_CURRENT_ADDRESS 2 +#define NV4_PME_VMI_POLL 0x200488 +#define NV4_PME_VMI_POLL_UNCD 0 +#define NV4_PME_VMI_POLL_UNCD_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_UNCD_PENDING 0x1 +#define NV4_PME_VMI_POLL_VIDCD 1 +#define NV4_PME_VMI_POLL_VIDCD_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_VIDCD_PENDING 0x1 +#define NV4_PME_VMI_POLL_AUDCD 2 +#define NV4_PME_VMI_POLL_AUDCD_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_AUDCD_PENDING 0x1 +#define NV4_PME_VMI_POLL_INT 3 +#define NV4_PME_VMI_POLL_INT_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_INT_PENDING 0x1 +#define NV4_PME_VMI_POLL_CPURDREC 4 +#define NV4_PME_VMI_POLL_CPURDREC_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_CPURDREC_PENDING 0x1 +#define NV4_PME_EXTERNAL(i) (0x200600+(i)*4) +#define NV4_PME_EXTERNAL_SIZE_1 256 +#define NV4_PME_EXTERNAL_DATA 0 + +#define NV4_PFB_START 0x100000 +#define NV4_PFB_END 0x100FFF + +#define NV4_PFB_BOOT_0 0x100000 +#define NV4_PFB_BOOT_0_RAM_AMOUNT 0 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_2MB 0x0 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_4MB 0x1 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_8MB 0x2 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_16MB 0x3 +#define NV4_PFB_BOOT_0_RAM_WIDTH_128 2 +#define NV4_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x0 +#define NV4_PFB_BOOT_0_RAM_WIDTH_128_ON 0x1 +#define NV4_PFB_BOOT_0_RAM_TYPE 3 +#define NV4_PFB_BOOT_0_RAM_TYPE_256K 0x0 +#define NV4_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x1 +#define NV4_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x2 +#define NV4_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x3 +#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x0 +#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x1 +#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x2 +#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x3 +#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x4 +#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x5 +#define NV4_PFB_BOOT_0_UMA 8 +#define NV4_PFB_BOOT_0_UMA_DISABLE 0x0 +#define NV4_PFB_BOOT_0_UMA_ENABLE 0x1 +#define NV4_PFB_BOOT_0_UMA_SIZE 12 +#define NV4_PFB_BOOT_0_UMA_SIZE_DEFAULT 0x7 +#define NV4_PFB_BOOT_0_UMA_SIZE_2M 0x0 +#define NV4_PFB_BOOT_0_UMA_SIZE_4M 0x1 +#define NV4_PFB_BOOT_0_UMA_SIZE_6M 0x2 +#define NV4_PFB_BOOT_0_UMA_SIZE_8M 0x3 +#define NV4_PFB_BOOT_0_UMA_SIZE_10M 0x4 +#define NV4_PFB_BOOT_0_UMA_SIZE_12M 0x5 +#define NV4_PFB_BOOT_0_UMA_SIZE_14M 0x6 +#define NV4_PFB_BOOT_0_UMA_SIZE_16M 0x7 +#define NV4_PFB_BOOT_0_UMA_SIZE_18M 0x8 +#define NV4_PFB_BOOT_0_UMA_SIZE_20M 0x9 +#define NV4_PFB_BOOT_0_UMA_SIZE_22M 0xA +#define NV4_PFB_BOOT_0_UMA_SIZE_24M 0xB +#define NV4_PFB_BOOT_0_UMA_SIZE_26M 0xC +#define NV4_PFB_BOOT_0_UMA_SIZE_28M 0xD +#define NV4_PFB_BOOT_0_UMA_SIZE_30M 0xE +#define NV4_PFB_BOOT_0_UMA_SIZE_32M 0xF +#define NV4_PFB_DEBUG_0 0x100080 +#define NV4_PFB_DEBUG_0_PAGE_MODE 0 +#define NV4_PFB_DEBUG_0_PAGE_MODE_ENABLED 0x0 +#define NV4_PFB_DEBUG_0_PAGE_MODE_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_REFRESH 4 +#define NV4_PFB_DEBUG_0_REFRESH_ENABLED 0x0 +#define NV4_PFB_DEBUG_0_REFRESH_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_REFRESH_COUNTX64 8 +#define NV4_PFB_DEBUG_0_REFRESH_COUNTX64_DEFAULT 0x10 +#define NV4_PFB_DEBUG_0_REFRESH_SLOW_CLK 14 +#define NV4_PFB_DEBUG_0_REFRESH_SLOW_CLK_ENABLED 0x1 +#define NV4_PFB_DEBUG_0_CASOE 20 +#define NV4_PFB_DEBUG_0_CASOE_ENABLED 0x0 +#define NV4_PFB_DEBUG_0_CASOE_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_CKE_INVERT 28 +#define NV4_PFB_DEBUG_0_CKE_INVERT_OFF 0x0 +#define NV4_PFB_DEBUG_0_CKE_INVERT_ON 0x1 +#define NV4_PFB_DEBUG_0_REFINC 29 +#define NV4_PFB_DEBUG_0_REFINC_DISABLED 0x0 +#define NV4_PFB_DEBUG_0_REFINC_ENABLED 0x1 +#define NV4_PFB_DEBUG_0_SAVE_POWER 30 +#define NV4_PFB_DEBUG_0_SAVE_POWER_ON 0x0 +#define NV4_PFB_DEBUG_0_SAVE_POWER_OFF 0x1 +#define NV4_PFB_GREEN_0 0x1000C0 +#define NV4_PFB_GREEN_0_LEVEL 0 +#define NV4_PFB_GREEN_0_LEVEL_VIDEO_ENABLED 0x0 +#define NV4_PFB_GREEN_0_LEVEL_VIDEO_DISABLED 0x1 +#define NV4_PFB_GREEN_0_LEVEL_TIMING_DISABLED 0x2 +#define NV4_PFB_GREEN_0_LEVEL_MEMORY_DISABLED 0x3 +#define NV4_PFB_CONFIG_0 0x100200 +#define NV4_PFB_CONFIG_0_TYPE 0 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x120 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x220 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x320 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x4120 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x4220 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x4320 +#define NV4_PFB_CONFIG_0_TYPE_TETRIS 0x2000 +#define NV4_PFB_CONFIG_0_TYPE_NOTILING 0x1114 +#define NV4_PFB_CONFIG_0_TETRIS_MODE 15 +// 18:15 = tetris mode # +#define NV4_PFB_CONFIG_0_TETRIS_MODE_PASS 0x0 +// 18 = shift # +#define NV4_PFB_CONFIG_0_TETRIS_SHIFT 18 +#define NV4_PFB_CONFIG_0_BANK_SWAP 20 +#define NV4_PFB_CONFIG_0_BANK_SWAP_OFF 0x0 +#define NV4_PFB_CONFIG_0_BANK_SWAP_1M 0x1 +#define NV4_PFB_CONFIG_0_BANK_SWAP_2M 0x5 +#define NV4_PFB_CONFIG_0_BANK_SWAP_4M 0x7 +#define NV4_PFB_CONFIG_0_UNUSED 23 +#define NV4_PFB_CONFIG_0_SCRAMBLE_EN 29 +#define NV4_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x0 +#define NV4_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x1 +#define NV4_PFB_CONFIG_0_PRAMIN_WR 28 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_INIT 0x0 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x1 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK 24 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x0 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0xF +#define NV4_PFB_CONFIG_1 0x100204 +#define NV4_PFB_CONFIG_1_CAS_LATENCY 0 +#define NV4_PFB_CONFIG_1_CAS_LATENCY_3 0x3 +#define NV4_PFB_CONFIG_1_CAS_LATENCY_2 0x2 +#define NV4_PFB_CONFIG_1_CAS_LATENCY_4 0x4 +#define NV4_PFB_CONFIG_1_RAS_RAS 4 +#define NV4_PFB_CONFIG_1_RAS_RAS_DEFAULT 0x9 +#define NV4_PFB_CONFIG_1_RAS_RAS_9CYCLES 0x8 +#define NV4_PFB_CONFIG_1_RAS_RAS_8CYCLES 0x7 +#define NV4_PFB_CONFIG_1_RAS_RAS_7CYCLES 0x6 +#define NV4_PFB_CONFIG_1_RAS_PCHG 8 +#define NV4_PFB_CONFIG_1_RAS_PCHG_DEFAULT 0x2 +#define NV4_PFB_CONFIG_1_RAS_PCHG_2CYCLES 0x1 +#define NV4_PFB_CONFIG_1_RAS_LOW 12 +#define NV4_PFB_CONFIG_1_RAS_LOW_DEFAULT 0x6 +#define NV4_PFB_CONFIG_1_RAS_LOW_7CYCLES 0x7 +#define NV4_PFB_CONFIG_1_RAS_LOW_5CYCLES 0x5 +#define NV4_PFB_CONFIG_1_RAS_LOW_4CYCLES 0x4 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS 16 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS_DEFAULT 0x1 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS_2CYCLES 0x2 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS_0CYCLES 0x0 +#define NV4_PFB_CONFIG_1_WRITE_TO_READ 20 +#define NV4_PFB_CONFIG_1_WRITE_TO_READ_DEFAULT 0x0 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1 24 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_DEFAULT 0x1 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_2CYCLES 0x2 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_0CYCLES 0x0 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE 28 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_DEFAULT 0x4 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_5CYCLES 0x5 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_3CYCLES 0x3 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_2CYCLES 0x2 +#define NV4_PFB_CONFIG_1_READ_TO_PCHG 31 +#define NV4_PFB_CONFIG_1_READ_TO_PCHG_ON 0x1 +#define NV4_PFB_CONFIG_1_READ_TO_PCHG_OFF 0x0 +#define NV4_PFB_RTL 0x100300 +#define NV4_PFB_RTL_H 0 +#define NV4_PFB_RTL_H_DEFAULT 0x0 +#define NV4_PFB_RTL_MC 1 +#define NV4_PFB_RTL_MC_DEFAULT 0x0 +#define NV4_PFB_RTL_V 2 +#define NV4_PFB_RTL_V_DEFAULT 0x0 +#define NV4_PFB_RTL_G 3 +#define NV4_PFB_RTL_G_DEFAULT 0x0 +#define NV4_PFB_RTL_GB 4 +#define NV4_PFB_RTL_GB_DEFAULT 0x0 +#define NV4_PFB_SCRAMBLE(i) (0x100400+((i)*4)) +#define NV4_PFB_SCRAMBLE_SIZE_1 8 +#define NV4_PFB_SCRAMBLE_w0 0 +#define NV4_PFB_SCRAMBLE_w1 8 +#define NV4_PFB_SCRAMBLE_w2 16 +#define NV4_PFB_SCRAMBLE_w3 24 +#define NV4_PFB_SCRAMBLE_EN 0x100420 +#define NV4_PFB_SCRAMBLE_VALUE_0 0x03020100 +#define NV4_PFB_SCRAMBLE_VALUE_1 0x07060504 +#define NV4_PFB_SCRAMBLE_VALUE_2 0x0b0a0908 +#define NV4_PFB_SCRAMBLE_VALUE_3 0x0f0e0d0c +#define NV4_PFB_SCRAMBLE_VALUE_4 0x13121110 +#define NV4_PFB_SCRAMBLE_VALUE_5 0x17161514 +#define NV4_PFB_SCRAMBLE_VALUE_6 0x1b1a1918 +#define NV4_PFB_SCRAMBLE_VALUE_7 0x1f1e1d1c +#define NV4_PFB_CONFIG_0_RESOLUTION 0 +#define NV4_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0xA +#define NV4_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0xD +#define NV4_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0xF +#define NV4_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x10 +#define NV4_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x14 +#define NV4_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x19 +#define NV4_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x1e +#define NV4_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x20 +#define NV4_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x24 +#define NV4_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x28 +#define NV4_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x32 +#define NV4_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x14 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH 8 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x1 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x2 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x3 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x1 +#define NV4_PFB_CONFIG_0_TILING 12 +#define NV4_PFB_CONFIG_0_TILING_ENABLED 0x0 +#define NV4_PFB_CONFIG_0_TILING_DISABLED 0x1 +#define NV4_PFB_CONFIG_0_TILING_DEBUG 13 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_DISABLED 0x0 +#define NV4_PFB_CONFIG_0_TILE 12 +#define NV4_PFB_CONFIG_0_TILE_OLD1024_FIXED 0x0 +#define NV4_PFB_CONFIG_0_TILE_OLD1024_VARIABLE 0x4 +#define NV4_PFB_CONFIG_0_TILE_TETRIS_ALLOW 0x1 +#define NV4_PFB_CONFIG_0_TILE_TETRIS_REDUNDANT 0x2 +#define NV4_PFB_CONFIG_0_TILE_TETRIS_REDUNDANT2 0x3 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON 13 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON_ENABLED 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON_DISABLED 0x1 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE 14 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE_FIXED 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE_VARIABLE 0x1 +// tetris mode # = 17:15 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_MODE 15 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_MODE_PASS 0x0 +// tetris shift # = 18 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_SHIFT 18 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP 20 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_OFF 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_ON 0x1 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB 21 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_1M 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_2M 0x2 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_4M 0x3 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_UNUSED 23 +#define NV4_PFB_CONFIG_1_SGRAM100 3 +#define NV4_PFB_CONFIG_1_SGRAM100_ENABLED 0x0 +#define NV4_PFB_CONFIG_1_SGRAM100_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_CKE_ALWAYSON 29 +#define NV4_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x0 +#define NV4_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x1 + +// WARNING! WARNING! WARNING! +// STB V4400 has shown PROM at 0x700000 instead of 0x300000 (errata), clashing with first 0x10000 of instance memory +// Nvidia never ran into this issue because they never used that area +// But this part may not work +#define NV4_PRAMIN_START 0x700000 +#define NV4_PRAMIN_END 0x7FFFFF + +#define NV4_PRAMIN_CONTEXT_0 ( 0*32+31):( 0*32+ 0) +#define NV4_PRAMIN_CONTEXT_1 ( 1*32+31):( 1*32+ 0) +#define NV4_PRAMIN_CONTEXT_2 ( 2*32+31):( 2*32+ 0) +#define NV4_PRAMIN_CONTEXT_3 ( 3*32+31):( 3*32+ 0) +#define NV4_PRAMIN_RAMHT_START 0x710000 +#define NV4_PRAMIN_RAMHT_END 0x710FFF +#define NV4_PRAMIN_RAMFC_START 0x711000 +#define NV4_PRAMIN_RAMFC_END 0x7111FF +#define NV4_PRAMIN_RAMRO_START 0x711200 +#define NV4_PRAMIN_RAMRO_END 0x7113FF +#define NV4_PRAMIN_CTX_0(i) (0x700000 + (i)*16) +// This is the same format as PGRAPH_CTX_SWITCH +#define NV4_PRAMIN_CTX_0_SIZE_1 0x10000 +#define NV4_PRAMIN_CTX_0_NVCLASS 0 +#define NV4_PRAMIN_CTX_0_CHROMA_KEY 12 +#define NV4_PRAMIN_CTX_0_CHROMA_KEY_ENABLE 0x1 +#define NV4_PRAMIN_CTX_0_USER_CLIP 13 +#define NV4_PRAMIN_CTX_0_USER_CLIP_ENABLE 0x1 +#define NV4_PRAMIN_CTX_0_SWIZZLE 14 +#define NV4_PRAMIN_CTX_0_SWIZZLE_ENABLE 0x1 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG 17:15 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_AND 0x0 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_ROP_AND 0x1 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_AND 0x2 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY 0x3 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_PRE 0x4 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_PRE 0x5 +#define NV4_PRAMIN_CTX_0_PATCH_STATUS 24 +#define NV4_PRAMIN_CTX_0_PATCH_STATUS_INVALID 0x0 +#define NV4_PRAMIN_CTX_0_PATCH_STATUS_VALID 0x1 +#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE 25 +#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE_INVALID 0x0 +#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE_VALID 0x1 +#define NV4_PRAMIN_CTX_1(i) (0x700004 + (i)*16) +#define NV4_PRAMIN_CTX_1_SIZE_1 0x10000 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT 0 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT_INVALID 0x00 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT_CGA6_M1 0x01 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT_LE_M1 0x02 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT 8 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_INVALID 0x00 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y8 0x01 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A8Y8 0x02 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X24Y8 0x03 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A1R5G5B5 0x06 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X1R5G5B5 0x07 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X17R5G5B5 0x09 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_R5G6B5 0x0A +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16R5G6B5 0x0B +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16R5G6B5 0x0C +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A8R8G8B8 0x0D +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X8R8G8B8 0x0E +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y16 0x0F +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16Y16 0x10 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16Y16 0x11 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y32 0x14 +#define NV4_PRAMIN_CTX_1_NOTIFY_INSTANCE 16 +#define NV4_PRAMIN_CTX_1_NOTIFY_INSTANCE_INVALID 0x00 +#define NV4_PRAMIN_CTX_2(i) (0x700008 + (i)*16) +#define NV4_PRAMIN_CTX_2_SIZE_1 0x10000 +#define NV4_PRAMIN_CTX_2_DMA_0_INSTANCE 0 +#define NV4_PRAMIN_CTX_2_DMA_0_INSTANCE_INVALID 0x00 +#define NV4_PRAMIN_CTX_2_DMA_1_INSTANCE 16 +#define NV4_PRAMIN_CTX_2_DMA_1_INSTANCE_INVALID 0x00 + +#define NV4_FIFO_DMA_OPCODE ( 0*32+31):( 0*32+29) +#define NV4_FIFO_DMA_OPCODE_METHOD 0x0 +#define NV4_FIFO_DMA_OPCODE_JUMP 0x1 +#define NV4_FIFO_DMA_METHOD_COUNT ( 0*32+28):( 0*32+18) +#define NV4_FIFO_DMA_METHOD_SUBCHANNEL ( 0*32+15):( 0*32+13) +#define NV4_FIFO_DMA_METHOD_ADDRESS ( 0*32+12):( 0*32+ 2) +#define NV4_FIFO_DMA_DATA ( 1*32+31):( 1*32+ 0) +#define NV4_FIFO_DMA_JUMP_OFFSET 2 + +// DFB is in BAR1. Access it as VRAM + +#define NV4_PEXTDEV_BOOT_0 0x101000 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1 +#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 2 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x3 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6 +#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE 7 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x2 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x3 +#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11 +#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x1 + +#define NV4_PDAC_START 0x680000 +#define NV4_PDAC_END 0x680FFF + +#define NV4_PDAC_DATA(i) (0x680000+(i)*4) +#define NV4_PDAC_DATA_SIZE_1 16 +#define NV4_PDAC_DATA_VALUE 0 + +// WARNING! +// This has shown up at 0x700000 on real NV4 +#define NV4_PROM_START 0x300000 +#define NV4_PROM_END 0x30FFFF +#define NV4_PROM_DATA(i) (NV4_PROM_START+(i)) +#define NV4_PROM_SIZE 65536 + +#define NV4_PROM_ERRATA_START 0x700000 +#define NV4_PROM_ERRATA_END 0x70FFFF +#define NV4_PROM_ERRATA_DATA(i) (NV4_PROM_ERRATA_START+(i)) + +#define NV4_PRM 0x5FFF:0x4000 +#define NV4_PRM_INTR_0 0x4100 +#define NV4_PRM_INTR_0_TRACE_MPU401 0 +#define NV4_PRM_INTR_0_TRACE_MPU401_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_MPU401_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_MPU401_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_FM 4 +#define NV4_PRM_INTR_0_TRACE_FM_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_FM_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_FM_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL 8 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER 12 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW 16 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW_RESET 0x1 +#define NV4_PRM_INTR_EN_0 0x4140 +#define NV4_PRM_INTR_EN_0_TRACE_MPU401 0 +#define NV4_PRM_INTR_EN_0_TRACE_MPU401_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_FM 4 +#define NV4_PRM_INTR_EN_0_TRACE_FM_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_SB_DIGITAL 8 +#define NV4_PRM_INTR_EN_0_TRACE_SB_DIGITAL_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_SB_MIXER 12 +#define NV4_PRM_INTR_EN_0_TRACE_SB_MIXER_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_OVERFLOW 16 +#define NV4_PRM_INTR_EN_0_TRACE_OVERFLOW_ENABLED 0x1 +#define NV4_PRM_RAMRM 0x4200 +#define NV4_PRM_RAMRM_BASE_ADDRESS 12 +#define NV4_PRM_RAMRM_BASE_ADDRESS_2000 0x2000 +#define NV4_PRM_TRACE 0x4300 +#define NV4_PRM_TRACE_IO_CAPTURE 0 +#define NV4_PRM_TRACE_IO_CAPTURE_DISABLED 0x0 +#define NV4_PRM_TRACE_IO_CAPTURE_WRITES 0x1 +#define NV4_PRM_TRACE_IO_CAPTURE_READS 0x2 +#define NV4_PRM_TRACE_IO_CAPTURE_READS_WRITES 0x3 +#define NV4_PRM_TRACE_IO_WRITE 4 +#define NV4_PRM_TRACE_IO_WRITE_NONE 0x0 +#define NV4_PRM_TRACE_IO_WRITE_OCCURED 0x1 +#define NV4_PRM_TRACE_IO_WRITE_RESET 0x1 +#define NV4_PRM_TRACE_IO_READ 5 +#define NV4_PRM_TRACE_IO_READ_NONE 0x0 +#define NV4_PRM_TRACE_IO_READ_OCCURED 0x1 +#define NV4_PRM_TRACE_IO_READ_RESET 0x1 +#define NV4_PRM_TRACE_INDEX 0x4310 +#define NV4_PRM_TRACE_INDEX_ADDRESS 0 +#define NV4_PRM_TRACE_INDEX_ADDRESS_0 0x0 +#define NV4_PRM_IGNORE_0 0x4320 +#define NV4_PRM_IGNORE_0_MPU401 0 +#define NV4_PRM_IGNORE_0_MPU401_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_MPU401_WRITES 0x1 +#define NV4_PRM_IGNORE_0_MPU401_READS 0x2 +#define NV4_PRM_IGNORE_0_MPU401_READS_WRITES 0x3 +#define NV4_PRM_IGNORE_0_FM 4 +#define NV4_PRM_IGNORE_0_FM_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_FM_WRITES 0x1 +#define NV4_PRM_IGNORE_0_FM_READS 0x2 +#define NV4_PRM_IGNORE_0_FM_READS_WRITES 0x3 +#define NV4_PRM_IGNORE_0_SB_DIGITAL 8 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_WRITES 0x1 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_READS 0x2 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_READS_WRITES 0x3 +#define NV4_PRM_IGNORE_0_SB_MIXER 12 +#define NV4_PRM_IGNORE_0_SB_MIXER_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_SB_MIXER_WRITES 0x1 +#define NV4_PRM_IGNORE_0_SB_MIXER_READS 0x2 +#define NV4_PRM_IGNORE_0_SB_MIXER_READS_WRITES 0x3 + +// +// PIO submission +// + +#define NV4_USER_START 0x800000 +#define NV4_USER_END 0xFFFFFF + +#define NV4_USER_OBJECT(i,j) (0x800000+(i)*0x10000+(j)*0x2000) +#define NV4_USER_OBJECT_SIZE_1 16 +#define NV4_USER_OBJECT_SIZE_2 8 +#define NV4_USER_OBJECT_HANDLE 0 +#define NV4_USER_FREE016(i,j) (0x800010+(i)*65536+(j)*8192) +#define NV4_USER_FREE016_SIZE_1 16 +#define NV4_USER_FREE016_SIZE_2 8 +#define NV4_USER_FREE016_COUNT_LO 0 +#define NV4_USER_FREE016_COUNT_LO_0 0x0 +#define NV4_USER_FREE016_COUNT 2 +#define NV4_USER_FREE016_COUNT_HI 10 +#define NV4_USER_FREE016_COUNT_HI_0 0x0 +#define NV4_USER_FREE032(i,j) (0x800010+(i)*65536+(j)*8192) +#define NV4_USER_FREE032_SIZE_1 16 +#define NV4_USER_FREE032_SIZE_2 8 +#define NV4_USER_FREE032_COUNT_LO 0 +#define NV4_USER_FREE032_COUNT_LO_0 0x0 +#define NV4_USER_FREE032_COUNT 2 +#define NV4_USER_FREE032_COUNT_HI 10 +#define NV4_USER_FREE032_COUNT_HI_0 0x0 +#define NV4_USER_ZERO016(i,j,k) (0x0800012+(i)*65536+(j)*8192+(k)*2) +#define NV4_USER_ZERO016_SIZE_1 16 +#define NV4_USER_ZERO016_SIZE_2 8 +#define NV4_USER_ZERO016_SIZE_3 7 +#define NV4_USER_ZERO016_COUNT 0 +#define NV4_USER_ZERO016_COUNT_0 0x0 +#define NV4_USER_ZERO032(i,j,k) (0x0800014+(i)*65536+(j)*8192+(k)*4) +#define NV4_USER_ZERO032_SIZE_1 16 +#define NV4_USER_ZERO032_SIZE_2 8 +#define NV4_USER_ZERO032_SIZE_3 3 +#define NV4_USER_ZERO032_COUNT 0 +#define NV4_USER_ZERO032_COUNT_0 0x0 +#define NV4_USER_DMA_PUT(i,j) (0x800040+(i)*0x10000+(j)*0x2000) +#define NV4_USER_DMA_PUT_OFFSET 2 +#define NV4_USER_DMA_GET(i,j) (0x800044+(i)*0x10000+(j)*0x2000) +#define NV4_USER_DMA_GET_OFFSET 2 + +#define NV4_USER_ADR_CHID 16 +#define NV4_USER_ADR_SUBCHID 13 +#define NV4_USER_ADR_METHOD 0 +#define NV4_USER_DEVICE 16 + +#define NV4_PTIMER_START 0x9000 +#define NV4_PTIMER_END 0x9FFF + +#define NV4_PTIMER_INTR_0 0x9100 +#define NV4_PTIMER_INTR_0_ALARM 0 +#define NV4_PTIMER_INTR_0_ALARM_NOT_PENDING 0x0 +#define NV4_PTIMER_INTR_0_ALARM_PENDING 0x1 +#define NV4_PTIMER_INTR_0_ALARM_RESET 0x1 +#define NV4_PTIMER_INTR_EN_0 0x9140 +#define NV4_PTIMER_INTR_EN_0_ALARM 0 +#define NV4_PTIMER_INTR_EN_0_ALARM_ENABLED 0x1 // 0 = disabled +#define NV4_PTIMER_NUMERATOR 0x9200 +#define NV4_PTIMER_NUMERATOR_VALUE 0 +#define NV4_PTIMER_NUMERATOR_VALUE_0 0x0 +#define NV4_PTIMER_DENOMINATOR 0x9210 +#define NV4_PTIMER_DENOMINATOR_VALUE 0 +#define NV4_PTIMER_DENOMINATOR_VALUE_0 0x0 +#define NV4_PTIMER_TIME_0 0x9400 +#define NV4_PTIMER_TIME_0_NSEC 31:5 +#define NV4_PTIMER_TIME_1 0x9410 +#define NV4_PTIMER_TIME_1_NSEC 0 +#define NV4_PTIMER_ALARM_0 0x9420 +#define NV4_PTIMER_ALARM_0_NSEC 31:5 + +#define NV4_TRACE 0xFFFF: 0x0 +#define NV4_TRACE_DATA ( 0*32+ 7):( 0*32+ 0) +#define NV4_TRACE_ACCESS ( 0*32+14):( 0*32+14) +#define NV4_TRACE_ACCESS_WRITE 0x0 +#define NV4_TRACE_ACCESS_READ 0x1 +#define NV4_TRACE_TYPE ( 0*32+15):( 0*32+15) +#define NV4_TRACE_TYPE_IO 0x0 +#define NV4_TRACE_TYPE_MEMORY 0x1 +#define NV4_TRACE_ADDRESS ( 0*32+31):( 0*32+16) + +#define NV4_RAMHT_SIZE_0 0xFFF +#define NV4_RAMHT_SIZE_1 0x1FFF +#define NV4_RAMHT_SIZE_2 0x3FFF +#define NV4_RAMHT_SIZE_3 0x7FFF +#define NV4_RAMHT_HANDLE ( 0*32+31):( 0*32+ 0) +#define NV4_RAMHT_INSTANCE ( 1*32+15):( 1*32+ 0) +#define NV4_RAMHT_ENGINE ( 1*32+17):( 1*32+16) +#define NV4_RAMHT_ENGINE_SW 0x0 +#define NV4_RAMHT_ENGINE_GRAPHICS 0x1 +#define NV4_RAMHT_ENGINE_DVD 0x2 +#define NV4_RAMHT_CHID ( 1*32+27):( 1*32+24) +#define NV4_RAMHT_STATUS ( 1*32+31):( 1*32+31) +#define NV4_RAMHT_STATUS_INVALID 0x0 +#define NV4_RAMHT_STATUS_VALID 0x1 + +#define NV4_RAMRO_SIZE_0 0x1FF +#define NV4_RAMRO_SIZE_1 0x1FFF +#define NV4_RAMRO_METHOD ( 0*32+12):( 0*32+ 0) +#define NV4_RAMRO_SUBCHANNEL ( 0*32+15):( 0*32+13) +#define NV4_RAMRO_CHID ( 0*32+22):( 0*32+16) +#define NV4_RAMRO_TYPE ( 0*32+23):( 0*32+23) +#define NV4_RAMRO_TYPE_WRITE 0x0 +#define NV4_RAMRO_TYPE_READ 0x1 +#define NV4_RAMRO_BYTE_ENABLES ( 0*32+27):( 0*32+24) +#define NV4_RAMRO_REASON ( 0*32+31):( 0*32+28) +#define NV4_RAMRO_REASON_ILLEGAL_ACCESS 0x0 +#define NV4_RAMRO_REASON_NO_CACHE_AVAILABLE 0x1 +#define NV4_RAMRO_REASON_CACHE_RAN_OUT 0x2 +#define NV4_RAMRO_REASON_FREE_COUNT_OVERRUN 0x3 +#define NV4_RAMRO_REASON_CAUGHT_LYING 0x4 +#define NV4_RAMRO_REASON_RESERVED_ACCESS 0x5 +#define NV4_RAMRO_DATA ( 1*32+31):( 1*32+ 0) + +#define NV4_RAMFC_SIZE_0 0x1FF +#define NV4_RAMFC_DMA_PUT ( 0*32+28):( 0*32+ 2) +#define NV4_RAMFC_DMA_GET ( 1*32+28):( 1*32+ 2) +#define NV4_RAMFC_DMA_INST ( 2*32+15):( 2*32+ 0) +#define NV4_RAMFC_DMA_METHOD ( 3*32+12):( 3*32+ 2) +#define NV4_RAMFC_DMA_SUBCHANNEL ( 3*32+15):( 3*32+13) +#define NV4_RAMFC_DMA_METHOD_COUNT ( 3*32+28):( 3*32+18) +#define NV4_RAMFC_DMA_FETCH_TRIG ( 4*32+ 7):( 4*32+ 3) +#define NV4_RAMFC_DMA_FETCH_SIZE ( 4*32+15):( 4*32+13) +#define NV4_RAMFC_DMA_FETCH_MAX_REQS ( 4*32+19):( 4*32+16) +#define NV4_RAMFC_ENGINE_SUB_0 ( 5*32+ 1):( 5*32+ 0) +#define NV4_RAMFC_ENGINE_SUB_1 ( 5*32+ 5):( 5*32+ 4) +#define NV4_RAMFC_ENGINE_SUB_2 ( 5*32+ 9):( 5*32+ 8) +#define NV4_RAMFC_ENGINE_SUB_3 ( 5*32+13):( 5*32+12) +#define NV4_RAMFC_ENGINE_SUB_4 ( 5*32+17):( 5*32+16) +#define NV4_RAMFC_ENGINE_SUB_5 ( 5*32+21):( 5*32+20) +#define NV4_RAMFC_ENGINE_SUB_6 ( 5*32+25):( 5*32+24) +#define NV4_RAMFC_ENGINE_SUB_7 ( 5*32+29):( 5*32+28) +#define NV4_RAMFC_ENGINE_SW 0x0 +#define NV4_RAMFC_ENGINE_GRAPHICS 0x1 +#define NV4_RAMFC_ENGINE_DVD 0x2 +#define NV4_RAMFC_PULL1_ENGINE ( 6*32+ 1):( 6*32+ 0) +#define NV4_RAMFC_PULL1_ENGINE_SW 0x0 +#define NV4_RAMFC_PULL1_ENGINE_GRAPHICS 0x1 +#define NV4_RAMFC_PULL1_ENGINE_DVD 0x2 + + +#define NV4_RAMDVD_CTX_TABLE (63*32+31):( 0*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT(c,s) (((c)*4+((s)/2))*32+((s)%2)*16+15):(((c)*4+((s)/2))*32+((s)%2)*16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_0 ( 0*32+15):( 0*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_1 ( 0*32+31):( 0*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_2 ( 1*32+15):( 1*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_3 ( 1*32+31):( 1*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_4 ( 2*32+15):( 2*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_5 ( 2*32+31):( 2*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_6 ( 3*32+15):( 3*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_7 ( 3*32+31):( 3*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_0 (60*32+15):(60*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_1 (60*32+31):(60*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_2 (61*32+15):(61*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_3 (61*32+31):(61*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_4 (62*32+15):(62*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_5 (62*32+31):(62*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_6 (63*32+15):(63*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_7 (63*32+31):(63*32+16) + +#define NV4_DMA_CLASS ( 0*32+11):( 0*32+ 0) +#define NV4_DMA_PAGE_TABLE ( 0*32+12):( 0*32+12) +#define NV4_DMA_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_DMA_PAGE_TABLE_PRESENT 0x1 +#define NV4_DMA_PAGE_ENTRY ( 0*32+13):( 0*32+13) +#define NV4_DMA_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_DMA_PAGE_ENTRY_LINEAR 0x1 +#define NV4_DMA_TARGET_NODE ( 0*32+17):( 0*32+16) +#define NV4_DMA_TARGET_NODE_NVM 0x0 +#define NV4_DMA_TARGET_NODE_PCI 0x2 +#define NV4_DMA_TARGET_NODE_AGP 0x3 +#define NV4_DMA_ADJUST ( 0*32+31):( 0*32+20) +#define NV4_DMA_LIMIT ( 1*32+31):( 1*32+ 0) +#define NV4_DMA_ACCESS ( 2*32+ 1):( 2*32+ 1) +#define NV4_DMA_ACCESS_READ_ONLY 0x0 +#define NV4_DMA_ACCESS_READ_AND_WRITE 0x1 +#define NV4_DMA_FRAME_ADDRESS ( 2*32+31):( 2*32+12) + +#define NV4_SUBCHAN_CTX_SWITCH ( 0*32+31):( 0*32+ 0) +#define NV4_SUBCHAN_DMA_INSTANCE ( 1*32+15):( 1*32+ 0) +#define NV4_SUBCHAN_NOTIFY_INSTANCE ( 1*32+31):( 1*32+16) +#define NV4_SUBCHAN_MEMFMT_INSTANCE ( 2*32+15):( 2*32+ 0) +#define NV4_SUBCHAN_MEMFMT_LINEAR ( 2*32+16):( 2*32+16) +#define NV4_SUBCHAN_MEMFMT_LINEAR_OUT 0x0 +#define NV4_SUBCHAN_MEMFMT_LINEAR_IN 0x1 \ No newline at end of file