From c6d272fa9edfaea11a8a71e9c9f10077f335c0e1 Mon Sep 17 00:00:00 2001 From: BlueRain-debug Date: Thu, 22 Jan 2026 17:35:24 +0000 Subject: [PATCH 1/7] Translated using Weblate (Chinese (Simplified Han script)) Currently translated at 100.0% (1004 of 1004 strings) Translation: 86Box/86Box Translate-URL: https://weblate.86box.net/projects/86box/86box/zh_Hans/ --- src/qt/languages/zh-CN.po | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/qt/languages/zh-CN.po b/src/qt/languages/zh-CN.po index a960d8b2d..c922e207b 100644 --- a/src/qt/languages/zh-CN.po +++ b/src/qt/languages/zh-CN.po @@ -1,6 +1,6 @@ msgid "" msgstr "" -"PO-Revision-Date: 2026-01-18 19:18+0000\n" +"PO-Revision-Date: 2026-01-23 17:57+0000\n" "Last-Translator: BlueRain-debug \n" "Language-Team: Chinese (Simplified Han script) \n" @@ -2666,7 +2666,7 @@ msgid "&Unmute" msgstr "解除静音(&U)" msgid "Softfloat FPU" -msgstr "Softfloat FPU" +msgstr "软浮点FPU" msgid "High performance impact" msgstr "重大性能影响" From 570483a8287cc4b2e44bb464592b63a55b4f75bc Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 24 Jan 2026 16:10:08 +0100 Subject: [PATCH 2/7] PCI: Make PCI configuration reads and writes length-aware and fix the DC390 PCI device ID AND'ing with EEPROM DO. --- src/chipset/ali1435.c | 4 +- src/chipset/ali1489.c | 4 +- src/chipset/ali1531.c | 18 ++--- src/chipset/ali1541.c | 20 ++--- src/chipset/ali1543.c | 130 ++++++++++++++++----------------- src/chipset/ali1621.c | 8 +- src/chipset/ims8848.c | 4 +- src/chipset/intel_420ex.c | 26 +++---- src/chipset/intel_4x0.c | 40 +++++----- src/chipset/intel_i450kx.c | 16 ++-- src/chipset/intel_piix.c | 90 +++++++++++------------ src/chipset/intel_sio.c | 22 +++--- src/chipset/opti822.c | 5 +- src/chipset/sis_5511.c | 8 +- src/chipset/sis_5571.c | 8 +- src/chipset/sis_5581.c | 8 +- src/chipset/sis_5591.c | 8 +- src/chipset/sis_5600.c | 8 +- src/chipset/sis_85c496.c | 52 ++++++------- src/chipset/sis_85c50x.c | 38 +++++----- src/chipset/stpc.c | 20 ++--- src/chipset/umc_8886.c | 5 +- src/chipset/umc_8890.c | 4 +- src/chipset/umc_hb4.c | 4 +- src/chipset/via_apollo.c | 15 ++-- src/chipset/via_pipc.c | 46 ++++++------ src/chipset/via_vt82c505.c | 16 ++-- src/chipset/vl82c59x.c | 8 +- src/device/pci_bridge.c | 5 +- src/device/vfio.c | 100 ++++++++++++------------- src/disk/hdc_ide_cmd640.c | 5 +- src/disk/hdc_ide_cmd646.c | 5 +- src/disk/hdc_ide_rz1000.c | 5 +- src/disk/hdc_ide_w83769f.c | 5 +- src/include/86box/pci.h | 8 +- src/network/net_ne2000.c | 4 +- src/network/net_pcnet.c | 4 +- src/network/net_rtl8139.c | 4 +- src/network/net_tulip.c | 4 +- src/pci.c | 52 +++++++++---- src/pci_dummy.c | 4 +- src/scsi/scsi_buslogic.c | 4 +- src/scsi/scsi_ncr53c8xx.c | 4 +- src/scsi/scsi_pcscsi.c | 17 +++-- src/sound/snd_audiopci.c | 8 +- src/sound/snd_cmi8x38.c | 4 +- src/video/vid_ati_mach64.c | 4 +- src/video/vid_ati_mach8.c | 4 +- src/video/vid_bochs_vbe.c | 5 +- src/video/vid_chips_69000.c | 4 +- src/video/vid_cl54xx.c | 4 +- src/video/vid_et4000w32.c | 4 +- src/video/vid_mga.c | 4 +- src/video/vid_s3.c | 12 +-- src/video/vid_s3_virge.c | 4 +- src/video/vid_tgui9440.c | 4 +- src/video/vid_voodoo.c | 4 +- src/video/vid_voodoo_banshee.c | 4 +- 58 files changed, 484 insertions(+), 450 deletions(-) diff --git a/src/chipset/ali1435.c b/src/chipset/ali1435.c index aebd10f32..6619e033c 100644 --- a/src/chipset/ali1435.c +++ b/src/chipset/ali1435.c @@ -98,7 +98,7 @@ ali1435_update_irqs(ali1435_t *dev, int set) } static void -ali1435_pci_write(int func, int addr, uint8_t val, void *priv) +ali1435_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { ali1435_t *dev = (ali1435_t *) priv; int irq; @@ -163,7 +163,7 @@ ali1435_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -ali1435_pci_read(int func, int addr, void *priv) +ali1435_pci_read(int func, int addr, UNUSED(int len), void *priv) { const ali1435_t *dev = (ali1435_t *) priv; uint8_t ret; diff --git a/src/chipset/ali1489.c b/src/chipset/ali1489.c index 96ebd4a3d..fdf0697ec 100644 --- a/src/chipset/ali1489.c +++ b/src/chipset/ali1489.c @@ -411,7 +411,7 @@ ali1489_read(uint16_t addr, void *priv) } static void -ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +ali1489_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { ali1489_t *dev = (ali1489_t *) priv; @@ -434,7 +434,7 @@ ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -ali1489_pci_read(UNUSED(int func), int addr, void *priv) +ali1489_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const ali1489_t *dev = (ali1489_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/ali1531.c b/src/chipset/ali1531.c index 1603dbca4..b57fe1606 100644 --- a/src/chipset/ali1531.c +++ b/src/chipset/ali1531.c @@ -132,7 +132,7 @@ ali1531_shadow_recalc(UNUSED(int cur_reg), ali1531_t *dev) } static void -ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv) +ali1531_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { ali1531_t *dev = (ali1531_t *) priv; @@ -298,7 +298,7 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -ali1531_read(UNUSED(int func), int addr, void *priv) +ali1531_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const ali1531_t *dev = (ali1531_t *) priv; uint8_t ret = 0xff; @@ -341,18 +341,18 @@ ali1531_reset(void *priv) dev->pci_conf[0x5a] = 0x20; dev->pci_conf[0x70] = 0x22; - ali1531_write(0, 0x42, 0x00, dev); - ali1531_write(0, 0x43, 0x00, dev); + ali1531_write(0, 0x42, 1, 0x00, dev); + ali1531_write(0, 0x43, 1, 0x00, dev); - ali1531_write(0, 0x47, 0x00, dev); - ali1531_write(0, 0x48, 0x00, dev); + ali1531_write(0, 0x47, 1, 0x00, dev); + ali1531_write(0, 0x48, 1, 0x00, dev); for (uint8_t i = 0; i < 4; i++) - ali1531_write(0, 0x4c + i, 0x00, dev); + ali1531_write(0, 0x4c + i, 1, 0x00, dev); for (uint8_t i = 0; i < 16; i += 2) { - ali1531_write(0, 0x60 + i, 0x08, dev); - ali1531_write(0, 0x61 + i, 0x40, dev); + ali1531_write(0, 0x60 + i, 1, 0x08, dev); + ali1531_write(0, 0x61 + i, 1, 0x40, dev); } } diff --git a/src/chipset/ali1541.c b/src/chipset/ali1541.c index 1506d880a..02fd51c0b 100644 --- a/src/chipset/ali1541.c +++ b/src/chipset/ali1541.c @@ -177,7 +177,7 @@ ali1541_mask_bar(ali1541_t *dev) } static void -ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv) +ali1541_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { ali1541_t *dev = (ali1541_t *) priv; @@ -562,7 +562,7 @@ ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -ali1541_read(UNUSED(int func), int addr, void *priv) +ali1541_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const ali1541_t *dev = (ali1541_t *) priv; uint8_t ret = 0xff; @@ -613,20 +613,20 @@ ali1541_reset(void *priv) dev->pci_conf[0xe0] = 0x01; cpu_cache_int_enabled = 1; - ali1541_write(0, 0x42, 0x00, dev); + ali1541_write(0, 0x42, 1, 0x00, dev); - ali1541_write(0, 0x54, 0x00, dev); - ali1541_write(0, 0x55, 0x00, dev); + ali1541_write(0, 0x54, 1, 0x00, dev); + ali1541_write(0, 0x55, 1, 0x00, dev); for (uint8_t i = 0; i < 4; i++) - ali1541_write(0, 0x56 + i, 0x00, dev); + ali1541_write(0, 0x56 + i, 1, 0x00, dev); - ali1541_write(0, 0x60, 0x07, dev); - ali1541_write(0, 0x61, 0x40, dev); + ali1541_write(0, 0x60, 1, 0x07, dev); + ali1541_write(0, 0x61, 1, 0x40, dev); for (uint8_t i = 0; i < 14; i += 2) { - ali1541_write(0, 0x62 + i, 0x00, dev); - ali1541_write(0, 0x63 + i, 0x00, dev); + ali1541_write(0, 0x62 + i, 1, 0x00, dev); + ali1541_write(0, 0x63 + i, 1, 0x00, dev); } } diff --git a/src/chipset/ali1543.c b/src/chipset/ali1543.c index 8ef8e6a20..3d5ddf603 100644 --- a/src/chipset/ali1543.c +++ b/src/chipset/ali1543.c @@ -112,13 +112,13 @@ ali1533_ddma_handler(UNUSED(ali1543_t *dev)) static void ali5229_ide_handler(ali1543_t *dev); static void ali5229_ide_irq_handler(ali1543_t *dev); -static void ali5229_write(int func, int addr, uint8_t val, void *priv); +static void ali5229_write(int func, int addr, int len, uint8_t val, void *priv); -static void ali7101_write(int func, int addr, uint8_t val, void *priv); -static uint8_t ali7101_read(int func, int addr, void *priv); +static void ali7101_write(int func, int addr, int len, uint8_t val, void *priv); +static uint8_t ali7101_read(int func, int addr, int len, void *priv); static void -ali1533_write(int func, int addr, uint8_t val, void *priv) +ali1533_write(int func, int addr, int len, uint8_t val, void *priv) { ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val); @@ -453,7 +453,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv) case 0x7c ... 0xff: if ((dev->type == 1) && !dev->pmu_dev_enable) { dev->pmu_dev_enable = 1; - ali7101_write(func, addr, val, priv); + ali7101_write(func, addr, len, val, priv); dev->pmu_dev_enable = 0; } break; @@ -464,7 +464,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -ali1533_read(int func, int addr, void *priv) +ali1533_read(int func, int addr, int len, void *priv) { ali1543_t *dev = (ali1543_t *) priv; uint8_t ret = 0xff; @@ -478,7 +478,7 @@ ali1533_read(int func, int addr, void *priv) ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00); else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) { dev->pmu_dev_enable = 1; - ret = ali7101_read(func, addr, priv); + ret = ali7101_read(func, addr, len, priv); dev->pmu_dev_enable = 0; } } @@ -690,23 +690,23 @@ ali5229_chip_reset(ali1543_t *dev) dev->ide_conf[0x4f] = 0x1a; } - ali5229_write(0, 0x04, 0x05, dev); - ali5229_write(0, 0x10, 0xf1, dev); - ali5229_write(0, 0x11, 0x01, dev); - ali5229_write(0, 0x14, 0xf5, dev); - ali5229_write(0, 0x15, 0x03, dev); - ali5229_write(0, 0x18, 0x71, dev); - ali5229_write(0, 0x19, 0x01, dev); - ali5229_write(0, 0x1a, 0x75, dev); - ali5229_write(0, 0x1b, 0x03, dev); - ali5229_write(0, 0x20, 0x01, dev); - ali5229_write(0, 0x21, 0xf0, dev); - ali5229_write(0, 0x4d, 0x00, dev); + ali5229_write(0, 0x04, 1, 0x05, dev); + ali5229_write(0, 0x10, 1, 0xf1, dev); + ali5229_write(0, 0x11, 1, 0x01, dev); + ali5229_write(0, 0x14, 1, 0xf5, dev); + ali5229_write(0, 0x15, 1, 0x03, dev); + ali5229_write(0, 0x18, 1, 0x71, dev); + ali5229_write(0, 0x19, 1, 0x01, dev); + ali5229_write(0, 0x1a, 1, 0x75, dev); + ali5229_write(0, 0x1b, 1, 0x03, dev); + ali5229_write(0, 0x20, 1, 0x01, dev); + ali5229_write(0, 0x21, 1, 0xf0, dev); + ali5229_write(0, 0x4d, 1, 0x00, dev); dev->ide_conf[0x09] = 0xfa; - ali5229_write(0, 0x09, 0xfa, dev); - ali5229_write(0, 0x52, 0x00, dev); + ali5229_write(0, 0x09, 1, 0xfa, dev); + ali5229_write(0, 0x52, 1, 0x00, dev); - ali5229_write(0, 0x50, 0x02, dev); + ali5229_write(0, 0x50, 1, 0x02, dev); sff_set_slot(dev->ide_controller[0], dev->ide_slot); sff_set_slot(dev->ide_controller[1], dev->ide_slot); @@ -716,7 +716,7 @@ ali5229_chip_reset(ali1543_t *dev) } static void -ali5229_write(int func, int addr, uint8_t val, void *priv) +ali5229_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M5229: [W] dev->ide_conf[%02x] = %02x\n", addr, val); @@ -885,7 +885,7 @@ ali5229_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -ali5229_read(int func, int addr, void *priv) +ali5229_read(int func, int addr, UNUSED(int len), void *priv) { const ali1543_t *dev = (ali1543_t *) priv; uint8_t ret = 0xff; @@ -908,7 +908,7 @@ ali5229_read(int func, int addr, void *priv) } static void -ali5237_write(int func, int addr, uint8_t val, void *priv) +ali5237_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val); @@ -975,7 +975,7 @@ ali5237_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -ali5237_read(int func, int addr, void *priv) +ali5237_read(int func, int addr, UNUSED(int len), void *priv) { const ali1543_t *dev = (ali1543_t *) priv; uint8_t ret = 0xff; @@ -987,7 +987,7 @@ ali5237_read(int func, int addr, void *priv) } static void -ali7101_write(int func, int addr, uint8_t val, void *priv) +ali7101_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M7101: [W] dev->pmu_conf[%02x] = %02x\n", addr, val); @@ -1408,7 +1408,7 @@ ali7101_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -ali7101_read(int func, int addr, void *priv) +ali7101_read(int func, int addr, UNUSED(int len), void *priv) { ali1543_t *dev = (ali1543_t *) priv; uint8_t ret = 0xff; @@ -1516,11 +1516,11 @@ ali1543_reset(void *priv) dev->usb_conf[0x0b] = 0x0c; dev->usb_conf[0x3d] = 0x01; - ali5237_write(0, 0x04, 0x00, dev); - ali5237_write(0, 0x10, 0x00, dev); - ali5237_write(0, 0x11, 0x00, dev); - ali5237_write(0, 0x12, 0x00, dev); - ali5237_write(0, 0x13, 0x00, dev); + ali5237_write(0, 0x04, 1, 0x00, dev); + ali5237_write(0, 0x10, 1, 0x00, dev); + ali5237_write(0, 0x11, 1, 0x00, dev); + ali5237_write(0, 0x12, 1, 0x00, dev); + ali5237_write(0, 0x13, 1, 0x00, dev); /* M7101 */ memset(dev->pmu_conf, 0x00, sizeof(dev->pmu_conf)); @@ -1536,26 +1536,26 @@ ali1543_reset(void *priv) acpi_set_slot(dev->acpi, dev->pmu_slot); acpi_set_nvr(dev->acpi, dev->nvr); - ali7101_write(0, 0x04, 0x0f, dev); - ali7101_write(0, 0x10, 0x01, dev); - ali7101_write(0, 0x11, 0x00, dev); - ali7101_write(0, 0x12, 0x00, dev); - ali7101_write(0, 0x13, 0x00, dev); - ali7101_write(0, 0x14, 0x01, dev); - ali7101_write(0, 0x15, 0x00, dev); - ali7101_write(0, 0x16, 0x00, dev); - ali7101_write(0, 0x17, 0x00, dev); - ali7101_write(0, 0x40, 0x00, dev); - ali7101_write(0, 0x41, 0x00, dev); - ali7101_write(0, 0x42, 0x00, dev); - ali7101_write(0, 0x43, 0x00, dev); - ali7101_write(0, 0x77, 0x00, dev); - ali7101_write(0, 0xbd, 0x00, dev); - ali7101_write(0, 0xc0, 0x00, dev); - ali7101_write(0, 0xc1, 0x00, dev); - ali7101_write(0, 0xc2, 0x00, dev); - ali7101_write(0, 0xc3, 0x00, dev); - ali7101_write(0, 0xe0, 0x00, dev); + ali7101_write(0, 0x04, 1, 0x0f, dev); + ali7101_write(0, 0x10, 1, 0x01, dev); + ali7101_write(0, 0x11, 1, 0x00, dev); + ali7101_write(0, 0x12, 1, 0x00, dev); + ali7101_write(0, 0x13, 1, 0x00, dev); + ali7101_write(0, 0x14, 1, 0x01, dev); + ali7101_write(0, 0x15, 1, 0x00, dev); + ali7101_write(0, 0x16, 1, 0x00, dev); + ali7101_write(0, 0x17, 1, 0x00, dev); + ali7101_write(0, 0x40, 1, 0x00, dev); + ali7101_write(0, 0x41, 1, 0x00, dev); + ali7101_write(0, 0x42, 1, 0x00, dev); + ali7101_write(0, 0x43, 1, 0x00, dev); + ali7101_write(0, 0x77, 1, 0x00, dev); + ali7101_write(0, 0xbd, 1, 0x00, dev); + ali7101_write(0, 0xc0, 1, 0x00, dev); + ali7101_write(0, 0xc1, 1, 0x00, dev); + ali7101_write(0, 0xc2, 1, 0x00, dev); + ali7101_write(0, 0xc3, 1, 0x00, dev); + ali7101_write(0, 0xe0, 1, 0x00, dev); /* Do the bridge last due to device deactivations. */ /* M1533 */ @@ -1570,19 +1570,19 @@ ali1543_reset(void *priv) dev->pci_conf[0x0a] = 0x01; dev->pci_conf[0x0b] = 0x06; - ali1533_write(0, 0x41, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */ - ali1533_write(0, 0x48, 0x00, dev); /* Disables all IRQ's. */ - ali1533_write(0, 0x44, 0x00, dev); - ali1533_write(0, 0x4d, 0x00, dev); - ali1533_write(0, 0x53, 0x00, dev); - ali1533_write(0, 0x58, 0x00, dev); - ali1533_write(0, 0x5f, 0x00, dev); - ali1533_write(0, 0x72, 0x00, dev); - ali1533_write(0, 0x74, 0x00, dev); - ali1533_write(0, 0x75, 0x00, dev); - ali1533_write(0, 0x76, 0x00, dev); + ali1533_write(0, 0x41, 1, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */ + ali1533_write(0, 0x48, 1, 0x00, dev); /* Disables all IRQ's. */ + ali1533_write(0, 0x44, 1, 0x00, dev); + ali1533_write(0, 0x4d, 1, 0x00, dev); + ali1533_write(0, 0x53, 1, 0x00, dev); + ali1533_write(0, 0x58, 1, 0x00, dev); + ali1533_write(0, 0x5f, 1, 0x00, dev); + ali1533_write(0, 0x72, 1, 0x00, dev); + ali1533_write(0, 0x74, 1, 0x00, dev); + ali1533_write(0, 0x75, 1, 0x00, dev); + ali1533_write(0, 0x76, 1, 0x00, dev); if (dev->type == 1) - ali1533_write(0, 0x78, 0x00, dev); + ali1533_write(0, 0x78, 1, 0x00, dev); unmask_a20_in_smm = 1; } diff --git a/src/chipset/ali1621.c b/src/chipset/ali1621.c index 95602496c..217c1b865 100644 --- a/src/chipset/ali1621.c +++ b/src/chipset/ali1621.c @@ -255,7 +255,7 @@ ali1621_mask_bar(ali1621_t *dev) } static void -ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv) +ali1621_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { ali1621_t *dev = (ali1621_t *) priv; @@ -581,7 +581,7 @@ ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -ali1621_read(UNUSED(int func), int addr, void *priv) +ali1621_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const ali1621_t *dev = (ali1621_t *) priv; uint8_t ret = 0xff; @@ -647,10 +647,10 @@ ali1621_reset(void *priv) dev->pci_conf[0xf2] = dev->pci_conf[0xf6] = dev->pci_conf[0xfa] = dev->pci_conf[0xfe] = 0x21; dev->pci_conf[0xf3] = dev->pci_conf[0xf7] = dev->pci_conf[0xfb] = dev->pci_conf[0xff] = 0x43; - ali1621_write(0, 0x83, 0x08, dev); + ali1621_write(0, 0x83, 1, 0x08, dev); for (uint8_t i = 0; i < 4; i++) - ali1621_write(0, 0x84 + i, 0x00, dev); + ali1621_write(0, 0x84 + i, 1, 0x00, dev); } static void diff --git a/src/chipset/ims8848.c b/src/chipset/ims8848.c index 13fed304b..16625f3a1 100644 --- a/src/chipset/ims8848.c +++ b/src/chipset/ims8848.c @@ -292,7 +292,7 @@ ims8848_read(uint16_t addr, void *priv) } static void -ims8849_pci_write(int func, int addr, uint8_t val, void *priv) +ims8849_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { ims8848_t *dev = (ims8848_t *) priv; @@ -326,7 +326,7 @@ ims8849_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -ims8849_pci_read(int func, int addr, void *priv) +ims8849_pci_read(int func, UNUSED(int len), int addr, void *priv) { const ims8848_t *dev = (ims8848_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/intel_420ex.c b/src/chipset/intel_420ex.c index daa55c72c..67e2ae069 100644 --- a/src/chipset/intel_420ex.c +++ b/src/chipset/intel_420ex.c @@ -183,7 +183,7 @@ i420ex_drb_recalc(i420ex_t *dev) static void -i420ex_write(int func, int addr, uint8_t val, void *priv) +i420ex_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { i420ex_t *dev = (i420ex_t *) priv; @@ -397,7 +397,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -i420ex_read(int func, int addr, void *priv) +i420ex_read(int func, int addr, UNUSED(int len), void *priv) { const i420ex_t *dev = (i420ex_t *) priv; uint8_t ret; @@ -472,31 +472,31 @@ i420ex_reset(void *priv) { i420ex_t *dev = (i420ex_t *) priv; - i420ex_write(0, 0x48, 0x00, priv); + i420ex_write(0, 0x48, 1, 0x00, priv); /* Disable the PIC mouse latch. */ - i420ex_write(0, 0x4e, 0x03, priv); + i420ex_write(0, 0x4e, 1, 0x03, priv); for (uint8_t i = 0; i < 7; i++) - i420ex_write(0, 0x59 + i, 0x00, priv); + i420ex_write(0, 0x59 + i, 1, 0x00, priv); for (uint8_t i = 0; i <= 4; i++) dev->regs[0x60 + i] = 0x01; dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */ dev->smram_locked = 0; - i420ex_write(0, 0x70, 0x00, priv); + i420ex_write(0, 0x70, 1, 0x00, priv); mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - i420ex_write(0, 0xa0, 0x08, priv); - i420ex_write(0, 0xa2, 0x00, priv); - i420ex_write(0, 0xa4, 0x00, priv); - i420ex_write(0, 0xa5, 0x00, priv); - i420ex_write(0, 0xa6, 0x00, priv); - i420ex_write(0, 0xa7, 0x00, priv); - i420ex_write(0, 0xa8, 0x0f, priv); + i420ex_write(0, 0xa0, 1, 0x08, priv); + i420ex_write(0, 0xa2, 1, 0x00, priv); + i420ex_write(0, 0xa4, 1, 0x00, priv); + i420ex_write(0, 0xa5, 1, 0x00, priv); + i420ex_write(0, 0xa6, 1, 0x00, priv); + i420ex_write(0, 0xa7, 1, 0x00, priv); + i420ex_write(0, 0xa8, 1, 0x0f, priv); } static void diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 18f4ee66a..48627e39b 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -243,7 +243,7 @@ pm2_cntrl_write(UNUSED(uint16_t addr), uint8_t val, void *priv) } static void -i4x0_write(int func, int addr, uint8_t val, void *priv) +i4x0_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { i4x0_t *dev = (i4x0_t *) priv; uint8_t *regs = (uint8_t *) dev->regs; @@ -1535,7 +1535,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -i4x0_read(int func, int addr, void *priv) +i4x0_read(int func, int addr, UNUSED(int len), void *priv) { i4x0_t *dev = (i4x0_t *) priv; uint8_t ret = 0xff; @@ -1563,12 +1563,12 @@ i4x0_reset(void *priv) memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t)); if (dev->type >= INTEL_430FX) - i4x0_write(0, 0x59, 0x00, priv); + i4x0_write(0, 0x59, 1, 0x00, priv); else - i4x0_write(0, 0x59, 0x0f, priv); + i4x0_write(0, 0x59, 1, 0x0f, priv); for (uint8_t i = 0; i < 6; i++) - i4x0_write(0, 0x5a + i, 0x00, priv); + i4x0_write(0, 0x5a + i, 1, 0x00, priv); for (uint8_t i = 0; i <= dev->max_drb; i++) dev->regs[0x60 + i] = dev->drb_default; @@ -1582,18 +1582,18 @@ i4x0_reset(void *priv) if (dev->type >= INTEL_430FX) { dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */ - i4x0_write(0, 0x72, 0x02, priv); + i4x0_write(0, 0x72, 1, 0x02, priv); } else if (dev->type >= INTEL_430LX) { dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */ - i4x0_write(0, 0x72, 0x00, priv); + i4x0_write(0, 0x72, 1, 0x00, priv); } else { dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */ - i4x0_write(0, 0x57, 0x02, priv); + i4x0_write(0, 0x57, 1, 0x02, priv); } if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, - (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv); + 1, (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv); } } @@ -1932,24 +1932,24 @@ i4x0_init(const device_t *info) else if (dev->type >= INTEL_440LX) cpu_set_agp_speed(cpu_busspeed); - i4x0_write(regs[0x59], 0x59, 0x00, dev); - i4x0_write(regs[0x5a], 0x5a, 0x00, dev); - i4x0_write(regs[0x5b], 0x5b, 0x00, dev); - i4x0_write(regs[0x5c], 0x5c, 0x00, dev); - i4x0_write(regs[0x5d], 0x5d, 0x00, dev); - i4x0_write(regs[0x5e], 0x5e, 0x00, dev); - i4x0_write(regs[0x5f], 0x5f, 0x00, dev); + i4x0_write(regs[0x59], 0x59, 1, 0x00, dev); + i4x0_write(regs[0x5a], 0x5a, 1, 0x00, dev); + i4x0_write(regs[0x5b], 0x5b, 1, 0x00, dev); + i4x0_write(regs[0x5c], 0x5c, 1, 0x00, dev); + i4x0_write(regs[0x5d], 0x5d, 1, 0x00, dev); + i4x0_write(regs[0x5e], 0x5e, 1, 0x00, dev); + i4x0_write(regs[0x5f], 0x5f, 1, 0x00, dev); if (dev->type >= INTEL_430FX) - i4x0_write(0, 0x72, 0x02, dev); + i4x0_write(0, 0x72, 1, 0x02, dev); else if (dev->type >= INTEL_430LX) - i4x0_write(0, 0x72, 0x00, dev); + i4x0_write(0, 0x72, 1, 0x00, dev); else - i4x0_write(0, 0x57, 0x02, dev); + i4x0_write(0, 0x57, 1, 0x02, dev); if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, - (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev); + 1, (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev); } pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev, &dev->pci_slot); diff --git a/src/chipset/intel_i450kx.c b/src/chipset/intel_i450kx.c index 34cc6a62f..cb793179a 100644 --- a/src/chipset/intel_i450kx.c +++ b/src/chipset/intel_i450kx.c @@ -126,7 +126,7 @@ i450kx_vid_buf_recalc(i450kx_t *dev, int bus) } static void -pb_write(int func, int addr, uint8_t val, void *priv) +pb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { i450kx_t *dev = (i450kx_t *) priv; @@ -371,7 +371,7 @@ pb_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -pb_read(int func, int addr, void *priv) +pb_read(int func, int addr, UNUSED(int len), void *priv) { const i450kx_t *dev = (i450kx_t *) priv; uint8_t ret = 0xff; @@ -400,7 +400,7 @@ mc_fill_drbs(i450kx_t *dev) } static void -mc_write(int func, int addr, uint8_t val, void *priv) +mc_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { i450kx_t *dev = (i450kx_t *) priv; @@ -601,7 +601,7 @@ mc_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -mc_read(int func, int addr, void *priv) +mc_read(int func, int addr, UNUSED(int len), void *priv) { const i450kx_t *dev = (i450kx_t *) priv; uint8_t ret = 0xff; @@ -707,9 +707,9 @@ i450kx_reset(void *priv) #endif i450kx_smram_recalc(dev, 1); i450kx_vid_buf_recalc(dev, 1); - pb_write(0, 0x59, 0x30, dev); + pb_write(0, 0x59, 1, 0x30, dev); for (i = 0x5a; i <= 0x5f; i++) - pb_write(0, i, 0x33, dev); + pb_write(0, i, 1, 0x33, dev); /* Defaults MC */ dev->mc_pci_conf[0x00] = 0x86; @@ -779,9 +779,9 @@ i450kx_reset(void *priv) i450kx_smram_recalc(dev, 0); i450kx_vid_buf_recalc(dev, 0); - mc_write(0, 0x59, 0x03, dev); + mc_write(0, 0x59, 1, 0x03, dev); for (i = 0x5a; i <= 0x5f; i++) - mc_write(0, i, 0x00, dev); + mc_write(0, i, 1, 0x00, dev); for (i = 0x60; i <= 0x6f; i++) dev->mc_pci_conf[i] = 0x01; } diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 9d4d88687..9f7814869 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -464,7 +464,7 @@ piix_trap_update(void *priv) } static void -piix_write(int func, int addr, uint8_t val, void *priv) +piix_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { piix_t *dev = (piix_t *) priv; uint8_t *fregs; @@ -1192,7 +1192,7 @@ piix_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -piix_read(int func, int addr, void *priv) +piix_read(int func, int addr, UNUSED(int len), void *priv) { piix_t *dev = (piix_t *) priv; uint8_t ret = 0xff; @@ -1447,68 +1447,68 @@ piix_reset(void *priv) const piix_t *dev = (piix_t *) priv; if (dev->type > 3) { - piix_write(3, 0x04, 0x00, priv); - piix_write(3, 0x5b, 0x00, priv); + piix_write(3, 0x04, 1, 0x00, priv); + piix_write(3, 0x5b, 1, 0x00, priv); } else { - piix_write(0, 0xa0, 0x08, priv); - piix_write(0, 0xa2, 0x00, priv); - piix_write(0, 0xa4, 0x00, priv); - piix_write(0, 0xa5, 0x00, priv); - piix_write(0, 0xa6, 0x00, priv); - piix_write(0, 0xa7, 0x00, priv); - piix_write(0, 0xa8, 0x0f, priv); + piix_write(0, 0xa0, 1, 0x08, priv); + piix_write(0, 0xa2, 1, 0x00, priv); + piix_write(0, 0xa4, 1, 0x00, priv); + piix_write(0, 0xa5, 1, 0x00, priv); + piix_write(0, 0xa6, 1, 0x00, priv); + piix_write(0, 0xa7, 1, 0x00, priv); + piix_write(0, 0xa8, 1, 0x0f, priv); } /* Disable the PIC mouse latch. */ - piix_write(0, 0x4e, 0x03, priv); + piix_write(0, 0x4e, 1, 0x03, priv); if (dev->type == 5) - piix_write(0, 0xe1, 0x40, priv); - piix_write(1, 0x04, 0x00, priv); + piix_write(0, 0xe1, 1, 0x40, priv); + piix_write(1, 0x04, 1, 0x00, priv); if (dev->type == 5) { - piix_write(1, 0x09, 0x8a, priv); - piix_write(1, 0x10, 0xf1, priv); - piix_write(1, 0x11, 0x01, priv); - piix_write(1, 0x14, 0xf5, priv); - piix_write(1, 0x15, 0x03, priv); - piix_write(1, 0x18, 0x71, priv); - piix_write(1, 0x19, 0x01, priv); - piix_write(1, 0x1c, 0x75, priv); - piix_write(1, 0x1d, 0x03, priv); + piix_write(1, 0x09, 1, 0x8a, priv); + piix_write(1, 0x10, 1, 0xf1, priv); + piix_write(1, 0x11, 1, 0x01, priv); + piix_write(1, 0x14, 1, 0xf5, priv); + piix_write(1, 0x15, 1, 0x03, priv); + piix_write(1, 0x18, 1, 0x71, priv); + piix_write(1, 0x19, 1, 0x01, priv); + piix_write(1, 0x1c, 1, 0x75, priv); + piix_write(1, 0x1d, 1, 0x03, priv); } else - piix_write(1, 0x09, 0x80, priv); - piix_write(1, 0x20, 0x01, priv); - piix_write(1, 0x21, 0x00, priv); - piix_write(1, 0x41, 0x00, priv); - piix_write(1, 0x43, 0x00, priv); + piix_write(1, 0x09, 1, 0x80, priv); + piix_write(1, 0x20, 1, 0x01, priv); + piix_write(1, 0x21, 1, 0x00, priv); + piix_write(1, 0x41, 1, 0x00, priv); + piix_write(1, 0x43, 1, 0x00, priv); ide_pri_disable(); ide_sec_disable(); if (dev->type >= 3) { - piix_write(2, 0x04, 0x00, priv); + piix_write(2, 0x04, 1, 0x00, priv); if (dev->type == 5) { - piix_write(2, 0x10, 0x00, priv); - piix_write(2, 0x11, 0x00, priv); - piix_write(2, 0x12, 0x00, priv); - piix_write(2, 0x13, 0x00, priv); + piix_write(2, 0x10, 1, 0x00, priv); + piix_write(2, 0x11, 1, 0x00, priv); + piix_write(2, 0x12, 1, 0x00, priv); + piix_write(2, 0x13, 1, 0x00, priv); } else { - piix_write(2, 0x20, 0x01, priv); - piix_write(2, 0x21, 0x00, priv); - piix_write(2, 0x22, 0x00, priv); - piix_write(2, 0x23, 0x00, priv); + piix_write(2, 0x20, 1, 0x01, priv); + piix_write(2, 0x21, 1, 0x00, priv); + piix_write(2, 0x22, 1, 0x00, priv); + piix_write(2, 0x23, 1, 0x00, priv); } } if (dev->type >= 4) { - piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, priv); - piix_write(3, 0x40, 0x01, priv); - piix_write(3, 0x41, 0x00, priv); - piix_write(3, 0x5b, 0x00, priv); - piix_write(3, 0x80, 0x00, priv); - piix_write(3, 0x90, 0x01, priv); - piix_write(3, 0x91, 0x00, priv); - piix_write(3, 0xd2, 0x00, priv); + piix_write(0, 0xb0, 1, is_pentium ? 0x00 : 0x04, priv); + piix_write(3, 0x40, 1, 0x01, priv); + piix_write(3, 0x41, 1, 0x00, priv); + piix_write(3, 0x5b, 1, 0x00, priv); + piix_write(3, 0x80, 1, 0x00, priv); + piix_write(3, 0x90, 1, 0x01, priv); + piix_write(3, 0x91, 1, 0x00, priv); + piix_write(3, 0xd2, 1, 0x00, priv); } sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY); diff --git a/src/chipset/intel_sio.c b/src/chipset/intel_sio.c index 739785acb..c28fa5471 100644 --- a/src/chipset/intel_sio.c +++ b/src/chipset/intel_sio.c @@ -135,7 +135,7 @@ sio_timer_readw(uint16_t addr, void *priv) } static void -sio_write(int func, int addr, uint8_t val, void *priv) +sio_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { sio_t *dev = (sio_t *) priv; uint8_t old; @@ -324,7 +324,7 @@ sio_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sio_read(int func, int addr, void *priv) +sio_read(int func, int addr, UNUSED(int len), void *priv) { const sio_t *dev = (sio_t *) priv; uint8_t ret; @@ -473,20 +473,20 @@ sio_reset(void *priv) const sio_t *dev = (sio_t *) priv; /* Disable the PIC mouse latch. */ - sio_write(0, 0x4d, 0x40, priv); + sio_write(0, 0x4d, 1, 0x40, priv); - sio_write(0, 0x57, 0x04, priv); + sio_write(0, 0x57, 1, 0x04, priv); dma_set_params(1, 0xffffffff); if (dev->id == 0x03) { - sio_write(0, 0xa0, 0x08, priv); - sio_write(0, 0xa2, 0x00, priv); - sio_write(0, 0xa4, 0x00, priv); - sio_write(0, 0xa5, 0x00, priv); - sio_write(0, 0xa6, 0x00, priv); - sio_write(0, 0xa7, 0x00, priv); - sio_write(0, 0xa8, 0x0f, priv); + sio_write(0, 0xa0, 1, 0x08, priv); + sio_write(0, 0xa2, 1, 0x00, priv); + sio_write(0, 0xa4, 1, 0x00, priv); + sio_write(0, 0xa5, 1, 0x00, priv); + sio_write(0, 0xa6, 1, 0x00, priv); + sio_write(0, 0xa7, 1, 0x00, priv); + sio_write(0, 0xa8, 1, 0x0f, priv); } } diff --git a/src/chipset/opti822.c b/src/chipset/opti822.c index 2f416a1c2..2029a6b40 100644 --- a/src/chipset/opti822.c +++ b/src/chipset/opti822.c @@ -48,7 +48,6 @@ typedef struct opti822_t { uint8_t pci_regs[256]; } opti822_t; -// #define ENABLE_OPTI822_LOG 1 #ifdef ENABLE_OPTI822_LOG int opti822_do_log = ENABLE_OPTI822_LOG; @@ -131,7 +130,7 @@ opti822_update_irqs(opti822_t *dev, int set) } static void -opti822_pci_write(int func, int addr, uint8_t val, void *priv) +opti822_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { opti822_t *dev = (opti822_t *) priv; int irq; @@ -336,7 +335,7 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -opti822_pci_read(int func, int addr, void *priv) +opti822_pci_read(int func, int addr, UNUSED(int len), void *priv) { const opti822_t *dev = (opti822_t *) priv; uint8_t ret; diff --git a/src/chipset/sis_5511.c b/src/chipset/sis_5511.c index 38fcfe717..c22f798af 100644 --- a/src/chipset/sis_5511.c +++ b/src/chipset/sis_5511.c @@ -76,7 +76,7 @@ typedef struct sis_5511_t { } sis_5511_t; static void -sis_5511_write(int func, int addr, uint8_t val, void *priv) +sis_5511_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5511_t *dev = (sis_5511_t *) priv; @@ -87,7 +87,7 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5511_read(int func, int addr, void *priv) +sis_5511_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5511_t *dev = (sis_5511_t *) priv; uint8_t ret = 0xff; @@ -101,7 +101,7 @@ sis_5511_read(int func, int addr, void *priv) } static void -sis_5513_write(int func, int addr, uint8_t val, void *priv) +sis_5513_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5511_t *dev = (sis_5511_t *) priv; @@ -114,7 +114,7 @@ sis_5513_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5513_read(int func, int addr, void *priv) +sis_5513_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5511_t *dev = (sis_5511_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/sis_5571.c b/src/chipset/sis_5571.c index 02e86a98a..824f1f338 100644 --- a/src/chipset/sis_5571.c +++ b/src/chipset/sis_5571.c @@ -75,7 +75,7 @@ typedef struct sis_5571_t { } sis_5571_t; static void -sis_5571_write(int func, int addr, uint8_t val, void *priv) +sis_5571_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5571_t *dev = (sis_5571_t *) priv; @@ -86,7 +86,7 @@ sis_5571_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5571_read(int func, int addr, void *priv) +sis_5571_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5571_t *dev = (sis_5571_t *) priv; uint8_t ret = 0xff; @@ -100,7 +100,7 @@ sis_5571_read(int func, int addr, void *priv) } static void -sis_5572_write(int func, int addr, uint8_t val, void *priv) +sis_5572_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5571_t *dev = (sis_5571_t *) priv; @@ -120,7 +120,7 @@ sis_5572_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5572_read(int func, int addr, void *priv) +sis_5572_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5571_t *dev = (sis_5571_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/sis_5581.c b/src/chipset/sis_5581.c index 525fe6598..ea54a407b 100644 --- a/src/chipset/sis_5581.c +++ b/src/chipset/sis_5581.c @@ -75,7 +75,7 @@ typedef struct sis_5581_t { } sis_5581_t; static void -sis_5581_write(int func, int addr, uint8_t val, void *priv) +sis_5581_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5581_t *dev = (sis_5581_t *) priv; @@ -86,7 +86,7 @@ sis_5581_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5581_read(int func, int addr, void *priv) +sis_5581_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5581_t *dev = (sis_5581_t *) priv; uint8_t ret = 0xff; @@ -100,7 +100,7 @@ sis_5581_read(int func, int addr, void *priv) } static void -sis_5582_write(int func, int addr, uint8_t val, void *priv) +sis_5582_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5581_t *dev = (sis_5581_t *) priv; @@ -120,7 +120,7 @@ sis_5582_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5582_read(int func, int addr, void *priv) +sis_5582_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5581_t *dev = (sis_5581_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/sis_5591.c b/src/chipset/sis_5591.c index d814e0f74..48cbe9765 100644 --- a/src/chipset/sis_5591.c +++ b/src/chipset/sis_5591.c @@ -76,7 +76,7 @@ typedef struct sis_5591_t { } sis_5591_t; static void -sis_5591_write(int func, int addr, uint8_t val, void *priv) +sis_5591_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5591_t *dev = (sis_5591_t *) priv; @@ -89,7 +89,7 @@ sis_5591_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5591_read(int func, int addr, void *priv) +sis_5591_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5591_t *dev = (sis_5591_t *) priv; uint8_t ret = 0xff; @@ -105,7 +105,7 @@ sis_5591_read(int func, int addr, void *priv) } static void -sis_5595_write(int func, int addr, uint8_t val, void *priv) +sis_5595_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5591_t *dev = (sis_5591_t *) priv; @@ -125,7 +125,7 @@ sis_5595_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5595_read(int func, int addr, void *priv) +sis_5595_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5591_t *dev = (sis_5591_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/sis_5600.c b/src/chipset/sis_5600.c index 564243c68..2610ea88f 100644 --- a/src/chipset/sis_5600.c +++ b/src/chipset/sis_5600.c @@ -76,7 +76,7 @@ typedef struct sis_5600_t { } sis_5600_t; static void -sis_5600_write(int func, int addr, uint8_t val, void *priv) +sis_5600_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5600_t *dev = (sis_5600_t *) priv; @@ -89,7 +89,7 @@ sis_5600_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5600_read(int func, int addr, void *priv) +sis_5600_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5600_t *dev = (sis_5600_t *) priv; uint8_t ret = 0xff; @@ -105,7 +105,7 @@ sis_5600_read(int func, int addr, void *priv) } static void -sis_5595_write(int func, int addr, uint8_t val, void *priv) +sis_5595_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { const sis_5600_t *dev = (sis_5600_t *) priv; @@ -125,7 +125,7 @@ sis_5595_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_5595_read(int func, int addr, void *priv) +sis_5595_read(int func, int addr, UNUSED(int len), void *priv) { const sis_5600_t *dev = (sis_5600_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c index f2c1941d4..a04f01633 100644 --- a/src/chipset/sis_85c496.c +++ b/src/chipset/sis_85c496.c @@ -216,7 +216,7 @@ sis_85c496_drb_recalc(sis_85c496_t *dev) /* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */ static void -sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +sis_85c49x_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { sis_85c496_t *dev = (sis_85c496_t *) priv; uint8_t old; @@ -507,7 +507,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv) +sis_85c49x_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const sis_85c496_t *dev = (sis_85c496_t *) priv; uint8_t ret = dev->pci_conf[addr]; @@ -577,35 +577,35 @@ sis_85c496_reset(void *priv) { sis_85c496_t *dev = (sis_85c496_t *) priv; - sis_85c49x_pci_write(0, 0x44, 0x00, dev); - sis_85c49x_pci_write(0, 0x45, 0x00, dev); - sis_85c49x_pci_write(0, 0x58, 0x00, dev); - sis_85c49x_pci_write(0, 0x59, 0x00, dev); - sis_85c49x_pci_write(0, 0x5a, 0x00, dev); - // sis_85c49x_pci_write(0, 0x5a, 0x06, dev); + sis_85c49x_pci_write(0, 0x44, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x45, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x58, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x59, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x5a, 1, 0x00, dev); + // sis_85c49x_pci_write(0, 0x5a, 1, 0x06, dev); for (uint8_t i = 0; i < 8; i++) dev->pci_conf[0x48 + i] = 0x02; - sis_85c49x_pci_write(0, 0x80, 0x00, dev); - sis_85c49x_pci_write(0, 0x81, 0x00, dev); - sis_85c49x_pci_write(0, 0x9e, 0x00, dev); - sis_85c49x_pci_write(0, 0x8d, 0x00, dev); - sis_85c49x_pci_write(0, 0xa0, 0xff, dev); - sis_85c49x_pci_write(0, 0xa1, 0xff, dev); - sis_85c49x_pci_write(0, 0xc0, 0x00, dev); - sis_85c49x_pci_write(0, 0xc1, 0x00, dev); - sis_85c49x_pci_write(0, 0xc2, 0x00, dev); - sis_85c49x_pci_write(0, 0xc3, 0x00, dev); - sis_85c49x_pci_write(0, 0xc8, 0x00, dev); - sis_85c49x_pci_write(0, 0xc9, 0x00, dev); - sis_85c49x_pci_write(0, 0xca, 0x00, dev); - sis_85c49x_pci_write(0, 0xcb, 0x00, dev); + sis_85c49x_pci_write(0, 0x80, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x81, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x9e, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0x8d, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xa0, 1, 0xff, dev); + sis_85c49x_pci_write(0, 0xa1, 1, 0xff, dev); + sis_85c49x_pci_write(0, 0xc0, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xc1, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xc2, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xc3, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xc8, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xc9, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xca, 1, 0x00, dev); + sis_85c49x_pci_write(0, 0xcb, 1, 0x00, dev); - sis_85c49x_pci_write(0, 0xd0, 0x79, dev); - sis_85c49x_pci_write(0, 0xd1, 0xff, dev); - sis_85c49x_pci_write(0, 0xd0, 0x78, dev); - sis_85c49x_pci_write(0, 0xd4, 0x00, dev); + sis_85c49x_pci_write(0, 0xd0, 1, 0x79, dev); + sis_85c49x_pci_write(0, 0xd1, 1, 0xff, dev); + sis_85c49x_pci_write(0, 0xd0, 1, 0x78, dev); + sis_85c49x_pci_write(0, 0xd4, 1, 0x00, dev); dev->pci_conf[0x67] = 0x00; dev->pci_conf[0xc6] = 0x00; diff --git a/src/chipset/sis_85c50x.c b/src/chipset/sis_85c50x.c index e932ff6ca..5eb3b518d 100644 --- a/src/chipset/sis_85c50x.c +++ b/src/chipset/sis_85c50x.c @@ -199,7 +199,7 @@ sis_85c50x_smm_recalc(sis_85c50x_t *dev) } static void -sis_85c50x_write(int func, int addr, uint8_t val, void *priv) +sis_85c50x_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { sis_85c50x_t *dev = (sis_85c50x_t *) priv; @@ -311,7 +311,7 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_85c50x_read(int func, int addr, void *priv) +sis_85c50x_read(int func, int addr, UNUSED(int len), void *priv) { const sis_85c50x_t *dev = (sis_85c50x_t *) priv; uint8_t ret = 0xff; @@ -344,7 +344,7 @@ sis_85c50x_ide_recalc(sis_85c50x_t *dev) } static void -sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv) +sis_85c50x_sb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { sis_85c50x_t *dev = (sis_85c50x_t *) priv; @@ -393,7 +393,7 @@ sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -sis_85c50x_sb_read(int func, int addr, void *priv) +sis_85c50x_sb_read(int func, int addr, UNUSED(int len), void *priv) { const sis_85c50x_t *dev = (sis_85c50x_t *) priv; uint8_t ret = 0xff; @@ -553,17 +553,17 @@ sis_85c50x_reset(void *priv) dev->pci_conf[0x0a] = 0x00; dev->pci_conf[0x0b] = 0x06; - sis_85c50x_write(0, 0x51, 0x00, dev); - sis_85c50x_write(0, 0x53, 0x00, dev); - sis_85c50x_write(0, 0x54, 0x00, dev); - sis_85c50x_write(0, 0x55, 0x00, dev); - sis_85c50x_write(0, 0x56, 0x00, dev); - sis_85c50x_write(0, 0x5b, 0x00, dev); - sis_85c50x_write(0, 0x60, 0x00, dev); - sis_85c50x_write(0, 0x64, 0x00, dev); - sis_85c50x_write(0, 0x65, 0x00, dev); - sis_85c50x_write(0, 0x68, 0x00, dev); - sis_85c50x_write(0, 0x69, 0xff, dev); + sis_85c50x_write(0, 0x51, 1, 0x00, dev); + sis_85c50x_write(0, 0x53, 1, 0x00, dev); + sis_85c50x_write(0, 0x54, 1, 0x00, dev); + sis_85c50x_write(0, 0x55, 1, 0x00, dev); + sis_85c50x_write(0, 0x56, 1, 0x00, dev); + sis_85c50x_write(0, 0x5b, 1, 0x00, dev); + sis_85c50x_write(0, 0x60, 1, 0x00, dev); + sis_85c50x_write(0, 0x64, 1, 0x00, dev); + sis_85c50x_write(0, 0x65, 1, 0x00, dev); + sis_85c50x_write(0, 0x68, 1, 0x00, dev); + sis_85c50x_write(0, 0x69, 1, 0xff, dev); if (dev->type & 1) { for (uint8_t i = 0; i < 8; i++) @@ -586,10 +586,10 @@ sis_85c50x_reset(void *priv) dev->pci_conf_sb[0x0b] = 0x06; if (dev->type & 2) dev->pci_conf_sb[0x0e] = 0x80; - sis_85c50x_sb_write(0, 0x41, 0x80, dev); - sis_85c50x_sb_write(0, 0x42, 0x80, dev); - sis_85c50x_sb_write(0, 0x43, 0x80, dev); - sis_85c50x_sb_write(0, 0x44, 0x80, dev); + sis_85c50x_sb_write(0, 0x41, 1, 0x80, dev); + sis_85c50x_sb_write(0, 0x42, 1, 0x80, dev); + sis_85c50x_sb_write(0, 0x43, 1, 0x80, dev); + sis_85c50x_sb_write(0, 0x44, 1, 0x80, dev); if (dev->type & 2) { /* IDE (SiS 5503) */ diff --git a/src/chipset/stpc.c b/src/chipset/stpc.c index 56eca8268..e78a68c20 100644 --- a/src/chipset/stpc.c +++ b/src/chipset/stpc.c @@ -213,7 +213,7 @@ stpc_localbus_read(uint16_t addr, void *priv) } static void -stpc_nb_write(int func, int addr, uint8_t val, void *priv) +stpc_nb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { stpc_t *dev = (stpc_t *) priv; @@ -260,7 +260,7 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -stpc_nb_read(int func, int addr, void *priv) +stpc_nb_read(int func, int addr, UNUSED(int len), void *priv) { const stpc_t *dev = (stpc_t *) priv; uint8_t ret; @@ -337,7 +337,7 @@ stpc_ide_bm_handlers(stpc_t *dev) } static void -stpc_ide_write(int func, int addr, uint8_t val, void *priv) +stpc_ide_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { stpc_t *dev = (stpc_t *) priv; @@ -445,7 +445,7 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -stpc_ide_read(int func, int addr, void *priv) +stpc_ide_read(int func, int addr, UNUSED(int len), void *priv) { const stpc_t *dev = (stpc_t *) priv; uint8_t ret; @@ -466,12 +466,12 @@ stpc_ide_read(int func, int addr, void *priv) } static void -stpc_isab_write(int func, int addr, uint8_t val, void *priv) +stpc_isab_write(int func, int addr, int len, uint8_t val, void *priv) { stpc_t *dev = (stpc_t *) priv; if ((func == 1) && (dev->local != STPC_ATLAS)) { - stpc_ide_write(0, addr, val, priv); + stpc_ide_write(0, addr, len, val, priv); return; } @@ -507,13 +507,13 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -stpc_isab_read(int func, int addr, void *priv) +stpc_isab_read(int func, int addr, int len, void *priv) { const stpc_t *dev = (stpc_t *) priv; uint8_t ret; if ((func == 1) && (dev->local != STPC_ATLAS)) - ret = stpc_ide_read(0, addr, priv); + ret = stpc_ide_read(0, addr, len, priv); else if (func > 0) ret = 0xff; else @@ -524,7 +524,7 @@ stpc_isab_read(int func, int addr, void *priv) } static void -stpc_usb_write(int func, int addr, uint8_t val, void *priv) +stpc_usb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { stpc_t *dev = (stpc_t *) priv; @@ -571,7 +571,7 @@ stpc_usb_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -stpc_usb_read(int func, int addr, void *priv) +stpc_usb_read(int func, int addr, UNUSED(int len), void *priv) { const stpc_t *dev = (stpc_t *) priv; uint8_t ret; diff --git a/src/chipset/umc_8886.c b/src/chipset/umc_8886.c index 3725394c3..7350f5058 100644 --- a/src/chipset/umc_8886.c +++ b/src/chipset/umc_8886.c @@ -84,6 +84,7 @@ #include <86box/machine.h> #include <86box/pic.h> #include <86box/pci.h> +#include <86box/plat_unused.h> #include <86box/port_92.h> #include <86box/chipset.h> @@ -187,7 +188,7 @@ umc_8886_irq_recalc(umc_8886_t *dev) } static void -umc_8886_write(int func, int addr, uint8_t val, void *priv) +umc_8886_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { umc_8886_t *dev = (umc_8886_t *) priv; @@ -293,7 +294,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -umc_8886_read(int func, int addr, void *priv) +umc_8886_read(int func, int addr, UNUSED(int len), void *priv) { const umc_8886_t *dev = (umc_8886_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/umc_8890.c b/src/chipset/umc_8890.c index cb69ce6a8..1be55de88 100644 --- a/src/chipset/umc_8890.c +++ b/src/chipset/umc_8890.c @@ -119,7 +119,7 @@ um8890_smram(umc_8890_t *dev) } static void -um8890_write(int func, int addr, uint8_t val, void *priv) +um8890_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { umc_8890_t *dev = (umc_8890_t *)priv; @@ -158,7 +158,7 @@ um8890_write(int func, int addr, uint8_t val, void *priv) static uint8_t -um8890_read(int func, int addr, void *priv) +um8890_read(int func, int addr, UNUSED(int len), void *priv) { umc_8890_t *dev = (umc_8890_t *)priv; uint8_t ret = 0xff; diff --git a/src/chipset/umc_hb4.c b/src/chipset/umc_hb4.c index 55901b32e..ae62da166 100644 --- a/src/chipset/umc_hb4.c +++ b/src/chipset/umc_hb4.c @@ -275,7 +275,7 @@ hb4_smram(hb4_t *dev) } static void -hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv) +hb4_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { hb4_t *dev = (hb4_t *) priv; @@ -336,7 +336,7 @@ hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -hb4_read(int func, int addr, void *priv) +hb4_read(int func, int addr, UNUSED(int len), void *priv) { const hb4_t *dev = (hb4_t *) priv; uint8_t ret = 0xff; diff --git a/src/chipset/via_apollo.c b/src/chipset/via_apollo.c index 3236bbbbe..b4646ba04 100644 --- a/src/chipset/via_apollo.c +++ b/src/chipset/via_apollo.c @@ -29,6 +29,7 @@ #include <86box/device.h> #include <86box/pci.h> #include <86box/chipset.h> +#include <86box/plat_unused.h> #include <86box/spd.h> #include <86box/agpgart.h> @@ -225,7 +226,7 @@ via_apollo_setup(via_apollo_t *dev) } static void -via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) +via_apollo_host_bridge_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { via_apollo_t *dev = (via_apollo_t *) priv; if (func) @@ -684,7 +685,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -via_apollo_read(int func, int addr, void *priv) +via_apollo_read(int func, int addr, UNUSED(int len), void *priv) { const via_apollo_t *dev = (via_apollo_t *) priv; uint8_t ret = 0xff; @@ -701,11 +702,11 @@ via_apollo_read(int func, int addr, void *priv) } static void -via_apollo_write(int func, int addr, uint8_t val, void *priv) +via_apollo_write(int func, int addr, int len, uint8_t val, void *priv) { switch (func) { case 0: - via_apollo_host_bridge_write(func, addr, val, priv); + via_apollo_host_bridge_write(func, addr, len, val, priv); break; default: break; @@ -715,9 +716,9 @@ via_apollo_write(int func, int addr, uint8_t val, void *priv) static void via_apollo_reset(void *priv) { - via_apollo_write(0, 0x61, 0x00, priv); - via_apollo_write(0, 0x62, 0x00, priv); - via_apollo_write(0, 0x63, 0x00, priv); + via_apollo_write(0, 0x61, 1, 0x00, priv); + via_apollo_write(0, 0x62, 1, 0x00, priv); + via_apollo_write(0, 0x63, 1, 0x00, priv); } static void * diff --git a/src/chipset/via_pipc.c b/src/chipset/via_pipc.c index a476b9b99..a5883791e 100644 --- a/src/chipset/via_pipc.c +++ b/src/chipset/via_pipc.c @@ -170,8 +170,8 @@ pipc_log(const char *fmt, ...) static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem); static void pipc_codec_handlers(pipc_t *dev, uint8_t modem); static void pipc_sb_handlers(pipc_t *dev, uint8_t modem); -static uint8_t pipc_read(int func, int addr, void *priv); -static void pipc_write(int func, int addr, uint8_t val, void *priv); +static uint8_t pipc_read(int func, int addr, int len, void *priv); +static void pipc_write(int func, int addr, int len, uint8_t val, void *priv); static void pipc_io_trap_pact(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv) @@ -930,7 +930,7 @@ pipc_sb_get_buffer(int32_t *buffer, int len, void *priv) } static uint8_t -pipc_read(int func, int addr, void *priv) +pipc_read(int func, int addr, UNUSED(int len), void *priv) { pipc_t *dev = (pipc_t *) priv; uint8_t ret = 0xff; @@ -1026,7 +1026,7 @@ pipc_ddma_update(pipc_t *dev, int addr) } static void -pipc_write(int func, int addr, uint8_t val, void *priv) +pipc_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { pipc_t *dev = (pipc_t *) priv; int c; @@ -1661,34 +1661,34 @@ pipc_reset(void *priv) pipc_t *dev = (pipc_t *) priv; uint8_t pm_func = dev->usb[1] ? 4 : 3; - pipc_write(pm_func, 0x41, 0x00, priv); - pipc_write(pm_func, 0x48, 0x01, priv); - pipc_write(pm_func, 0x49, 0x00, priv); + pipc_write(pm_func, 0x41, 1, 0x00, priv); + pipc_write(pm_func, 0x48, 1, 0x01, priv); + pipc_write(pm_func, 0x49, 1, 0x00, priv); dev->power_regs[0x42] = ((dev->local >> 16) == VIA_PIPC_586) ? 0x00 : 0x50; acpi_set_irq_line(dev->acpi, 0x00); - pipc_write(1, 0x04, 0x80, priv); - pipc_write(1, 0x09, 0x85, priv); - pipc_write(1, 0x10, 0xf1, priv); - pipc_write(1, 0x11, 0x01, priv); - pipc_write(1, 0x14, 0xf5, priv); - pipc_write(1, 0x15, 0x03, priv); - pipc_write(1, 0x18, 0x71, priv); - pipc_write(1, 0x19, 0x01, priv); - pipc_write(1, 0x1c, 0x75, priv); - pipc_write(1, 0x1d, 0x03, priv); - pipc_write(1, 0x20, 0x01, priv); - pipc_write(1, 0x21, 0xcc, priv); + pipc_write(1, 0x04, 1, 0x80, priv); + pipc_write(1, 0x09, 1, 0x85, priv); + pipc_write(1, 0x10, 1, 0xf1, priv); + pipc_write(1, 0x11, 1, 0x01, priv); + pipc_write(1, 0x14, 1, 0xf5, priv); + pipc_write(1, 0x15, 1, 0x03, priv); + pipc_write(1, 0x18, 1, 0x71, priv); + pipc_write(1, 0x19, 1, 0x01, priv); + pipc_write(1, 0x1c, 1, 0x75, priv); + pipc_write(1, 0x1d, 1, 0x03, priv); + pipc_write(1, 0x20, 1, 0x01, priv); + pipc_write(1, 0x21, 1, 0xcc, priv); if (dev->local <= VIA_PIPC_586B) - pipc_write(1, 0x40, 0x04, priv); + pipc_write(1, 0x40, 1, 0x04, priv); else - pipc_write(1, 0x40, 0x00, priv); + pipc_write(1, 0x40, 1, 0x00, priv); if (dev->local < VIA_PIPC_586B) - pipc_write(0, 0x44, 0x00, priv); + pipc_write(0, 0x44, 1, 0x00, priv); - pipc_write(0, 0x77, 0x00, priv); + pipc_write(0, 0x77, 1, 0x00, priv); sff_set_slot(dev->bm[0], dev->pci_slot); sff_set_slot(dev->bm[1], dev->pci_slot); diff --git a/src/chipset/via_vt82c505.c b/src/chipset/via_vt82c505.c index 3daeec85b..467509fb6 100644 --- a/src/chipset/via_vt82c505.c +++ b/src/chipset/via_vt82c505.c @@ -38,7 +38,7 @@ typedef struct vt82c505_t { } vt82c505_t; static void -vt82c505_write(int func, int addr, uint8_t val, void *priv) +vt82c505_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { vt82c505_t *dev = (vt82c505_t *) priv; uint8_t irq; @@ -126,7 +126,7 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -vt82c505_read(int func, int addr, void *priv) +vt82c505_read(int func, int addr, UNUSED(int len), void *priv) { const vt82c505_t *dev = (vt82c505_t *) priv; uint8_t ret = 0xff; @@ -147,7 +147,7 @@ vt82c505_out(uint16_t addr, uint8_t val, void *priv) if (addr == 0xa8) dev->index = val; else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f)) - vt82c505_write(0, dev->index, val, priv); + vt82c505_write(0, dev->index, 1, val, priv); } static uint8_t @@ -157,7 +157,7 @@ vt82c505_in(uint16_t addr, void *priv) uint8_t ret = 0xff; if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f)) - ret = vt82c505_read(0, dev->index, priv); + ret = vt82c505_read(0, dev->index, 1, priv); return ret; } @@ -173,16 +173,16 @@ vt82c505_reset(void *priv) for (uint8_t i = 0x80; i <= 0x9f; i++) { switch (i) { case 0x81: - vt82c505_write(0, i, 0x01, priv); + vt82c505_write(0, i, 1, 0x01, priv); break; case 0x84: - vt82c505_write(0, i, 0x03, priv); + vt82c505_write(0, i, 1, 0x03, priv); break; case 0x93: - vt82c505_write(0, i, 0x40, priv); + vt82c505_write(0, i, 1, 0x40, priv); break; default: - vt82c505_write(0, i, 0x00, priv); + vt82c505_write(0, i, 1, 0x00, priv); break; } } diff --git a/src/chipset/vl82c59x.c b/src/chipset/vl82c59x.c index 69b6ebf1d..30cc63065 100644 --- a/src/chipset/vl82c59x.c +++ b/src/chipset/vl82c59x.c @@ -208,7 +208,7 @@ vl82c59x_set_pm_io(void *priv) } static void -vl82c59x_write(int func, int addr, uint8_t val, void *priv) +vl82c59x_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { vl82c59x_t *dev = (vl82c59x_t *) priv; @@ -275,7 +275,7 @@ vl82c59x_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -vl82c59x_read(int func, int addr, void *priv) +vl82c59x_read(int func, int addr, UNUSED(int len), void *priv) { const vl82c59x_t *dev = (vl82c59x_t *) priv; uint8_t ret = 0xff; @@ -292,7 +292,7 @@ vl82c59x_read(int func, int addr, void *priv) } static void -vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv) +vl82c59x_sb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { vl82c59x_t *dev = (vl82c59x_t *) priv; uint8_t irq; @@ -380,7 +380,7 @@ vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -vl82c59x_sb_read(int func, int addr, void *priv) +vl82c59x_sb_read(int func, int addr, UNUSED(int len), void *priv) { const vl82c59x_t *dev = (vl82c59x_t *) priv; uint8_t ret = 0xff; diff --git a/src/device/pci_bridge.c b/src/device/pci_bridge.c index d9aeeffb6..0a323484a 100644 --- a/src/device/pci_bridge.c +++ b/src/device/pci_bridge.c @@ -28,6 +28,7 @@ #include <86box/device.h> #include <86box/pci.h> #include <86box/plat_fallthrough.h> +#include <86box/plat_unused.h> #define PCI_BRIDGE_DEC_21150 0x10110022 #define PCI_BRIDGE_DEC_21152 0x10110024 @@ -93,7 +94,7 @@ pci_bridge_get_bus_index(void *priv) } static void -pci_bridge_write(int func, int addr, uint8_t val, void *priv) +pci_bridge_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { pci_bridge_t *dev = (pci_bridge_t *) priv; @@ -391,7 +392,7 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -pci_bridge_read(int func, int addr, void *priv) +pci_bridge_read(int func, int addr, UNUSED(int len), void *priv) { const pci_bridge_t *dev = (pci_bridge_t *) priv; uint8_t ret; diff --git a/src/device/vfio.c b/src/device/vfio.c index 2217eb509..776ded002 100644 --- a/src/device/vfio.c +++ b/src/device/vfio.c @@ -246,12 +246,12 @@ vfio_log(const char *fmt, ...) #endif static uint8_t vfio_bar_gettype(vfio_device_t *dev, vfio_region_t *bar); -static uint8_t vfio_config_readb(int func, int addr, void *priv); -static uint16_t vfio_config_readw(int func, int addr, void *priv); -static uint32_t vfio_config_readl(int func, int addr, void *priv); -static void vfio_config_writeb(int func, int addr, uint8_t val, void *priv); -static void vfio_config_writew(int func, int addr, uint16_t val, void *priv); -static void vfio_config_writel(int func, int addr, uint32_t val, void *priv); +static uint8_t vfio_config_readb(int func, int addr, int len, void *priv); +static uint16_t vfio_config_readw(int func, int addr, int len, void *priv); +static uint32_t vfio_config_readl(int func, int addr, int len, void *priv); +static void vfio_config_writeb(int func, int addr, int len, uint8_t val, void *priv); +static void vfio_config_writew(int func, int addr, int len, uint16_t val, void *priv); +static void vfio_config_writel(int func, int addr, int len, uint32_t val, void *priv); static void vfio_irq_intx_setpin(vfio_device_t *dev); static void vfio_irq_msi_disable(vfio_device_t *dev); static void vfio_irq_msix_disable(vfio_device_t *dev); @@ -371,7 +371,7 @@ vfio_quirk_configmirror_readb(uint32_t addr, void *priv) vfio_mem_readb_fd(addr, bar); /* Read configuration register. */ - uint8_t ret = vfio_config_readb(0, addr - bar->quirks.configmirror.offset, dev); + uint8_t ret = vfio_config_readb(0, addr - bar->quirks.configmirror.offset, 1, dev); vfio_log_op("VFIO %s: Config mirror: Read %02X from index %02X\n", dev->name, ret, addr - bar->quirks.configmirror.offset); @@ -388,7 +388,7 @@ vfio_quirk_configmirror_readw(uint32_t addr, void *priv) vfio_mem_readw_fd(addr, bar); /* Read configuration register. */ - uint16_t ret = vfio_config_readw(0, addr - bar->quirks.configmirror.offset, dev); + uint16_t ret = vfio_config_readw(0, addr - bar->quirks.configmirror.offset, 2, dev); vfio_log_op("VFIO %s: Config mirror: Read %04X from index %02X\n", dev->name, ret, addr - bar->quirks.configmirror.offset); @@ -405,7 +405,7 @@ vfio_quirk_configmirror_readl(uint32_t addr, void *priv) vfio_mem_readl_fd(addr, bar); /* Read configuration register. */ - uint32_t ret = vfio_config_readl(0, addr - bar->quirks.configmirror.offset, dev); + uint32_t ret = vfio_config_readl(0, addr - bar->quirks.configmirror.offset, 4, dev); vfio_log_op("VFIO %s: Config mirror: Read %08X from index %02X\n", dev->name, ret, addr - bar->quirks.configmirror.offset); @@ -421,7 +421,7 @@ vfio_quirk_configmirror_writeb(uint32_t addr, uint8_t val, void *priv) /* Write configuration register. */ vfio_log_op("VFIO %s: Config mirror: Write %02X to index %02X\n", dev->name, val, addr - bar->quirks.configmirror.offset); - vfio_config_writeb(0, addr - bar->quirks.configmirror.offset, val, dev); + vfio_config_writeb(0, addr - bar->quirks.configmirror.offset, 1, val, dev); } static void @@ -433,7 +433,7 @@ vfio_quirk_configmirror_writew(uint32_t addr, uint16_t val, void *priv) /* Write configuration register. */ vfio_log_op("VFIO %s: Config mirror: Write %04X to index %02X\n", dev->name, val, addr - bar->quirks.configmirror.offset); - vfio_config_writew(0, addr - bar->quirks.configmirror.offset, val, dev); + vfio_config_writew(0, addr - bar->quirks.configmirror.offset, 2, val, dev); } static void @@ -445,7 +445,7 @@ vfio_quirk_configmirror_writel(uint32_t addr, uint32_t val, void *priv) /* Write configuration register. */ vfio_log_op("VFIO %s: Config mirror: Write %08X to index %02X\n", dev->name, val, addr - bar->quirks.configmirror.offset); - vfio_config_writel(0, addr - bar->quirks.configmirror.offset, val, dev); + vfio_config_writel(0, addr - bar->quirks.configmirror.offset, 4, val, dev); } static void @@ -541,11 +541,11 @@ vfio_quirk_configwindow_data_readb(uint16_t addr, void *priv) /* Read configuration register if part of the main PCI configuration space. */ uint32_t index = bar->quirks.configwindow.index; if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) { - ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[0].start, dev); + ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[0].start, 1, dev); vfio_log_op("VFIO %s: Config window: Read %02X from primary index %08X\n", dev->name, ret, index); } else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) { - ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[1].start, dev); + ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[1].start, 1, dev); vfio_log_op("VFIO %s: Config window: Read %02X from secondary index %08X\n", dev->name, ret, index); } @@ -565,11 +565,11 @@ vfio_quirk_configwindow_data_readw(uint16_t addr, void *priv) /* Read configuration register if part of the main PCI configuration space. */ uint32_t index = bar->quirks.configwindow.index; if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) { - ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[0].start, dev); + ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[0].start, 2, dev); vfio_log_op("VFIO %s: Config window: Read %04X from primary index %08X\n", dev->name, ret, index); } else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) { - ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[1].start, dev); + ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[1].start, 2, dev); vfio_log_op("VFIO %s: Config window: Read %04X from secondary index %08X\n", dev->name, ret, index); } @@ -589,11 +589,11 @@ vfio_quirk_configwindow_data_readl(uint16_t addr, void *priv) /* Read configuration register if part of the main PCI configuration space. */ uint32_t index = bar->quirks.configwindow.index; if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) { - ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[0].start, dev); + ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[0].start, 4, dev); vfio_log_op("VFIO %s: Config window: Read %08X from primary index %08X\n", dev->name, ret, index); } else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) { - ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[1].start, dev); + ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[1].start, 4, dev); vfio_log_op("VFIO %s: Config window: Read %08X from secondary index %08X\n", dev->name, ret, index); } @@ -612,12 +612,12 @@ vfio_quirk_configwindow_data_writeb(uint16_t addr, uint8_t val, void *priv) if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) { vfio_log_op("VFIO %s: Config window: Write %02X to primary index %08X\n", dev->name, val, index); - vfio_config_writeb(0, index - bar->quirks.configwindow.offset[0].start, val, dev); + vfio_config_writeb(0, index - bar->quirks.configwindow.offset[0].start, 1, val, dev); return; } else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) { vfio_log_op("VFIO %s: Config window: Write %02X to secondary index %08X\n", dev->name, val, index); - vfio_config_writeb(0, index - bar->quirks.configwindow.offset[1].start, val, dev); + vfio_config_writeb(0, index - bar->quirks.configwindow.offset[1].start, 1, val, dev); return; } @@ -636,12 +636,12 @@ vfio_quirk_configwindow_data_writew(uint16_t addr, uint16_t val, void *priv) if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) { vfio_log_op("VFIO %s: Config window: Write %04X to primary index %08X\n", dev->name, val, index); - vfio_config_writew(0, index - bar->quirks.configwindow.offset[0].start, val, dev); + vfio_config_writew(0, index - bar->quirks.configwindow.offset[0].start, 2, val, dev); return; } else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) { vfio_log_op("VFIO %s: Config window: Write %04X to secondary index %08X\n", dev->name, val, index); - vfio_config_writew(0, index - bar->quirks.configwindow.offset[1].start, val, dev); + vfio_config_writew(0, index - bar->quirks.configwindow.offset[1].start, 2, val, dev); return; } @@ -660,12 +660,12 @@ vfio_quirk_configwindow_data_writel(uint16_t addr, uint32_t val, void *priv) if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) { vfio_log_op("VFIO %s: Config window: Write %08X to primary index %08X\n", dev->name, val, index); - vfio_config_writel(0, index - bar->quirks.configwindow.offset[0].start, val, dev); + vfio_config_writel(0, index - bar->quirks.configwindow.offset[0].start, 4, val, dev); return; } else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) { vfio_log_op("VFIO %s: Config window: Write %08X to secondary index %08X\n", dev->name, val, index); - vfio_config_writel(0, index - bar->quirks.configwindow.offset[1].start, val, dev); + vfio_config_writel(0, index - bar->quirks.configwindow.offset[1].start, 4, val, dev); return; } @@ -1037,7 +1037,7 @@ vfio_quirk_nvidia3d0_data_readb(uint16_t addr, void *priv) /* Read configuration register if part of the main PCI configuration space. */ if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) { - ret = vfio_config_readb(0, dev->quirks.nvidia3d0.index, dev); + ret = vfio_config_readb(0, dev->quirks.nvidia3d0.index, 1, dev); vfio_log_op("VFIO %s: NVIDIA 3D0: Read %02X from index %08X\n", dev->name, ret, dev->quirks.nvidia3d0.index); } @@ -1057,7 +1057,7 @@ vfio_quirk_nvidia3d0_data_readw(uint16_t addr, void *priv) /* Read configuration register if part of the main PCI configuration space. */ if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) { - ret = vfio_config_readw(0, dev->quirks.nvidia3d0.index, dev); + ret = vfio_config_readw(0, dev->quirks.nvidia3d0.index, 2, dev); vfio_log_op("VFIO %s: NVIDIA 3D0: Read %04X from index %08X\n", dev->name, ret, dev->quirks.nvidia3d0.index); } @@ -1077,7 +1077,7 @@ vfio_quirk_nvidia3d0_data_readl(uint16_t addr, void *priv) /* Read configuration register if part of the main PCI configuration space. */ if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) { - ret = vfio_config_readl(0, dev->quirks.nvidia3d0.index, dev); + ret = vfio_config_readl(0, dev->quirks.nvidia3d0.index, 4, dev); vfio_log_op("VFIO %s: NVIDIA 3D0: Read %08X from index %08X\n", dev->name, ret, dev->quirks.nvidia3d0.index); } @@ -1104,7 +1104,7 @@ vfio_quirk_nvidia3d0_data_writeb(uint16_t addr, uint8_t val, void *priv) /* Write configuration register. */ vfio_log_op("VFIO %s: NVIDIA 3D0: Write %02X to index %08X\n", dev->name, val, dev->quirks.nvidia3d0.index); - vfio_config_writeb(0, dev->quirks.nvidia3d0.index, val, dev); + vfio_config_writeb(0, dev->quirks.nvidia3d0.index, val, 1, dev); return; } } @@ -1131,7 +1131,7 @@ vfio_quirk_nvidia3d0_data_writew(uint16_t addr, uint16_t val, void *priv) if (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000)) { vfio_log_op("VFIO %s: NVIDIA 3D0: Write %04X to index %08X\n", dev->name, val, dev->quirks.nvidia3d0.index); - vfio_config_writew(0, dev->quirks.nvidia3d0.index, val, dev); + vfio_config_writew(0, dev->quirks.nvidia3d0.index, val, 2, dev); return; } } @@ -1159,7 +1159,7 @@ vfio_quirk_nvidia3d0_data_writel(uint16_t addr, uint32_t val, void *priv) /* Write configuration register. */ vfio_log_op("VFIO %s: NVIDIA 3D0: Write %08X to index %08X\n", dev->name, val, dev->quirks.nvidia3d0.index); - vfio_config_writel(0, dev->quirks.nvidia3d0.index, val, dev); + vfio_config_writel(0, dev->quirks.nvidia3d0.index, val, 4, dev); return; } } @@ -1198,7 +1198,7 @@ vfio_quirk_remap(vfio_device_t *dev, vfio_region_t *bar, uint8_t enable) /* BAR 2 configuration space mirror, and BAR 1/4 configuration space window. */ if (j && !i) { /* QEMU only enables the mirror here if BAR 2 is 64-bit capable. */ - if ((bar->bar_id == 2) && ((vfio_config_readb(0, 0x18, dev) & 0x07) == 0x04)) + if ((bar->bar_id == 2) && ((vfio_config_readb(0, 0x18, 1, dev) & 0x07) == 0x04)) vfio_quirk_configmirror(dev, bar, 0x4000, 0, enable); else if (bar->bar_id == 4) vfio_quirk_configwindow(dev, bar, 0x00, 4, 0x04, 4, 0x4000, 0x4000, enable); @@ -1479,7 +1479,7 @@ ceilpow2(uint32_t size) } static uint8_t -vfio_config_readb(int func, int addr, void *priv) +vfio_config_readb(int func, int addr, UNUSED(int len), void *priv) { vfio_device_t *dev = (vfio_device_t *) priv; if (func) @@ -1602,19 +1602,19 @@ end: } static uint16_t -vfio_config_readw(int func, int addr, void *priv) +vfio_config_readw(int func, int addr, UNUSED(int len), void *priv) { - return vfio_config_readb(func, addr, priv) | (vfio_config_readb(func, addr + 1, priv) << 8); + return vfio_config_readb(func, addr, 2, priv) | (vfio_config_readb(func, addr + 1, 2, priv) << 8); } static uint32_t -vfio_config_readl(int func, int addr, void *priv) +vfio_config_readl(int func, int addr, UNUSED(int len), void *priv) { - return vfio_config_readb(func, addr, priv) | (vfio_config_readb(func, addr + 1, priv) << 8) | (vfio_config_readb(func, addr + 2, priv) << 16) | (vfio_config_readb(func, addr + 3, priv) << 24); + return vfio_config_readb(func, addr, 4, priv) | (vfio_config_readb(func, addr + 1, 4, priv) << 8) | (vfio_config_readb(func, addr + 2, 4, priv) << 16) | (vfio_config_readb(func, addr + 3, 4, priv) << 24); } static void -vfio_config_writeb(int func, int addr, uint8_t val, void *priv) +vfio_config_writeb(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { vfio_device_t *dev = (vfio_device_t *) priv; if (func) @@ -1850,19 +1850,19 @@ end: } static void -vfio_config_writew(int func, int addr, uint16_t val, void *priv) +vfio_config_writew(int func, int addr, UNUSED(int len), uint16_t val, void *priv) { - vfio_config_writeb(func, addr, val, priv); - vfio_config_writeb(func, addr | 1, val >> 8, priv); + vfio_config_writeb(func, addr, 2, val, priv); + vfio_config_writeb(func, addr | 1, 2, val >> 8, priv); } static void -vfio_config_writel(int func, int addr, uint32_t val, void *priv) +vfio_config_writel(int func, int addr, UNUSED(int len), uint32_t val, void *priv) { - vfio_config_writeb(func, addr, val, priv); - vfio_config_writeb(func, addr | 1, val >> 8, priv); - vfio_config_writeb(func, addr | 2, val >> 16, priv); - vfio_config_writeb(func, addr | 3, val >> 24, priv); + vfio_config_writeb(func, addr, 4, val, priv); + vfio_config_writeb(func, addr | 1, 4, val >> 8, priv); + vfio_config_writeb(func, addr | 2, 4, val >> 16, priv); + vfio_config_writeb(func, addr | 3, 4, val >> 24, priv); } static void @@ -2549,13 +2549,13 @@ vfio_dev_prereset(vfio_device_t *dev) /* Extra steps for devices with power management capability. */ if (dev->pm_cap) { /* Make sure the device is in D0 state. */ - uint8_t pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, dev), + uint8_t pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, 1, dev), state = pm_ctrl & 0x03; if (state) { pm_ctrl &= ~0x03; - vfio_config_writeb(0, dev->pm_cap + 4, pm_ctrl, dev); + vfio_config_writeb(0, dev->pm_cap + 4, pm_ctrl, 1, dev); - pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, dev); + pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, 1, dev); state = pm_ctrl & 0x03; if (state) vfio_log("VFIO %s: Device stuck in D%d state\n", dev->name, state); @@ -2566,10 +2566,10 @@ vfio_dev_prereset(vfio_device_t *dev) } /* Enable function-level reset if supported. */ - dev->can_flr_reset = (dev->pcie_cap && (vfio_config_readb(0, dev->pcie_cap + 7, dev) & 0x10)) || (dev->af_cap && (vfio_config_readb(0, dev->af_cap + 3, dev) & 0x02)); + dev->can_flr_reset = (dev->pcie_cap && (vfio_config_readb(0, dev->pcie_cap + 7, 1, dev) & 0x10)) || (dev->af_cap && (vfio_config_readb(0, dev->af_cap + 3, 1, dev) & 0x02)); /* Disable bus master, BARs, expansion ROM and VGA regions; also enable INTx. */ - vfio_config_writew(0, 0x04, vfio_config_readw(0, 0x04, dev) & ~0x0407, dev); + vfio_config_writew(0, 0x04, vfio_config_readw(0, 0x04, 2, dev) & ~0x0407, dev); } static void diff --git a/src/disk/hdc_ide_cmd640.c b/src/disk/hdc_ide_cmd640.c index ea2a195d9..44e488df4 100644 --- a/src/disk/hdc_ide_cmd640.c +++ b/src/disk/hdc_ide_cmd640.c @@ -30,6 +30,7 @@ #include <86box/mem.h> #include <86box/pci.h> #include <86box/pic.h> +#include <86box/plat_unused.h> #include <86box/timer.h> #include <86box/hdc.h> #include <86box/hdc_ide.h> @@ -289,7 +290,7 @@ cmd640_vlb_readl(uint16_t addr, void *priv) } static void -cmd640_pci_write(int func, int addr, uint8_t val, void *priv) +cmd640_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { cmd640_t *dev = (cmd640_t *) priv; @@ -367,7 +368,7 @@ cmd640_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -cmd640_pci_read(int func, int addr, void *priv) +cmd640_pci_read(int func, int addr, UNUSED(int len), void *priv) { cmd640_t *dev = (cmd640_t *) priv; uint8_t ret = 0xff; diff --git a/src/disk/hdc_ide_cmd646.c b/src/disk/hdc_ide_cmd646.c index 333cd5e30..9cd50e871 100644 --- a/src/disk/hdc_ide_cmd646.c +++ b/src/disk/hdc_ide_cmd646.c @@ -30,6 +30,7 @@ #include <86box/mem.h> #include <86box/pci.h> #include <86box/pic.h> +#include <86box/plat_unused.h> #include <86box/timer.h> #include <86box/hdc.h> #include <86box/hdc_ide.h> @@ -296,7 +297,7 @@ cmd646_bios_handler(cmd646_t *dev) } static void -cmd646_pci_write(int func, int addr, uint8_t val, void *priv) +cmd646_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { cmd646_t *dev = (cmd646_t *) priv; int reg50 = dev->regs[0x50]; @@ -481,7 +482,7 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -cmd646_pci_read(int func, int addr, void *priv) +cmd646_pci_read(int func, int addr, UNUSED(int len), void *priv) { cmd646_t *dev = (cmd646_t *) priv; uint8_t ret = 0xff; diff --git a/src/disk/hdc_ide_rz1000.c b/src/disk/hdc_ide_rz1000.c index 56568cc2c..7559041b8 100644 --- a/src/disk/hdc_ide_rz1000.c +++ b/src/disk/hdc_ide_rz1000.c @@ -30,6 +30,7 @@ #include <86box/mem.h> #include <86box/pci.h> #include <86box/pic.h> +#include <86box/plat_unused.h> #include <86box/timer.h> #include <86box/hdc.h> #include <86box/hdc_ide.h> @@ -108,7 +109,7 @@ rz1000_ide_handlers(rz1000_t *dev) } static void -rz1000_pci_write(int func, int addr, uint8_t val, void *priv) +rz1000_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { rz1000_t *dev = (rz1000_t *) priv; @@ -138,7 +139,7 @@ rz1000_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -rz1000_pci_read(int func, int addr, void *priv) +rz1000_pci_read(int func, int addr, UNUSED(int len), void *priv) { rz1000_t *dev = (rz1000_t *) priv; uint8_t ret = 0xff; diff --git a/src/disk/hdc_ide_w83769f.c b/src/disk/hdc_ide_w83769f.c index 25ee16d10..cb4d91778 100644 --- a/src/disk/hdc_ide_w83769f.c +++ b/src/disk/hdc_ide_w83769f.c @@ -30,6 +30,7 @@ #include <86box/mem.h> #include <86box/pci.h> #include <86box/pic.h> +#include <86box/plat_unused.h> #include <86box/timer.h> #include <86box/hdc.h> #include <86box/hdc_ide.h> @@ -233,7 +234,7 @@ w83769f_vlb_readl(uint16_t addr, void *priv) } static void -w83769f_pci_write(int func, int addr, uint8_t val, void *priv) +w83769f_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { w83769f_t *dev = (w83769f_t *) priv; @@ -252,7 +253,7 @@ w83769f_pci_write(int func, int addr, uint8_t val, void *priv) } static uint8_t -w83769f_pci_read(int func, int addr, void *priv) +w83769f_pci_read(int func, int addr, UNUSED(int len), void *priv) { w83769f_t *dev = (w83769f_t *) priv; uint8_t ret = 0xff; diff --git a/src/include/86box/pci.h b/src/include/86box/pci.h index a721db005..f5f5aee04 100644 --- a/src/include/86box/pci.h +++ b/src/include/86box/pci.h @@ -266,12 +266,12 @@ extern void pci_remap_bus(uint8_t bus_index, uint8_t bus_number); extern void pci_register_bus_slot(int bus, int card, int type, int inta, int intb, int intc, int intd); /* Add a PCI card. */ -extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv), - void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot); +extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv), + void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot); /* Add an instance of the PCI bridge. */ -extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, void *priv), - void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, +extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, int len, void *priv), + void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot); /* Register the cards that have been added into slots. */ diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 3e2e7dd38..decb23d02 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -799,7 +799,7 @@ nic_update_bios(nic_t *dev) } static uint8_t -nic_pci_read(UNUSED(int func), int addr, void *priv) +nic_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const nic_t *dev = (nic_t *) priv; uint8_t ret = 0x00; @@ -894,7 +894,7 @@ nic_pci_read(UNUSED(int func), int addr, void *priv) } static void -nic_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +nic_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { nic_t *dev = (nic_t *) priv; uint8_t valxor; diff --git a/src/network/net_pcnet.c b/src/network/net_pcnet.c index 2d9aa88bb..e4cad2552 100644 --- a/src/network/net_pcnet.c +++ b/src/network/net_pcnet.c @@ -2588,7 +2588,7 @@ pcnet_ioset(nic_t *dev, uint16_t addr, int len) } static void -pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +pcnet_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { nic_t *dev = (nic_t *) priv; uint8_t valxor; @@ -2671,7 +2671,7 @@ pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) } static uint8_t -pcnet_pci_read(UNUSED(int func), int addr, void *priv) +pcnet_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const nic_t *dev = (nic_t *) priv; diff --git a/src/network/net_rtl8139.c b/src/network/net_rtl8139.c index 9cc52417f..5c50f088c 100644 --- a/src/network/net_rtl8139.c +++ b/src/network/net_rtl8139.c @@ -3100,7 +3100,7 @@ rtl8139_timer(void *priv) } static uint8_t -rtl8139_pci_read(UNUSED(int func), int addr, void *priv) +rtl8139_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const RTL8139State *s = (RTL8139State *) priv; @@ -3157,7 +3157,7 @@ rtl8139_pci_read(UNUSED(int func), int addr, void *priv) } static void -rtl8139_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +rtl8139_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { RTL8139State *s = (RTL8139State *) priv; diff --git a/src/network/net_tulip.c b/src/network/net_tulip.c index 3f1825a1e..e95810cfa 100644 --- a/src/network/net_tulip.c +++ b/src/network/net_tulip.c @@ -1182,7 +1182,7 @@ tulip_srom_crc(uint8_t *eeprom) } static uint8_t -tulip_pci_read(UNUSED(int func), int addr, void *priv) +tulip_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const TULIPState *s = (TULIPState *) priv; uint8_t ret = 0; @@ -1301,7 +1301,7 @@ tulip_pci_read(UNUSED(int func), int addr, void *priv) } static void -tulip_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +tulip_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { TULIPState *s = (TULIPState *) priv; diff --git a/src/pci.c b/src/pci.c index 16e8cdb4f..9d08a9e08 100644 --- a/src/pci.c +++ b/src/pci.c @@ -40,15 +40,15 @@ typedef struct pci_card_t { uint8_t irq_routing[PCI_INT_PINS_NUM]; void * priv; - void (*write)(int func, int addr, uint8_t val, void *priv); - uint8_t (*read)(int func, int addr, void *priv); + void (*write)(int func, int addr, int len, uint8_t val, void *priv); + uint8_t (*read)(int func, int addr, int len, void *priv); } pci_card_t; typedef struct pci_card_desc_t { uint8_t type; void * priv; - void (*write)(int func, int addr, uint8_t val, void *priv); - uint8_t (*read)(int func, int addr, void *priv); + void (*write)(int func, int addr, int len, uint8_t val, void *priv); + uint8_t (*read)(int func, int addr, int len, void *priv); uint8_t *slot; } pci_card_desc_t; @@ -91,6 +91,7 @@ static int pci_card; static int pci_bus; static int pci_key; static int pci_trc_reg = 0; +static int pci_access_len = 0; static uint32_t pci_enable = 0x00000000; static void pci_reset_regs(void); @@ -174,7 +175,7 @@ pci_irq(uint8_t slot, uint8_t pci_int, int level, int set, uint8_t *irq_state) return; if (pci_flags & FLAG_NO_IRQ_STEERING) - irq_line = pci_cards[slot].read(0, 0x3c, pci_cards[slot].priv); + irq_line = pci_cards[slot].read(0, 0x3c, 1, pci_cards[slot].priv); else { irq_routing = pci_cards[slot].irq_routing[pci_int_index]; @@ -349,12 +350,12 @@ pci_reg_write(uint16_t port, uint8_t val) slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card]; if (slot != PCI_CARD_INVALID) { if (pci_cards[slot].write) - pci_cards[slot].write(pci_func, pci_index | (port & 0x03), val, pci_cards[slot].priv); + pci_cards[slot].write(pci_func, pci_index | (port & 0x03), pci_access_len, val, pci_cards[slot].priv); } - pci_log("PCI: [WB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X = %02X\n", + pci_log("PCI: [WB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X, length %I = %02X\n", (port >= 0xc000) ? 2 : 1, slot, (slot == PCI_CARD_INVALID) ? "non-existent" : (pci_cards[slot].write ? "used" : "unused"), - pci_card, pci_bus, pci_func, pci_index | (port & 0x03), val); + pci_card, pci_bus, pci_func, pci_index | (port & 0x03), pci_access_len, val); } static void @@ -364,6 +365,8 @@ pci_reset_regs(void) pci_enable = 0x00000000; pci_flags &= ~(FLAG_CONFIG_IO_ON | FLAG_CONFIG_M1_IO_ON); + + pci_access_len = 1; } void @@ -496,16 +499,24 @@ pci_writew(uint16_t port, uint16_t val, UNUSED(void *priv)) { if (port & 0x0001) { /* Non-aligned access, split into two byte accesses. */ + if (pci_access_len == 1) + pci_access_len = 2; pci_write(port, val & 0xff, priv); pci_write(port + 1, val >> 8, priv); + if (pci_access_len == 2) + pci_access_len = 1; } else { /* Aligned access, still split because we cheat. */ switch (port) { case 0xcfc: case 0xcfe: case 0xc000 ... 0xcffe: + if (pci_access_len == 1) + pci_access_len = 2; pci_write(port, val & 0xff, priv); pci_write(port + 1, val >> 8, priv); + if (pci_access_len == 2) + pci_access_len = 1; break; default: @@ -519,8 +530,10 @@ pci_writel(uint16_t port, uint32_t val, UNUSED(void *priv)) { if (port & 0x0003) { /* Non-aligned access, split into two word accesses. */ + pci_access_len = 4; pci_writew(port, val & 0xffff, priv); pci_writew(port + 2, val >> 16, priv); + pci_access_len = 1; } else { /* Aligned access. */ switch (port) { @@ -545,8 +558,10 @@ pci_writel(uint16_t port, uint32_t val, UNUSED(void *priv)) case 0xcfc: case 0xc000 ... 0xcffc: /* Still split because we cheat. */ + pci_access_len = 4; pci_writew(port, val & 0xffff, priv); pci_writew(port + 2, val >> 16, priv); + pci_access_len = 1; break; default: @@ -569,12 +584,12 @@ pci_reg_read(uint16_t port) slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card]; if (slot != PCI_CARD_INVALID) { if (pci_cards[slot].read) - ret = pci_cards[slot].read(pci_func, pci_index | (port & 0x03), pci_cards[slot].priv); + ret = pci_cards[slot].read(pci_func, pci_index | (port & 0x03), pci_access_len, pci_cards[slot].priv); } - pci_log("PCI: [RB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X = %02X\n", + pci_log("PCI: [RB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X, length %i = %02X\n", (port >= 0xc000) ? 2 : 1, slot, (slot == PCI_CARD_INVALID) ? "non-existent" : (pci_cards[slot].read ? "used" : "unused"), - pci_card, pci_bus, pci_func, pci_index | (port & 0x03), ret); + pci_card, pci_bus, pci_access_len, pci_index | (port & 0x03), pci_func, ret); return ret; } @@ -643,8 +658,12 @@ pci_readw(uint16_t port, UNUSED(void *priv)) case 0xcfc: case 0xcfe: case 0xc000 ... 0xcffe: + if (pci_access_len == 1) + pci_access_len = 2; ret = pci_read(port, priv); ret |= ((uint16_t) pci_read(port + 1, priv)) << 8; + if (pci_access_len == 2) + pci_access_len = 1; break; default: @@ -662,8 +681,10 @@ pci_readl(uint16_t port, UNUSED(void *priv)) if (port & 0x0003) { /* Non-aligned access, split into two word accesses. */ + pci_access_len = 4; ret = pci_readw(port, priv); ret |= ((uint32_t) pci_readw(port + 2, priv)) << 16; + pci_access_len = 1; } else { /* Aligned access. */ switch (port) { @@ -682,8 +703,10 @@ pci_readl(uint16_t port, UNUSED(void *priv)) case 0xcfc: case 0xc000 ... 0xcffc: /* Still split because we cheat. */ + pci_access_len = 4; ret = pci_readw(port, priv); ret |= ((uint32_t) pci_readw(port + 2, priv)) << 16; + pci_access_len = 1; break; } } @@ -781,8 +804,8 @@ pci_find_slot(uint8_t add_type, uint8_t ignore_slot) /* Add a PCI card. */ void -pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv), - void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot) +pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv), + void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot) { pci_card_desc_t *dev; @@ -853,7 +876,8 @@ pci_register_card(int pci_card) /* Add an instance of the PCI bridge. */ void -pci_add_bridge(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot) +pci_add_bridge(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv), + void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot) { pci_card_t *card; uint8_t bridge_slot = (add_type == PCI_ADD_NORMAL) ? last_normal_pci_card_id : pci_find_slot(add_type, 0xff); diff --git a/src/pci_dummy.c b/src/pci_dummy.c index bceb58c22..e5395bed8 100644 --- a/src/pci_dummy.c +++ b/src/pci_dummy.c @@ -38,7 +38,7 @@ pci_dummy_interrupt(int set, pci_dummy_t *dev) } static uint8_t -pci_dummy_read(uint16_t port, void *priv) +pci_dummy_read(uint16_t port, UNUSED(int len), void *priv) { pci_dummy_t *dev = (pci_dummy_t *) priv; uint8_t ret = 0xff; @@ -90,7 +90,7 @@ pci_dummy_readl(uint16_t port, void *priv) } static void -pci_dummy_write(uint16_t port, UNUSED(uint8_t val), void *priv) +pci_dummy_write(uint16_t port, UNUSED(uint8_t val), UNUSED(int len), void *priv) { pci_dummy_t *dev = (pci_dummy_t *) priv; diff --git a/src/scsi/scsi_buslogic.c b/src/scsi/scsi_buslogic.c index daeb0a3e4..754750b22 100644 --- a/src/scsi/scsi_buslogic.c +++ b/src/scsi/scsi_buslogic.c @@ -1117,7 +1117,7 @@ BuslogicBIOSUpdate(buslogic_data_t *bl) } static uint8_t -BuslogicPCIRead(UNUSED(int func), int addr, void *priv) +BuslogicPCIRead(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const x54x_t *dev = (x54x_t *) priv; #ifdef ENABLE_BUSLOGIC_LOG @@ -1203,7 +1203,7 @@ BuslogicPCIRead(UNUSED(int func), int addr, void *priv) } static void -BuslogicPCIWrite(UNUSED(int func), int addr, uint8_t val, void *priv) +BuslogicPCIWrite(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { x54x_t *dev = (x54x_t *) priv; buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data; diff --git a/src/scsi/scsi_ncr53c8xx.c b/src/scsi/scsi_ncr53c8xx.c index bc3ecec0b..eef94c916 100644 --- a/src/scsi/scsi_ncr53c8xx.c +++ b/src/scsi/scsi_ncr53c8xx.c @@ -2283,7 +2283,7 @@ uint8_t ncr53c8xx_pci_regs[256]; bar_t ncr53c8xx_pci_bar[4]; static uint8_t -ncr53c8xx_pci_read(UNUSED(int func), int addr, void *priv) +ncr53c8xx_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { ncr53c8xx_t *dev = (ncr53c8xx_t *) priv; @@ -2387,7 +2387,7 @@ ncr53c8xx_pci_read(UNUSED(int func), int addr, void *priv) } static void -ncr53c8xx_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +ncr53c8xx_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { ncr53c8xx_t *dev = (ncr53c8xx_t *) priv; uint8_t valxor; diff --git a/src/scsi/scsi_pcscsi.c b/src/scsi/scsi_pcscsi.c index 11793f5a9..51aea3f46 100644 --- a/src/scsi/scsi_pcscsi.c +++ b/src/scsi/scsi_pcscsi.c @@ -1997,7 +1997,7 @@ esp_bios_disable(esp_t *dev) #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08 static uint8_t -esp_pci_read(UNUSED(int func), int addr, void *priv) +esp_pci_read(UNUSED(int func), int addr, int len, void *priv) { esp_t *dev = (esp_t *) priv; @@ -2009,12 +2009,15 @@ esp_pci_read(UNUSED(int func), int addr, void *priv) if (!dev->has_bios || dev->local) return 0x22; else { - if (nmc93cxx_eeprom_read(dev->eeprom)) - return 0x22; - else { - dev->eeprom->dev.out = 1; - return 2; + uint8_t ret = 0x22; + + if (len == 1) { + /* First byte of address space is AND-ed with EEPROM DO line */ + if (!nmc93cxx_eeprom_read(dev->eeprom)) + ret &= 0x00; } + + return ret; } break; case 0x01: @@ -2084,7 +2087,7 @@ esp_pci_read(UNUSED(int func), int addr, void *priv) } static void -esp_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +esp_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { esp_t *dev = (esp_t *) priv; uint8_t valxor; diff --git a/src/sound/snd_audiopci.c b/src/sound/snd_audiopci.c index 23c4863c7..9a4cb3c6f 100644 --- a/src/sound/snd_audiopci.c +++ b/src/sound/snd_audiopci.c @@ -1905,7 +1905,7 @@ update_legacy(es137x_t *dev, uint32_t old_legacy_ctrl) } static uint8_t -es1370_pci_read(int func, int addr, void *priv) +es1370_pci_read(int func, int addr, UNUSED(int len), void *priv) { const es137x_t *dev = (es137x_t *) priv; @@ -2001,7 +2001,7 @@ es1370_pci_read(int func, int addr, void *priv) } static uint8_t -es1371_pci_read(int func, int addr, void *priv) +es1371_pci_read(int func, int addr, UNUSED(int len), void *priv) { const es137x_t *dev = (es137x_t *) priv; @@ -2103,7 +2103,7 @@ es137x_io_set(es137x_t *dev, int set) } static void -es1370_pci_write(int func, int addr, uint8_t val, void *priv) +es1370_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { es137x_t *dev = (es137x_t *) priv; @@ -2154,7 +2154,7 @@ es1370_pci_write(int func, int addr, uint8_t val, void *priv) } static void -es1371_pci_write(int func, int addr, uint8_t val, void *priv) +es1371_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { es137x_t *dev = (es137x_t *) priv; diff --git a/src/sound/snd_cmi8x38.c b/src/sound/snd_cmi8x38.c index 9ee003689..d4490ac23 100644 --- a/src/sound/snd_cmi8x38.c +++ b/src/sound/snd_cmi8x38.c @@ -966,7 +966,7 @@ cmi8x38_remap(cmi8x38_t *dev) } static uint8_t -cmi8x38_pci_read(int func, int addr, void *priv) +cmi8x38_pci_read(int func, int addr, UNUSED(int len), void *priv) { const cmi8x38_t *dev = (cmi8x38_t *) priv; uint8_t ret = 0xff; @@ -980,7 +980,7 @@ cmi8x38_pci_read(int func, int addr, void *priv) } static void -cmi8x38_pci_write(int func, int addr, uint8_t val, void *priv) +cmi8x38_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { cmi8x38_t *dev = (cmi8x38_t *) priv; diff --git a/src/video/vid_ati_mach64.c b/src/video/vid_ati_mach64.c index ceaf4224b..8ce13f14d 100644 --- a/src/video/vid_ati_mach64.c +++ b/src/video/vid_ati_mach64.c @@ -5129,7 +5129,7 @@ mach64_writel_be(uint32_t addr, uint32_t val, void *priv) } uint8_t -mach64_pci_read(UNUSED(int func), int addr, void *priv) +mach64_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const mach64_t *mach64 = (mach64_t *) priv; @@ -5214,7 +5214,7 @@ mach64_pci_read(UNUSED(int func), int addr, void *priv) } void -mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +mach64_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { mach64_t *mach64 = (mach64_t *) priv; diff --git a/src/video/vid_ati_mach8.c b/src/video/vid_ati_mach8.c index ccb194146..fff9bce3e 100644 --- a/src/video/vid_ati_mach8.c +++ b/src/video/vid_ati_mach8.c @@ -7092,7 +7092,7 @@ ati8514_pos_write(uint16_t port, uint8_t val, void *priv) } static uint8_t -mach32_pci_read(UNUSED(int func), int addr, void *priv) +mach32_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const mach_t *mach = (mach_t *) priv; uint8_t ret = 0x00; @@ -7171,7 +7171,7 @@ mach32_pci_read(UNUSED(int func), int addr, void *priv) } static void -mach32_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +mach32_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { mach_t *mach = (mach_t *) priv; if ((addr >= 0x30) && (addr <= 0x33) && !mach->has_bios) diff --git a/src/video/vid_bochs_vbe.c b/src/video/vid_bochs_vbe.c index 0a41bec2d..d14e92ec1 100644 --- a/src/video/vid_bochs_vbe.c +++ b/src/video/vid_bochs_vbe.c @@ -39,6 +39,7 @@ #include <86box/vid_svga.h> #include <86box/vid_svga_render.h> #include <86box/pci.h> +#include <86box/plat_unused.h> #include <86box/i2c.h> #include <86box/vid_ddc.h> @@ -628,7 +629,7 @@ bochs_vbe_in(uint16_t addr, void *priv) } static uint8_t -bochs_vbe_pci_read(const int func, const int addr, void *priv) +bochs_vbe_pci_read(const int func, const int addr, UNUSED(const int len), void *priv) { const bochs_vbe_t *dev = (bochs_vbe_t *) priv; uint8_t ret = 0x00; @@ -711,7 +712,7 @@ bochs_vbe_disable_handlers(bochs_vbe_t *dev) } static void -bochs_vbe_pci_write(const int func, const int addr, const uint8_t val, void *priv) +bochs_vbe_pci_write(const int func, const int addr, UNUSED(const int len), const uint8_t val, void *priv) { bochs_vbe_t *dev = (bochs_vbe_t *) priv; diff --git a/src/video/vid_chips_69000.c b/src/video/vid_chips_69000.c index ef48207e1..2cd6c4162 100644 --- a/src/video/vid_chips_69000.c +++ b/src/video/vid_chips_69000.c @@ -2141,7 +2141,7 @@ chips_69000_in(uint16_t addr, void *priv) } static uint8_t -chips_69000_pci_read(UNUSED(int func), int addr, void *priv) +chips_69000_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { chips_69000_t *chips = (chips_69000_t *) priv; uint8_t ret = 0x00; @@ -2215,7 +2215,7 @@ chips_69000_pci_read(UNUSED(int func), int addr, void *priv) } static void -chips_69000_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +chips_69000_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { chips_69000_t *chips = (chips_69000_t *) priv; diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index 4161e223e..cec60332e 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -3934,7 +3934,7 @@ gd54xx_start_blit(uint32_t cpu_dat, uint32_t count, gd54xx_t *gd54xx, svga_t *sv } static uint8_t -cl_pci_read(UNUSED(int func), int addr, void *priv) +cl_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const gd54xx_t *gd54xx = (gd54xx_t *) priv; const svga_t *svga = &gd54xx->svga; @@ -4046,7 +4046,7 @@ cl_pci_read(UNUSED(int func), int addr, void *priv) } static void -cl_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +cl_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { gd54xx_t *gd54xx = (gd54xx_t *) priv; const svga_t *svga = &gd54xx->svga; diff --git a/src/video/vid_et4000w32.c b/src/video/vid_et4000w32.c index 4abb9a767..18d6b4575 100644 --- a/src/video/vid_et4000w32.c +++ b/src/video/vid_et4000w32.c @@ -2652,7 +2652,7 @@ et4000w32p_io_set(et4000w32p_t *et4000) } uint8_t -et4000w32p_pci_read(UNUSED(int func), int addr, void *priv) +et4000w32p_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const et4000w32p_t *et4000 = (et4000w32p_t *) priv; @@ -2709,7 +2709,7 @@ et4000w32p_pci_read(UNUSED(int func), int addr, void *priv) } void -et4000w32p_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +et4000w32p_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { et4000w32p_t *et4000 = (et4000w32p_t *) priv; svga_t *svga = &et4000->svga; diff --git a/src/video/vid_mga.c b/src/video/vid_mga.c index 07b0869f7..449b21866 100644 --- a/src/video/vid_mga.c +++ b/src/video/vid_mga.c @@ -6337,7 +6337,7 @@ mystique_tvp3026_gpio_write(uint8_t cntl, uint8_t data, void *priv) } static uint8_t -mystique_pci_read(UNUSED(int func), int addr, void *priv) +mystique_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { mystique_t *mystique = (mystique_t *) priv; uint8_t ret = 0x00; @@ -6574,7 +6574,7 @@ mystique_pci_read(UNUSED(int func), int addr, void *priv) } static void -mystique_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +mystique_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { mystique_t *mystique = (mystique_t *) priv; diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c index fc7499ff6..3965391cb 100644 --- a/src/video/vid_s3.c +++ b/src/video/vid_s3.c @@ -458,8 +458,8 @@ static void s3_accel_out_l(uint16_t port, uint32_t val, void *priv); static uint8_t s3_accel_in(uint16_t port, void *priv); static uint16_t s3_accel_in_w(uint16_t port, void *priv); static uint32_t s3_accel_in_l(uint16_t port, void *priv); -static uint8_t s3_pci_read(int func, int addr, void *priv); -static void s3_pci_write(int func, int addr, uint8_t val, void *priv); +static uint8_t s3_pci_read(int func, int addr, int len, void *priv); +static void s3_pci_write(int func, int addr, int len, uint8_t val, void *priv); #ifdef ENABLE_S3_LOG int s3_do_log = ENABLE_S3_LOG; @@ -2013,7 +2013,7 @@ s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val) int addr_lo = addr & 1; if (svga->crtc[0x53] & 0x08) { if ((addr >= 0x08000) && (addr <= 0x0803f)) - s3_pci_write(0, addr & 0xff, val, s3); + s3_pci_write(0, addr & 0xff, 1, val, s3); } switch (addr & 0x1fffe) { @@ -6736,7 +6736,7 @@ s3_accel_read(uint32_t addr, void *priv) if (svga->crtc[0x53] & 0x08) { if ((addr >= 0x08000) && (addr <= 0x0803f)) - return s3_pci_read(0, addr & 0xff, s3); + return s3_pci_read(0, addr & 0xff, 1, s3); switch (addr & 0x1ffff) { case 0x83b0 ... 0x83df: return s3_in(addr & 0x3ff, s3); @@ -11001,7 +11001,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi } static uint8_t -s3_pci_read(UNUSED(int func), int addr, void *priv) +s3_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const s3_t *s3 = (s3_t *) priv; const svga_t *svga = &s3->svga; @@ -11090,7 +11090,7 @@ s3_pci_read(UNUSED(int func), int addr, void *priv) } static void -s3_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +s3_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { s3_t *s3 = (s3_t *) priv; svga_t *svga = &s3->svga; diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c index abeba064e..b53dd5e8c 100644 --- a/src/video/vid_s3_virge.c +++ b/src/video/vid_s3_virge.c @@ -5024,7 +5024,7 @@ s3_virge_overlay_draw(svga_t *svga, int displine) } static uint8_t -s3_virge_pci_read(UNUSED(int func), int addr, void *priv) +s3_virge_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const virge_t *virge = (virge_t *) priv; const svga_t *svga = &virge->svga; @@ -5189,7 +5189,7 @@ s3_virge_pci_read(UNUSED(int func), int addr, void *priv) } static void -s3_virge_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +s3_virge_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { virge_t *virge = (virge_t *) priv; svga_t *svga = &virge->svga; diff --git a/src/video/vid_tgui9440.c b/src/video/vid_tgui9440.c index 28c02363c..2a76ee2a4 100644 --- a/src/video/vid_tgui9440.c +++ b/src/video/vid_tgui9440.c @@ -1096,7 +1096,7 @@ tgui_hwcursor_draw(svga_t *svga, int displine) } uint8_t -tgui_pci_read(UNUSED(int func), int addr, void *priv) +tgui_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv) { const tgui_t *tgui = (tgui_t *) priv; @@ -1166,7 +1166,7 @@ tgui_pci_read(UNUSED(int func), int addr, void *priv) } void -tgui_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) +tgui_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv) { tgui_t *tgui = (tgui_t *) priv; svga_t *svga = &tgui->svga; diff --git a/src/video/vid_voodoo.c b/src/video/vid_voodoo.c index 72a57e66c..78aba3cad 100644 --- a/src/video/vid_voodoo.c +++ b/src/video/vid_voodoo.c @@ -1005,7 +1005,7 @@ voodoo_recalcmapping(voodoo_set_t *set) } uint8_t -voodoo_pci_read(int func, int addr, void *priv) +voodoo_pci_read(int func, int addr, UNUSED(int len), void *priv) { const voodoo_t *voodoo = (voodoo_t *) priv; @@ -1069,7 +1069,7 @@ voodoo_pci_read(int func, int addr, void *priv) } void -voodoo_pci_write(int func, int addr, uint8_t val, void *priv) +voodoo_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { voodoo_t *voodoo = (voodoo_t *) priv; diff --git a/src/video/vid_voodoo_banshee.c b/src/video/vid_voodoo_banshee.c index f914c7e86..f6f0476ad 100644 --- a/src/video/vid_voodoo_banshee.c +++ b/src/video/vid_voodoo_banshee.c @@ -3066,7 +3066,7 @@ banshee_vsync_callback(svga_t *svga) } static uint8_t -banshee_pci_read(int func, int addr, void *priv) +banshee_pci_read(int func, int addr, UNUSED(int len), void *priv) { const banshee_t *banshee = (banshee_t *) priv; #if 0 @@ -3276,7 +3276,7 @@ banshee_pci_read(int func, int addr, void *priv) } static void -banshee_pci_write(int func, int addr, uint8_t val, void *priv) +banshee_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv) { banshee_t *banshee = (banshee_t *) priv; #if 0 From 01779aaf4edefb91b9ed9d2c49fe418c31174d8c Mon Sep 17 00:00:00 2001 From: kotochi98 <185547947+kotochi98@users.noreply.github.com> Date: Sat, 24 Jan 2026 13:49:46 +0300 Subject: [PATCH 3/7] Add the beta evaluation BIOS for the MiTAC 6110zu and set the R804 retail BIOS as the default --- src/machine/m_at_slot1.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c index 713ab09c0..cbd0cdec5 100644 --- a/src/machine/m_at_slot1.c +++ b/src/machine/m_at_slot1.c @@ -1431,20 +1431,20 @@ static const device_config_t vei8_config[] = { .name = "bios", .description = "BIOS Version", .type = CONFIG_BIOS, - .default_string = "vei8", + .default_string = "6110zu", .default_int = 0, .file_filter = NULL, .spinner = { 0 }, .selection = { { 0 } }, .bios = { { - .name = "Award Modular BIOS v6.00PG - Revision QHW.10.01 (HP Sherwood-B)", - .internal_name = "vei8", + .name = "Award Modular BIOS v6.00PG - Revision 61100003 (beta)", + .internal_name = "6110zu0003", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 262144, - .files = { "roms/machines/vei8/QHW1001.BIN", "" } + .files = { "roms/machines/vei8/61100003.BIN", "" } }, { .name = "Award Modular BIOS v6.00PG - Revision R804", @@ -1455,6 +1455,15 @@ static const device_config_t vei8_config[] = { .size = 262144, .files = { "roms/machines/vei8/r804.bin", "" } }, + { + .name = "Award Modular BIOS v6.00PG - Revision QHW.10.01 (HP Sherwood-B)", + .internal_name = "vei8", + .bios_type = BIOS_NORMAL, + .files_no = 1, + .local = 0, + .size = 262144, + .files = { "roms/machines/vei8/QHW1001.BIN", "" } + }, { .files_no = 0 } } }, From 6d668558dccc59a9f44d1c37530e8753cc3ae78f Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 24 Jan 2026 16:25:21 +0100 Subject: [PATCH 4/7] NMC 93cXX EEPROM: Remove the left-over NULL check in nmc_93cxx_eeperom_data(). --- src/mem/nmc93cxx.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mem/nmc93cxx.c b/src/mem/nmc93cxx.c index 17d97591e..dada96454 100644 --- a/src/mem/nmc93cxx.c +++ b/src/mem/nmc93cxx.c @@ -265,8 +265,6 @@ nmc93cxx_eeprom_close(void *priv) uint16_t * nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom) { - if (UNLIKELY(eeprom == NULL)) - return NULL; /* Get EEPROM data array. */ return &eeprom->dev.data[0]; } From fb03df6feb446440c27b552e0c4be9eccc523bbb Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 24 Jan 2026 17:55:20 +0100 Subject: [PATCH 5/7] Cirrus Logic: Reintroduce the thunks to SVGA reads/writes removed in build 5479, fixes E-Ten Chinese System. --- src/video/vid_cl54xx.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index cec60332e..089b2ec7f 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -2288,8 +2288,14 @@ gd54xx_write(uint32_t addr, uint8_t val, void *priv) xga_write_test(addr, val, svga); + if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) { + svga_write(addr, val, svga); + return; + } + addr &= svga->banked_mask; addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1]; + svga_write_linear(addr, val, svga); } @@ -2312,6 +2318,11 @@ gd54xx_writew(uint32_t addr, uint16_t val, void *priv) xga_write_test(addr, val, svga); xga_write_test(addr + 1, val >> 8, svga); + if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) { + svga_writew(addr, val, svga); + return; + } + addr &= svga->banked_mask; addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1]; @@ -2346,6 +2357,11 @@ gd54xx_writel(uint32_t addr, uint32_t val, void *priv) xga_write_test(addr + 2, val >> 16, svga); xga_write_test(addr + 3, val >> 24, svga); + if ((svga->seqregs[0x07] & 0x01) == 0) { + svga_writel(addr, val, svga); + return; + } + addr &= svga->banked_mask; addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1]; @@ -2898,6 +2914,9 @@ gd54xx_read(uint32_t addr, void *priv) svga_t *svga = (svga_t *) priv; gd54xx_t *gd54xx = (gd54xx_t *) svga->local; + if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) + return svga_read(addr, svga); + if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) return gd54xx_mem_sys_dest_read(gd54xx, 0); @@ -2916,6 +2935,9 @@ gd54xx_readw(uint32_t addr, void *priv) gd54xx_t *gd54xx = (gd54xx_t *) svga->local; uint16_t ret; + if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) + return svga_readw(addr, svga); + if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) { ret = gd54xx_read(addr, svga); @@ -2938,6 +2960,9 @@ gd54xx_readl(uint32_t addr, void *priv) gd54xx_t *gd54xx = (gd54xx_t *) svga->local; uint32_t ret; + if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) + return svga_readl(addr, svga); + if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) { ret = gd54xx_read(addr, svga); From f491069512eeae3b8f3d6c88e4619484e176bc3b Mon Sep 17 00:00:00 2001 From: OBattler Date: Sun, 25 Jan 2026 00:46:42 +0100 Subject: [PATCH 6/7] Trident TGUI: Remove excess logging. --- src/video/vid_tgui9440.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video/vid_tgui9440.c b/src/video/vid_tgui9440.c index 2a76ee2a4..f91fc3f96 100644 --- a/src/video/vid_tgui9440.c +++ b/src/video/vid_tgui9440.c @@ -784,7 +784,7 @@ tgui_recalctimings(svga_t *svga) else if (svga->gdcreg[0xf] & 0x40) svga->clock *= 3.0; - pclog("GDCREGF=%02x, miscout=%02x.\n", svga->gdcreg[0xf] & 0x48, svga->miscout & 0x0c); + // pclog("GDCREGF=%02x, miscout=%02x.\n", svga->gdcreg[0xf] & 0x48, svga->miscout & 0x0c); } else { //pclog("TGUI9400CXi: Clock double=%d.\n", (((svga->miscout >> 2) & 3) | ((tgui->newctrl2 << 2) & 4) | ((tgui->newctrl2 >> 3) & 8))); switch (((svga->miscout >> 2) & 3) | ((tgui->newctrl2 << 2) & 4) | ((tgui->newctrl2 >> 3) & 8)) { From ca37758018206ba764d867dd44e95258a24454c2 Mon Sep 17 00:00:00 2001 From: Dmitry Borisov Date: Sun, 25 Jan 2026 08:40:56 +0600 Subject: [PATCH 7/7] nmc93cxx: Rewrite the nmc93cxx emulation This patch rewrites the nmc93cxx emulation code. The primary aim of the rewrite is to fix the Qlogic 1080 BIOS v1.11 flashing feature (the card utilizes a 93C56 chip in 128x16 mode). This work is derived from the MAME serial EEPROM emulation code written by Aaron Giles and published under BSD-3-Clause license. https://github.com/mamedev/mame/blob/master/src/devices/machine/eepromser.cpp The code is modelled on the MAME code with the following differences: - Removed support for the ER5911 and MSM16911 EEPROM devices. - Removed support for the X24C44 NOVRAM device. - Removed support for the Seiko S-29X90 EEPROM devices. The 86Box changes: - The nmc93cxx code now also supports EEPROM devices in 8-bit mode. - Make the default_content parameter optional. - Make the nmc93cxx_eeprom_data function to return a const pointer. --- src/include/86box/nmc93cxx.h | 79 +++- src/mem/nmc93cxx.c | 765 +++++++++++++++++++++++++++-------- src/network/net_ne2000.c | 17 +- src/network/net_rtl8139.c | 8 +- src/network/net_tulip.c | 8 +- src/scsi/scsi_pcscsi.c | 15 +- src/video/vid_s3.c | 6 +- 7 files changed, 669 insertions(+), 229 deletions(-) diff --git a/src/include/86box/nmc93cxx.h b/src/include/86box/nmc93cxx.h index dd02b2d06..b8c9d61b6 100644 --- a/src/include/86box/nmc93cxx.h +++ b/src/include/86box/nmc93cxx.h @@ -1,25 +1,72 @@ -#include <86box/vid_ati_eeprom.h> +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Header of the emulation of the National Semiconductors NMC93Cxx EEPROMs + * (16 bits or 8 bits). + * + * Authors: Cacodemon345 + * + * Copyright 2023 Cacodemon345 + */ +#pragma once -typedef struct nmc93cxx_eeprom_t { - ati_eeprom_t dev; - uint8_t addrbits; - uint16_t size; - char filename[1024]; -} nmc93cxx_eeprom_t; +/* Forward declaration to hide internal device state from users. */ +typedef struct nmc93cxx_eeprom_t nmc93cxx_eeprom_t; +/* EEPROM device type used to specify the size of data array. */ +typedef enum nmc93cxx_eeprom_type { + /* + * Standard 93CX6 class of 16-bit EEPROMs. + * + * Type / Bits per cell / Number of cells + */ + NMC_93C06_x16_16, + NMC_93C46_x16_64, + NMC_93C56_x16_128, + NMC_93C57_x16_128, + NMC_93C66_x16_256, + NMC_93C76_x16_512, + NMC_93C86_x16_1024, + + /* + * Some manufacturers use pin 6 as an "ORG" pin which, + * when pulled low, configures memory for 8-bit accesses. + * + * Type / Bits per cell / Number of cells + */ + NMC_93C46_x8_128, + NMC_93C56_x8_256, + NMC_93C57_x8_256, + NMC_93C66_x8_512, + NMC_93C76_x8_1024, + NMC_93C86_x8_2048, +} nmc93cxx_eeprom_type; + +/* EEPROM device parameters. */ typedef struct nmc93cxx_eeprom_params_t { - uint16_t nwords; - char *filename; - uint16_t *default_content; + /* Device type */ + nmc93cxx_eeprom_type type; + /* Name of EEPROM image file */ + const char *filename; + /* + * Optional pointer to the default data buffer. + * The buffer size should match the size of EEPROM data array specified by nmc93cxx_eeprom_type. + */ + const void *default_content; } nmc93cxx_eeprom_params_t; -/* Read from the EEPROM. */ -uint16_t nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom); +/* Read the state of the data output (DO) line. */ +bool nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *dev); -/* Write to the EEPROM. */ -void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi); +/* Set the state of the input lines. */ +void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *dev, bool eecs, bool eesk, bool eedi); -/* Get EEPROM data array. */ -uint16_t *nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom); +/* Returns pointer to the current EEPROM data array. */ +const uint16_t *nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *dev); extern const device_t nmc93cxx_device; diff --git a/src/mem/nmc93cxx.c b/src/mem/nmc93cxx.c index dada96454..c998fb825 100644 --- a/src/mem/nmc93cxx.c +++ b/src/mem/nmc93cxx.c @@ -6,267 +6,676 @@ * * This file is part of the 86Box distribution. * - * Emulation of National Semiconductors NMC93Cxx EEPROMs. + * Emulation of National Semiconductors NMC93Cxx EEPROMs (16 bits or 8 bits). * * Authors: Cacodemon345 * * Copyright 2023 Cacodemon345 */ -/* Ported over from QEMU */ +/* Ported over from the MAME eepromser.cpp implementation. Copyright 2013 Aaron Giles */ + +#ifdef ENABLE_NMC93CXX_EEPROM_LOG +#include +#endif #include #include +#include #include #include -#include +#include #include #include -#define HAVE_STDARG_H +#include + #include <86box/86box.h> #include <86box/device.h> #include <86box/timer.h> #include <86box/nvr.h> +#include <86box/log.h> #include <86box/nmc93cxx.h> #include <86box/plat_unused.h> +#define WRITE_TIME_US 1750 +#define WRITE_ALL_TIME_US 8000 +#define ERASE_TIME_US 1000 +#define ERASE_ALL_TIME_US 8000 + +typedef enum EepromCommand { + COMMAND_INVALID, + COMMAND_READ, + COMMAND_WRITE, + COMMAND_ERASE, + COMMAND_LOCK, + COMMAND_UNLOCK, + COMMAND_WRITEALL, + COMMAND_ERASEALL, + COMMAND_COPY_EEPROM_TO_RAM, + COMMAND_COPY_RAM_TO_EEPROM +} EepromCommand; + +typedef enum EepromState { + STATE_IN_RESET, + STATE_WAIT_FOR_START_BIT, + STATE_WAIT_FOR_COMMAND, + STATE_READING_DATA, + STATE_WAIT_FOR_DATA, + STATE_WAIT_FOR_COMPLETION +} EepromState; + +typedef enum EepromEvent { + EVENT_CS_RISING_EDGE = 1 << 0, + EVENT_CS_FALLING_EDGE = 1 << 1, + EVENT_CLK_RISING_EDGE = 1 << 2, + EVENT_CLK_FALLING_EDGE = 1 << 3 +} EepromEvent; + +struct nmc93cxx_eeprom_t { + /* Command completion timer */ + pc_timer_t cmd_complete_timer; + /* Write tick */ + uint32_t write_tick; + /* State of the CS line */ + bool cs_state; + /* State of the CLK line */ + bool clk_state; + /* State of the DI line */ + bool di_state; + /* READY/BUSY status during a programming operation */ + bool is_busy; + /* Internal device state */ + EepromState state; + /* Accumulator of command+address bits */ + uint32_t command_address_accum; + /* Current address extracted from command */ + uint32_t address; + /* Holds data coming in/going out */ + uint32_t shift_register; + /* Number of bits accumulated */ + uint32_t bits_accum; + /* Current command */ + EepromCommand command; + /* Number of memory cells */ + uint16_t cells; + /* Number of bits per cell */ + uint16_t data_bits; + /* Number of address bits in a command */ + uint8_t command_address_bits; + /* Number of address bits in an address */ + uint8_t address_bits; + /* Are we locked against writes? */ + bool is_locked; + /* Tick of the last CS rising edge */ + uint32_t last_cs_rising_edge_tick; + /* Device logging */ + void *log; + /* Name of EEPROM image file */ + char filename[1024]; + + /* EEPROM image words, must be the last structure member */ + uint16_t array_data[]; +}; + #ifdef ENABLE_NMC93CXX_EEPROM_LOG int nmc93cxx_eeprom_do_log = ENABLE_NMC93CXX_EEPROM_LOG; static void -nmc93cxx_eeprom_log(int lvl, const char *fmt, ...) +nmc93cxx_eeprom_log(nmc93cxx_eeprom_t *dev, int lvl, const char *fmt, ...) { va_list ap; if (nmc93cxx_eeprom_do_log >= lvl) { va_start(ap, fmt); - pclog_ex(fmt, ap); + log_out(dev->log, fmt, ap); va_end(ap); } } #else -# define nmc93cxx_eeprom_log(lvl, fmt, ...) +# define nmc93cxx_eeprom_log(dev, lvl, fmt, ...) #endif +#define MAKE_CASE(x) case x: return #x; +static char* +nmc93cxx_eeprom_state_to_name(EepromState state) +{ + switch (state) { + MAKE_CASE(STATE_IN_RESET); + MAKE_CASE(STATE_WAIT_FOR_START_BIT); + MAKE_CASE(STATE_WAIT_FOR_COMMAND); + MAKE_CASE(STATE_READING_DATA); + MAKE_CASE(STATE_WAIT_FOR_DATA); + MAKE_CASE(STATE_WAIT_FOR_COMPLETION); + default: return ""; + } +} + +static char* +nmc93cxx_eeprom_cmd_to_name(EepromCommand command) +{ + switch (command) { + MAKE_CASE(COMMAND_INVALID); + MAKE_CASE(COMMAND_READ); + MAKE_CASE(COMMAND_WRITE); + MAKE_CASE(COMMAND_ERASE); + MAKE_CASE(COMMAND_LOCK); + MAKE_CASE(COMMAND_UNLOCK); + MAKE_CASE(COMMAND_WRITEALL); + MAKE_CASE(COMMAND_ERASEALL); + MAKE_CASE(COMMAND_COPY_EEPROM_TO_RAM); + MAKE_CASE(COMMAND_COPY_RAM_TO_EEPROM); + default: return ""; + } +} +#undef MAKE_CASE + +static void +nmc93cxx_eeprom_set_state(nmc93cxx_eeprom_t *dev, EepromState state) +{ + if (dev->state != state) { + nmc93cxx_eeprom_log(dev, 2, "EEPROM: New state %s\n", nmc93cxx_eeprom_state_to_name(state)); + } + dev->state = state; +} + +static void +nmc93cxx_eeprom_cmd_complete_timer_callback(void *priv) +{ + nmc93cxx_eeprom_t *dev = priv; + + dev->is_busy = false; +} + +static void +nmc93cxx_eeprom_start_cmd_timer(nmc93cxx_eeprom_t *dev, double period) +{ + dev->is_busy = true; + timer_on_auto(&dev->cmd_complete_timer, period); +} + static void * nmc93cxx_eeprom_init(const device_t *info) { - uint16_t nwords = 64; - uint8_t addrbits = 6; - uint8_t filldefault = 1; nmc93cxx_eeprom_params_t *params_details = (nmc93cxx_eeprom_params_t *) info->local; - nmc93cxx_eeprom_t *eeprom = NULL; - if (info->local == 0) - return NULL; + nmc93cxx_eeprom_t *dev; + bool fill_default = true; + uint16_t cells, nwords, data_bits; + uint8_t addrbits; - nwords = params_details->nwords; + /* Check for mandatory parameters */ + assert(params_details != NULL); + assert(params_details->filename != NULL); - switch (nwords) { - case 16: - case 64: + switch (params_details->type) { + /* 16-bit EEPROMs */ + case NMC_93C06_x16_16: + cells = 16; addrbits = 6; + data_bits = 16; break; - case 128: - case 256: + case NMC_93C46_x16_64: + cells = 64; + addrbits = 6; + data_bits = 16; + break; + case NMC_93C56_x16_128: + cells = 128; addrbits = 8; + data_bits = 16; break; + case NMC_93C57_x16_128: + cells = 128; + addrbits = 7; + data_bits = 16; + break; + case NMC_93C66_x16_256: + cells = 256; + addrbits = 8; + data_bits = 16; + break; + case NMC_93C76_x16_512: + cells = 512; + addrbits = 10; + data_bits = 16; + break; + case NMC_93C86_x16_1024: + cells = 1024; + addrbits = 10; + data_bits = 16; + break; + + /* 8-bit EEPROMs */ + case NMC_93C46_x8_128: + cells = 128; + addrbits = 7; + data_bits = 8; + break; + case NMC_93C56_x8_256: + cells = 256; + addrbits = 9; + data_bits = 8; + break; + case NMC_93C57_x8_256: + cells = 256; + addrbits = 8; + data_bits = 8; + break; + case NMC_93C66_x8_512: + cells = 512; + addrbits = 9; + data_bits = 8; + break; + case NMC_93C76_x8_1024: + cells = 1024; + addrbits = 11; + data_bits = 8; + break; + case NMC_93C86_x8_2048: + cells = 1024; + addrbits = 11; + data_bits = 8; + break; + default: - nwords = 64; - addrbits = 6; + /* Invalid parameter passed to the device */ + assert(false); break; } - eeprom = calloc(1, sizeof(nmc93cxx_eeprom_t) + ((nwords + 1) * 2)); - if (!eeprom) + + /* The "ORG" pin can select the x8 or x16 memory organization */ + if (data_bits == 16) { + nwords = cells; + } else { + nwords = cells / 2; + + assert(data_bits == 8); + } + + dev = calloc(1, offsetof(nmc93cxx_eeprom_t, array_data[nwords])); + if (!dev) return NULL; - eeprom->size = nwords; - eeprom->addrbits = addrbits; - /* Output DO is tristate, read results in 1. */ - eeprom->dev.out = 1; + dev->cells = cells; + dev->command_address_bits = addrbits; + dev->data_bits = data_bits; + dev->is_locked = true; + dev->command = COMMAND_INVALID; + dev->log = log_open("nmc93cxx"); + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); - if (params_details->filename) { - FILE *fp = nvr_fopen(params_details->filename, "rb"); - strncpy(eeprom->filename, params_details->filename, sizeof(eeprom->filename) - 1); - if (fp) { - filldefault = !fread(eeprom->dev.data, sizeof(uint16_t), nwords, fp); - fclose(fp); - } + /* Load the EEPROM image */ + snprintf(dev->filename, sizeof(dev->filename), "%s", params_details->filename); + FILE *fp = nvr_fopen(dev->filename, "rb"); + if (fp) { + fill_default = !fread(dev->array_data, dev->data_bits / 8, dev->cells, fp); + fclose(fp); + } + if (fill_default && params_details->default_content) { + memcpy(dev->array_data, params_details->default_content, dev->cells * (dev->data_bits / 8)); } - if (filldefault) { - memcpy(eeprom->dev.data, params_details->default_content, nwords * sizeof(uint16_t)); + /* Compute address bits */ + uint32_t count = dev->cells - 1; + dev->address_bits = 0; + while (count != 0) { + count >>= 1; + dev->address_bits++; } - return eeprom; + timer_add(&dev->cmd_complete_timer, nmc93cxx_eeprom_cmd_complete_timer_callback, dev, 0); + + return dev; +} + +static uint32_t +nmc93cxx_eeprom_cell_read(nmc93cxx_eeprom_t *dev, uint32_t address) +{ + if (dev->data_bits == 16) { + return dev->array_data[address]; + } else { + return *((uint8_t *)dev->array_data + address); + } } static void -nmc93cxx_eeprom_save(nmc93cxx_eeprom_t *eeprom) +nmc93cxx_eeprom_cell_write(nmc93cxx_eeprom_t *dev, uint32_t address, uint32_t data) { - FILE *fp = nvr_fopen(eeprom->filename, "wb"); - if (!fp) - return; - fwrite(eeprom->dev.data, 2, eeprom->size, fp); - fclose(fp); + if (dev->data_bits == 16) { + dev->array_data[address] = data; + } else { + *((uint8_t *)dev->array_data + address) = data; + } +} + +static void +nmc93cxx_eeprom_handle_cmd_write(nmc93cxx_eeprom_t *dev, uint32_t address, uint32_t data) +{ + nmc93cxx_eeprom_log(dev, 1, "EEPROM: WR %08lX <-- %X\n", address, data); + + nmc93cxx_eeprom_cell_write(dev, address, data); + nmc93cxx_eeprom_start_cmd_timer(dev, WRITE_TIME_US); +} + +static void +nmc93cxx_eeprom_handle_cmd_write_all(nmc93cxx_eeprom_t *dev, uint32_t data) +{ + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Write all operation %X\n", data); + + for (uint32_t address = 0; address < (1 << dev->address_bits); ++address) { + nmc93cxx_eeprom_cell_write(dev, address, nmc93cxx_eeprom_cell_read(dev, address) & data); + } + + nmc93cxx_eeprom_start_cmd_timer(dev, WRITE_ALL_TIME_US); +} + +static void +nmc93cxx_eeprom_handle_cmd_erase(nmc93cxx_eeprom_t *dev, uint32_t address) +{ + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Erase data at %08lx\n", address); + + nmc93cxx_eeprom_cell_write(dev, address, ~0); + nmc93cxx_eeprom_start_cmd_timer(dev, ERASE_TIME_US); +} + +static void +nmc93cxx_eeprom_handle_cmd_erase_all(nmc93cxx_eeprom_t *dev) +{ + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Erase all operation\n"); + + for (uint32_t address = 0; address < (1 << dev->address_bits); ++address) { + nmc93cxx_eeprom_cell_write(dev, address, ~0); + } + + nmc93cxx_eeprom_start_cmd_timer(dev, ERASE_ALL_TIME_US); +} + +static void +nmc93cxx_eeprom_parse_command_and_address(nmc93cxx_eeprom_t *dev) +{ + dev->address = dev->command_address_accum & ((1 << dev->command_address_bits) - 1); + + /* Extract the command portion and handle it */ + switch (dev->command_address_accum >> dev->command_address_bits) { + /* Opcode 0 needs two more bits to decode the operation */ + case 0: + switch (dev->address >> (dev->command_address_bits - 2)) { + case 0: dev->command = COMMAND_LOCK; break; + case 1: dev->command = COMMAND_WRITEALL; break; + case 2: dev->command = COMMAND_ERASEALL; break; + case 3: dev->command = COMMAND_UNLOCK; break; + } + dev->address = 0; + break; + + case 1: dev->command = COMMAND_WRITE; break; + case 2: dev->command = COMMAND_READ; break; + case 3: dev->command = COMMAND_ERASE; break; + + default: + dev->command = COMMAND_INVALID; + break; + } + + if (dev->address >= (1 << dev->address_bits)) { + nmc93cxx_eeprom_log(dev, 1, "EEPROM: out-of-range address 0x%X provided (maximum should be 0x%X)\n", dev->address, (1 << dev->address_bits) - 1); + } +} + +static void +nmc93cxx_eeprom_execute_command(nmc93cxx_eeprom_t *dev) +{ + /* Parse into a generic command and reset the accumulator count */ + nmc93cxx_eeprom_parse_command_and_address(dev); + dev->bits_accum = 0; + + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Execute command %s\n", nmc93cxx_eeprom_cmd_to_name(dev->command)); + switch (dev->command) { + /* + * Advance to the READING_DATA state; data is fetched after first CLK + * reset the shift register to 0 to simulate the dummy 0 bit that happens prior + * to the first clock + */ + case COMMAND_READ: + dev->shift_register = 0; + nmc93cxx_eeprom_set_state(dev, STATE_READING_DATA); + break; + + /* Reset the shift register and wait for enough data to be clocked through */ + case COMMAND_WRITE: + case COMMAND_WRITEALL: + dev->shift_register = 0; + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_DATA); + break; + + /* Erase the parsed address (unless locked) and wait for it to complete */ + case COMMAND_ERASE: + if (dev->is_locked) { + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to erase while locked\n"); + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + } + nmc93cxx_eeprom_handle_cmd_erase(dev, dev->address); + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION); + break; + + /* Lock the chip; return to IN_RESET state */ + case COMMAND_LOCK: + dev->is_locked = true; + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + + /* Unlock the chip; return to IN_RESET state */ + case COMMAND_UNLOCK: + dev->is_locked = false; + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + + /* Erase the entire chip (unless locked) and wait for it to complete */ + case COMMAND_ERASEALL: + if (dev->is_locked) { + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to erase all while locked\n"); + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + } + nmc93cxx_eeprom_handle_cmd_erase_all(dev); + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION); + break; + + default: + nmc93cxx_eeprom_log(dev, 1, "execute_command called with invalid command %d\n", dev->command); + assert(false); + break; + } +} + +static void +nmc93cxx_eeprom_execute_write_command(nmc93cxx_eeprom_t *dev) +{ + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Execute write command %s\n", nmc93cxx_eeprom_cmd_to_name(dev->command)); + + switch (dev->command) { + /* Reset the shift register and wait for enough data to be clocked through */ + case COMMAND_WRITE: + if (dev->is_locked) { + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to write to address 0x%X while locked\n", dev->address); + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + } + nmc93cxx_eeprom_handle_cmd_write(dev, dev->address, dev->shift_register); + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION); + break; + + /* + * Write the entire EEPROM with the same data; ERASEALL is required before so we + * AND against the already-present data + */ + case COMMAND_WRITEALL: + if (dev->is_locked) { + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to write all while locked\n"); + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + } + nmc93cxx_eeprom_handle_cmd_write_all(dev, dev->shift_register); + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION); + break; + + default: + nmc93cxx_eeprom_log(dev, 1, "execute_command called with invalid command %d\n", dev->command); + assert(false); + break; + } +} + +static void +nmc93cxx_eeprom_handle_event(nmc93cxx_eeprom_t *dev, EepromEvent event) +{ + switch (dev->state) { + /* CS is not asserted; wait for a rising CS to move us forward, ignoring all clocks */ + case STATE_IN_RESET: + if (event == EVENT_CS_RISING_EDGE) + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_START_BIT); + break; + + /* + * CS is asserted; wait for rising clock with a 1 start bit; falling CS will reset us + * note that because each bit is written independently, it is possible for us to receive + * a false rising CLK edge at the exact same time as a rising CS edge; it appears we + * should ignore these edges (makes sense really) + */ + case STATE_WAIT_FOR_START_BIT: + if ((event == EVENT_CLK_RISING_EDGE) && dev->di_state && !dev->is_busy && (dev->write_tick != dev->last_cs_rising_edge_tick)) { + dev->command_address_accum = 0; + dev->bits_accum = 0; + nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMMAND); + } else if (event == EVENT_CS_FALLING_EDGE) + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + + /* CS is asserted; wait for a command to come through; falling CS will reset us */ + case STATE_WAIT_FOR_COMMAND: + if (event == EVENT_CLK_RISING_EDGE) { + /* If we have enough bits for a command + address, check it out */ + dev->command_address_accum = (dev->command_address_accum << 1) | dev->di_state; + if (++dev->bits_accum == 2 + dev->command_address_bits) + nmc93cxx_eeprom_execute_command(dev); + } else if (event == EVENT_CS_FALLING_EDGE) + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + + /* CS is asserted; reading data, clock the shift register; falling CS will reset us */ + case STATE_READING_DATA: + if (event == EVENT_CLK_RISING_EDGE) { + uint32_t bit_index = dev->bits_accum++; + + /* Wrapping the address on multi-read */ + if (((bit_index % dev->data_bits) == 0) && (bit_index == 0)) + { + uint32_t addr = (dev->address + dev->bits_accum / dev->data_bits) & ((1 << dev->address_bits) - 1); + uint32_t data = nmc93cxx_eeprom_cell_read(dev, addr); + + nmc93cxx_eeprom_log(dev, 1, "EEPROM: RD %08lX --> %X\n", addr, data); + + dev->shift_register = data << (32 - dev->data_bits); + } else { + dev->shift_register = (dev->shift_register << 1) | 1; + } + } else if (event == EVENT_CS_FALLING_EDGE) { + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + + if (dev->bits_accum > (dev->data_bits + 1)) + nmc93cxx_eeprom_log(dev, 1, "EEPROM: Overclocked read by %d bits\n", dev->bits_accum - dev->data_bits); + else if (dev->bits_accum < dev->data_bits) + nmc93cxx_eeprom_log(dev, 1, "EEPROM: CS deasserted in READING_DATA after %d bits\n", dev->bits_accum); + } + break; + + /* CS is asserted; waiting for data; clock data through until we accumulate enough; falling CS will reset us */ + case STATE_WAIT_FOR_DATA: + if (event == EVENT_CLK_RISING_EDGE) { + dev->shift_register = (dev->shift_register << 1) | dev->di_state; + if (++dev->bits_accum == dev->data_bits) + nmc93cxx_eeprom_execute_write_command(dev); + } else if (event == EVENT_CS_FALLING_EDGE) { + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + nmc93cxx_eeprom_log(dev, 1, "EEPROM: CS deasserted in STATE_WAIT_FOR_DATA after %d bits\n", dev->bits_accum); + } + break; + + /* CS is asserted; waiting for completion; watch for CS falling */ + case STATE_WAIT_FOR_COMPLETION: + if (event == EVENT_CS_FALLING_EDGE) + nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET); + break; + + default: + break; + } } void -nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi) +nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *dev, bool eecs, bool eesk, bool eedi) { - uint8_t tick = eeprom->dev.count; - uint8_t eedo = eeprom->dev.out; - uint16_t address = eeprom->dev.address; - uint8_t command = eeprom->dev.opcode; + assert(dev != NULL); - nmc93cxx_eeprom_log(1, "CS=%u SK=%u DI=%u DO=%u, tick = %u\n", - eecs, eesk, eedi, eedo, tick); + dev->write_tick++; - if (!eeprom->dev.oldena && eecs) { - /* Start chip select cycle. */ - nmc93cxx_eeprom_log(1, "Cycle start, waiting for 1st start bit (0)\n"); - tick = 0; - command = 0x0; - address = 0x0; - } else if (eeprom->dev.oldena && !eecs) { - /* End chip select cycle. This triggers write / erase. */ - if (!eeprom->dev.wp) { - uint8_t subcommand = address >> (eeprom->addrbits - 2); - if (command == 0 && subcommand == 2) { - /* Erase all. */ - for (address = 0; address < eeprom->size; address++) - eeprom->dev.data[address] = 0xffff; + nmc93cxx_eeprom_log(dev, 3, "EEPROM: CS=%u SK=%u DI=%u DO=%u, tick = %u\n", + eecs, eesk, eedi, nmc93cxx_eeprom_read(dev), dev->write_tick); - nmc93cxx_eeprom_save(eeprom); - } else if (command == 3) { - /* Erase word. */ - eeprom->dev.data[address] = 0xffff; - nmc93cxx_eeprom_save(eeprom); - } else if (tick >= (2 + 2 + eeprom->addrbits + 16)) { - if (command == 1) { - /* Write word. */ - eeprom->dev.data[address] &= eeprom->dev.dat; - nmc93cxx_eeprom_save(eeprom); - } else if (command == 0 && subcommand == 1) { - /* Write all. */ - for (address = 0; address < eeprom->size; address++) - eeprom->dev.data[address] &= eeprom->dev.dat; + if (dev->cs_state != eecs) { + dev->cs_state = eecs; - nmc93cxx_eeprom_save(eeprom); - } - } + /* Remember the rising edge tick so we don't process CLK signals at the same time */ + if (eecs) { + dev->last_cs_rising_edge_tick = dev->write_tick; } - /* Output DO is tristate, read results in 1. */ - eedo = 1; - } else if (eecs && !eeprom->dev.oldclk && eesk) { - /* Raising edge of clock shifts data in. */ - if (tick == 0) { - /* Wait for 1st start bit. */ - if (eedi == 0) { - nmc93cxx_eeprom_log(1, "Got correct 1st start bit, waiting for 2nd start bit (1)\n"); - tick++; - } else { - nmc93cxx_eeprom_log(1, "wrong 1st start bit (is 1, should be 0)\n"); - tick = 2; -#if 0 - ~ assert(!"wrong start bit"); -#endif - } - } else if (tick == 1) { - /* Wait for 2nd start bit. */ - if (eedi != 0) { - nmc93cxx_eeprom_log(1, "Got correct 2nd start bit, getting command + address\n"); - tick++; - } else { - nmc93cxx_eeprom_log(1, "1st start bit is longer than needed\n"); - } - } else if (tick < 2 + 2) { - /* Got 2 start bits, transfer 2 opcode bits. */ - tick++; - command <<= 1; - if (eedi) { - command += 1; - } - } else if (tick < 2 + 2 + eeprom->addrbits) { - /* Got 2 start bits and 2 opcode bits, transfer all address bits. */ - tick++; - address = ((address << 1) | eedi); - if (tick == 2 + 2 + eeprom->addrbits) { - nmc93cxx_eeprom_log(1, "Address = 0x%02x (value 0x%04x)\n", - address, eeprom->dev.data[address]); - if (command == 2) { - eedo = 0; - } - address = address % eeprom->size; - if (command == 0) { - /* Command code in upper 2 bits of address. */ - switch (address >> (eeprom->addrbits - 2)) { - case 0: - nmc93cxx_eeprom_log(1, "write disable command\n"); - eeprom->dev.wp = 1; - break; - case 1: - nmc93cxx_eeprom_log(1, "write all command\n"); - break; - case 2: - nmc93cxx_eeprom_log(1, "erase all command\n"); - break; - case 3: - nmc93cxx_eeprom_log(1, "write enable command\n"); - eeprom->dev.wp = 0; - break; - default: - break; - } - } else { - /* Read, write or erase word. */ - eeprom->dev.dat = eeprom->dev.data[address]; - } - } - } else if (tick < 2 + 2 + eeprom->addrbits + 16) { - /* Transfer 16 data bits. */ - tick++; - if (command == 2) { - /* Read word. */ - eedo = ((eeprom->dev.dat & 0x8000) != 0); - } - eeprom->dev.dat <<= 1; - eeprom->dev.dat += eedi; - } else { - nmc93cxx_eeprom_log(1, "additional unneeded tick, not processed\n"); - } + nmc93cxx_eeprom_handle_event(dev, eecs ? EVENT_CS_RISING_EDGE : EVENT_CS_FALLING_EDGE); + } + + dev->di_state = eedi; + + if (dev->clk_state != eesk) { + dev->clk_state = eesk; + nmc93cxx_eeprom_handle_event(dev, eesk ? EVENT_CLK_RISING_EDGE : EVENT_CLK_FALLING_EDGE); } - /* Save status of EEPROM. */ - eeprom->dev.count = tick; - eeprom->dev.oldena = eecs; - eeprom->dev.oldclk = eesk; - eeprom->dev.out = eedo; - eeprom->dev.address = address; - eeprom->dev.opcode = command; } -uint16_t -nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom) +bool +nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *dev) { - /* Return status of pin DO (0 or 1). */ - return eeprom->dev.out; + assert(dev != NULL); + + if (dev->state == STATE_WAIT_FOR_START_BIT) { + /* Read the state of the READY/BUSY line */ + return !dev->is_busy; + } else if (dev->state == STATE_READING_DATA) { + /* Read the current output bit */ + return ((dev->shift_register & 0x80000000) != 0); + } + + /* The DO pin is tristated */ + return true; } static void nmc93cxx_eeprom_close(void *priv) { - nmc93cxx_eeprom_t *eeprom = (nmc93cxx_eeprom_t *) priv; - FILE *fp = nvr_fopen(eeprom->filename, "wb"); + nmc93cxx_eeprom_t *dev = priv; + FILE *fp = nvr_fopen(dev->filename, "wb"); if (fp) { - fwrite(eeprom->dev.data, 2, eeprom->size, fp); + fwrite(dev->array_data, dev->data_bits / 8, dev->cells, fp); fclose(fp); } - free(priv); + log_close(dev->log); + free(dev); } -uint16_t * -nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom) +const uint16_t * +nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *dev) { + assert(dev != NULL); + /* Get EEPROM data array. */ - return &eeprom->dev.data[0]; + return &dev->array_data[0]; } const device_t nmc93cxx_device = { diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index decb23d02..979905385 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -182,7 +182,7 @@ nic_config_reset(void *priv) { nic_t *dev = (nic_t *) priv; - uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); dev->config1 = (data[0x00] & 0x7f) | 0x80; dev->config2 = (data[0x01] & 0xdf); @@ -425,7 +425,7 @@ page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len)) case 0xd: /* CONFIG4 */ if (dev->board == NE2K_RTL8019AS_PNP) { - uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); ret = data[0x03]; } break; @@ -464,7 +464,7 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) if ((val & 0xc0) == 0x80) nmc93cxx_eeprom_write(dev->eeprom, !!(val & 0x08), !!(val & 0x04), !!(val & 0x02)); else if ((val & 0xc0) == 0x40) { - uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); dev->config1 = (data[0x00] & 0x7f) | 0x80; dev->config2 = (data[0x01] & 0xdf); @@ -1391,18 +1391,15 @@ nic_init(const device_t *info) nmc93cxx_eeprom_params_t params; char filename[1024] = { 0 }; - params.nwords = 64; - params.default_content = (uint16_t *) dev->eeprom_data; + params.type = NMC_93C46_x16_64; + params.default_content = dev->eeprom_data; params.filename = filename; int inst = device_get_instance(); snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, inst); dev->eeprom = device_add_inst_params(&nmc93cxx_device, inst, ¶ms); - if (dev->eeprom == NULL) { - free(dev); - return NULL; - } + if (info->local == NE2K_RTL8019AS_PNP) { - uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); dev->config1 = (data[0x00] & 0x7f) | 0x80; dev->config2 = (data[0x01] & 0xdf); diff --git a/src/network/net_rtl8139.c b/src/network/net_rtl8139.c index 5c50f088c..0daf25a6a 100644 --- a/src/network/net_rtl8139.c +++ b/src/network/net_rtl8139.c @@ -3286,15 +3286,11 @@ nic_init(const device_t *info) for (uint32_t i = 0; i < 6; i++) s->phys[MAC0 + i] = mac_bytes[i]; - params.nwords = 64; - params.default_content = (uint16_t *) s->eeprom_data; + params.type = NMC_93C46_x16_64; + params.default_content = s->eeprom_data; params.filename = filename; snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, s->inst); s->eeprom = device_add_inst_params(&nmc93cxx_device, s->inst, ¶ms); - if (s->eeprom == NULL) { - free(s); - return NULL; - } s->nic = network_attach(s, (uint8_t *) &s->phys[MAC0], rtl8139_do_receive, rtl8139_set_link_status); timer_add(&s->timer, rtl8139_timer, s, 0); diff --git a/src/network/net_tulip.c b/src/network/net_tulip.c index e95810cfa..b5219cf23 100644 --- a/src/network/net_tulip.c +++ b/src/network/net_tulip.c @@ -1642,16 +1642,12 @@ nic_init(const device_t *info) } if (info->local != 3) { - params.nwords = 64; - params.default_content = (uint16_t *) s->eeprom_data; + params.type = NMC_93C46_x16_64; + params.default_content = s->eeprom_data; params.filename = filename; int inst = device_get_instance(); snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, inst); s->eeprom = device_add_inst_params(&nmc93cxx_device, inst, ¶ms); - if (s->eeprom == NULL) { - free(s); - return NULL; - } } s->tulip_pci_bar[0].addr_regs[0] = 1; diff --git a/src/scsi/scsi_pcscsi.c b/src/scsi/scsi_pcscsi.c index 51aea3f46..327d35cbb 100644 --- a/src/scsi/scsi_pcscsi.c +++ b/src/scsi/scsi_pcscsi.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -2091,19 +2092,17 @@ esp_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *pr { esp_t *dev = (esp_t *) priv; uint8_t valxor; - int eesk; - int eedi; esp_log("%04X:%08X: ESP PCI: Write value %02X to register %02X\n", CS, cpu_state.pc, val, addr); if (!dev->local) { if ((addr >= 0x80) && (addr <= 0xFF)) { if (addr == 0x80) { - eesk = val & 0x80 ? 1 : 0; - eedi = val & 0x40 ? 1 : 0; - nmc93cxx_eeprom_write(dev->eeprom, 1, eesk, eedi); + bool eesk = !!(val & 0x80); + bool eedi = !!(val & 0x40); + nmc93cxx_eeprom_write(dev->eeprom, true, eesk, eedi); } else if (addr == 0xc0) - nmc93cxx_eeprom_write(dev->eeprom, 0, 0, 0); + nmc93cxx_eeprom_write(dev->eeprom, false, false, false); // esp_log("ESP PCI: Write value %02X to register %02X\n", val, addr); return; } @@ -2300,8 +2299,8 @@ dc390_init(const device_t *info) dev->eeprom_data[EE_CHKSUM1] = checksum & 0xff; dev->eeprom_data[EE_CHKSUM2] = checksum >> 8; - params.nwords = 64; - params.default_content = (uint16_t *) dev->eeprom_data; + params.type = NMC_93C46_x16_64; + params.default_content = dev->eeprom_data; params.filename = filename; snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, dev->eeprom_inst); dev->eeprom = device_add_inst_params(&nmc93cxx_device, dev->eeprom_inst, ¶ms); diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c index 3965391cb..37ade5ad1 100644 --- a/src/video/vid_s3.c +++ b/src/video/vid_s3.c @@ -12237,15 +12237,11 @@ s3_init(const device_t *info) checksum = s3_calc_crc16(64, s3->eeprom_data); s3->eeprom_data[0x00] = checksum; - params.nwords = 64; + params.type = NMC_93C46_x16_64; params.default_content = s3->eeprom_data; params.filename = filename; snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, s3->eeprom_inst); s3->eeprom = device_add_inst_params(&nmc93cxx_device, s3->eeprom_inst, ¶ms); - if (s3->eeprom == NULL) { - free(s3); - return NULL; - } } s3->accel.multifunc[0xd] = 0xd000;