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Merge pull request #16 from 86Box/master

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Merge master
This commit is contained in:
JustinJ553
2021-11-14 19:08:42 +08:00
committed by GitHub
parent 906f856dd0 e24da32acf
commit 79e84b276c
171 changed files with 15602 additions and 5614 deletions
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2
src/cpu/386_common.c
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@@ -591,7 +591,7 @@ smram_restore_state_p5(uint32_t *saved_state)
smm_seg_load(&cpu_state.seg_gs);
if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
smbase = saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET] & 0x00ffffff;
smbase = saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET];
/* Am486/5x86 stuff */
if (!is_pentium) {

34
src/cpu/386_ops.h
View File

@@ -148,9 +148,9 @@ static int fopcode;
static int ILLEGAL(uint32_t fetchdat)
{
pclog("[%04X:%08X] Illegal instruction %08X (%02X)\n", CS, cpu_state.pc, fetchdat, fopcode);
cpu_state.pc = cpu_state.oldpc;
pclog("Illegal instruction %08X (%02X)\n", fetchdat, fopcode);
x86illegal();
return 0;
}
@@ -457,7 +457,7 @@ const OpFn OP_TABLE(386_0f)[1024] =
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_w_r_a16, opMOV_r_b_a16, opMOV_r_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -479,7 +479,7 @@ const OpFn OP_TABLE(386_0f)[1024] =
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_l_r_a16, opMOV_r_b_a16, opMOV_r_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -501,7 +501,7 @@ const OpFn OP_TABLE(386_0f)[1024] =
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_w_r_a32, opMOV_r_b_a32, opMOV_r_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -523,7 +523,7 @@ const OpFn OP_TABLE(386_0f)[1024] =
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_l_r_a32, opMOV_r_b_a32, opMOV_r_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -548,7 +548,7 @@ const OpFn OP_TABLE(486_0f)[1024] =
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_w_r_a16, opMOV_r_b_a16, opMOV_r_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -570,7 +570,7 @@ const OpFn OP_TABLE(486_0f)[1024] =
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_l_r_a16, opMOV_r_b_a16, opMOV_r_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -592,7 +592,7 @@ const OpFn OP_TABLE(486_0f)[1024] =
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_w_r_a32, opMOV_r_b_a32, opMOV_r_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -614,7 +614,7 @@ const OpFn OP_TABLE(486_0f)[1024] =
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_l_r_a32, opMOV_r_b_a32, opMOV_r_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -821,7 +821,7 @@ const OpFn OP_TABLE(ibm486_0f)[1024] =
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_w_r_a16, opMOV_r_b_a16, opMOV_r_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, ILLEGAL, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -843,7 +843,7 @@ const OpFn OP_TABLE(ibm486_0f)[1024] =
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_l_r_a16, opMOV_r_b_a16, opMOV_r_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, ILLEGAL, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -865,7 +865,7 @@ const OpFn OP_TABLE(ibm486_0f)[1024] =
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_w_r_a32, opMOV_r_b_a32, opMOV_r_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, ILLEGAL, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -887,7 +887,7 @@ const OpFn OP_TABLE(ibm486_0f)[1024] =
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_l_r_a32, opMOV_r_b_a32, opMOV_r_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, ILLEGAL, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -1094,7 +1094,7 @@ const OpFn OP_TABLE(pentium_0f)[1024] =
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_w_r_a16, opMOV_r_b_a16, opMOV_r_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -1116,7 +1116,7 @@ const OpFn OP_TABLE(pentium_0f)[1024] =
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a16, opMOV_l_r_a16, opMOV_r_b_a16, opMOV_r_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -1138,7 +1138,7 @@ const OpFn OP_TABLE(pentium_0f)[1024] =
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_w_r_a32, opMOV_r_b_a32, opMOV_r_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -1160,7 +1160,7 @@ const OpFn OP_TABLE(pentium_0f)[1024] =
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ opMOV_b_r_a32, opMOV_l_r_a32, opMOV_r_b_a32, opMOV_r_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,

4
src/cpu/CMakeLists.txt
View File

@@ -24,10 +24,6 @@ if(CYRIX_6X86)
target_compile_definitions(cpu PRIVATE USE_CYRIX_6X86)
endif()
if(M6117)
target_compile_definitions(cpu PRIVATE USE_M6117)
endif()
if(DYNAREC)
add_library(cgt OBJECT codegen_timing_486.c codegen_timing_686.c
codegen_timing_common.c codegen_timing_k6.c

6
src/cpu/cpu.c
View File

@@ -124,6 +124,10 @@ int isa_cycles, cpu_inited,
timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned;
uint32_t cpu_features, cpu_fast_off_flags;
uint32_t _tr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
uint32_t cache_index = 0;
uint8_t _cache[2048];
uint64_t cpu_CR4_mask, tsc = 0;
uint64_t pmc[2] = {0, 0};
@@ -2290,6 +2294,7 @@ amd_k_invalid_rdmsr:
EDX = tsc >> 32;
break;
}
pclog("RDMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
break;
case CPU_PENTIUMPRO:
@@ -2695,6 +2700,7 @@ amd_k_invalid_wrmsr:
case CPU_CxGX1:
case CPU_Cx6x86MX:
#endif
pclog("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
switch (ECX) {
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);

4
src/cpu/cpu.h
View File

@@ -542,6 +542,9 @@ extern uint64_t amd_efer, star;
#define msw cpu_state.CR0.w
extern uint32_t cr2, cr3, cr4;
extern uint32_t dr[8];
extern uint32_t _tr[8];
extern uint32_t cache_index;
extern uint8_t _cache[2048];
/*Segments -
@@ -656,6 +659,7 @@ extern void resetx86(void);
extern void refreshread(void);
extern void resetreadlookup(void);
extern void softresetx86(void);
extern void hardresetx86(void);
extern void x86_int(int num);
extern void x86_int_sw(int num);
extern int x86_int_sw_rm(int num);

2
src/cpu/cpu_table.c
View File

@@ -186,7 +186,6 @@ const cpu_family_t cpu_families[] = {
{"", 0}
}
},
#if defined(DEV_BRANCH) && defined(USE_M6117)
{
.package = CPU_PKG_M6117,
.manufacturer = "ALi",
@@ -198,7 +197,6 @@ const cpu_family_t cpu_families[] = {
{"", 0}
}
},
#endif
{
.package = CPU_PKG_386SLC_IBM,
.manufacturer = "IBM",

36
src/cpu/x86.c
View File

@@ -26,6 +26,8 @@
#include "cpu.h"
#include "x86.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
@@ -239,8 +241,13 @@ reset_common(int hard)
leave_smm();
/* Needed for the ALi M1533. */
if (soft_reset_pci && !hard)
if (is486 && (hard || soft_reset_pci)) {
pci_reset();
if (!hard && soft_reset_pci) {
dma_reset();
device_reset_all();
}
}
use32 = 0;
cpu_cur_status = 0;
@@ -299,7 +306,8 @@ reset_common(int hard)
smi_block = 0;
if (hard) {
smbase = is_am486dxl ? 0x00060000 : 0x00030000;
if (is486)
smbase = is_am486dxl ? 0x00060000 : 0x00030000;
ppi_reset();
}
in_sys = 0;
@@ -307,8 +315,12 @@ reset_common(int hard)
shadowbios = shadowbios_write = 0;
alt_access = cpu_end_block_after_ins = 0;
if (hard)
if (hard) {
reset_on_hlt = hlt_reset_pending = 0;
cache_index = 0;
memset(_tr, 0x00, sizeof(_tr));
memset(_cache, 0x00, sizeof(_cache));
}
if (!is286)
reset_808x(hard);
@@ -334,3 +346,21 @@ softresetx86(void)
reset_common(0);
}
/* Actual hard reset. */
void
hardresetx86(void)
{
dma_reset();
device_reset_all();
cpu_alt_reset = 0;
mem_a20_alt = 0;
mem_a20_recalc();
flushmmucache();
resetx86();
}

2
src/cpu/x86_ops_misc.h
View File

@@ -607,6 +607,8 @@ static int opF7_l_a32(uint32_t fetchdat)
static int opHLT(uint32_t fetchdat)
{
pclog("HLT: CS = %04X, DS = %04X, ES = %04X, SS = %04X, IP = %04X\n", CS, DS, ES, SS, cpu_state.pc);
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
x86gpf(NULL,0);

81
src/cpu/x86_ops_mov_ctrl.h
View File

@@ -256,54 +256,113 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
return 0;
}
static void opMOV_r_TRx(void)
{
uint32_t base;
base = _tr[4] & 0xfffff800;
switch (cpu_reg) {
case 3:
pclog("[R] %08X cache = %08X\n", base + cache_index, _tr[3]);
_tr[3] = *(uint32_t *) &(_cache[cache_index]);
cache_index = (cache_index + 4) & 0xf;
break;
}
cpu_state.regs[cpu_rm].l = _tr[cpu_reg];
CLOCK_CYCLES(6);
}
static int opMOV_r_TRx_a16(uint32_t fetchdat)
{
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
if ((cpu_s->cpu_type == CPU_PENTIUM) || ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1)))
{
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
opMOV_r_TRx();
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_TRx_a32(uint32_t fetchdat)
{
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
if ((cpu_s->cpu_type == CPU_PENTIUM) || ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1)))
{
x86gpf(NULL, 0);
return 1;
}
fetch_ea_32(fetchdat);
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
opMOV_r_TRx();
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
static void opMOV_TRx_r(void)
{
uint32_t base;
int i, ctl;
_tr[cpu_reg] = cpu_state.regs[cpu_rm].l;
base = _tr[4] & 0xfffff800;
ctl = _tr[5] & 3;
switch (cpu_reg) {
case 3:
pclog("[W] %08X cache = %08X\n", base + cache_index, _tr[3]);
*(uint32_t *) &(_cache[cache_index]) = _tr[3];
cache_index = (cache_index + 4) & 0xf;
break;
case 4:
if (!(cr0 & 1) && !(_tr[5] & (1 << 19)))
pclog("TAG = %08X, DEST = %08X\n", base, base + cache_index - 16);
break;
case 5:
pclog("[16] EXT = %i (%i), SET = %04X\n", !!(_tr[5] & (1 << 19)), _tr[5] & 0x03, _tr[5] & 0x7f0);
if (!(_tr[5] & (1 << 19))) {
switch(ctl) {
case 0:
pclog(" Cache fill or read...\n", base);
break;
case 1:
base += (_tr[5] & 0x7f0);
pclog(" Writing 16 bytes to %08X...\n", base);
for (i = 0; i < 16; i += 4)
mem_writel_phys(base + i, *(uint32_t *) &(_cache[i]));
break;
case 2:
base += (_tr[5] & 0x7f0);
pclog(" Reading 16 bytes from %08X...\n", base);
for (i = 0; i < 16; i += 4)
*(uint32_t *) &(_cache[i]) = mem_readl_phys(base + i);
break;
case 3:
pclog(" Cache invalidate/flush...\n", base);
break;
}
}
break;
}
CLOCK_CYCLES(6);
}
static int opMOV_TRx_r_a16(uint32_t fetchdat)
{
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
if ((cpu_s->cpu_type == CPU_PENTIUM) || ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1)))
{
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
opMOV_TRx_r();
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_TRx_r_a32(uint32_t fetchdat)
{
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
if ((cpu_s->cpu_type == CPU_PENTIUM) || ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1)))
{
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
fetch_ea_32(fetchdat);
opMOV_TRx_r();
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}

284
src/cpu/x86seg.c
View File

@@ -942,173 +942,173 @@ void loadcscall(uint16_t seg)
segdat[2] = (segdat[2] & ~(3 << (5+8))) | (CPL << (5+8));
} else /* On non-conforming segments, set RPL = CPL */
seg = (seg & 0xfffc) | CPL;
CS = seg;
do_seg_load(&cpu_state.seg_cs, segdat);
if ((CPL == 3) && (oldcpl != 3))
flushmmucache_cr3();
CS = seg;
do_seg_load(&cpu_state.seg_cs, segdat);
if ((CPL == 3) && (oldcpl != 3))
flushmmucache_cr3();
#ifdef USE_NEW_DYNAREC
oldcpl = CPL;
oldcpl = CPL;
#endif
#ifdef ENABLE_X86SEG_LOG
x86seg_log("Complete\n");
x86seg_log("Complete\n");
#endif
cycles -= timing_call_pm;
} else {
type = segdat[2] & 0x0f00;
x86seg_log("Type %03X\n", type);
switch (type) {
case 0x0400: /* Call gate */
case 0x0c00: /* 386 Call gate */
x86seg_log("Callgate %08X\n", cpu_state.pc);
cgate32 = (type & 0x0800);
cgate16 = !cgate32;
cycles -= timing_call_pm;
} else {
type = segdat[2] & 0x0f00;
x86seg_log("Type %03X\n", type);
switch (type) {
case 0x0400: /* Call gate */
case 0x0c00: /* 386 Call gate */
x86seg_log("Callgate %08X\n", cpu_state.pc);
cgate32 = (type & 0x0800);
cgate16 = !cgate32;
#ifndef USE_NEW_DYNAREC
oldcs = CS;
oldcs = CS;
#endif
count = segdat[2] & 0x001f;
if (DPL < CPL) {
x86gpf("loadcscall(): ex DPL < CPL",seg & 0xfffc);
return;
}
if (DPL < (seg & 0x0003)) {
x86gpf("loadcscall(): ex DPL < RPL", seg & 0xfffc);
return;
}
if (!(segdat[2] & 0x8000)) {
x86np("Call gate not present", seg & 0xfffc);
return;
}
seg2 = segdat[1];
count = segdat[2] & 0x001f;
if (DPL < CPL) {
x86gpf("loadcscall(): ex DPL < CPL",seg & 0xfffc);
return;
}
if (DPL < (seg & 0x0003)) {
x86gpf("loadcscall(): ex DPL < RPL", seg & 0xfffc);
return;
}
if (!(segdat[2] & 0x8000)) {
x86np("Call gate not present", seg & 0xfffc);
return;
}
seg2 = segdat[1];
x86seg_log("New address : %04X:%08X\n", seg2, newpc);
x86seg_log("New address : %04X:%08X\n", seg2, newpc);
if (!(seg2 & 0xfffc)) {
x86gpf("loadcscall(): ex selector is NULL", 0);
return;
}
addr = seg2 & 0xfff8;
dt = (seg2 & 0x0004) ? &ldt : &gdt;
if ((addr + 7) > dt->limit) {
x86gpf("loadcscall(): ex Selector > DT limit", seg2 & 0xfff8);
return;
}
addr += dt->base;
read_descriptor(addr, segdat, segdat32, 1);
if (cpu_state.abrt)
return;
if (!(seg2 & 0xfffc)) {
x86gpf("loadcscall(): ex selector is NULL", 0);
return;
}
addr = seg2 & 0xfff8;
dt = (seg2 & 0x0004) ? &ldt : &gdt;
if ((addr + 7) > dt->limit) {
x86gpf("loadcscall(): ex Selector > DT limit", seg2 & 0xfff8);
return;
}
addr += dt->base;
read_descriptor(addr, segdat, segdat32, 1);
if (cpu_state.abrt)
return;
x86seg_log("Code seg2 call - %04X - %04X %04X %04X\n", seg2, segdat[0], segdat[1], segdat[2]);
if (DPL > CPL) {
x86gpf("loadcscall(): ex DPL > CPL", seg2 & 0xfffc);
return;
}
if (!(segdat[2] & 0x8000)) {
x86seg_log("Call gate CS not present %04X\n", seg2);
x86np("Call gate CS not present", seg2 & 0xfffc);
return;
}
if (DPL > CPL) {
x86gpf("loadcscall(): ex DPL > CPL", seg2 & 0xfffc);
return;
}
if (!(segdat[2] & 0x8000)) {
x86seg_log("Call gate CS not present %04X\n", seg2);
x86np("Call gate CS not present", seg2 & 0xfffc);
return;
}
switch (segdat[2] & 0x1f00) {
case 0x1800: case 0x1900: case 0x1a00: case 0x1b00: /* Non-conforming code */
if (DPL < CPL) {
switch (segdat[2] & 0x1f00) {
case 0x1800: case 0x1900: case 0x1a00: case 0x1b00: /* Non-conforming code */
if (DPL < CPL) {
#ifdef USE_NEW_DYNAREC
uint16_t oldcs = CS;
uint16_t oldcs = CS;
#endif
oaddr = addr;
/* Load new stack */
oldss = SS;
oldsp = oldsp2 = ESP;
cpl_override = 1;
if (tr.access & 8) {
addr = 4 + tr.base + (DPL << 3);
newss = readmemw(0, addr + 4);
if (cpu_16bitbus) {
newsp = readmemw(0, addr);
newsp |= (readmemw(0, addr + 2) << 16);
} else
newsp = readmeml(0, addr);
} else {
addr = 2 + tr.base + (DPL * 4);
newss = readmemw(0, addr + 2);
oaddr = addr;
/* Load new stack */
oldss = SS;
oldsp = oldsp2 = ESP;
cpl_override = 1;
if (tr.access & 8) {
addr = 4 + tr.base + (DPL << 3);
newss = readmemw(0, addr + 4);
if (cpu_16bitbus) {
newsp = readmemw(0, addr);
}
cpl_override = 0;
if (cpu_state.abrt)
return;
x86seg_log("New stack %04X:%08X\n", newss, newsp);
if (!(newss & 0xfffc)) {
x86ts(NULL, newss & 0xfffc);
return;
}
addr = newss & 0xfff8;
dt = (newss & 0x0004) ? &ldt : &gdt;
if ((addr + 7) > dt->limit) {
fatal("Bigger than DT limit %04X %08X %04X CSC SS\n", newss, addr, dt->limit);
x86ts(NULL, newss & ~3);
return;
}
addr += dt->base;
x86seg_log("Read stack seg\n");
read_descriptor(addr, segdat2, segdat232, 1);
if (cpu_state.abrt)
return;
x86seg_log("Read stack seg done!\n");
if (((newss & 0x0003) != DPL) || (DPL2 != DPL)) {
x86ts(NULL, newss & 0xfffc);
return;
}
if ((segdat2[2] & 0x1a00) != 0x1200) {
x86ts("Call gate loading SS unknown type", newss & 0xfffc);
return;
}
if (!(segdat2[2] & 0x8000)) {
x86ss("Call gate loading SS not present", newss & 0xfffc);
return;
}
if (!stack32)
oldsp &= 0xffff;
SS = newss;
set_stack32((segdat2[3] & 0x0040) ? 1 : 0);
if (stack32)
ESP = newsp;
else
SP = newsp;
newsp |= (readmemw(0, addr + 2) << 16);
} else
newsp = readmeml(0, addr);
} else {
addr = 2 + tr.base + (DPL * 4);
newss = readmemw(0, addr + 2);
newsp = readmemw(0, addr);
}
cpl_override = 0;
if (cpu_state.abrt)
return;
x86seg_log("New stack %04X:%08X\n", newss, newsp);
if (!(newss & 0xfffc)) {
x86ts(NULL, newss & 0xfffc);
return;
}
addr = newss & 0xfff8;
dt = (newss & 0x0004) ? &ldt : &gdt;
if ((addr + 7) > dt->limit) {
fatal("Bigger than DT limit %04X %08X %04X CSC SS\n", newss, addr, dt->limit);
x86ts(NULL, newss & ~3);
return;
}
addr += dt->base;
x86seg_log("Read stack seg\n");
read_descriptor(addr, segdat2, segdat232, 1);
if (cpu_state.abrt)
return;
x86seg_log("Read stack seg done!\n");
if (((newss & 0x0003) != DPL) || (DPL2 != DPL)) {
x86ts(NULL, newss & 0xfffc);
return;
}
if ((segdat2[2] & 0x1a00) != 0x1200) {
x86ts("Call gate loading SS unknown type", newss & 0xfffc);
return;
}
if (!(segdat2[2] & 0x8000)) {
x86ss("Call gate loading SS not present", newss & 0xfffc);
return;
}
if (!stack32)
oldsp &= 0xffff;
SS = newss;
set_stack32((segdat2[3] & 0x0040) ? 1 : 0);
if (stack32)
ESP = newsp;
else
SP = newsp;
do_seg_load(&cpu_state.seg_ss, segdat2);
do_seg_load(&cpu_state.seg_ss, segdat2);
x86seg_log("Set access 1\n");
cpl_override = 1;
writememw(0, addr + 4, segdat2[2] | 0x100); /* Set accessed bit */
cpl_override = 0;
x86seg_log("Set access 1\n");
cpl_override = 1;
writememw(0, addr + 4, segdat2[2] | 0x100); /* Set accessed bit */
cpl_override = 0;
CS = seg2;
do_seg_load(&cpu_state.seg_cs, segdat);
if ((CPL == 3) && (oldcpl != 3))
flushmmucache_cr3();
CS = seg2;
do_seg_load(&cpu_state.seg_cs, segdat);
if ((CPL == 3) && (oldcpl != 3))
flushmmucache_cr3();
#ifdef USE_NEW_DYNAREC
oldcpl = CPL;
oldcpl = CPL;
#endif
set_use32(segdat[3] & 0x0040);
cpu_state.pc = newpc;
set_use32(segdat[3] & 0x0040);
cpu_state.pc = newpc;
x86seg_log("Set access 2\n");
x86seg_log("Set access 2\n");
cpl_override = 1;
writememw(0, oaddr + 4, segdat[2] | 0x100); /* Set accessed bit */
cpl_override = 0;
cpl_override = 1;
writememw(0, oaddr + 4, segdat[2] | 0x100); /* Set accessed bit */
cpl_override = 0;
x86seg_log("Type %04X\n", type);
if (type == 0x0c00) {
PUSHL(oldss);
PUSHL(oldsp2);
if (cpu_state.abrt) {
SS = oldss;
ESP = oldsp2;
x86seg_log("Type %04X\n", type);
if (type == 0x0c00) {
PUSHL(oldss);
PUSHL(oldsp2);
if (cpu_state.abrt) {
SS = oldss;
ESP = oldsp2;
#ifdef USE_NEW_DYNAREC
CS = oldcs;
CS = oldcs;
#endif
return;
return;
}
if (count) {
while (count--) {