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GPU revision switch, pmc_boot fixes

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This commit is contained in:
starfrost013
2024-12-05 23:10:50 +00:00
parent e7ca410d36
commit 831afb5fa1
4 changed files with 39 additions and 5 deletions
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7
src/include/86box/nv/vid_nv.h
View File

@@ -97,6 +97,7 @@ typedef struct nv_base_s
uint32_t bar0_mmio_base; // PCI Base Address Register 0 - MMIO Base
uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE)
nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation)
uint32_t gpu_revision; // GPU Stepping
} nv_base_t;
#define NV_REG_LIST_END 0xD15EA5E
@@ -120,7 +121,11 @@ typedef struct nv_register_s
nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs);
#define NV3_BOOT_REG_DEFAULT 0x00300111
// Default value for the boot information register.
// Depends on the chip
#define NV3_BOOT_REG_REV_A00 0x00030100
#define NV3_BOOT_REG_REV_B00 0x00030110
#define NV3_BOOT_REG_REV_C00 0x00030120
// Master Control
typedef struct nv3_pmc_s

6
src/video/nv/nv3/nv3_core.c
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@@ -158,7 +158,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
break;
case NV3_PCI_CFG_REVISION:
ret = NV3_PCI_CFG_REVISION_B00; // Commercial release
ret = nv3->nvbase.gpu_revision; // Commercial release
break;
case PCI_REG_PROG_IF:
@@ -752,8 +752,10 @@ void* nv3_init(const device_t *info)
else
nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file);
// set the vram amount and gpu revision
uint32_t vram_amount = device_get_config_int("VRAM");
nv3->nvbase.gpu_revision = device_get_config_int("Chip Revision");
// set up the bus and start setting up SVGA core
if (nv3->nvbase.bus_generation == nv_bus_pci)
{

23
src/video/nv/nv3/nv3_core_config.c
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@@ -94,7 +94,7 @@ const device_config_t nv3_config[] =
// Memory configuration
{
.name = "VRAM",
.description = "VRAM",
.description = "VRAM Size",
.type = CONFIG_SELECTION,
.default_int = VRAM_SIZE_4MB,
.selection =
@@ -116,6 +116,27 @@ const device_config_t nv3_config[] =
}
},
{
.name = "Chip Revision",
.description = "Chip Revision",
.type = CONFIG_SELECTION,
.default_int = NV3_PCI_CFG_REVISION_B00,
.selection =
{
{
.description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997)",
.value = NV3_PCI_CFG_REVISION_A00,
},
{
.description = "RIVA 128 (NV3) / Stepping B0 (August 1997)",
.value = NV3_PCI_CFG_REVISION_B00,
},
{
.description = "RIVA 128 ZX (NV3T) / Stepping C0 (March 1998)",
.value = NV3_PCI_CFG_REVISION_C00,
},
}
},
{
.type = CONFIG_END
}

8
src/video/nv/nv3/subsystems/nv3_pmc.c
View File

@@ -34,7 +34,13 @@ void nv3_pmc_init()
{
nv_log("NV3: Initialising PMC....\n");
nv3->pmc.boot = NV3_BOOT_REG_DEFAULT;
if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_A00)
nv3->pmc.boot = NV3_BOOT_REG_REV_A00;
else if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_B00)
nv3->pmc.boot = NV3_BOOT_REG_REV_B00;
else
nv3->pmc.boot = NV3_BOOT_REG_REV_C00;
nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_SOFTWARE;
nv_log("NV3: Initialising PMC: Done\n");