diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h
index a00699a62..3d4bd9b0a 100644
--- a/src/include/86box/nv/vid_nv3.h
+++ b/src/include/86box/nv/vid_nv3.h
@@ -808,7 +808,6 @@ typedef struct nv3_pfifo_cache_s
     uint8_t channel;                    // The DMA channel ID of this cache.
     uint32_t status;
     uint32_t puller_control;
-    uint32_t control;
     uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL];  // Only one of these exists for cache0
 
     /* cache1 only 
diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c
index 1e52175c5..b788f0e94 100644
--- a/src/video/nv/nv3/subsystems/nv3_pfifo.c
+++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c
@@ -143,10 +143,10 @@ uint32_t nv3_pfifo_read(uint32_t address)
                     ret = nv3->pfifo.ramro_config;
                     break;
                 case NV3_PFIFO_CACHE0_PULLER_CONTROL:
-                    ret = nv3->pfifo.cache0_settings.control;
+                    ret = nv3->pfifo.cache0_settings.puller_control;
                     break;
                 case NV3_PFIFO_CACHE1_PULLER_CONTROL:
-                    ret = nv3->pfifo.cache1_settings.control;
+                    ret = nv3->pfifo.cache1_settings.puller_control;
                     break;
                 case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY:
                     ret = nv3->pfifo.cache0_settings.context_is_dirty;
@@ -368,10 +368,10 @@ void nv3_pfifo_write(uint32_t address, uint32_t value)
                     break;
                 // Control
                 case NV3_PFIFO_CACHE0_PULLER_CONTROL:
-                    nv3->pfifo.cache0_settings.control = value; // 8bits meaningful
+                    nv3->pfifo.cache0_settings.puller_control = value; // 8bits meaningful
                     break;
                 case NV3_PFIFO_CACHE1_PULLER_CONTROL:
-                    nv3->pfifo.cache1_settings.control = value; // 8bits meaningful
+                    nv3->pfifo.cache1_settings.puller_control = value; // 8bits meaningful
                     break;
                 case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY:
                     nv3->pfifo.cache0_settings.context_is_dirty = value;
@@ -648,7 +648,6 @@ void nv3_pfifo_cache1_pull()
     if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address)
         return;
 
-    // There is only one entry for cache0 
     uint32_t get_address = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably
 
     uint16_t current_channel = nv3->pfifo.cache1_settings.channel;
diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c
index 8782abd8a..7d294d820 100644
--- a/src/video/nv/nv3/subsystems/nv3_pgraph.c
+++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c
@@ -134,9 +134,11 @@ uint32_t nv3_pgraph_read(uint32_t address)
                 //interrupt status and enable regs
                 case NV3_PGRAPH_INTR_0:
                     ret = nv3->pgraph.interrupt_status_0;
+                    nv3_pmc_clear_interrupts();
                     break;
                 case NV3_PGRAPH_INTR_1:
                     ret = nv3->pgraph.interrupt_status_1;
+                    nv3_pmc_clear_interrupts();
                     break;
                 case NV3_PGRAPH_INTR_EN_0:
                     ret = nv3->pgraph.interrupt_enable_0;
@@ -323,7 +325,8 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
                 // Only bits divisible by 4 matter
                 // and only bit0-16 is defined in intr_1 
                 case NV3_PGRAPH_INTR_EN_0:
-                    nv3->pgraph.interrupt_enable_0 = value & 0x11111111; 
+                    value |= (1 << NV3_PGRAPH_INTR_EN_0_VBLANK);
+                    nv3->pgraph.interrupt_enable_0 = value & 0x11111111;                     
                     nv3_pmc_handle_interrupts(true);
                     break;
                 case NV3_PGRAPH_INTR_EN_1: