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very large rewrite. use custom rendering code (for both DFB and GPU) to allow sub-scanline switches; implement a real pixel clock; only blit stuff that actually changed; add void to functions for actions (this may break some things)

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This commit is contained in:
starfrost013
2025-04-09 21:29:46 +01:00
parent c1506772de
commit 911a71c67f
9 changed files with 378 additions and 152 deletions
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10
src/include/86box/nv/render/vid_nv3_render.h
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@@ -18,13 +18,17 @@
#pragma once
/* Core */
void nv3_render_15bpp(svga_t *svga);
void nv3_render_16bpp(svga_t *svga);
void nv3_render_32bpp(svga_t *svga);
void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj);
void nv3_render_current_bpp_dfb_8(uint32_t address);
void nv3_render_current_bpp_dfb_16(uint32_t address);
void nv3_render_current_bpp_dfb_32(uint32_t address);
void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj);
uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded);

9
src/include/86box/nv/vid_nv.h
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@@ -72,6 +72,9 @@ void nv_log_verbose_only(const char *fmt, ...);
#define NV_ARCHITECTURE_NV3 3 // Riva 128
#define NV_ARCHITECTURE_NV4 4 // Riva TNT and later
#define NV_MAX_BUF_SIZE_X 1920 // Maximum buffer size, X
#define NV_MAX_BUF_SIZE_Y 1200 // Maximum buffer size, Y
typedef enum nv_bus_generation_e
{
// NV1 - Prototype version
@@ -113,7 +116,9 @@ typedef struct nv_base_s
uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE)
nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation)
uint32_t gpu_revision; // GPU Stepping
double pixel_clock_frequency; // Frequency used for pixel clock
double pixel_clock_frequency; // Frequency used for pixel clock#
double refresh_time; // Rough estimation of refresh rate, for when we can present the screen
double refresh_clock; // Time since the last refresh
rivatimer_t* pixel_clock_timer; // Timer for measuring pixel clock
bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times
double memory_clock_frequency; // Source Frequency for PTIMER
@@ -139,7 +144,7 @@ typedef struct nv_register_s
int32_t address; // MMIO Address
char* friendly_name; // Friendly name
// reg_ptr not needed as a parameter, because we implicitly know which register si being tiwddled
uint32_t (*on_read)(); // Optional on-read function
uint32_t (*on_read)(void); // Optional on-read function
void (*on_write)(uint32_t value); // Optional on-write fucntion
} nv_register_t;

34
src/include/86box/nv/vid_nv3.h
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@@ -1457,7 +1457,7 @@ void nv3_recalc_timings(svga_t* svga);
void nv3_force_redraw(void* priv);
/* BAR0 GPU MMIO read */
void nv3_update_mappings(); // Update memory mappings
void nv3_update_mappings(void); // Update memory mappings
uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO
uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO
uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO
@@ -1556,12 +1556,12 @@ void nv3_user_write(uint32_t address, uint32_t value);
// GPU subsystems
// NV3 PMC
void nv3_pmc_init();
uint32_t nv3_pmc_clear_interrupts();
void nv3_pmc_init(void);
uint32_t nv3_pmc_clear_interrupts(void);
uint32_t nv3_pmc_handle_interrupts(bool send_now);
// NV3 PGRAPH
void nv3_pgraph_init();
void nv3_pgraph_init(void);
uint32_t nv3_pgraph_read(uint32_t address);
void nv3_pgraph_write(uint32_t address, uint32_t value);
void nv3_pgraph_vblank_start(svga_t* svga);
@@ -1599,46 +1599,46 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_c
void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context,nv3_grobj_t grobj);
// NV3 PFIFO
void nv3_pfifo_init();
void nv3_pfifo_init(void);
uint32_t nv3_pfifo_read(uint32_t address);
void nv3_pfifo_write(uint32_t address, uint32_t value);
void nv3_pfifo_interrupt(uint32_t id, bool fire_now);
// NV3 PFIFO - Caches
//cache0_push not a thing
void nv3_pfifo_cache0_pull();
void nv3_pfifo_cache0_pull(void);
void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val);
void nv3_pfifo_cache1_pull();
void nv3_pfifo_cache1_pull(void);
uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val);
uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val);
uint32_t nv3_pfifo_cache1_num_free_spaces();
uint32_t nv3_pfifo_cache1_num_free_spaces(void);
// NV3 PFB
void nv3_pfb_init();
void nv3_pfb_init(void);
// NV3 PEXTDEV/PSTRAPS
void nv3_pextdev_init();
void nv3_pextdev_init(void);
// NV3 PBUS
void nv3_pbus_init();
void nv3_pbus_init(void);
// NV3 PBUS RMA - Real Mode Access for VBIOS
uint8_t nv3_pbus_rma_read(uint16_t addr);
void nv3_pbus_rma_write(uint16_t addr, uint8_t val);
// NV3 PRAMDAC (Final presentation)
void nv3_pramdac_init();
void nv3_pramdac_set_vram_clock();
void nv3_pramdac_set_pixel_clock();
void nv3_pramdac_init(void);
void nv3_pramdac_set_vram_clock(void);
void nv3_pramdac_set_pixel_clock(void);
void nv3_pramdac_pixel_clock_poll(double real_time);
void nv3_pramdac_memory_clock_poll(double real_time);
// NV3 PTIMER
void nv3_ptimer_init();
void nv3_ptimer_init(void);
void nv3_ptimer_tick(double real_time);
// NV3 PVIDEO
void nv3_pvideo_init();
void nv3_pvideo_init(void);
// NV3 PME (Mediaport)
void nv3_pme_init();
void nv3_pme_init(void);