From d4781bd409c53438db70495911682a1d73241d0f Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sun, 19 Apr 2020 00:32:37 +0200
Subject: [PATCH 01/43] Fixed a slight mistake in the T1000 code, fixes #590.

---
 src/machine/m_xt_t1000.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/machine/m_xt_t1000.c b/src/machine/m_xt_t1000.c
index 447354c3c..bf31be9f7 100644
--- a/src/machine/m_xt_t1000.c
+++ b/src/machine/m_xt_t1000.c
@@ -1024,7 +1024,7 @@ t1000_configsys_load(void)
     f = plat_fopen(nvr_path(L"t1000_config.nvr"), L"rb");
     if (f != NULL) {
 	size = sizeof(t1000.t1000_nvram);
-	if (fread(t1000.t1000_nvram, size, 1, f) != size)
+	if (fread(t1000.t1000_nvram, 1, size, f) != size)
 		fatal("t1000_configsys_load(): Error reading data\n");
 	fclose(f);
     }

From 5de8564fdc2d7e8ba32ad1584b057ffb6dc34271 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sun, 19 Apr 2020 14:16:21 +0200
Subject: [PATCH 02/43] Changed the way mem_add_bios() determine if the CPU has
 16-bit bus or not, fixes #667.

---
 src/mem.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/mem.c b/src/mem.c
index 459f7f6e6..25e84f593 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -2192,6 +2192,11 @@ mem_set_mem_state_smm(uint32_t base, uint32_t size, int state)
 void
 mem_add_bios(void)
 {
+    int temp_cpu_type, temp_cpu_16bitbus;
+
+    temp_cpu_type = machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type;
+    temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC );
+
     if (biosmask > 0x1ffff) {
 	/* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */
 	mem_mapping_add(&bios_mapping, 0xe0000, 0x20000,
@@ -2212,12 +2217,12 @@ mem_add_bios(void)
     }
 
     if (AT) {
-	mem_mapping_add(&bios_high_mapping, biosaddr | (cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
+	mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
 			mem_read_bios,mem_read_biosw,mem_read_biosl,
 			mem_write_null,mem_write_nullw,mem_write_nulll,
 			rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
 
-	mem_set_mem_state(biosaddr | (cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
+	mem_set_mem_state(biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
 			  MEM_READ_ROMCS | MEM_WRITE_ROMCS);
     }
 }

From cd0a57b6c3738c2e3ea24c04a11575667dedf8cb Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sun, 19 Apr 2020 18:26:57 +0200
Subject: [PATCH 03/43] Re-added some x87 differences between the old and new
 recompilers, fixes #692.

---
 src/cpu_common/x87.c               | 30 ++++++++++++++++
 src/cpu_common/x87.h               |  6 +++-
 src/cpu_common/x87_ops.h           | 30 ++++++++++++++++
 src/cpu_common/x87_ops_arith.h     | 48 ++++++++++++-------------
 src/cpu_common/x87_ops_loadstore.h |  5 ++-
 src/cpu_common/x87_ops_misc.h      | 56 +++++++++++++++++++++---------
 6 files changed, 130 insertions(+), 45 deletions(-)

diff --git a/src/cpu_common/x87.c b/src/cpu_common/x87.c
index 148172aab..8183f2e3e 100644
--- a/src/cpu_common/x87.c
+++ b/src/cpu_common/x87.c
@@ -42,6 +42,7 @@ fpu_log(const char *fmt, ...)
 #define X87_TAG_INVALID 2
 #define X87_TAG_EMPTY   3
 
+#ifdef USE_NEW_DYNAREC
 uint16_t x87_gettag()
 {
         uint16_t ret = 0;
@@ -78,6 +79,35 @@ void x87_settag(uint16_t new_tag)
                         cpu_state.tag[c] = TAG_VALID;
         }
 }
+#else
+uint16_t x87_gettag()
+{
+        uint16_t ret = 0;
+        int c;
+        
+        for (c = 0; c < 8; c++)
+        {
+                if (cpu_state.tag[c] & TAG_UINT64)
+                        ret |= 2 << (c*2);
+                else
+                        ret |= (cpu_state.tag[c] << (c*2));
+        }
+
+        return ret;
+}
+
+void x87_settag(uint16_t new_tag)
+{
+        cpu_state.tag[0] = new_tag & 3;
+        cpu_state.tag[1] = (new_tag >> 2) & 3;
+        cpu_state.tag[2] = (new_tag >> 4) & 3;
+        cpu_state.tag[3] = (new_tag >> 6) & 3;
+        cpu_state.tag[4] = (new_tag >> 8) & 3;
+        cpu_state.tag[5] = (new_tag >> 10) & 3;
+        cpu_state.tag[6] = (new_tag >> 12) & 3;
+        cpu_state.tag[7] = (new_tag >> 14) & 3;
+}
+#endif
 
 
 #ifdef ENABLE_808X_LOG
diff --git a/src/cpu_common/x87.h b/src/cpu_common/x87.h
index 3d240960b..106e8c23c 100644
--- a/src/cpu_common/x87.h
+++ b/src/cpu_common/x87.h
@@ -30,10 +30,14 @@ void x87_settag(uint16_t new_tag);
 #define TAG_EMPTY  0
 #define TAG_VALID  (1 << 0)
 /*Hack for FPU copy. If set then MM[].q contains the 64-bit integer loaded by FILD*/
+#ifdef USE_NEW_DYNAREC
 #define TAG_UINT64 (1 << 7)
+#else
+#define TAG_UINT64 (1 << 2)
+#endif
 
 /*Old dynarec stuff.*/
-#define TAG_NOT_UINT64 0x7f
+#define TAG_NOT_UINT64 0xfb
 
 #define X87_ROUNDING_NEAREST 0
 #define X87_ROUNDING_DOWN    1
diff --git a/src/cpu_common/x87_ops.h b/src/cpu_common/x87_ops.h
index 3b8d038cb..80560a8ae 100644
--- a/src/cpu_common/x87_ops.h
+++ b/src/cpu_common/x87_ops.h
@@ -98,7 +98,11 @@ static __inline void x87_push(double i)
         cpu_state.TOP=(cpu_state.TOP-1)&7;
 #endif
         cpu_state.ST[cpu_state.TOP&7] = i;
+#ifdef USE_NEW_DYNAREC
         cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+#else
+        cpu_state.tag[cpu_state.TOP&7] = (i == 0.0) ? TAG_VALID : 0;
+#endif
 }
 
 static __inline void x87_push_u64(uint64_t i)
@@ -117,7 +121,11 @@ static __inline void x87_push_u64(uint64_t i)
         cpu_state.TOP=(cpu_state.TOP-1)&7;
 #endif
         cpu_state.ST[cpu_state.TOP&7] = td.d;
+#ifdef USE_NEW_DYNAREC
         cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+#else
+        cpu_state.tag[cpu_state.TOP&7] = (td.d == 0.0) ? TAG_VALID : 0;
+#endif
 }
 
 static __inline double x87_pop()
@@ -127,6 +135,7 @@ static __inline double x87_pop()
 #ifdef USE_NEW_DYNAREC
         cpu_state.TOP++;
 #else
+        cpu_state.tag[cpu_state.TOP&7] |= TAG_UINT64;
         cpu_state.TOP=(cpu_state.TOP+1)&7;
 #endif
         return t;
@@ -263,13 +272,22 @@ static __inline void x87_ld_frstor(int reg)
         cpu_state.MM[reg].q = readmemq(easeg, cpu_state.eaaddr);
         cpu_state.MM_w4[reg] = readmemw(easeg, cpu_state.eaaddr + 8);
 
+#ifdef USE_NEW_DYNAREC
         if ((cpu_state.MM_w4[reg] == 0x5555) && (cpu_state.tag[reg] & TAG_UINT64))
+#else
+        if ((cpu_state.MM_w4[reg] == 0x5555) && (cpu_state.tag[reg] == 2))
+#endif
         {
+#ifndef USE_NEW_DYNAREC
+		cpu_state.tag[reg] = TAG_UINT64;
+#endif
                 cpu_state.ST[reg] = (double)cpu_state.MM[reg].q;
         }
         else
         {
+#ifdef USE_NEW_DYNAREC
                 cpu_state.tag[reg] &= ~TAG_UINT64;
+#endif
                 cpu_state.ST[reg] = x87_ld80();
         }
 }
@@ -426,6 +444,18 @@ typedef union
         } while (0)
 #endif
 
+#ifdef USE_NEW_DYNAREC
+# define FP_TAG_VALID	cpu_state.tag[cpu_state.TOP&7] = TAG_VALID
+# define FP_TAG_VALID_F	cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID
+# define FP_TAG_DEFAULT	cpu_state.tag[cpu_state.TOP&7] = TAG_VALID | TAG_UINT64
+# define FP_TAG_VALID_N	cpu_state.tag[(cpu_state.TOP + 1) & 7] = TAG_VALID
+#else
+# define FP_TAG_VALID	cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64
+# define FP_TAG_VALID_F	cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64
+# define FP_TAG_DEFAULT	cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
+# define FP_TAG_VALID_N	cpu_state.tag[(cpu_state.TOP + 1) & 7] &= ~TAG_UINT64
+#endif
+
 #include "x87_ops_arith.h"
 #include "x87_ops_misc.h"
 #include "x87_ops_loadstore.h"
diff --git a/src/cpu_common/x87_ops_arith.h b/src/cpu_common/x87_ops_arith.h
index 1e7722a17..853da6678 100644
--- a/src/cpu_common/x87_ops_arith.h
+++ b/src/cpu_common/x87_ops_arith.h
@@ -11,7 +11,7 @@ static int opFADD ## name ## _a ## a_size(uint32_t fetchdat)    \
         ST(0) += use_var;                                       \
         if ((cpu_state.npxc >> 10) & 3)                                   \
                 fesetround(FE_TONEAREST);                       \
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;             \
+        FP_TAG_VALID;						\
         CLOCK_CYCLES(8);                                        \
         return 0;                                               \
 }                                                               \
@@ -48,7 +48,7 @@ static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat)    \
 	SEG_CHECK_READ(cpu_state.ea_seg);                       \
         load_var = get(); if (cpu_state.abrt) return 1;                   \
         x87_div(ST(0), ST(0), use_var);                         \
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;             \
+        FP_TAG_VALID;						\
         CLOCK_CYCLES(73);                                       \
         return 0;                                               \
 }                                                               \
@@ -60,7 +60,7 @@ static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat)   \
 	SEG_CHECK_READ(cpu_state.ea_seg);                       \
         load_var = get(); if (cpu_state.abrt) return 1;                   \
         x87_div(ST(0), use_var, ST(0));                         \
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;             \
+        FP_TAG_VALID;						\
         CLOCK_CYCLES(73);                                       \
         return 0;                                               \
 }                                                               \
@@ -72,7 +72,7 @@ static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat)    \
 	SEG_CHECK_READ(cpu_state.ea_seg);                       \
         load_var = get(); if (cpu_state.abrt) return 1;                   \
         ST(0) *= use_var;                                       \
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;             \
+        FP_TAG_VALID;						\
         CLOCK_CYCLES(11);                                       \
         return 0;                                               \
 }                                                               \
@@ -84,7 +84,7 @@ static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat)    \
 	SEG_CHECK_READ(cpu_state.ea_seg);                       \
         load_var = get(); if (cpu_state.abrt) return 1;                   \
         ST(0) -= use_var;                                       \
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;             \
+        FP_TAG_VALID;						\
         CLOCK_CYCLES(8);                                        \
         return 0;                                               \
 }                                                               \
@@ -96,7 +96,7 @@ static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat)   \
 	SEG_CHECK_READ(cpu_state.ea_seg);                       \
         load_var = get(); if (cpu_state.abrt) return 1;                   \
         ST(0) = use_var - ST(0);                                \
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;             \
+        FP_TAG_VALID;						\
         CLOCK_CYCLES(8);                                        \
         return 0;                                               \
 }
@@ -126,7 +126,7 @@ static int opFADD(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = ST(0) + ST(fetchdat & 7);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+	FP_TAG_VALID;
         CLOCK_CYCLES(8);
         return 0;
 }
@@ -135,7 +135,7 @@ static int opFADDr(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         CLOCK_CYCLES(8);
         return 0;
 }
@@ -144,7 +144,7 @@ static int opFADDP(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         x87_pop();
         CLOCK_CYCLES(8);
         return 0;
@@ -233,7 +233,7 @@ static int opFDIV(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_div(ST(0), ST(0), ST(fetchdat & 7));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+	FP_TAG_VALID;
         CLOCK_CYCLES(73);
         return 0;
 }
@@ -242,7 +242,7 @@ static int opFDIVr(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         CLOCK_CYCLES(73);
         return 0;
 }
@@ -251,7 +251,7 @@ static int opFDIVP(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         x87_pop();
         CLOCK_CYCLES(73);
         return 0;
@@ -262,7 +262,7 @@ static int opFDIVR(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_div(ST(0), ST(fetchdat&7), ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+	FP_TAG_VALID;
         CLOCK_CYCLES(73);
         return 0;
 }
@@ -271,7 +271,7 @@ static int opFDIVRr(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         CLOCK_CYCLES(73);
         return 0;
 }
@@ -280,7 +280,7 @@ static int opFDIVRP(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         x87_pop();
         CLOCK_CYCLES(73);
         return 0;
@@ -291,7 +291,7 @@ static int opFMUL(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = ST(0) * ST(fetchdat & 7);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+	FP_TAG_VALID;
         CLOCK_CYCLES(16);
         return 0;
 }
@@ -300,7 +300,7 @@ static int opFMULr(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         CLOCK_CYCLES(16);
         return 0;
 }
@@ -309,7 +309,7 @@ static int opFMULP(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         x87_pop();
         CLOCK_CYCLES(16);
         return 0;
@@ -320,7 +320,7 @@ static int opFSUB(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = ST(0) - ST(fetchdat & 7);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+	FP_TAG_VALID;
         CLOCK_CYCLES(8);
         return 0;
 }
@@ -329,7 +329,7 @@ static int opFSUBr(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         CLOCK_CYCLES(8);
         return 0;
 }
@@ -338,7 +338,7 @@ static int opFSUBP(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         x87_pop();
         CLOCK_CYCLES(8);
         return 0;
@@ -349,7 +349,7 @@ static int opFSUBR(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = ST(fetchdat & 7) - ST(0);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+	FP_TAG_VALID;
         CLOCK_CYCLES(8);
         return 0;
 }
@@ -358,7 +358,7 @@ static int opFSUBRr(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         CLOCK_CYCLES(8);
         return 0;
 }
@@ -367,7 +367,7 @@ static int opFSUBRP(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
+	FP_TAG_VALID_F;
         x87_pop();
         CLOCK_CYCLES(8);
         return 0;
diff --git a/src/cpu_common/x87_ops_loadstore.h b/src/cpu_common/x87_ops_loadstore.h
index fa33171c8..4d4983962 100644
--- a/src/cpu_common/x87_ops_loadstore.h
+++ b/src/cpu_common/x87_ops_loadstore.h
@@ -15,7 +15,6 @@
  *		Copyright 2008-2019 Sarah Walker.
  *		Copyright 2016-2019 Miran Grca.
  */
-
 static int opFILDiw_a16(uint32_t fetchdat)
 {
         int16_t temp;
@@ -102,7 +101,7 @@ static int opFILDiq_a16(uint32_t fetchdat)
         temp64 = geteaq(); if (cpu_state.abrt) return 1;
         x87_push((double)temp64);
         cpu_state.MM[cpu_state.TOP&7].q = temp64;
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID | TAG_UINT64;
+	FP_TAG_DEFAULT;
 
         CLOCK_CYCLES(10);
         return 0;
@@ -117,7 +116,7 @@ static int opFILDiq_a32(uint32_t fetchdat)
         temp64 = geteaq(); if (cpu_state.abrt) return 1;
         x87_push((double)temp64);
         cpu_state.MM[cpu_state.TOP&7].q = temp64;
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID | TAG_UINT64;
+	FP_TAG_DEFAULT;
 
         CLOCK_CYCLES(10);
         return 0;
diff --git a/src/cpu_common/x87_ops_misc.h b/src/cpu_common/x87_ops_misc.h
index a4e437744..1856a00e8 100644
--- a/src/cpu_common/x87_ops_misc.h
+++ b/src/cpu_common/x87_ops_misc.h
@@ -51,7 +51,11 @@ static int opFINIT(uint32_t fetchdat)
         codegen_set_rounding_mode(X87_ROUNDING_NEAREST);
         cpu_state.npxs = 0;
 	p = (uint64_t *)cpu_state.tag;
+#ifdef USE_NEW_DYNAREC
         *p = 0;
+#else
+        *p = 0x0303030303030303ll;
+#endif
         cpu_state.TOP = 0;
 	cpu_state.ismmx = 0;
         CLOCK_CYCLES(17);
@@ -64,7 +68,11 @@ static int opFFREE(uint32_t fetchdat)
 {
         FP_ENTER();
         cpu_state.pc++;
+#ifdef USE_NEW_DYNAREC
         cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_EMPTY;
+#else
+        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = 3;
+#endif
         CLOCK_CYCLES(3);
         return 0;
 }
@@ -141,10 +149,16 @@ static int FSTOR()
         /*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
           something like this is needed*/
 	p = (uint64_t *) cpu_state.tag;
+#ifdef USE_NEW_DYNAREC
         if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
             cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
             !cpu_state.TOP && (*p == 0x0101010101010101ull))
-        cpu_state.ismmx = 1;
+#else
+        if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
+            cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
+            !cpu_state.TOP && !(*p))
+ #endif
+		cpu_state.ismmx = 1;
 
         CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
         return cpu_state.abrt;
@@ -308,7 +322,11 @@ static int FSAVE()
         codegen_set_rounding_mode(X87_ROUNDING_NEAREST);
         cpu_state.npxs = 0;
 	p = (uint64_t *)cpu_state.tag;
+#ifdef USE_NEW_DYNAREC
         *p = 0;
+#else
+        *p = 0x0303030303030303ll;
+#endif
         cpu_state.TOP = 0;
         cpu_state.ismmx = 0;
 
@@ -398,7 +416,7 @@ static int opFCHS(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = -ST(0);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(6);
         return 0;
 }
@@ -408,7 +426,7 @@ static int opFABS(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = fabs(ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(3);
         return 0;
 }
@@ -429,7 +447,11 @@ static int opFXAM(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         cpu_state.npxs &= ~(C0|C1|C2|C3);
+#ifdef USE_NEW_DYNAREC
         if (cpu_state.tag[cpu_state.TOP&7] == TAG_EMPTY)	cpu_state.npxs |= (C0|C3);
+#else
+        if (cpu_state.tag[cpu_state.TOP&7] == 3)	cpu_state.npxs |= (C0|C3);
+#endif
         else if (ST(0) == 0.0) cpu_state.npxs |= C3;
         else                   cpu_state.npxs |= C2;
         if (ST(0) < 0.0)       cpu_state.npxs |= C1;
@@ -496,7 +518,7 @@ static int opFLDZ(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         x87_push(0.0);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(4);
         return 0;
 }
@@ -506,7 +528,7 @@ static int opF2XM1(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = pow(2.0, ST(0)) - 1.0;
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(200);
         return 0;
 }
@@ -516,7 +538,7 @@ static int opFYL2X(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(1) = ST(1) * (log(ST(0)) / log(2.0));
-        cpu_state.tag[(cpu_state.TOP + 1) & 7] = TAG_VALID;
+        FP_TAG_VALID_N;
         x87_pop();
         CLOCK_CYCLES(250);
         return 0;
@@ -527,7 +549,7 @@ static int opFYL2XP1(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(1) = ST(1) * (log1p(ST(0)) / log(2.0));
-        cpu_state.tag[(cpu_state.TOP + 1) & 7] = TAG_VALID;
+        FP_TAG_VALID_N;
         x87_pop();
         CLOCK_CYCLES(250);
         return 0;
@@ -538,7 +560,7 @@ static int opFPTAN(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = tan(ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         x87_push(1.0);
         cpu_state.npxs &= ~C2;
         CLOCK_CYCLES(235);
@@ -550,7 +572,7 @@ static int opFPATAN(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(1) = atan2(ST(1), ST(0));
-        cpu_state.tag[(cpu_state.TOP + 1) & 7] = TAG_VALID;
+        FP_TAG_VALID_N;
         x87_pop();
         CLOCK_CYCLES(250);
         return 0;
@@ -589,7 +611,7 @@ static int opFPREM(uint32_t fetchdat)
         cpu_state.pc++;
         temp64 = (int64_t)(ST(0) / ST(1));
         ST(0) = ST(0) - (ST(1) * (double)temp64);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         cpu_state.npxs &= ~(C0|C1|C2|C3);
         if (temp64 & 4) cpu_state.npxs|=C0;
         if (temp64 & 2) cpu_state.npxs|=C3;
@@ -605,7 +627,7 @@ static int opFPREM1(uint32_t fetchdat)
         cpu_state.pc++;
         temp64 = (int64_t)(ST(0) / ST(1));
         ST(0) = ST(0) - (ST(1) * (double)temp64);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         cpu_state.npxs &= ~(C0|C1|C2|C3);
         if (temp64 & 4) cpu_state.npxs|=C0;
         if (temp64 & 2) cpu_state.npxs|=C3;
@@ -620,7 +642,7 @@ static int opFSQRT(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = sqrt(ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(83);
         return 0;
 }
@@ -633,7 +655,7 @@ static int opFSINCOS(uint32_t fetchdat)
         cpu_state.pc++;
         td = ST(0);
         ST(0) = sin(td);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         x87_push(cos(td));
         cpu_state.npxs &= ~C2;
         CLOCK_CYCLES(330);
@@ -646,7 +668,7 @@ static int opFRNDINT(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = (double)x87_fround(ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(21);
         return 0;
 }
@@ -658,7 +680,7 @@ static int opFSCALE(uint32_t fetchdat)
         cpu_state.pc++;
         temp64 = (int64_t)ST(1);
         ST(0) = ST(0) * pow(2.0, (double)temp64);
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         CLOCK_CYCLES(30);
         return 0;
 }
@@ -669,7 +691,7 @@ static int opFSIN(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = sin(ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         cpu_state.npxs &= ~C2;
         CLOCK_CYCLES(300);
         return 0;
@@ -680,7 +702,7 @@ static int opFCOS(uint32_t fetchdat)
         FP_ENTER();
         cpu_state.pc++;
         ST(0) = cos(ST(0));
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
+        FP_TAG_VALID;
         cpu_state.npxs &= ~C2;
         CLOCK_CYCLES(300);
         return 0;

From 89332120593d6746aab1297d5abb826ba46e25c1 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Mon, 20 Apr 2020 02:25:20 +0200
Subject: [PATCH 04/43] Fixed S3 ViRGE 24bpp 8x8 patterns.

---
 src/video/vid_s3_virge.c | 30 ++++++++++++++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c
index 6043f8c16..f64556d4e 100644
--- a/src/video/vid_s3_virge.c
+++ b/src/video/vid_s3_virge.c
@@ -210,6 +210,7 @@ typedef struct virge_t
                 
                 uint32_t pattern_8[8*8];
                 uint32_t pattern_16[8*8];
+                uint32_t pattern_24[8*8];
                 uint32_t pattern_32[8*8];
 
                 uint32_t prdx;
@@ -1072,16 +1073,29 @@ static void fifo_thread(void *param)
                                                 {
                                                         int x = (fifo->addr_type & FIFO_ADDR) & 4;
                                                         int y = ((fifo->addr_type & FIFO_ADDR) >> 3) & 7;
+							int color, xx;
+							int byte, addr;
+
                                                         virge->s3d.pattern_8[y*8 + x]     = val & 0xff;
                                                         virge->s3d.pattern_8[y*8 + x + 1] = val >> 8;
                                                         virge->s3d.pattern_8[y*8 + x + 2] = val >> 16;
                                                         virge->s3d.pattern_8[y*8 + x + 3] = val >> 24;
-                        
+
                                                         x = ((fifo->addr_type & FIFO_ADDR) >> 1) & 6;
                                                         y = ((fifo->addr_type & FIFO_ADDR) >> 4) & 7;
                                                         virge->s3d.pattern_16[y*8 + x]     = val & 0xffff;
                                                         virge->s3d.pattern_16[y*8 + x + 1] = val >> 16;
 
+							addr = ((fifo->addr_type & FIFO_ADDR) & 0x00ff);
+							for (xx = 0; xx < 4; xx++) {
+					                        x = ((addr + xx) / 3) % 8;
+				        	                y = ((addr + xx) / 24) % 8;
+								color = ((addr + xx) % 3) << 3;
+								byte = (xx << 3);
+								virge->s3d.pattern_24[y*8 + x] &= ~(0xff << color);
+				                	        virge->s3d.pattern_24[y*8 + x] |= ((val >> byte) & 0xff) << color;
+							}
+
                                                         x = ((fifo->addr_type & FIFO_ADDR) >> 2) & 7;
                                                         y = ((fifo->addr_type & FIFO_ADDR) >> 5) & 7;
                                                         virge->s3d.pattern_32[y*8 + x] = val & 0xffffff;
@@ -1597,6 +1611,8 @@ static void s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *p)
                 {
                         int x = addr & 4;
                         int y = (addr >> 3) & 7;
+			int color, xx;
+			int byte;
                         virge->s3d.pattern_8[y*8 + x]     = val & 0xff;
                         virge->s3d.pattern_8[y*8 + x + 1] = val >> 8;
                         virge->s3d.pattern_8[y*8 + x + 2] = val >> 16;
@@ -1607,6 +1623,16 @@ static void s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *p)
                         virge->s3d.pattern_16[y*8 + x]     = val & 0xffff;
                         virge->s3d.pattern_16[y*8 + x + 1] = val >> 16;
 
+			addr &= 0x00ff;
+			for (xx = 0; xx < 4; xx++) {
+	                        x = ((addr + xx) / 3) % 8;
+        	                y = ((addr + xx) / 24) % 8;
+				color = ((addr + xx) % 3) << 3;
+				byte = (xx << 3);
+				virge->s3d.pattern_24[y*8 + x] &= ~(0xff << color);
+                	        virge->s3d.pattern_24[y*8 + x] |= ((val >> byte) & 0xff) << color;
+			}
+
                         x = (addr >> 2) & 7;
                         y = (addr >> 5) & 7;
                         virge->s3d.pattern_32[y*8 + x] = val & 0xffffff;
@@ -1989,7 +2015,7 @@ static void s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat)
                 bpp = 2;
                 x_mul = 3;
                 cpu_dat_shift = 24;
-                pattern_data = virge->s3d.pattern_32;
+                pattern_data = virge->s3d.pattern_24;
                 src_fg_clr = virge->s3d.src_fg_clr;
                 src_bg_clr = virge->s3d.src_bg_clr;
                 break;

From fd8e59b6f2042190380d1dfd16f71fe5f5af930d Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Mon, 20 Apr 2020 14:50:03 +0200
Subject: [PATCH 05/43] Moved the AMI WinBIOS SiS 471 to the Dev branch because
 literally any such BIOS I try, has problems. Also moved the Matrox cards to
 the Dev branch.

---
 src/include/86box/machine.h  |  2 ++
 src/include/86box/video.h    |  2 ++
 src/machine/m_at_386dx_486.c |  2 ++
 src/machine/machine_table.c  | 46 +++++++++++++++++++-----------------
 src/video/vid_table.c        |  2 ++
 src/win/Makefile.mingw       | 22 ++++++++++++++++-
 src/win/Makefile_ndr.mingw   | 22 ++++++++++++++++-
 7 files changed, 74 insertions(+), 24 deletions(-)

diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h
index 8a3febc15..838dc9a0d 100644
--- a/src/include/86box/machine.h
+++ b/src/include/86box/machine.h
@@ -227,7 +227,9 @@ extern int	machine_at_opti495_mr_init(const machine_t *);
 extern int	machine_at_ami471_init(const machine_t *);
 extern int	machine_at_dtk486_init(const machine_t *);
 extern int	machine_at_px471_init(const machine_t *);
+#if defined(DEV_BRANCH) && defined(USE_WIN471)
 extern int	machine_at_win471_init(const machine_t *);
+#endif
 
 extern int	machine_at_r418_init(const machine_t *);
 extern int	machine_at_ls486e_init(const machine_t *);
diff --git a/src/include/86box/video.h b/src/include/86box/video.h
index 2ee72aefe..04f81c628 100644
--- a/src/include/86box/video.h
+++ b/src/include/86box/video.h
@@ -269,9 +269,11 @@ extern const device_t ht216_32_pb410a_device;
 extern const device_t im1024_device;
 extern const device_t pgc_device;
 
+#if defined(DEV_BRANCH) && defined(USE_MGA)
 /* Matrox Mystique */
 extern const device_t mystique_device;
 extern const device_t mystique_220_device;
+#endif
 
 /* Oak OTI-0x7 */
 extern const device_t oti037c_device;
diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c
index d17525025..d168aaf14 100644
--- a/src/machine/m_at_386dx_486.c
+++ b/src/machine/m_at_386dx_486.c
@@ -267,6 +267,7 @@ machine_at_px471_init(const machine_t *model)
 }
 
 
+#if defined(DEV_BRANCH) && defined(USE_WIN471)
 int
 machine_at_win471_init(const machine_t *model)
 {
@@ -283,6 +284,7 @@ machine_at_win471_init(const machine_t *model)
 
     return ret;
 }
+#endif
 
 
 static void
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index 903f2bbe7..ae8f41b08 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -61,7 +61,7 @@
 
 
 const machine_t machines[] = {
-	//8088 Machines
+    /* 8088 Machines */
     { "[8088] AMI XT clone",			"amixt",		{{"Intel",      cpus_8088},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA,											 64,  640,  64,   0,		machine_xt_amixt_init, NULL			},
     { "[8088] Compaq Portable",			"portable",		{{"Intel",      cpus_8088},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VIDEO,									128,  640, 128,   0,	       machine_xt_compaq_init, NULL			},
     { "[8088] DTK XT clone",			"dtk",			{{"Intel",      cpus_8088},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA,											 64,  640,  64,   0,		  machine_xt_dtk_init, NULL			},
@@ -84,7 +84,7 @@ const machine_t machines[] = {
     { "[8088] Xi8088",				"xi8088",		{{"Intel",      cpus_8088},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2,								 64, 1024, 128, 127,	       machine_xt_xi8088_init, xi8088_get_device	},
     { "[8088] Zenith Data SupersPort",		"zdsupers",		{{"Intel",      cpus_8088},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA,											128,  640, 128,   0,	       machine_xt_zenith_init, NULL			},
     
-	//8086 Machines
+    /* 8086 Machines */
     { "[8086] Amstrad PC1512",			"pc1512",		{{"Intel",      cpus_pc1512}, {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE,					512,  640, 128,  63,		  machine_pc1512_init, pc1512_get_device	},
     { "[8086] Amstrad PC1640",			"pc1640",		{{"Intel",      cpus_8086},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE,							640,  640,   0,  63,		  machine_pc1640_init, pc1640_get_device	},
     { "[8086] Amstrad PC2086",			"pc2086",		{{"Intel",      cpus_8086},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE,					640,  640,   0,  63,		  machine_pc2086_init, pc2086_get_device	},
@@ -98,10 +98,10 @@ const machine_t machines[] = {
     { "[8086] VTech Laser XT3",			"lxt3",			{{"Intel",      cpus_8086},   {"",      NULL},       {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA,											256,  640, 256,   0,		 machine_xt_lxt3_init, NULL			},
 #endif
 
-	//286 XT machines
+    /* 286 XT machines */
     { "[286 XT] Hedaka HED-919",		"hed919",		{{"",      cpus_286},         {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA,											 64,  640,  64,   0,	       machine_xt_hed919_init, NULL			},
 
-	//286 AT machines
+    /* 286 AT machines */
     { "[286 ISA] AMI 286 clone",		"ami286",		{{"",      cpus_286},         {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT,										512, 8192, 128, 127,	     machine_at_neat_ami_init, NULL			},
     { "[286 ISA] Award 286 clone",		"award286",		{{"",      cpus_286},         {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT,										512,16384, 128, 127,	     machine_at_award286_init, NULL			},
     { "[286 ISA] Phoenix 286 clone",		"px286",		{{"",      cpus_286},         {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT,										512,16384, 128, 127,	     machine_at_px286_init, NULL			},
@@ -131,10 +131,10 @@ const machine_t machines[] = {
 
     { "[286 ISA] Samsung Deskmaster 286",	"deskmaster286",	{{"",      cpus_286},         {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT,										512,16384, 128, 127,	   machine_at_deskmaster286_init, NULL			},
 
-	//286 machines that utilize the MCA bus
+    /* 286 machines that utilize the MCA bus */
     { "[286 MCA] IBM PS/2 model 50",		"ibmps2_m50",		{{"Intel", cpus_ps2_m30_286}, {"IBM",cpus_IBM486SLC},{"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO,						  1,   10,   1,  63,	    machine_ps2_model_50_init, NULL			},
 
-	//386SX machines
+    /* 386SX machines */
     { "[386SX ISA] AMA-932J",			"ama932j",		{{"Intel", cpus_i386SX},      {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO,						512, 8192, 128, 127,          machine_at_ama932j_init, at_ama932j_get_device 	},
 #if defined(DEV_BRANCH) && defined(USE_AMI386SX)
     { "[386SX ISA] AMI Unknown 386SX",		"ami386",		{{"Intel", cpus_i386SX},      {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC,								512,16384, 128, 127,	     machine_at_headland_init, NULL			},
@@ -148,29 +148,29 @@ const machine_t machines[] = {
 
     { "[386SX ISA] Goldstar 386",		"goldstar386",		{{"Intel", cpus_i386SX},      {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC,								512, 8192, 128, 127,	  machine_at_goldstar386_init, NULL			},
 
-	//386SX machines which utilize the MCA bus
+    /* 386SX machines which utilize the MCA bus */
     { "[386SX MCA] IBM PS/2 model 55SX",	"ibmps2_m55sx",		{{"Intel", cpus_i386SX},      {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"",    NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO,						  1,    8,   1,  63,	  machine_ps2_model_55sx_init, NULL			},
 
-	//386DX machines
+    /* 386DX machines */
     { "[386DX ISA] Compaq Portable III (386)",  "portableiii386",       {{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO,			  			  1,   14,   1, 127,   machine_at_portableiii386_init, at_cpqiii_get_device	},
     { "[386DX ISA] ECS 386/32",			"ecs386",		{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT,										512,16384, 512, 127,	       machine_at_ecs386_init, NULL			},		
     { "[386DX ISA] Micronics 386 clone",	"micronics386",		{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC,								512, 8192, 128, 127,	 machine_at_micronics386_init, NULL			},
 
-	//386DX machines which utilize the VLB bus
+    /* 386DX machines which utilize the VLB bus */
     { "[386DX VLB] Award 386DX clone",		"award386dx",		{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	      machine_at_opti495_init, NULL			},
     { "[386DX VLB] Dataexpert SX495 (386DX)",	"ami386dx",		{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	  machine_at_opti495_ami_init, NULL			},
 #if defined(DEV_BRANCH) && defined(USE_MR495)
     { "[386DX VLB] MR 386DX clone",		"mr386dx",		{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	   machine_at_opti495_mr_init, NULL			},
 #endif
 
-	//386DX machines which utilize the MCA bus
+    /* 386DX machines which utilize the MCA bus */
     { "[386DX MCA] IBM PS/2 model 70 (type 3)",	"ibmps2_m70_type3",	{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"",     NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO,						  2,   16,   2,  63,  machine_ps2_model_70_type3_init, NULL			},
     { "[386DX MCA] IBM PS/2 model 80",		"ibmps2_m80",		{{"Intel", cpus_i386DX},      {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"",     NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO,						  1,   12,   1,  63,	    machine_ps2_model_80_init, NULL			},
 
-	//486 machines with just the ISA slot
+    /* 486 machines with just the ISA slot */
     { "[486 ISA] Packard Bell PB410A",		"pb410a",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO,			  	  4,   36,   1, 127,	       machine_at_pb410a_init, NULL			},    
 
-	//486 machines
+    /* 486 machines */
     { "[486 VLB] Award 486 clone",		"award486",		{{"Intel", cpus_i486S1},      {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	      machine_at_opti495_init, NULL			},    
     { "[486 VLB] Dataexpert SX495 (486)",	"ami486",		{{"Intel", cpus_i486S1},      {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	  machine_at_opti495_ami_init, NULL			},
     { "[486 VLB] Olystar LIL1429",		"ali1429",		{{"Intel", cpus_i486S1},      {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	      machine_at_ali1429_init, NULL			},
@@ -179,7 +179,9 @@ const machine_t machines[] = {
 #endif
     { "[486 VLB] AMI SiS 471",			"ami471",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   64,   1, 127,	       machine_at_ami471_init, NULL			},
     { "[486 VLB] AMI WinBIOS 486",		"win486",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   32,   1, 127,	  machine_at_winbios1429_init, NULL			},
+#if defined(DEV_BRANCH) && defined(USE_WIN471)
     { "[486 VLB] AMI WinBIOS SiS 471",		"win471",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   64,   1, 127,	       machine_at_win471_init, NULL			},
+#endif
     { "[486 VLB] DTK PKM-0038S E-2",		"dtk486",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC,						  1,   64,   1, 127,	       machine_at_dtk486_init, NULL			},
 
 #if defined(DEV_BRANCH) && defined(USE_MR495)
@@ -191,14 +193,14 @@ const machine_t machines[] = {
     { "[486 MCA] IBM PS/2 model 70 (type 4)",	"ibmps2_m70_type4",	{{"Intel", cpus_i486S1},      {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"",      NULL},     {"",      NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO,						  2,   16,   2,  63,  machine_ps2_model_70_type4_init, NULL			},
 #endif
 
-	//486 machines which utilize the PCI bus
+    /* 486 machines which utilize the PCI bus */
     { "[486 PCI] ASUS PCI/I-486SP3G",		"486sp3g",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  1,  128,   1, 127,	      machine_at_486sp3g_init, NULL			},
     { "[486 PCI] Intel Classic/PCI",		"alfredo",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  2,  128,   2, 127,	      machine_at_alfredo_init, NULL			},
     { "[486 PCI] Lucky Star LS-486E",		"ls486e",		{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  1,  128,   1, 127,	       machine_at_ls486e_init, NULL			},
     { "[486 PCI] Rise Computer R418",		"r418",			{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  1,  255,   1, 127,		 machine_at_r418_init, NULL			},
     { "[486 PCI] Zida Tomato 4DP",		"4dps",			{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  1,  255,   1, 127,		 machine_at_4dps_init, NULL			},
 
-	//Socket 4 machines
+    /* Socket 4 machines */
     { "[Socket 4 LX] IBM Ambra DP60 PCI",	"ambradp60",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	    machine_at_ambradp60_init, NULL			},
 #if defined(DEV_BRANCH) && defined(USE_VPP60)
     { "[Socket 4 LX] IBM PS/ValuePoint P60",	"valuepointp60",	{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  2,  128,   2, 127,	machine_at_valuepointp60_init, NULL			},
@@ -206,7 +208,7 @@ const machine_t machines[] = {
     { "[Socket 4 LX] Intel Premiere/PCI",	"revenge",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	       machine_at_batman_init, NULL			},
     { "[Socket 4 LX] Micro Star 586MC1",	"586mc1",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  2,  128,   2, 127,	       machine_at_586mc1_init, NULL			},
 
-	//Socket 5 machines
+    /* Socket 5 machines */
     { "[Socket 5 NX] Intel Premiere/PCI II",	"plato",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,		machine_at_plato_init, NULL			},
     { "[Socket 5 NX] IBM Ambra DP90 PCI",	"ambradp90",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	    machine_at_ambradp90_init, NULL			},
     { "[Socket 5 NX] Gigabyte GA-586IP",	"430nx",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,		machine_at_430nx_init, NULL			},
@@ -220,7 +222,7 @@ const machine_t machines[] = {
     { "[Socket 5 FX] PC Partner MB500N",	"mb500n",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 127,	       machine_at_mb500n_init, NULL			},
     { "[Socket 5 FX] President Award 430FX PCI","president",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 127,	    machine_at_president_init, NULL			},
 
-	//Socket 7 machines
+    /* Socket 7 machines */
     { "[Socket 7-3V FX] ASUS P/I-P54TP4XE",	"p54tp4xe",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	     machine_at_p54tp4xe_init, NULL			},
     { "[Socket 7-3V FX] Intel Advanced/ATX",	"thor",			MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,		 machine_at_thor_init, NULL			},
     { "[Socket 7-3V FX] Intel Advanced/EV",	"endeavor",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO,			  8,  128,   8, 127,	     machine_at_endeavor_init, at_endeavor_get_device	},
@@ -243,7 +245,7 @@ const machine_t machines[] = {
     { "[Socket 7 VX] Jetway J656VXD",		"j656vxd",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 127,	      machine_at_j656vxd_init, NULL			},
     { "[Socket 7 VX] PC Partner MB520N",	"mb520n",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	       machine_at_mb520n_init, NULL			},
     { "[Socket 7 VX] Shuttle HOT-557",		"430vx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	       machine_at_i430vx_init, NULL			},
-    // txp4 for compatibility reasons
+
     { "[Socket 7 TX] ASUS TX97",		"tx97",			MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	         machine_at_tx97_init, NULL			},
     { "[Socket 7 TX] Gigabyte GA-586T2",        "586t2",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_586t2_init, NULL			},
     { "[Socket 7 TX] Intel YM430TX",		"ym430tx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_ym430tx_init, NULL			},
@@ -255,17 +257,17 @@ const machine_t machines[] = {
  
     { "[Socket 7 VP3] QDI Advance II",		"advanceii",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	    machine_at_advanceii_init, NULL			},
     
-	//Super Socket 7 machines
+    /* Super Socket 7 machines */
     { "[Super 7 MVP3] AOpen AX59 Pro",		"ax59pro",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8, 1024,  8, 255,	      machine_at_ax59pro_init, NULL			},
     { "[Super 7 MVP3] FIC VA-503+",		"ficva503p",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,  8, 255,	         machine_at_mvp3_init, NULL			},
 
-	//Socket 8 machines
+    /* Socket 8 machines */
     { "[Socket 8 FX] Gigabyte GA-686NX",	"686nx",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	        machine_at_686nx_init, NULL			},
     { "[Socket 8 FX] PC Partner MB600N",	"mb600n",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	       machine_at_mb600n_init, NULL			},
     { "[Socket 8 FX] Biostar MB-8500ttc",	"8500ttc",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	      machine_at_8500ttc_init, NULL			},
     { "[Socket 8 FX] Micronics M6MI",		"m6mi",			{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	         machine_at_m6mi_init, NULL			},
-    
-	//Slot 1 machines
+
+    /* Slot 1 machines */
     { "[Slot 1 FX] ECS P6KFX-A",		"p6kfx",		{{"Intel", cpus_PentiumII_28v},{"",    NULL},        {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	        machine_at_p6kfx_init, NULL			},
 
     { "[Slot 1 BX] Gigabyte GA-6BXC",		"6bxc",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		 machine_at_6bxc_init, NULL			},
@@ -275,7 +277,7 @@ const machine_t machines[] = {
 
     { "[Slot 1 ZX] Packard Bell Bora Pro",	"borapro",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 255,	      machine_at_borapro_init, NULL			},
 
-	//PGA370 machines
+    /* PGA370 machines */
     { "[Socket 370 BX] ASUS CUBX",		"cubx",			{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_cubx_init, NULL			},
     { "[Socket 370 BX] A-Trend ATC7020BXII",	"atc7020bxii",		{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,	  machine_at_atc7020bxii_init, NULL			},
     { "[Socket 370 ZX] Soltek SL-63A1",		"63a",			{{"Intel", cpus_Celeron},     {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 255,		  machine_at_63a_init, NULL			},
diff --git a/src/video/vid_table.c b/src/video/vid_table.c
index 57f77b83e..f1f10835b 100644
--- a/src/video/vid_table.c
+++ b/src/video/vid_table.c
@@ -122,8 +122,10 @@ video_cards[] = {
     { "[PCI] Diamond Stealth 3D 3000 (S3 ViRGE/VX)",	"stealth3d_3000_pci",	&s3_virge_988_pci_device		},
     { "[PCI] Diamond Stealth 64 DRAM (S3 Trio64)",	"stealth64d_pci",	&s3_diamond_stealth64_pci_device	},
     { "[PCI] Diamond Stealth 64 VRAM (S3 Vision964)",	"stealth64v_pci",	&s3_diamond_stealth64_964_pci_device	},
+#if defined(DEV_BRANCH) && defined(USE_MGA)
     { "[PCI] Matrox Mystique",				"mystique",		&mystique_device			},
     { "[PCI] Matrox Mystique 220",			"mystique_220",		&mystique_220_device			},
+#endif
     { "[PCI] Number Nine 9FX (S3 Trio64)",		"n9_9fx_pci",		&s3_9fx_pci_device			},
     { "[PCI] Paradise Bahamas 64 (S3 Vision864)",	"bahamas64_pci",	&s3_bahamas64_pci_device		},
     { "[PCI] Phoenix S3 Vision864",			"px_vision864_pci",	&s3_phoenix_vision864_pci_device	},
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index b1da998a4..f48318b7d 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -47,6 +47,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef LASERXT
   LASERXT	:= y
  endif
+ ifndef MGA
+  MGA		:= y
+ endif
  ifndef MR495
   MR495		:= y
  endif
@@ -83,6 +86,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef VNC
   VNC		:= y
  endif
+ ifndef WIN471
+  WIN471	:= y
+ endif
  ifndef XL24
   XL24		:= y
  endif
@@ -102,6 +108,9 @@ else
  ifndef LASERXT
   LASERXT	:= n
  endif
+ ifndef MGA
+  MGA		:= n
+ endif
  ifndef MR495
   MR495		:= n
  endif
@@ -135,6 +144,9 @@ else
  ifndef VNC
   VNC		:= n
  endif
+ ifndef WIN471
+  WIN471	:= n
+ endif
  ifndef XL24
   XL24		:= n
  endif
@@ -414,6 +426,11 @@ OPTS		+= -DUSE_LASERXT
 DEVBROBJ	+= m_xt_laserxt.o
 endif
 
+ifeq ($(MGA), y)
+OPTS		+= -DUSE_MGA
+DEVBROBJ	+= vid_mga.o
+endif
+
 ifeq ($(MR495), y)
 OPTS		+= -DUSE_MR495
 endif
@@ -459,6 +476,10 @@ ifeq ($(VGAWONDER), y)
 OPTS		+= -DUSE_VGAWONDER
 endif
 
+ifeq ($(WIN471), y)
+OPTS		+= -DUSE_WIN471
+endif
+
 ifeq ($(XL24), y)
 OPTS		+= -DUSE_XL24
 endif
@@ -639,7 +660,6 @@ VIDOBJ		:= video.o \
 		    vid_et4000.o vid_sc1502x_ramdac.o \
 		    vid_et4000w32.o vid_stg_ramdac.o \
 		    vid_ht216.o \
-			vid_mga.o \
 		    vid_oak_oti.o \
 		    vid_paradise.o \
 		    vid_ti_cf62011.o \
diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw
index 63aa78608..a5242812d 100644
--- a/src/win/Makefile_ndr.mingw
+++ b/src/win/Makefile_ndr.mingw
@@ -47,6 +47,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef LASERXT
   LASERXT	:= y
  endif
+ ifndef MGA
+  MGA		:= y
+ endif
  ifndef MR495
   MR495		:= y
  endif
@@ -83,6 +86,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef VNC
   VNC		:= y
  endif
+ ifndef WIN471
+  WIN471		:= y
+ endif
  ifndef XL24
   XL24		:= y
  endif
@@ -102,6 +108,9 @@ else
  ifndef LASERXT
   LASERXT	:= n
  endif
+ ifndef MGA
+  MGA		:= n
+ endif
  ifndef MR495
   MR495		:= n
  endif
@@ -138,6 +147,9 @@ else
  ifndef VNC
   VNC		:= n
  endif
+ ifndef WIN471
+  WIN471		:= n
+ endif
  ifndef XL24
   XL24		:= n
  endif
@@ -423,6 +435,11 @@ OPTS		+= -DUSE_LASERXT
 DEVBROBJ	+= m_xt_laserxt.o
 endif
 
+ifeq ($(MGA), y)
+OPTS		+= -DUSE_MGA
+DEVBROBJ	+= vid_mga.o
+endif
+
 ifeq ($(MR495), y)
 OPTS		+= -DUSE_MR495
 endif
@@ -468,6 +485,10 @@ ifeq ($(VGAWONDER), y)
 OPTS		+= -DUSE_VGAWONDER
 endif
 
+ifeq ($(WIN471), y)
+OPTS		+= -DUSE_WIN471
+endif
+
 ifeq ($(XL24), y)
 OPTS		+= -DUSE_XL24
 endif
@@ -643,7 +664,6 @@ VIDOBJ		:= video.o \
 		    vid_et4000.o vid_sc1502x_ramdac.o \
 		    vid_et4000w32.o vid_stg_ramdac.o \
 		    vid_ht216.o \
-			vid_mga.o \
 		    vid_oak_oti.o \
 		    vid_paradise.o \
 		    vid_ti_cf62011.o \

From de15c50a5b32e5c701d15b96446a25200ac14e25 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Mon, 20 Apr 2020 14:51:25 +0200
Subject: [PATCH 06/43] Removed some excess files.

---
 src/x87_bak/x87.h               |   58 -
 src/x87_bak/x87_ops.h           | 2147 -------------------------------
 src/x87_bak/x87_ops_arith.h     |  427 ------
 src/x87_bak/x87_ops_loadstore.h |  492 -------
 src/x87_bak/x87_ops_misc.h      |  877 -------------
 5 files changed, 4001 deletions(-)
 delete mode 100644 src/x87_bak/x87.h
 delete mode 100644 src/x87_bak/x87_ops.h
 delete mode 100644 src/x87_bak/x87_ops_arith.h
 delete mode 100644 src/x87_bak/x87_ops_loadstore.h
 delete mode 100644 src/x87_bak/x87_ops_misc.h

diff --git a/src/x87_bak/x87.h b/src/x87_bak/x87.h
deleted file mode 100644
index be30c280c..000000000
--- a/src/x87_bak/x87.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#define C0 (1<<8)
-#define C1 (1<<9)
-#define C2 (1<<10)
-#define C3 (1<<14)
-
-uint32_t x87_pc_off,x87_op_off;
-uint16_t x87_pc_seg,x87_op_seg;
-
-static inline void x87_set_mmx()
-{
-#ifdef USE_NEW_DYNAREC
-        cpu_state.TOP = 0;
-        *(uint64_t *)cpu_state.tag = 0x0101010101010101ull;
-        cpu_state.ismmx = 1;
-#else
-	uint64_t *p;
-        cpu_state.TOP = 0;
-	p = (uint64_t *)cpu_state.tag;
-        *p = 0;
-        cpu_state.ismmx = 1;
-#endif
-}
-
-static inline void x87_emms()
-{
-#ifdef USE_NEW_DYNAREC
-        *(uint64_t *)cpu_state.tag = 0;
-        cpu_state.ismmx = 0;
-#else
-	uint64_t *p;
-	p = (uint64_t *)cpu_state.tag;
-        *p = 0;
-        cpu_state.ismmx = 0;
-#endif
-}
-
-
-uint16_t x87_gettag();
-void x87_settag(uint16_t new_tag);
-
-#ifdef USE_NEW_DYNAREC
-#define TAG_EMPTY  0
-#define TAG_VALID  (1 << 0)
-/*Hack for FPU copy. If set then MM[].q contains the 64-bit integer loaded by FILD*/
-#define TAG_UINT64 (1 << 7)
-
-#define X87_ROUNDING_NEAREST 0
-#define X87_ROUNDING_DOWN    1
-#define X87_ROUNDING_UP      2
-#define X87_ROUNDING_CHOP    3
-
-void codegen_set_rounding_mode(int mode);
-#else
-#define TAG_EMPTY  0
-#define TAG_VALID  (1 << 0)
-/*Hack for FPU copy. If set then MM[].q contains the 64-bit integer loaded by FILD*/
-#define TAG_UINT64 (1 << 2)
-#endif
diff --git a/src/x87_bak/x87_ops.h b/src/x87_bak/x87_ops.h
deleted file mode 100644
index 5e1530a23..000000000
--- a/src/x87_bak/x87_ops.h
+++ /dev/null
@@ -1,2147 +0,0 @@
-/*
- * 86Box	A hypervisor and IBM PC system emulator that specializes in
- *		running old operating systems and software designed for IBM
- *		PC systems and compatibles from 1981 through fairly recent
- *		system designs based on the PCI bus.
- *
- *		This file is part of the 86Box distribution.
- *
- *		x87 FPU instructions core.
- *
- *
- *
- * Authors:	Fred N. van Kempen, <decwiz@yahoo.com>
- *		Sarah Walker, <tommowalker@tommowalker.co.uk>
- *		leilei,
- *		Miran Grca, <mgrca8@gmail.com>
- *
- *		Copyright 2008-2019 Sarah Walker.
- *		Copyright 2016-2019 leilei.
- *		Copyright 2016-2019 Miran Grca.
- *		Copyright 2018,2019 Fred N. van Kempen.
- */
-#include <math.h>
-#include <fenv.h>
-#ifdef _MSC_VER
-# include <intrin.h>
-#endif
-// #include "x87_timings.h"
-
-#ifdef ENABLE_FPU_LOG
-extern void	fpu_log(const char *fmt, ...);
-#else
-#ifndef fpu_log
-#define fpu_log(fmt, ...)
-#endif
-#endif
-
-static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZERO};
-
-#define ST(x) cpu_state.ST[((cpu_state.TOP+(x))&7)]
-
-#define STATUS_ZERODIVIDE 4
-
-#ifdef FPU_8087
-#define x87_div(dst, src1, src2) do                             \
-        {                                                       \
-                if (((double)src2) == 0.0)                      \
-                {                                               \
-                        cpu_state.npxs |= STATUS_ZERODIVIDE;    \
-                        if (cpu_state.npxc & STATUS_ZERODIVIDE) \
-                                dst = src1 / (double)src2;      \
-                        else                                    \
-                        {                                       \
-                                fpu_log("FPU : divide by zero\n"); \
-				if (!(cpu_state.npxc & 0x80)) {	\
-					cpu_state.npxs |= 0x80;	\
-					nmi = 1;		\
-				}				\
-                                return 1;                       \
-                        }                                       \
-                }                                               \
-                else                                            \
-                        dst = src1 / (double)src2;              \
-        } while (0)
-#else
-#define x87_div(dst, src1, src2) do                             \
-        {                                                       \
-                if (((double)src2) == 0.0)                      \
-                {                                               \
-                        cpu_state.npxs |= STATUS_ZERODIVIDE;    \
-                        if (cpu_state.npxc & STATUS_ZERODIVIDE) \
-                                dst = src1 / (double)src2;      \
-                        else                                    \
-                        {                                       \
-                                fpu_log("FPU : divide by zero\n"); \
-                                picint(1 << 13);        	\
-                                return 1;                       \
-                        }                                       \
-                }                                               \
-                else                                            \
-                        dst = src1 / (double)src2;              \
-        } while (0)
-#endif
-        
-static __inline void x87_checkexceptions()
-{
-}
-
-static __inline void x87_push(double i)
-{
-#ifdef USE_NEW_DYNAREC
-        cpu_state.TOP--;
-        cpu_state.ST[cpu_state.TOP&7] = i;
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
-#else
-        cpu_state.TOP=(cpu_state.TOP-1)&7;
-        cpu_state.ST[cpu_state.TOP] = i;
-        cpu_state.tag[cpu_state.TOP&7] = (i == 0.0) ? 1 : 0;
-#endif
-}
-
-static __inline void x87_push_u64(uint64_t i)
-{
-        union
-        {
-                double d;
-                uint64_t ll;
-        } td;
-                
-        td.ll = i;
-
-#ifdef USE_NEW_DYNAREC
-        cpu_state.TOP--;
-        cpu_state.ST[cpu_state.TOP&7] = td.d;
-        cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
-#else
-        cpu_state.TOP=(cpu_state.TOP-1)&7;
-        cpu_state.ST[cpu_state.TOP] = td.d;
-        cpu_state.tag[cpu_state.TOP&7] = (td.d == 0.0) ? 1 : 0;
-#endif
-}
-
-static __inline double x87_pop()
-{
-#ifdef USE_NEW_DYNAREC
-        double t = cpu_state.ST[cpu_state.TOP&7];
-        cpu_state.tag[cpu_state.TOP&7] = TAG_EMPTY;
-        cpu_state.TOP++;
-        return t;
-#else
-        double t = cpu_state.ST[cpu_state.TOP];
-        cpu_state.tag[cpu_state.TOP&7] = 3;
-        cpu_state.TOP=(cpu_state.TOP+1)&7;
-        return t;
-#endif
-}
-
-static int old_round = FE_TONEAREST;
-
-static __inline int64_t x87_round_save(void)
-{
-    old_round = fetgetround();
-}
-
-static __inline int64_t x87_round_set(void)
-{
-    old_round = fetgetround();
-
-    switch ((cpu_state.npxc >> 10) & 3) {
-	case 0: /*Nearest*/
-		fesetround(FE_TONEAREST);
-		break;
-	case 1: /*Down*/
-		fesetround(FE_DOWNWARD);
-		break;
-	case 2: /*Up*/
-		fesetround(FE_UPWARD);
-		break;
-	case 3: /*Chop*/
-		fesetround(FE_TOWARDZERO);
-		break;
-    }
-}
-
-static __inline int64_t x87_round_restore(void)
-{
-    fesetround(old_round);
-}
-
-#ifdef PCEM_CODE
-static __inline int64_t x87_fround(double b)
-{
-#ifdef PCEM_CODE
-        int64_t a, c;
-#endif
-        
-        switch ((cpu_state.npxc >> 10) & 3)
-        {
-                case 0: /*Nearest*/
-#ifdef PCEM_CODE
-                a = (int64_t)floor(b);
-                c = (int64_t)floor(b + 1.0);
-                if ((b - a) < (c - b))
-                        return a;
-                else if ((b - a) > (c - b))
-                        return c;
-                else
-                        return (a & 1) ? c : a;
-#else
-		return (int64_t)round(b);
-#endif
-                case 1: /*Down*/
-                return (int64_t)floor(b);
-                case 2: /*Up*/
-                return (int64_t)ceil(b);
-                case 3: /*Chop*/
-#ifdef PCEM_CODE
-                return (int64_t)b;
-#else
-		return (int64_t)trunc(b);
-#endif
-        }
-        
-        return 0;
-}
-#else
-static __inline int64_t x87_fround(double b)
-{
-    int64_t ret;
-
-    x87_round_set();
-    ret = (int64_t) rint(b);
-    x87_round_restore();
-}
-#endif
-#define BIAS80 16383
-#define BIAS64 1023
-
-static __inline double x87_ld80()
-{
-       	int64_t exp64;
-       	int64_t blah;
-       	int64_t exp64final;
-      	int64_t mant64;
-       	int64_t sign;
-
-	struct {
-		int16_t begin;
-		union
-		{
-                        double d;
-                        uint64_t ll;
-                } eind;
-	} test;
-
-	test.eind.ll = readmeml(easeg,cpu_state.eaaddr);
-	test.eind.ll |= (uint64_t)readmeml(easeg,cpu_state.eaaddr+4)<<32;
-	test.begin = readmemw(easeg,cpu_state.eaaddr+8);
-
-       	exp64 = (((test.begin&0x7fff) - BIAS80));
-       	blah = ((exp64 >0)?exp64:-exp64)&0x3ff;
-       	exp64final = ((exp64 >0)?blah:-blah) +BIAS64;
-
-       	mant64 = (test.eind.ll >> 11) & (0xfffffffffffffll);
-       	sign = (test.begin&0x8000)?1:0;
-
-        if ((test.begin & 0x7fff) == 0x7fff)
-                exp64final = 0x7ff;
-        if ((test.begin & 0x7fff) == 0)
-                exp64final = 0;
-        if (test.eind.ll & 0x400) 
-                mant64++;
-
-        test.eind.ll = (sign <<63)|(exp64final << 52)| mant64;
-
-	return test.eind.d;
-}
-
-static __inline void x87_st80(double d)
-{
-       	int64_t sign80;
-       	int64_t exp80;
-       	int64_t exp80final;
-       	int64_t mant80;
-       	int64_t mant80final;
-
-	struct {
-		int16_t begin;
-		union
-		{
-                        double d;
-                        uint64_t ll;
-                } eind;
-	} test;
-	
-	test.eind.d=d;
-	
-       	sign80 = (test.eind.ll&(0x8000000000000000ll))?1:0;
-       	exp80 =  test.eind.ll&(0x7ff0000000000000ll);
-       	exp80final = (exp80>>52);
-       	mant80 = test.eind.ll&(0x000fffffffffffffll);
-       	mant80final = (mant80 << 11);
-
-       	if (exp80final == 0x7ff) /*Infinity / Nan*/
-       	{
-                exp80final = 0x7fff;
-                mant80final |= (0x8000000000000000ll);
-        }
-       	else if (d != 0){  /* Zero is a special case */
-       		/* Elvira wants the 8 and tcalc doesn't */
-       		mant80final |= (0x8000000000000000ll);
-       		/* Ca-cyber doesn't like this when result is zero. */
-       		exp80final += (BIAS80 - BIAS64);
-       	}
-       	test.begin = (((int16_t)sign80)<<15)| (int16_t)exp80final;
-       	test.eind.ll = mant80final;
-
-	writememl(easeg,cpu_state.eaaddr,test.eind.ll & 0xffffffff);
-	writememl(easeg,cpu_state.eaaddr+4,test.eind.ll>>32);
-	writememw(easeg,cpu_state.eaaddr+8,test.begin);
-}
-
-static __inline void x87_st_fsave(int reg)
-{
-        reg = (cpu_state.TOP + reg) & 7;
-        
-        if (cpu_state.tag[reg] & TAG_UINT64)
-        {
-        	writememl(easeg, cpu_state.eaaddr, cpu_state.MM[reg].q & 0xffffffff);
-        	writememl(easeg, cpu_state.eaaddr + 4, cpu_state.MM[reg].q >> 32);
-        	writememw(easeg, cpu_state.eaaddr + 8, 0x5555);
-        }
-        else
-                x87_st80(cpu_state.ST[reg]);
-}
-
-static __inline void x87_ld_frstor(int reg)
-{
-        reg = (cpu_state.TOP + reg) & 7;
-        
-        cpu_state.MM[reg].q = readmemq(easeg, cpu_state.eaaddr);
-        cpu_state.MM_w4[reg] = readmemw(easeg, cpu_state.eaaddr + 8);
-
-#ifdef USE_NEW_DYNAREC
-        if ((cpu_state.MM_w4[reg] == 0x5555) && (cpu_state.tag[reg] & TAG_UINT64))
-        {
-                cpu_state.ST[reg] = (double)cpu_state.MM[reg].q;
-        }
-        else
-        {
-                cpu_state.tag[reg] &= ~TAG_UINT64;
-                cpu_state.ST[reg] = x87_ld80();
-        }
-#else
-        if (cpu_state.MM_w4[reg] == 0x5555 && cpu_state.tag[reg] == 2)
-        {
-                cpu_state.tag[reg] = TAG_UINT64;
-                cpu_state.ST[reg] = (double)cpu_state.MM[reg].q;
-        }
-        else
-                cpu_state.ST[reg] = x87_ld80();
-#endif
-}
-
-static __inline void x87_ldmmx(MMX_REG *r, uint16_t *w4)
-{
-        r->l[0] = readmeml(easeg, cpu_state.eaaddr);
-        r->l[1] = readmeml(easeg, cpu_state.eaaddr + 4);
-        *w4 = readmemw(easeg, cpu_state.eaaddr + 8);
-}
-
-static __inline void x87_stmmx(MMX_REG r)
-{
-        writememl(easeg, cpu_state.eaaddr,     r.l[0]);
-        writememl(easeg, cpu_state.eaaddr + 4, r.l[1]);
-        writememw(easeg, cpu_state.eaaddr + 8, 0xffff);
-}
-
-#include <inttypes.h>
-
-static __inline uint16_t x87_compare(double a, double b)
-{
-#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
-        uint32_t result;
-	double ea = a, eb = b;
-	const uint64_t ia = 0x3fec1a6ff866a936ull;
-	const uint64_t ib = 0x3fec1a6ff866a938ull;
-
-	/* Hack to make CHKCOP happy. */
-	if (!memcmp(&ea, &ia, 8) && !memcmp(&eb, &ib, 8))
-		return C3;
-
-	if (!is386 && !(cpu_state.npxc & 0x1000) &&
-	    ((a == INFINITY) || (a == -INFINITY)) && ((b == INFINITY) || (b == -INFINITY)))
-		eb = ea;
-
-#ifndef _MSC_VER
-        /* Memory barrier, to force GCC to write to the input parameters
-         * before the compare rather than after */
-        __asm volatile ("" : : : "memory");
-        
-        __asm(
-                "fldl %2\n"
-                "fldl %1\n"
-                "fclex\n"
-                "fcompp\n"                
-                "fnstsw %0\n"
-                : "=m" (result)
-                : "m" (ea), "m" (eb)
-        );
-#else
-        _ReadWriteBarrier();
-        _asm
-        {
-                fld eb
-                fld ea
-                fclex
-                fcompp
-                fnstsw result
-        }
-#endif
-
-        return result & (C0|C2|C3);
-#else
-        /* Generic C version is known to give incorrect results in some
-         * situations, eg comparison of infinity (Unreal) */
-        uint32_t result = 0;
-	double ea = a, eb = b;
-
-	if (!is386 && !(cpu_state.npxc & 0x1000) &&
-	    ((a == INFINITY) || (a == -INFINITY)) && ((b == INFINITY) || (b == -INFINITY)))
-		eb = ea;
-
-        if (ea == eb)
-                result |= C3;
-        else if (ea < eb)
-                result |= C0;
-                
-        return result;
-#endif
-}
-
-static __inline uint16_t x87_ucompare(double a, double b)
-{
-#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64 || defined __amd64__
-        uint32_t result;
-        
-#ifndef _MSC_VER
-        /* Memory barrier, to force GCC to write to the input parameters
-         * before the compare rather than after */
-        asm volatile ("" : : : "memory");
-        
-        asm(
-                "fldl %2\n"
-                "fldl %1\n"
-                "fclex\n"
-                "fucompp\n"                
-                "fnstsw %0\n"
-                : "=m" (result)
-                : "m" (a), "m" (b)
-        );
-#else
-        _ReadWriteBarrier();
-        _asm
-        {
-                fld b
-                fld a
-                fclex
-                fcompp
-                fnstsw result
-        }
-#endif
-
-        return result & (C0|C2|C3);
-#else
-        /* Generic C version is known to give incorrect results in some
-         * situations, eg comparison of infinity (Unreal) */
-        uint32_t result = 0;
-        
-        if (a == b)
-                result |= C3;
-        else if (a < b)
-                result |= C0;
-                
-        return result;
-#endif
-}
-
-typedef union
-{
-        float s;
-        uint32_t i;
-} x87_ts;
-
-typedef union
-{
-        double d;
-        uint64_t i;
-} x87_td;
-
-#ifdef FPU_8087
-#define FP_ENTER() {			\
-		fpucount++;		\
-	}
-#else
-#define FP_ENTER() do                   \
-        {                               \
-                if (cr0 & 0xc)          \
-                {                       \
-                        x86_int(7);     \
-                        return 1;       \
-                }                       \
-                fpucount++;             \
-        } while (0)
-#endif
-
-// #ifdef USE_NEW_DYNAREC
-#if 1
-#define FP_TAG() cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
-#define FP_FTAG() cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
-#define FP_LSTAG()  cpu_state.tag[cpu_state.TOP&7] = TAG_VALID | TAG_UINT64;
-#define FP_LSQ()  cpu_state.MM[cpu_state.TOP&7].q = temp64;
-#define FP_LSRETQ()  temp64 = cpu_state.MM[cpu_state.TOP&7].q;
-#define FP_NTAG() cpu_state.tag[(cpu_state.TOP + 1) & 7] = TAG_VALID;
-#ifdef USE_NEW_DYNAREC
-#define FP_NNPXC() codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#else
-#define FP_NNPXC() cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00) | (cpu_state.npxc & 0xc00);
-#endif
-#define FP_TOP(x) (x & 7)
-#define FP_DTAG 0ULL
-#define FP_CTAG 0x0101010101010101ull
-#define FP_EMPTY TAG_EMPTY
-#ifdef USE_NEW_DYNAREC
-#define FP_RNPXC() codegen_set_rounding_mode(X87_ROUNDING_NEAREST);
-#else
-#define FP_RNPXC() cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
-#endif
-#define FP_ZTAG() cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
-#define FP_DECTOP() cpu_state.TOP--;
-#define FP_INCTOP() cpu_state.TOP++;
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)))
-#define FP_686
-#endif
-#else
-#define FP_TAG() cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
-#define FP_FTAG() cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
-#define FP_LSTAG()  cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
-#define FP_LSQ()  cpu_state.MM[cpu_state.TOP].q = temp64;
-#define FP_LSRETQ()  temp64 = cpu_state.MM[cpu_state.TOP].q;
-#define FP_NTAG() cpu_state.tag[(cpu_state.TOP + 1) & 7] &= ~TAG_UINT64;
-#define FP_NNPXC() cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00) | (cpu_state.npxc & 0xc00);
-#define FP_TOP(x) (x)
-#define FP_DTAG 0x0303030303030303ll
-#define FP_CTAG 0ULL
-#define FP_EMPTY 3
-#define FP_RNPXC() cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
-#define FP_ZTAG() cpu_state.tag[cpu_state.TOP&7] = 1;
-#define FP_DECTOP() cpu_state.TOP = (cpu_state.TOP - 1) & 7
-#define FP_INCTOP() cpu_state.TOP = (cpu_state.TOP + 1) & 7
-#if defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686))
-#define FP_686
-#endif
-#endif
-
-#include "x87_ops_arith.h"
-#include "x87_ops_misc.h"
-#include "x87_ops_loadstore.h"
-
-#ifndef FPU_8087
-static int op_nofpu_a16(uint32_t fetchdat)
-{
-        if (cr0 & 0xc)
-        {
-                x86_int(7);
-                return 1;
-        }
-        else
-	{
-                fetch_ea_16(fetchdat);
-		return 0;
-	}
-}
-static int op_nofpu_a32(uint32_t fetchdat)
-{
-        if (cr0 & 0xc)
-        {
-                x86_int(7);
-                return 1;
-        }
-        else
-	{
-                fetch_ea_32(fetchdat);
-		return 0;
-	}
-}
-#endif
-
-#ifdef FPU_8087
-static int FPU_ILLEGAL_a16(uint32_t fetchdat)
-{
-	geteaw();
-        wait(timing_rr, 0);
-        return 0;
-}
-#else
-static int FPU_ILLEGAL_a16(uint32_t fetchdat)
-{
-        fetch_ea_16(fetchdat);
-        CLOCK_CYCLES(timing_rr);
-        PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
-        return 0;
-}
-
-static int FPU_ILLEGAL_a32(uint32_t fetchdat)
-{
-        fetch_ea_32(fetchdat);
-        CLOCK_CYCLES(timing_rr);
-        PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
-        return 0;
-}
-#endif
-
-#define ILLEGAL_a16 FPU_ILLEGAL_a16
-
-#ifdef FPU_8087
-const OpFn OP_TABLE(fpu_8087_d8)[32] =
-{
-        opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
-        opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
-        opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
-        opFADD,      opFMUL,      opFCOM,      opFCOMP,      opFSUB,      opFSUBR,      opFDIV,      opFDIVR
-};
-
-const OpFn OP_TABLE(fpu_8087_d9)[256] =
-{
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,
-        opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,
-        opFNOP,       ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16, /*Invalid*/
-        opFCHS,       opFABS,       ILLEGAL_a16,  ILLEGAL_a16,  opFTST,       opFXAM,       ILLEGAL_a16,  ILLEGAL_a16,
-        opFLD1,       opFLDL2T,     opFLDL2E,     opFLDPI,      opFLDEG2,     opFLDLN2,     opFLDZ,       ILLEGAL_a16,
-        opF2XM1,      opFYL2X,      opFPTAN,      opFPATAN,     ILLEGAL_a16,  ILLEGAL_a16,  opFDECSTP,    opFINCSTP,
-        opFPREM,      opFYL2XP1,    opFSQRT,      ILLEGAL_a16,   opFRNDINT,   opFSCALE,     ILLEGAL_a16,  ILLEGAL_a16
-};
-
-const OpFn OP_TABLE(fpu_8087_da)[256] =
-{
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-
-const OpFn OP_TABLE(fpu_8087_db)[256] =
-{
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFI,         opFI,         opFCLEX,      opFINIT,      ILLEGAL_a16,  opFNOP,       ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-
-const OpFn OP_TABLE(fpu_8087_dc)[32] =
-{
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDr,     opFMULr,     ILLEGAL_a16, ILLEGAL_a16,  opFSUBRr,    opFSUBr,      opFDIVRr,    opFDIVr
-};
-
-const OpFn OP_TABLE(fpu_8087_dd)[256] =
-{
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-
-const OpFn OP_TABLE(fpu_8087_de)[256] =
-{
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,
-        opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  opFCOMPP,     ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,
-        opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,
-        opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,
-        opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,
-};
-
-const OpFn OP_TABLE(fpu_8087_df)[256] =
-{
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-#else
-#define ILLEGAL_a32 FPU_ILLEGAL_a32
-
-const OpFn OP_TABLE(fpu_d8_a16)[32] =
-{
-        opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
-        opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
-        opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
-        opFADD,      opFMUL,      opFCOM,      opFCOMP,      opFSUB,      opFSUBR,      opFDIV,      opFDIVR
-};
-const OpFn OP_TABLE(fpu_d8_a32)[32] =
-{
-        opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32,
-        opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32,
-        opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32,
-        opFADD,      opFMUL,      opFCOM,      opFCOMP,      opFSUB,      opFSUBR,      opFDIV,      opFDIVR
-};
-
-const OpFn OP_TABLE(fpu_287_d9_a16)[256] =
-{
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,
-        opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,
-        opFNOP,       ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16, /*Invalid*/
-        opFCHS,       opFABS,       ILLEGAL_a16,  ILLEGAL_a16,  opFTST,       opFXAM,       ILLEGAL_a16,  ILLEGAL_a16,
-        opFLD1,       opFLDL2T,     opFLDL2E,     opFLDPI,      opFLDEG2,     opFLDLN2,     opFLDZ,       ILLEGAL_a16,
-        opF2XM1,      opFYL2X,      opFPTAN,      opFPATAN,     ILLEGAL_a16,  opFPREM1,     opFDECSTP,    opFINCSTP,
-        opFPREM,      opFYL2XP1,    opFSQRT,      opFSINCOS,    opFRNDINT,    opFSCALE,     opFSIN,       opFCOS
-};
-
-const OpFn OP_TABLE(fpu_287_d9_a32)[256] =
-{
-        opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,
-        opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,
-        opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, 
-        opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,
-        opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32,
-        opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,
-
-        opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,
-        opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,
-        opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, 
-        opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,
-        opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32,
-        opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,
-
-        opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,
-        opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,
-        opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, 
-        opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,
-        opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32,
-        opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,
-
-        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,
-        opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,
-        opFNOP,       ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32, /*Invalid*/
-        opFCHS,       opFABS,       ILLEGAL_a32,  ILLEGAL_a32,  opFTST,       opFXAM,       ILLEGAL_a32,  ILLEGAL_a32,
-        opFLD1,       opFLDL2T,     opFLDL2E,     opFLDPI,      opFLDEG2,     opFLDLN2,     opFLDZ,       ILLEGAL_a32,
-        opF2XM1,      opFYL2X,      opFPTAN,      opFPATAN,     ILLEGAL_a32,  opFPREM1,     opFDECSTP,    opFINCSTP,
-        opFPREM,      opFYL2XP1,    opFSQRT,      opFSINCOS,    opFRNDINT,    opFSCALE,     opFSIN,       opFCOS
-};
-
-const OpFn OP_TABLE(fpu_d9_a16)[256] =
-{
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,   opFLDs_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,   opFSTs_a16,
-        opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,  opFSTPs_a16,
-        opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, opFLDENV_a16, 
-        opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,  opFLDCW_a16,
-        opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16, opFSTENV_a16,
-        opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,  opFSTCW_a16,
-
-        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,
-        opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,
-        opFNOP,       ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,  /*Invalid*/
-        opFCHS,       opFABS,       ILLEGAL_a16,  ILLEGAL_a16,  opFTST,       opFXAM,       ILLEGAL_a16,  ILLEGAL_a16,
-        opFLD1,       opFLDL2T,     opFLDL2E,     opFLDPI,      opFLDEG2,     opFLDLN2,     opFLDZ,       ILLEGAL_a16,
-        opF2XM1,      opFYL2X,      opFPTAN,      opFPATAN,     ILLEGAL_a16,  opFPREM1,     opFDECSTP,    opFINCSTP,
-        opFPREM,      opFYL2XP1,    opFSQRT,      opFSINCOS,    opFRNDINT,    opFSCALE,     opFSIN,       opFCOS
-};
-
-const OpFn OP_TABLE(fpu_d9_a32)[256] =
-{
-        opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,
-        opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,
-        opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, 
-        opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,
-        opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32,
-        opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,
-
-        opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,
-        opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,
-        opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, 
-        opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,
-        opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32,
-        opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,
-
-        opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,   opFLDs_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,   opFSTs_a32,
-        opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,  opFSTPs_a32,
-        opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, opFLDENV_a32, 
-        opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,  opFLDCW_a32,
-        opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32, opFSTENV_a32,
-        opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,  opFSTCW_a32,
-
-        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,        opFLD,
-        opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,       opFXCH,
-        opFNOP,       ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,       opFSTP,  /*Invalid*/
-        opFCHS,       opFABS,       ILLEGAL_a32,  ILLEGAL_a32,  opFTST,       opFXAM,       ILLEGAL_a32,  ILLEGAL_a32,
-        opFLD1,       opFLDL2T,     opFLDL2E,     opFLDPI,      opFLDEG2,     opFLDLN2,     opFLDZ,       ILLEGAL_a32,
-        opF2XM1,      opFYL2X,      opFPTAN,      opFPATAN,     ILLEGAL_a32,  opFPREM1,     opFDECSTP,    opFINCSTP,
-        opFPREM,      opFYL2XP1,    opFSQRT,      opFSINCOS,    opFRNDINT,    opFSCALE,     opFSIN,       opFCOS
-};
-
-const OpFn OP_TABLE(fpu_287_da_a16)[256] =
-{
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_287_da_a32)[256] =
-{
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-const OpFn OP_TABLE(fpu_da_a16)[256] =
-{
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  opFUCOMPP,    ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_da_a32)[256] =
-{
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  opFUCOMPP,    ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)))
-const OpFn OP_TABLE(fpu_686_da_a16)[256] =
-{
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,  opFADDil_a16,
-        opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,  opFMULil_a16,
-        opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,  opFCOMil_a16,
-        opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16, opFCOMPil_a16,
-        opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,  opFSUBil_a16,
-        opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16, opFSUBRil_a16,
-        opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,  opFDIVil_a16,
-        opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16, opFDIVRil_a16,
-
-        opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,
-        opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,
-        opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,
-        opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  opFUCOMPP,    ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_686_da_a32)[256] =
-{
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,  opFADDil_a32,
-        opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,  opFMULil_a32,
-        opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,  opFCOMil_a32,
-        opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32, opFCOMPil_a32,
-        opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,  opFSUBil_a32,
-        opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32, opFSUBRil_a32,
-        opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,  opFDIVil_a32,
-        opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32, opFDIVRil_a32,
-
-        opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,      opFCMOVB,
-        opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,      opFCMOVE,
-        opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,     opFCMOVBE,
-        opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,      opFCMOVU,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  opFUCOMPP,    ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-#endif
-
-const OpFn OP_TABLE(fpu_287_db_a16)[256] =
-{
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFNOP,        opFNOP,        opFCLEX,       opFINIT,       opFNOP,        opFNOP,        ILLEGAL_a16,       ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_287_db_a32)[256] =
-{
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFNOP,        opFNOP,        opFCLEX,       opFINIT,       opFNOP,        opFNOP,        ILLEGAL_a32,       ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-const OpFn OP_TABLE(fpu_db_a16)[256] =
-{
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFNOP,        opFNOP,        opFCLEX,       opFINIT,       opFNOP,        opFNOP,        ILLEGAL_a16,       ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_db_a32)[256] =
-{
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFNOP,        opFNOP,        opFCLEX,       opFINIT,       opFNOP,        opFNOP,        ILLEGAL_a32,       ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)))
-const OpFn OP_TABLE(fpu_686_db_a16)[256] =
-{
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,  opFILDil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,  opFISTil_a16,
-        opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16, opFISTPil_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,    opFLDe_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,   opFSTPe_a16,
-
-        opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,
-        opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,
-        opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,
-        opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,
-        opFNOP,        opFNOP,        opFCLEX,       opFINIT,       opFNOP,        opFNOP,        ILLEGAL_a16,       ILLEGAL_a16,
-        opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,
-        opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_686_db_a32)[256] =
-{
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,  opFILDil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,  opFISTil_a32,
-        opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32, opFISTPil_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,    opFLDe_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,   opFSTPe_a32,
-
-        opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,     opFCMOVNB,
-        opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,     opFCMOVNE,
-        opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,    opFCMOVNBE,
-        opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,     opFCMOVNU,
-        opFNOP,        opFNOP,        opFCLEX,       opFINIT,       opFNOP,        opFNOP,        ILLEGAL_a32,       ILLEGAL_a32,
-        opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,      opFUCOMI,
-        opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,       opFCOMI,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-#endif
-
-const OpFn OP_TABLE(fpu_287_dc_a16)[32] =
-{
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDr,     opFMULr,     ILLEGAL_a16, ILLEGAL_a16,  opFSUBRr,    opFSUBr,      opFDIVRr,    opFDIVr
-};
-const OpFn OP_TABLE(fpu_287_dc_a32)[32] =
-{
-        opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
-        opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
-        opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
-        opFADDr,     opFMULr,     ILLEGAL_a32, ILLEGAL_a32,  opFSUBRr,    opFSUBr,      opFDIVRr,    opFDIVr
-};
-
-const OpFn OP_TABLE(fpu_dc_a16)[32] =
-{
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
-        opFADDr,     opFMULr,     opFCOM,      opFCOMP,      opFSUBRr,    opFSUBr,      opFDIVRr,    opFDIVr
-};
-const OpFn OP_TABLE(fpu_dc_a32)[32] =
-{
-        opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
-        opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
-        opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
-        opFADDr,     opFMULr,     opFCOM,      opFCOMP,      opFSUBRr,    opFSUBr,      opFDIVRr,    opFDIVr
-};
-
-const OpFn OP_TABLE(fpu_287_dd_a16)[256] =
-{
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_287_dd_a32)[256] =
-{
-        opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,
-        opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,
-        opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,
-        opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,
-
-        opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,
-        opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,
-        opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,
-        opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,
-
-        opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,
-        opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,
-        opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,
-        opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,
-
-        opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-const OpFn OP_TABLE(fpu_dd_a16)[256] =
-{
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,    opFLDd_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,    opFSTd_a16,
-        opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,   opFSTPd_a16,
-        opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,   opFSTOR_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,   opFSAVE_a16,
-        opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,   opFSTSW_a16,
-
-        opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,
-        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,
-        opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,
-        opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_dd_a32)[256] =
-{
-        opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,
-        opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,
-        opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,
-        opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,
-
-        opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,
-        opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,
-        opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,
-        opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,
-
-        opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,    opFLDd_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,    opFSTd_a32,
-        opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,   opFSTPd_a32,
-        opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,   opFSTOR_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,   opFSAVE_a32,
-        opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,   opFSTSW_a32,
-
-        opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,       opFFREE,
-        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,
-        opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,         opFST,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,       opFUCOM,
-        opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,      opFUCOMP,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-const OpFn OP_TABLE(fpu_287_de_a16)[256] =
-{
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,
-        opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  opFCOMPP,     ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,
-        opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,
-        opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,
-        opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,
-};
-
-const OpFn OP_TABLE(fpu_287_de_a32)[256] =
-{
-        opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,
-        opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,
-        opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,
-        opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32,
-        opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,
-        opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32,
-        opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,
-        opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32,
-
-        opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,
-        opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,
-        opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,
-        opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32,
-        opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,
-        opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32,
-        opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,
-        opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32,
-
-        opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,
-        opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,
-        opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,
-        opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32,
-        opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,
-        opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32,
-        opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,
-        opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32,
-
-        opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,
-        opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  opFCOMPP,     ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,
-        opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,
-        opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,
-        opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,
-};
-
-const OpFn OP_TABLE(fpu_de_a16)[256] =
-{
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,  opFADDiw_a16,
-        opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,  opFMULiw_a16,
-        opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,  opFCOMiw_a16,
-        opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16, opFCOMPiw_a16,
-        opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,  opFSUBiw_a16,
-        opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16, opFSUBRiw_a16,
-        opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,  opFDIViw_a16,
-        opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16, opFDIVRiw_a16,
-
-        opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,
-        opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,
-        opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,
-        ILLEGAL_a16,  opFCOMPP,     ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,
-        opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,
-        opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,
-        opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,
-};
-
-const OpFn OP_TABLE(fpu_de_a32)[256] =
-{
-        opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,
-        opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,
-        opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,
-        opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32,
-        opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,
-        opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32,
-        opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,
-        opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32,
-
-        opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,
-        opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,
-        opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,
-        opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32,
-        opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,
-        opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32,
-        opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,
-        opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32,
-
-        opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,  opFADDiw_a32,
-        opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,  opFMULiw_a32,
-        opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,  opFCOMiw_a32,
-        opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32, opFCOMPiw_a32,
-        opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,  opFSUBiw_a32,
-        opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32, opFSUBRiw_a32,
-        opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,  opFDIViw_a32,
-        opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32, opFDIVRiw_a32,
-
-        opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,       opFADDP,
-        opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,       opFMULP,
-        opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,       opFCOMP,
-        ILLEGAL_a32,  opFCOMPP,     ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,      opFSUBRP,
-        opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,       opFSUBP,
-        opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,      opFDIVRP,
-        opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,       opFDIVP,
-};
-
-const OpFn OP_TABLE(fpu_287_df_a16)[256] =
-{
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFSTSW_AX,   ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_287_df_a32)[256] =
-{
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFSTSW_AX,   ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-const OpFn OP_TABLE(fpu_df_a16)[256] =
-{
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTSW_AX,   ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_df_a32)[256] =
-{
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTSW_AX,   ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)))
-const OpFn OP_TABLE(fpu_686_df_a16)[256] =
-{
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,  opFILDiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,  opFISTiw_a16,
-        opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16, opFISTPiw_a16,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,  opFILDiq_a16,
-        FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,     FBSTP_a16,
-        FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,   FISTPiq_a16,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTSW_AX,   ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-        opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,
-        opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,
-        ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,  ILLEGAL_a16,
-};
-const OpFn OP_TABLE(fpu_686_df_a32)[256] =
-{
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,  opFILDiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,  opFISTiw_a32,
-        opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32, opFISTPiw_a32,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,  opFILDiq_a32,
-        FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,     FBSTP_a32,
-        FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,   FISTPiq_a32,
-
-        opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,      opFFREEP,
-        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,        opFXCH,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,        opFSTP,
-        opFSTSW_AX,   ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-        opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,     opFUCOMIP,
-        opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,      opFCOMIP,
-        ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,  ILLEGAL_a32,
-};
-#endif
-
-const OpFn OP_TABLE(nofpu_a16)[256] =
-{
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-        op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
-};
-const OpFn OP_TABLE(nofpu_a32)[256] =
-{
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-        op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
-};
-#endif
-
-#undef ILLEGAL
diff --git a/src/x87_bak/x87_ops_arith.h b/src/x87_bak/x87_ops_arith.h
deleted file mode 100644
index 133ecb689..000000000
--- a/src/x87_bak/x87_ops_arith.h
+++ /dev/null
@@ -1,427 +0,0 @@
-#define opFPU(name, optype, a_size, load_var, get, use_var)     \
-static int opFADD ## name ## _a ## a_size(uint32_t fetchdat)    \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        if ((cpu_state.npxc >> 10) & 3)                                   \
-                fesetround(rounding_modes[(cpu_state.npxc >> 10) & 3]);   \
-        ST(0) += use_var;                                       \
-        if ((cpu_state.npxc >> 10) & 3)                                   \
-                fesetround(FE_TONEAREST);                       \
-        FP_TAG();              \
-        CLOCK_CYCLES(8);                                        \
-        return 0;                                               \
-}                                                               \
-static int opFCOM ## name ## _a ## a_size(uint32_t fetchdat)    \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        cpu_state.npxs &= ~(C0|C2|C3);                                    \
-        cpu_state.npxs |= x87_compare(ST(0), (double)use_var);            \
-        CLOCK_CYCLES(4);                                        \
-        return 0;                                               \
-}                                                               \
-static int opFCOMP ## name ## _a ## a_size(uint32_t fetchdat)   \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        cpu_state.npxs &= ~(C0|C2|C3);                                    \
-        cpu_state.npxs |= x87_compare(ST(0), (double)use_var);            \
-        x87_pop();                                              \
-        CLOCK_CYCLES(4);                                        \
-        return 0;                                               \
-}                                                               \
-static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat)    \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        x87_div(ST(0), ST(0), use_var);                         \
-        FP_TAG();              \
-        CLOCK_CYCLES(73);                                       \
-        return 0;                                               \
-}                                                               \
-static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat)   \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        x87_div(ST(0), use_var, ST(0));                         \
-        FP_TAG();              \
-        CLOCK_CYCLES(73);                                       \
-        return 0;                                               \
-}                                                               \
-static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat)    \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        ST(0) *= use_var;                                       \
-        FP_TAG();                                \
-        CLOCK_CYCLES(11);                                       \
-        return 0;                                               \
-}                                                               \
-static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat)    \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        ST(0) -= use_var;                                       \
-        FP_TAG();              \
-        CLOCK_CYCLES(8);                                        \
-        return 0;                                               \
-}                                                               \
-static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat)   \
-{                                                               \
-        optype t;                                               \
-        FP_ENTER();                                             \
-        fetch_ea_ ## a_size(fetchdat);                          \
-		SEG_CHECK_READ(cpu_state.ea_seg);                       \
-        load_var = get(); if (cpu_state.abrt) return 1;                   \
-        ST(0) = use_var - ST(0);                                \
-        FP_TAG();              \
-        CLOCK_CYCLES(8);                                        \
-        return 0;                                               \
-}
-
-
-opFPU(s, x87_ts, 16, t.i, geteal, t.s)
-#ifndef FPU_8087
-opFPU(s, x87_ts, 32, t.i, geteal, t.s)
-#endif
-opFPU(d, x87_td, 16, t.i, geteaq, t.d)
-#ifndef FPU_8087
-opFPU(d, x87_td, 32, t.i, geteaq, t.d)
-#endif
-
-opFPU(iw, uint16_t, 16, t, geteaw, (double)(int16_t)t)
-#ifndef FPU_8087
-opFPU(iw, uint16_t, 32, t, geteaw, (double)(int16_t)t)
-#endif
-opFPU(il, uint32_t, 16, t, geteal, (double)(int32_t)t)
-#ifndef FPU_8087
-opFPU(il, uint32_t, 32, t, geteal, (double)(int32_t)t)
-#endif
-
-
-
-
-static int opFADD(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = ST(0) + ST(fetchdat & 7);
-        FP_TAG();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-static int opFADDr(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
-        FP_FTAG();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-static int opFADDP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
-        FP_FTAG();
-        x87_pop();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFCOM(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-        if (ST(0) == ST(fetchdat & 7))     cpu_state.npxs |= C3;
-        else if (ST(0) < ST(fetchdat & 7)) cpu_state.npxs |= C0;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFCOMP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-        cpu_state.npxs |= x87_compare(ST(0), ST(fetchdat & 7));
-        x87_pop();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFCOMPP(uint32_t fetchdat)
-{
-	uint64_t *p, *q;
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-	p = (uint64_t *)&ST(0);
-	q = (uint64_t *)&ST(1);
-        if ((*p == ((uint64_t)1 << 63) && *q == 0) && is386)
-                cpu_state.npxs |= C0; /*Nasty hack to fix 80387 detection*/
-        else
-                cpu_state.npxs |= x87_compare(ST(0), ST(1));
-
-        x87_pop();
-        x87_pop();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFUCOMPP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-        cpu_state.npxs |= x87_ucompare(ST(0), ST(1));
-        x87_pop();
-        x87_pop();
-        CLOCK_CYCLES(5);
-        return 0;
-}
-
-#ifdef FP_686
-static int opFCOMI(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        flags_rebuild();
-        cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
-        if (ST(0) == ST(fetchdat & 7))     cpu_state.flags |= Z_FLAG;
-        else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-static int opFCOMIP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        flags_rebuild();
-        cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
-        if (ST(0) == ST(fetchdat & 7))     cpu_state.flags |= Z_FLAG;
-        else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
-        x87_pop();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-#endif
-#endif
-
-static int opFDIV(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_div(ST(0), ST(0), ST(fetchdat & 7));
-        FP_TAG();
-        CLOCK_CYCLES(73);
-        return 0;
-}
-static int opFDIVr(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
-        FP_FTAG();
-        CLOCK_CYCLES(73);
-        return 0;
-}
-static int opFDIVP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
-        FP_FTAG();
-        x87_pop();
-        CLOCK_CYCLES(73);
-        return 0;
-}
-
-static int opFDIVR(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_div(ST(0), ST(fetchdat&7), ST(0));
-        FP_TAG();
-        CLOCK_CYCLES(73);
-        return 0;
-}
-static int opFDIVRr(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
-        FP_FTAG();
-        CLOCK_CYCLES(73);
-        return 0;
-}
-static int opFDIVRP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
-        FP_FTAG();
-        x87_pop();
-        CLOCK_CYCLES(73);
-        return 0;
-}
-
-static int opFMUL(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = ST(0) * ST(fetchdat & 7);
-        FP_TAG();
-        CLOCK_CYCLES(16);
-        return 0;
-}
-static int opFMULr(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
-        FP_FTAG();
-        CLOCK_CYCLES(16);
-        return 0;
-}
-static int opFMULP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
-        FP_FTAG();
-        x87_pop();
-        CLOCK_CYCLES(16);
-        return 0;
-}
-
-static int opFSUB(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = ST(0) - ST(fetchdat & 7);
-        FP_TAG();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-static int opFSUBr(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
-        FP_FTAG();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-static int opFSUBP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
-        FP_FTAG();
-        x87_pop();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFSUBR(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = ST(fetchdat & 7) - ST(0);
-        FP_TAG();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-static int opFSUBRr(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
-        FP_FTAG();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-static int opFSUBRP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
-        FP_FTAG();
-        x87_pop();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-#ifndef FPU_8087
-static int opFUCOM(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-        cpu_state.npxs |= x87_ucompare(ST(0), ST(fetchdat & 7));
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFUCOMP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-        cpu_state.npxs |= x87_ucompare(ST(0), ST(fetchdat & 7));
-        x87_pop();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-#ifdef FP_686
-static int opFUCOMI(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        flags_rebuild();
-        cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
-        if (ST(0) == ST(fetchdat & 7))     cpu_state.flags |= Z_FLAG;
-        else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-static int opFUCOMIP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        flags_rebuild();
-        cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
-        if (ST(0) == ST(fetchdat & 7))     cpu_state.flags |= Z_FLAG;
-        else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
-        x87_pop();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-#endif
-#endif
diff --git a/src/x87_bak/x87_ops_loadstore.h b/src/x87_bak/x87_ops_loadstore.h
deleted file mode 100644
index 925fe87bd..000000000
--- a/src/x87_bak/x87_ops_loadstore.h
+++ /dev/null
@@ -1,492 +0,0 @@
-/*
- * 86Box	A hypervisor and IBM PC system emulator that specializes in
- *		running old operating systems and software designed for IBM
- *		PC systems and compatibles from 1981 through fairly recent
- *		system designs based on the PCI bus.
- *
- *		This file is part of the 86Box distribution.
- *
- *		x87 FPU instructions core.
- *
- *
- *
- * Author:	Sarah Walker, <http://pcem-emulator.co.uk/>
- *		Miran Grca, <mgrca8@gmail.com>
- *		Copyright 2008-2019 Sarah Walker.
- *		Copyright 2016-2019 Miran Grca.
- */
-
-static int opFILDiw_a16(uint32_t fetchdat)
-{
-        int16_t temp;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        temp = geteaw(); if (cpu_state.abrt) return 1;
-        x87_push((double)temp);
-        CLOCK_CYCLES(13);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFILDiw_a32(uint32_t fetchdat)
-{
-        int16_t temp;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        temp = geteaw(); if (cpu_state.abrt) return 1;
-        x87_push((double)temp);
-        CLOCK_CYCLES(13);
-        return 0;
-}
-#endif
-
-static int opFISTiw_a16(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteaw((int16_t)temp64);
-        CLOCK_CYCLES(29);
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFISTiw_a32(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteaw((int16_t)temp64);
-        CLOCK_CYCLES(29);
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFISTPiw_a16(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteaw((int16_t)temp64); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(29);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFISTPiw_a32(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteaw((int16_t)temp64); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(29);
-        return 0;
-}
-#endif
-
-static int opFILDiq_a16(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        temp64 = geteaq(); if (cpu_state.abrt) return 1;
-        x87_push((double)temp64);
-        FP_LSQ();
-        FP_LSTAG();
-
-        CLOCK_CYCLES(10);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFILDiq_a32(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        temp64 = geteaq(); if (cpu_state.abrt) return 1;
-        x87_push((double)temp64);
-        FP_LSQ();
-        FP_LSTAG();
-
-        CLOCK_CYCLES(10);
-        return 0;
-}
-#endif
-
-static int FBSTP_a16(uint32_t fetchdat)
-{
-        double tempd;
-        int c;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        tempd = ST(0);
-        if (tempd < 0.0) 
-                tempd = -tempd;
-        for (c = 0; c < 9; c++)
-        {
-                uint8_t tempc = (uint8_t)floor(fmod(tempd, 10.0));
-                tempd -= floor(fmod(tempd, 10.0));
-                tempd /= 10.0;
-                tempc |= ((uint8_t)floor(fmod(tempd, 10.0))) << 4;
-                tempd -= floor(fmod(tempd, 10.0));
-                tempd /= 10.0;
-                writememb(easeg, cpu_state.eaaddr + c, tempc);
-        }
-        tempc = (uint8_t)floor(fmod(tempd, 10.0));
-        if (ST(0) < 0.0) tempc |= 0x80;
-        writememb(easeg, cpu_state.eaaddr + 9, tempc); if (cpu_state.abrt) return 1;
-        x87_pop();
-        return 0;
-}
-#ifndef FPU_8087
-static int FBSTP_a32(uint32_t fetchdat)
-{
-        double tempd;
-        int c;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        tempd = ST(0);
-        if (tempd < 0.0) 
-                tempd = -tempd;
-        for (c = 0; c < 9; c++)
-        {
-                uint8_t tempc = (uint8_t)floor(fmod(tempd, 10.0));
-                tempd -= floor(fmod(tempd, 10.0));
-                tempd /= 10.0;
-                tempc |= ((uint8_t)floor(fmod(tempd, 10.0))) << 4;
-                tempd -= floor(fmod(tempd, 10.0));
-                tempd /= 10.0;
-                writememb(easeg, cpu_state.eaaddr + c, tempc);
-        }
-        tempc = (uint8_t)floor(fmod(tempd, 10.0));
-        if (ST(0) < 0.0) tempc |= 0x80;
-        writememb(easeg, cpu_state.eaaddr + 9, tempc); if (cpu_state.abrt) return 1;
-        x87_pop();
-        return 0;
-}
-#endif
-
-static int FISTPiq_a16(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
-                FP_LSRETQ()
-        else
-                temp64 = x87_fround(ST(0));
-        seteaq(temp64); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(29);
-        return 0;
-}
-#ifndef FPU_8087
-static int FISTPiq_a32(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
-                FP_LSRETQ()
-        else
-                temp64 = x87_fround(ST(0));
-        seteaq(temp64); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(29);
-        return 0;
-}
-#endif
-
-static int opFILDil_a16(uint32_t fetchdat)
-{
-        int32_t templ;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        templ = geteal(); if (cpu_state.abrt) return 1;
-        x87_push((double)templ);
-        CLOCK_CYCLES(9);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFILDil_a32(uint32_t fetchdat)
-{
-        int32_t templ;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        templ = geteal(); if (cpu_state.abrt) return 1;
-        x87_push((double)templ);
-        CLOCK_CYCLES(9);
-        return 0;
-}
-#endif
-
-static int opFISTil_a16(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteal((int32_t)temp64);
-        CLOCK_CYCLES(28);
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFISTil_a32(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteal((int32_t)temp64);
-        CLOCK_CYCLES(28);
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFISTPil_a16(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteal((int32_t)temp64); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(28);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFISTPil_a32(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp64 = x87_fround(ST(0));
-        seteal((int32_t)temp64); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(28);
-        return 0;
-}
-#endif
-
-static int opFLDe_a16(uint32_t fetchdat)
-{
-        double t;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_READ(cpu_state.ea_seg);		
-        t=x87_ld80(); if (cpu_state.abrt) return 1;
-        x87_push(t);
-        CLOCK_CYCLES(6);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFLDe_a32(uint32_t fetchdat)
-{
-        double t;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_READ(cpu_state.ea_seg);
-        t=x87_ld80(); if (cpu_state.abrt) return 1;
-        x87_push(t);
-        CLOCK_CYCLES(6);
-        return 0;
-}
-#endif
-
-static int opFSTPe_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        x87_st80(ST(0)); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(6);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFSTPe_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        x87_st80(ST(0)); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(6);
-        return 0;
-}
-#endif
-
-static int opFLDd_a16(uint32_t fetchdat)
-{
-        x87_td t;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_READ(cpu_state.ea_seg);
-        t.i = geteaq(); if (cpu_state.abrt) return 1;
-        x87_push(t.d);
-        CLOCK_CYCLES(3);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFLDd_a32(uint32_t fetchdat)
-{
-        x87_td t;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        t.i = geteaq(); if (cpu_state.abrt) return 1;
-        x87_push(t.d);
-        CLOCK_CYCLES(3);
-        return 0;
-}
-#endif
-
-static int opFSTd_a16(uint32_t fetchdat)
-{
-        x87_td t;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        t.d = ST(0);
-        seteaq(t.i);
-        CLOCK_CYCLES(8);
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSTd_a32(uint32_t fetchdat)
-{
-        x87_td t;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        t.d = ST(0);
-        seteaq(t.i);
-        CLOCK_CYCLES(8);
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFSTPd_a16(uint32_t fetchdat)
-{
-        x87_td t;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        t.d = ST(0);
-        seteaq(t.i); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFSTPd_a32(uint32_t fetchdat)
-{
-        x87_td t;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        t.d = ST(0);
-        seteaq(t.i); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(8);
-        return 0;
-}
-#endif
-
-static int opFLDs_a16(uint32_t fetchdat)
-{
-        x87_ts ts;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-		SEG_CHECK_READ(cpu_state.ea_seg);
-        ts.i = geteal(); if (cpu_state.abrt) return 1;
-        x87_push((double)ts.s);
-        CLOCK_CYCLES(3);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFLDs_a32(uint32_t fetchdat)
-{
-        x87_ts ts;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_READ(cpu_state.ea_seg);
-        ts.i = geteal(); if (cpu_state.abrt) return 1;
-        x87_push((double)ts.s);
-        CLOCK_CYCLES(3);
-        return 0;
-}
-#endif
-
-static int opFSTs_a16(uint32_t fetchdat)
-{
-        x87_ts ts;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        ts.s = (float)ST(0);
-        seteal(ts.i);
-        CLOCK_CYCLES(7);
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSTs_a32(uint32_t fetchdat)
-{
-        x87_ts ts;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        ts.s = (float)ST(0);
-        seteal(ts.i);
-        CLOCK_CYCLES(7);
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFSTPs_a16(uint32_t fetchdat)
-{
-        x87_ts ts;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        ts.s = (float)ST(0);
-        seteal(ts.i); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(7);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFSTPs_a32(uint32_t fetchdat)
-{
-        x87_ts ts;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        ts.s = (float)ST(0);
-        seteal(ts.i); if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(7);
-        return 0;
-}
-#endif
diff --git a/src/x87_bak/x87_ops_misc.h b/src/x87_bak/x87_ops_misc.h
deleted file mode 100644
index 406c6c86d..000000000
--- a/src/x87_bak/x87_ops_misc.h
+++ /dev/null
@@ -1,877 +0,0 @@
-#ifdef FPU_8087
-static int opFI(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-	cpu_state.npxc &= ~0x80;
-	if (rmdat == 0xe1)
-		cpu_state.npxc |= 0x80;
-	wait(3, 0);
-        return 0;
-}
-#else
-static int opFSTSW_AX(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        AX = cpu_state.npxs;
-        CLOCK_CYCLES(3);
-        return 0;
-}
-#endif
-
-
-static int opFNOP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFCLEX(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= 0xff00;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFINIT(uint32_t fetchdat)
-{
-	uint64_t *p;
-        FP_ENTER();
-        cpu_state.pc++;
-#ifdef FPU_8087
-        cpu_state.npxc = 0x3FF;
-#else
-        cpu_state.npxc = 0x37F;
-#endif
-        FP_RNPXC();
-        cpu_state.npxs = 0;
-	p = (uint64_t *)cpu_state.tag;
-        *p = FP_DTAG;
-        cpu_state.TOP = 0;
-	cpu_state.ismmx = 0;
-        CLOCK_CYCLES(17);
-	CPU_BLOCK_END();
-        return 0;
-}
-
-
-static int opFFREE(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = FP_EMPTY;
-        CLOCK_CYCLES(3);
-        return 0;
-}
-
-static int opFFREEP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = FP_EMPTY; if (cpu_state.abrt) return 1;
-        x87_pop();
-        CLOCK_CYCLES(3);
-        return 0;
-}
-
-static int opFST(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(0);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = cpu_state.tag[cpu_state.TOP & 7];
-        CLOCK_CYCLES(3);
-        return 0;
-}
-
-static int opFSTP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(fetchdat & 7) = ST(0);
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = cpu_state.tag[cpu_state.TOP & 7];
-        x87_pop();
-        CLOCK_CYCLES(3);
-        return 0;
-}
-
-
-
-
-static int FSTOR()
-{
-	uint64_t *p;
-        FP_ENTER();
-        switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
-        {
-                case 0x000: /*16-bit real mode*/
-                case 0x001: /*16-bit protected mode*/
-                cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
-                FP_NNPXC();
-                cpu_state.npxs = readmemw(easeg, cpu_state.eaaddr+2);
-                x87_settag(readmemw(easeg, cpu_state.eaaddr+4));
-                cpu_state.TOP = (cpu_state.npxs >> 11) & 7;
-                cpu_state.eaaddr += 14;
-                break;
-                case 0x100: /*32-bit real mode*/
-                case 0x101: /*32-bit protected mode*/
-                cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
-                FP_NNPXC();
-                cpu_state.npxs = readmemw(easeg, cpu_state.eaaddr+4);
-                x87_settag(readmemw(easeg, cpu_state.eaaddr+8));
-                cpu_state.TOP = (cpu_state.npxs >> 11) & 7;
-                cpu_state.eaaddr += 28;
-                break;
-        }
-        x87_ld_frstor(0); cpu_state.eaaddr += 10;
-        x87_ld_frstor(1); cpu_state.eaaddr += 10;
-        x87_ld_frstor(2); cpu_state.eaaddr += 10;
-        x87_ld_frstor(3); cpu_state.eaaddr += 10;
-        x87_ld_frstor(4); cpu_state.eaaddr += 10;
-        x87_ld_frstor(5); cpu_state.eaaddr += 10;
-        x87_ld_frstor(6); cpu_state.eaaddr += 10;
-        x87_ld_frstor(7);
-        
-        cpu_state.ismmx = 0;
-        /*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
-          something like this is needed*/
-	p = (uint64_t *)cpu_state.tag;
-        if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
-            cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
-            !cpu_state.TOP && (*p == FP_CTAG))
-        cpu_state.ismmx = 1;
-
-        CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
-        return cpu_state.abrt;
-}
-static int opFSTOR_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_READ(cpu_state.ea_seg);
-        FSTOR();
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSTOR_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_READ(cpu_state.ea_seg);
-        FSTOR();
-        return cpu_state.abrt;
-}
-#endif
-
-static int FSAVE()
-{
-	uint64_t *p;
-
-        FP_ENTER();
-        cpu_state.npxs = (cpu_state.npxs & ~(7 << 11)) | (FP_TOP(cpu_state.TOP) << 11);
-
-        switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
-        {
-                case 0x000: /*16-bit real mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
-                writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
-                cpu_state.eaaddr+=14;
-                if (cpu_state.ismmx)
-                {
-                        x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[7]);
-                }
-                else
-                {
-                        x87_st_fsave(0); cpu_state.eaaddr+=10;
-                        x87_st_fsave(1); cpu_state.eaaddr+=10;
-                        x87_st_fsave(2); cpu_state.eaaddr+=10;
-                        x87_st_fsave(3); cpu_state.eaaddr+=10;
-                        x87_st_fsave(4); cpu_state.eaaddr+=10;
-                        x87_st_fsave(5); cpu_state.eaaddr+=10;
-                        x87_st_fsave(6); cpu_state.eaaddr+=10;
-                        x87_st_fsave(7);
-                }
-                break;
-                case 0x001: /*16-bit protected mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
-                writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+8,x87_pc_seg);
-                writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
-                writememw(easeg,cpu_state.eaaddr+12,x87_op_seg);
-                cpu_state.eaaddr+=14;
-                if (cpu_state.ismmx)
-                {
-                        x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[7]);
-                }
-                else
-                {
-                        x87_st_fsave(0); cpu_state.eaaddr+=10;
-                        x87_st_fsave(1); cpu_state.eaaddr+=10;
-                        x87_st_fsave(2); cpu_state.eaaddr+=10;
-                        x87_st_fsave(3); cpu_state.eaaddr+=10;
-                        x87_st_fsave(4); cpu_state.eaaddr+=10;
-                        x87_st_fsave(5); cpu_state.eaaddr+=10;
-                        x87_st_fsave(6); cpu_state.eaaddr+=10;
-                        x87_st_fsave(7);
-                }
-                break;
-                case 0x100: /*32-bit real mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+4,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
-                writememw(easeg,cpu_state.eaaddr+12,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+20,x87_op_off);
-                writememl(easeg,cpu_state.eaaddr+24,(x87_op_off>>16)<<12);
-                cpu_state.eaaddr+=28;
-                if (cpu_state.ismmx)
-                {
-                        x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[7]);
-                }
-                else
-                {
-                        x87_st_fsave(0); cpu_state.eaaddr+=10;
-                        x87_st_fsave(1); cpu_state.eaaddr+=10;
-                        x87_st_fsave(2); cpu_state.eaaddr+=10;
-                        x87_st_fsave(3); cpu_state.eaaddr+=10;
-                        x87_st_fsave(4); cpu_state.eaaddr+=10;
-                        x87_st_fsave(5); cpu_state.eaaddr+=10;
-                        x87_st_fsave(6); cpu_state.eaaddr+=10;
-                        x87_st_fsave(7);
-                }
-                break;
-                case 0x101: /*32-bit protected mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+4,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
-                writememl(easeg,cpu_state.eaaddr+12,x87_pc_off);
-                writememl(easeg,cpu_state.eaaddr+16,x87_pc_seg);
-                writememl(easeg,cpu_state.eaaddr+20,x87_op_off);
-                writememl(easeg,cpu_state.eaaddr+24,x87_op_seg);
-                cpu_state.eaaddr+=28;
-                if (cpu_state.ismmx)
-                {
-                        x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
-                        x87_stmmx(cpu_state.MM[7]);
-                }
-                else
-                {
-                        x87_st_fsave(0); cpu_state.eaaddr+=10;
-                        x87_st_fsave(1); cpu_state.eaaddr+=10;
-                        x87_st_fsave(2); cpu_state.eaaddr+=10;
-                        x87_st_fsave(3); cpu_state.eaaddr+=10;
-                        x87_st_fsave(4); cpu_state.eaaddr+=10;
-                        x87_st_fsave(5); cpu_state.eaaddr+=10;
-                        x87_st_fsave(6); cpu_state.eaaddr+=10;
-                        x87_st_fsave(7);
-                }
-                break;
-        }
-
-        cpu_state.npxc = 0x37F;
-        FP_RNPXC();
-        cpu_state.npxs = 0;
-	p = (uint64_t *)cpu_state.tag;
-	*p = FP_DTAG;
-        cpu_state.TOP = 0;
-        cpu_state.ismmx = 0;
-
-        CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
-        return cpu_state.abrt;
-}
-static int opFSAVE_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        FSAVE();
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSAVE_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        FSAVE();
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFSTSW_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        seteaw((cpu_state.npxs & 0xC7FF) | (FP_TOP(cpu_state.TOP) << 11));
-        CLOCK_CYCLES(3);
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSTSW_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        seteaw((cpu_state.npxs & 0xC7FF) | (FP_TOP(cpu_state.TOP) << 11));
-        CLOCK_CYCLES(3);
-        return cpu_state.abrt;
-}
-#endif
-
-
-static int opFLD(uint32_t fetchdat)
-{
-        int old_tag;
-        uint64_t old_i64;
-        
-        FP_ENTER();
-        cpu_state.pc++;
-        old_tag = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];
-        old_i64 = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q;
-        x87_push(ST(fetchdat&7));
-        cpu_state.tag[FP_TOP(cpu_state.TOP)] = old_tag;
-        cpu_state.MM[FP_TOP(cpu_state.TOP)].q = old_i64;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFXCH(uint32_t fetchdat)
-{
-        double td;
-        uint8_t old_tag;
-        uint64_t old_i64;
-        FP_ENTER();
-        cpu_state.pc++;
-        td = ST(0);
-        ST(0) = ST(fetchdat&7);
-        ST(fetchdat&7) = td;
-        old_tag = cpu_state.tag[FP_TOP(cpu_state.TOP)];
-        cpu_state.tag[FP_TOP(cpu_state.TOP)] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];
-        cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = old_tag;
-        old_i64 = cpu_state.MM[FP_TOP(cpu_state.TOP)].q;
-        cpu_state.MM[FP_TOP(cpu_state.TOP)].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q;
-        cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q = old_i64;
-        
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFCHS(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = -ST(0);
-        FP_TAG();
-        CLOCK_CYCLES(6);
-        return 0;
-}
-
-static int opFABS(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = fabs(ST(0));
-        FP_TAG();
-        CLOCK_CYCLES(3);
-        return 0;
-}
-
-static int opFTST(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C2|C3);
-        if (ST(0) == 0.0)     cpu_state.npxs |= C3;
-        else if (ST(0) < 0.0) cpu_state.npxs |= C0;
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFXAM(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        cpu_state.npxs &= ~(C0|C1|C2|C3);
-        if (cpu_state.tag[cpu_state.TOP&7] == FP_EMPTY)   cpu_state.npxs |= (C0|C3);
-        else if (ST(0) == 0.0) cpu_state.npxs |= C3;
-        else                   cpu_state.npxs |= C2;
-        if (ST(0) < 0.0)       cpu_state.npxs |= C1;
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFLD1(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push(1.0);
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFLDL2T(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push(3.3219280948873623);
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFLDL2E(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push(1.4426950408889634);
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFLDPI(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push(3.141592653589793);
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFLDEG2(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push(0.3010299956639812);
-        CLOCK_CYCLES(8);
-        return 0;
-}
-
-static int opFLDLN2(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push_u64(0x3fe62e42fefa39f0ull);
-        CLOCK_CYCLES(8);
-        return 0;
-}
- 
-static int opFLDZ(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        x87_push(0.0);
-        FP_ZTAG();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opF2XM1(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = pow(2.0, ST(0)) - 1.0;
-        FP_TAG();
-        CLOCK_CYCLES(200);
-        return 0;
-}
-
-static int opFYL2X(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(1) = ST(1) * (log(ST(0)) / log(2.0));
-        FP_NTAG();
-        x87_pop();
-        CLOCK_CYCLES(250);
-        return 0;
-}
-
-static int opFYL2XP1(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(1) = ST(1) * (log(ST(0)+1.0) / log(2.0));
-        FP_NTAG();
-        x87_pop();
-        CLOCK_CYCLES(250);
-        return 0;
-}
-
-static int opFPTAN(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = tan(ST(0));
-        FP_TAG();
-        x87_push(1.0);
-        cpu_state.npxs &= ~C2;
-        CLOCK_CYCLES(235);
-        return 0;
-}
-
-static int opFPATAN(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(1) = atan2(ST(1), ST(0));
-        FP_NTAG();
-        x87_pop();
-        CLOCK_CYCLES(250);
-        return 0;
-}
-
-static int opFDECSTP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        FP_DECTOP();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFINCSTP(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        FP_INCTOP();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-
-static int opFPREM(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        cpu_state.pc++;
-        temp64 = (int64_t)(ST(0) / ST(1));
-        ST(0) = ST(0) - (ST(1) * (double)temp64);
-        FP_TAG();
-        cpu_state.npxs &= ~(C0|C1|C2|C3);
-        if (temp64 & 4) cpu_state.npxs|=C0;
-        if (temp64 & 2) cpu_state.npxs|=C3;
-        if (temp64 & 1) cpu_state.npxs|=C1;
-        CLOCK_CYCLES(100);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFPREM1(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        cpu_state.pc++;
-        temp64 = (int64_t)(ST(0) / ST(1));
-        ST(0) = ST(0) - (ST(1) * (double)temp64);
-        FP_TAG();
-        cpu_state.npxs &= ~(C0|C1|C2|C3);
-        if (temp64 & 4) cpu_state.npxs|=C0;
-        if (temp64 & 2) cpu_state.npxs|=C3;
-        if (temp64 & 1) cpu_state.npxs|=C1;
-        CLOCK_CYCLES(100);
-        return 0;
-}
-#endif
-
-static int opFSQRT(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = sqrt(ST(0));
-        FP_TAG();
-        CLOCK_CYCLES(83);
-        return 0;
-}
-
-#ifndef FPU_8087
-static int opFSINCOS(uint32_t fetchdat)
-{
-        double td;
-        FP_ENTER();
-        cpu_state.pc++;
-        td = ST(0);
-        ST(0) = sin(td);
-        FP_TAG();
-        x87_push(cos(td));
-        cpu_state.npxs &= ~C2;
-        CLOCK_CYCLES(330);
-        return 0;
-}
-#endif
-
-static int opFRNDINT(uint32_t fetchdat)
-{
-	double rounded;
-        FP_ENTER();
-        cpu_state.pc++;
-	rounded = (double) x87_fround(ST(0));
-#ifndef PCEM_CODE
-	if (rounded > ST(0))
-		cpu_state.npxs |= C1;
-	else
-		cpu_state.npxs &= ~C1;
-#endif
-        ST(0) = rounded;
-        FP_TAG();
-        CLOCK_CYCLES(21);
-        return 0;
-}
-
-static int opFSCALE(uint32_t fetchdat)
-{
-        int64_t temp64;
-        FP_ENTER();
-        cpu_state.pc++;
-        temp64 = (int64_t)ST(1);
-        ST(0) = ST(0) * pow(2.0, (double)temp64);
-        FP_TAG();
-        CLOCK_CYCLES(30);
-        return 0;
-}
-
-#ifndef FPU_8087
-static int opFSIN(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = sin(ST(0));
-        FP_TAG();
-        cpu_state.npxs &= ~C2;
-        CLOCK_CYCLES(300);
-        return 0;
-}
-
-static int opFCOS(uint32_t fetchdat)
-{
-        FP_ENTER();
-        cpu_state.pc++;
-        ST(0) = cos(ST(0));
-        FP_TAG();
-        cpu_state.npxs &= ~C2;
-        CLOCK_CYCLES(300);
-        return 0;
-}
-#endif
-
-
-static int FLDENV()
-{
-        FP_ENTER();
-        switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
-        {
-                case 0x000: /*16-bit real mode*/
-                case 0x001: /*16-bit protected mode*/
-                cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
-                FP_NNPXC();
-                cpu_state.npxs = readmemw(easeg, cpu_state.eaaddr+2);
-                x87_settag(readmemw(easeg, cpu_state.eaaddr+4));
-                cpu_state.TOP = (cpu_state.npxs >> 11) & 7;
-                break;
-                case 0x100: /*32-bit real mode*/
-                case 0x101: /*32-bit protected mode*/
-                cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
-                FP_NNPXC();
-                cpu_state.npxs = readmemw(easeg, cpu_state.eaaddr+4);
-                x87_settag(readmemw(easeg, cpu_state.eaaddr+8));
-                cpu_state.TOP = (cpu_state.npxs >> 11) & 7;
-                break;
-        }
-        CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
-        return cpu_state.abrt;
-}
-
-static int opFLDENV_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-        SEG_CHECK_READ(cpu_state.ea_seg);
-        FLDENV();
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFLDENV_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-        SEG_CHECK_READ(cpu_state.ea_seg);
-        FLDENV();
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFLDCW_a16(uint32_t fetchdat)
-{
-        uint16_t tempw;
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-        SEG_CHECK_READ(cpu_state.ea_seg);
-        tempw = geteaw();
-        if (cpu_state.abrt) return 1;
-        cpu_state.npxc = tempw;
-        FP_NNPXC();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-#ifndef FPU_8087
-static int opFLDCW_a32(uint32_t fetchdat)
-{
-        uint16_t tempw;
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-        SEG_CHECK_READ(cpu_state.ea_seg);
-        tempw = geteaw();
-        if (cpu_state.abrt) return 1;
-        cpu_state.npxc = tempw;
-        FP_NNPXC();
-        CLOCK_CYCLES(4);
-        return 0;
-}
-#endif
-
-static int FSTENV()
-{
-        FP_ENTER();
-        switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
-        {
-                case 0x000: /*16-bit real mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
-                writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
-                break;
-                case 0x001: /*16-bit protected mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
-                writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+8,x87_pc_seg);
-                writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
-                writememw(easeg,cpu_state.eaaddr+12,x87_op_seg);
-                break;
-                case 0x100: /*32-bit real mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+4,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
-                writememw(easeg,cpu_state.eaaddr+12,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+20,x87_op_off);
-                writememl(easeg,cpu_state.eaaddr+24,(x87_op_off>>16)<<12);
-                break;
-                case 0x101: /*32-bit protected mode*/
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+4,cpu_state.npxs);
-                writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
-                writememl(easeg,cpu_state.eaaddr+12,x87_pc_off);
-                writememl(easeg,cpu_state.eaaddr+16,x87_pc_seg);
-                writememl(easeg,cpu_state.eaaddr+20,x87_op_off);
-                writememl(easeg,cpu_state.eaaddr+24,x87_op_seg);
-                break;
-        }
-        CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
-        return cpu_state.abrt;
-}
-
-static int opFSTENV_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-        SEG_CHECK_WRITE(cpu_state.ea_seg);
-        FSTENV();
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSTENV_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-        SEG_CHECK_WRITE(cpu_state.ea_seg);
-        FSTENV();
-        return cpu_state.abrt;
-}
-#endif
-
-static int opFSTCW_a16(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_16(fetchdat);
-        SEG_CHECK_WRITE(cpu_state.ea_seg);
-        seteaw(cpu_state.npxc);
-        CLOCK_CYCLES(3);
-        return cpu_state.abrt;
-}
-#ifndef FPU_8087
-static int opFSTCW_a32(uint32_t fetchdat)
-{
-        FP_ENTER();
-        fetch_ea_32(fetchdat);
-        SEG_CHECK_WRITE(cpu_state.ea_seg);
-        seteaw(cpu_state.npxc);
-        CLOCK_CYCLES(3);
-        return cpu_state.abrt;
-}
-#endif
-
-#ifndef FPU_8087
-#ifdef FP_686
-#define opFCMOV(condition)                                                              \
-        static int opFCMOV ## condition(uint32_t fetchdat)                              \
-        {                                                                               \
-                FP_ENTER();                                                             \
-                cpu_state.pc++;                                                         \
-                if (cond_ ## condition)                                                 \
-                {                                                                       \
-                        cpu_state.tag[FP_TOP(cpu_state.TOP)] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];                           \
-                        cpu_state.MM[FP_TOP(cpu_state.TOP)].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q;                     \
-                        ST(0) = ST(fetchdat & 7);                                       \
-                }                                                                       \
-                CLOCK_CYCLES(4);                                                        \
-                return 0;                                                               \
-        }
-
-#define cond_U   ( PF_SET())
-#define cond_NU  (!PF_SET())
-
-opFCMOV(B)
-opFCMOV(E)
-opFCMOV(BE)
-opFCMOV(U)
-opFCMOV(NB)
-opFCMOV(NE)
-opFCMOV(NBE)
-opFCMOV(NU)
-#endif
-#endif

From 9a287c31e5a6e99b615e8828044daf8bdce8f284 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Mon, 20 Apr 2020 14:52:07 +0200
Subject: [PATCH 07/43] Removed network.rar.

---
 src/network.rar | Bin 204438 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 src/network.rar

diff --git a/src/network.rar b/src/network.rar
deleted file mode 100644
index 363c66769d7f4811f61e70b7541bb22fe308816f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 204438
zcmZs?LzE~=v}K#NZQHhO+qUzhZQHhO+qP}n{`b|d8lxK3itcX3j5YTPB||4dEO0=8
z5>|l>7(h@60B}ISxt3^u0P7yFa%v!8=zUm_a5@6*(MukGU;ubK(|>OEPS*5B&TfVd
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O?LzORr-^d|2>2hUPd!fn


From 2de9a3f37aa9f8f2e18a36c653e43a340da0fb5c Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Mon, 20 Apr 2020 19:02:13 +0200
Subject: [PATCH 08/43] Set Link State from VBox to 86Box implemented on the
 PCnet card (any other nics don't have it and will simply return NULL). The
 PCnet-based Racal nic now has its own OID to make its drivers happy
 (according to VBox).

---
 src/include/86box/network.h |   4 +-
 src/network/net_3c503.c     |   2 +-
 src/network/net_ne2000.c    |   2 +-
 src/network/net_pcap.c      |   2 +-
 src/network/net_pcnet.c     | 258 +++++++++++++++++++++++++++---------
 src/network/net_slirp.c     |   2 +-
 src/network/net_wd8003.c    |   2 +-
 src/network/network.c       |   3 +-
 8 files changed, 203 insertions(+), 72 deletions(-)

diff --git a/src/include/86box/network.h b/src/include/86box/network.h
index 39dbe49bc..9a0916382 100644
--- a/src/include/86box/network.h
+++ b/src/include/86box/network.h
@@ -66,6 +66,7 @@ enum {
 
 typedef void (*NETRXCB)(void *, uint8_t *, int);
 typedef int (*NETWAITCB)(void *);
+typedef int (*NETSETLINKSTATE)(void *);
 
 
 typedef struct {
@@ -76,6 +77,7 @@ typedef struct {
     int			(*poll)(void *);
     NETRXCB		rx;
     NETWAITCB		wait;
+    NETSETLINKSTATE	set_link_state;
 } netcard_t;
 
 typedef struct {
@@ -101,7 +103,7 @@ extern void	network_busy(uint8_t set);
 extern void	network_end(void);
 
 extern void	network_init(void);
-extern void	network_attach(void *, uint8_t *, NETRXCB, NETWAITCB);
+extern void	network_attach(void *, uint8_t *, NETRXCB, NETWAITCB, NETSETLINKSTATE);
 extern void	network_close(void);
 extern void	network_reset(void);
 extern int	network_available(void);
diff --git a/src/network/net_3c503.c b/src/network/net_3c503.c
index b983ca3a3..c75c07353 100644
--- a/src/network/net_3c503.c
+++ b/src/network/net_3c503.c
@@ -617,7 +617,7 @@ threec503_nic_init(const device_t *info)
     dev->regs.gacfr = 0x09;	/* Start with RAM mapping enabled. */
 
     /* Attach ourselves to the network module. */
-    network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL);
+    network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL, NULL);
 
     return(dev);
 }
diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c
index 6649db62c..5158673c1 100644
--- a/src/network/net_ne2000.c
+++ b/src/network/net_ne2000.c
@@ -1469,7 +1469,7 @@ nic_init(const device_t *info)
 	nic_reset(dev);
 
     /* Attach ourselves to the network module. */
-    network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL);
+    network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL, NULL);
 
     nelog(1, "%s: %s attached IO=0x%X IRQ=%d\n", dev->name,
 	dev->is_pci?"PCI":"ISA", dev->base_address, dev->base_irq);
diff --git a/src/network/net_pcap.c b/src/network/net_pcap.c
index 21a43190b..beba36ca9 100644
--- a/src/network/net_pcap.c
+++ b/src/network/net_pcap.c
@@ -184,7 +184,7 @@ poll_thread(void *arg)
 	if (pcap == NULL) break;
 
 	/* Wait for the next packet to arrive. */
-	if (network_get_wait() || (poll_card->wait && poll_card->wait(poll_card->priv)))
+	if (network_get_wait() || (poll_card->set_link_state && poll_card->set_link_state(poll_card->priv)) || (poll_card->wait && poll_card->wait(poll_card->priv)))
 		data = NULL;
 	else
 		data = (uint8_t *)f_pcap_next((void *)pcap, &h);
diff --git a/src/network/net_pcnet.c b/src/network/net_pcnet.c
index f7cf2a5dc..777858624 100644
--- a/src/network/net_pcnet.c
+++ b/src/network/net_pcnet.c
@@ -64,10 +64,12 @@ typedef struct RTNETETHERHDR
 #define MII_MAX_REG                     32
 #define CSR_MAX_REG                     128
 
+/** Maximum number of times we report a link down to the guest (failure to send frame) */
+#define PCNET_MAX_LINKDOWN_REPORTED     3
+
 /** Maximum frame size we handle */
 #define MAX_FRAME                       1536
 
-
 /** @name Bus configuration registers
  * @{ */
 #define BCR_MSRDA       0
@@ -230,9 +232,16 @@ typedef struct {
     /** Error counter for bad receive descriptors. */
     uint32_t uCntBadRMD;
     uint16_t u16CSR0LastSeenByGuest;
-    uint64_t last_poll;
+    /** If set the link is currently up. */
+    int fLinkUp;
+    /** If set the link is temporarily down because of a saved state load. */
+    int fLinkTempDown;
+    /** Number of times we've reported the link down. */
+    uint32_t cLinkDownReported;
+    /** MS to wait before we enable the link. */
+    uint32_t cMsLinkUpDelay;
     uint8_t maclocal[6]; /* configured MAC (local) address */
-    pc_timer_t poll_timer, timer_soft_int;
+    pc_timer_t timer_soft_int, timer_restore;
 } nic_t;
 
 /** @todo All structs: big endian? */
@@ -403,6 +412,17 @@ pcnet_do_irq(nic_t *dev, int issue)
 	}	
 }
 
+/**
+ * Checks if the link is up.
+ * @returns true if the link is up.
+ * @returns false if the link is down.
+ */
+static __inline int
+pcnetIsLinkUp(nic_t *dev)
+{
+    return !dev->fLinkTempDown && dev->fLinkUp;
+}
+
 /**
  * Load transmit message descriptor
  * Make sure we read the own flag first.
@@ -1214,6 +1234,12 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size)
         buf = buf1;
         size = 60;
     }
+    
+    /*
+     * Drop packets if the cable is not connected
+     */
+    if (!pcnetIsLinkUp(dev))
+	return;    
 
     pcnetlog(1, "%s: pcnetReceiveNoSync: RX %x:%x:%x:%x:%x:%x > %x:%x:%x:%x:%x:%x len %d\n", dev->name,
 	buf[6], buf[7], buf[8], buf[9], buf[10], buf[11],
@@ -1408,6 +1434,28 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size)
     pcnetUpdateIrq(dev);
 }
 
+/**
+ * Fails a TMD with a link down error.
+ */
+static void
+pcnetXmitFailTMDLinkDown(nic_t *dev, TMD *pTmd)
+{
+    /* make carrier error - hope this is correct. */
+    dev->cLinkDownReported++;
+    pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
+    dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR */
+}
+
+/**
+ * Fails a TMD with a generic error.
+ */
+static void
+pcnetXmitFailTMDGeneric(nic_t *dev, TMD *pTmd)
+{
+    /* make carrier error - hope this is correct. */
+    pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
+    dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR */
+}
 
 /**
  * Actually try transmit frames.
@@ -1435,6 +1483,12 @@ pcnetAsyncTransmit(nic_t *dev)
         if (!pcnetTdtePoll(dev, &tmd))
             break;
 
+        /* Don't continue sending packets when the link is down. */
+        if ((!pcnetIsLinkUp(dev)
+                        &&  dev->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED)
+            )
+            break;
+
         pcnetlog(3, "%s: TMDLOAD %#010x\n", dev->name, PHYSADDR(dev, CSR_CXDA(dev)));
 		
         int fLoopback = CSR_LOOP(dev);
@@ -1446,52 +1500,59 @@ pcnetAsyncTransmit(nic_t *dev)
             const int cb = 4096 - tmd.tmd1.bcnt;
             pcnetlog("%s: pcnetAsyncTransmit: stp&enp: cb=%d xmtrc=%#x\n", dev->name, cb, CSR_XMTRC(dev));			
 
-	    /* From the manual: ``A zero length buffer is acceptable as
-	    * long as it is not the last buffer in a chain (STP = 0 and
-	    * ENP = 1).'' That means that the first buffer might have a
-	    * zero length if it is not the last one in the chain. */
-	    if (cb <= MAX_FRAME) {
-		dev->xmit_pos = cb;
-		DMAPageRead(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb);
+	    if ((pcnetIsLinkUp(dev) || fLoopback)) {
+	    
+		/* From the manual: ``A zero length buffer is acceptable as
+		 * long as it is not the last buffer in a chain (STP = 0 and
+		 * ENP = 1).'' That means that the first buffer might have a
+		 * zero length if it is not the last one in the chain. */
+		if (cb <= MAX_FRAME) {
+		    dev->xmit_pos = cb;
+		    DMAPageRead(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb);
 
-		if (fLoopback) {
-		    if (HOST_IS_OWNER(CSR_CRST(dev)))
-			pcnetRdtePoll(dev);
+		    if (fLoopback) {
+			if (HOST_IS_OWNER(CSR_CRST(dev)))
+			    pcnetRdtePoll(dev);
 
-		    pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos);		    
+			pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos);		    
+		    } else {
+			pcnetlog(3, "%s: pcnetAsyncTransmit: transmit loopbuf stp and enp, xmit pos = %d\n", dev->name, dev->xmit_pos);
+			network_tx(dev->abLoopBuf, dev->xmit_pos);		        
+		    }
+		} else if (cb == 4096) {
+		    /* The Windows NT4 pcnet driver sometimes marks the first
+		     * unused descriptor as owned by us. Ignore that (by
+		     * passing it back). Do not update the ring counter in this
+		     * case (otherwise that driver becomes even more confused,
+		     * which causes transmit to stall for about 10 seconds).
+		     * This is just a workaround, not a final solution. 
+		     */
+		    /* r=frank: IMHO this is the correct implementation. The
+		     * manual says: ``If the OWN bit is set and the buffer
+		     * length is 0, the OWN bit will be cleared. In the C-LANCE
+		     * the buffer length of 0 is interpreted as a 4096-byte
+		     * buffer.'' 
+		     */
+		    /* r=michaln: Perhaps not quite right. The C-LANCE (Am79C90)
+		     * datasheet explains that the old LANCE (Am7990) ignored
+		     * the top four bits next to BCNT and a count of 0 was
+		     * interpreted as 4096. In the C-LANCE, that is still the
+		     * case if the top bits are all ones. If all 16 bits are
+		     * zero, the C-LANCE interprets it as zero-length transmit
+		     * buffer. It's not entirely clear if the later models
+		     * (PCnet-ISA, PCnet-PCI) behave like the C-LANCE or not.
+		     * It is possible that the actual behavior of the C-LANCE
+		     * and later hardware is that the buffer lengths are *16-bit*
+		     * two's complement numbers between 0 and 4096. AMD's drivers
+		     * in fact generally treat the length as a 16-bit quantity. */
+		    pcnetlog(1, "%s: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", dev->name);
+		    pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)));
+		    break;
 		} else {
-		    pcnetlog(3, "%s: pcnetAsyncTransmit: transmit loopbuf stp and enp, xmit pos = %d\n", dev->name, dev->xmit_pos);
-		    network_tx(dev->abLoopBuf, dev->xmit_pos);		        
+		    pcnetXmitFailTMDGeneric(dev, &tmd);
 		}
-	    } else if (cb == 4096) {
-		/* The Windows NT4 pcnet driver sometimes marks the first
-		 * unused descriptor as owned by us. Ignore that (by
-		 * passing it back). Do not update the ring counter in this
-		 * case (otherwise that driver becomes even more confused,
-		 * which causes transmit to stall for about 10 seconds).
-		 * This is just a workaround, not a final solution. 
-		 */
-		/* r=frank: IMHO this is the correct implementation. The
-		 * manual says: ``If the OWN bit is set and the buffer
-		 * length is 0, the OWN bit will be cleared. In the C-LANCE
-		 * the buffer length of 0 is interpreted as a 4096-byte
-		 * buffer.'' 
-		 */
-		/* r=michaln: Perhaps not quite right. The C-LANCE (Am79C90)
-		 * datasheet explains that the old LANCE (Am7990) ignored
-		 * the top four bits next to BCNT and a count of 0 was
-		 * interpreted as 4096. In the C-LANCE, that is still the
-		 * case if the top bits are all ones. If all 16 bits are
-		 * zero, the C-LANCE interprets it as zero-length transmit
-		 * buffer. It's not entirely clear if the later models
-		 * (PCnet-ISA, PCnet-PCI) behave like the C-LANCE or not.
-		 * It is possible that the actual behavior of the C-LANCE
-		 * and later hardware is that the buffer lengths are *16-bit*
-		 * two's complement numbers between 0 and 4096. AMD's drivers
-		 * in fact generally treat the length as a 16-bit quantity. */
-		pcnetlog(1, "%s: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", dev->name);
-		pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)));
-		break;
+	    } else {
+		pcnetXmitFailTMDLinkDown(dev, &tmd);
 	    }
 
             /* Write back the TMD and pass it to the host (clear own bit). */
@@ -2021,8 +2082,9 @@ pcnet_mii_readw(nic_t *dev, uint16_t miiaddr)
 		| 0x0008 /* Able to do auto-negotiation. */
 		| 0x0004 /* Link up. */
 		| 0x0001; /* Extended Capability, i.e. registers 4+ valid. */
-	    if (isolate) {
+	    if (!dev->fLinkUp || dev->fLinkTempDown || isolate) {
 		val &= ~(0x0020 | 0x0004);
+		dev->cLinkDownReported++;
 	    }
 	    if (!autoneg) {
 		/* Auto-negotiation disabled. */
@@ -2056,7 +2118,7 @@ pcnet_mii_readw(nic_t *dev, uint16_t miiaddr)
 
 	case 5:
 	    /* Link partner ability register. */
-	    if (!isolate) {
+	    if (dev->fLinkUp && !dev->fLinkTempDown && !isolate) {
 	        val = 0x8000 /* Next page bit. */
 		    | 0x4000 /* Link partner acked us. */
 		    | 0x0400 /* Can do flow control. */
@@ -2064,23 +2126,25 @@ pcnet_mii_readw(nic_t *dev, uint16_t miiaddr)
 		    | 0x0001; /* Use CSMA selector. */
 	    } else {
 	        val = 0;
+		dev->cLinkDownReported++;
 	    }
 	    break;
 
 	case 6:
 	    /* Auto negotiation expansion register. */
-	    if (!isolate) {
+	    if (dev->fLinkUp && !dev->fLinkTempDown && !isolate) {
 		val = 0x0008 /* Link partner supports npage. */
 		    | 0x0004 /* Enable npage words. */
 		    | 0x0001; /* Can do N-way auto-negotiation. */
 	    } else {
 		val = 0;
+		dev->cLinkDownReported++;
 	    }
 	    break;
 	    
 	case 18:
 	    /* Diagnostic Register (FreeBSD pcn/ac101 driver reads this). */
-	    if (!isolate) {
+	    if (dev->fLinkUp && !dev->fLinkTempDown && !isolate) {
 		val = 0x1000 /* Receive PLL locked. */
 		    | 0x0200; /* Signal detected. */
 		
@@ -2095,6 +2159,7 @@ pcnet_mii_readw(nic_t *dev, uint16_t miiaddr)
 		}
 	    } else {
 		val = 0;
+		dev->cLinkDownReported++;
 	    }
 	    break;
 	    
@@ -2117,6 +2182,11 @@ pcnet_bcr_readw(nic_t *dev, uint16_t rap)
 	case BCR_LED2:
 	case BCR_LED3:
 		val = dev->aBCR[rap] & ~0x8000;
+		if (dev->fLinkTempDown || !dev->fLinkUp) {
+		    if (rap == 4)
+			dev->cLinkDownReported++;
+		    val &= ~0x40;
+		}
 		val |= (val & 0x017f & dev->u32Lnkst) ? 0x8000 : 0;
 		break;
 		
@@ -2623,6 +2693,27 @@ pcnet_pci_read(int func, int addr, void *p)
     return(0);
 }
 
+/**
+ * Takes down the link temporarily if it's current status is up.
+ *
+ * This is used during restore and when replumbing the network link.
+ *
+ * The temporary link outage is supposed to indicate to the OS that all network
+ * connections have been lost and that it for instance is appropriate to
+ * renegotiate any DHCP lease.
+ *
+ * @param  pThis        The PCnet shared instance data.
+ */
+static void 
+pcnetTempLinkDown(nic_t *dev)
+{
+    if (dev->fLinkUp) {
+        dev->fLinkTempDown = 1;
+        dev->cLinkDownReported = 0;
+        dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR (this is probably wrong) */
+        timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC);
+    }
+}
 
 /**
  * Check if the device/driver can receive data now.
@@ -2664,6 +2755,34 @@ pcnetWaitReceiveAvail(void *priv)
     return dev->fMaybeOutOfSpace;
 }
 
+static int
+pcnetSetLinkState(void *priv)
+{
+    nic_t *dev = (nic_t *) priv;
+    int fLinkUp;
+    
+    if (dev->fLinkTempDown) {
+	pcnetTempLinkDown(dev);
+	return 1;
+    }
+    
+    fLinkUp = (dev->fLinkUp && !dev->fLinkTempDown);
+    if (dev->fLinkUp != fLinkUp) {
+	dev->fLinkUp = fLinkUp;
+	if (fLinkUp) {
+	    dev->fLinkTempDown = 1;
+	    dev->cLinkDownReported = 0;
+            dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR (this is probably wrong) */
+	    timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC);
+	} else {
+	    dev->cLinkDownReported = 0;
+            dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR (this is probably wrong) */
+	}
+    }
+    
+    return 0;
+}
+
 static void
 pcnetTimerSoftInt(void *priv)
 {
@@ -2675,16 +2794,18 @@ pcnetTimerSoftInt(void *priv)
 }
 
 static void
-pcnetTimerCallback(void *priv)
+pcnetTimerRestore(void *priv)
 {
     nic_t *dev = (nic_t *) priv;
     
-#ifdef ENABLE_PCNET_LOG
-    pcnetlog(3, "Timer Callback to RX\n");
-#endif
-    pcnetPollRxTx(dev);
-    
-    timer_disable(&dev->poll_timer);
+    if (dev->cLinkDownReported <= PCNET_MAX_LINKDOWN_REPORTED) {
+	timer_advance_u64(&dev->timer_restore, 1500000 * TIMER_USEC);
+    } else {
+	dev->fLinkTempDown = 0;
+	if (dev->fLinkUp) {
+	    dev->aCSR[0] &= ~(0x8000 | 0x2000); /* ERR | CERR - probably not 100% correct either... */
+	}
+    }
 }
 
 static void *
@@ -2717,10 +2838,19 @@ pcnet_init(const device_t *info)
 	pcnet_mem_init(dev, 0x0fffff00);
 	pcnet_mem_disable(dev);
     }
-
-    dev->maclocal[0] = 0x00;  /* 00:0C:87 (AMD OID) */
-    dev->maclocal[1] = 0x0C;
-    dev->maclocal[2] = 0x87;
+    
+    dev->fLinkUp = 1;
+    dev->cMsLinkUpDelay = 5000;
+    
+    if (dev->board == DEV_AM79C960_EB) {
+	    dev->maclocal[0] = 0x02;  /* 02:07:01 (Racal OID) */
+	    dev->maclocal[1] = 0x07;
+	    dev->maclocal[2] = 0x01;
+    } else {
+	    dev->maclocal[0] = 0x00;  /* 00:0C:87 (AMD OID) */
+	    dev->maclocal[1] = 0x0C;
+	    dev->maclocal[2] = 0x87;
+    }
 
     /* See if we have a local MAC address configured. */
     mac = device_get_config_mac("mac", -1);
@@ -2816,12 +2946,12 @@ pcnet_init(const device_t *info)
     pcnetHardReset(dev);
 
     /* Attach ourselves to the network module. */
-    network_attach(dev, dev->aPROM, pcnetReceiveNoSync, pcnetWaitReceiveAvail);
+    network_attach(dev, dev->aPROM, pcnetReceiveNoSync, pcnetWaitReceiveAvail, pcnetSetLinkState);
 
     if (dev->board == DEV_AM79C973)
         timer_add(&dev->timer_soft_int, pcnetTimerSoftInt, dev, 0);
-    
-    timer_add(&dev->poll_timer, pcnetTimerCallback, dev, 0);
+
+    timer_add(&dev->timer_restore, pcnetTimerRestore, dev, 0);
 
     return(dev);
 }
@@ -2838,8 +2968,6 @@ pcnet_close(void *priv)
     network_close();
     
     if (dev) {
-	timer_disable(&dev->poll_timer);
-	
 	free(dev);
 	dev = NULL;
     
diff --git a/src/network/net_slirp.c b/src/network/net_slirp.c
index 3adc8d6f7..c1af9fc65 100644
--- a/src/network/net_slirp.c
+++ b/src/network/net_slirp.c
@@ -147,7 +147,7 @@ poll_thread(void *arg)
 	/* Wait for the next packet to arrive. */
 	data_valid = 0;
 
-	if ((!network_get_wait() && !(poll_card->wait && poll_card->wait(poll_card->priv))) && (QueuePeek(slirpq) != 0)) {
+	if ((!network_get_wait() && !(poll_card->set_link_state && poll_card->set_link_state(poll_card->priv)) && !(poll_card->wait && poll_card->wait(poll_card->priv))) && (QueuePeek(slirpq) != 0)) {
 		/* Grab a packet from the queue. */
 		// ui_sb_update_icon(SB_NETWORK, 1);
 
diff --git a/src/network/net_wd8003.c b/src/network/net_wd8003.c
index 7f0b5aeeb..953212a0b 100644
--- a/src/network/net_wd8003.c
+++ b/src/network/net_wd8003.c
@@ -771,7 +771,7 @@ wd_init(const device_t *info)
     mem_mapping_disable(&dev->ram_mapping);		
 
     /* Attach ourselves to the network module. */
-    network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL);
+    network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL, NULL);
 
     if (!(dev->board_chip & WE_ID_BUS_MCA)) {
 	wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name,
diff --git a/src/network/network.c b/src/network/network.c
index db69227f3..4273cf6fb 100644
--- a/src/network/network.c
+++ b/src/network/network.c
@@ -223,7 +223,7 @@ network_init(void)
  * modules.
  */
 void
-network_attach(void *dev, uint8_t *mac, NETRXCB rx, NETWAITCB wait)
+network_attach(void *dev, uint8_t *mac, NETRXCB rx, NETWAITCB wait, NETSETLINKSTATE set_link_state)
 {
     if (network_card == 0) return;
 
@@ -231,6 +231,7 @@ network_attach(void *dev, uint8_t *mac, NETRXCB rx, NETWAITCB wait)
     net_cards[network_card].priv = dev;
     net_cards[network_card].rx = rx;
     net_cards[network_card].wait = wait;
+    net_cards[network_card].set_link_state = set_link_state;
     network_mac = mac;
 
     network_set_wait(0);

From 64b56db0d75ca3c86ac8c0129a3c452ae18b7b66 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Tue, 21 Apr 2020 00:27:22 +0200
Subject: [PATCH 09/43] Fixed the implementation of XADD - fixes Windows 2000
 Service Pack 4, and hopefully also Linux.

---
 src/cpu_common/x86_ops_atomic.h | 85 +++++++++++++++++++--------------
 1 file changed, 49 insertions(+), 36 deletions(-)

diff --git a/src/cpu_common/x86_ops_atomic.h b/src/cpu_common/x86_ops_atomic.h
index 54725d316..13b672e31 100644
--- a/src/cpu_common/x86_ops_atomic.h
+++ b/src/cpu_common/x86_ops_atomic.h
@@ -132,83 +132,96 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
         return 0;
 }
 
+/* dest = eab, src = r8 */
 static int opXADD_b_a16(uint32_t fetchdat)
 {
-        uint8_t temp, temp2;
+        uint8_t temp;
+	uint8_t src, dest;
         fetch_ea_16(fetchdat);
         SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp = geteab();                        if (cpu_state.abrt) return 1;
-	temp2 = getr8(cpu_reg);
-        setr8(cpu_reg, temp);
-        seteab(temp + temp2);              if (cpu_state.abrt) return 1;
-        setadd8(temp, temp2);
+	src = getr8(cpu_reg);
+        dest = geteab();		if (cpu_state.abrt) return 1;
+	temp = src + dest;
+        seteab(temp);			if (cpu_state.abrt) return 1;
+        setadd8(src, dest);
+        setr8(cpu_reg, dest);
         CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
         return 0;
 }
 static int opXADD_b_a32(uint32_t fetchdat)
 {
-        uint8_t temp, temp2;
+        uint8_t temp;
+	uint8_t src, dest;
         fetch_ea_32(fetchdat);
         SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp = geteab();                        if (cpu_state.abrt) return 1;
-	temp2 = getr8(cpu_reg);
-        setr8(cpu_reg, temp);
-        seteab(temp + temp2);              if (cpu_state.abrt) return 1;
-        setadd8(temp, temp2);
+	src = getr8(cpu_reg);
+        dest = geteab();		if (cpu_state.abrt) return 1;
+	temp = src + dest;
+        seteab(temp);			if (cpu_state.abrt) return 1;
+        setadd8(src, dest);
+        setr8(cpu_reg, dest);
         CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
         return 0;
 }
 
 static int opXADD_w_a16(uint32_t fetchdat)
 {
-        uint16_t temp, temp2;
+        uint16_t temp;
+	uint16_t src, dest;
         fetch_ea_16(fetchdat);
         SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp = geteaw();                        if (cpu_state.abrt) return 1;
-	temp2 = cpu_state.regs[cpu_reg].w;
-        cpu_state.regs[cpu_reg].w = temp;
-        seteaw(temp + temp2);   if (cpu_state.abrt) return 1;
-        setadd16(temp, temp2);
+	src = cpu_state.regs[cpu_reg].w;
+        dest = geteaw();		if (cpu_state.abrt) return 1;
+	temp = src + dest;
+        seteaw(temp);			if (cpu_state.abrt) return 1;
+        setadd16(src, dest);
+        cpu_state.regs[cpu_reg].w = dest;
         CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
         return 0;
 }
 static int opXADD_w_a32(uint32_t fetchdat)
 {
-        uint16_t temp, temp2;
+        uint16_t temp;
+	uint16_t src, dest;
         fetch_ea_32(fetchdat);
         SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp = geteaw();                        if (cpu_state.abrt) return 1;
-	temp2 = cpu_state.regs[cpu_reg].w;
-        cpu_state.regs[cpu_reg].w = temp;
-        seteaw(temp + temp2);   if (cpu_state.abrt) return 1;
-        setadd16(temp, temp2);
+	src = cpu_state.regs[cpu_reg].w;
+        dest = geteaw();		if (cpu_state.abrt) return 1;
+	temp = src + dest;
+        seteaw(temp);			if (cpu_state.abrt) return 1;
+        setadd16(src, dest);
+        cpu_state.regs[cpu_reg].w = dest;
         CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
         return 0;
 }
 
 static int opXADD_l_a16(uint32_t fetchdat)
 {
-        uint32_t temp, temp2;
+        uint32_t temp;
+	uint32_t src, dest;
         fetch_ea_16(fetchdat);
         SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp = geteal();                        if (cpu_state.abrt) return 1;
-	temp2 = cpu_state.regs[cpu_reg].l;
-        cpu_state.regs[cpu_reg].l = temp;
-        seteal(temp + temp2);   if (cpu_state.abrt) return 1;
-        setadd32(temp, temp2);
+	src = cpu_state.regs[cpu_reg].l;
+        dest = geteal();		if (cpu_state.abrt) return 1;
+	temp = src + dest;
+        seteal(temp);			if (cpu_state.abrt) return 1;
+        setadd32(src, dest);
+        cpu_state.regs[cpu_reg].l = dest;
         CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
         return 0;
 }
 static int opXADD_l_a32(uint32_t fetchdat)
 {
-        uint32_t temp, temp2;
+        uint32_t temp;
+	uint32_t src, dest;
         fetch_ea_32(fetchdat);
         SEG_CHECK_WRITE(cpu_state.ea_seg);
-        temp = geteal();                        if (cpu_state.abrt) return 1;
-	temp2 = cpu_state.regs[cpu_reg].l;
-        cpu_state.regs[cpu_reg].l = temp;
-        seteal(temp + temp2);   if (cpu_state.abrt) return 1;
-        setadd32(temp, temp2);
+	src = cpu_state.regs[cpu_reg].l;
+        dest = geteal();		if (cpu_state.abrt) return 1;
+	temp = src + dest;
+        seteal(temp);			if (cpu_state.abrt) return 1;
+        setadd32(src, dest);
+        cpu_state.regs[cpu_reg].l = dest;
         CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
         return 0;
 }

From 022d1f818e4035034968c80199c8ece8c6ed5110 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Tue, 21 Apr 2020 04:34:22 +0200
Subject: [PATCH 10/43] Fixed PAE enough to get Lubuntu 17.10 to Kernel Panic
 (apparent lack of IDE driver) instead of triple fault reset.

---
 src/mem.c | 44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/mem.c b/src/mem.c
index 25e84f593..be1589b3d 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -355,14 +355,14 @@ mmutranslatereal_normal(uint32_t addr, int rw)
 static uint64_t
 mmutranslatereal_pae(uint32_t addr, int rw)
 {
-    uint64_t temp,temp2,temp3;
+    uint64_t temp,temp2,temp3,temp4;
     uint64_t addr2,addr3,addr4;
 
     if (cpu_state.abrt)
 	return 0xffffffffffffffffULL;
 
     addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
-    temp = temp2 = rammap64(addr2);
+    temp = temp2 = rammap64(addr2) & 0x000000ffffffffffULL;
     if (!(temp & 1)) {
 	cr2 = addr;
 	temp &= 1;
@@ -373,8 +373,8 @@ mmutranslatereal_pae(uint32_t addr, int rw)
 	return 0xffffffffffffffffULL;
     }
 
-    addr3 = (temp & ~0xfff) + ((addr >> 18) & 0xff8);
-    temp = rammap64(addr3);
+    addr3 = (temp & ~0xfffULL) + ((addr >> 18) & 0xff8);
+    temp = temp4 = rammap64(addr3) & 0x000000ffffffffffULL;
     temp3 = temp & temp2;
     if (!(temp & 1)) {
 	cr2 = addr;
@@ -387,8 +387,8 @@ mmutranslatereal_pae(uint32_t addr, int rw)
     }
 
     if (temp & 0x80) {
-	/*4MB page*/
-	if (((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) {
+	/*2MB page*/
+	if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) {
 		cr2 = addr;
 		temp &= 1;
 		if (CPL == 3)
@@ -403,12 +403,12 @@ mmutranslatereal_pae(uint32_t addr, int rw)
 	mmu_perm = temp & 4;
 	rammap64(addr3) |= 0x20;
 
-	return ((temp & ~0x1fffff) + (addr & 0x1fffff)) & 0x0000000fffffffffULL;
+	return ((temp & ~0x1fffffULL) + (addr & 0x1fffffULL)) & 0x000000ffffffffffULL;
     }
 
-    addr4 = (temp & ~0xfff) + ((addr >> 9) & 0xff8);
-    temp = rammap64(addr4);
-    temp3 = temp & temp3;
+    addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8);
+    temp = rammap64(addr4) & 0x000000ffffffffffULL;
+    temp3 = temp & temp4;
     if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) {
 	cr2 = addr;
 	temp &= 1;
@@ -423,7 +423,7 @@ mmutranslatereal_pae(uint32_t addr, int rw)
     rammap64(addr3) |= 0x20;
     rammap64(addr4) |= (rw? 0x60 : 0x20);
 
-    return ((temp & ~0xfff) + ((uint64_t) (addr & 0xfff))) & 0x0000000fffffffffULL;
+    return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL;
 }
 
 
@@ -481,20 +481,20 @@ mmutranslate_noabrt_normal(uint32_t addr, int rw)
 static uint64_t
 mmutranslate_noabrt_pae(uint32_t addr, int rw)
 {
-    uint32_t temp,temp2,temp3;
-    uint32_t addr2,addr3,addr4;
+    uint64_t temp,temp2,temp3,temp4;
+    uint64_t addr2,addr3,addr4;
 
     if (cpu_state.abrt) 
 	return 0xffffffffffffffffULL;
 
     addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
-    temp = temp2 = rammap64(addr2);
+    temp = temp2 = rammap64(addr2) & 0x000000ffffffffffULL;
 
     if (! (temp & 1))
 	return 0xffffffffffffffffULL;
 
-    addr3 = (temp & ~0xfff) + ((addr >> 18) & 0xff8);
-    temp = rammap64(addr3);
+    addr3 = (temp & ~0xfffULL) + ((addr >> 18) & 0xff8);
+    temp = temp4 = rammap64(addr3) & 0x000000ffffffffffULL;
     temp3 = temp & temp2;
 
     if (! (temp & 1))
@@ -502,20 +502,20 @@ mmutranslate_noabrt_pae(uint32_t addr, int rw)
 
     if (temp & 0x80) {
 	/*2MB page*/
-	if (((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
+	if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
 		return 0xffffffffffffffffULL;
 
-	return ((temp & ~0x1fffff) + (addr & 0x1fffff)) & 0x0000000fffffffffULL;
+	return ((temp & ~0x1fffffULL) + (addr & 0x1fffff)) & 0x000000ffffffffffULL;
     }
 
-    addr4 = (temp & ~0xfff) + ((addr >> 9) & 0xff8);
-    temp = rammap64(addr4);
-    temp3 = temp & temp3;
+    addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8);
+    temp = rammap64(addr4) & 0x000000ffffffffffULL;;
+    temp3 = temp & temp4;
 
     if (!(temp&1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
 	return 0xffffffffffffffffULL;
 
-    return ((temp & ~0xfff) + ((uint64_t) (addr & 0xfff))) & 0x0000000fffffffffULL;
+    return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL;
 }
 
 

From 70862a3c25279f9e4183154e0ad99bde406c944d Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Tue, 21 Apr 2020 19:24:00 +0200
Subject: [PATCH 11/43] Added dmmy support for MSR 0x179 for Debian 10.

---
 src/cpu_common/cpu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/cpu_common/cpu.c b/src/cpu_common/cpu.c
index bff70e6b1..c77e02ca4 100644
--- a/src/cpu_common/cpu.c
+++ b/src/cpu_common/cpu.c
@@ -2779,14 +2779,20 @@ void cpu_RDMSR()
 			if (machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_PENTIUMPRO)  goto i686_invalid_rdmsr;
 			EAX &= 0xFFFF0000;
 			EAX |= cs_msr;
+			EDX = 0x00000000;
 			break;
 			case 0x175:
 			if (machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_PENTIUMPRO)  goto i686_invalid_rdmsr;
 			EAX = esp_msr;
+			EDX = 0x00000000;
 			break;
 			case 0x176:
 			if (machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_PENTIUMPRO)  goto i686_invalid_rdmsr;
 			EAX = eip_msr;
+			EDX = 0x00000000;
+			break;
+			case 0x179:
+			EAX = EDX = 0x00000000;
 			break;
 			case 0x186:
                         EAX = ecx186_msr & 0xffffffff;
@@ -3212,6 +3218,8 @@ void cpu_WRMSR()
 			if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUMPRO)  goto i686_invalid_wrmsr;
 			eip_msr = EAX;
 			break;
+			case 0x179:
+			break;
 			case 0x186:
 			ecx186_msr = EAX | ((uint64_t)EDX << 32);
 			break;			

From d499d63fd1d317665507748cbd58432823dcf2ea Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Tue, 21 Apr 2020 23:52:10 +0200
Subject: [PATCH 12/43] Implemented the Pentium Pro+ HINT_NOP instructions and
 slightly reworked the Deschutes+ FXSAVE/FXRSTOR instructions.

---
 src/cpu_common/386_ops.h      |  24 +-
 src/cpu_common/x86_ops_i686.h | 573 ++++++++++++----------------------
 2 files changed, 218 insertions(+), 379 deletions(-)

diff --git a/src/cpu_common/386_ops.h b/src/cpu_common/386_ops.h
index f6467dea1..674186337 100644
--- a/src/cpu_common/386_ops.h
+++ b/src/cpu_common/386_ops.h
@@ -1177,7 +1177,7 @@ const OpFn OP_TABLE(pentiumpro_0f)[1024] =
         /*16-bit data, 16-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1199,7 +1199,7 @@ const OpFn OP_TABLE(pentiumpro_0f)[1024] =
         /*32-bit data, 16-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1221,7 +1221,7 @@ const OpFn OP_TABLE(pentiumpro_0f)[1024] =
         /*16-bit data, 32-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1243,7 +1243,7 @@ const OpFn OP_TABLE(pentiumpro_0f)[1024] =
         /*32-bit data, 32-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1268,7 +1268,7 @@ const OpFn OP_TABLE(pentium2_0f)[1024] =
         /*16-bit data, 16-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1290,7 +1290,7 @@ const OpFn OP_TABLE(pentium2_0f)[1024] =
         /*32-bit data, 16-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1312,7 +1312,7 @@ const OpFn OP_TABLE(pentium2_0f)[1024] =
         /*16-bit data, 32-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1334,7 +1334,7 @@ const OpFn OP_TABLE(pentium2_0f)[1024] =
         /*32-bit data, 32-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1359,7 +1359,7 @@ const OpFn OP_TABLE(pentium2d_0f)[1024] =
         /*16-bit data, 16-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1381,7 +1381,7 @@ const OpFn OP_TABLE(pentium2d_0f)[1024] =
         /*32-bit data, 16-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16, opHINT_NOP_a16,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1403,7 +1403,7 @@ const OpFn OP_TABLE(pentium2d_0f)[1024] =
         /*16-bit data, 32-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
@@ -1425,7 +1425,7 @@ const OpFn OP_TABLE(pentium2d_0f)[1024] =
         /*32-bit data, 32-bit addr*/
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opNOP,          ILLEGAL,        ILLEGAL,
-/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32, opHINT_NOP_a32,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
diff --git a/src/cpu_common/x86_ops_i686.h b/src/cpu_common/x86_ops_i686.h
index 469076c8b..dad86b410 100644
--- a/src/cpu_common/x86_ops_i686.h
+++ b/src/cpu_common/x86_ops_i686.h
@@ -45,377 +45,216 @@ opSYSEXIT(uint32_t fetchdat)
 }
 
 
+static int
+fx_save_stor_common(uint32_t fetchdat, int bits)
+{
+    uint8_t fxinst = 0;
+    uint16_t twd = x87_gettag();
+    uint32_t old_eaaddr = 0;
+    uint8_t ftwb = 0;
+    uint16_t rec_ftw = 0;
+    uint16_t fpus = 0;
+    uint64_t *p;
+
+    if (CPUID < 0x650)
+	return ILLEGAL(fetchdat);
+
+    FP_ENTER();
+
+    if (bits == 32) {
+	fetch_ea_32(fetchdat);
+    } else {
+	fetch_ea_16(fetchdat);
+    }
+
+    if (cpu_state.eaaddr & 0xf) {
+	x386_dynarec_log("Effective address %08X not on 16-byte boundary\n", cpu_state.eaaddr);
+	x86gpf(NULL, 0);
+	return cpu_state.abrt;
+    }
+
+    fxinst = (rmdat >> 3) & 7;
+
+    if ((fxinst > 1) || (cpu_mod == 3)) {
+	x86illegal();
+	return cpu_state.abrt;
+    }
+
+    FP_ENTER();
+
+    old_eaaddr = cpu_state.eaaddr;
+
+    if (fxinst == 1) {
+	/* FXRSTOR */
+	cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
+	fpus = readmemw(easeg, cpu_state.eaaddr + 2);
+	cpu_state.npxc = (cpu_state.npxc & ~FPU_CW_Reserved_Bits) | 0x0040;
+	codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
+	cpu_state.TOP = (fpus >> 11) & 7;
+	cpu_state.npxs &= fpus & ~0x3800;
+
+	x87_pc_off = readmeml(easeg, cpu_state.eaaddr+8);
+	x87_pc_seg = readmemw(easeg, cpu_state.eaaddr+12);
+
+	ftwb = readmemb(easeg, cpu_state.eaaddr + 4);
+
+	if (ftwb & 0x01)  rec_ftw |= 0x0003;
+	if (ftwb & 0x02)  rec_ftw |= 0x000C;
+	if (ftwb & 0x04)  rec_ftw |= 0x0030;
+	if (ftwb & 0x08)  rec_ftw |= 0x00C0;
+	if (ftwb & 0x10)  rec_ftw |= 0x0300;
+	if (ftwb & 0x20)  rec_ftw |= 0x0C00;
+	if (ftwb & 0x40)  rec_ftw |= 0x3000;
+	if (ftwb & 0x80)  rec_ftw |= 0xC000;
+
+	x87_op_off = readmeml(easeg, cpu_state.eaaddr+16);
+	x87_op_off |= (readmemw(easeg, cpu_state.eaaddr + 6) >> 12) << 16;
+	x87_op_seg = readmemw(easeg, cpu_state.eaaddr+20);
+
+	cpu_state.eaaddr = old_eaaddr + 32;
+	x87_ldmmx(&(cpu_state.MM[0]), &(cpu_state.MM_w4[0])); x87_ld_frstor(0);
+
+	cpu_state.eaaddr = old_eaaddr + 48;
+	x87_ldmmx(&(cpu_state.MM[1]), &(cpu_state.MM_w4[1])); x87_ld_frstor(1);
+
+	cpu_state.eaaddr = old_eaaddr + 64;
+	x87_ldmmx(&(cpu_state.MM[2]), &(cpu_state.MM_w4[2])); x87_ld_frstor(2);
+
+	cpu_state.eaaddr = old_eaaddr + 80;
+	x87_ldmmx(&(cpu_state.MM[3]), &(cpu_state.MM_w4[3])); x87_ld_frstor(3);
+
+	cpu_state.eaaddr = old_eaaddr + 96;
+	x87_ldmmx(&(cpu_state.MM[4]), &(cpu_state.MM_w4[4])); x87_ld_frstor(4);
+
+	cpu_state.eaaddr = old_eaaddr + 112;
+	x87_ldmmx(&(cpu_state.MM[5]), &(cpu_state.MM_w4[5])); x87_ld_frstor(5);
+
+	cpu_state.eaaddr = old_eaaddr + 128;
+	x87_ldmmx(&(cpu_state.MM[6]), &(cpu_state.MM_w4[6])); x87_ld_frstor(6);
+
+	cpu_state.eaaddr = old_eaaddr + 144;
+	x87_ldmmx(&(cpu_state.MM[7]), &(cpu_state.MM_w4[7])); x87_ld_frstor(7);
+
+	cpu_state.ismmx = 0;
+	/*Horrible hack, but as 86Box doesn't keep the FPU stack in 80-bit precision at all times
+	  something like this is needed*/
+	p = (uint64_t *) cpu_state.tag;
+#ifdef USE_NEW_DYNAREC
+	if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
+	    cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
+	    !cpu_state.TOP && (*p == 0x0101010101010101ull))
+#else
+	if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
+	    cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
+	    !cpu_state.TOP && !(*p))
+#endif
+		cpu_state.ismmx = 1;
+
+	x87_settag(rec_ftw);
+
+	CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
+
+	if (cpu_state.abrt)
+		x386_dynarec_log("FXRSTOR: abrt != 0\n");
+    } else {
+	/* FXSAVE */
+	if ((twd & 0x0003) == 0x0003)  ftwb |= 0x01;
+	if ((twd & 0x000C) == 0x000C)  ftwb |= 0x02;
+	if ((twd & 0x0030) == 0x0030)  ftwb |= 0x04;
+	if ((twd & 0x00C0) == 0x00C0)  ftwb |= 0x08;
+	if ((twd & 0x0300) == 0x0300)  ftwb |= 0x10;
+	if ((twd & 0x0C00) == 0x0C00)  ftwb |= 0x20;
+	if ((twd & 0x3000) == 0x3000)  ftwb |= 0x40;
+	if ((twd & 0xC000) == 0xC000)  ftwb |= 0x80;
+
+	writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
+	writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
+	writememb(easeg,cpu_state.eaaddr+4,ftwb);
+
+	writememw(easeg,cpu_state.eaaddr+6,(x87_op_off>>16)<<12);
+	writememl(easeg,cpu_state.eaaddr+8,x87_pc_off);
+	writememw(easeg,cpu_state.eaaddr+12,x87_pc_seg);
+
+	writememl(easeg,cpu_state.eaaddr+16,x87_op_off);
+	writememw(easeg,cpu_state.eaaddr+20,x87_op_seg);
+
+	cpu_state.eaaddr = old_eaaddr + 32;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[0]) : x87_st_fsave(0);
+
+	cpu_state.eaaddr = old_eaaddr + 48;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[1]) : x87_st_fsave(1);
+
+	cpu_state.eaaddr = old_eaaddr + 64;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[2]) : x87_st_fsave(2);
+
+	cpu_state.eaaddr = old_eaaddr + 80;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[3]) : x87_st_fsave(3);
+
+	cpu_state.eaaddr = old_eaaddr + 96;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[4]) : x87_st_fsave(4);
+
+	cpu_state.eaaddr = old_eaaddr + 112;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[5]) : x87_st_fsave(5);
+
+	cpu_state.eaaddr = old_eaaddr + 128;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[6]) : x87_st_fsave(6);
+
+	cpu_state.eaaddr = old_eaaddr + 144;
+	cpu_state.ismmx ? x87_stmmx(cpu_state.MM[7]) : x87_st_fsave(7);
+
+	cpu_state.eaaddr = old_eaaddr;
+
+	cpu_state.npxc = 0x37F;
+        codegen_set_rounding_mode(X87_ROUNDING_NEAREST);
+	cpu_state.npxs = 0;
+	p = (uint64_t *)cpu_state.tag;
+#ifdef USE_NEW_DYNAREC
+        *p = 0;
+#else
+        *p = 0x0303030303030303ll;
+#endif
+	cpu_state.TOP = 0;
+	cpu_state.ismmx = 0;
+
+	CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
+
+	if (cpu_state.abrt)
+		x386_dynarec_log("FXSAVE: abrt != 0\n");
+    }
+
+    return cpu_state.abrt;
+}
+
+
 static int
 opFXSAVESTOR_a16(uint32_t fetchdat)
 {
-	uint8_t fxinst = 0;
-	uint16_t twd = x87_gettag();
-	uint16_t old_eaaddr = 0;
-	uint8_t ftwb = 0;
-	uint16_t rec_ftw = 0;
-	uint16_t fpus = 0;
-	uint64_t *p;
-
-	if (CPUID < 0x650)  return ILLEGAL(fetchdat);
-
-	FP_ENTER();
-
-	fetch_ea_16(fetchdat);
-
-	if (cpu_state.eaaddr & 0xf)
-	{
-		x386_dynarec_log("Effective address %04X not on 16-byte boundary\n", cpu_state.eaaddr);
-		x86gpf(NULL, 0);
-		return cpu_state.abrt;
-	}
-
-	fxinst = (rmdat >> 3) & 7;
-
-	if ((fxinst > 1) || (cpu_mod == 3))
-	{
-		x86illegal();
-		return cpu_state.abrt;
-	}
-
-	FP_ENTER();
-
-	old_eaaddr = cpu_state.eaaddr;
-
-	if (fxinst == 1)
-	{
-		/* FXRSTOR */
-		cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
-#ifdef USE_NEW_DYNAREC
-                codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#endif
-		fpus = readmemw(easeg, cpu_state.eaaddr + 2);
-		cpu_state.npxc = (cpu_state.npxc & ~FPU_CW_Reserved_Bits) | 0x0040;
-#ifdef USE_NEW_DYNAREC
-                codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#endif
-		cpu_state.TOP = (fpus >> 11) & 7;
-		cpu_state.npxs &= fpus & ~0x3800;
-
-		/* foo = readmemw(easeg, cpu_state.eaaddr + 6) & 0x7FF; */
-
-               	x87_pc_off = readmeml(easeg, cpu_state.eaaddr+8);
-                x87_pc_seg = readmemw(easeg, cpu_state.eaaddr+12);
-		/* if (cr0 & 1)
-		{
-			x87_pc_seg &= 0xFFFC;
-			x87_pc_seg |= ((cpu_state.seg_cs.access >> 5) & 3);
-		} */
-
-		ftwb = readmemb(easeg, cpu_state.eaaddr + 4);
-
-		if (ftwb & 0x01)  rec_ftw |= 0x0003;
-		if (ftwb & 0x02)  rec_ftw |= 0x000C;
-		if (ftwb & 0x04)  rec_ftw |= 0x0030;
-		if (ftwb & 0x08)  rec_ftw |= 0x00C0;
-		if (ftwb & 0x10)  rec_ftw |= 0x0300;
-		if (ftwb & 0x20)  rec_ftw |= 0x0C00;
-		if (ftwb & 0x40)  rec_ftw |= 0x3000;
-		if (ftwb & 0x80)  rec_ftw |= 0xC000;
-
-               	x87_op_off = readmeml(easeg, cpu_state.eaaddr+16);
-		x87_op_off |= (readmemw(easeg, cpu_state.eaaddr + 6) >> 12) << 16;
-                x87_op_seg = readmemw(easeg, cpu_state.eaaddr+20);
-		/* if (cr0 & 1)
-		{
-			x87_op_seg &= 0xFFFC;
-			x87_op_seg |= ((_ds.access >> 5) & 3);
-		} */
-
-		cpu_state.eaaddr = old_eaaddr + 32;
-		x87_ldmmx(&(cpu_state.MM[0]), &(cpu_state.MM_w4[0])); x87_ld_frstor(0);
-
-		cpu_state.eaaddr = old_eaaddr + 48;
-		x87_ldmmx(&(cpu_state.MM[1]), &(cpu_state.MM_w4[1])); x87_ld_frstor(1);
-
-		cpu_state.eaaddr = old_eaaddr + 64;
-		x87_ldmmx(&(cpu_state.MM[2]), &(cpu_state.MM_w4[2])); x87_ld_frstor(2);
-
-		cpu_state.eaaddr = old_eaaddr + 80;
-		x87_ldmmx(&(cpu_state.MM[3]), &(cpu_state.MM_w4[3])); x87_ld_frstor(3);
-
-		cpu_state.eaaddr = old_eaaddr + 96;
-		x87_ldmmx(&(cpu_state.MM[4]), &(cpu_state.MM_w4[4])); x87_ld_frstor(4);
-
-		cpu_state.eaaddr = old_eaaddr + 112;
-		x87_ldmmx(&(cpu_state.MM[5]), &(cpu_state.MM_w4[5])); x87_ld_frstor(5);
-
-		cpu_state.eaaddr = old_eaaddr + 128;
-		x87_ldmmx(&(cpu_state.MM[6]), &(cpu_state.MM_w4[6])); x87_ld_frstor(6);
-
-		cpu_state.eaaddr = old_eaaddr + 144;
-		x87_ldmmx(&(cpu_state.MM[7]), &(cpu_state.MM_w4[7])); x87_ld_frstor(7);
-
-	        cpu_state.ismmx = 0;
-	        /*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
-	          something like this is needed*/
-		p = (uint64_t *)cpu_state.tag;
-		if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
-			cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
-			!cpu_state.TOP && !(*p))
-	        cpu_state.ismmx = 1;
-
-		x87_settag(rec_ftw);
-
-	        CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
-
-		if(cpu_state.abrt)  x386_dynarec_log("FXRSTOR: abrt != 0\n");
-	}
-	else
-	{
-		/* FXSAVE */
-		if ((twd & 0x0003) == 0x0003)  ftwb |= 0x01;
-		if ((twd & 0x000C) == 0x000C)  ftwb |= 0x02;
-		if ((twd & 0x0030) == 0x0030)  ftwb |= 0x04;
-		if ((twd & 0x00C0) == 0x00C0)  ftwb |= 0x08;
-		if ((twd & 0x0300) == 0x0300)  ftwb |= 0x10;
-		if ((twd & 0x0C00) == 0x0C00)  ftwb |= 0x20;
-		if ((twd & 0x3000) == 0x3000)  ftwb |= 0x40;
-		if ((twd & 0xC000) == 0xC000)  ftwb |= 0x80;
-
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
-                writememb(easeg,cpu_state.eaaddr+4,ftwb);
-
-                writememw(easeg,cpu_state.eaaddr+6,(x87_op_off>>16)<<12);
-               	writememl(easeg,cpu_state.eaaddr+8,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+12,x87_pc_seg);
-
-                writememl(easeg,cpu_state.eaaddr+16,x87_op_off);
-                writememw(easeg,cpu_state.eaaddr+20,x87_op_seg);
-
-		cpu_state.eaaddr = old_eaaddr + 32;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[0]) : x87_st_fsave(0);
-
-		cpu_state.eaaddr = old_eaaddr + 48;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[1]) : x87_st_fsave(1);
-
-		cpu_state.eaaddr = old_eaaddr + 64;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[2]) : x87_st_fsave(2);
-
-		cpu_state.eaaddr = old_eaaddr + 80;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[3]) : x87_st_fsave(3);
-
-		cpu_state.eaaddr = old_eaaddr + 96;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[4]) : x87_st_fsave(4);
-
-		cpu_state.eaaddr = old_eaaddr + 112;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[5]) : x87_st_fsave(5);
-
-		cpu_state.eaaddr = old_eaaddr + 128;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[6]) : x87_st_fsave(6);
-
-		cpu_state.eaaddr = old_eaaddr + 144;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[7]) : x87_st_fsave(7);
-
-		cpu_state.eaaddr = old_eaaddr;
-
-        	cpu_state.npxc = 0x37F;
-#ifdef USE_NEW_DYNAREC
-                codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#endif
-	        cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
-        	cpu_state.npxs = 0;
-		p = (uint64_t *)cpu_state.tag;
-	        *p = 0x0303030303030303ll;
-        	cpu_state.TOP = 0;
-	        cpu_state.ismmx = 0;
-
-		CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
-
-		if(cpu_state.abrt)  x386_dynarec_log("FXSAVE: abrt != 0\n");
-	}
-
-	return cpu_state.abrt;
+    return fx_save_stor_common(fetchdat, 16);
 }
 
-static int opFXSAVESTOR_a32(uint32_t fetchdat)
+
+static int
+opFXSAVESTOR_a32(uint32_t fetchdat)
 {
-	uint8_t fxinst = 0;
-	uint16_t twd = x87_gettag();
-	uint32_t old_eaaddr = 0;
-	uint8_t ftwb = 0;
-	uint16_t rec_ftw = 0;
-	uint16_t fpus = 0;
-	uint64_t *p;
-
-	if (CPUID < 0x650)  return ILLEGAL(fetchdat);
-
-	FP_ENTER();
-
-	fetch_ea_32(fetchdat);
-
-	if (cpu_state.eaaddr & 0xf)
-	{
-		x386_dynarec_log("Effective address %08X not on 16-byte boundary\n", cpu_state.eaaddr);
-		x86gpf(NULL, 0);
-		return cpu_state.abrt;
-	}
-
-	fxinst = (rmdat >> 3) & 7;
-
-	if ((fxinst > 1) || (cpu_mod == 3))
-	{
-		x86illegal();
-		return cpu_state.abrt;
-	}
-
-	FP_ENTER();
-
-	old_eaaddr = cpu_state.eaaddr;
-
-	if (fxinst == 1)
-	{
-		/* FXRSTOR */
-		cpu_state.npxc = readmemw(easeg, cpu_state.eaaddr);
-#ifdef USE_NEW_DYNAREC
-                codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#endif
-		fpus = readmemw(easeg, cpu_state.eaaddr + 2);
-		cpu_state.npxc = (cpu_state.npxc & ~FPU_CW_Reserved_Bits) | 0x0040;
-#ifdef USE_NEW_DYNAREC
-                codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#endif
-		cpu_state.TOP = (fpus >> 11) & 7;
-		cpu_state.npxs &= fpus & ~0x3800;
-
-		/* foo = readmemw(easeg, cpu_state.eaaddr + 6) & 0x7FF; */
-
-               	x87_pc_off = readmeml(easeg, cpu_state.eaaddr+8);
-                x87_pc_seg = readmemw(easeg, cpu_state.eaaddr+12);
-		/* if (cr0 & 1)
-		{
-			x87_pc_seg &= 0xFFFC;
-			x87_pc_seg |= ((cpu_state.seg_cs.access >> 5) & 3);
-		} */
-
-		ftwb = readmemb(easeg, cpu_state.eaaddr + 4);
-
-		if (ftwb & 0x01)  rec_ftw |= 0x0003;
-		if (ftwb & 0x02)  rec_ftw |= 0x000C;
-		if (ftwb & 0x04)  rec_ftw |= 0x0030;
-		if (ftwb & 0x08)  rec_ftw |= 0x00C0;
-		if (ftwb & 0x10)  rec_ftw |= 0x0300;
-		if (ftwb & 0x20)  rec_ftw |= 0x0C00;
-		if (ftwb & 0x40)  rec_ftw |= 0x3000;
-		if (ftwb & 0x80)  rec_ftw |= 0xC000;
-
-               	x87_op_off = readmeml(easeg, cpu_state.eaaddr+16);
-		x87_op_off |= (readmemw(easeg, cpu_state.eaaddr + 6) >> 12) << 16;
-                x87_op_seg = readmemw(easeg, cpu_state.eaaddr+20);
-		/* if (cr0 & 1)
-		{
-			x87_op_seg &= 0xFFFC;
-			x87_op_seg |= ((_ds.access >> 5) & 3);
-		} */
-
-		cpu_state.eaaddr = old_eaaddr + 32;
-		x87_ldmmx(&(cpu_state.MM[0]), &(cpu_state.MM_w4[0])); x87_ld_frstor(0);
-
-		cpu_state.eaaddr = old_eaaddr + 48;
-		x87_ldmmx(&(cpu_state.MM[1]), &(cpu_state.MM_w4[1])); x87_ld_frstor(1);
-
-		cpu_state.eaaddr = old_eaaddr + 64;
-		x87_ldmmx(&(cpu_state.MM[2]), &(cpu_state.MM_w4[2])); x87_ld_frstor(2);
-
-		cpu_state.eaaddr = old_eaaddr + 80;
-		x87_ldmmx(&(cpu_state.MM[3]), &(cpu_state.MM_w4[3])); x87_ld_frstor(3);
-
-		cpu_state.eaaddr = old_eaaddr + 96;
-		x87_ldmmx(&(cpu_state.MM[4]), &(cpu_state.MM_w4[4])); x87_ld_frstor(4);
-
-		cpu_state.eaaddr = old_eaaddr + 112;
-		x87_ldmmx(&(cpu_state.MM[5]), &(cpu_state.MM_w4[5])); x87_ld_frstor(5);
-
-		cpu_state.eaaddr = old_eaaddr + 128;
-		x87_ldmmx(&(cpu_state.MM[6]), &(cpu_state.MM_w4[6])); x87_ld_frstor(6);
-
-		cpu_state.eaaddr = old_eaaddr + 144;
-		x87_ldmmx(&(cpu_state.MM[7]), &(cpu_state.MM_w4[7])); x87_ld_frstor(7);
-
-	        cpu_state.ismmx = 0;
-	        /*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
-	          something like this is needed*/
-		p = (uint64_t *)cpu_state.tag;
-		if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
-			cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
-			!cpu_state.TOP && !(*p))
-	        cpu_state.ismmx = 1;
-
-		x87_settag(rec_ftw);
-
-	        CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
-
-		if(cpu_state.abrt)  x386_dynarec_log("FXRSTOR: abrt != 0\n");
-	}
-	else
-	{
-		/* FXSAVE */
-		if ((twd & 0x0003) == 0x0003)  ftwb |= 0x01;
-		if ((twd & 0x000C) == 0x000C)  ftwb |= 0x02;
-		if ((twd & 0x0030) == 0x0030)  ftwb |= 0x04;
-		if ((twd & 0x00C0) == 0x00C0)  ftwb |= 0x08;
-		if ((twd & 0x0300) == 0x0300)  ftwb |= 0x10;
-		if ((twd & 0x0C00) == 0x0C00)  ftwb |= 0x20;
-		if ((twd & 0x3000) == 0x3000)  ftwb |= 0x40;
-		if ((twd & 0xC000) == 0xC000)  ftwb |= 0x80;
-
-                writememw(easeg,cpu_state.eaaddr,cpu_state.npxc);
-                writememw(easeg,cpu_state.eaaddr+2,cpu_state.npxs);
-                writememb(easeg,cpu_state.eaaddr+4,ftwb);
-
-                writememw(easeg,cpu_state.eaaddr+6,(x87_op_off>>16)<<12);
-               	writememl(easeg,cpu_state.eaaddr+8,x87_pc_off);
-                writememw(easeg,cpu_state.eaaddr+12,x87_pc_seg);
-
-                writememl(easeg,cpu_state.eaaddr+16,x87_op_off);
-                writememw(easeg,cpu_state.eaaddr+20,x87_op_seg);
-
-		cpu_state.eaaddr = old_eaaddr + 32;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[0]) : x87_st_fsave(0);
-
-		cpu_state.eaaddr = old_eaaddr + 48;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[1]) : x87_st_fsave(1);
-
-		cpu_state.eaaddr = old_eaaddr + 64;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[2]) : x87_st_fsave(2);
-
-		cpu_state.eaaddr = old_eaaddr + 80;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[3]) : x87_st_fsave(3);
-
-		cpu_state.eaaddr = old_eaaddr + 96;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[4]) : x87_st_fsave(4);
-
-		cpu_state.eaaddr = old_eaaddr + 112;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[5]) : x87_st_fsave(5);
-
-		cpu_state.eaaddr = old_eaaddr + 128;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[6]) : x87_st_fsave(6);
-
-		cpu_state.eaaddr = old_eaaddr + 144;
-		cpu_state.ismmx ? x87_stmmx(cpu_state.MM[7]) : x87_st_fsave(7);
-
-		cpu_state.eaaddr = old_eaaddr;
-
-        	cpu_state.npxc = 0x37F;
-#ifdef USE_NEW_DYNAREC
-                codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
-#endif
-	        cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
-        	cpu_state.npxs = 0;
-		p = (uint64_t *)cpu_state.tag;
-	        *p = 0x0303030303030303ll;
-        	cpu_state.TOP = 0;
-	        cpu_state.ismmx = 0;
-
-		CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
-
-		if(cpu_state.abrt)  x386_dynarec_log("FXSAVE: abrt != 0\n");
-	}
-
-	return cpu_state.abrt;
+    return fx_save_stor_common(fetchdat, 32);
+}
+
+
+static int
+opHINT_NOP_a16(uint32_t fetchdat)
+{
+    fetch_ea_16(fetchdat);
+    CLOCK_CYCLES((is486) ? 1 : 3);
+    PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
+    return 0;
+}
+
+
+static int
+opHINT_NOP_a32(uint32_t fetchdat)
+{
+    fetch_ea_32(fetchdat);
+    CLOCK_CYCLES((is486) ? 1 : 3);
+    PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
+    return 0;
 }

From 21f979a748d3f6dd0ccec34465abd5e64674a4d9 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Wed, 22 Apr 2020 01:29:14 +0200
Subject: [PATCH 13/43] A fix in mem_add_bios() to make non-AT+ machines not
 segmentation fault the emulator on startup.

---
 src/mem.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mem.c b/src/mem.c
index be1589b3d..5bfd37fcf 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -2192,10 +2192,12 @@ mem_set_mem_state_smm(uint32_t base, uint32_t size, int state)
 void
 mem_add_bios(void)
 {
-    int temp_cpu_type, temp_cpu_16bitbus;
+    int temp_cpu_type, temp_cpu_16bitbus = 1;
 
-    temp_cpu_type = machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type;
-    temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC );
+    if (AT) {
+	temp_cpu_type = machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type;
+	temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC );
+    }
 
     if (biosmask > 0x1ffff) {
 	/* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */

From 15dcd63e728c40bfd01ac013a99bdd9b38c27134 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Wed, 22 Apr 2020 13:19:28 +0200
Subject: [PATCH 14/43] Console is now only initialized when the emulator is
 started with the -D / --debug parameter.

---
 src/win/win.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/src/win/win.c b/src/win/win.c
index e79844528..e8d2af475 100644
--- a/src/win/win.c
+++ b/src/win/win.c
@@ -233,7 +233,8 @@ CreateConsole(int init)
     int i;
 
     if (! init) {
-	FreeConsole();
+	if (force_debug)
+		FreeConsole();
 	return;
     }
 
@@ -271,6 +272,13 @@ CreateConsole(int init)
 }
 
 
+static void
+CloseConsole(void)
+{
+    CreateConsole(0);
+}
+
+
 /* Process the commandline, and create standard argc/argv array. */
 static int
 ProcessCommandLine(wchar_t ***argw)
@@ -362,7 +370,8 @@ WinMain(HINSTANCE hInst, HINSTANCE hPrev, LPSTR lpszArg, int nCmdShow)
     set_language(0x0409);
 
     /* Create console window. */
-    CreateConsole(1);
+    if (force_debug)
+	CreateConsole(1);
 
     /* Process the command line for options. */
     argc = ProcessCommandLine(&argw);
@@ -370,7 +379,8 @@ WinMain(HINSTANCE hInst, HINSTANCE hPrev, LPSTR lpszArg, int nCmdShow)
     /* Pre-initialize the system, this loads the config file. */
     if (! pc_init(argc, argw)) {
 	/* Detach from console. */
-	CreateConsole(0);
+	if (force_debug)
+		CreateConsole(0);
 
 	if (source_hwnd)
 		PostMessage((HWND) (uintptr_t) source_hwnd, WM_HAS_SHUTDOWN, (WPARAM) 0, (LPARAM) hwndMain);
@@ -380,9 +390,8 @@ WinMain(HINSTANCE hInst, HINSTANCE hPrev, LPSTR lpszArg, int nCmdShow)
 	return(1);
     }
 
-    /* Cleanup: we may no longer need the console. */
-    if (! force_debug)
-	CreateConsole(0);
+    if (force_debug)
+	atexit(CloseConsole);
 
     /* Handle our GUI. */
     i = ui_init(nCmdShow);

From cf7ecacb9d07b980e279a5eed3ad012f628f309d Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Wed, 22 Apr 2020 22:11:01 +0200
Subject: [PATCH 15/43] Fixed a typo in the Sound Blaster IRQ update code,
 reported by TheCollector1995.

---
 src/sound/snd_sb_dsp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/sound/snd_sb_dsp.c b/src/sound/snd_sb_dsp.c
index d9d1c3f5a..30b5ae23a 100644
--- a/src/sound/snd_sb_dsp.c
+++ b/src/sound/snd_sb_dsp.c
@@ -184,7 +184,7 @@ sb_update_irq(sb_dsp_t *dsp)
 
     irq_pending = (dsp->sb_irq8 && !dsp->sb_irqm8) ||
 		  (dsp->sb_irq16 && !dsp->sb_irqm16) ||
-		  (dsp->sb_irq401 && !dsp->sb_irq401);
+		  (dsp->sb_irq401 && !dsp->sb_irqm401);
 
     if (irq_pending)
 	picint(1 << dsp->sb_irqnum);

From 5073a2c37e9eecea1ad65a3084b453d3a92eff00 Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Wed, 22 Apr 2020 22:29:25 +0200
Subject: [PATCH 16/43] The AZT MPU is not SB's UART MPU.

---
 src/sound/snd_azt2316a.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/sound/snd_azt2316a.c b/src/sound/snd_azt2316a.c
index 9e534a1d9..b88ee9abb 100644
--- a/src/sound/snd_azt2316a.c
+++ b/src/sound/snd_azt2316a.c
@@ -1179,7 +1179,6 @@ azt_init(const device_t *info)
         	mpu401_init(azt2316a->mpu, azt2316a->cur_mpu401_addr, azt2316a->cur_mpu401_irq, M_UART, device_get_config_int("receive_input401"));
 	} else
 		azt2316a->mpu = NULL;
-	sb_dsp_set_mpu(&azt2316a->sb->dsp, azt2316a->mpu);
 
 	if (device_get_config_int("receive_input"))
 		midi_in_handler(1, sb_dsp_input_msg, sb_dsp_input_sysex, &azt2316a->sb->dsp);

From d20c5d525c094428da5ae104b5ae1b10d6da1869 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 01:07:11 +0200
Subject: [PATCH 17/43] Fixed the old dynarec's MOD R/M tables to include the
 3DNow! instructions, and both dynarec's MOD R/M tables to include the i686
 hintable NOP's.

---
 src/cpu/codegen_x86-64.c | 4 ++--
 src/cpu/codegen_x86.c    | 6 +++---
 src/cpu_new/codegen.c    | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/cpu/codegen_x86-64.c b/src/cpu/codegen_x86-64.c
index a396e0008..051a3b414 100644
--- a/src/cpu/codegen_x86-64.c
+++ b/src/cpu/codegen_x86-64.c
@@ -548,8 +548,8 @@ static int opcode_modrm[256] =
 };
 int opcode_0f_modrm[256] =
 {
-        1, 1, 1, 1,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*00*/
-        0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*10*/
+        1, 1, 1, 1,  0, 0, 0, 0,  0, 0, 0, 0,  0, 1, 0, 1, /*00*/
+        0, 0, 0, 0,  0, 0, 0, 0,  1, 1, 1, 1,  1, 1, 1, 1, /*10*/
         1, 1, 1, 1,  1, 1, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*20*/
         0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*30*/
 
diff --git a/src/cpu/codegen_x86.c b/src/cpu/codegen_x86.c
index 037c377a6..8755f2cd2 100644
--- a/src/cpu/codegen_x86.c
+++ b/src/cpu/codegen_x86.c
@@ -1660,8 +1660,8 @@ static int opcode_modrm[256] =
 };
 int opcode_0f_modrm[256] =
 {
-        1, 1, 1, 1,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*00*/
-        0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*10*/
+        1, 1, 1, 1,  0, 0, 0, 0,  0, 0, 0, 0,  0, 1, 0, 1, /*00*/
+        0, 0, 0, 0,  0, 0, 0, 0,  1, 1, 1, 1,  1, 1, 1, 1, /*10*/
         1, 1, 1, 1,  1, 1, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*20*/
         0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*30*/
 
@@ -1680,7 +1680,7 @@ int opcode_0f_modrm[256] =
         0, 1, 1, 0,  0, 1, 0, 0,  1, 1, 0, 1,  1, 1, 0, 1, /*e0*/
         0, 1, 1, 1,  0, 1, 0, 0,  1, 1, 1, 0,  1, 1, 1, 0  /*f0*/
 };
-        
+
 void codegen_debug()
 {
 }
diff --git a/src/cpu_new/codegen.c b/src/cpu_new/codegen.c
index 96c64e2c5..e38dfb7a2 100644
--- a/src/cpu_new/codegen.c
+++ b/src/cpu_new/codegen.c
@@ -370,7 +370,7 @@ static uint8_t opcode_modrm[256] =
 static uint8_t opcode_0f_modrm[256] =
 {
         1, 1, 1, 1,  0, 0, 0, 0,  0, 0, 0, 0,  0, 1, 0, 1, /*00*/
-        0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*10*/
+        0, 0, 0, 0,  0, 0, 0, 0,  1, 1, 1, 1,  1, 1, 1, 1, /*10*/
         1, 1, 1, 1,  1, 1, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*20*/
         0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*30*/
 

From 7dcb8f6f1f696db1ac48f57ad3b09e956c51ab87 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <dhrdlicka@users.noreply.github.com>
Date: Thu, 23 Apr 2020 01:24:01 +0200
Subject: [PATCH 18/43] win: Add the "Media" menu to the menubar This is an
 alternative way to mount images to the virtual drives, as many people found
 the current behavior confusing.

---
 src/include/86box/language.h |   3 +-
 src/include/86box/win.h      |   1 +
 src/win/86Box.rc             |   1 +
 src/win/win_stbar.c          | 463 +++++++++++++++++++++--------------
 src/win/win_ui.c             |   3 +
 5 files changed, 281 insertions(+), 190 deletions(-)

diff --git a/src/include/86box/language.h b/src/include/86box/language.h
index f112ec19f..7aa2e17ee 100644
--- a/src/include/86box/language.h
+++ b/src/include/86box/language.h
@@ -99,6 +99,7 @@
 #define IDS_2123	2123		// "Unable to initialize Ghostscript..."
 #define IDS_2124	2124		// "MO %i (%03i): %ls"
 #define IDS_2125	2125		// "MO images (*.IM?)\0*.IM..."
+#define IDS_2126	2126		// "Media"
 
 #define IDS_4096	4096		// "Hard disk (%s)"
 #define IDS_4097	4097		// "%01i:%01i"
@@ -177,7 +178,7 @@
 
 #define IDS_LANG_ENUS	IDS_7168
 
-#define STR_NUM_2048	78
+#define STR_NUM_2048	79
 #define STR_NUM_3072	11
 #define STR_NUM_4096	18
 #define STR_NUM_4352	7
diff --git a/src/include/86box/win.h b/src/include/86box/win.h
index 597ebaa59..5498d3f07 100644
--- a/src/include/86box/win.h
+++ b/src/include/86box/win.h
@@ -168,6 +168,7 @@ extern void	win_settings_open_ex(HWND hwnd, int category);
 /* Functions in win_stbar.c: */
 extern HWND	hwndSBAR;
 extern void	StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst);
+extern int	MediaMenuHandler(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam);
 
 
 /* Functions in win_dialog.c: */
diff --git a/src/win/86Box.rc b/src/win/86Box.rc
index 432a0b8c1..214dd945a 100644
--- a/src/win/86Box.rc
+++ b/src/win/86Box.rc
@@ -915,6 +915,7 @@ BEGIN
     IDS_2123	"Unable to initialize Ghostscript, gsdll32.dll is required for automatic convertion of PostScript files to PDF.\n\nAny documents sent to the generic PostScript printer will be saved as PostScript files (.ps)."
     IDS_2124	"MO %i (%03i): %ls"
     IDS_2125	"MO images (*.IM?)\0*.IM?\0All files (*.*)\0*.*\0"
+    IDS_2126	"&Media"
 END
 
 STRINGTABLE DISCARDABLE 
diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c
index ecb9c8a62..0dfd7af1d 100644
--- a/src/win/win_stbar.c
+++ b/src/win/win_stbar.c
@@ -72,6 +72,9 @@ static int	sb_parts = 0;
 static int	sb_ready = 0;
 static uint8_t	sb_map[256];
 
+static HMENU	hmenuMedia;
+static HMENU	*media_menu_handles;
+
 
 /* Also used by win_settings.c */
 intptr_t
@@ -483,10 +486,33 @@ ui_sb_update_tip(int meaning)
 	}
 
 	SendMessage(hwndSBAR, SB_SETTIPTEXT, part, (LPARAM)sbTips[part]);
+	ModifyMenu(hmenuMedia, part, MF_BYPOSITION, (UINT_PTR)media_menu_handles[part], sbTips[part]);
     }
 }
 
 
+static void
+MediaMenuDestroyMenus(void)
+{
+    int i;
+
+    if (sb_parts == 0) return;
+
+    if (! media_menu_handles) return;
+
+    for (i=0; i<sb_parts; i++) {
+	if (media_menu_handles[i]) {
+		RemoveMenu(hmenuMedia, (UINT_PTR)media_menu_handles[i], MF_BYCOMMAND);
+		DestroyMenu(media_menu_handles[i]);
+		media_menu_handles[i] = NULL;
+	}
+    }
+
+    free(media_menu_handles);
+    media_menu_handles = NULL;
+}
+
+
 static void
 StatusBarDestroyMenus(void)
 {
@@ -529,6 +555,18 @@ StatusBarDestroyTips(void)
 }
 
 
+static HMENU
+MediaMenuCreatePopupMenu(int part)
+{
+    HMENU h;
+
+    h = CreatePopupMenu();
+    AppendMenu(hmenuMedia, MF_POPUP | MF_STRING, (UINT_PTR)h, 0);
+
+    return(h);
+}
+
+
 static HMENU
 StatusBarCreatePopupMenu(int part)
 {
@@ -594,6 +632,7 @@ ui_sb_update_panes(void)
 	}
 	StatusBarDestroyMenus();
 	StatusBarDestroyTips();
+	MediaMenuDestroyMenus();
     }
 
     memset(sb_map, 0xff, sizeof(sb_map));
@@ -656,6 +695,8 @@ ui_sb_update_panes(void)
      memset(sb_menu_handles, 0, sb_parts * sizeof(HMENU));
     sbTips = (WCHAR **)malloc(sb_parts * sizeof(WCHAR *));
      memset(sbTips, 0, sb_parts * sizeof(WCHAR *));
+    media_menu_handles = (HMENU *)malloc(sb_parts * sizeof(HMENU));
+     memset(media_menu_handles, 0, sb_parts * sizeof(HMENU));
 
     sb_parts = 0;
     for (i=0; i<FDD_NUM; i++) {
@@ -777,9 +818,15 @@ ui_sb_update_panes(void)
 			sb_part_icons[i] = (wcslen(floppyfns[sb_part_meanings[i] & 0xf]) == 0) ? 128 : 0;
 			sb_part_icons[i] |= fdd_type_to_icon(fdd_get_type(sb_part_meanings[i] & 0xf));
 			sb_menu_handles[i] = StatusBarCreatePopupMenu(i);
+			media_menu_handles[i] = MediaMenuCreatePopupMenu(i);
+
 			StatusBarCreateFloppySubmenu(sb_menu_handles[i], sb_part_meanings[i] & 0xf);
+			StatusBarCreateFloppySubmenu(media_menu_handles[i], sb_part_meanings[i] & 0xf);
+
 			EnableMenuItem(sb_menu_handles[i], IDM_FLOPPY_EJECT | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | ((sb_part_icons[i] & 128) ? MF_GRAYED : MF_ENABLED));
+			EnableMenuItem(media_menu_handles[i], IDM_FLOPPY_EJECT | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | ((sb_part_icons[i] & 128) ? MF_GRAYED : MF_ENABLED));
 			StatusBarCreateFloppyTip(i);
+
 			break;
 
 		case SB_CDROM:		/* CD-ROM */
@@ -790,27 +837,45 @@ ui_sb_update_panes(void)
 				sb_part_icons[i] = 128;
 			sb_part_icons[i] |= 32;
 			sb_menu_handles[i] = StatusBarCreatePopupMenu(i);
+			media_menu_handles[i] = MediaMenuCreatePopupMenu(i);
+
 			StatusBarCreateCdromSubmenu(sb_menu_handles[i], sb_part_meanings[i] & 0xf);
+			StatusBarCreateCdromSubmenu(media_menu_handles[i], sb_part_meanings[i] & 0xf);
+
 			EnableMenuItem(sb_menu_handles[i], IDM_CDROM_RELOAD | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | MF_GRAYED);
+			EnableMenuItem(media_menu_handles[i], IDM_CDROM_RELOAD | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | MF_GRAYED);
 			StatusBarCreateCdromTip(i);
+
 			break;
 
 		case SB_ZIP:		/* Iomega ZIP */
 			sb_part_icons[i] = (wcslen(zip_drives[sb_part_meanings[i] & 0xf].image_path) == 0) ? 128 : 0;
 			sb_part_icons[i] |= 48;
 			sb_menu_handles[i] = StatusBarCreatePopupMenu(i);
+			media_menu_handles[i] = MediaMenuCreatePopupMenu(i);
+
 			StatusBarCreateZIPSubmenu(sb_menu_handles[i], sb_part_meanings[i] & 0xf);
+			StatusBarCreateZIPSubmenu(media_menu_handles[i], sb_part_meanings[i] & 0xf);
+
 			EnableMenuItem(sb_menu_handles[i], IDM_ZIP_EJECT | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | ((sb_part_icons[i] & 128) ? MF_GRAYED : MF_ENABLED));
+			EnableMenuItem(media_menu_handles[i], IDM_ZIP_EJECT | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | ((sb_part_icons[i] & 128) ? MF_GRAYED : MF_ENABLED));
 			StatusBarCreateZIPTip(i);
+
 			break;
 			
 		case SB_MO:		/* Magneto-Optical disk */	
 			sb_part_icons[i] = (wcslen(mo_drives[sb_part_meanings[i] & 0xf].image_path) == 0) ? 128 : 0;
 			sb_part_icons[i] |= 56;
 			sb_menu_handles[i] = StatusBarCreatePopupMenu(i);
+			media_menu_handles[i] = MediaMenuCreatePopupMenu(i);
+
 			StatusBarCreateMOSubmenu(sb_menu_handles[i], sb_part_meanings[i] & 0xf);
+			StatusBarCreateMOSubmenu(media_menu_handles[i], sb_part_meanings[i] & 0xf);
+
 			EnableMenuItem(sb_menu_handles[i], IDM_MO_EJECT | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | ((sb_part_icons[i] & 128) ? MF_GRAYED : MF_ENABLED));
+			EnableMenuItem(media_menu_handles[i], IDM_MO_EJECT | (sb_part_meanings[i] & 0xf), MF_BYCOMMAND | ((sb_part_icons[i] & 128) ? MF_GRAYED : MF_ENABLED));
 			StatusBarCreateMOTip(i);
+
 			break;
 
 		case SB_HDD:		/* Hard disk */
@@ -838,6 +903,7 @@ ui_sb_update_panes(void)
 		SendMessage(hwndSBAR, SB_SETTEXT, i | SBT_NOBORDERS, (LPARAM)L"");
 		SendMessage(hwndSBAR, SB_SETICON, i, (LPARAM)hIcon[sb_part_icons[i]]);
 		SendMessage(hwndSBAR, SB_SETTIPTEXT, i, (LPARAM)sbTips[i]);
+		ModifyMenu(hmenuMedia, i, MF_BYPOSITION, (UINT_PTR)media_menu_handles[i], sbTips[i]);
 	} else
 		SendMessage(hwndSBAR, SB_SETICON, i, (LPARAM)NULL);
     }
@@ -868,8 +934,8 @@ ui_sb_mount_floppy_img(uint8_t id, int part, uint8_t wp, wchar_t *file_name)
     fdd_load(id, file_name);
     if (sb_ready) {
 	ui_sb_update_icon_state(SB_FLOPPY | id, wcslen(floppyfns[id]) ? 0 : 1);
-	EnableMenuItem(sb_menu_handles[part], IDM_FLOPPY_EJECT | id, MF_BYCOMMAND | (wcslen(floppyfns[id]) ? MF_ENABLED : MF_GRAYED));
-    	EnableMenuItem(sb_menu_handles[part], IDM_FLOPPY_EXPORT_TO_86F | id, MF_BYCOMMAND | (wcslen(floppyfns[id]) ? MF_ENABLED : MF_GRAYED));
+	ui_sb_enable_menu_item(SB_FLOPPY | id, IDM_FLOPPY_EJECT | id, MF_BYCOMMAND | (wcslen(floppyfns[id]) ? MF_ENABLED : MF_GRAYED));
+    	ui_sb_enable_menu_item(SB_FLOPPY | id, IDM_FLOPPY_EXPORT_TO_86F | id, MF_BYCOMMAND | (wcslen(floppyfns[id]) ? MF_ENABLED : MF_GRAYED));
 	ui_sb_update_tip(SB_FLOPPY | id);
     }
     config_save();
@@ -887,8 +953,8 @@ ui_sb_mount_zip_img(uint8_t id, int part, uint8_t wp, wchar_t *file_name)
     zip_insert(dev);
     if (sb_ready) {
 	ui_sb_update_icon_state(SB_ZIP | id, wcslen(zip_drives[id].image_path) ? 0 : 1);
-	EnableMenuItem(sb_menu_handles[part], IDM_ZIP_EJECT | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_ENABLED : MF_GRAYED));
-	EnableMenuItem(sb_menu_handles[part], IDM_ZIP_RELOAD | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_GRAYED : MF_ENABLED));
+	ui_sb_enable_menu_item(SB_ZIP | id, IDM_ZIP_EJECT | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_ENABLED : MF_GRAYED));
+	ui_sb_enable_menu_item(SB_ZIP | id, IDM_ZIP_RELOAD | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_GRAYED : MF_ENABLED));
 	ui_sb_update_tip(SB_ZIP | id);
     }
     config_save();
@@ -905,13 +971,203 @@ ui_sb_mount_mo_img(uint8_t id, int part, uint8_t wp, wchar_t *file_name)
     mo_insert(dev);
     if (sb_ready) {
 	ui_sb_update_icon_state(SB_MO | id, wcslen(mo_drives[id].image_path) ? 0 : 1);
-	EnableMenuItem(sb_menu_handles[part], IDM_MO_EJECT | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_ENABLED : MF_GRAYED));
-	EnableMenuItem(sb_menu_handles[part], IDM_MO_RELOAD | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_GRAYED : MF_ENABLED));
+	ui_sb_enable_menu_item(SB_MO | id, IDM_MO_EJECT | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_ENABLED : MF_GRAYED));
+	ui_sb_enable_menu_item(SB_MO | id, IDM_MO_RELOAD | id, MF_BYCOMMAND | (wcslen(zip_drives[id].image_path) ? MF_GRAYED : MF_ENABLED));
 	ui_sb_update_tip(SB_MO | id);
     }
     config_save();
 }
 
+int
+MediaMenuHandler(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
+{
+    int id = 0, ret = 0;
+    uint8_t part = 0;
+    WCHAR temp_path[1024];
+    int item_id, item_params;
+
+    item_id = LOWORD(wParam) & 0xff00;	/* low 8 bits */
+    item_params = LOWORD(wParam) & 0x00ff;	/* high 8 bits */
+
+    switch (item_id) {
+	case IDM_FLOPPY_IMAGE_NEW:
+		id = item_params & 0x0003;
+		part = sb_map[SB_FLOPPY | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		NewFloppyDialogCreate(hwnd, id, part);
+		break;
+
+	case IDM_FLOPPY_IMAGE_EXISTING:
+	case IDM_FLOPPY_IMAGE_EXISTING_WP:
+		id = item_params & 0x0003;
+		part = sb_map[SB_FLOPPY | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		ret = file_dlg_w_st(hwnd, IDS_2118, floppyfns[id], 0);
+		if (! ret)
+			ui_sb_mount_floppy_img(id, part, (item_id == IDM_FLOPPY_IMAGE_EXISTING_WP) ? 1 : 0, wopenfilestring);
+		break;
+
+	case IDM_FLOPPY_EJECT:
+		id = item_params & 0x0003;
+		part = sb_map[SB_FLOPPY | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+				break;
+
+		fdd_close(id);
+		ui_sb_update_icon_state(SB_FLOPPY | id, 1);
+		ui_sb_enable_menu_item(SB_FLOPPY | id, IDM_FLOPPY_EJECT | id, MF_BYCOMMAND | MF_GRAYED);
+		ui_sb_enable_menu_item(SB_FLOPPY | id, IDM_FLOPPY_EJECT | id, MF_BYCOMMAND | MF_GRAYED);
+		ui_sb_update_tip(SB_FLOPPY | id);
+		config_save();
+		break;
+
+	case IDM_FLOPPY_EXPORT_TO_86F:
+		id = item_params & 0x0003;
+		part = sb_map[SB_FLOPPY | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		ret = file_dlg_w_st(hwnd, IDS_2076, floppyfns[id], 1);
+		if (! ret) {
+			plat_pause(1);
+			ret = d86f_export(id, wopenfilestring);
+			if (!ret)
+				ui_msgbox(MBX_ERROR, (wchar_t *)IDS_4108);
+			plat_pause(0);
+		}
+		break;
+
+	case IDM_CDROM_MUTE:
+		id = item_params & 0x0007;
+		part = sb_map[SB_CDROM | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+				break;
+
+		cdrom[id].sound_on ^= 1;
+		ui_sb_check_menu_item(SB_CDROM | id, IDM_CDROM_MUTE | id, cdrom[id].sound_on ? MF_UNCHECKED : MF_CHECKED);
+		config_save();
+		sound_cd_thread_reset();
+		break;
+
+	case IDM_CDROM_EMPTY:
+		id = item_params & 0x0007;
+		part = sb_map[SB_CDROM | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		cdrom_eject(id);
+		break;
+
+	case IDM_CDROM_RELOAD:
+		id = item_params & 0x0007;
+		part = sb_map[SB_CDROM | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		cdrom_reload(id);
+		break;
+
+	case IDM_CDROM_IMAGE:
+		id = item_params & 0x0007;
+		part = sb_map[SB_CDROM | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		if (!file_dlg_w_st(hwnd, IDS_2075, cdrom[id].image_path, 0)) {
+			cdrom[id].prev_host_drive = cdrom[id].host_drive;
+			wcscpy(temp_path, wopenfilestring);
+			wcscpy(cdrom[id].prev_image_path, cdrom[id].image_path);
+			if (cdrom[id].ops && cdrom[id].ops->exit)
+				cdrom[id].ops->exit(&(cdrom[id]));
+			cdrom[id].ops = NULL;
+			memset(cdrom[id].image_path, 0, sizeof(cdrom[id].image_path));
+			cdrom_image_open(&(cdrom[id]), temp_path);
+			/* Signal media change to the emulated machine. */
+			if (cdrom[id].insert)
+				cdrom[id].insert(cdrom[id].priv);
+			cdrom[id].host_drive = (wcslen(cdrom[id].image_path) == 0) ? 0 : 200;
+			if (cdrom[id].host_drive == 200) {
+				ui_sb_check_menu_item(SB_CDROM | id, IDM_CDROM_EMPTY | id, MF_UNCHECKED);
+				ui_sb_check_menu_item(SB_CDROM | id, IDM_CDROM_IMAGE | id, MF_CHECKED);
+				ui_sb_update_icon_state(SB_CDROM | id, 0);
+			} else {
+				ui_sb_check_menu_item(SB_CDROM | id, IDM_CDROM_IMAGE | id, MF_UNCHECKED);
+				ui_sb_check_menu_item(SB_CDROM | id, IDM_CDROM_EMPTY | id, MF_CHECKED);
+				ui_sb_update_icon_state(SB_CDROM | id, 1);
+			}
+			ui_sb_enable_menu_item(SB_CDROM | id, IDM_CDROM_RELOAD | id, MF_BYCOMMAND | MF_GRAYED);
+			ui_sb_update_tip(SB_CDROM | id);
+			config_save();
+		}
+		break;
+
+	case IDM_ZIP_IMAGE_NEW:
+		id = item_params & 0x0003;
+		part = sb_map[SB_ZIP | id];
+		NewFloppyDialogCreate(hwnd, id | 0x80, part);	/* NewZIPDialogCreate */
+		break;
+
+	case IDM_ZIP_IMAGE_EXISTING:
+	case IDM_ZIP_IMAGE_EXISTING_WP:
+		id = item_params & 0x0003;
+		part = sb_map[SB_ZIP | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		ret = file_dlg_w_st(hwnd, IDS_2058, zip_drives[id].image_path, 0);
+		if (! ret)
+			ui_sb_mount_zip_img(id, part, (item_id == IDM_ZIP_IMAGE_EXISTING_WP) ? 1 : 0, wopenfilestring);
+		break;
+
+	case IDM_ZIP_EJECT:
+		id = item_params & 0x0003;
+		zip_eject(id);
+		break;
+
+	case IDM_ZIP_RELOAD:
+		id = item_params & 0x0003;
+		zip_reload(id);
+		break;
+
+	case IDM_MO_IMAGE_NEW:
+		id = item_params & 0x0003;
+		part = sb_map[SB_MO | id];
+		NewFloppyDialogCreate(hwnd, id | 0x80, part);	/* NewZIPDialogCreate */
+		break;
+
+	case IDM_MO_IMAGE_EXISTING:
+	case IDM_MO_IMAGE_EXISTING_WP:
+		id = item_params & 0x0003;
+		part = sb_map[SB_MO | id];
+		if ((part == 0xff) || (sb_menu_handles == NULL))
+			break;
+
+		ret = file_dlg_w_st(hwnd, IDS_2125, mo_drives[id].image_path, 0);
+		if (! ret)
+			ui_sb_mount_mo_img(id, part, (item_id == IDM_MO_IMAGE_EXISTING_WP) ? 1 : 0, wopenfilestring);
+		break;
+
+	case IDM_MO_EJECT:
+		id = item_params & 0x0003;
+		mo_eject(id);
+		break;
+
+	case IDM_MO_RELOAD:
+		id = item_params & 0x0003;
+		mo_reload(id);
+		break;
+
+	default:
+		return(0);
+    }
+
+    return(1);
+}
+
 
 /* Handle messages for the Status Bar window. */
 #if defined(__amd64__) || defined(__aarch64__)
@@ -921,195 +1177,13 @@ static BOOL CALLBACK
 #endif
 StatusBarProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
 {
-    WCHAR temp_path[1024];
     RECT rc;
     POINT pt;
-    int ret = 0;
     int item_id = 0;
-    int item_params = 0;
-    int id = 0;
-    uint8_t part = 0;
 
     switch (message) {
 	case WM_COMMAND:
-		item_id = LOWORD(wParam) & 0xff00;	/* low 8 bits */
-		item_params = LOWORD(wParam) & 0x00ff;	/* high 8 bits */
-
-                switch (item_id) {
-			case IDM_FLOPPY_IMAGE_NEW:
-				id = item_params & 0x0003;
-				part = sb_map[SB_FLOPPY | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				NewFloppyDialogCreate(hwnd, id, part);
-				break;
-
-			case IDM_FLOPPY_IMAGE_EXISTING:
-			case IDM_FLOPPY_IMAGE_EXISTING_WP:
-				id = item_params & 0x0003;
-				part = sb_map[SB_FLOPPY | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				ret = file_dlg_w_st(hwnd, IDS_2118, floppyfns[id], 0);
-				if (! ret)
-					ui_sb_mount_floppy_img(id, part, (item_id == IDM_FLOPPY_IMAGE_EXISTING_WP) ? 1 : 0, wopenfilestring);
-				break;
-
-			case IDM_FLOPPY_EJECT:
-				id = item_params & 0x0003;
-				part = sb_map[SB_FLOPPY | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-						break;
-
-				fdd_close(id);
-				ui_sb_update_icon_state(SB_FLOPPY | id, 1);
-				EnableMenuItem(sb_menu_handles[part], IDM_FLOPPY_EJECT | id, MF_BYCOMMAND | MF_GRAYED);
-				EnableMenuItem(sb_menu_handles[part], IDM_FLOPPY_EXPORT_TO_86F | id, MF_BYCOMMAND | MF_GRAYED);
-				ui_sb_update_tip(SB_FLOPPY | id);
-				config_save();
-				break;
-
-			case IDM_FLOPPY_EXPORT_TO_86F:
-				id = item_params & 0x0003;
-				part = sb_map[SB_FLOPPY | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				ret = file_dlg_w_st(hwnd, IDS_2076, floppyfns[id], 1);
-				if (! ret) {
-					plat_pause(1);
-					ret = d86f_export(id, wopenfilestring);
-					if (!ret)
-						ui_msgbox(MBX_ERROR, (wchar_t *)IDS_4108);
-					plat_pause(0);
-				}
-				break;
-
-			case IDM_CDROM_MUTE:
-				id = item_params & 0x0007;
-				part = sb_map[SB_CDROM | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-						break;
-
-				cdrom[id].sound_on ^= 1;
-				CheckMenuItem(sb_menu_handles[part], IDM_CDROM_MUTE | id, cdrom[id].sound_on ? MF_UNCHECKED : MF_CHECKED);
-				config_save();
-				sound_cd_thread_reset();
-				break;
-
-			case IDM_CDROM_EMPTY:
-				id = item_params & 0x0007;
-				part = sb_map[SB_CDROM | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				cdrom_eject(id);
-				break;
-
-			case IDM_CDROM_RELOAD:
-				id = item_params & 0x0007;
-				part = sb_map[SB_CDROM | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				cdrom_reload(id);
-				break;
-
-			case IDM_CDROM_IMAGE:
-				id = item_params & 0x0007;
-				part = sb_map[SB_CDROM | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				if (!file_dlg_w_st(hwnd, IDS_2075, cdrom[id].image_path, 0)) {
-					cdrom[id].prev_host_drive = cdrom[id].host_drive;
-					wcscpy(temp_path, wopenfilestring);
-					wcscpy(cdrom[id].prev_image_path, cdrom[id].image_path);
-					if (cdrom[id].ops && cdrom[id].ops->exit)
-						cdrom[id].ops->exit(&(cdrom[id]));
-					cdrom[id].ops = NULL;
-					memset(cdrom[id].image_path, 0, sizeof(cdrom[id].image_path));
-					cdrom_image_open(&(cdrom[id]), temp_path);
-					/* Signal media change to the emulated machine. */
-					if (cdrom[id].insert)
-						cdrom[id].insert(cdrom[id].priv);
-					cdrom[id].host_drive = (wcslen(cdrom[id].image_path) == 0) ? 0 : 200;
-					if (cdrom[id].host_drive == 200) {
-						CheckMenuItem(sb_menu_handles[part], IDM_CDROM_EMPTY | id, MF_UNCHECKED);
-						CheckMenuItem(sb_menu_handles[part], IDM_CDROM_IMAGE | id, MF_CHECKED);
-						ui_sb_update_icon_state(SB_CDROM | id, 0);
-					} else {
-						CheckMenuItem(sb_menu_handles[part], IDM_CDROM_IMAGE | id, MF_UNCHECKED);
-						CheckMenuItem(sb_menu_handles[part], IDM_CDROM_EMPTY | id, MF_CHECKED);
-						ui_sb_update_icon_state(SB_CDROM | id, 1);
-					}
-					EnableMenuItem(sb_menu_handles[part], IDM_CDROM_RELOAD | id, MF_BYCOMMAND | MF_GRAYED);
-					ui_sb_update_tip(SB_CDROM | id);
-					config_save();
-				}
-				break;
-
-			case IDM_ZIP_IMAGE_NEW:
-				id = item_params & 0x0003;
-				part = sb_map[SB_ZIP | id];
-				NewFloppyDialogCreate(hwnd, id | 0x80, part);	/* NewZIPDialogCreate */
-				break;
-
-			case IDM_ZIP_IMAGE_EXISTING:
-			case IDM_ZIP_IMAGE_EXISTING_WP:
-				id = item_params & 0x0003;
-				part = sb_map[SB_ZIP | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				ret = file_dlg_w_st(hwnd, IDS_2058, zip_drives[id].image_path, 0);
-				if (! ret)
-					ui_sb_mount_zip_img(id, part, (item_id == IDM_ZIP_IMAGE_EXISTING_WP) ? 1 : 0, wopenfilestring);
-				break;
-
-			case IDM_ZIP_EJECT:
-				id = item_params & 0x0003;
-				zip_eject(id);
-				break;
-
-			case IDM_ZIP_RELOAD:
-				id = item_params & 0x0003;
-				zip_reload(id);
-				break;
-
-			case IDM_MO_IMAGE_NEW:
-				id = item_params & 0x0003;
-				part = sb_map[SB_MO | id];
-				NewFloppyDialogCreate(hwnd, id | 0x80, part);	/* NewZIPDialogCreate */
-				break;
-
-			case IDM_MO_IMAGE_EXISTING:
-			case IDM_MO_IMAGE_EXISTING_WP:
-				id = item_params & 0x0003;
-				part = sb_map[SB_MO | id];
-				if ((part == 0xff) || (sb_menu_handles == NULL))
-					break;
-
-				ret = file_dlg_w_st(hwnd, IDS_2125, mo_drives[id].image_path, 0);
-				if (! ret)
-					ui_sb_mount_mo_img(id, part, (item_id == IDM_MO_IMAGE_EXISTING_WP) ? 1 : 0, wopenfilestring);
-				break;
-
-			case IDM_MO_EJECT:
-				id = item_params & 0x0003;
-				mo_eject(id);
-				break;
-
-			case IDM_MO_RELOAD:
-				id = item_params & 0x0003;
-				mo_reload(id);
-				break;
-
-			default:
-				break;
-		}
+		MediaMenuHandler(hwnd, message, wParam, lParam);
 		return(0);
 
 	case WM_LBUTTONDOWN:
@@ -1148,6 +1222,7 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
     RECT rectDialog;
     int dw, dh;
     uint8_t i;
+    HMENU hmenu;
 
     /* Load our icons into the cache for faster access. */
     for (i = 16; i < 18; i++)
@@ -1219,6 +1294,8 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
      memset(sb_menu_handles, 0, sb_parts * sizeof(HMENU));
     sbTips = (WCHAR **)malloc(sb_parts * sizeof(WCHAR *));
      memset(sbTips, 0, sb_parts * sizeof(WCHAR *));
+    media_menu_handles = (HMENU *)malloc(sb_parts * sizeof(HMENU));
+     memset(media_menu_handles, 0, sb_parts * sizeof(HMENU));
     sb_parts = 0;
     iStatusWidths[sb_parts] = -1;
     sb_part_meanings[sb_parts] = SB_TEXT;
@@ -1227,6 +1304,12 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
     SendMessage(hwndSBAR, SB_SETPARTS, (WPARAM)sb_parts, (LPARAM)iStatusWidths);
     SendMessage(hwndSBAR, SB_SETTEXT, 0 | SBT_NOBORDERS,
 		(LPARAM)L"Welcome to 86Box !");
+
+    hmenu = GetMenu(hwndParent);
+    hmenuMedia = CreatePopupMenu();
+    InsertMenu(hmenu, 2, MF_BYPOSITION | MF_STRING | MF_POPUP, (UINT_PTR)hmenuMedia, plat_get_string(IDS_2126));
+    DrawMenuBar(hwndParent);
+    
     sb_ready = 1;
 }
 
@@ -1245,6 +1328,7 @@ ui_sb_check_menu_item(int tag, int id, int chk)
         return;
 
     CheckMenuItem(sb_menu_handles[part], id, chk);
+    CheckMenuItem(media_menu_handles[part], id, chk);
 }
 
 
@@ -1262,6 +1346,7 @@ ui_sb_enable_menu_item(int tag, int id, int flg)
         return;
 
     EnableMenuItem(sb_menu_handles[part], id, flg);
+    EnableMenuItem(media_menu_handles[part], id, flg);
 }
 
 
diff --git a/src/win/win_ui.c b/src/win/win_ui.c
index 2a9099c3f..cc4240949 100644
--- a/src/win/win_ui.c
+++ b/src/win/win_ui.c
@@ -594,6 +594,9 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
 				svga_dump_vram();
 				break;
 #endif
+			default:
+				MediaMenuHandler(hwnd, message, wParam, lParam);
+				break;
 		}
 		return(0);
 

From 870fdaef3df769b8ff5a402fe9caaa5c239159d6 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 02:22:27 +0200
Subject: [PATCH 19/43] Fixed some warnings in win_jsconf.c.

---
 src/win/win_jsconf.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/src/win/win_jsconf.c b/src/win/win_jsconf.c
index f4269871b..a557f753d 100644
--- a/src/win/win_jsconf.c
+++ b/src/win/win_jsconf.c
@@ -59,7 +59,7 @@ static void rebuild_axis_button_selections(HWND hdlg)
                                 sprintf(s, "%s (Y axis)", plat_joystick_state[joystick-1].pov[d].name);
                                 SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)s);
                         }
-						for (d = 0; d < plat_joystick_state[joystick - 1].nr_sliders; d++)
+			for (d = 0; d < plat_joystick_state[joystick - 1].nr_sliders; d++)
                         {
                                 SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)plat_joystick_state[joystick - 1].slider[d].name);
                         }
@@ -126,8 +126,7 @@ static int get_axis(HWND hdlg, int id)
         HWND h = GetDlgItem(hdlg, id);
         int axis_sel = SendMessage(h, CB_GETCURSEL, 0, 0);
         int nr_axes = plat_joystick_state[joystick_state[joystick_nr].plat_joystick_nr-1].nr_axes;
-		int nr_povs = plat_joystick_state[joystick_state[joystick_nr].plat_joystick_nr - 1].nr_povs;
-        int nr_sliders = plat_joystick_state[joystick_state[joystick_nr].plat_joystick_nr - 1].nr_sliders;
+	int nr_povs = plat_joystick_state[joystick_state[joystick_nr].plat_joystick_nr - 1].nr_povs;
 		
         if (axis_sel < nr_axes)
                 return axis_sel;
@@ -175,7 +174,6 @@ joystickconfig_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
 	int joystick;
 	int nr_axes;
 	int nr_povs;
-	int nr_sliders;
 	int mapping;
 
         switch (message)
@@ -199,7 +197,6 @@ joystickconfig_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
                         {
                                 nr_axes = plat_joystick_state[joystick-1].nr_axes;
                                 nr_povs = plat_joystick_state[joystick-1].nr_povs;
-								nr_sliders = plat_joystick_state[joystick - 1].nr_sliders;
 								
                                 for (c = 0; c < joystick_get_axis_count(joystick_config_type); c++)
                                 {
@@ -211,8 +208,8 @@ joystickconfig_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
                                         else if (mapping & POV_Y)
                                                 SendMessage(h, CB_SETCURSEL, nr_axes + (mapping & 3)*2 + 1, 0);
                                         else if (mapping & SLIDER)
-												SendMessage(h, CB_SETCURSEL, nr_axes + nr_povs * 2 + (mapping & 3), 0);										
-										else
+						SendMessage(h, CB_SETCURSEL, nr_axes + nr_povs * 2 + (mapping & 3), 0);										
+					else
                                                 SendMessage(h, CB_SETCURSEL, mapping, 0);
                                         id += 2;
                                 } 

From e3296f452964d462519868ac9db70a3188634efd Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 02:23:59 +0200
Subject: [PATCH 20/43] Split USB and Distributed DMA into their own files in
 preparation for the overhaul of the VIA southbridges.

---
 src/ddma.c                 | 200 +++++++++++++++++++++++++++++
 src/include/86box/ddma.h   |  56 ++++++++
 src/include/86box/usb.h    |  86 +++++++------
 src/intel_piix.c           | 253 +++----------------------------------
 src/usb.c                  | 196 +++++++++++++++++++++++-----
 src/win/Makefile.mingw     |   6 +-
 src/win/Makefile_ndr.mingw |   6 +-
 7 files changed, 496 insertions(+), 307 deletions(-)
 create mode 100644 src/ddma.c
 create mode 100644 src/include/86box/ddma.h

diff --git a/src/ddma.c b/src/ddma.c
new file mode 100644
index 000000000..98e4da293
--- /dev/null
+++ b/src/ddma.c
@@ -0,0 +1,200 @@
+/*
+ * 86Box	A hypervisor and IBM PC system emulator that specializes in
+ *		running old operating systems and software designed for IBM
+ *		PC systems and compatibles from 1981 through fairly recent
+ *		system designs based on the PCI bus.
+ *
+ *		This file is part of the 86Box distribution.
+ *
+ *		Distributed DMA emulation.
+ *
+ *
+ *
+ * Authors:	Miran Grca, <mgrca8@gmail.com>
+ *
+ *		Copyright 2020 Miran Grca.
+ */
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <wchar.h>
+#define HAVE_STDARG_H
+#include <86box/86box.h>
+#include "cpu.h"
+#include <86box/device.h>
+#include <86box/mem.h>
+#include <86box/io.h>
+#include <86box/pci.h>
+#include <86box/pic.h>
+#include <86box/timer.h>
+#include <86box/keyboard.h>
+#include <86box/nvr.h>
+#include <86box/pit.h>
+#include <86box/dma.h>
+#include <86box/ddma.h>
+
+
+#ifdef ENABLE_DDMA_LOG
+int ddma_do_log = ENABLE_DDMA_LOG;
+
+
+static void
+ddma_log(const char *fmt, ...)
+{
+    va_list ap;
+
+    if (ddma_do_log) {
+	va_start(ap, fmt);
+	pclog_ex(fmt, ap);
+	va_end(ap);
+    }
+}
+#else
+#define ddma_log(fmt, ...)
+#endif
+
+static uint8_t
+ddma_reg_read(uint16_t addr, void *p)
+{
+    ddma_channel_t *dev = (ddma_channel_t *) p;
+    uint8_t ret = 0xff;
+    int ch = dev->channel;
+    int dmab = (ch >= 4) ? 0xc0 : 0x00;
+
+    switch (addr & 0x0f) {
+	case 0x00:
+		ret = dma[ch].ac & 0xff;
+		break;
+	case 0x01:
+		ret = (dma[ch].ac >> 8) & 0xff;
+		break;
+	case 0x02:
+		ret = dma[ch].page;
+		break;
+	case 0x04:
+		ret = dma[ch].cc & 0xff;
+		break;
+	case 0x05:
+		ret = (dma[ch].cc >> 8) & 0xff;
+		break;
+	case 0x09:
+		ret = inb(dmab + 0x08);
+		break;
+    }
+
+    return ret;
+}
+
+
+static void
+ddma_reg_write(uint16_t addr, uint8_t val, void *p)
+{
+    ddma_channel_t *dev = (ddma_channel_t *) p;
+    int ch = dev->channel;
+    int page_regs[4] = { 7, 3, 1, 2 };
+    int i, dmab = (ch >= 4) ? 0xc0 : 0x00;
+
+    switch (addr & 0x0f) {
+	case 0x00:
+		dma[ch].ab = (dma[ch].ab & 0xffff00) | val;
+		dma[ch].ac = dma[ch].ab;
+		break;
+	case 0x01:
+		dma[ch].ab = (dma[ch].ab & 0xff00ff) | (val << 8);
+		dma[ch].ac = dma[ch].ab;
+		break;
+	case 0x02:
+		if (ch >= 4)
+			outb(0x88 + page_regs[ch], val);
+		else
+			outb(0x80 + page_regs[ch], val);
+		break;
+	case 0x04:
+		dma[ch].cb = (dma[ch].cb & 0xffff00) | val;
+		dma[ch].cc = dma[ch].cb;
+		break;
+	case 0x05:
+		dma[ch].cb = (dma[ch].cb & 0xff00ff) | (val << 8);
+		dma[ch].cc = dma[ch].cb;
+		break;
+	case 0x08:
+		outb(dmab + 0x08, val);
+		break;
+	case 0x09:
+		outb(dmab + 0x09, val);
+		break;
+	case 0x0a:
+		outb(dmab + 0x0a, val);
+		break;
+	case 0x0b:
+		outb(dmab + 0x0b, val);
+		break;
+	case 0x0d:
+		outb(dmab + 0x0d, val);
+		break;
+	case 0x0e:
+		for (i = 0; i < 4; i++)
+			outb(dmab + 0x0a, i);
+		break;
+	case 0x0f:
+		outb(dmab + 0x0a, (val << 2) | (ch & 3));
+		break;
+    }
+}
+
+
+void
+ddma_update_io_mapping(ddma_t *dev, int ch, uint8_t base_l, uint8_t base_h, int enable)
+{
+    if (dev->channels[ch].enable && (dev->channels[ch].io_base != 0x0000))
+	io_removehandler(dev->channels[ch].io_base, 0x10, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->channels[ch]);
+
+    dev->channels[ch].io_base = base_l | (base_h << 8);
+    dev->channels[ch].enable = enable;
+
+    if (dev->channels[ch].enable && (dev->channels[ch].io_base != 0x0000))
+	io_sethandler(dev->channels[ch].io_base, 0x10, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->channels[ch]);
+}
+
+
+static void
+ddma_close(void *priv)
+{
+    ddma_t *dev = (ddma_t *) priv;
+
+    free(dev);
+}
+
+
+static void *
+ddma_init(const device_t *info)
+{
+    ddma_t *dev;
+    int i;
+
+    dev = (ddma_t *)malloc(sizeof(ddma_t));
+    if (dev == NULL) return(NULL);
+    memset(dev, 0x00, sizeof(ddma_t));
+
+    for (i = 0; i < 8; i++)
+	dev->channels[i].channel = i;
+
+    return dev;
+}
+
+
+const device_t ddma_device =
+{
+    "Distributed DMA",
+    DEVICE_PCI,
+    0,
+    ddma_init, 
+    ddma_close, 
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
diff --git a/src/include/86box/ddma.h b/src/include/86box/ddma.h
new file mode 100644
index 000000000..2d0a9f8d9
--- /dev/null
+++ b/src/include/86box/ddma.h
@@ -0,0 +1,56 @@
+/*
+ * 86Box	A hypervisor and IBM PC system emulator that specializes in
+ *		running old operating systems and software designed for IBM
+ *		PC systems and compatibles from 1981 through fairly recent
+ *		system designs based on the PCI bus.
+ *
+ *		This file is part of the 86Box distribution.
+ *
+ *		Implementation of the ISA Bus (de)Bugger expansion card
+ *		sold as a DIY kit in the late 1980's in The Netherlands.
+ *		This card was a assemble-yourself 8bit ISA addon card for
+ *		PC and AT systems that had several tools to aid in low-
+ *		level debugging (mostly for faulty BIOSes, bootloaders
+ *		and system kernels...)
+ *
+ *		Definitions for the Distributed DMA emulation.
+ *
+ *
+ *
+ * Authors:	Miran Grca, <mgrca8@gmail.com>
+ *
+ *		Copyright 2020 Miran Grca.
+ */
+#ifndef DDMA_H
+# define DDMA_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+    uint16_t		io_base;
+    int			channel, enable;
+} ddma_channel_t;
+
+typedef struct
+{
+    ddma_channel_t	channels[8];
+} ddma_t;
+
+
+/* Global variables. */
+extern const device_t	ddma_device;
+
+
+/* Functions. */
+extern void		ddma_update_io_mapping(ddma_t *dev, int ch, uint8_t base_l, uint8_t base_h, int enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif	/*DDMA_H*/
diff --git a/src/include/86box/usb.h b/src/include/86box/usb.h
index 69adcf96b..b027796a2 100644
--- a/src/include/86box/usb.h
+++ b/src/include/86box/usb.h
@@ -1,41 +1,55 @@
-/* Copyright holders: Melissa Goad
-   see COPYING for more details
-*/
+/*
+ * 86Box	A hypervisor and IBM PC system emulator that specializes in
+ *		running old operating systems and software designed for IBM
+ *		PC systems and compatibles from 1981 through fairly recent
+ *		system designs based on the PCI bus.
+ *
+ *		This file is part of the 86Box distribution.
+ *
+ *		Implementation of the ISA Bus (de)Bugger expansion card
+ *		sold as a DIY kit in the late 1980's in The Netherlands.
+ *		This card was a assemble-yourself 8bit ISA addon card for
+ *		PC and AT systems that had several tools to aid in low-
+ *		level debugging (mostly for faulty BIOSes, bootloaders
+ *		and system kernels...)
+ *
+ *		Definitions for the Distributed DMA emulation.
+ *
+ *
+ *
+ * Authors:	Miran Grca, <mgrca8@gmail.com>
+ *
+ *		Copyright 2020 Miran Grca.
+ */
+#ifndef USB_H
+# define USB_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 typedef struct
 {
-    uint8_t pid; //low 4 bits are the real pid, top 4 bits are just ~pid
-    uint8_t dev_addr;
-    uint8_t dev_endpoint;
-    int crc5;
-    uint16_t crc16;
-    uint8_t data[1024];
-    int len;
-    void* device;
-} usb_packet_t;
+    uint8_t		ohci_mmio[4096];
+    uint16_t		uhci_io_base;
+    int			uhci_enable, ohci_enable;
+    uint32_t		ohci_mem_base;
+    mem_mapping_t	ohci_mmio_mapping;
+} usb_t;
 
-typedef enum
-{
-    USB_DEV_TYPE_NONE = 0,
-    USB_DEV_TYPE_MOUSE,
-    USB_DEV_TYPE_TABLET,
-    USB_DEV_TYPE_KEYPAD,
-    USB_DEV_TYPE_DISK,
-    USB_DEV_TYPE_CDROM,
-    USB_DEV_TYPE_HUB,
-    USB_DEV_TYPE_PRINTER
-} usb_device_type_t;
 
-typedef enum
-{
-    USB_PID_TOKEN_STALL = 0x1e,
-    USB_PID_TOKEN_SETUP = 0x2d,
-    USB_PID_TOKEN_PRE = 0x3c,
-    USB_PID_TOKEN_DATA1 = 0x4b,
-    USB_PID_TOKEN_NAK = 0x5a,
-    USB_PID_TOKEN_IN = 0x69,
-    USB_PID_TOKEN_SOF = 0xa5,
-    USB_PID_TOKEN_DATA0 = 0xc3,
-    USB_PID_TOKEN_ACK = 0xd2,
-    USB_PID_TOKEN_OUT = 0xe1
-} usb_pid_type_t;
\ No newline at end of file
+/* Global variables. */
+extern const device_t	usb_device;
+
+
+/* Functions. */
+extern void		uhci_update_io_mapping(usb_t *dev, uint8_t base_l, uint8_t base_h, int enable);
+extern void		ohci_update_mem_mapping(usb_t *dev, uint8_t base1, uint8_t base2, uint8_t base3, int enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif	/*USB_H*/
diff --git a/src/intel_piix.c b/src/intel_piix.c
index 8e83e0f0e..33061c4dd 100644
--- a/src/intel_piix.c
+++ b/src/intel_piix.c
@@ -40,6 +40,7 @@
 #include <86box/timer.h>
 #include <86box/nvr.h>
 #include <86box/acpi.h>
+#include <86box/ddma.h>
 #include <86box/pci.h>
 #include <86box/pic.h>
 #include <86box/pit.h>
@@ -47,19 +48,13 @@
 #include <86box/hdc.h>
 #include <86box/hdc_ide.h>
 #include <86box/hdc_ide_sff8038i.h>
+#include <86box/usb.h>
 #include <86box/zip.h>
 #include <86box/machine.h>
 #include <86box/smbus_piix4.h>
 #include <86box/piix.h>
 
 
-typedef struct
-{
-    uint16_t		io_base;
-    int			base_channel;
-} ddma_t;
-
-
 typedef struct
 {
     uint8_t		cur_readout_reg, rev,
@@ -68,15 +63,14 @@ typedef struct
 			regs[4][256],
 			readout_regs[256], board_config[2];
     uint16_t		func0_id, nvr_io_base,
-			usb_io_base, acpi_io_base;
+			acpi_io_base;
     double		fast_off_period;
-    uint8_t		*usb_smsc_mmio;
-    mem_mapping_t	usb_smsc_mmio_mapping;
     sff8038i_t		*bm[2];
-    ddma_t		ddma[2];
     smbus_piix4_t *	smbus;
     apm_t *		apm;
     nvr_t *		nvr;
+    ddma_t *		ddma;
+    usb_t *		usb;
     acpi_t *		acpi;
     port_92_t *		port_92;
     pc_timer_t		fast_off_timer;
@@ -246,200 +240,6 @@ kbc_alias_update_io_mapping(piix_t *dev)
 }
 
 
-static uint8_t
-ddma_reg_read(uint16_t addr, void *p)
-{
-    ddma_t *dev = (ddma_t *) p;
-    uint8_t ret = 0xff;
-    int rel_ch = (addr & 0x30) >> 4;
-    int ch = dev->base_channel + rel_ch;
-    int dmab = (ch >= 4) ? 0xc0 : 0x00;
-
-    switch (addr & 0x0f) {
-	case 0x00:
-		ret = dma[ch].ac & 0xff;
-		break;
-	case 0x01:
-		ret = (dma[ch].ac >> 8) & 0xff;
-		break;
-	case 0x02:
-		ret = dma[ch].page;
-		break;
-	case 0x04:
-		ret = dma[ch].cc & 0xff;
-		break;
-	case 0x05:
-		ret = (dma[ch].cc >> 8) & 0xff;
-		break;
-	case 0x09:
-		ret = inb(dmab + 0x08);
-		break;
-    }
-
-    return ret;
-}
-
-
-static void
-ddma_reg_write(uint16_t addr, uint8_t val, void *p)
-{
-    ddma_t *dev = (ddma_t *) p;
-    int rel_ch = (addr & 0x30) >> 4;
-    int ch = dev->base_channel + rel_ch;
-    int page_regs[4] = { 7, 3, 1, 2 };
-    int i, dmab = (ch >= 4) ? 0xc0 : 0x00;
-
-    switch (addr & 0x0f) {
-	case 0x00:
-		dma[ch].ab = (dma[ch].ab & 0xffff00) | val;
-		dma[ch].ac = dma[ch].ab;
-		break;
-	case 0x01:
-		dma[ch].ab = (dma[ch].ab & 0xff00ff) | (val << 8);
-		dma[ch].ac = dma[ch].ab;
-		break;
-	case 0x02:
-		if (ch >= 4)
-			outb(0x88 + page_regs[rel_ch], val);
-		else
-			outb(0x80 + page_regs[rel_ch], val);
-		break;
-	case 0x04:
-		dma[ch].cb = (dma[ch].cb & 0xffff00) | val;
-		dma[ch].cc = dma[ch].cb;
-		break;
-	case 0x05:
-		dma[ch].cb = (dma[ch].cb & 0xff00ff) | (val << 8);
-		dma[ch].cc = dma[ch].cb;
-		break;
-	case 0x08:
-		outb(dmab + 0x08, val);
-		break;
-	case 0x09:
-		outb(dmab + 0x09, val);
-		break;
-	case 0x0a:
-		outb(dmab + 0x0a, val);
-		break;
-	case 0x0b:
-		outb(dmab + 0x0b, val);
-		break;
-	case 0x0d:
-		outb(dmab + 0x0d, val);
-		break;
-	case 0x0e:
-		for (i = 0; i < 4; i++)
-			outb(dmab + 0x0a, i);
-		break;
-	case 0x0f:
-		outb(dmab + 0x0a, (val << 2) | rel_ch);
-		break;
-    }
-}
-
-
-static void
-ddma_update_io_mapping(piix_t *dev, int n)
-{
-    int base_reg = 0x92 + (n << 1);
-
-    if (dev->ddma[n].io_base != 0x0000)
-	io_removehandler(dev->ddma[n].io_base, 0x40, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->ddma[n]);
-
-    dev->ddma[n].io_base = (dev->regs[0][base_reg] & ~0x3f) | (dev->regs[0][base_reg + 1] << 8);
-
-    if (dev->ddma[n].io_base != 0x0000)
-	io_sethandler(dev->ddma[n].io_base, 0x40, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->ddma[n]);
-}
-
-
-static uint8_t
-usb_reg_read(uint16_t addr, void *p)
-{
-    uint8_t ret = 0xff;
-
-    switch (addr & 0x1f) {
-	case 0x10: case 0x11: case 0x12: case 0x13:
-		/* Port status */
-                ret = 0x00;
-		break;
-    }
-
-    return ret;
-}
-
-
-static void
-usb_reg_write(uint16_t addr, uint8_t val, void *p)
-{
-}
-
-
-static void
-usb_update_io_mapping(piix_t *dev)
-{
-    if (dev->usb_io_base != 0x0000)
-	io_removehandler(dev->usb_io_base, 0x20, usb_reg_read, NULL, NULL, usb_reg_write, NULL, NULL, dev);
-
-    dev->usb_io_base = (dev->regs[2][0x20] & ~0x1f) | (dev->regs[2][0x21] << 8);
-
-    if ((dev->regs[2][PCI_REG_COMMAND] & PCI_COMMAND_IO) && (dev->usb_io_base != 0x0000))
-	io_sethandler(dev->usb_io_base, 0x20, usb_reg_read, NULL, NULL, usb_reg_write, NULL, NULL, dev);
-}
-
-
-static void
-usb_smsc_update_mem_mapping(piix_t *dev)
-{
-    uint32_t usb_bar;
-
-    mem_mapping_disable(&dev->usb_smsc_mmio_mapping);
-
-    usb_bar = ((dev->regs[2][0x11] << 8) | (dev->regs[2][0x12] << 16) | (dev->regs[2][0x13] << 24)) & 0xfffff000;
-
-    if ((dev->regs[2][0x04] & 0x02) && (usb_bar != 0x00000000))
-    	mem_mapping_set_addr(&dev->usb_smsc_mmio_mapping, usb_bar, 0x1000);
-}
-
-
-static uint8_t
-usb_smsc_mmio_read(uint32_t addr, void *p)
-{
-    piix_t *dev = (piix_t *) p;
-    uint8_t ret = 0x00;
-
-    addr &= 0x00000fff;
-
-    ret = dev->usb_smsc_mmio[addr];
-
-    return ret;
-}
-
-
-static void
-usb_smsc_mmio_write(uint32_t addr, uint8_t val, void *p)
-{
-    piix_t *dev = (piix_t *) p;
-
-    addr &= 0x00000fff;
-
-    switch (addr) {
-    	case 0x08: /* HCCOMMANDSTATUS */
-    		/* bit HostControllerReset must be cleared for the controller to be seen as initialized */
-    		val &= ~0x01;
-
-    		/* bit OwnershipChangeRequest triggers an ownership change (SMM <-> OS) */
-    		if (val & 0x0f) {
-    			dev->usb_smsc_mmio[0x0f] = 0x40;
-    			dev->usb_smsc_mmio[0x05] &= ~(dev->usb_smsc_mmio[0x05] & 0x01);
-    		}
-    		break;
-    }
-
-    dev->usb_smsc_mmio[addr] = val;
-}
-
-
 static void
 smbus_update_io_mapping(piix_t *dev)
 {
@@ -480,6 +280,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 {
     piix_t *dev = (piix_t *) priv;
     uint8_t *fregs;
+    int i;
 
     /* Return on unsupported function. */
     if (dev->max_func > 0) {
@@ -643,10 +444,12 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0x92: case 0x93: case 0x94: case 0x95:
 		if (dev->type > 3) {
 			if (addr & 0x01)
-				fregs[addr] = val & 0xc0;
-			else
 				fregs[addr] = val & 0xff;
-			ddma_update_io_mapping(dev, (addr >> 2) & 1);
+			else
+				fregs[addr] = val & 0xc0;
+
+			for (i = 0; i < 4; i++)
+				ddma_update_io_mapping(dev->ddma, (addr & 4) + i, fregs[addr & 0xfe] + (i << 4), fregs[addr | 0x01], 1);
 		}
 		break;
 	case 0xa0:
@@ -886,10 +689,10 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0x04:
 		if (dev->type > 4) {
 			fregs[0x04] = (val & 7);
-			usb_smsc_update_mem_mapping(dev);
+			ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM);
 		} else {
 			fregs[0x04] = (val & 5);
-			usb_update_io_mapping(dev);
+			uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO);
 		}
 		break;
 	case 0x07:
@@ -917,25 +720,25 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0x11:
 		if (dev->type > 4) {
 			fregs[addr] = val & 0xf0;
-			usb_smsc_update_mem_mapping(dev);
+			ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM);
 		}
 		break;
 	case 0x12: case 0x13:
 		if (dev->type > 4) {
 			fregs[addr] = val;
-			usb_smsc_update_mem_mapping(dev);
+			ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM);
 		}
 		break;
 	case 0x20:
 		if (dev->type < 5) {
 			fregs[0x20] = (val & 0xe0) | 1;
-			usb_update_io_mapping(dev);
+			uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO);
 		}
 		break;
 	case 0x21:
 		if (dev->type < 5) {
 			fregs[0x21] = val;
-			usb_update_io_mapping(dev);
+			uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO);
 		}
 		break;
 	case 0x3c:
@@ -1263,14 +1066,6 @@ piix_reset_hard(piix_t *dev)
 		fregs[0xff] = (dev->type > 3) ? 0x10 : 0x00;
 	}
 	dev->max_func = 1;	/* It starts with USB disabled, then enables it. */
-
-	/* SMSC OHCI memory-mapped registers */
-	if (dev->usb_smsc_mmio) {
-		memset(dev->usb_smsc_mmio, 0, 4096);
-		dev->usb_smsc_mmio[0x00] = 0x10;
-		dev->usb_smsc_mmio[0x01] = 0x01;
-		dev->usb_smsc_mmio[0x48] = 0x02;
-	}
     }
 
     /* Function 3: Power Management */
@@ -1394,20 +1189,12 @@ static void
 	dev->acpi = device_add(&acpi_device);
 	acpi_set_slot(dev->acpi, dev->pci_slot);
 	acpi_set_nvr(dev->acpi, dev->nvr);
+
+	dev->ddma = device_add(&ddma_device);
+	dev->usb = device_add(&usb_device);
     } else
 	timer_add(&dev->fast_off_timer, piix_fast_off_count, dev, 0);
 
-    if (dev->type > 4) {
-    	dev->usb_smsc_mmio = (uint8_t *) malloc(4096);
-	memset(dev->usb_smsc_mmio, 0x00, 4096);
-
-    	mem_mapping_add(&dev->usb_smsc_mmio_mapping, 0, 0,
-			usb_smsc_mmio_read,  NULL, NULL,
-			usb_smsc_mmio_write, NULL, NULL,
-			NULL, MEM_MAPPING_EXTERNAL, dev);
-    	mem_mapping_disable(&dev->usb_smsc_mmio_mapping);
-    }
-
     piix_reset_hard(dev);
     piix_log("Maximum function: %i\n", dev->max_func);
     cpu_fast_off_flags = 0x00000000;
diff --git a/src/usb.c b/src/usb.c
index 721289afb..9b04c0383 100644
--- a/src/usb.c
+++ b/src/usb.c
@@ -1,53 +1,185 @@
-/* Copyright holders: Melissa Goad
-   see COPYING for more details
-*/
+/*
+ * 86Box	A hypervisor and IBM PC system emulator that specializes in
+ *		running old operating systems and software designed for IBM
+ *		PC systems and compatibles from 1981 through fairly recent
+ *		system designs based on the PCI bus.
+ *
+ *		This file is part of the 86Box distribution.
+ *
+ *		Universal Serial Bus emulation (currently dummy UHCI and
+ *		OHCI).
+ *
+ *
+ *
+ * Authors:	Miran Grca, <mgrca8@gmail.com>
+ *
+ *		Copyright 2020 Miran Grca.
+ */
+#include <stdarg.h>
 #include <stdio.h>
 #include <stdint.h>
+#include <stdlib.h>
 #include <string.h>
 #include <wchar.h>
+#define HAVE_STDARG_H
+#include <86box/86box.h>
+#include <86box/device.h>
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/usb.h>
 
 
-void *usb_priv[32];
-static int usb_min_card, usb_max_card;
+#ifdef ENABLE_USB_LOG
+int usb_do_log = ENABLE_USB_LOG;
 
 
-void (*usb_packet_handle[32])(usb_packet_t* packet, void *priv);
-
-
-void usb_init(int min_card, int max_card)
+static void
+usb_log(const char *fmt, ...)
 {
-        int c;
-        
-        for (c = 0; c < 32; c++)
-            usb_packet_handle[c] = usb_priv[c] = NULL;
-        
-        usb_min_card = min_card;
-        usb_max_card = max_card;
+    va_list ap;
+
+    if (usb_do_log) {
+	va_start(ap, fmt);
+	pclog_ex(fmt, ap);
+	va_end(ap);
+    }
+}
+#else
+#define usb_log(fmt, ...)
+#endif
+
+
+static uint8_t
+uhci_reg_read(uint16_t addr, void *p)
+{
+    uint8_t ret = 0xff;
+
+    switch (addr & 0x1f) {
+	case 0x10: case 0x11: case 0x12: case 0x13:
+		/* Port status */
+                ret = 0x00;
+		break;
+    }
+
+    return ret;
 }
 
 
-void usb_add_specific(int card, void (*packet_handle)(usb_packet_t *packet, void *priv), void *priv)
+static void
+uhci_reg_write(uint16_t addr, uint8_t val, void *p)
 {
-              usb_packet_handle[card] = packet_handle;
-              usb_priv[card] = priv;
 }
 
 
-void usb_add(void (*packet_handle)(usb_packet_t *packet, void *priv), void *priv)
+void
+uhci_update_io_mapping(usb_t *dev, uint8_t base_l, uint8_t base_h, int enable)
 {
-        int c;
-        
-        for (c = usb_min_card; c <= usb_max_card; c++)
-        {
-                if (!usb_packet_handle[c])
-                {
-                              usb_packet_handle[c] = packet_handle;
-                              usb_priv[c] = priv;
-			// pclog("USB device added to card: %i\n", c);
-                        return;
-                }
-        }
+    if (dev->uhci_enable && (dev->uhci_io_base != 0x0000))
+	io_removehandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, NULL, NULL, dev);
+
+    dev->uhci_io_base = base_l | (base_h << 8);
+    dev->uhci_enable = enable;
+
+    if (dev->uhci_enable && (dev->uhci_io_base != 0x0000))
+	io_sethandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, NULL, NULL, dev);
 }
+
+
+static uint8_t
+ohci_mmio_read(uint32_t addr, void *p)
+{
+    usb_t *dev = (usb_t *) p;
+    uint8_t ret = 0x00;
+
+    addr &= 0x00000fff;
+
+    ret = dev->ohci_mmio[addr];
+
+    return ret;
+}
+
+
+static void
+ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
+{
+    usb_t *dev = (usb_t *) p;
+
+    addr &= 0x00000fff;
+
+    switch (addr) {
+    	case 0x08: /* HCCOMMANDSTATUS */
+    		/* bit HostControllerReset must be cleared for the controller to be seen as initialized */
+    		val &= ~0x01;
+
+    		/* bit OwnershipChangeRequest triggers an ownership change (SMM <-> OS) */
+    		if (val & 0x0f) {
+    			dev->ohci_mmio[0x0f] = 0x40;
+    			dev->ohci_mmio[0x05] &= ~(dev->ohci_mmio[0x05] & 0x01);
+    		}
+    		break;
+    }
+
+    dev->ohci_mmio[addr] = val;
+}
+
+
+void
+ohci_update_mem_mapping(usb_t *dev, uint8_t base1, uint8_t base2, uint8_t base3, int enable)
+{
+    if (dev->ohci_enable && (dev->ohci_mem_base != 0x00000000))
+	mem_mapping_disable(&dev->ohci_mmio_mapping);
+
+    dev->ohci_mem_base = ((base1 << 8) | (base2 << 16) | (base3 << 24)) & 0xfffff000;
+    dev->ohci_enable = enable;
+
+    if (dev->ohci_enable && (dev->ohci_mem_base != 0x00000000))
+    	mem_mapping_set_addr(&dev->ohci_mmio_mapping, dev->ohci_mem_base, 0x1000);
+}
+
+
+static void
+usb_close(void *priv)
+{
+    usb_t *dev = (usb_t *) priv;
+
+    free(dev);
+}
+
+
+static void *
+usb_init(const device_t *info)
+{
+    usb_t *dev;
+
+    dev = (usb_t *)malloc(sizeof(usb_t));
+    if (dev == NULL) return(NULL);
+    memset(dev, 0x00, sizeof(usb_t));
+
+    memset(dev->ohci_mmio, 0x00, 4096);
+    dev->ohci_mmio[0x00] = 0x10;
+    dev->ohci_mmio[0x01] = 0x01;
+    dev->ohci_mmio[0x48] = 0x02;
+
+    mem_mapping_add(&dev->ohci_mmio_mapping, 0, 0,
+		    ohci_mmio_read,  NULL, NULL,
+		    ohci_mmio_write, NULL, NULL,
+		    NULL, MEM_MAPPING_EXTERNAL, dev);
+    mem_mapping_disable(&dev->ohci_mmio_mapping);
+
+    return dev;
+}
+
+
+const device_t usb_device =
+{
+    "Universal Serial Bus",
+    DEVICE_PCI,
+    0,
+    usb_init, 
+    usb_close, 
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index f48318b7d..f8044ddd5 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -512,9 +512,9 @@ CXXFLAGS	:= $(CFLAGS)
 #########################################################################
 #		Create the (final) list of objects to build.		#
 #########################################################################
-MAINOBJ		:= pc.o config.o random.o timer.o io.o acpi.o apm.o dma.o nmi.o \
-		   pic.o pit.o port_92.o ppi.o pci.o mca.o mcr.o mem.o \
-		   rom.o device.o nvr.o nvr_at.o nvr_ps2.o sst_flash.o via_vt82c586b.o \
+MAINOBJ		:= pc.o config.o random.o timer.o io.o acpi.o apm.o dma.o ddma.o \
+		   nmi.o pic.o pit.o port_92.o ppi.o pci.o mca.o mcr.o mem.o rom.o \
+		   usb.o device.o nvr.o nvr_at.o nvr_ps2.o sst_flash.o via_vt82c586b.o \
 		   via_vt82c596b.o $(VNCOBJ)
 
 INTELOBJ	:= intel_flash.o \
diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw
index a5242812d..1a15963e6 100644
--- a/src/win/Makefile_ndr.mingw
+++ b/src/win/Makefile_ndr.mingw
@@ -516,9 +516,9 @@ CXXFLAGS	:= $(CFLAGS)
 #########################################################################
 #		Create the (final) list of objects to build.		#
 #########################################################################
-MAINOBJ		:= pc.o config.o random.o timer.o io.o acpi.o apm.o dma.o nmi.o \
-		   pic.o pit.o port_92.o ppi.o pci.o mca.o mcr.o mem.o \
-		   rom.o device.o nvr.o nvr_at.o nvr_ps2.o sst_flash.o via_vt82c586b.o \
+MAINOBJ		:= pc.o config.o random.o timer.o io.o acpi.o apm.o dma.o ddma.o \
+		   nmi.o pic.o pit.o port_92.o ppi.o pci.o mca.o mcr.o mem.o rom.o \
+		   usb.o device.o nvr.o nvr_at.o nvr_ps2.o sst_flash.o via_vt82c586b.o \
 		   via_vt82c596b.o $(VNCOBJ)
 
 INTELOBJ	:= intel_flash.o \

From 3b85d4f0c7ef0ee1490a2d5583838f4c090baf1a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <dhrdlicka@users.noreply.github.com>
Date: Thu, 23 Apr 2020 12:58:19 +0200
Subject: [PATCH 21/43] win: Add a placeholder menuitem for the Media menu This
 makes it possible to change the position of the menu by only editing the
 resource script itself.

---
 src/include/86box/resource.h |  2 ++
 src/win/86Box.rc             |  1 +
 src/win/win_stbar.c          | 29 +++++++++++++++++++++++------
 3 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/include/86box/resource.h b/src/include/86box/resource.h
index 60990f691..59dc27d0d 100644
--- a/src/include/86box/resource.h
+++ b/src/include/86box/resource.h
@@ -300,6 +300,8 @@
 #define IDM_VID_GRAY_GREEN	40083
 #define IDM_VID_GRAY_WHITE	40084
 
+#define IDM_MEDIA		40085
+
 #ifdef USE_DISCORD
 #define IDM_DISCORD		40090
 #endif
diff --git a/src/win/86Box.rc b/src/win/86Box.rc
index 214dd945a..caba77e71 100644
--- a/src/win/86Box.rc
+++ b/src/win/86Box.rc
@@ -112,6 +112,7 @@ BEGIN
         MENUITEM "CGA/PCjr/Tandy/E&GA/(S)VGA overscan",     IDM_VID_OVERSCAN
         MENUITEM "Change contrast for &monochrome display", IDM_VID_CGACON
     END
+    MENUITEM "&Media",				IDM_MEDIA
     POPUP "&Tools"
     BEGIN
         MENUITEM "&Settings...",                IDM_CONFIG
diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c
index 0dfd7af1d..080afad72 100644
--- a/src/win/win_stbar.c
+++ b/src/win/win_stbar.c
@@ -1215,6 +1215,27 @@ StatusBarProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
 }
 
 
+void
+MediaMenuCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
+{
+    HMENU hmenu;
+    LPWSTR lpMenuName;
+
+    hmenu = GetMenu(hwndParent);
+    hmenuMedia = CreatePopupMenu();
+
+    int len = GetMenuString(hmenu, IDM_MEDIA, NULL, 0, MF_BYCOMMAND);
+    lpMenuName = malloc((len + 1) * sizeof(WCHAR));
+    GetMenuString(hmenu, IDM_MEDIA, lpMenuName, len + 1, MF_BYCOMMAND);
+
+    InsertMenu(hmenu, IDM_MEDIA, MF_BYCOMMAND | MF_STRING | MF_POPUP, (UINT_PTR)hmenuMedia, lpMenuName);
+    RemoveMenu(hmenu, IDM_MEDIA, MF_BYCOMMAND);
+    DrawMenuBar(hwndParent);
+
+    free(lpMenuName);
+}
+
+
 /* API: Create and set up the Status Bar window. */
 void
 StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
@@ -1222,7 +1243,6 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
     RECT rectDialog;
     int dw, dh;
     uint8_t i;
-    HMENU hmenu;
 
     /* Load our icons into the cache for faster access. */
     for (i = 16; i < 18; i++)
@@ -1305,11 +1325,8 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
     SendMessage(hwndSBAR, SB_SETTEXT, 0 | SBT_NOBORDERS,
 		(LPARAM)L"Welcome to 86Box !");
 
-    hmenu = GetMenu(hwndParent);
-    hmenuMedia = CreatePopupMenu();
-    InsertMenu(hmenu, 2, MF_BYPOSITION | MF_STRING | MF_POPUP, (UINT_PTR)hmenuMedia, plat_get_string(IDS_2126));
-    DrawMenuBar(hwndParent);
-    
+    MediaMenuCreate(hwndParent, idStatus, hInst);
+
     sb_ready = 1;
 }
 

From cab0bb845ad375d9f83318161c939ed7c950061f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <dhrdlicka@users.noreply.github.com>
Date: Thu, 23 Apr 2020 13:02:14 +0200
Subject: [PATCH 22/43] win: Move the statusbar initial text to resources

---
 src/include/86box/language.h | 2 +-
 src/win/86Box.rc             | 2 +-
 src/win/win_stbar.c          | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/include/86box/language.h b/src/include/86box/language.h
index 7aa2e17ee..9b3065be9 100644
--- a/src/include/86box/language.h
+++ b/src/include/86box/language.h
@@ -99,7 +99,7 @@
 #define IDS_2123	2123		// "Unable to initialize Ghostscript..."
 #define IDS_2124	2124		// "MO %i (%03i): %ls"
 #define IDS_2125	2125		// "MO images (*.IM?)\0*.IM..."
-#define IDS_2126	2126		// "Media"
+#define IDS_2126	2126		// "Welcome to 86Box!"
 
 #define IDS_4096	4096		// "Hard disk (%s)"
 #define IDS_4097	4097		// "%01i:%01i"
diff --git a/src/win/86Box.rc b/src/win/86Box.rc
index caba77e71..c71fb8b43 100644
--- a/src/win/86Box.rc
+++ b/src/win/86Box.rc
@@ -916,7 +916,7 @@ BEGIN
     IDS_2123	"Unable to initialize Ghostscript, gsdll32.dll is required for automatic convertion of PostScript files to PDF.\n\nAny documents sent to the generic PostScript printer will be saved as PostScript files (.ps)."
     IDS_2124	"MO %i (%03i): %ls"
     IDS_2125	"MO images (*.IM?)\0*.IM?\0All files (*.*)\0*.*\0"
-    IDS_2126	"&Media"
+    IDS_2126	"Welcome to 86Box!"
 END
 
 STRINGTABLE DISCARDABLE 
diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c
index 080afad72..bdbd13f87 100644
--- a/src/win/win_stbar.c
+++ b/src/win/win_stbar.c
@@ -1323,7 +1323,7 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
     sb_parts++;
     SendMessage(hwndSBAR, SB_SETPARTS, (WPARAM)sb_parts, (LPARAM)iStatusWidths);
     SendMessage(hwndSBAR, SB_SETTEXT, 0 | SBT_NOBORDERS,
-		(LPARAM)L"Welcome to 86Box !");
+		(LPARAM)plat_get_string(IDS_2126));
 
     MediaMenuCreate(hwndParent, idStatus, hInst);
 

From 812999f480d27f77d771d386abb995aaa0070c78 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 14:42:32 +0200
Subject: [PATCH 23/43] The PIIX code now also initializes the USB device on
 the PIIX3, fixes #713.

---
 src/intel_piix.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel_piix.c b/src/intel_piix.c
index 33061c4dd..64f5c6c0a 100644
--- a/src/intel_piix.c
+++ b/src/intel_piix.c
@@ -1182,6 +1182,9 @@ static void
     dev->bm[0] = device_add_inst(&sff8038i_device, 1);
     dev->bm[1] = device_add_inst(&sff8038i_device, 2);
 
+    if (dev->type >= 3)
+	dev->usb = device_add(&usb_device);
+
     if (dev->type > 3) {
 	dev->nvr = device_add(&piix4_nvr_device);
 	dev->smbus = device_add(&piix4_smbus_device);
@@ -1191,7 +1194,6 @@ static void
 	acpi_set_nvr(dev->acpi, dev->nvr);
 
 	dev->ddma = device_add(&ddma_device);
-	dev->usb = device_add(&usb_device);
     } else
 	timer_add(&dev->fast_off_timer, piix_fast_off_count, dev, 0);
 

From 8b8ba3d5a797e0269e7bfb7feccefe69db3cf06c Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 15:11:32 +0200
Subject: [PATCH 24/43] IDE sector and sector count now return 0xFF (noise) on
 an unassigned IDE device, fixed TC430HX hanging with empty IDE channels.

---
 src/disk/hdc_ide.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c
index 4b2e46b13..2b6104ee8 100644
--- a/src/disk/hdc_ide.c
+++ b/src/disk/hdc_ide.c
@@ -1815,12 +1815,13 @@ ide_readb(uint16_t addr, void *priv)
 	case 0x2: /* Sector count */
 		if (ide->type == IDE_ATAPI)
 			temp = ide->sc->phase;
-		else
+		else if (ide->type != IDE_NONE)
 			temp = ide->secount;
 		break;
 
 	case 0x3: /* Sector */
-		temp = (uint8_t) ide->sector;
+		if (ide->type != IDE_NONE)
+			temp = (uint8_t) ide->sector;
 		break;
 
 	case 0x4: /* Cylinder low */

From ae36bb093b134d3e99f8c69f49215f9882891877 Mon Sep 17 00:00:00 2001
From: tiseno100 <58827426+tiseno100@users.noreply.github.com>
Date: Thu, 23 Apr 2020 16:57:52 +0300
Subject: [PATCH 25/43] 430VX rework

Make the 430HX & 430VX Phoenix boards available while removed the 596B AMI machine
---
 src/include/86box/machine.h   | 13 ++----
 src/machine/m_at_socket370.c  | 29 ------------
 src/machine/m_at_socket7_s7.c | 86 +++++++++++++++++------------------
 src/machine/machine_table.c   | 38 ++++++++++++----
 4 files changed, 73 insertions(+), 93 deletions(-)

diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h
index 838dc9a0d..c07f74ed7 100644
--- a/src/include/86box/machine.h
+++ b/src/include/86box/machine.h
@@ -287,15 +287,14 @@ extern int	machine_at_acerv35n_init(const machine_t *);
 extern int	machine_at_ap53_init(const machine_t *);
 extern int	machine_at_p55t2p4_init(const machine_t *);
 extern int	machine_at_p55t2s_init(const machine_t *);
+extern int	machine_at_m7shi_init(const machine_t *);
 extern int	machine_at_tc430hx_init(const machine_t *);
-extern int	machine_at_equium5200_init(const machine_t *);	/* Toshiba branded CU430HX.
-								   Works as intended (No need to set an MPU too). */
+extern int	machine_at_equium5200_init(const machine_t *);
 
 extern int	machine_at_p55tvp4_init(const machine_t *);
-extern int	machine_at_i430vx_init(const machine_t *);
 extern int	machine_at_p55va_init(const machine_t *);
-extern int	machine_at_j656vxd_init(const machine_t *);
-extern int	machine_at_mb520n_init(const machine_t *);
+extern int	machine_at_i430vx_init(const machine_t *);
+extern int	machine_at_brio80xx_init(const machine_t *);
 
 extern int	machine_at_p55xb2_init(const machine_t *);
 extern int	machine_at_tx97_init(const machine_t *);
@@ -336,10 +335,6 @@ extern int	machine_at_atc7020bxii_init(const machine_t *);
 extern int	machine_at_63a_init(const machine_t *);
 extern int	machine_at_apas3_init(const machine_t *);
 
-#if defined(DEV_BRANCH) && defined(USE_596B)
-extern int	machine_at_bx98_init(const machine_t *);
-#endif
-
 /* m_at_t3100e.c */
 extern int	machine_at_t3100e_init(const machine_t *);
 
diff --git a/src/machine/m_at_socket370.c b/src/machine/m_at_socket370.c
index 24425793a..009999f07 100644
--- a/src/machine/m_at_socket370.c
+++ b/src/machine/m_at_socket370.c
@@ -199,32 +199,3 @@ machine_at_apas3_init(const machine_t *model)
     return ret;
 }
 
-
-#if defined(DEV_BRANCH) && defined(USE_596B)
-int
-machine_at_bx98_init(const machine_t *model)
-{
-    int ret;
-
-    ret = bios_load_linear(L"roms/machines/bx98/vc98103e.bin",
-			   0x000c0000, 262144, 0);
-
-    if (bios_only || !ret)
-	return ret;
-
-    machine_at_common_init_ex(model, 2);
-
-    pci_init(PCI_CONFIG_TYPE_1);
-    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
-    pci_register_slot(0x01, PCI_CARD_NORMAL, 	  1, 2, 3, 4);
-    device_add(&via_apro_device);
-    device_add(&via_vt82c596b_device);
-    device_add(&um8669f_device);
-    device_add(&keyboard_ps2_ami_pci_device);
-    device_add(&sst_flash_39sf020_device);
-    spd_register(SPD_TYPE_SDRAM, 0x7, 256);
-
-    return ret;
-}
-#endif
diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c
index 9b4a615db..c0314ad88 100644
--- a/src/machine/m_at_socket7_s7.c
+++ b/src/machine/m_at_socket7_s7.c
@@ -302,6 +302,34 @@ machine_at_p55t2s_init(const machine_t *model)
     return ret;
 }
 
+int
+machine_at_m7shi_init(const machine_t *model)
+{
+    int ret;
+
+    ret = bios_load_linear(L"roms/machines/m7shi/m7shi2n.rom",
+			   0x000c0000, 262144, 0);
+
+    if (bios_only || !ret)
+	return ret;
+
+    machine_at_common_init(model);
+
+    pci_init(PCI_CONFIG_TYPE_1);
+    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x12, PCI_CARD_NORMAL, 4, 1, 2, 3);
+    pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
+    pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
+    pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
+    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
+    device_add(&i430vx_device);
+    device_add(&piix3_device);
+    device_add(&keyboard_ps2_ami_pci_device);
+    device_add(&fdc37c932fr_device);
+    device_add(&intel_flash_bxt_device);
+
+    return ret;
+}
 
 int
 machine_at_tc430hx_init(const machine_t *model)
@@ -372,13 +400,12 @@ machine_at_equium5200_init(const machine_t *model) // Information about that mac
     return ret;
 }
 
-
 int
 machine_at_p55tvp4_init(const machine_t *model)
 {
     int ret;
 
-    ret = bios_load_linear(L"roms/machines/p55tvp4/tv5i0204.awd",
+    ret = bios_load_linear(L"roms/machines/p55tvp4/0204_128.BIN",
 			   0x000e0000, 131072, 0);
 
     if (bios_only || !ret)
@@ -388,21 +415,20 @@ machine_at_p55tvp4_init(const machine_t *model)
 
     pci_init(PCI_CONFIG_TYPE_1);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
-    pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
-    pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
     pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
+    pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
+    pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
+	pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
     pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
     device_add(&i430vx_device);
     device_add(&piix3_device);
-    device_add(&keyboard_ps2_pci_device);
+    device_add(&keyboard_ps2_ami_pci_device); //It uses the AMIKEY KBC
     device_add(&w83877f_device);
     device_add(&intel_flash_bxt_device);
 
     return ret;
 }
 
-
 int
 machine_at_i430vx_init(const machine_t *model)
 {
@@ -432,7 +458,6 @@ machine_at_i430vx_init(const machine_t *model)
     return ret;
 }
 
-
 int
 machine_at_p55va_init(const machine_t *model)
 {
@@ -462,14 +487,13 @@ machine_at_p55va_init(const machine_t *model)
     return ret;
 }
 
-
 int
-machine_at_j656vxd_init(const machine_t *model)
+machine_at_brio80xx_init(const machine_t *model)
 {
     int ret;
 
-    ret = bios_load_linear(L"roms/machines/j656vxd/J656VXD.BIN",
-			   0x000e0000, 131072, 0);
+    ret = bios_load_linear(L"roms/machines/brio80xx/Hf0705.rom",
+			   0x000c0000, 262144, 0);
 
     if (bios_only || !ret)
 	return ret;
@@ -477,49 +501,21 @@ machine_at_j656vxd_init(const machine_t *model)
     machine_at_common_init(model);
 
     pci_init(PCI_CONFIG_TYPE_1);
-    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
+    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
+    pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
     pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
-    pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
-    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
-    device_add(&i430vx_device);
-    device_add(&piix3_device);
-    device_add(&keyboard_ps2_pci_device);
-    device_add(&fdc37c669_device);
-    device_add(&intel_flash_bxt_device);
-
-    return ret;
-}
-int
-machine_at_mb520n_init(const machine_t *model)
-{
-    int ret;
-
-    ret = bios_load_linear(L"roms/machines/mb520n/520n503s.rom",
-			   0x000e0000, 131072, 0);
-
-    if (bios_only || !ret)
-	return ret;
-
-    machine_at_common_init(model);
-
-    pci_init(PCI_CONFIG_TYPE_1);
-    pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
-    pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
-    pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
-    pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
-    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
     device_add(&i430vx_device);
     device_add(&piix3_device);
     device_add(&keyboard_ps2_ami_pci_device);
-    device_add(&fdc37c669_device);
+    device_add(&fdc37c932fr_device);
     device_add(&intel_flash_bxt_device);
 
     return ret;
 }
 
-
 int
 machine_at_p55xb2_init(const machine_t *model)
 {
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index ae8f41b08..cd64e4830 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -201,6 +201,7 @@ const machine_t machines[] = {
     { "[486 PCI] Zida Tomato 4DP",		"4dps",			{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  1,  255,   1, 127,		 machine_at_4dps_init, NULL			},
 
     /* Socket 4 machines */
+	//430LX
     { "[Socket 4 LX] IBM Ambra DP60 PCI",	"ambradp60",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	    machine_at_ambradp60_init, NULL			},
 #if defined(DEV_BRANCH) && defined(USE_VPP60)
     { "[Socket 4 LX] IBM PS/ValuePoint P60",	"valuepointp60",	{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  2,  128,   2, 127,	machine_at_valuepointp60_init, NULL			},
@@ -209,10 +210,12 @@ const machine_t machines[] = {
     { "[Socket 4 LX] Micro Star 586MC1",	"586mc1",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  2,  128,   2, 127,	       machine_at_586mc1_init, NULL			},
 
     /* Socket 5 machines */
+	//430NX
     { "[Socket 5 NX] Intel Premiere/PCI II",	"plato",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,		machine_at_plato_init, NULL			},
     { "[Socket 5 NX] IBM Ambra DP90 PCI",	"ambradp90",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	    machine_at_ambradp90_init, NULL			},
     { "[Socket 5 NX] Gigabyte GA-586IP",	"430nx",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,		machine_at_430nx_init, NULL			},
-
+	
+	//430FX
     { "[Socket 5 FX] AMI Apollo",		"apollo",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 127,	       machine_at_apollo_init, NULL			},
 #if defined(DEV_BRANCH) && defined(USE_VECTRA54)
     { "[Socket 5 FX] HP Vectra VL 5 Series 4",  "vectra54",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 511,	     machine_at_vectra54_init, NULL			},
@@ -223,6 +226,7 @@ const machine_t machines[] = {
     { "[Socket 5 FX] President Award 430FX PCI","president",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 127,	    machine_at_president_init, NULL			},
 
     /* Socket 7 machines */
+	//430FX
     { "[Socket 7-3V FX] ASUS P/I-P54TP4XE",	"p54tp4xe",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	     machine_at_p54tp4xe_init, NULL			},
     { "[Socket 7-3V FX] Intel Advanced/ATX",	"thor",			MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,		 machine_at_thor_init, NULL			},
     { "[Socket 7-3V FX] Intel Advanced/EV",	"endeavor",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO,			  8,  128,   8, 127,	     machine_at_endeavor_init, at_endeavor_get_device	},
@@ -231,21 +235,24 @@ const machine_t machines[] = {
 #endif
     { "[Socket 7-3V FX] Packard Bell PB640",	"pb640",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO,	 		  8,  128,   8, 127,		machine_at_pb640_init, at_pb640_get_device	},
 
+	//430HX
     { "[Socket 7-3V HX] Acer M3a",		"acerm3a",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  192,   8, 127,	      machine_at_acerm3a_init, NULL			},
     { "[Socket 7-3V HX] AOpen AP53",		"ap53",			MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 127,		 machine_at_ap53_init, NULL			},    
     { "[Socket 7-3V HX] SuperMicro Super P55T2S","p55t2s",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  768,   8, 127,	       machine_at_p55t2s_init, NULL			},
 
     { "[Socket 7 HX] Acer V35n",		"acerv35n",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  192,   8, 127,	     machine_at_acerv35n_init, NULL			},
     { "[Socket 7 HX] ASUS P/I-P55T2P4",		"p55t2p4",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 127,	      machine_at_p55t2p4_init, NULL			},
+    { "[Socket 7 HX] Micronics M7S-Hi",		"m7shi",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_m7shi_init, NULL			},
     { "[Socket 7 HX] TC430HX",			"tc430hx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 255,	      machine_at_tc430hx_init, NULL			},
     { "[Socket 7 HX] Toshiba Equium 5200D",	"equium5200",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  192,   8, 127,	   machine_at_equium5200_init, NULL			},
 
+	//430VX
     { "[Socket 7 VX] ASUS P/I-P55TVP4",		"p55tvp4",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_p55tvp4_init, NULL			},
-    { "[Socket 7 VX] Epox P55-VA",		"p55va",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 127,		machine_at_p55va_init, NULL			},
-    { "[Socket 7 VX] Jetway J656VXD",		"j656vxd",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 127,	      machine_at_j656vxd_init, NULL			},
-    { "[Socket 7 VX] PC Partner MB520N",	"mb520n",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	       machine_at_mb520n_init, NULL			},
     { "[Socket 7 VX] Shuttle HOT-557",		"430vx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	       machine_at_i430vx_init, NULL			},
+    { "[Socket 7 VX] Epox P55-VA",		"p55va",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 127,		machine_at_p55va_init, NULL			},
+    { "[Socket 7 VX] HP Brio 80xx",			"brio80xx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_brio80xx_init, NULL		},
 
+	//430TX
     { "[Socket 7 TX] ASUS TX97",		"tx97",			MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	         machine_at_tx97_init, NULL			},
     { "[Socket 7 TX] Gigabyte GA-586T2",        "586t2",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_586t2_init, NULL			},
     { "[Socket 7 TX] Intel YM430TX",		"ym430tx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_ym430tx_init, NULL			},
@@ -253,39 +260,50 @@ const machine_t machines[] = {
     { "[Socket 7 TX] PC Partner TXA807DS",	"807ds",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_807ds_init, NULL			},
     { "[Socket 7 TX] SuperMicro P5MMS98",	"p5mms98",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_p5mms98_init, NULL			},
  
+	//Apollo VPX
     { "[Socket 7 VPX] Zida Tomato TX100",	"tx100",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 127,	        machine_at_tx100_init, NULL			},
- 
+
+	//Apollo VP3
     { "[Socket 7 VP3] QDI Advance II",		"advanceii",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	    machine_at_advanceii_init, NULL			},
     
     /* Super Socket 7 machines */
+	//Apollo MVP3
     { "[Super 7 MVP3] AOpen AX59 Pro",		"ax59pro",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8, 1024,  8, 255,	      machine_at_ax59pro_init, NULL			},
     { "[Super 7 MVP3] FIC VA-503+",		"ficva503p",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,  8, 255,	         machine_at_mvp3_init, NULL			},
 
     /* Socket 8 machines */
+	//440FX
     { "[Socket 8 FX] Gigabyte GA-686NX",	"686nx",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	        machine_at_686nx_init, NULL			},
     { "[Socket 8 FX] PC Partner MB600N",	"mb600n",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	       machine_at_mb600n_init, NULL			},
     { "[Socket 8 FX] Biostar MB-8500ttc",	"8500ttc",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	      machine_at_8500ttc_init, NULL			},
     { "[Socket 8 FX] Micronics M6MI",		"m6mi",			{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	         machine_at_m6mi_init, NULL			},
 
     /* Slot 1 machines */
+	//440FX
     { "[Slot 1 FX] ECS P6KFX-A",		"p6kfx",		{{"Intel", cpus_PentiumII_28v},{"",    NULL},        {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	        machine_at_p6kfx_init, NULL			},
 
+	//440LX
+	
+	
+	//440BX
     { "[Slot 1 BX] Gigabyte GA-6BXC",		"6bxc",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		 machine_at_6bxc_init, NULL			},
     { "[Slot 1 BX] ASUS P2B-LS",		"p2bls",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		machine_at_p2bls_init, NULL			},
     { "[Slot 1 BX] ASUS P3B-F",			"p3bf",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_p3bf_init, NULL			},
     { "[Slot 1 BX] ABit BF6",			"bf6",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		  machine_at_bf6_init, NULL			},
 
+	//440ZX
     { "[Slot 1 ZX] Packard Bell Bora Pro",	"borapro",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 255,	      machine_at_borapro_init, NULL			},
 
     /* PGA370 machines */
+	//440BX
     { "[Socket 370 BX] ASUS CUBX",		"cubx",			{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_cubx_init, NULL			},
     { "[Socket 370 BX] A-Trend ATC7020BXII",	"atc7020bxii",		{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,	  machine_at_atc7020bxii_init, NULL			},
-    { "[Socket 370 ZX] Soltek SL-63A1",		"63a",			{{"Intel", cpus_Celeron},     {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 255,		  machine_at_63a_init, NULL			},
-    { "[Socket 370 APRO] PC Partner APAS3",	"apas3",		{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,	  				  8, 1024,   8, 255,            machine_at_apas3_init, NULL			},
 
-#if defined(DEV_BRANCH) && defined(USE_596B)
-    { "[Socket 370 APRO] Zida Tomato BX98",	"bx98",			{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,	  				  8, 1024,   8, 255,		 machine_at_bx98_init, NULL			},
-#endif
+	//440ZX
+    { "[Socket 370 ZX] Soltek SL-63A1",		"63a",			{{"Intel", cpus_Celeron},     {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 255,		  machine_at_63a_init, NULL			},
+
+	//VIA Apollo Pro
+    { "[Socket 370 APRO] PC Partner APAS3",	"apas3",		{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,	  				  8, 1024,   8, 255,            machine_at_apas3_init, NULL			},
 
     { NULL,					NULL,			{{"",      0},                {"",    0},            {"",      0},           {"",         0},     {"",      0}},    0,                                                                                                    0,    0,   0,   0,			         NULL, NULL			}
 };

From 9c6493a6f8765081bafeb3d2051a4ea180fbeb36 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 17:49:04 +0200
Subject: [PATCH 26/43] Fixed the two new Phoenix machines by switching their
 Super I/O chips to SMC FDC73C935 (it's really 932/935 without additional
 letters), fixing some things in said Super I/O chips, and giving the HP Brio
 80xx the correct (SST 29EE020) Flash chip.

---
 src/machine/m_at_socket7_s7.c |  9 +++++----
 src/machine/machine_table.c   |  2 +-
 src/sio_fdc37c93x.c           | 14 ++++++++++++++
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c
index c0314ad88..5dbd00b48 100644
--- a/src/machine/m_at_socket7_s7.c
+++ b/src/machine/m_at_socket7_s7.c
@@ -322,10 +322,10 @@ machine_at_m7shi_init(const machine_t *model)
     pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
     pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    device_add(&i430vx_device);
+    device_add(&i430hx_device);
     device_add(&piix3_device);
     device_add(&keyboard_ps2_ami_pci_device);
-    device_add(&fdc37c932fr_device);
+    device_add(&fdc37c935_device);
     device_add(&intel_flash_bxt_device);
 
     return ret;
@@ -510,8 +510,9 @@ machine_at_brio80xx_init(const machine_t *model)
     device_add(&i430vx_device);
     device_add(&piix3_device);
     device_add(&keyboard_ps2_ami_pci_device);
-    device_add(&fdc37c932fr_device);
-    device_add(&intel_flash_bxt_device);
+    device_add(&fdc37c935_device);
+    // device_add(&intel_flash_bxt_device);
+    device_add(&sst_flash_29ee020_device);
 
     return ret;
 }
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index cd64e4830..b116a452a 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -242,7 +242,7 @@ const machine_t machines[] = {
 
     { "[Socket 7 HX] Acer V35n",		"acerv35n",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  192,   8, 127,	     machine_at_acerv35n_init, NULL			},
     { "[Socket 7 HX] ASUS P/I-P55T2P4",		"p55t2p4",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 127,	      machine_at_p55t2p4_init, NULL			},
-    { "[Socket 7 HX] Micronics M7S-Hi",		"m7shi",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_m7shi_init, NULL			},
+    { "[Socket 7 HX] Micronics M7S-Hi",		"m7shi",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 511,	        machine_at_m7shi_init, NULL			},
     { "[Socket 7 HX] TC430HX",			"tc430hx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 255,	      machine_at_tc430hx_init, NULL			},
     { "[Socket 7 HX] Toshiba Equium 5200D",	"equium5200",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  192,   8, 127,	   machine_at_equium5200_init, NULL			},
 
diff --git a/src/sio_fdc37c93x.c b/src/sio_fdc37c93x.c
index e5ed9e164..7e08ab373 100644
--- a/src/sio_fdc37c93x.c
+++ b/src/sio_fdc37c93x.c
@@ -393,6 +393,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
 				fdc37c93x_serial_handler(dev, 0);
 			if (valxor & 0x20)
 				fdc37c93x_serial_handler(dev, 1);
+			if ((valxor & 0x40) && (dev->chip_id != 0x02))
+				fdc37c932fr_access_bus_handler(dev);
 			break;
 	}
 
@@ -406,6 +408,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
 			case 0x30:
 			case 0x60:
 			case 0x61:
+				if ((dev->cur_reg == 0x30) && (val & 0x01))
+					dev->regs[0x22] |= 0x01;
 				if (valxor)
 					fdc37c93x_fdc_handler(dev);
 				break;
@@ -454,6 +458,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
 			case 0x60:
 			case 0x61:
 			case 0x70:
+				if ((dev->cur_reg == 0x30) && (val & 0x01))
+					dev->regs[0x22] |= 0x08;
 				if (valxor)
 					fdc37c93x_lpt_handler(dev);
 				break;
@@ -466,6 +472,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
 			case 0x60:
 			case 0x61:
 			case 0x70:
+				if ((dev->cur_reg == 0x30) && (val & 0x01))
+					dev->regs[0x22] |= 0x10;
 				if (valxor)
 					fdc37c93x_serial_handler(dev, 0);
 				break;
@@ -478,6 +486,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
 			case 0x60:
 			case 0x61:
 			case 0x70:
+				if ((dev->cur_reg == 0x30) && (val & 0x01))
+					dev->regs[0x22] |= 0x20;
 				if (valxor)
 					fdc37c93x_serial_handler(dev, 1);
 				break;
@@ -556,6 +566,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
 			case 0x60:
 			case 0x61:
 			case 0x70:
+				if ((dev->cur_reg == 0x30) && (val & 0x01))
+					dev->regs[0x22] |= 0x40;
 				if (valxor)
 					fdc37c932fr_access_bus_handler(dev);
 				break;
@@ -757,6 +769,8 @@ fdc37c93x_init(const device_t *info)
     if (dev->chip_id == 0x03)
 	dev->access_bus = device_add(&access_bus_device);
 
+    io_sethandler(0x370, 0x0002,
+		  fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
     io_sethandler(0x3f0, 0x0002,
 		  fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
 

From d042939600dfa494af5d305c5109db0030be2b34 Mon Sep 17 00:00:00 2001
From: tiseno100 <58827426+tiseno100@users.noreply.github.com>
Date: Thu, 23 Apr 2020 20:17:18 +0300
Subject: [PATCH 27/43] Added the Packard Bell PB680

Intel AMI based board. To cover up the needs for an AMI BIOS on 430VX
---
 src/include/86box/machine.h   |  1 +
 src/machine/m_at_socket7_s7.c | 33 +++++++++++++++++++++++++++++++++
 src/machine/machine_table.c   |  1 +
 3 files changed, 35 insertions(+)

diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h
index c07f74ed7..b24bbcff1 100644
--- a/src/include/86box/machine.h
+++ b/src/include/86box/machine.h
@@ -295,6 +295,7 @@ extern int	machine_at_p55tvp4_init(const machine_t *);
 extern int	machine_at_p55va_init(const machine_t *);
 extern int	machine_at_i430vx_init(const machine_t *);
 extern int	machine_at_brio80xx_init(const machine_t *);
+extern int	machine_at_pb680_init(const machine_t *);
 
 extern int	machine_at_p55xb2_init(const machine_t *);
 extern int	machine_at_tx97_init(const machine_t *);
diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c
index 5dbd00b48..702f7d9d3 100644
--- a/src/machine/m_at_socket7_s7.c
+++ b/src/machine/m_at_socket7_s7.c
@@ -517,6 +517,39 @@ machine_at_brio80xx_init(const machine_t *model)
     return ret;
 }
 
+int
+machine_at_pb680_init(const machine_t *model)
+{
+    int ret;
+
+    ret = bios_load_linear_combined2(L"roms/machines/pb680/1012DN0R.BIO",
+				     L"roms/machines/pb680/1012DN0R.BI1",
+				     L"roms/machines/pb680/1012DN0R.BI2",
+				     L"roms/machines/pb680/1012DN0R.BI3",
+				     L"roms/machines/pb680/1012DN0R.RCV",
+				     0x3a000, 128);
+
+    if (bios_only || !ret)
+	return ret;
+
+    machine_at_common_init(model);
+
+    pci_init(PCI_CONFIG_TYPE_1);
+    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
+    pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
+    pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
+    pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
+    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    device_add(&i430vx_device);
+    device_add(&piix3_device);
+    device_add(&keyboard_ps2_ami_pci_device);
+    device_add(&pc87306_device);
+    device_add(&intel_flash_bxt_ami_device);
+
+    return ret;
+}
+
 int
 machine_at_p55xb2_init(const machine_t *model)
 {
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index b116a452a..c00091cbb 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -251,6 +251,7 @@ const machine_t machines[] = {
     { "[Socket 7 VX] Shuttle HOT-557",		"430vx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	       machine_at_i430vx_init, NULL			},
     { "[Socket 7 VX] Epox P55-VA",		"p55va",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 127,		machine_at_p55va_init, NULL			},
     { "[Socket 7 VX] HP Brio 80xx",			"brio80xx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_brio80xx_init, NULL		},
+    { "[Socket 7 VX] Packard Bell PB680",	"pb680",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_pb680_init, NULL		},
 
 	//430TX
     { "[Socket 7 TX] ASUS TX97",		"tx97",			MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	         machine_at_tx97_init, NULL			},

From e132bf21e36bc818463296e46055cafff2c2382b Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Thu, 23 Apr 2020 20:15:20 +0200
Subject: [PATCH 28/43] Simplified memory handler for the wd80x3 nic family.

---
 src/network/net_wd8003.c | 87 ++++++++--------------------------------
 1 file changed, 17 insertions(+), 70 deletions(-)

diff --git a/src/network/net_wd8003.c b/src/network/net_wd8003.c
index 953212a0b..7eeb4d136 100644
--- a/src/network/net_wd8003.c
+++ b/src/network/net_wd8003.c
@@ -175,68 +175,22 @@ wd_soft_reset(void *priv)
 }
 
 
-static uint32_t
-wd_ram_read(uint32_t addr, unsigned len, void *priv)
-{
-    wd_t *dev = (wd_t *)priv;
-    uint32_t ret;
-    uint16_t ram_mask = dev->ram_size - 1;
-
-    ret = dev->dp8390->mem[addr & ram_mask];
-
-    if (len == 2)
-	ret |= dev->dp8390->mem[(addr + 1) & ram_mask] << 8;
-
-    return ret;	
-}
-
-
 static uint8_t
-wd_ram_readb(uint32_t addr, void *priv)
+wd_ram_read(uint32_t addr, void *priv)
 {
     wd_t *dev = (wd_t *)priv;
-
-    return wd_ram_read(addr, 1, dev);
+	
+    wdlog("WD80x3: RAM Read: addr=%06x, val=%02x\n", addr & (dev->ram_size - 1), dev->dp8390->mem[addr & (dev->ram_size - 1)]);
+    return dev->dp8390->mem[addr & (dev->ram_size - 1)];
 }
 
-
-static uint16_t
-wd_ram_readw(uint32_t addr, void *priv)
-{
-    wd_t *dev = (wd_t *)priv;
-
-    return wd_ram_read(addr, 2, dev);
-}
-
-
 static void
-wd_ram_write(uint32_t addr, uint32_t val, unsigned len, void *priv)
+wd_ram_write(uint32_t addr, uint8_t val, void *priv)
 {
     wd_t *dev = (wd_t *)priv;
-    uint16_t ram_mask = dev->ram_size - 1;
-
-    dev->dp8390->mem[addr & ram_mask] = val & 0xff;
-
-    if (len == 2)
-	dev->dp8390->mem[(addr + 1) & ram_mask] = val >> 8;
-}
-
-
-static void
-wd_ram_writeb(uint32_t addr, uint8_t val, void *priv)
-{
-    wd_t *dev = (wd_t *)priv;
-
-    wd_ram_write(addr, val, 1, dev);
-}
-
-
-static void
-wd_ram_writew(uint32_t addr, uint16_t val, void *priv)
-{
-    wd_t *dev = (wd_t *)priv;
-
-    wd_ram_write(addr, val, 2, dev);
+    
+    dev->dp8390->mem[addr & (dev->ram_size - 1)] = val;
+    wdlog("WD80x3: RAM Write: addr=%06x, val=%02x\n", addr & (dev->ram_size - 1), val);
 }
 
 
@@ -605,7 +559,7 @@ wd_mca_write(int port, uint8_t val, void *priv)
      * So, remove current address, if any.
      */
     if (dev->base_address)
-	wd_io_remove(dev, dev->base_address);	
+	wd_io_remove(dev, dev->base_address);
 
     dev->base_address = (dev->pos_regs[2] & 0xfe) << 4;
     dev->ram_addr = (dev->pos_regs[3] & 0xfc) << 12;
@@ -685,7 +639,7 @@ wd_init(const device_t *info)
     dev->dp8390 = device_add(&dp8390_device);
     dev->dp8390->priv = dev;
     dev->dp8390->interrupt = wd_interrupt;
-    dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CLEAR_IRQ);
+    dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
 
     switch(dev->board) {
 	/* Ethernet, ISA, no interface chip, RAM 8k */
@@ -748,25 +702,18 @@ wd_init(const device_t *info)
     memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal));
 
     wdlog("%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
-	  dev->name, dev->base_address, dev->irq,
-	  dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2],
-	  dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]);
+	dev->name, dev->base_address, dev->irq,
+	dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2],
+	dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]);
 
     /* Reset the board. */
     wd_reset(dev);
 
     /* Map this system into the memory map. */
-    if (dev->bit16 & 1) {
-	mem_mapping_add(&dev->ram_mapping, dev->ram_addr, dev->ram_size,
-			wd_ram_readb, wd_ram_readw, NULL,
-			wd_ram_writeb, wd_ram_writew, NULL,
-			NULL, MEM_MAPPING_EXTERNAL, dev);
-    } else {
-	mem_mapping_add(&dev->ram_mapping, dev->ram_addr, dev->ram_size,
-			wd_ram_readb, NULL, NULL,
-			wd_ram_writeb, NULL, NULL,
-			NULL, MEM_MAPPING_EXTERNAL, dev);
-    }
+    mem_mapping_add(&dev->ram_mapping, dev->ram_addr, dev->ram_size,
+	wd_ram_read, NULL, NULL,
+	wd_ram_write, NULL, NULL,
+	NULL, MEM_MAPPING_EXTERNAL, dev);
 
     mem_mapping_disable(&dev->ram_mapping);		
 

From 191687e5ac130e5b5274efaa23992ab080a81008 Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Thu, 23 Apr 2020 20:19:40 +0200
Subject: [PATCH 29/43] Hopefully fixed the dp8390 side of the wd80x3.

---
 src/network/net_dp8390.c | 24 ++++++------------------
 1 file changed, 6 insertions(+), 18 deletions(-)

diff --git a/src/network/net_dp8390.c b/src/network/net_dp8390.c
index 376b4dc51..892101976 100644
--- a/src/network/net_dp8390.c
+++ b/src/network/net_dp8390.c
@@ -204,11 +204,8 @@ dp8390_write_cr(dp8390_t *dev, uint32_t val)
     /* Check for start-tx */
     if ((val & 0x04) && dev->TCR.loop_cntl) {
 	if (dev->TCR.loop_cntl) {
-	    if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC))
-		dp8390_rx(dev, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start],
-		    dev->tx_bytes);
-	    else
-		dp8390_rx(dev, dev->mem, dev->tx_bytes);
+	    dp8390_rx(dev, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start],
+		dev->tx_bytes);
 	}
     } else if (val & 0x04) {
 	if (dev->CR.stop || (!dev->CR.start && (dev->flags & DP8390_FLAG_CHECK_CR))) {
@@ -226,11 +223,8 @@ dp8390_write_cr(dp8390_t *dev, uint32_t val)
 
 	/* Send the packet to the system driver */
 	dev->CR.tx_packet = 1;
-
-	if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC))
-	    network_tx(&dev->mem[(dev->tx_page_start * 256) - dev->mem_start], dev->tx_bytes);
-	else
-	    network_tx(dev->mem, dev->tx_bytes);
+	
+	network_tx(&dev->mem[(dev->tx_page_start * 256) - dev->mem_start], dev->tx_bytes);
 
 	/* some more debug */
 #ifdef ENABLE_DP8390_LOG
@@ -394,10 +388,7 @@ dp8390_rx(void *priv, uint8_t *buf, int io_len)
 	       pkthdr[0], pkthdr[1], pkthdr[2], pkthdr[3]);
 
     /* Copy into buffer, update curpage, and signal interrupt if config'd */
-    if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC))
-	startptr = &dev->mem[(dev->curr_page * 256) - dev->mem_start];
-    else
-	startptr = dev->mem + ((dev->curr_page * 256) - dev->mem_start);
+    startptr = &dev->mem[(dev->curr_page * 256) - dev->mem_start];
     memcpy(startptr, pkthdr, sizeof(pkthdr));
     if ((nextpage > dev->curr_page) ||
 	((dev->curr_page + pages) == dev->page_stop)) {
@@ -405,10 +396,7 @@ dp8390_rx(void *priv, uint8_t *buf, int io_len)
     } else {
 	endbytes = (dev->page_stop - dev->curr_page) * 256;
 	memcpy(startptr+sizeof(pkthdr), buf, endbytes-sizeof(pkthdr));
-	if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC))
-	    startptr = &dev->mem[(dev->page_start * 256) - dev->mem_start];
-	else
-	    startptr = dev->mem + ((dev->page_start * 256) - dev->mem_start);
+	startptr = &dev->mem[(dev->page_start * 256) - dev->mem_start];
 	memcpy(startptr, buf+endbytes-sizeof(pkthdr), io_len-endbytes+8);
     }
     dev->curr_page = nextpage;

From e42a99cc0e129c7f56e88a6cb82d6b8915066852 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 20:57:13 +0200
Subject: [PATCH 30/43] Added a PCI APM device that has a reset function that
 clears and status back to 0x00 on device reset, fixes soft reset hangs on the
 ASUS P/I-P55TVP4, and also made it clear that the TC430HX is Intel.

---
 src/apm.c                   | 57 +++++++++++++++++++++++++++----------
 src/include/86box/apm.h     |  3 +-
 src/intel_piix.c            |  6 ++--
 src/machine/machine_table.c |  2 +-
 src/pci.c                   |  1 -
 5 files changed, 48 insertions(+), 21 deletions(-)

diff --git a/src/apm.c b/src/apm.c
index 59f8e40e2..b197c0964 100644
--- a/src/apm.c
+++ b/src/apm.c
@@ -49,43 +49,55 @@ apm_log(const char *fmt, ...)
 
 
 void
-apm_set_do_smi(apm_t *apm, uint8_t do_smi)
+apm_set_do_smi(apm_t *dev, uint8_t do_smi)
 {
-    apm->do_smi = do_smi;
+    dev->do_smi = do_smi;
 }
 
 
 static void
 apm_out(uint16_t port, uint8_t val, void *p)
 {
-    apm_t *apm = (apm_t *) p;
+    apm_t *dev = (apm_t *) p;
 
     apm_log("[%04X:%08X] APM write: %04X = %02X (BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, BX, CX);
 
     port &= 0x0001;
 
     if (port == 0x0000) {
-	apm->cmd = val;
-	if (apm->do_smi)
+	dev->cmd = val;
+	if (dev->do_smi)
     		smi_line = 1;
     } else
-	apm->stat = val;
+	dev->stat = val;
 }
 
 
 static uint8_t
 apm_in(uint16_t port, void *p)
 {
-    apm_t *apm = (apm_t *) p;
-
-    apm_log("[%04X:%08X] APM read: %04X = FF\n", CS, cpu_state.pc, port);
+    apm_t *dev = (apm_t *) p;
+    uint8_t ret = 0xff;
 
     port &= 0x0001;
 
     if (port == 0x0000)
-	return apm->cmd;
+	ret = dev->cmd;
     else
-	return apm->stat;
+	ret = dev->stat;
+
+    apm_log("[%04X:%08X] APM read: %04X = %02X\n", CS, cpu_state.pc, port, ret);
+
+    return ret;
+}
+
+
+static void
+apm_reset(void *p)
+{
+    apm_t *dev = (apm_t *)p;
+
+    dev->cmd = dev->stat = 0x00;
 }
 
 
@@ -101,12 +113,12 @@ apm_close(void *p)
 static void
 *apm_init(const device_t *info)
 {
-    apm_t *apm = (apm_t *) malloc(sizeof(apm_t));
-    memset(apm, 0, sizeof(apm_t));
+    apm_t *dev = (apm_t *) malloc(sizeof(apm_t));
+    memset(dev, 0, sizeof(apm_t));
 
-    io_sethandler(0x00b2, 0x0002, apm_in, NULL, NULL, apm_out, NULL, NULL, apm);
+    io_sethandler(0x00b2, 0x0002, apm_in, NULL, NULL, apm_out, NULL, NULL, dev);
 
-    return apm;
+    return dev;
 }
 
 
@@ -123,3 +135,18 @@ const device_t apm_device =
     NULL,
     NULL
 };
+
+
+const device_t apm_pci_device =
+{
+    "Advanced Power Management (PCI)",
+    DEVICE_PCI,
+    0,
+    apm_init,
+    apm_close, 
+    apm_reset,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
diff --git a/src/include/86box/apm.h b/src/include/86box/apm.h
index e420ec717..b7754f78a 100644
--- a/src/include/86box/apm.h
+++ b/src/include/86box/apm.h
@@ -38,10 +38,11 @@ typedef struct
 
 /* Global variables. */
 extern const device_t	apm_device;
+extern const device_t	apm_pci_device;
 
 
 /* Functions. */
-extern void		apm_set_do_smi(apm_t *apm, uint8_t do_smi);
+extern void		apm_set_do_smi(apm_t *dev, uint8_t do_smi);
 
 #ifdef __cplusplus
 }
diff --git a/src/intel_piix.c b/src/intel_piix.c
index 64f5c6c0a..257b9be9a 100644
--- a/src/intel_piix.c
+++ b/src/intel_piix.c
@@ -455,7 +455,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0xa0:
 		if (dev->type < 4) {
 			fregs[addr] = val & 0x1f;
-			apm_set_do_smi(dev->apm, (val & 0x01) | (fregs[0xa2] & 0x80));
+			apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(fregs[0xa2] & 0x80));
 			switch ((val & 0x18) >> 3) {
 				case 0x00:
 					dev->fast_off_period = PCICLK * 32768.0 * 60000.0;
@@ -480,7 +480,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0xa2:
 		if (dev->type < 4) {
 			fregs[addr] = val & 0xff;
-			apm_set_do_smi(dev->apm, (fregs[0xa0] & 0x01) | (val & 0x80));
+			apm_set_do_smi(dev->apm, !!(fregs[0xa0] & 0x01) && !!(val & 0x80));
 		}
 		break;
 	case 0xaa: case 0xac: case 0xae:
@@ -1206,7 +1206,7 @@ static void
     } else
 	cpu_fast_off_val = cpu_fast_off_count = 0;
 
-    dev->apm = device_add(&apm_device);
+    dev->apm = device_add(&apm_pci_device);
     /* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */
     io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev);
     dev->port_92 = device_add(&port_92_pci_device);
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index c00091cbb..b358fde33 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -243,7 +243,7 @@ const machine_t machines[] = {
     { "[Socket 7 HX] Acer V35n",		"acerv35n",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  192,   8, 127,	     machine_at_acerv35n_init, NULL			},
     { "[Socket 7 HX] ASUS P/I-P55T2P4",		"p55t2p4",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 127,	      machine_at_p55t2p4_init, NULL			},
     { "[Socket 7 HX] Micronics M7S-Hi",		"m7shi",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 511,	        machine_at_m7shi_init, NULL			},
-    { "[Socket 7 HX] TC430HX",			"tc430hx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 255,	      machine_at_tc430hx_init, NULL			},
+    { "[Socket 7 HX] Intel TC430HX",		"tc430hx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 255,	      machine_at_tc430hx_init, NULL			},
     { "[Socket 7 HX] Toshiba Equium 5200D",	"equium5200",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  192,   8, 127,	   machine_at_equium5200_init, NULL			},
 
 	//430VX
diff --git a/src/pci.c b/src/pci.c
index f0b411d71..1e142a554 100644
--- a/src/pci.c
+++ b/src/pci.c
@@ -710,7 +710,6 @@ void
 trc_write(uint16_t port, uint8_t val, void *priv)
 {
     pci_log("TRC Write: %02X\n", val);
-    pci_log("TRC Write: %02X\n", val);
 
     if (!(trc_reg & 4) && (val & 4))
 	trc_reset(val);

From 746175e3976614168afa733d17704b1c4956dfc3 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 23 Apr 2020 23:10:13 +0200
Subject: [PATCH 31/43] Fixed the PB680 PCI slots.

---
 src/machine/m_at_socket7_s7.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c
index 702f7d9d3..4eb1f963b 100644
--- a/src/machine/m_at_socket7_s7.c
+++ b/src/machine/m_at_socket7_s7.c
@@ -511,7 +511,6 @@ machine_at_brio80xx_init(const machine_t *model)
     device_add(&piix3_device);
     device_add(&keyboard_ps2_ami_pci_device);
     device_add(&fdc37c935_device);
-    // device_add(&intel_flash_bxt_device);
     device_add(&sst_flash_29ee020_device);
 
     return ret;
@@ -536,7 +535,7 @@ machine_at_pb680_init(const machine_t *model)
 
     pci_init(PCI_CONFIG_TYPE_1);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
+    pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
     pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
     pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
     pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);

From 3942f97a1a291d563cfef5ef7a8ab36c950cf646 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Fri, 24 Apr 2020 00:36:49 +0200
Subject: [PATCH 32/43] Removed the AMI Apollo.

---
 src/include/86box/machine.h  |  1 -
 src/machine/m_at_socket4_5.c | 31 -------------------------
 src/machine/machine_table.c  | 44 +++++++++++++++++-------------------
 3 files changed, 21 insertions(+), 55 deletions(-)

diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h
index b24bbcff1..7e51ab210 100644
--- a/src/include/86box/machine.h
+++ b/src/include/86box/machine.h
@@ -265,7 +265,6 @@ extern int	machine_at_endeavor_init(const machine_t *);
 extern int	machine_at_zappa_init(const machine_t *);
 extern int	machine_at_mb500n_init(const machine_t *);
 extern int	machine_at_president_init(const machine_t *);
-extern int	machine_at_apollo_init(const machine_t *);
 #if defined(DEV_BRANCH) && defined(USE_VECTRA54)
 extern int	machine_at_vectra54_init(const machine_t *);
 #endif
diff --git a/src/machine/m_at_socket4_5.c b/src/machine/m_at_socket4_5.c
index b86c3fe4b..81dcb13ac 100644
--- a/src/machine/m_at_socket4_5.c
+++ b/src/machine/m_at_socket4_5.c
@@ -384,37 +384,6 @@ machine_at_president_init(const machine_t *model)
 }
 
 
-int
-machine_at_apollo_init(const machine_t *model)
-{
-    int ret;
-
-    ret = bios_load_linear(L"roms/machines/apollo/S728P.ROM",
-			   0x000e0000, 131072, 0);
-
-    if (bios_only || !ret)
-	return ret;
-
-    machine_at_common_init_ex(model, 2);
-    device_add(&ls486e_nvr_device);
-
-    pci_init(PCI_CONFIG_TYPE_1);
-    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
-    pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
-    pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
-    pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
-    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
-    device_add(&i430fx_device);
-    device_add(&piix_device);
-    device_add(&keyboard_ps2_pci_device);
-    device_add(&fdc37c932fr_device);
-    device_add(&intel_flash_bxt_device);
-
-    return ret;
-}
-
-
 #if defined(DEV_BRANCH) && defined(USE_VECTRA54)
 int
 machine_at_vectra54_init(const machine_t *model)
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index b358fde33..8cc0dbfaf 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -201,7 +201,7 @@ const machine_t machines[] = {
     { "[486 PCI] Zida Tomato 4DP",		"4dps",			{{"Intel", cpus_i486},        {"AMD", cpus_Am486},   {"Cyrix", cpus_Cx486},  {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  1,  255,   1, 127,		 machine_at_4dps_init, NULL			},
 
     /* Socket 4 machines */
-	//430LX
+    /* 430LX */
     { "[Socket 4 LX] IBM Ambra DP60 PCI",	"ambradp60",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	    machine_at_ambradp60_init, NULL			},
 #if defined(DEV_BRANCH) && defined(USE_VPP60)
     { "[Socket 4 LX] IBM PS/ValuePoint P60",	"valuepointp60",	{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  2,  128,   2, 127,	machine_at_valuepointp60_init, NULL			},
@@ -210,13 +210,12 @@ const machine_t machines[] = {
     { "[Socket 4 LX] Micro Star 586MC1",	"586mc1",		{{"Intel", cpus_Pentium5V},   {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  2,  128,   2, 127,	       machine_at_586mc1_init, NULL			},
 
     /* Socket 5 machines */
-	//430NX
+    /* 430NX */
     { "[Socket 5 NX] Intel Premiere/PCI II",	"plato",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,		machine_at_plato_init, NULL			},
     { "[Socket 5 NX] IBM Ambra DP90 PCI",	"ambradp90",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,	    machine_at_ambradp90_init, NULL			},
     { "[Socket 5 NX] Gigabyte GA-586IP",	"430nx",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  2,  128,   2, 127,		machine_at_430nx_init, NULL			},
-	
-	//430FX
-    { "[Socket 5 FX] AMI Apollo",		"apollo",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 127,	       machine_at_apollo_init, NULL			},
+
+    /* 430FX */
 #if defined(DEV_BRANCH) && defined(USE_VECTRA54)
     { "[Socket 5 FX] HP Vectra VL 5 Series 4",  "vectra54",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 511,	     machine_at_vectra54_init, NULL			},
 #endif
@@ -226,7 +225,7 @@ const machine_t machines[] = {
     { "[Socket 5 FX] President Award 430FX PCI","president",		MACHINE_CPUS_PENTIUM_S5,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC,						  8,  128,   8, 127,	    machine_at_president_init, NULL			},
 
     /* Socket 7 machines */
-	//430FX
+    /* 430FX */
     { "[Socket 7-3V FX] ASUS P/I-P54TP4XE",	"p54tp4xe",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	     machine_at_p54tp4xe_init, NULL			},
     { "[Socket 7-3V FX] Intel Advanced/ATX",	"thor",			MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,		 machine_at_thor_init, NULL			},
     { "[Socket 7-3V FX] Intel Advanced/EV",	"endeavor",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO,			  8,  128,   8, 127,	     machine_at_endeavor_init, at_endeavor_get_device	},
@@ -235,7 +234,7 @@ const machine_t machines[] = {
 #endif
     { "[Socket 7-3V FX] Packard Bell PB640",	"pb640",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO,	 		  8,  128,   8, 127,		machine_at_pb640_init, at_pb640_get_device	},
 
-	//430HX
+    /* 430HX */
     { "[Socket 7-3V HX] Acer M3a",		"acerm3a",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  192,   8, 127,	      machine_at_acerm3a_init, NULL			},
     { "[Socket 7-3V HX] AOpen AP53",		"ap53",			MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 127,		 machine_at_ap53_init, NULL			},    
     { "[Socket 7-3V HX] SuperMicro Super P55T2S","p55t2s",		MACHINE_CPUS_PENTIUM_S73V,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  768,   8, 127,	       machine_at_p55t2s_init, NULL			},
@@ -246,64 +245,63 @@ const machine_t machines[] = {
     { "[Socket 7 HX] Intel TC430HX",		"tc430hx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 255,	      machine_at_tc430hx_init, NULL			},
     { "[Socket 7 HX] Toshiba Equium 5200D",	"equium5200",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  192,   8, 127,	   machine_at_equium5200_init, NULL			},
 
-	//430VX
+    /* 430VX */
     { "[Socket 7 VX] ASUS P/I-P55TVP4",		"p55tvp4",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_p55tvp4_init, NULL			},
     { "[Socket 7 VX] Shuttle HOT-557",		"430vx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  128,   8, 127,	       machine_at_i430vx_init, NULL			},
     { "[Socket 7 VX] Epox P55-VA",		"p55va",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  128,   8, 127,		machine_at_p55va_init, NULL			},
     { "[Socket 7 VX] HP Brio 80xx",			"brio80xx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_brio80xx_init, NULL		},
     { "[Socket 7 VX] Packard Bell PB680",	"pb680",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	      machine_at_pb680_init, NULL		},
 
-	//430TX
+    /* 430TX */
     { "[Socket 7 TX] ASUS TX97",		"tx97",			MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	         machine_at_tx97_init, NULL			},
     { "[Socket 7 TX] Gigabyte GA-586T2",        "586t2",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_586t2_init, NULL			},
     { "[Socket 7 TX] Intel YM430TX",		"ym430tx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_ym430tx_init, NULL			},
     { "[Socket 7 TX] Iwill P55XB2",		"p55xb2",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	       machine_at_p55xb2_init, NULL			},
     { "[Socket 7 TX] PC Partner TXA807DS",	"807ds",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_807ds_init, NULL			},
     { "[Socket 7 TX] SuperMicro P5MMS98",	"p5mms98",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_p5mms98_init, NULL			},
- 
-	//Apollo VPX
+
+    /* Apollo VPX */
     { "[Socket 7 VPX] Zida Tomato TX100",	"tx100",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 127,	        machine_at_tx100_init, NULL			},
 
-	//Apollo VP3
+    /* Apollo VP3 */
     { "[Socket 7 VP3] QDI Advance II",		"advanceii",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	    machine_at_advanceii_init, NULL			},
     
     /* Super Socket 7 machines */
-	//Apollo MVP3
+    /* Apollo MVP3 */
     { "[Super 7 MVP3] AOpen AX59 Pro",		"ax59pro",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8, 1024,  8, 255,	      machine_at_ax59pro_init, NULL			},
     { "[Super 7 MVP3] FIC VA-503+",		"ficva503p",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,  8, 255,	         machine_at_mvp3_init, NULL			},
 
     /* Socket 8 machines */
-	//440FX
+    /* 440FX */
     { "[Socket 8 FX] Gigabyte GA-686NX",	"686nx",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	        machine_at_686nx_init, NULL			},
     { "[Socket 8 FX] PC Partner MB600N",	"mb600n",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	       machine_at_mb600n_init, NULL			},
     { "[Socket 8 FX] Biostar MB-8500ttc",	"8500ttc",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	      machine_at_8500ttc_init, NULL			},
     { "[Socket 8 FX] Micronics M6MI",		"m6mi",			{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	         machine_at_m6mi_init, NULL			},
 
     /* Slot 1 machines */
-	//440FX
+    /* 440FX */
     { "[Slot 1 FX] ECS P6KFX-A",		"p6kfx",		{{"Intel", cpus_PentiumII_28v},{"",    NULL},        {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	        machine_at_p6kfx_init, NULL			},
 
-	//440LX
-	
-	
-	//440BX
+    /* 440LX */
+
+    /* 440BX */
     { "[Slot 1 BX] Gigabyte GA-6BXC",		"6bxc",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		 machine_at_6bxc_init, NULL			},
     { "[Slot 1 BX] ASUS P2B-LS",		"p2bls",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		machine_at_p2bls_init, NULL			},
     { "[Slot 1 BX] ASUS P3B-F",			"p3bf",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_p3bf_init, NULL			},
     { "[Slot 1 BX] ABit BF6",			"bf6",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		  machine_at_bf6_init, NULL			},
 
-	//440ZX
+    /* 440ZX */
     { "[Slot 1 ZX] Packard Bell Bora Pro",	"borapro",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 255,	      machine_at_borapro_init, NULL			},
 
     /* PGA370 machines */
-	//440BX
+    /* 440BX */
     { "[Socket 370 BX] ASUS CUBX",		"cubx",			{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_cubx_init, NULL			},
     { "[Socket 370 BX] A-Trend ATC7020BXII",	"atc7020bxii",		{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,	  machine_at_atc7020bxii_init, NULL			},
 
-	//440ZX
+    /* 440ZX */
     { "[Socket 370 ZX] Soltek SL-63A1",		"63a",			{{"Intel", cpus_Celeron},     {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 255,		  machine_at_63a_init, NULL			},
 
-	//VIA Apollo Pro
+    /* VIA Apollo Pro */
     { "[Socket 370 APRO] PC Partner APAS3",	"apas3",		{{"Intel", cpus_Celeron},     {"VIA", cpus_Cyrix3},  {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,	  				  8, 1024,   8, 255,            machine_at_apas3_init, NULL			},
 
     { NULL,					NULL,			{{"",      0},                {"",    0},            {"",      0},           {"",         0},     {"",      0}},    0,                                                                                                    0,    0,   0,   0,			         NULL, NULL			}

From f9de3183aa32df1d277df894f2bf936a3417e9ed Mon Sep 17 00:00:00 2001
From: Shaojun Li <i@shaojun.li>
Date: Fri, 24 Apr 2020 13:33:56 +0800
Subject: [PATCH 33/43] Allow relative path of disk images.

---
 src/config.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/config.c b/src/config.c
index 0cc5d35a1..d63294264 100644
--- a/src/config.c
+++ b/src/config.c
@@ -957,7 +957,12 @@ load_hard_disks(void)
 		wcsncpy(hdd[c].fn, &wp[wcslen(usr_path)], sizeof_w(hdd[c].fn));
 	} else
 #endif
-	wcsncpy(hdd[c].fn, wp, sizeof_w(hdd[c].fn));
+	if (plat_path_abs(wp)) {
+		wcsncpy(hdd[c].fn, wp, sizeof_w(hdd[c].fn));
+	} else {
+		wcsncpy(hdd[c].fn, usr_path, sizeof_w(hdd[c].fn));
+		wcsncat(hdd[c].fn, wp, sizeof_w(hdd[c].fn)-wcslen(usr_path));
+	}
 
 	/* If disk is empty or invalid, mark it for deletion. */
 	if (! hdd_is_valid(c)) {
@@ -1832,7 +1837,10 @@ save_hard_disks(void)
 
 	sprintf(temp, "hdd_%02i_fn", c+1);
 	if (hdd_is_valid(c) && (wcslen(hdd[c].fn) != 0))
-		config_set_wstring(cat, temp, hdd[c].fn);
+		if (wcsnicmp(hdd[c].fn, usr_path, wcslen(usr_path)))
+			config_set_wstring(cat, temp, &hdd[c].fn[wcslen(usr_path)]);
+		else
+			config_set_wstring(cat, temp, hdd[c].fn);
 	else
 		config_delete_var(cat, temp);
     }

From 0e7c0cca02ca2e16fbb43f68df936b9298b6e83e Mon Sep 17 00:00:00 2001
From: Shaojun Li <i@shaojun.li>
Date: Fri, 24 Apr 2020 13:38:52 +0800
Subject: [PATCH 34/43] Fix the close button of about dialog not working.

---
 src/win/win_about.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/win/win_about.c b/src/win/win_about.c
index b0001b177..0c57c346d 100644
--- a/src/win/win_about.c
+++ b/src/win/win_about.c
@@ -53,6 +53,7 @@ AboutDialogProcedure(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
 	case WM_COMMAND:
                 switch (LOWORD(wParam)) {
 			case IDOK:
+			case IDCANCEL:
 				EndDialog(hdlg, 0);
 				plat_pause(0);
 				return TRUE;

From 31216312f73a92f59ab2cb89508359e531c2e0a3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <dhrdlicka@users.noreply.github.com>
Date: Fri, 24 Apr 2020 14:42:01 +0200
Subject: [PATCH 35/43] config: fix hard disk images outside usrpath

---
 src/config.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/config.c b/src/config.c
index d63294264..0d3b13a29 100644
--- a/src/config.c
+++ b/src/config.c
@@ -1837,7 +1837,7 @@ save_hard_disks(void)
 
 	sprintf(temp, "hdd_%02i_fn", c+1);
 	if (hdd_is_valid(c) && (wcslen(hdd[c].fn) != 0))
-		if (wcsnicmp(hdd[c].fn, usr_path, wcslen(usr_path)))
+		if (!wcsnicmp(hdd[c].fn, usr_path, wcslen(usr_path)))
 			config_set_wstring(cat, temp, &hdd[c].fn[wcslen(usr_path)]);
 		else
 			config_set_wstring(cat, temp, hdd[c].fn);

From af07bd5e6c01a93f143546641de09af7e563c8b8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <dhrdlicka@users.noreply.github.com>
Date: Fri, 24 Apr 2020 14:56:30 +0200
Subject: [PATCH 36/43] win: Don't show full path for HD images in usrpath

---
 src/win/win_settings.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/win/win_settings.c b/src/win/win_settings.c
index a6e34420b..b34afd943 100644
--- a/src/win/win_settings.c
+++ b/src/win/win_settings.c
@@ -2352,7 +2352,10 @@ win_settings_hard_disks_update_item(HWND hwndList, int i, int column)
 	lvI.pszText = szText;
 	lvI.iImage = 0;
     } else if (column == 1) {
-	lvI.pszText = temp_hdd[i].fn;
+	if (!wcsnicmp(temp_hdd[i].fn, usr_path, wcslen(usr_path)))
+		lvI.pszText = temp_hdd[i].fn + wcslen(usr_path);
+	else
+		lvI.pszText = temp_hdd[i].fn;
 	lvI.iImage = 0;
     } else if (column == 2) {
 	wsprintf(szText, plat_get_string(IDS_4098), temp_hdd[i].tracks);
@@ -2421,7 +2424,10 @@ win_settings_hard_disks_recalc_list(HWND hwndList)
 			return FALSE;
 
 		lvI.iSubItem = 1;
-		lvI.pszText = temp_hdd[i].fn;
+		if (!wcsnicmp(temp_hdd[i].fn, usr_path, wcslen(usr_path)))
+			lvI.pszText = temp_hdd[i].fn + wcslen(usr_path);
+		else
+			lvI.pszText = temp_hdd[i].fn;
 		lvI.iItem = j;
 		lvI.iImage = 0;
 

From fe6df042be95c74dfcba8c01ffcb44d33c2dac13 Mon Sep 17 00:00:00 2001
From: nerd73 <nerd7b@gmail.com>
Date: Sat, 25 Apr 2020 03:24:59 -0600
Subject: [PATCH 37/43] Implement a proper P6 timing model

---
 src/cpu/codegen_timing_p6.c     | 1864 ++++++++++++++++---------------
 src/cpu_new/codegen_timing_p6.c | 1864 ++++++++++++++++---------------
 2 files changed, 1902 insertions(+), 1826 deletions(-)

diff --git a/src/cpu/codegen_timing_p6.c b/src/cpu/codegen_timing_p6.c
index 0cddde494..a0da30304 100644
--- a/src/cpu/codegen_timing_p6.c
+++ b/src/cpu/codegen_timing_p6.c
@@ -1,4 +1,5 @@
-/*Hacky P6 timings based on K6 timings*/
+/*Basic P6 timing model by plant/nerd73. Based on the K6 timing model*/
+/*Some cycle timings come from https://www.agner.org/optimize/instruction_tables.pdf*/
 #include <stdio.h>
 #include <stdint.h>
 #include <string.h>
@@ -21,24 +22,26 @@ typedef enum uop_type_t
         UOP_ALU = 0,   /*Executes in Integer X or Y units*/
         UOP_ALUX,      /*Executes in Integer X unit*/
         UOP_LOAD,      /*Executes in Load unit*/
-        UOP_STORE,     /*Executes in Store unit*/
+        UOP_STORED,    /*Executes in Data Store unit*/
+	UOP_STOREA,    /*Executes in Address Store unit*/
         UOP_FLOAD,     /*Executes in Load unit*/
-        UOP_FSTORE,    /*Executes in Store unit*/
+        UOP_FSTORED,   /*Executes in Data Store unit*/
+	UOP_FSTOREA,   /*Executes in Address Store unit*/
         UOP_MLOAD,     /*Executes in Load unit*/
-        UOP_MSTORE,    /*Executes in Store unit*/
+        UOP_MSTORED,   /*Executes in Data Store unit*/
+        UOP_MSTOREA,   /*Executes in Address Store unit*/
         UOP_FLOAT,     /*Executes in Floating Point unit*/
-        UOP_MEU,       /*Executes in Multimedia unit*/
-        UOP_MEU_SHIFT, /*Executes in Multimedia unit or ALU X/Y. Uses MMX shifter*/
-        UOP_MEU_MUL,   /*Executes in Multimedia unit or ALU X/Y. Uses MMX multiplier*/
+        UOP_MMX,       /*Executes in Integer X or Y units as MMX*/
+        UOP_MMX_SHIFT, /*Executes in Integer Y unit. Uses MMX shifter*/
+        UOP_MMX_MUL,   /*Executes in Integer X unit. Uses MMX multiplier*/
         UOP_BRANCH,    /*Executes in Branch unit*/
         UOP_LIMM       /*Does not require an execution unit*/
 } uop_type_t;
 
 typedef enum decode_type_t
 {
-        DECODE_SHORT,
-        DECODE_LONG,
-        DECODE_VECTOR
+        DECODE_SIMPLE,
+        DECODE_COMPLEX,
 } decode_type_t;
 
 #define MAX_UOPS 10
@@ -46,7 +49,6 @@ typedef enum decode_type_t
 typedef struct risc86_uop_t
 {
         uop_type_t type;
-        double throughput;
         double latency;
 } risc86_uop_t;
 
@@ -60,804 +62,885 @@ typedef struct risc86_instruction_t
 static const risc86_instruction_t alu_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_ALU, .latency = 1}
 };
 static const risc86_instruction_t alux_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1}
 };
 static const risc86_instruction_t load_alu_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t load_alux_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
 };
 static const risc86_instruction_t alu_store_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency = 1},
+        .uop[1] = {.type = UOP_ALU,     .latency = 1},
+        .uop[2] = {.type = UOP_STORED,  .latency = 1},
+        .uop[3] = {.type = UOP_STOREA,  .latency = 1}	
+	};
 static const risc86_instruction_t alux_store_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,    .latency = 1},
+        .uop[2] = {.type = UOP_STORED,  .latency = 1},
+        .uop[3] = {.type = UOP_STOREA,  .latency = 1}		
 };
 
 static const risc86_instruction_t branch_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_BRANCH, .latency = 1}
 };
 
 static const risc86_instruction_t limm_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LIMM, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_LIMM, .latency = 1}
 };
 
 static const risc86_instruction_t load_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1}
 };
 
 static const risc86_instruction_t store_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED,  .latency = 1},
+        .uop[1] = {.type = UOP_STOREA,  .latency = 1}		
 };
 
 
 static const risc86_instruction_t bswap_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,   .latency = 1},	
 };
 static const risc86_instruction_t leave_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1},
+        .uop[2] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t lods_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t loop_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
 };
 static const risc86_instruction_t mov_reg_seg_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
 };
 static const risc86_instruction_t movs_op =
 {
         .nr_uops = 4,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t pop_reg_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t pop_mem_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t push_imm_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_STORE,  .throughput = 1, .latency = 2},
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED,  .latency = 1},
+        .uop[1] = {.type = UOP_STOREA,  .latency = 1},	
 };
 static const risc86_instruction_t push_mem_op =
 {
-        .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1}
 };
 static const risc86_instruction_t push_seg_op =
 {
-        .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},
+	.uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t stos_op =
 {
-        .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t test_reg_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t test_reg_b_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,   .latency = 1}
 };
 static const risc86_instruction_t test_mem_imm_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t test_mem_imm_b_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
 };
 static const risc86_instruction_t xchg_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .latency = 1}
 };
 
 
 static const risc86_instruction_t mmx_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX, .latency = 1.5}
 };
 static const risc86_instruction_t mmx_mul_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1.5, .latency = 3}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
 static const risc86_instruction_t mmx_shift_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU_SHIFT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX_SHIFT, .latency = 1.5}
 };
 static const risc86_instruction_t load_mmx_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU,  .throughput = 1.5, .latency = 3}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency =   1},
+        .uop[1] = {.type = UOP_MMX,  .latency = 1.5}
 };
 static const risc86_instruction_t load_mmx_mul_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency =   3},
+        .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
 static const risc86_instruction_t load_mmx_shift_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD,      .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU_SHIFT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,      .latency =   3},
+        .uop[1] = {.type = UOP_MMX_SHIFT, .latency = 1.5}
 };
 static const risc86_instruction_t mload_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MLOAD, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_MLOAD, .latency = 3},
 };
 
 static const risc86_instruction_t mstore_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MSTORE, .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_MSTORED, .latency = 1},
+        .uop[1] = {.type = UOP_MSTOREA, .latency = 1}
 };
 static const risc86_instruction_t pmul_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
 static const risc86_instruction_t pmul_mem_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency =   3},
+        .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
-
 static const risc86_instruction_t float_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 1}
+};
+static const risc86_instruction_t fadd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 3}
+};
+static const risc86_instruction_t fmul_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_ALU, .latency = 5}
+};
+static const risc86_instruction_t float2_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 1}
+};
+static const risc86_instruction_t fchs_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 2},
+        .uop[2] = {.type = UOP_FLOAT, .latency = 2}	
 };
 static const risc86_instruction_t load_float_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_FLOAT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 1}
+};
+static const risc86_instruction_t load_fadd_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 3}
+};
+static const risc86_instruction_t load_fmul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 5}
 };
 static const risc86_instruction_t fstore_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FSTORED, .latency = 1},
+        .uop[1] = {.type = UOP_FSTOREA, .latency = 1},
+};
+static const risc86_instruction_t load_fiadd_op =
+{
+        .nr_uops = 7,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[2] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[3] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[4] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[5] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[6] = {.type = UOP_FLOAT, .latency = 1}	
 };
-
 static const risc86_instruction_t fdiv_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 38, .latency = 38}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 32}
 };
 static const risc86_instruction_t fdiv_mem_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_FLOAT, .throughput = 38, .latency = 38}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 38}
 };
 static const risc86_instruction_t fsin_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 62, .latency = 62}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 60}
 };
 static const risc86_instruction_t fsqrt_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 49, .latency = 49}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 69}
 };
 
-static const risc86_instruction_t vector_fldcw_op =
+static const risc86_instruction_t complex_fldcw_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 8, .latency = 8}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 10}
 };
-static const risc86_instruction_t vector_float_op =
+static const risc86_instruction_t complex_float_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 1}
 };
-static const risc86_instruction_t vector_float_l_op =
+static const risc86_instruction_t complex_float_l_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 50, .latency = 50}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 50}
 };
-static const risc86_instruction_t vector_flde_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[2] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
-};
-static const risc86_instruction_t vector_fste_op =
+static const risc86_instruction_t complex_flde_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2},
-        .uop[1] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[2] = {.type = UOP_FLOAT, .latency = 2}
+};
+static const risc86_instruction_t complex_fste_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT,   .latency = 2},
+        .uop[1] = {.type = UOP_FSTORED, .latency = 1},
+        .uop[2] = {.type = UOP_FSTOREA, .latency = 1}
 };
 
-static const risc86_instruction_t vector_alu1_op =
+static const risc86_instruction_t complex_alu1_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alu2_op =
+static const risc86_instruction_t complex_alu2_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alu3_op =
+static const risc86_instruction_t complex_alu3_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alu6_op =
+static const risc86_instruction_t complex_alu6_op =
 {
         .nr_uops = 6,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .latency = 1},
+        .uop[3] = {.type = UOP_ALU, .latency = 1},
+        .uop[4] = {.type = UOP_ALU, .latency = 1},
+        .uop[5] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alux1_op =
+static const risc86_instruction_t complex_alux1_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1}
 };
-static const risc86_instruction_t vector_alux3_op =
+static const risc86_instruction_t complex_alux3_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .latency = 1}
 };
-static const risc86_instruction_t vector_alux6_op =
+static const risc86_instruction_t complex_alux6_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .nr_uops = 6,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .latency = 1},
+        .uop[3] = {.type = UOP_ALUX, .latency = 1},
+        .uop[4] = {.type = UOP_ALUX, .latency = 1},
+        .uop[5] = {.type = UOP_ALUX, .latency = 1}
 };
-static const risc86_instruction_t vector_alu_store_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_alux_store_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_arpl_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_bound_op =
+static const risc86_instruction_t complex_alu_store_op =
 {
         .nr_uops = 4,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1},	
 };
-static const risc86_instruction_t vector_bsx_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_call_far_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
-        .uop[1] = {.type = UOP_STORE,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_cli_sti_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 7, .latency = 7}
-};
-static const risc86_instruction_t vector_cmps_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_cmpsb_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_cmpxchg_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-};
-static const risc86_instruction_t vector_cmpxchg_b_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-};
-static const risc86_instruction_t vector_cpuid_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 22, .latency = 22}
-};
-static const risc86_instruction_t vector_div16_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_div16_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_div32_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
-};
-static const risc86_instruction_t vector_div32_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
-};
-static const risc86_instruction_t vector_emms_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 25, .latency = 25}
-};
-static const risc86_instruction_t vector_enter_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE,  .throughput =  1, .latency =  2},
-        .uop[1] = {.type = UOP_ALU,    .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_femms_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 6, .latency = 6}
-};
-static const risc86_instruction_t vector_in_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 10, .latency = 11}
-};
-static const risc86_instruction_t vector_ins_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 10, .latency = 11},
-        .uop[1] = {.type = UOP_STORE, .throughput =  1, .latency =  1},
-        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
-};
-static const risc86_instruction_t vector_int_op =
-{
-        .nr_uops = 5,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
-        .uop[1] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
-        .uop[2] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
-        .uop[3] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
-        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
-};
-static const risc86_instruction_t vector_iret_op =
-{
-        .nr_uops = 5,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
-        .uop[1] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
-        .uop[2] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
-        .uop[3] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
-        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
-};
-static const risc86_instruction_t vector_invd_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1000, .latency = 1000}
-};
-static const risc86_instruction_t vector_jmp_far_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_load_alu_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_load_alux_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_loop_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_lss_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_mov_mem_seg_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mov_seg_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_mov_seg_reg_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_mul_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mul_mem_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mul64_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mul64_mem_op =
+static const risc86_instruction_t complex_alux_store_op =
 {
         .nr_uops = 4,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1}	
 };
-static const risc86_instruction_t vector_out_op =
+static const risc86_instruction_t complex_arpl_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,   .latency = 3},
+        .uop[1] = {.type = UOP_ALU,   .latency = 3}
+};
+static const risc86_instruction_t complex_bound_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,  .latency = 1},
+        .uop[3] = {.type = UOP_ALU,  .latency = 1}
+};
+static const risc86_instruction_t complex_bsx_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE, .throughput = 10, .latency = 10}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 10}
 };
-static const risc86_instruction_t vector_outs_op =
+static const risc86_instruction_t complex_call_far_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,     .latency = 3},
+        .uop[1] = {.type = UOP_STORED,  .latency = 1},
+        .uop[2] = {.type = UOP_STOREA,  .latency = 1},	
+        .uop[3] = {.type = UOP_BRANCH,  .latency = 1}
+};
+static const risc86_instruction_t complex_cli_sti_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 7}
+};
+static const risc86_instruction_t complex_cmps_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput =  1, .latency =  1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 10, .latency = 10},
-        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 1}
 };
-static const risc86_instruction_t vector_pusha_op =
+static const risc86_instruction_t complex_cmpsb_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_cmpxchg_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_cmpxchg_b_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_cpuid_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 23}
+};
+static const risc86_instruction_t complex_div16_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 10}
+};
+static const risc86_instruction_t complex_div16_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency =  1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 10}
+};
+static const risc86_instruction_t complex_div32_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 18}
+};
+static const risc86_instruction_t complex_div32_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,  .latency = 18}
+};
+static const risc86_instruction_t complex_emms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 25}
+};
+static const risc86_instruction_t complex_enter_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency =  1},
+        .uop[1] = {.type = UOP_STOREA, .latency =  1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 10}
+};
+static const risc86_instruction_t complex_femms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 6}
+};
+static const risc86_instruction_t complex_in_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 10}
+};
+static const risc86_instruction_t complex_ins_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 10},
+        .uop[1] = {.type = UOP_STORED, .latency =  1},
+        .uop[2] = {.type = UOP_STOREA, .latency =  1},
+        .uop[3] = {.type = UOP_ALU,    .latency =  1}
+};
+static const risc86_instruction_t complex_int_op =
 {
         .nr_uops = 8,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[6] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[7] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,     .latency = 20},
+        .uop[1] = {.type = UOP_STORED,  .latency =  1},
+        .uop[2] = {.type = UOP_STOREA,  .latency =  1},
+        .uop[3] = {.type = UOP_STORED,  .latency =  1},
+        .uop[4] = {.type = UOP_STOREA,  .latency =  1},
+        .uop[5] = {.type = UOP_STORED,  .latency =  1},
+        .uop[6] = {.type = UOP_STOREA,  .latency =  1},	
+        .uop[7] = {.type = UOP_BRANCH,  .latency =  1}
 };
-static const risc86_instruction_t vector_popa_op =
+static const risc86_instruction_t complex_iret_op =
+{
+        .nr_uops = 5,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency =  3},
+        .uop[1] = {.type = UOP_LOAD,   .latency =  3},
+        .uop[2] = {.type = UOP_LOAD,   .latency =  3},
+        .uop[3] = {.type = UOP_ALU,    .latency = 20},
+        .uop[4] = {.type = UOP_BRANCH, .latency =  1}
+};
+static const risc86_instruction_t complex_invd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 500}
+};
+static const risc86_instruction_t complex_jmp_far_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 3},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_load_alu_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
+};
+static const risc86_instruction_t complex_load_alux_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_loop_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_lss_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 3}
+};
+static const risc86_instruction_t complex_mov_mem_seg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},
+};
+static const risc86_instruction_t complex_mov_seg_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 3}
+};
+static const risc86_instruction_t complex_mov_seg_reg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,   .latency = 3}
+};
+static const risc86_instruction_t complex_mul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_mul_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_ALUX,   .latency = 1}
+};
+static const risc86_instruction_t complex_mul64_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_mul64_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[3] = {.type = UOP_ALUX,   .latency = 1}
+};
+static const risc86_instruction_t complex_out_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency = 10},
+        .uop[1] = {.type = UOP_STOREA, .latency = 10},
+};
+static const risc86_instruction_t complex_outs_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency =  1},
+        .uop[1] = {.type = UOP_STORED, .latency = 10},
+        .uop[1] = {.type = UOP_STOREA, .latency = 10},	
+        .uop[2] = {.type = UOP_ALU,    .latency =  1}
+};
+static const risc86_instruction_t complex_pusha_op =
 {
         .nr_uops = 8,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[6] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[7] = {.type = UOP_LOAD, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency = 2},
+        .uop[1] = {.type = UOP_STOREA, .latency = 2},
+        .uop[2] = {.type = UOP_STORED, .latency = 2},
+        .uop[3] = {.type = UOP_STOREA, .latency = 2},
+        .uop[4] = {.type = UOP_STORED, .latency = 2},
+        .uop[5] = {.type = UOP_STOREA, .latency = 2},
+        .uop[6] = {.type = UOP_STORED, .latency = 2},
+        .uop[7] = {.type = UOP_STOREA, .latency = 2}
 };
-static const risc86_instruction_t vector_popf_op =
+static const risc86_instruction_t complex_popa_op =
+{
+        .nr_uops = 8,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD, .latency = 1},
+        .uop[2] = {.type = UOP_LOAD, .latency = 1},
+        .uop[3] = {.type = UOP_LOAD, .latency = 1},
+        .uop[4] = {.type = UOP_LOAD, .latency = 1},
+        .uop[5] = {.type = UOP_LOAD, .latency = 1},
+        .uop[6] = {.type = UOP_LOAD, .latency = 1},
+        .uop[7] = {.type = UOP_LOAD, .latency = 1}
+};
+static const risc86_instruction_t complex_popf_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput =  1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 17, .latency = 17}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency =  3},
+        .uop[1] = {.type = UOP_ALUX, .latency = 17}
 };
-static const risc86_instruction_t vector_push_mem_op =
+static const risc86_instruction_t complex_push_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency = 1},
+        .uop[1] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_pushf_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_ret_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_retf_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 3},
+        .uop[2] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_scas_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_scasb_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_setcc_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,    .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,    .latency = 1},
+        .uop[2] = {.type = UOP_FSTORED, .latency = 1},
+        .uop[3] = {.type = UOP_FSTOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_setcc_reg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,  .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,  .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .latency = 1}
+};
+static const risc86_instruction_t complex_test_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
+};
+static const risc86_instruction_t complex_test_mem_b_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_xchg_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_xlat_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1},
+        .uop[1] = {.type = UOP_LOAD,   .latency = 1}
+};
+static const risc86_instruction_t complex_wbinvd_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_pushf_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_ret_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_retf_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
-        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_scas_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_scasb_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_setcc_mem_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_setcc_reg_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_test_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_test_mem_b_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_xchg_mem_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_xlat_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2}
-};
-static const risc86_instruction_t vector_wbinvd_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 10000, .latency = 10000}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 10000}
 };
 
+
 #define INVALID NULL
 
 static const risc86_instruction_t *opcode_timings[256] =
@@ -865,38 +948,38 @@ static const risc86_instruction_t *opcode_timings[256] =
 /*      ADD                    ADD                    ADD                   ADD*/
 /*00*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      ADD                    ADD                    PUSH ES               POP ES*/
-        &alux_op,              &alu_op,               &push_seg_op,         &vector_mov_seg_mem_op,
+        &alux_op,              &alu_op,               &push_seg_op,         &complex_mov_seg_mem_op,
 /*      OR                     OR                     OR                    OR*/
         &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      OR                     OR                     PUSH CS               */
         &alux_op,              &alu_op,               &push_seg_op,         INVALID,
 
 /*      ADC                    ADC                    ADC                   ADC*/
-/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*10*/  &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op,
 /*      ADC                    ADC                    PUSH SS               POP SS*/
-        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+        &complex_alux1_op,     &complex_alu1_op,      &push_seg_op,         &complex_mov_seg_mem_op,
 /*      SBB                    SBB                    SBB                   SBB*/
-/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*10*/  &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op,
 /*      SBB                    SBB                    PUSH DS               POP DS*/
-        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+        &complex_alux1_op,     &complex_alu1_op,      &push_seg_op,         &complex_mov_seg_mem_op,
 
 /*      AND                    AND                    AND                   AND*/
 /*20*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      AND                    AND                                          DAA*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux1_op,
 /*      SUB                    SUB                    SUB                   SUB*/
         &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      SUB                    SUB                                          DAS*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux1_op,
 
 /*      XOR                    XOR                    XOR                   XOR*/
 /*30*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      XOR                    XOR                                          AAA*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux6_op,
 /*      CMP                    CMP                    CMP                   CMP*/
         &load_alux_op,         &load_alu_op,          &load_alux_op,        &load_alu_op,
 /*      CMP                    CMP                                          AAS*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux6_op,
 
 /*      INC EAX                INC ECX                INC EDX                INC EBX*/
 /*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
@@ -917,12 +1000,12 @@ static const risc86_instruction_t *opcode_timings[256] =
         &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
 
 /*      PUSHA                  POPA                   BOUND                  ARPL*/
-/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+/*60*/  &complex_pusha_op,     &complex_popa_op,      &complex_bound_op,     &complex_arpl_op,
         INVALID,               INVALID,               INVALID,               INVALID,
 /*      PUSH imm               IMUL                   PUSH imm               IMUL*/
-        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+        &push_imm_op,          &complex_mul_op,       &push_imm_op,          &complex_mul_op,
 /*      INSB                   INSW                   OUTSB                  OUTSW*/
-        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+        &complex_ins_op,       &complex_ins_op,       &complex_outs_op,      &complex_outs_op,
 
 /*      Jxx*/
 /*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
@@ -932,29 +1015,29 @@ static const risc86_instruction_t *opcode_timings[256] =
 
 /*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      TEST                       TEST                       XCHG                       XCHG*/
-        &vector_test_mem_b_op,     &vector_test_mem_op,       &vector_xchg_mem_op,       &vector_xchg_mem_op,
+        &complex_test_mem_b_op,    &complex_test_mem_op,      &complex_xchg_mem_op,      &complex_xchg_mem_op,
 /*      MOV                        MOV                        MOV                        MOV*/
         &store_op,                 &store_op,                 &load_op,                  &load_op,
 /*      MOV from seg               LEA                        MOV to seg                 POP*/
-        &vector_mov_mem_seg_op,    &store_op,                 &vector_mov_seg_mem_op,    &pop_mem_op,
+        &complex_mov_mem_seg_op,   &store_op,                 &complex_mov_seg_mem_op,   &pop_mem_op,
 
 /*      NOP                        XCHG                       XCHG                       XCHG*/
 /*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      XCHG                       XCHG                       XCHG                       XCHG*/
         &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      CBW                        CWD                        CALL far                   WAIT*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_call_far_op,      &limm_op,
 /*      PUSHF                      POPF                       SAHF                       LAHF*/
-        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+        &complex_pushf_op,         &complex_popf_op,          &complex_alux1_op,         &complex_alux1_op,
 
 /*      MOV                        MOV                        MOV                        MOV*/
 /*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
 /*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
-        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+        &movs_op,                  &movs_op,                  &complex_cmpsb_op,         &complex_cmps_op,
 /*      TEST                       TEST                       STOSB                      STOSW*/
         &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
 /*      LODSB                      LODSW                      SCASB                      SCASW*/
-        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+        &lods_op,                  &lods_op,                  &complex_scasb_op,         &complex_scas_op,
 
 /*      MOV*/
 /*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
@@ -963,37 +1046,37 @@ static const risc86_instruction_t *opcode_timings[256] =
         &limm_op,       &limm_op,       &limm_op,       &limm_op,
 
 /*                                                            RET imm                    RET*/
-/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*c0*/  INVALID,                   INVALID,                   &complex_ret_op,           &complex_ret_op,
 /*      LES                        LDS                        MOV                        MOV*/
-        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+        &complex_lss_op,           &complex_lss_op,           &store_op,                 &store_op,
 /*      ENTER                      LEAVE                      RETF                       RETF*/
-        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+        &complex_enter_op,         &leave_op,                 &complex_retf_op,          &complex_retf_op,
 /*      INT3                       INT                        INTO                       IRET*/
-        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+        &complex_int_op,           &complex_int_op,           &complex_int_op,           &complex_iret_op,
 
 
 /*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      AAM                        AAD                        SETALC                     XLAT*/
-        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        &complex_alux6_op,         &complex_alux3_op,         &complex_alux1_op,         &complex_xlat_op,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
-/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*e0*/  &complex_loop_op,          &complex_loop_op,          &loop_op,                  &complex_loop_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 /*      CALL                       JMP                        JMP                        JMP*/
-        &store_op,                 &branch_op,                &vector_jmp_far_op,           &branch_op,
+        &store_op,                 &branch_op,                &complex_jmp_far_op,       &branch_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 
 /*                                                            REPNE                      REPE*/
 /*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      HLT                        CMC*/
-        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+        &complex_alux1_op,          &complex_alu2_op,           INVALID,                   INVALID,
 /*      CLC                        STC                        CLI                        STI*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+        &complex_alu1_op,           &complex_alu1_op,           &complex_cli_sti_op,        &complex_cli_sti_op,
 /*      CLD                        STD                        INCDEC*/
-        &vector_alu1_op,           &vector_alu1_op,           &alux_store_op,            INVALID
+        &complex_alu1_op,           &complex_alu1_op,           &alux_store_op,            INVALID
 };
 
 static const risc86_instruction_t *opcode_timings_mod3[256] =
@@ -1001,38 +1084,38 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
 /*      ADD                       ADD                       ADD                       ADD*/
 /*00*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      ADD                       ADD                       PUSH ES                   POP ES*/
-        &alux_op,                 &alu_op,                  &push_seg_op,             &vector_mov_seg_mem_op,
+        &alux_op,                 &alu_op,                  &push_seg_op,             &complex_mov_seg_mem_op,
 /*      OR                        OR                        OR                        OR*/
         &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      OR                        OR                        PUSH CS                   */
         &alux_op,                 &alu_op,                  &push_seg_op,             INVALID,
 
 /*      ADC                       ADC                       ADC                       ADC*/
-/*10*/  &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+/*10*/  &complex_alux1_op,        &complex_alu1_op,         &complex_alux1_op,        &complex_alu1_op,
 /*      ADC                       ADC                       PUSH SS                   POP SS*/
-        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+        &complex_alux1_op,        &complex_alu1_op,         &push_seg_op,             &complex_mov_seg_mem_op,
 /*      SBB                       SBB                       SBB                       SBB*/
-        &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+        &complex_alux1_op,        &complex_alu1_op,         &complex_alux1_op,        &complex_alu1_op,
 /*      SBB                       SBB                       PUSH DS                   POP DS*/
-        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+        &complex_alux1_op,        &complex_alu1_op,         &push_seg_op,             &complex_mov_seg_mem_op,
 
 /*      AND                       AND                       AND                       AND*/
 /*20*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      AND                       AND                                                 DAA*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux1_op,
 /*      SUB                       SUB                       SUB                       SUB*/
         &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      SUB                       SUB                                                 DAS*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux1_op,
 
 /*      XOR                       XOR                       XOR                       XOR*/
 /*30*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      XOR                       XOR                                                 AAA*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux6_op,
 /*      CMP                       CMP                       CMP                       CMP*/
         &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      CMP                       CMP                                                 AAS*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux6_op,
 
 /*      INC EAX                INC ECX                INC EDX                INC EBX*/
 /*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
@@ -1053,12 +1136,12 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
         &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
 
 /*      PUSHA                  POPA                   BOUND                  ARPL*/
-/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+/*60*/  &complex_pusha_op,     &complex_popa_op,      &complex_bound_op,     &complex_arpl_op,
         INVALID,               INVALID,               INVALID,               INVALID,
 /*      PUSH imm               IMUL                   PUSH imm               IMUL*/
-        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+        &push_imm_op,          &complex_mul_op,       &push_imm_op,          &complex_mul_op,
 /*      INSB                   INSW                   OUTSB                  OUTSW*/
-        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+        &complex_ins_op,       &complex_ins_op,       &complex_outs_op,      &complex_outs_op,
 
 /*      Jxx*/
 /*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
@@ -1068,29 +1151,29 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
 
 /*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      TEST                       TEST                       XCHG                       XCHG*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_alu3_op,           &vector_alu3_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_alu3_op,          &complex_alu3_op,
 /*      MOV                        MOV                        MOV                        MOV*/
         &store_op,                 &store_op,                 &load_op,                  &load_op,
 /*      MOV from seg               LEA                        MOV to seg                 POP*/
-        &mov_reg_seg_op,           &store_op,                 &vector_mov_seg_reg_op,    &pop_reg_op,
+        &mov_reg_seg_op,           &store_op,                 &complex_mov_seg_reg_op,   &pop_reg_op,
 
 /*      NOP                        XCHG                       XCHG                       XCHG*/
 /*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      XCHG                       XCHG                       XCHG                       XCHG*/
         &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      CBW                        CWD                        CALL far                   WAIT*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_call_far_op,      &limm_op,
 /*      PUSHF                      POPF                       SAHF                       LAHF*/
-        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+        &complex_pushf_op,         &complex_popf_op,          &complex_alux1_op,         &complex_alux1_op,
 
 /*      MOV                        MOV                        MOV                        MOV*/
 /*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
 /*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
-        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+        &movs_op,                  &movs_op,                  &complex_cmpsb_op,         &complex_cmps_op,
 /*      TEST                       TEST                       STOSB                      STOSW*/
         &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
 /*      LODSB                      LODSW                      SCASB                      SCASW*/
-        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+        &lods_op,                  &lods_op,                  &complex_scasb_op,         &complex_scas_op,
 
 /*      MOV*/
 /*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
@@ -1099,57 +1182,57 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
         &limm_op,       &limm_op,       &limm_op,       &limm_op,
 
 /*                                                            RET imm                    RET*/
-/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*c0*/  INVALID,                   INVALID,                   &complex_ret_op,           &complex_ret_op,
 /*      LES                        LDS                        MOV                        MOV*/
-        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+        &complex_lss_op,           &complex_lss_op,           &store_op,                 &store_op,
 /*      ENTER                      LEAVE                      RETF                       RETF*/
-        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+        &complex_enter_op,         &leave_op,                 &complex_retf_op,          &complex_retf_op,
 /*      INT3                       INT                        INTO                       IRET*/
-        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+        &complex_int_op,           &complex_int_op,           &complex_int_op,           &complex_iret_op,
 
 
 /*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      AAM                        AAD                        SETALC                     XLAT*/
-        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        &complex_alux6_op,         &complex_alux3_op,         &complex_alux1_op,         &complex_xlat_op,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
-/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*e0*/  &complex_loop_op,          &complex_loop_op,          &loop_op,                  &complex_loop_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 /*      CALL                       JMP                        JMP                        JMP*/
-        &store_op,                 &branch_op,                &vector_jmp_far_op,        &branch_op,
+        &store_op,                 &branch_op,                &complex_jmp_far_op,       &branch_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 
 /*                                                            REPNE                      REPE*/
 /*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      HLT                        CMC*/
-        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+        &complex_alux1_op,         &complex_alu2_op,          INVALID,                  INVALID,
 /*      CLC                        STC                        CLI                        STI*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_cli_sti_op,       &complex_cli_sti_op,
 /*      CLD                        STD                        INCDEC*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_alux1_op,          INVALID
+        &complex_alu1_op,          &complex_alu1_op,          &complex_alux1_op,        INVALID
 };
 
 static const risc86_instruction_t *opcode_timings_0f[256] =
 {
-/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
-        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
-        INVALID,                &load_op,               &vector_femms_op,       INVALID,
+/*00*/  &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        INVALID,                &complex_alu6_op,       &complex_alu6_op,       INVALID,
+        &complex_invd_op,       &complex_wbinvd_op,     INVALID,                INVALID,
+        INVALID,                &load_op,               &complex_femms_op,      INVALID,
 
 /*10*/  INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
 
-/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
+/*20*/  &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        &complex_alu6_op,       &complex_alu6_op,       INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
 
-/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
+/*30*/  &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,       INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
@@ -1170,7 +1253,7 @@ static const risc86_instruction_t *opcode_timings_0f[256] =
         INVALID,                INVALID,                &mload_op,              &mload_op,
 
 /*70*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
-        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &vector_emms_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &complex_emms_op,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                &mstore_op,             &mstore_op,
 
@@ -1179,122 +1262,122 @@ static const risc86_instruction_t *opcode_timings_0f[256] =
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
 
-/*90*/  &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
-        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
-        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
-        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+/*90*/  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
+        &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
+        &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
+        &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
 
-/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_load_alu_op,
-        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                INVALID,
-        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_load_alu_op,
-        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                &vector_mul_op,
+/*a0*/  &push_seg_op,           &complex_mov_seg_mem_op,&complex_cpuid_op,      &complex_load_alu_op,
+        &complex_alu_store_op,  &complex_alu_store_op,  INVALID,                INVALID,
+        &push_seg_op,           &complex_mov_seg_mem_op,INVALID,                &complex_load_alu_op,
+        &complex_alu_store_op,  &complex_alu_store_op,  INVALID,                &complex_mul_op,
 
-/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_load_alu_op,
-        &vector_lss_op,         &vector_lss_op,         &load_alux_op,          &load_alu_op,
-        INVALID,                INVALID,                &vector_load_alu_op,    &vector_load_alu_op,
-        &vector_bsx_op,         &vector_bsx_op,         &load_alux_op,          &load_alu_op,
+/*b0*/  &complex_cmpxchg_b_op,   &complex_cmpxchg_op,    &complex_lss_op,        &complex_load_alu_op,
+        &complex_lss_op,         &complex_lss_op,        &load_alux_op,          &load_alu_op,
+        INVALID,                 INVALID,                &complex_load_alu_op,   &complex_load_alu_op,
+        &complex_bsx_op,         &complex_bsx_op,        &load_alux_op,          &load_alu_op,
 
-/*c0*/  &vector_alux_store_op,  &vector_alu_store_op,   INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                &vector_cmpxchg_op,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+/*c0*/  &complex_alux_store_op,  &complex_alu_store_op,  INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                &complex_cmpxchg_op,
+        &bswap_op,               &bswap_op,              &bswap_op,              &bswap_op,
+        &bswap_op,               &bswap_op,              &bswap_op,              &bswap_op,
 
-/*d0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
-        INVALID,                &load_mmx_mul_op,       INVALID,                INVALID,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+/*d0*/  INVALID,                 &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                 &load_mmx_mul_op,       INVALID,                INVALID,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
 
-/*e0*/  &load_mmx_op,           &load_mmx_shift_op,     &load_mmx_shift_op,     INVALID,
-        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+/*e0*/  &load_mmx_op,            &load_mmx_shift_op,     &load_mmx_shift_op,     INVALID,
+        INVALID,                 &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
 
-/*f0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
-        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
-        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
-        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
+/*f0*/  INVALID,                 &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                 &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,            &load_mmx_op,           &load_mmx_op,           INVALID,
+        &load_mmx_op,            &load_mmx_op,           &load_mmx_op,           INVALID,
 };
 static const risc86_instruction_t *opcode_timings_0f_mod3[256] =
 {
-/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
-        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
-        INVALID,                INVALID,                &vector_femms_op,       INVALID,
+/*00*/  &complex_alu6_op,        &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        INVALID,                 &complex_alu6_op,       &complex_alu6_op,       INVALID,
+        &complex_invd_op,        &complex_wbinvd_op,     INVALID,                INVALID,
+        INVALID,                 INVALID,                &complex_femms_op,      INVALID,
 
-/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*10*/  INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
 
-/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*20*/  &complex_alu6_op,        &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        &complex_alu6_op,        &complex_alu6_op,       INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
 
-/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*30*/  &complex_alu6_op,        &complex_alu6_op,        &complex_alu6_op,        INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
 
-/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*40*/  INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
 
-/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*50*/  INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
 
-/*60*/  &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
-        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
-        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
-        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+/*60*/  &mmx_op,                 &mmx_op,                 &mmx_op,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 &mmx_op,
+        INVALID,                 INVALID,                 &mmx_op,                 &mmx_op,
 
-/*70*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
-        &mmx_op,                &mmx_op,                &mmx_op,                &vector_emms_op,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+/*70*/  INVALID,                 &mmx_shift_op,           &mmx_shift_op,           &mmx_shift_op,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 &complex_emms_op,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 &mmx_op,                 &mmx_op,
 
 /*80*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
 
-/*90*/  &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
-        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
-        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
-        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+/*90*/  &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
+        &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
+        &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
+        &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
 
-/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_alu1_op,
-        &vector_alu1_op,      &vector_alu1_op,          INVALID,                INVALID,
-        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_alu1_op,
-        &vector_alu1_op,      &vector_alu1_op,          INVALID,                &vector_mul_op,
+/*a0*/  &push_seg_op,            &complex_mov_seg_mem_op, &complex_cpuid_op,       &complex_alu1_op,
+        &complex_alu1_op,        &complex_alu1_op,        INVALID,                 INVALID,
+        &push_seg_op,            &complex_mov_seg_mem_op, INVALID,                 &complex_alu1_op,
+        &complex_alu1_op,        &complex_alu1_op,        INVALID,                 &complex_mul_op,
 
-/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_alu1_op,
-        &vector_lss_op,         &vector_lss_op,         &alux_op,               &alu_op,
-        INVALID,                INVALID,                &vector_alu1_op,        &vector_alu1_op,
-        &vector_bsx_op,         &vector_bsx_op,         &alux_op,               &alu_op,
+/*b0*/  &complex_cmpxchg_b_op,   &complex_cmpxchg_op,     &complex_lss_op,         &complex_alu1_op,
+        &complex_lss_op,         &complex_lss_op,         &alux_op,                &alu_op,
+        INVALID,                 INVALID,                 &complex_alu1_op,        &complex_alu1_op,
+        &complex_bsx_op,         &complex_bsx_op,         &alux_op,                &alu_op,
 
-/*c0*/  &vector_alux1_op,       &vector_alu1_op,        INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+/*c0*/  &complex_alux1_op,       &complex_alu1_op,        INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        &bswap_op,               &bswap_op,               &bswap_op,               &bswap_op,
+        &bswap_op,               &bswap_op,               &bswap_op,               &bswap_op,
 
-/*d0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
-        INVALID,                &mmx_mul_op,            INVALID,                INVALID,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+/*d0*/  INVALID,                 &mmx_shift_op,           &mmx_shift_op,           &mmx_shift_op,
+        INVALID,                 &mmx_mul_op,             INVALID,                 INVALID,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
 
-/*e0*/  &mmx_op,                &mmx_shift_op,          &mmx_shift_op,          INVALID,
-        INVALID,                &pmul_op,               INVALID,                INVALID,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+/*e0*/  &mmx_op,                 &mmx_shift_op,           &mmx_shift_op,           INVALID,
+        INVALID,                 &pmul_op,                INVALID,                 INVALID,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
 
-/*f0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
-        INVALID,                &pmul_op,               INVALID,                INVALID,
-        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
-        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
+/*f0*/  INVALID,                 &mmx_shift_op,           &mmx_shift_op,           &mmx_shift_op,
+        INVALID,                 &pmul_op,                INVALID,                 INVALID,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 INVALID,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 INVALID,
 };
 
 static const risc86_instruction_t *opcode_timings_0f0f[256] =
@@ -1466,100 +1549,100 @@ static const risc86_instruction_t *opcode_timings_0f0f_mod3[256] =
 
 static const risc86_instruction_t *opcode_timings_shift[8] =
 {
-        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,
-        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op
+        &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,
+        &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op
 };
 static const risc86_instruction_t *opcode_timings_shift_b[8] =
 {
-        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,
-        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op
+        &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op,
+        &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op
 };
 static const risc86_instruction_t *opcode_timings_shift_mod3[8] =
 {
-        &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,
-        &alu_op,           &alu_op,           &alu_op,           &alu_op
+        &complex_alu1_op,   &complex_alu1_op,   &complex_alu1_op,   &complex_alu1_op,
+        &alu_op,            &alu_op,            &alu_op,            &alu_op
 };
 static const risc86_instruction_t *opcode_timings_shift_b_mod3[8] =
 {
-        &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,
-        &alux_op,          &alux_op,          &alux_op,          &alux_op
+        &complex_alux1_op,  &complex_alux1_op,  &complex_alux1_op,  &complex_alux1_op,
+        &alux_op,           &alux_op,           &alux_op,           &alux_op
 };
 
 static const risc86_instruction_t *opcode_timings_80[8] =
 {
-        &alux_store_op, &alux_store_op, &vector_alux_store_op,  &vector_alux_store_op,
-        &alux_store_op, &alux_store_op, &alux_store_op,         &alux_store_op,
+        &alux_store_op, &alux_store_op, &complex_alux_store_op,  &complex_alux_store_op,
+        &alux_store_op, &alux_store_op, &alux_store_op,          &alux_store_op,
 };
 static const risc86_instruction_t *opcode_timings_80_mod3[8] =
 {
-        &alux_op,       &alux_op,       &alux_store_op,         &alux_store_op,
-        &alux_op,       &alux_op,       &alux_op,               &alux_op,
+        &alux_op,       &alux_op,       &alux_store_op,          &alux_store_op,
+        &alux_op,       &alux_op,       &alux_op,                &alux_op,
 };
 static const risc86_instruction_t *opcode_timings_8x[8] =
 {
-        &alu_store_op,  &alu_store_op,  &vector_alu_store_op,   &vector_alu_store_op,
-        &alu_store_op,  &alu_store_op,  &alu_store_op,          &alu_store_op,
+        &alu_store_op,  &alu_store_op,  &complex_alu_store_op,   &complex_alu_store_op,
+        &alu_store_op,  &alu_store_op,  &alu_store_op,           &alu_store_op,
 };
 static const risc86_instruction_t *opcode_timings_8x_mod3[8] =
 {
-        &alu_op,        &alu_op,        &alu_store_op,          &alu_store_op,
-        &alu_op,        &alu_op,        &alu_op,                &alu_op,
+        &alu_op,        &alu_op,        &alu_store_op,           &alu_store_op,
+        &alu_op,        &alu_op,        &alu_op,                 &alu_op,
 };
 
 static const risc86_instruction_t *opcode_timings_f6[8] =
 {
 /*      TST                                             NOT                     NEG*/
-        &test_mem_imm_b_op,     INVALID,                &vector_alux_store_op,  &vector_alux_store_op,
+        &test_mem_imm_b_op,     INVALID,                &complex_alux_store_op, &complex_alux_store_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul_mem_op,     &vector_mul_mem_op,     &vector_div16_mem_op,   &vector_div16_mem_op,
+        &complex_mul_mem_op,    &complex_mul_mem_op,    &complex_div16_mem_op,  &complex_div16_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_f6_mod3[8] =
 {
 /*      TST                                             NOT                     NEG*/
         &test_reg_b_op,         INVALID,                &alux_op,               &alux_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul_op,         &vector_mul_op,         &vector_div16_op,       &vector_div16_op,
+        &complex_mul_op,        &complex_mul_op,        &complex_div16_op,      &complex_div16_op,
 };
 static const risc86_instruction_t *opcode_timings_f7[8] =
 {
 /*      TST                                             NOT                     NEG*/
-        &test_mem_imm_op,       INVALID,                &vector_alu_store_op,   &vector_alu_store_op,
+        &test_mem_imm_op,       INVALID,                &complex_alu_store_op,  &complex_alu_store_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul64_mem_op,   &vector_mul64_mem_op,   &vector_div32_mem_op,   &vector_div32_mem_op,
+        &complex_mul64_mem_op,  &complex_mul64_mem_op,  &complex_div32_mem_op,  &complex_div32_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_f7_mod3[8] =
 {
 /*      TST                                             NOT                     NEG*/
         &test_reg_op,           INVALID,                &alu_op,                &alu_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul64_op,       &vector_mul64_op,       &vector_div32_op,       &vector_div32_op,
+        &complex_mul64_op,      &complex_mul64_op,      &complex_div32_op,      &complex_div32_op,
 };
 static const risc86_instruction_t *opcode_timings_ff[8] =
 {
 /*      INC                     DEC                     CALL                    CALL far*/
-        &alu_store_op,          &alu_store_op,          &store_op,              &vector_call_far_op,
+        &alu_store_op,          &alu_store_op,          &store_op,              &complex_call_far_op,
 /*      JMP                     JMP far                 PUSH*/
-        &branch_op,             &vector_jmp_far_op,     &push_mem_op,           INVALID
+        &branch_op,             &complex_jmp_far_op,    &push_mem_op,           INVALID
 };
 static const risc86_instruction_t *opcode_timings_ff_mod3[8] =
 {
 /*      INC                     DEC                     CALL                    CALL far*/
-        &vector_alu1_op,        &vector_alu1_op,        &store_op,              &vector_call_far_op,
+        &complex_alu1_op,       &complex_alu1_op,       &store_op,              &complex_call_far_op,
 /*      JMP                     JMP far                 PUSH*/
-        &branch_op,             &vector_jmp_far_op,     &vector_push_mem_op,    INVALID
+        &branch_op,             &complex_jmp_far_op,    &complex_push_mem_op,   INVALID
 };
 
 static const risc86_instruction_t *opcode_timings_d8[8] =
 {
 /*      FADDs            FMULs            FCOMs            FCOMPs*/
-        &load_float_op,  &load_float_op,  &load_float_op,  &load_float_op,
+        &load_fadd_op,   &load_fmul_op,   &load_float_op,  &load_float_op,
 /*      FSUBs            FSUBRs           FDIVs            FDIVRs*/
         &load_float_op,  &load_float_op,  &fdiv_mem_op,    &fdiv_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_d8_mod3[8] =
 {
 /*      FADD             FMUL             FCOM             FCOMP*/
-        &float_op,       &float_op,       &float_op,       &float_op,
+        &fadd_op,        &fmul_op,        &float_op,       &float_op,
 /*      FSUB             FSUBR            FDIV             FDIVR*/
         &float_op,       &float_op,       &fdiv_op,        &fdiv_op,
 };
@@ -1569,7 +1652,7 @@ static const risc86_instruction_t *opcode_timings_d9[8] =
 /*      FLDs                                    FSTs                 FSTPs*/
         &load_float_op,      INVALID,           &fstore_op,          &fstore_op,
 /*      FLDENV               FLDCW              FSTENV               FSTCW*/
-        &vector_float_l_op,  &vector_fldcw_op,  &vector_float_l_op,  &vector_float_op
+        &complex_float_l_op, &complex_fldcw_op, &complex_float_l_op, &complex_float_op
 };
 static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
 {
@@ -1577,16 +1660,16 @@ static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
         &float_op,    &float_op,    &float_op,    &float_op,
         &float_op,    &float_op,    &float_op,    &float_op,
         /*FXCH*/
-        &float_op,    &float_op,    &float_op,    &float_op,
-        &float_op,    &float_op,    &float_op,    &float_op,
+        &limm_op,     &limm_op,     &limm_op,     &limm_op,
+        &limm_op,     &limm_op,     &limm_op,     &limm_op,
         /*FNOP*/
         &float_op,    INVALID,      INVALID,      INVALID,
         INVALID,      INVALID,      INVALID,      INVALID,
         /*FSTP*/
-        &float_op,    &float_op,    &float_op,    &float_op,
-        &float_op,    &float_op,    &float_op,    &float_op,
+        &float2_op,  &float2_op,  &float2_op,  &float2_op,
+        &float2_op,  &float2_op,  &float2_op,  &float2_op,
 /*      opFCHS        opFABS*/
-        &float_op,    &float_op,    INVALID,      INVALID,
+        &fchs_op,     &float_op,    INVALID,      INVALID,
 /*      opFTST        opFXAM*/
         &float_op,    &float_op,    INVALID,      INVALID,
 /*      opFLD1        opFLDL2T      opFLDL2E      opFLDPI*/
@@ -1606,7 +1689,7 @@ static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
 static const risc86_instruction_t *opcode_timings_da[8] =
 {
 /*      FIADDl            FIMULl            FICOMl            FICOMPl*/
-        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+        &load_fadd_op,    &load_fmul_op,    &load_float_op,   &load_float_op,
 /*      FISUBl            FISUBRl           FIDIVl            FIDIVRl*/
         &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
 };
@@ -1622,7 +1705,7 @@ static const risc86_instruction_t *opcode_timings_db[8] =
 /*      FLDil                               FSTil         FSTPil*/
         &load_float_op,   INVALID,          &fstore_op,   &fstore_op,
 /*                        FLDe                            FSTPe*/
-        INVALID,          &vector_flde_op,  INVALID,      &vector_fste_op
+        INVALID,          &complex_flde_op,  INVALID,     &complex_fste_op
 };
 static const risc86_instruction_t *opcode_timings_db_mod3[64] =
 {
@@ -1656,14 +1739,14 @@ static const risc86_instruction_t *opcode_timings_db_mod3[64] =
 static const risc86_instruction_t *opcode_timings_dc[8] =
 {
 /*      FADDd             FMULd             FCOMd             FCOMPd*/
-        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+        &load_fadd_op,    &load_fmul_op,    &load_float_op,   &load_float_op,
 /*      FSUBd             FSUBRd            FDIVd             FDIVRd*/
         &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_dc_mod3[8] =
 {
 /*      opFADDr           opFMULr*/
-        &float_op,        &float_op,        INVALID,          INVALID,
+        &fadd_op,         &fmul_op,         INVALID,          INVALID,
 /*      opFSUBRr          opFSUBr           opFDIVRr          opFDIVr*/
         &float_op,        &float_op,        &fdiv_op,         &fdiv_op
 };
@@ -1673,7 +1756,7 @@ static const risc86_instruction_t *opcode_timings_dd[8] =
 /*      FLDd                                    FSTd                 FSTPd*/
         &load_float_op,     INVALID,            &fstore_op,          &fstore_op,
 /*      FRSTOR                                  FSAVE                FSTSW*/
-        &vector_float_l_op, INVALID,            &vector_float_l_op,  &vector_float_l_op
+        &complex_float_l_op, INVALID,           &complex_float_l_op, &complex_float_l_op
 };
 static const risc86_instruction_t *opcode_timings_dd_mod3[8] =
 {
@@ -1686,14 +1769,14 @@ static const risc86_instruction_t *opcode_timings_dd_mod3[8] =
 static const risc86_instruction_t *opcode_timings_de[8] =
 {
 /*      FIADDw            FIMULw            FICOMw            FICOMPw*/
-        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+        &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,
 /*      FISUBw            FISUBRw           FIDIVw            FIDIVRw*/
-        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+        &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,
 };
 static const risc86_instruction_t *opcode_timings_de_mod3[8] =
 {
 /*      FADDP            FMULP                          FCOMPP*/
-        &float_op,       &float_op,       INVALID,      &float_op,
+        &fadd_op,        &fmul_op,        INVALID,      &float_op,
 /*      FSUBP            FSUBRP           FDIVP         FDIVRP*/
         &float_op,       &float_op,       &fdiv_op,     &fdiv_op,
 };
@@ -1703,7 +1786,7 @@ static const risc86_instruction_t *opcode_timings_df[8] =
 /*      FILDiw                              FISTiw               FISTPiw*/
         &load_float_op,   INVALID,          &fstore_op,          &fstore_op,
 /*                        FILDiq            FBSTP                FISTPiq*/
-        INVALID,          &load_float_op,   &vector_float_l_op,  &fstore_op,
+        INVALID,          &load_float_op,   &complex_float_l_op, &fstore_op,
 };
 static const risc86_instruction_t *opcode_timings_df_mod3[8] =
 {
@@ -1731,34 +1814,27 @@ static p6_unit_t *units;
 /*Pentium Pro has no MMX*/
 static p6_unit_t ppro_units[] =
 {
-        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX)},                                 /*Integer X*/
-        {.uop_mask = (1 << UOP_ALU)},                                                   /*Integer Y*/
-        {.uop_mask = (1 << UOP_FLOAT)},                                                 /*Floating point*/
-        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},          /*Load*/
-        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)},         /*Store*/
-        {.uop_mask = (1 << UOP_BRANCH)}                                                 /*Branch*/
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT)},      /*Integer X & Floating point*/
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH)},            		/*Integer Y*/
+        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)},          		/*Load*/
+        {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED)},         		/*Data Store*/
+	{.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA)},       		/*Address Store*/
 };
 #define NR_PPRO_UNITS (sizeof(ppro_units) / sizeof(p6_unit_t))
 
-/*Well, it works I guess*/
+/*Pentium II/Celeron assigns the multiplier to port 0, the shifter to port 1, and shares the MMX ALU*/
 static p6_unit_t p2_units[] =
 {
-        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_MEU) |        /*Integer X*/
-                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},
-        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_MEU) |                          /*Integer Y*/
-                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},
-        {.uop_mask = (1 << UOP_FLOAT)},                                         	/*Floating point*/
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT) |              /*Integer X & Floating point*/
+	                 (1 << UOP_MMX) | (1 << UOP_MMX_MUL)},
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH) |                               /*Integer Y*/
+	                 (1 << UOP_MMX) | (1 << UOP_MMX_SHIFT)},           
         {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},  	/*Load*/
-        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)}, 	/*Store*/
-        {.uop_mask = (1 << UOP_BRANCH)}                                         	/*Branch*/
+        {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED) | (1 << UOP_MSTORED)},      /*Data Store*/
+	{.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA) | (1 << UOP_MSTOREA)}, 	/*Address Store*/
 };
 #define NR_P2_UNITS (sizeof(p2_units) / sizeof(p6_unit_t))
 
-/*First available cycles of shared execution units. Each of these can be submitted
-  to by ALU X and Y*/
-static int mul_first_available_cycle;
-static int shift_first_available_cycle;
-
 static int uop_run(const risc86_uop_t *uop, int decode_time)
 {
         int c;
@@ -1767,16 +1843,8 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
         
         /*UOP_LIMM does not require execution*/
         if (uop->type == UOP_LIMM)
-                return decode_time;
+               return decode_time;
 	
-        if (units == p2_units) /*More hackyness*/
-        {
-                if (uop->type == UOP_MEU_MUL && decode_time < mul_first_available_cycle)
-                        decode_time = mul_first_available_cycle;
-                else if (uop->type == UOP_MEU_SHIFT && decode_time < mul_first_available_cycle)
-                        decode_time = shift_first_available_cycle;
-        }
-
         /*Find execution unit for this uOP*/
         for (c = 0; c < nr_units; c++)
         {
@@ -1790,43 +1858,36 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
                 }
         }
         if (!best_unit)
-                fatal("uop_run: can not find execution unit\n");
+                  fatal("uop_run: can not find execution unit\n");
 
         if (best_start_cycle < decode_time)
                 best_start_cycle = decode_time;
-        best_unit->first_available_cycle = best_start_cycle + uop->throughput;
+        best_unit->first_available_cycle = best_start_cycle + uop->latency;
 	
-        if (units == p2_units) /*More hackyness*/
-        {
-                if (uop->type == UOP_MEU_MUL)
-                        mul_first_available_cycle = best_start_cycle + uop->throughput;
-                else if (uop->type == UOP_MEU_SHIFT)
-                        shift_first_available_cycle = best_start_cycle + uop->throughput;
-        }
 
-        return best_start_cycle + uop->throughput;
+
+        return best_start_cycle + uop->latency;
 }
 
-/*The K6 decoder can decode, per clock :
-  - 1 or 2 'short' instructions, each up to 2 uOPs and 7 bytes long
-  - 1 'long' instruction, up to 4 uOPs
-  - 1 'vector' instruction, up to 4 uOPs per cycle, plus (I think) 1 cycle startup delay)
+/*The P6 decoders can decode, per clock :
+  - 1 to 3 'simple' instructions, each up to 1 uOP and 7 bytes long
+  - 1 'complex' instruction, up to 4 uOPs or 3 per cycle for instructions longer than 4 uOPs
 */
 static struct
 {
         int nr_uops;
-        const risc86_uop_t *uops[4];
+        const risc86_uop_t *uops[6];	
         /*Earliest time a uop can start. If the timestamp is -1, then the uop is
           part of a dependency chain and the start time is the completion time of
           the previous uop*/
-        int earliest_start[4];
+        int earliest_start[6];
 } decode_buffer;
 
-#define NR_OPQUADS 6
-/*Timestamps of when the last six opquads completed. The K6 scheduler retires
-  opquads in order, so this is needed to determine when the next can be scheduled*/
-static int opquad_completion_timestamp[NR_OPQUADS];
-static int next_opquad = 0;
+#define NR_OPSEQS 3
+/*Timestamps of when the last three op sequences completed. Technically this is incorrect,
+as the actual size of the opseq buffer is 20 bytes and not 18, but I'm restricted to multiples of 6*/
+static int opseq_completion_timestamp[NR_OPSEQS];
+static int next_opseq = 0;
 
 #define NR_REGS 8
 /*Timestamp of when last operation on an integer register completed*/
@@ -1841,50 +1902,48 @@ void decode_flush_p6()
 {
         int c;
         int uop_timestamp = 0;
-
-        /*Decoded opquad can not be submitted if there are no free spaces in the
-          opquad buffer*/
-        if (decode_timestamp < opquad_completion_timestamp[next_opquad])
-                decode_timestamp = opquad_completion_timestamp[next_opquad];
+	
+        /*Decoded opseq can not be submitted if there are no free spaces in the
+          opseq buffer*/
+        if (decode_timestamp < opseq_completion_timestamp[next_opseq])
+                decode_timestamp = opseq_completion_timestamp[next_opseq];
 
         /*Ensure that uops can not be submitted before they have been decoded*/
         if (decode_timestamp > last_uop_timestamp)
                 last_uop_timestamp = decode_timestamp;
 
         /*Submit uops to execution units, and determine the latest completion time*/
-        for (c = 0; c < decode_buffer.nr_uops; c++)
+        for (c = 0; c < (decode_buffer.nr_uops); c++)
         {
                 int start_timestamp;
                 
-                if (decode_buffer.earliest_start[c] == -1)
-                        start_timestamp = last_uop_timestamp;
-                else
-                        start_timestamp = decode_buffer.earliest_start[c];
+
+                start_timestamp = decode_buffer.earliest_start[c];
                 
                 last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp);
                 if (last_uop_timestamp > uop_timestamp)
                         uop_timestamp = last_uop_timestamp;
         }
 
-        /*Calculate opquad completion time. Since opquads complete in order, it
+        /*Calculate opseq completion time. Since opseqs complete in order, it
           must be after the last completion.*/
         if (uop_timestamp <= last_complete_timestamp)
                 last_complete_timestamp = last_complete_timestamp + 1;
         else
                 last_complete_timestamp = uop_timestamp;
 
-        /*Advance to next opquad in buffer*/
-        opquad_completion_timestamp[next_opquad] = last_complete_timestamp;
-        next_opquad++;
-        if (next_opquad == NR_OPQUADS)
-                next_opquad = 0;
+        /*Advance to next opseq in buffer*/
+        opseq_completion_timestamp[next_opseq] = last_complete_timestamp;
+        next_opseq++;
+        if (next_opseq == NR_OPSEQS)
+                next_opseq = 0;
 
         decode_timestamp++;
         decode_buffer.nr_uops = 0;
 }
 
 /*The instruction is only of interest here if it's longer than 7 bytes, as that's the
-  limit on K6 short decoding*/
+  limit on P6 simple decoding*/
 static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_32)
 {
         int len = prefixes + 1; /*Opcode*/
@@ -1936,8 +1995,9 @@ static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_
 static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8)
 {
         uint32_t regmask_required;
-        uint32_t regmask_modified;
-        int c, d;
+        uint32_t regmask_modified;	
+        int c;
+	int d = 0; /*Complex decoder uOPs*/
         int earliest_start = 0;
         decode_type_t decode_type = ins->decode_type;
         int instr_length = codegen_timing_instr_length(deps, fetchdat, op_32);
@@ -1967,87 +2027,68 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
                         earliest_start = fpu_st_timestamp[reg];
         }
 
-        /*Short decoders are limited to 7 bytes*/
-        if (decode_type == DECODE_SHORT && instr_length > 7)
-                decode_type = DECODE_LONG;
-        /*Long decoder is limited to 11 bytes*/
-        else if (instr_length > 11)
-                decode_type = DECODE_VECTOR;
+        /*Simple decoders are limited to 7 bytes & 1 uOP*/
+        if (decode_type == DECODE_SIMPLE && instr_length > 7)
+                decode_type = DECODE_COMPLEX;
+	else if (decode_type == DECODE_SIMPLE && ins->nr_uops > 1)
+		decode_type = DECODE_COMPLEX;
 
         switch (decode_type)
-        {
-                case DECODE_SHORT:
-                if (decode_buffer.nr_uops)
+        {		
+                case DECODE_SIMPLE:		
+                if (decode_buffer.nr_uops - d == 2)
+                {			
+                        decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
+                        decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
+                        decode_buffer.nr_uops = 3;
+                        decode_flush_p6();
+                }		
+                else if (decode_buffer.nr_uops - d == 1)
+                {			
+                        decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
+                        decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
+                        decode_buffer.nr_uops = 2+d;
+			if (d)
+                        decode_flush_p6();
+                }		
+                else if (decode_buffer.nr_uops)
                 {
                         decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
                         decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
-                        if (ins->nr_uops > 1)
-                        {
-                                decode_buffer.uops[decode_buffer.nr_uops+1] = &ins->uop[1];
-                                decode_buffer.earliest_start[decode_buffer.nr_uops+1] = -1;
-                        }
-                        decode_buffer.nr_uops += ins->nr_uops;
-
-                        decode_flush_p6();
+                        decode_buffer.nr_uops = 1+d;			
                 }
                 else
                 {
-                        decode_buffer.nr_uops = ins->nr_uops;
+                        decode_buffer.nr_uops = 1;
                         decode_buffer.uops[0] = &ins->uop[0];
                         decode_buffer.earliest_start[0] = earliest_start;
-                        if (ins->nr_uops > 1)
-                        {
-                                decode_buffer.uops[1] = &ins->uop[1];
-                                decode_buffer.earliest_start[1] = -1;
-                        }
-                }
+                }		
                 break;
                 
-                case DECODE_LONG:
+                case DECODE_COMPLEX:
                 if (decode_buffer.nr_uops)
-                        decode_flush_p6();
+                        decode_flush_p6(); /*The 4-1-1 arrangement implies that a complex ins. can't be decoded after a simple one*/
                         
-                decode_buffer.nr_uops = ins->nr_uops;
-                for (c = 0; c < ins->nr_uops; c++)
-                {
-                        decode_buffer.uops[c] = &ins->uop[c];
-                        if (c == 0)
-                                decode_buffer.earliest_start[c] = earliest_start;
-                        else
-                                decode_buffer.earliest_start[c] = -1;
-                }
-                decode_flush_p6();
-                break;
-                
-                case DECODE_VECTOR:
-                if (decode_buffer.nr_uops)
-                        decode_flush_p6();
-                        
-                decode_timestamp++;
                 d = 0;
-
+		
                 for (c = 0; c < ins->nr_uops; c++)
                 {
                         decode_buffer.uops[d] = &ins->uop[c];
-                        if (c == 0)
-                                decode_buffer.earliest_start[d] = earliest_start;
-                        else
-                                decode_buffer.earliest_start[d] = -1;
-                        d++;
+                        decode_buffer.earliest_start[c] = earliest_start;
+			d++;
                                 
-                        if (d == 4)
+                        if (d == 3 && ins->nr_uops > 4) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/
                         {
                                 d = 0;
-                                decode_buffer.nr_uops = 4;
-                                decode_flush_p6();
+                                decode_buffer.nr_uops = 3;
+                                decode_flush_p6(); /*The other two decoders are halted to preserve in-order issue*/
                         }
                 }
-                if (d)
-                {
-                        decode_buffer.nr_uops = d;
-                        decode_flush_p6();
-                }
-                break;
+			if (d)
+			{
+                        decode_buffer.nr_uops = d;	
+			}		
+                break;	
         }
 
         /*Update write timestamps for any output registers*/
@@ -2098,15 +2139,12 @@ void codegen_timing_p6_block_start()
         for (c = 0; c < nr_units; c++)
                 units[c].first_available_cycle = 0;
 
-        mul_first_available_cycle = 0;
-        shift_first_available_cycle = 0;
-
         decode_timestamp = 0;
         last_complete_timestamp = 0;
         
-        for (c = 0; c < NR_OPQUADS; c++)
-                opquad_completion_timestamp[c] = 0;
-        next_opquad = 0;
+        for (c = 0; c < NR_OPSEQS; c++)
+                opseq_completion_timestamp[c] = 0;
+        next_opseq = 0;
         
         for (c = 0; c < NR_REGS; c++)
                 reg_available_timestamp[c] = 0;
@@ -2298,7 +2336,7 @@ void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint
         if (ins_table[opcode])
                 decode_instruction(ins_table[opcode], deps[opcode], fetchdat, op_32, bit8);
         else
-                decode_instruction(&vector_alu1_op, 0, fetchdat, op_32, bit8);
+                decode_instruction(&complex_alu1_op, 0, fetchdat, op_32, bit8);
         codegen_block_cycles += (last_complete_timestamp - old_last_complete_timestamp);
 }
 
@@ -2327,4 +2365,4 @@ codegen_timing_t codegen_timing_p6 =
         codegen_timing_p6_block_start,
         codegen_timing_p6_block_end,
         codegen_timing_p6_jump_cycles
-};
+};
\ No newline at end of file
diff --git a/src/cpu_new/codegen_timing_p6.c b/src/cpu_new/codegen_timing_p6.c
index d84a18904..845f46803 100644
--- a/src/cpu_new/codegen_timing_p6.c
+++ b/src/cpu_new/codegen_timing_p6.c
@@ -1,4 +1,5 @@
-/*Hacky P6 timings based on K6 timings*/
+/*Basic P6 timing model by plant/nerd73. Based on the K6 timing model*/
+/*Some cycle timings come from https://www.agner.org/optimize/instruction_tables.pdf*/
 #include <stdint.h>
 #include <86box/86box.h>
 #include "cpu.h"
@@ -18,24 +19,26 @@ typedef enum uop_type_t
         UOP_ALU = 0,   /*Executes in Integer X or Y units*/
         UOP_ALUX,      /*Executes in Integer X unit*/
         UOP_LOAD,      /*Executes in Load unit*/
-        UOP_STORE,     /*Executes in Store unit*/
+        UOP_STORED,    /*Executes in Data Store unit*/
+	UOP_STOREA,    /*Executes in Address Store unit*/
         UOP_FLOAD,     /*Executes in Load unit*/
-        UOP_FSTORE,    /*Executes in Store unit*/
+        UOP_FSTORED,   /*Executes in Data Store unit*/
+	UOP_FSTOREA,   /*Executes in Address Store unit*/
         UOP_MLOAD,     /*Executes in Load unit*/
-        UOP_MSTORE,    /*Executes in Store unit*/
+        UOP_MSTORED,   /*Executes in Data Store unit*/
+        UOP_MSTOREA,   /*Executes in Address Store unit*/
         UOP_FLOAT,     /*Executes in Floating Point unit*/
-        UOP_MEU,       /*Executes in Multimedia unit*/
-        UOP_MEU_SHIFT, /*Executes in Multimedia unit or ALU X/Y. Uses MMX shifter*/
-        UOP_MEU_MUL,   /*Executes in Multimedia unit or ALU X/Y. Uses MMX multiplier*/
+        UOP_MMX,       /*Executes in Integer X or Y units as MMX*/
+        UOP_MMX_SHIFT, /*Executes in Integer Y unit. Uses MMX shifter*/
+        UOP_MMX_MUL,   /*Executes in Integer X unit. Uses MMX multiplier*/
         UOP_BRANCH,    /*Executes in Branch unit*/
         UOP_LIMM       /*Does not require an execution unit*/
 } uop_type_t;
 
 typedef enum decode_type_t
 {
-        DECODE_SHORT,
-        DECODE_LONG,
-        DECODE_VECTOR
+        DECODE_SIMPLE,
+        DECODE_COMPLEX,
 } decode_type_t;
 
 #define MAX_UOPS 10
@@ -43,7 +46,6 @@ typedef enum decode_type_t
 typedef struct risc86_uop_t
 {
         uop_type_t type;
-        double throughput;
         double latency;
 } risc86_uop_t;
 
@@ -57,804 +59,885 @@ typedef struct risc86_instruction_t
 static const risc86_instruction_t alu_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_ALU, .latency = 1}
 };
 static const risc86_instruction_t alux_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1}
 };
 static const risc86_instruction_t load_alu_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t load_alux_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
 };
 static const risc86_instruction_t alu_store_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency = 1},
+        .uop[1] = {.type = UOP_ALU,     .latency = 1},
+        .uop[2] = {.type = UOP_STORED,  .latency = 1},
+        .uop[3] = {.type = UOP_STOREA,  .latency = 1}	
+	};
 static const risc86_instruction_t alux_store_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,    .latency = 1},
+        .uop[2] = {.type = UOP_STORED,  .latency = 1},
+        .uop[3] = {.type = UOP_STOREA,  .latency = 1}		
 };
 
 static const risc86_instruction_t branch_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_BRANCH, .latency = 1}
 };
 
 static const risc86_instruction_t limm_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LIMM, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_LIMM, .latency = 1}
 };
 
 static const risc86_instruction_t load_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1}
 };
 
 static const risc86_instruction_t store_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED,  .latency = 1},
+        .uop[1] = {.type = UOP_STOREA,  .latency = 1}		
 };
 
 
 static const risc86_instruction_t bswap_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,   .latency = 1},	
 };
 static const risc86_instruction_t leave_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1},
+        .uop[2] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t lods_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t loop_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
 };
 static const risc86_instruction_t mov_reg_seg_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
 };
 static const risc86_instruction_t movs_op =
 {
         .nr_uops = 4,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t pop_reg_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t pop_mem_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t push_imm_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_STORE,  .throughput = 1, .latency = 2},
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED,  .latency = 1},
+        .uop[1] = {.type = UOP_STOREA,  .latency = 1},	
 };
 static const risc86_instruction_t push_mem_op =
 {
-        .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1}
 };
 static const risc86_instruction_t push_seg_op =
 {
-        .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},
+	.uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t stos_op =
 {
-        .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t test_reg_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1}
 };
 static const risc86_instruction_t test_reg_b_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,   .latency = 1}
 };
 static const risc86_instruction_t test_mem_imm_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
 };
 static const risc86_instruction_t test_mem_imm_b_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
 };
 static const risc86_instruction_t xchg_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_LONG,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .latency = 1}
 };
 
 
 static const risc86_instruction_t mmx_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX, .latency = 1.5}
 };
 static const risc86_instruction_t mmx_mul_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1.5, .latency = 3}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
 static const risc86_instruction_t mmx_shift_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU_SHIFT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX_SHIFT, .latency = 1.5}
 };
 static const risc86_instruction_t load_mmx_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU,  .throughput = 1.5, .latency = 3}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency =   1},
+        .uop[1] = {.type = UOP_MMX,  .latency = 1.5}
 };
 static const risc86_instruction_t load_mmx_mul_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency =   3},
+        .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
 static const risc86_instruction_t load_mmx_shift_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD,      .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU_SHIFT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,      .latency =   3},
+        .uop[1] = {.type = UOP_MMX_SHIFT, .latency = 1.5}
 };
 static const risc86_instruction_t mload_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MLOAD, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_MLOAD, .latency = 3},
 };
 
 static const risc86_instruction_t mstore_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MSTORE, .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_MSTORED, .latency = 1},
+        .uop[1] = {.type = UOP_MSTOREA, .latency = 1}
 };
 static const risc86_instruction_t pmul_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
 static const risc86_instruction_t pmul_mem_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,    .latency =   3},
+        .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5}
 };
-
 static const risc86_instruction_t float_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 1}
+};
+static const risc86_instruction_t fadd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 3}
+};
+static const risc86_instruction_t fmul_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SIMPLE,
+        .uop[0] = {.type = UOP_ALU, .latency = 5}
+};
+static const risc86_instruction_t float2_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 1}
+};
+static const risc86_instruction_t fchs_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 2},
+        .uop[2] = {.type = UOP_FLOAT, .latency = 2}	
 };
 static const risc86_instruction_t load_float_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_FLOAT, .throughput = 1.5, .latency = 1.5}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 1}
+};
+static const risc86_instruction_t load_fadd_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 3}
+};
+static const risc86_instruction_t load_fmul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 5}
 };
 static const risc86_instruction_t fstore_op =
 {
-        .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FSTORED, .latency = 1},
+        .uop[1] = {.type = UOP_FSTOREA, .latency = 1},
+};
+static const risc86_instruction_t load_fiadd_op =
+{
+        .nr_uops = 7,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[2] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[3] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[4] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[5] = {.type = UOP_FLOAT, .latency = 1},
+        .uop[6] = {.type = UOP_FLOAT, .latency = 1}	
 };
-
 static const risc86_instruction_t fdiv_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 38, .latency = 38}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 32}
 };
 static const risc86_instruction_t fdiv_mem_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_FLOAT, .throughput = 38, .latency = 38}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAT, .latency = 38}
 };
 static const risc86_instruction_t fsin_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 62, .latency = 62}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 60}
 };
 static const risc86_instruction_t fsqrt_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_SHORT,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 49, .latency = 49}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 69}
 };
 
-static const risc86_instruction_t vector_fldcw_op =
+static const risc86_instruction_t complex_fldcw_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 8, .latency = 8}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 10}
 };
-static const risc86_instruction_t vector_float_op =
+static const risc86_instruction_t complex_float_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 1}
 };
-static const risc86_instruction_t vector_float_l_op =
+static const risc86_instruction_t complex_float_l_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 50, .latency = 50}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT, .latency = 50}
 };
-static const risc86_instruction_t vector_flde_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
-        .uop[2] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
-};
-static const risc86_instruction_t vector_fste_op =
+static const risc86_instruction_t complex_flde_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2},
-        .uop[1] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[1] = {.type = UOP_FLOAD, .latency = 1},
+        .uop[2] = {.type = UOP_FLOAT, .latency = 2}
+};
+static const risc86_instruction_t complex_fste_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_FLOAT,   .latency = 2},
+        .uop[1] = {.type = UOP_FSTORED, .latency = 1},
+        .uop[2] = {.type = UOP_FSTOREA, .latency = 1}
 };
 
-static const risc86_instruction_t vector_alu1_op =
+static const risc86_instruction_t complex_alu1_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alu2_op =
+static const risc86_instruction_t complex_alu2_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alu3_op =
+static const risc86_instruction_t complex_alu3_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alu6_op =
+static const risc86_instruction_t complex_alu6_op =
 {
         .nr_uops = 6,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .latency = 1},
+        .uop[3] = {.type = UOP_ALU, .latency = 1},
+        .uop[4] = {.type = UOP_ALU, .latency = 1},
+        .uop[5] = {.type = UOP_ALU, .latency = 1}
 };
-static const risc86_instruction_t vector_alux1_op =
+static const risc86_instruction_t complex_alux1_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1}
 };
-static const risc86_instruction_t vector_alux3_op =
+static const risc86_instruction_t complex_alux3_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .latency = 1}
 };
-static const risc86_instruction_t vector_alux6_op =
+static const risc86_instruction_t complex_alux6_op =
 {
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .nr_uops = 6,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .latency = 1},
+        .uop[3] = {.type = UOP_ALUX, .latency = 1},
+        .uop[4] = {.type = UOP_ALUX, .latency = 1},
+        .uop[5] = {.type = UOP_ALUX, .latency = 1}
 };
-static const risc86_instruction_t vector_alu_store_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_alux_store_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_arpl_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_bound_op =
+static const risc86_instruction_t complex_alu_store_op =
 {
         .nr_uops = 4,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1},	
 };
-static const risc86_instruction_t vector_bsx_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_call_far_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
-        .uop[1] = {.type = UOP_STORE,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_cli_sti_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 7, .latency = 7}
-};
-static const risc86_instruction_t vector_cmps_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_cmpsb_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_cmpxchg_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-};
-static const risc86_instruction_t vector_cmpxchg_b_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-};
-static const risc86_instruction_t vector_cpuid_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 22, .latency = 22}
-};
-static const risc86_instruction_t vector_div16_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_div16_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_div32_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
-};
-static const risc86_instruction_t vector_div32_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
-};
-static const risc86_instruction_t vector_emms_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 25, .latency = 25}
-};
-static const risc86_instruction_t vector_enter_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE,  .throughput =  1, .latency =  2},
-        .uop[1] = {.type = UOP_ALU,    .throughput = 10, .latency = 10}
-};
-static const risc86_instruction_t vector_femms_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 6, .latency = 6}
-};
-static const risc86_instruction_t vector_in_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 10, .latency = 11}
-};
-static const risc86_instruction_t vector_ins_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 10, .latency = 11},
-        .uop[1] = {.type = UOP_STORE, .throughput =  1, .latency =  1},
-        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
-};
-static const risc86_instruction_t vector_int_op =
-{
-        .nr_uops = 5,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
-        .uop[1] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
-        .uop[2] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
-        .uop[3] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
-        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
-};
-static const risc86_instruction_t vector_iret_op =
-{
-        .nr_uops = 5,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
-        .uop[1] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
-        .uop[2] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
-        .uop[3] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
-        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
-};
-static const risc86_instruction_t vector_invd_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 1000, .latency = 1000}
-};
-static const risc86_instruction_t vector_jmp_far_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_load_alu_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_load_alux_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_loop_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_lss_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_mov_mem_seg_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mov_seg_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_mov_seg_reg_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
-};
-static const risc86_instruction_t vector_mul_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mul_mem_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mul64_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_mul64_mem_op =
+static const risc86_instruction_t complex_alux_store_op =
 {
         .nr_uops = 4,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1}	
 };
-static const risc86_instruction_t vector_out_op =
+static const risc86_instruction_t complex_arpl_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,   .latency = 3},
+        .uop[1] = {.type = UOP_ALU,   .latency = 3}
+};
+static const risc86_instruction_t complex_bound_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,  .latency = 1},
+        .uop[3] = {.type = UOP_ALU,  .latency = 1}
+};
+static const risc86_instruction_t complex_bsx_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE, .throughput = 10, .latency = 10}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 10}
 };
-static const risc86_instruction_t vector_outs_op =
+static const risc86_instruction_t complex_call_far_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,     .latency = 3},
+        .uop[1] = {.type = UOP_STORED,  .latency = 1},
+        .uop[2] = {.type = UOP_STOREA,  .latency = 1},	
+        .uop[3] = {.type = UOP_BRANCH,  .latency = 1}
+};
+static const risc86_instruction_t complex_cli_sti_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 7}
+};
+static const risc86_instruction_t complex_cmps_op =
 {
         .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput =  1, .latency =  1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 10, .latency = 10},
-        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 1}
 };
-static const risc86_instruction_t vector_pusha_op =
+static const risc86_instruction_t complex_cmpsb_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_cmpxchg_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_cmpxchg_b_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_STORED, .latency = 1},
+        .uop[3] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_cpuid_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 23}
+};
+static const risc86_instruction_t complex_div16_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 10}
+};
+static const risc86_instruction_t complex_div16_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency =  1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 10}
+};
+static const risc86_instruction_t complex_div32_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 18}
+};
+static const risc86_instruction_t complex_div32_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,  .latency = 18}
+};
+static const risc86_instruction_t complex_emms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 25}
+};
+static const risc86_instruction_t complex_enter_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency =  1},
+        .uop[1] = {.type = UOP_STOREA, .latency =  1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 10}
+};
+static const risc86_instruction_t complex_femms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 6}
+};
+static const risc86_instruction_t complex_in_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 10}
+};
+static const risc86_instruction_t complex_ins_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 10},
+        .uop[1] = {.type = UOP_STORED, .latency =  1},
+        .uop[2] = {.type = UOP_STOREA, .latency =  1},
+        .uop[3] = {.type = UOP_ALU,    .latency =  1}
+};
+static const risc86_instruction_t complex_int_op =
 {
         .nr_uops = 8,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[6] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[7] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,     .latency = 20},
+        .uop[1] = {.type = UOP_STORED,  .latency =  1},
+        .uop[2] = {.type = UOP_STOREA,  .latency =  1},
+        .uop[3] = {.type = UOP_STORED,  .latency =  1},
+        .uop[4] = {.type = UOP_STOREA,  .latency =  1},
+        .uop[5] = {.type = UOP_STORED,  .latency =  1},
+        .uop[6] = {.type = UOP_STOREA,  .latency =  1},	
+        .uop[7] = {.type = UOP_BRANCH,  .latency =  1}
 };
-static const risc86_instruction_t vector_popa_op =
+static const risc86_instruction_t complex_iret_op =
+{
+        .nr_uops = 5,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency =  3},
+        .uop[1] = {.type = UOP_LOAD,   .latency =  3},
+        .uop[2] = {.type = UOP_LOAD,   .latency =  3},
+        .uop[3] = {.type = UOP_ALU,    .latency = 20},
+        .uop[4] = {.type = UOP_BRANCH, .latency =  1}
+};
+static const risc86_instruction_t complex_invd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 500}
+};
+static const risc86_instruction_t complex_jmp_far_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 3},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_load_alu_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
+};
+static const risc86_instruction_t complex_load_alux_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_loop_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_lss_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[2] = {.type = UOP_ALU,    .latency = 3}
+};
+static const risc86_instruction_t complex_mov_mem_seg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},
+};
+static const risc86_instruction_t complex_mov_seg_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 3}
+};
+static const risc86_instruction_t complex_mov_seg_reg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,   .latency = 3}
+};
+static const risc86_instruction_t complex_mul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_mul_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_ALUX,   .latency = 1}
+};
+static const risc86_instruction_t complex_mul64_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_mul64_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[2] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[3] = {.type = UOP_ALUX,   .latency = 1}
+};
+static const risc86_instruction_t complex_out_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency = 10},
+        .uop[1] = {.type = UOP_STOREA, .latency = 10},
+};
+static const risc86_instruction_t complex_outs_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency =  1},
+        .uop[1] = {.type = UOP_STORED, .latency = 10},
+        .uop[1] = {.type = UOP_STOREA, .latency = 10},	
+        .uop[2] = {.type = UOP_ALU,    .latency =  1}
+};
+static const risc86_instruction_t complex_pusha_op =
 {
         .nr_uops = 8,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[3] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[4] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[5] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[6] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[7] = {.type = UOP_LOAD, .throughput = 1, .latency = 1}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency = 2},
+        .uop[1] = {.type = UOP_STOREA, .latency = 2},
+        .uop[2] = {.type = UOP_STORED, .latency = 2},
+        .uop[3] = {.type = UOP_STOREA, .latency = 2},
+        .uop[4] = {.type = UOP_STORED, .latency = 2},
+        .uop[5] = {.type = UOP_STOREA, .latency = 2},
+        .uop[6] = {.type = UOP_STORED, .latency = 2},
+        .uop[7] = {.type = UOP_STOREA, .latency = 2}
 };
-static const risc86_instruction_t vector_popf_op =
+static const risc86_instruction_t complex_popa_op =
+{
+        .nr_uops = 8,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD, .latency = 1},
+        .uop[2] = {.type = UOP_LOAD, .latency = 1},
+        .uop[3] = {.type = UOP_LOAD, .latency = 1},
+        .uop[4] = {.type = UOP_LOAD, .latency = 1},
+        .uop[5] = {.type = UOP_LOAD, .latency = 1},
+        .uop[6] = {.type = UOP_LOAD, .latency = 1},
+        .uop[7] = {.type = UOP_LOAD, .latency = 1}
+};
+static const risc86_instruction_t complex_popf_op =
 {
         .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput =  1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 17, .latency = 17}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency =  3},
+        .uop[1] = {.type = UOP_ALUX, .latency = 17}
 };
-static const risc86_instruction_t vector_push_mem_op =
+static const risc86_instruction_t complex_push_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_STORED, .latency = 1},
+        .uop[1] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_pushf_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_ret_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_retf_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 3},
+        .uop[2] = {.type = UOP_BRANCH, .latency = 1}
+};
+static const risc86_instruction_t complex_scas_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_scasb_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_setcc_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,    .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,    .latency = 1},
+        .uop[2] = {.type = UOP_FSTORED, .latency = 1},
+        .uop[3] = {.type = UOP_FSTOREA, .latency = 1}
+};
+static const risc86_instruction_t complex_setcc_reg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALUX,  .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,  .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .latency = 1}
+};
+static const risc86_instruction_t complex_test_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALU,  .latency = 1}
+};
+static const risc86_instruction_t complex_test_mem_b_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .latency = 1}
+};
+static const risc86_instruction_t complex_xchg_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_LOAD,   .latency = 1},
+        .uop[1] = {.type = UOP_STORED, .latency = 1},
+        .uop[2] = {.type = UOP_STOREA, .latency = 1},	
+        .uop[3] = {.type = UOP_ALU,    .latency = 1}
+};
+static const risc86_instruction_t complex_xlat_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU,    .latency = 1},
+        .uop[1] = {.type = UOP_LOAD,   .latency = 1}
+};
+static const risc86_instruction_t complex_wbinvd_op =
 {
         .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_pushf_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_ret_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_retf_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
-        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_scas_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_scasb_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_setcc_mem_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_setcc_reg_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_test_mem_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_test_mem_b_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
-        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_xchg_mem_op =
-{
-        .nr_uops = 3,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
-        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
-};
-static const risc86_instruction_t vector_xlat_op =
-{
-        .nr_uops = 2,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
-        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2}
-};
-static const risc86_instruction_t vector_wbinvd_op =
-{
-        .nr_uops = 1,
-        .decode_type = DECODE_VECTOR,
-        .uop[0] = {.type = UOP_ALU, .throughput = 10000, .latency = 10000}
+        .decode_type = DECODE_COMPLEX,
+        .uop[0] = {.type = UOP_ALU, .latency = 10000}
 };
 
+
 #define INVALID NULL
 
 static const risc86_instruction_t *opcode_timings[256] =
@@ -862,38 +945,38 @@ static const risc86_instruction_t *opcode_timings[256] =
 /*      ADD                    ADD                    ADD                   ADD*/
 /*00*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      ADD                    ADD                    PUSH ES               POP ES*/
-        &alux_op,              &alu_op,               &push_seg_op,         &vector_mov_seg_mem_op,
+        &alux_op,              &alu_op,               &push_seg_op,         &complex_mov_seg_mem_op,
 /*      OR                     OR                     OR                    OR*/
         &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      OR                     OR                     PUSH CS               */
         &alux_op,              &alu_op,               &push_seg_op,         INVALID,
 
 /*      ADC                    ADC                    ADC                   ADC*/
-/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*10*/  &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op,
 /*      ADC                    ADC                    PUSH SS               POP SS*/
-        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+        &complex_alux1_op,     &complex_alu1_op,      &push_seg_op,         &complex_mov_seg_mem_op,
 /*      SBB                    SBB                    SBB                   SBB*/
-/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*10*/  &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op,
 /*      SBB                    SBB                    PUSH DS               POP DS*/
-        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+        &complex_alux1_op,     &complex_alu1_op,      &push_seg_op,         &complex_mov_seg_mem_op,
 
 /*      AND                    AND                    AND                   AND*/
 /*20*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      AND                    AND                                          DAA*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux1_op,
 /*      SUB                    SUB                    SUB                   SUB*/
         &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      SUB                    SUB                                          DAS*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux1_op,
 
 /*      XOR                    XOR                    XOR                   XOR*/
 /*30*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
 /*      XOR                    XOR                                          AAA*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux6_op,
 /*      CMP                    CMP                    CMP                   CMP*/
         &load_alux_op,         &load_alu_op,          &load_alux_op,        &load_alu_op,
 /*      CMP                    CMP                                          AAS*/
-        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+        &alux_op,              &alu_op,               INVALID,              &complex_alux6_op,
 
 /*      INC EAX                INC ECX                INC EDX                INC EBX*/
 /*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
@@ -914,12 +997,12 @@ static const risc86_instruction_t *opcode_timings[256] =
         &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
 
 /*      PUSHA                  POPA                   BOUND                  ARPL*/
-/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+/*60*/  &complex_pusha_op,     &complex_popa_op,      &complex_bound_op,     &complex_arpl_op,
         INVALID,               INVALID,               INVALID,               INVALID,
 /*      PUSH imm               IMUL                   PUSH imm               IMUL*/
-        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+        &push_imm_op,          &complex_mul_op,       &push_imm_op,          &complex_mul_op,
 /*      INSB                   INSW                   OUTSB                  OUTSW*/
-        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+        &complex_ins_op,       &complex_ins_op,       &complex_outs_op,      &complex_outs_op,
 
 /*      Jxx*/
 /*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
@@ -929,29 +1012,29 @@ static const risc86_instruction_t *opcode_timings[256] =
 
 /*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      TEST                       TEST                       XCHG                       XCHG*/
-        &vector_test_mem_b_op,     &vector_test_mem_op,       &vector_xchg_mem_op,       &vector_xchg_mem_op,
+        &complex_test_mem_b_op,    &complex_test_mem_op,      &complex_xchg_mem_op,      &complex_xchg_mem_op,
 /*      MOV                        MOV                        MOV                        MOV*/
         &store_op,                 &store_op,                 &load_op,                  &load_op,
 /*      MOV from seg               LEA                        MOV to seg                 POP*/
-        &vector_mov_mem_seg_op,    &store_op,                 &vector_mov_seg_mem_op,    &pop_mem_op,
+        &complex_mov_mem_seg_op,   &store_op,                 &complex_mov_seg_mem_op,   &pop_mem_op,
 
 /*      NOP                        XCHG                       XCHG                       XCHG*/
 /*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      XCHG                       XCHG                       XCHG                       XCHG*/
         &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      CBW                        CWD                        CALL far                   WAIT*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_call_far_op,      &limm_op,
 /*      PUSHF                      POPF                       SAHF                       LAHF*/
-        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+        &complex_pushf_op,         &complex_popf_op,          &complex_alux1_op,         &complex_alux1_op,
 
 /*      MOV                        MOV                        MOV                        MOV*/
 /*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
 /*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
-        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+        &movs_op,                  &movs_op,                  &complex_cmpsb_op,         &complex_cmps_op,
 /*      TEST                       TEST                       STOSB                      STOSW*/
         &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
 /*      LODSB                      LODSW                      SCASB                      SCASW*/
-        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+        &lods_op,                  &lods_op,                  &complex_scasb_op,         &complex_scas_op,
 
 /*      MOV*/
 /*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
@@ -960,37 +1043,37 @@ static const risc86_instruction_t *opcode_timings[256] =
         &limm_op,       &limm_op,       &limm_op,       &limm_op,
 
 /*                                                            RET imm                    RET*/
-/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*c0*/  INVALID,                   INVALID,                   &complex_ret_op,           &complex_ret_op,
 /*      LES                        LDS                        MOV                        MOV*/
-        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+        &complex_lss_op,           &complex_lss_op,           &store_op,                 &store_op,
 /*      ENTER                      LEAVE                      RETF                       RETF*/
-        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+        &complex_enter_op,         &leave_op,                 &complex_retf_op,          &complex_retf_op,
 /*      INT3                       INT                        INTO                       IRET*/
-        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+        &complex_int_op,           &complex_int_op,           &complex_int_op,           &complex_iret_op,
 
 
 /*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      AAM                        AAD                        SETALC                     XLAT*/
-        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        &complex_alux6_op,         &complex_alux3_op,         &complex_alux1_op,         &complex_xlat_op,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
-/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*e0*/  &complex_loop_op,          &complex_loop_op,          &loop_op,                  &complex_loop_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 /*      CALL                       JMP                        JMP                        JMP*/
-        &store_op,                 &branch_op,                &vector_jmp_far_op,           &branch_op,
+        &store_op,                 &branch_op,                &complex_jmp_far_op,       &branch_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 
 /*                                                            REPNE                      REPE*/
 /*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      HLT                        CMC*/
-        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+        &complex_alux1_op,          &complex_alu2_op,           INVALID,                   INVALID,
 /*      CLC                        STC                        CLI                        STI*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+        &complex_alu1_op,           &complex_alu1_op,           &complex_cli_sti_op,        &complex_cli_sti_op,
 /*      CLD                        STD                        INCDEC*/
-        &vector_alu1_op,           &vector_alu1_op,           &alux_store_op,            INVALID
+        &complex_alu1_op,           &complex_alu1_op,           &alux_store_op,            INVALID
 };
 
 static const risc86_instruction_t *opcode_timings_mod3[256] =
@@ -998,38 +1081,38 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
 /*      ADD                       ADD                       ADD                       ADD*/
 /*00*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      ADD                       ADD                       PUSH ES                   POP ES*/
-        &alux_op,                 &alu_op,                  &push_seg_op,             &vector_mov_seg_mem_op,
+        &alux_op,                 &alu_op,                  &push_seg_op,             &complex_mov_seg_mem_op,
 /*      OR                        OR                        OR                        OR*/
         &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      OR                        OR                        PUSH CS                   */
         &alux_op,                 &alu_op,                  &push_seg_op,             INVALID,
 
 /*      ADC                       ADC                       ADC                       ADC*/
-/*10*/  &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+/*10*/  &complex_alux1_op,        &complex_alu1_op,         &complex_alux1_op,        &complex_alu1_op,
 /*      ADC                       ADC                       PUSH SS                   POP SS*/
-        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+        &complex_alux1_op,        &complex_alu1_op,         &push_seg_op,             &complex_mov_seg_mem_op,
 /*      SBB                       SBB                       SBB                       SBB*/
-        &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+        &complex_alux1_op,        &complex_alu1_op,         &complex_alux1_op,        &complex_alu1_op,
 /*      SBB                       SBB                       PUSH DS                   POP DS*/
-        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+        &complex_alux1_op,        &complex_alu1_op,         &push_seg_op,             &complex_mov_seg_mem_op,
 
 /*      AND                       AND                       AND                       AND*/
 /*20*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      AND                       AND                                                 DAA*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux1_op,
 /*      SUB                       SUB                       SUB                       SUB*/
         &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      SUB                       SUB                                                 DAS*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux1_op,
 
 /*      XOR                       XOR                       XOR                       XOR*/
 /*30*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      XOR                       XOR                                                 AAA*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux6_op,
 /*      CMP                       CMP                       CMP                       CMP*/
         &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
 /*      CMP                       CMP                                                 AAS*/
-        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+        &alux_op,                 &alu_op,                  INVALID,                  &complex_alux6_op,
 
 /*      INC EAX                INC ECX                INC EDX                INC EBX*/
 /*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
@@ -1050,12 +1133,12 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
         &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
 
 /*      PUSHA                  POPA                   BOUND                  ARPL*/
-/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+/*60*/  &complex_pusha_op,     &complex_popa_op,      &complex_bound_op,     &complex_arpl_op,
         INVALID,               INVALID,               INVALID,               INVALID,
 /*      PUSH imm               IMUL                   PUSH imm               IMUL*/
-        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+        &push_imm_op,          &complex_mul_op,       &push_imm_op,          &complex_mul_op,
 /*      INSB                   INSW                   OUTSB                  OUTSW*/
-        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+        &complex_ins_op,       &complex_ins_op,       &complex_outs_op,      &complex_outs_op,
 
 /*      Jxx*/
 /*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
@@ -1065,29 +1148,29 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
 
 /*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      TEST                       TEST                       XCHG                       XCHG*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_alu3_op,           &vector_alu3_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_alu3_op,          &complex_alu3_op,
 /*      MOV                        MOV                        MOV                        MOV*/
         &store_op,                 &store_op,                 &load_op,                  &load_op,
 /*      MOV from seg               LEA                        MOV to seg                 POP*/
-        &mov_reg_seg_op,           &store_op,                 &vector_mov_seg_reg_op,    &pop_reg_op,
+        &mov_reg_seg_op,           &store_op,                 &complex_mov_seg_reg_op,   &pop_reg_op,
 
 /*      NOP                        XCHG                       XCHG                       XCHG*/
 /*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      XCHG                       XCHG                       XCHG                       XCHG*/
         &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
 /*      CBW                        CWD                        CALL far                   WAIT*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_call_far_op,      &limm_op,
 /*      PUSHF                      POPF                       SAHF                       LAHF*/
-        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+        &complex_pushf_op,         &complex_popf_op,          &complex_alux1_op,         &complex_alux1_op,
 
 /*      MOV                        MOV                        MOV                        MOV*/
 /*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
 /*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
-        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+        &movs_op,                  &movs_op,                  &complex_cmpsb_op,         &complex_cmps_op,
 /*      TEST                       TEST                       STOSB                      STOSW*/
         &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
 /*      LODSB                      LODSW                      SCASB                      SCASW*/
-        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+        &lods_op,                  &lods_op,                  &complex_scasb_op,         &complex_scas_op,
 
 /*      MOV*/
 /*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
@@ -1096,57 +1179,57 @@ static const risc86_instruction_t *opcode_timings_mod3[256] =
         &limm_op,       &limm_op,       &limm_op,       &limm_op,
 
 /*                                                            RET imm                    RET*/
-/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*c0*/  INVALID,                   INVALID,                   &complex_ret_op,           &complex_ret_op,
 /*      LES                        LDS                        MOV                        MOV*/
-        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+        &complex_lss_op,           &complex_lss_op,           &store_op,                 &store_op,
 /*      ENTER                      LEAVE                      RETF                       RETF*/
-        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+        &complex_enter_op,         &leave_op,                 &complex_retf_op,          &complex_retf_op,
 /*      INT3                       INT                        INTO                       IRET*/
-        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+        &complex_int_op,           &complex_int_op,           &complex_int_op,           &complex_iret_op,
 
 
 /*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      AAM                        AAD                        SETALC                     XLAT*/
-        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        &complex_alux6_op,         &complex_alux3_op,         &complex_alux1_op,         &complex_xlat_op,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
         INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
-/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*e0*/  &complex_loop_op,          &complex_loop_op,          &loop_op,                  &complex_loop_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 /*      CALL                       JMP                        JMP                        JMP*/
-        &store_op,                 &branch_op,                &vector_jmp_far_op,        &branch_op,
+        &store_op,                 &branch_op,                &complex_jmp_far_op,       &branch_op,
 /*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
-        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+        &complex_in_op,            &complex_in_op,            &complex_out_op,           &complex_out_op,
 
 /*                                                            REPNE                      REPE*/
 /*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
 /*      HLT                        CMC*/
-        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+        &complex_alux1_op,         &complex_alu2_op,          INVALID,                  INVALID,
 /*      CLC                        STC                        CLI                        STI*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+        &complex_alu1_op,          &complex_alu1_op,          &complex_cli_sti_op,       &complex_cli_sti_op,
 /*      CLD                        STD                        INCDEC*/
-        &vector_alu1_op,           &vector_alu1_op,           &vector_alux1_op,          INVALID
+        &complex_alu1_op,          &complex_alu1_op,          &complex_alux1_op,        INVALID
 };
 
 static const risc86_instruction_t *opcode_timings_0f[256] =
 {
-/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
-        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
-        INVALID,                &load_op,               &vector_femms_op,       INVALID,
+/*00*/  &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        INVALID,                &complex_alu6_op,       &complex_alu6_op,       INVALID,
+        &complex_invd_op,       &complex_wbinvd_op,     INVALID,                INVALID,
+        INVALID,                &load_op,               &complex_femms_op,      INVALID,
 
 /*10*/  INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
 
-/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
+/*20*/  &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        &complex_alu6_op,       &complex_alu6_op,       INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
 
-/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
+/*30*/  &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,       INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                INVALID,                INVALID,
@@ -1167,7 +1250,7 @@ static const risc86_instruction_t *opcode_timings_0f[256] =
         INVALID,                INVALID,                &mload_op,              &mload_op,
 
 /*70*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
-        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &vector_emms_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &complex_emms_op,
         INVALID,                INVALID,                INVALID,                INVALID,
         INVALID,                INVALID,                &mstore_op,             &mstore_op,
 
@@ -1176,122 +1259,122 @@ static const risc86_instruction_t *opcode_timings_0f[256] =
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
 
-/*90*/  &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
-        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
-        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
-        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+/*90*/  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
+        &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
+        &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
+        &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,  &complex_setcc_reg_op,
 
-/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_load_alu_op,
-        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                INVALID,
-        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_load_alu_op,
-        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                &vector_mul_op,
+/*a0*/  &push_seg_op,           &complex_mov_seg_mem_op,&complex_cpuid_op,      &complex_load_alu_op,
+        &complex_alu_store_op,  &complex_alu_store_op,  INVALID,                INVALID,
+        &push_seg_op,           &complex_mov_seg_mem_op,INVALID,                &complex_load_alu_op,
+        &complex_alu_store_op,  &complex_alu_store_op,  INVALID,                &complex_mul_op,
 
-/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_load_alu_op,
-        &vector_lss_op,         &vector_lss_op,         &load_alux_op,          &load_alu_op,
-        INVALID,                INVALID,                &vector_load_alu_op,    &vector_load_alu_op,
-        &vector_bsx_op,         &vector_bsx_op,         &load_alux_op,          &load_alu_op,
+/*b0*/  &complex_cmpxchg_b_op,   &complex_cmpxchg_op,    &complex_lss_op,        &complex_load_alu_op,
+        &complex_lss_op,         &complex_lss_op,        &load_alux_op,          &load_alu_op,
+        INVALID,                 INVALID,                &complex_load_alu_op,   &complex_load_alu_op,
+        &complex_bsx_op,         &complex_bsx_op,        &load_alux_op,          &load_alu_op,
 
-/*c0*/  &vector_alux_store_op,  &vector_alu_store_op,   INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                &vector_cmpxchg_op,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+/*c0*/  &complex_alux_store_op,  &complex_alu_store_op,  INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                &complex_cmpxchg_op,
+        &bswap_op,               &bswap_op,              &bswap_op,              &bswap_op,
+        &bswap_op,               &bswap_op,              &bswap_op,              &bswap_op,
 
-/*d0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
-        INVALID,                &load_mmx_mul_op,       INVALID,                INVALID,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+/*d0*/  INVALID,                 &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                 &load_mmx_mul_op,       INVALID,                INVALID,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
 
-/*e0*/  &load_mmx_op,           &load_mmx_shift_op,     &load_mmx_shift_op,     INVALID,
-        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
-        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+/*e0*/  &load_mmx_op,            &load_mmx_shift_op,     &load_mmx_shift_op,     INVALID,
+        INVALID,                 &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,            &load_mmx_op,           INVALID,                &load_mmx_op,
 
-/*f0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
-        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
-        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
-        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
+/*f0*/  INVALID,                 &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                 &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,            &load_mmx_op,           &load_mmx_op,           INVALID,
+        &load_mmx_op,            &load_mmx_op,           &load_mmx_op,           INVALID,
 };
 static const risc86_instruction_t *opcode_timings_0f_mod3[256] =
 {
-/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
-        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
-        INVALID,                INVALID,                &vector_femms_op,       INVALID,
+/*00*/  &complex_alu6_op,        &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        INVALID,                 &complex_alu6_op,       &complex_alu6_op,       INVALID,
+        &complex_invd_op,        &complex_wbinvd_op,     INVALID,                INVALID,
+        INVALID,                 INVALID,                &complex_femms_op,      INVALID,
 
-/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*10*/  INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
 
-/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
-        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*20*/  &complex_alu6_op,        &complex_alu6_op,       &complex_alu6_op,       &complex_alu6_op,
+        &complex_alu6_op,        &complex_alu6_op,       INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
+        INVALID,                 INVALID,                INVALID,                INVALID,
 
-/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*30*/  &complex_alu6_op,        &complex_alu6_op,        &complex_alu6_op,        INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
 
-/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*40*/  INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
 
-/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
+/*50*/  INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
 
-/*60*/  &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
-        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
-        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
-        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+/*60*/  &mmx_op,                 &mmx_op,                 &mmx_op,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 &mmx_op,
+        INVALID,                 INVALID,                 &mmx_op,                 &mmx_op,
 
-/*70*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
-        &mmx_op,                &mmx_op,                &mmx_op,                &vector_emms_op,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+/*70*/  INVALID,                 &mmx_shift_op,           &mmx_shift_op,           &mmx_shift_op,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 &complex_emms_op,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        INVALID,                 INVALID,                 &mmx_op,                 &mmx_op,
 
 /*80*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
         &branch_op,     &branch_op,     &branch_op,     &branch_op,
 
-/*90*/  &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
-        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
-        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
-        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+/*90*/  &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
+        &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
+        &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
+        &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,   &complex_setcc_mem_op,
 
-/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_alu1_op,
-        &vector_alu1_op,      &vector_alu1_op,          INVALID,                INVALID,
-        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_alu1_op,
-        &vector_alu1_op,      &vector_alu1_op,          INVALID,                &vector_mul_op,
+/*a0*/  &push_seg_op,            &complex_mov_seg_mem_op, &complex_cpuid_op,       &complex_alu1_op,
+        &complex_alu1_op,        &complex_alu1_op,        INVALID,                 INVALID,
+        &push_seg_op,            &complex_mov_seg_mem_op, INVALID,                 &complex_alu1_op,
+        &complex_alu1_op,        &complex_alu1_op,        INVALID,                 &complex_mul_op,
 
-/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_alu1_op,
-        &vector_lss_op,         &vector_lss_op,         &alux_op,               &alu_op,
-        INVALID,                INVALID,                &vector_alu1_op,        &vector_alu1_op,
-        &vector_bsx_op,         &vector_bsx_op,         &alux_op,               &alu_op,
+/*b0*/  &complex_cmpxchg_b_op,   &complex_cmpxchg_op,     &complex_lss_op,         &complex_alu1_op,
+        &complex_lss_op,         &complex_lss_op,         &alux_op,                &alu_op,
+        INVALID,                 INVALID,                 &complex_alu1_op,        &complex_alu1_op,
+        &complex_bsx_op,         &complex_bsx_op,         &alux_op,                &alu_op,
 
-/*c0*/  &vector_alux1_op,       &vector_alu1_op,        INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
-        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+/*c0*/  &complex_alux1_op,       &complex_alu1_op,        INVALID,                 INVALID,
+        INVALID,                 INVALID,                 INVALID,                 INVALID,
+        &bswap_op,               &bswap_op,               &bswap_op,               &bswap_op,
+        &bswap_op,               &bswap_op,               &bswap_op,               &bswap_op,
 
-/*d0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
-        INVALID,                &mmx_mul_op,            INVALID,                INVALID,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+/*d0*/  INVALID,                 &mmx_shift_op,           &mmx_shift_op,           &mmx_shift_op,
+        INVALID,                 &mmx_mul_op,             INVALID,                 INVALID,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
 
-/*e0*/  &mmx_op,                &mmx_shift_op,          &mmx_shift_op,          INVALID,
-        INVALID,                &pmul_op,               INVALID,                INVALID,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
-        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+/*e0*/  &mmx_op,                 &mmx_shift_op,           &mmx_shift_op,           INVALID,
+        INVALID,                 &pmul_op,                INVALID,                 INVALID,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
+        &mmx_op,                 &mmx_op,                 INVALID,                 &mmx_op,
 
-/*f0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
-        INVALID,                &pmul_op,               INVALID,                INVALID,
-        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
-        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
+/*f0*/  INVALID,                 &mmx_shift_op,           &mmx_shift_op,           &mmx_shift_op,
+        INVALID,                 &pmul_op,                INVALID,                 INVALID,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 INVALID,
+        &mmx_op,                 &mmx_op,                 &mmx_op,                 INVALID,
 };
 
 static const risc86_instruction_t *opcode_timings_0f0f[256] =
@@ -1463,100 +1546,100 @@ static const risc86_instruction_t *opcode_timings_0f0f_mod3[256] =
 
 static const risc86_instruction_t *opcode_timings_shift[8] =
 {
-        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,
-        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op
+        &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,
+        &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op
 };
 static const risc86_instruction_t *opcode_timings_shift_b[8] =
 {
-        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,
-        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op
+        &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op,
+        &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op,  &complex_alux_store_op
 };
 static const risc86_instruction_t *opcode_timings_shift_mod3[8] =
 {
-        &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,
-        &alu_op,           &alu_op,           &alu_op,           &alu_op
+        &complex_alu1_op,   &complex_alu1_op,   &complex_alu1_op,   &complex_alu1_op,
+        &alu_op,            &alu_op,            &alu_op,            &alu_op
 };
 static const risc86_instruction_t *opcode_timings_shift_b_mod3[8] =
 {
-        &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,
-        &alux_op,          &alux_op,          &alux_op,          &alux_op
+        &complex_alux1_op,  &complex_alux1_op,  &complex_alux1_op,  &complex_alux1_op,
+        &alux_op,           &alux_op,           &alux_op,           &alux_op
 };
 
 static const risc86_instruction_t *opcode_timings_80[8] =
 {
-        &alux_store_op, &alux_store_op, &vector_alux_store_op,  &vector_alux_store_op,
-        &alux_store_op, &alux_store_op, &alux_store_op,         &alux_store_op,
+        &alux_store_op, &alux_store_op, &complex_alux_store_op,  &complex_alux_store_op,
+        &alux_store_op, &alux_store_op, &alux_store_op,          &alux_store_op,
 };
 static const risc86_instruction_t *opcode_timings_80_mod3[8] =
 {
-        &alux_op,       &alux_op,       &alux_store_op,         &alux_store_op,
-        &alux_op,       &alux_op,       &alux_op,               &alux_op,
+        &alux_op,       &alux_op,       &alux_store_op,          &alux_store_op,
+        &alux_op,       &alux_op,       &alux_op,                &alux_op,
 };
 static const risc86_instruction_t *opcode_timings_8x[8] =
 {
-        &alu_store_op,  &alu_store_op,  &vector_alu_store_op,   &vector_alu_store_op,
-        &alu_store_op,  &alu_store_op,  &alu_store_op,          &alu_store_op,
+        &alu_store_op,  &alu_store_op,  &complex_alu_store_op,   &complex_alu_store_op,
+        &alu_store_op,  &alu_store_op,  &alu_store_op,           &alu_store_op,
 };
 static const risc86_instruction_t *opcode_timings_8x_mod3[8] =
 {
-        &alu_op,        &alu_op,        &alu_store_op,          &alu_store_op,
-        &alu_op,        &alu_op,        &alu_op,                &alu_op,
+        &alu_op,        &alu_op,        &alu_store_op,           &alu_store_op,
+        &alu_op,        &alu_op,        &alu_op,                 &alu_op,
 };
 
 static const risc86_instruction_t *opcode_timings_f6[8] =
 {
 /*      TST                                             NOT                     NEG*/
-        &test_mem_imm_b_op,     INVALID,                &vector_alux_store_op,  &vector_alux_store_op,
+        &test_mem_imm_b_op,     INVALID,                &complex_alux_store_op, &complex_alux_store_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul_mem_op,     &vector_mul_mem_op,     &vector_div16_mem_op,   &vector_div16_mem_op,
+        &complex_mul_mem_op,    &complex_mul_mem_op,    &complex_div16_mem_op,  &complex_div16_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_f6_mod3[8] =
 {
 /*      TST                                             NOT                     NEG*/
         &test_reg_b_op,         INVALID,                &alux_op,               &alux_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul_op,         &vector_mul_op,         &vector_div16_op,       &vector_div16_op,
+        &complex_mul_op,        &complex_mul_op,        &complex_div16_op,      &complex_div16_op,
 };
 static const risc86_instruction_t *opcode_timings_f7[8] =
 {
 /*      TST                                             NOT                     NEG*/
-        &test_mem_imm_op,       INVALID,                &vector_alu_store_op,   &vector_alu_store_op,
+        &test_mem_imm_op,       INVALID,                &complex_alu_store_op,  &complex_alu_store_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul64_mem_op,   &vector_mul64_mem_op,   &vector_div32_mem_op,   &vector_div32_mem_op,
+        &complex_mul64_mem_op,  &complex_mul64_mem_op,  &complex_div32_mem_op,  &complex_div32_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_f7_mod3[8] =
 {
 /*      TST                                             NOT                     NEG*/
         &test_reg_op,           INVALID,                &alu_op,                &alu_op,
 /*      MUL                     IMUL                    DIV                     IDIV*/
-        &vector_mul64_op,       &vector_mul64_op,       &vector_div32_op,       &vector_div32_op,
+        &complex_mul64_op,      &complex_mul64_op,      &complex_div32_op,      &complex_div32_op,
 };
 static const risc86_instruction_t *opcode_timings_ff[8] =
 {
 /*      INC                     DEC                     CALL                    CALL far*/
-        &alu_store_op,          &alu_store_op,          &store_op,              &vector_call_far_op,
+        &alu_store_op,          &alu_store_op,          &store_op,              &complex_call_far_op,
 /*      JMP                     JMP far                 PUSH*/
-        &branch_op,             &vector_jmp_far_op,     &push_mem_op,           INVALID
+        &branch_op,             &complex_jmp_far_op,    &push_mem_op,           INVALID
 };
 static const risc86_instruction_t *opcode_timings_ff_mod3[8] =
 {
 /*      INC                     DEC                     CALL                    CALL far*/
-        &vector_alu1_op,        &vector_alu1_op,        &store_op,              &vector_call_far_op,
+        &complex_alu1_op,       &complex_alu1_op,       &store_op,              &complex_call_far_op,
 /*      JMP                     JMP far                 PUSH*/
-        &branch_op,             &vector_jmp_far_op,     &vector_push_mem_op,    INVALID
+        &branch_op,             &complex_jmp_far_op,    &complex_push_mem_op,   INVALID
 };
 
 static const risc86_instruction_t *opcode_timings_d8[8] =
 {
 /*      FADDs            FMULs            FCOMs            FCOMPs*/
-        &load_float_op,  &load_float_op,  &load_float_op,  &load_float_op,
+        &load_fadd_op,   &load_fmul_op,   &load_float_op,  &load_float_op,
 /*      FSUBs            FSUBRs           FDIVs            FDIVRs*/
         &load_float_op,  &load_float_op,  &fdiv_mem_op,    &fdiv_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_d8_mod3[8] =
 {
 /*      FADD             FMUL             FCOM             FCOMP*/
-        &float_op,       &float_op,       &float_op,       &float_op,
+        &fadd_op,        &fmul_op,        &float_op,       &float_op,
 /*      FSUB             FSUBR            FDIV             FDIVR*/
         &float_op,       &float_op,       &fdiv_op,        &fdiv_op,
 };
@@ -1566,7 +1649,7 @@ static const risc86_instruction_t *opcode_timings_d9[8] =
 /*      FLDs                                    FSTs                 FSTPs*/
         &load_float_op,      INVALID,           &fstore_op,          &fstore_op,
 /*      FLDENV               FLDCW              FSTENV               FSTCW*/
-        &vector_float_l_op,  &vector_fldcw_op,  &vector_float_l_op,  &vector_float_op
+        &complex_float_l_op, &complex_fldcw_op, &complex_float_l_op, &complex_float_op
 };
 static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
 {
@@ -1574,16 +1657,16 @@ static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
         &float_op,    &float_op,    &float_op,    &float_op,
         &float_op,    &float_op,    &float_op,    &float_op,
         /*FXCH*/
-        &float_op,    &float_op,    &float_op,    &float_op,
-        &float_op,    &float_op,    &float_op,    &float_op,
+        &limm_op,     &limm_op,     &limm_op,     &limm_op,
+        &limm_op,     &limm_op,     &limm_op,     &limm_op,
         /*FNOP*/
         &float_op,    INVALID,      INVALID,      INVALID,
         INVALID,      INVALID,      INVALID,      INVALID,
         /*FSTP*/
-        &float_op,    &float_op,    &float_op,    &float_op,
-        &float_op,    &float_op,    &float_op,    &float_op,
+        &float2_op,  &float2_op,  &float2_op,  &float2_op,
+        &float2_op,  &float2_op,  &float2_op,  &float2_op,
 /*      opFCHS        opFABS*/
-        &float_op,    &float_op,    INVALID,      INVALID,
+        &fchs_op,     &float_op,    INVALID,      INVALID,
 /*      opFTST        opFXAM*/
         &float_op,    &float_op,    INVALID,      INVALID,
 /*      opFLD1        opFLDL2T      opFLDL2E      opFLDPI*/
@@ -1603,7 +1686,7 @@ static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
 static const risc86_instruction_t *opcode_timings_da[8] =
 {
 /*      FIADDl            FIMULl            FICOMl            FICOMPl*/
-        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+        &load_fadd_op,    &load_fmul_op,    &load_float_op,   &load_float_op,
 /*      FISUBl            FISUBRl           FIDIVl            FIDIVRl*/
         &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
 };
@@ -1619,7 +1702,7 @@ static const risc86_instruction_t *opcode_timings_db[8] =
 /*      FLDil                               FSTil         FSTPil*/
         &load_float_op,   INVALID,          &fstore_op,   &fstore_op,
 /*                        FLDe                            FSTPe*/
-        INVALID,          &vector_flde_op,  INVALID,      &vector_fste_op
+        INVALID,          &complex_flde_op,  INVALID,     &complex_fste_op
 };
 static const risc86_instruction_t *opcode_timings_db_mod3[64] =
 {
@@ -1653,14 +1736,14 @@ static const risc86_instruction_t *opcode_timings_db_mod3[64] =
 static const risc86_instruction_t *opcode_timings_dc[8] =
 {
 /*      FADDd             FMULd             FCOMd             FCOMPd*/
-        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+        &load_fadd_op,    &load_fmul_op,    &load_float_op,   &load_float_op,
 /*      FSUBd             FSUBRd            FDIVd             FDIVRd*/
         &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
 };
 static const risc86_instruction_t *opcode_timings_dc_mod3[8] =
 {
 /*      opFADDr           opFMULr*/
-        &float_op,        &float_op,        INVALID,          INVALID,
+        &fadd_op,         &fmul_op,         INVALID,          INVALID,
 /*      opFSUBRr          opFSUBr           opFDIVRr          opFDIVr*/
         &float_op,        &float_op,        &fdiv_op,         &fdiv_op
 };
@@ -1670,7 +1753,7 @@ static const risc86_instruction_t *opcode_timings_dd[8] =
 /*      FLDd                                    FSTd                 FSTPd*/
         &load_float_op,     INVALID,            &fstore_op,          &fstore_op,
 /*      FRSTOR                                  FSAVE                FSTSW*/
-        &vector_float_l_op, INVALID,            &vector_float_l_op,  &vector_float_l_op
+        &complex_float_l_op, INVALID,           &complex_float_l_op, &complex_float_l_op
 };
 static const risc86_instruction_t *opcode_timings_dd_mod3[8] =
 {
@@ -1683,14 +1766,14 @@ static const risc86_instruction_t *opcode_timings_dd_mod3[8] =
 static const risc86_instruction_t *opcode_timings_de[8] =
 {
 /*      FIADDw            FIMULw            FICOMw            FICOMPw*/
-        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+        &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,
 /*      FISUBw            FISUBRw           FIDIVw            FIDIVRw*/
-        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+        &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,   &load_fiadd_op,
 };
 static const risc86_instruction_t *opcode_timings_de_mod3[8] =
 {
 /*      FADDP            FMULP                          FCOMPP*/
-        &float_op,       &float_op,       INVALID,      &float_op,
+        &fadd_op,        &fmul_op,        INVALID,      &float_op,
 /*      FSUBP            FSUBRP           FDIVP         FDIVRP*/
         &float_op,       &float_op,       &fdiv_op,     &fdiv_op,
 };
@@ -1700,7 +1783,7 @@ static const risc86_instruction_t *opcode_timings_df[8] =
 /*      FILDiw                              FISTiw               FISTPiw*/
         &load_float_op,   INVALID,          &fstore_op,          &fstore_op,
 /*                        FILDiq            FBSTP                FISTPiq*/
-        INVALID,          &load_float_op,   &vector_float_l_op,  &fstore_op,
+        INVALID,          &load_float_op,   &complex_float_l_op, &fstore_op,
 };
 static const risc86_instruction_t *opcode_timings_df_mod3[8] =
 {
@@ -1728,34 +1811,27 @@ static p6_unit_t *units;
 /*Pentium Pro has no MMX*/
 static p6_unit_t ppro_units[] =
 {
-        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX)},                                 /*Integer X*/
-        {.uop_mask = (1 << UOP_ALU)},                                                   /*Integer Y*/
-        {.uop_mask = (1 << UOP_FLOAT)},                                                 /*Floating point*/
-        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},          /*Load*/
-        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)},         /*Store*/
-        {.uop_mask = (1 << UOP_BRANCH)}                                                 /*Branch*/
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT)},      /*Integer X & Floating point*/
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH)},            		/*Integer Y*/
+        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)},          		/*Load*/
+        {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED)},         		/*Data Store*/
+	{.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA)},       		/*Address Store*/
 };
 #define NR_PPRO_UNITS (sizeof(ppro_units) / sizeof(p6_unit_t))
 
-/*Well, it works I guess*/
+/*Pentium II/Celeron assigns the multiplier to port 0, the shifter to port 1, and shares the MMX ALU*/
 static p6_unit_t p2_units[] =
 {
-        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_MEU) |        /*Integer X*/
-                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},
-        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_MEU) |                          /*Integer Y*/
-                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},
-        {.uop_mask = (1 << UOP_FLOAT)},                                         	/*Floating point*/
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT) |              /*Integer X & Floating point*/
+	                 (1 << UOP_MMX) | (1 << UOP_MMX_MUL)},
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH) |                               /*Integer Y*/
+	                 (1 << UOP_MMX) | (1 << UOP_MMX_SHIFT)},           
         {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},  	/*Load*/
-        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)}, 	/*Store*/
-        {.uop_mask = (1 << UOP_BRANCH)}                                         	/*Branch*/
+        {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED) | (1 << UOP_MSTORED)},      /*Data Store*/
+	{.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA) | (1 << UOP_MSTOREA)}, 	/*Address Store*/
 };
 #define NR_P2_UNITS (sizeof(p2_units) / sizeof(p6_unit_t))
 
-/*First available cycles of shared execution units. Each of these can be submitted
-  to by ALU X and Y*/
-static int mul_first_available_cycle;
-static int shift_first_available_cycle;
-
 static int uop_run(const risc86_uop_t *uop, int decode_time)
 {
         int c;
@@ -1764,16 +1840,8 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
         
         /*UOP_LIMM does not require execution*/
         if (uop->type == UOP_LIMM)
-                return decode_time;
+               return decode_time;
 	
-        if (units == p2_units) /*More hackyness*/
-        {
-                if (uop->type == UOP_MEU_MUL && decode_time < mul_first_available_cycle)
-                        decode_time = mul_first_available_cycle;
-                else if (uop->type == UOP_MEU_SHIFT && decode_time < mul_first_available_cycle)
-                        decode_time = shift_first_available_cycle;
-        }
-
         /*Find execution unit for this uOP*/
         for (c = 0; c < nr_units; c++)
         {
@@ -1787,43 +1855,36 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
                 }
         }
         if (!best_unit)
-                fatal("uop_run: can not find execution unit\n");
+                  fatal("uop_run: can not find execution unit\n");
 
         if (best_start_cycle < decode_time)
                 best_start_cycle = decode_time;
-        best_unit->first_available_cycle = best_start_cycle + uop->throughput;
+        best_unit->first_available_cycle = best_start_cycle + uop->latency;
 	
-        if (units == p2_units) /*More hackyness*/
-        {
-                if (uop->type == UOP_MEU_MUL)
-                        mul_first_available_cycle = best_start_cycle + uop->throughput;
-                else if (uop->type == UOP_MEU_SHIFT)
-                        shift_first_available_cycle = best_start_cycle + uop->throughput;
-        }
 
-        return best_start_cycle + uop->throughput;
+
+        return best_start_cycle + uop->latency;
 }
 
-/*The K6 decoder can decode, per clock :
-  - 1 or 2 'short' instructions, each up to 2 uOPs and 7 bytes long
-  - 1 'long' instruction, up to 4 uOPs
-  - 1 'vector' instruction, up to 4 uOPs per cycle, plus (I think) 1 cycle startup delay)
+/*The P6 decoders can decode, per clock :
+  - 1 to 3 'simple' instructions, each up to 1 uOP and 7 bytes long
+  - 1 'complex' instruction, up to 4 uOPs or 3 per cycle for instructions longer than 4 uOPs
 */
 static struct
 {
         int nr_uops;
-        const risc86_uop_t *uops[4];
+        const risc86_uop_t *uops[6];	
         /*Earliest time a uop can start. If the timestamp is -1, then the uop is
           part of a dependency chain and the start time is the completion time of
           the previous uop*/
-        int earliest_start[4];
+        int earliest_start[6];
 } decode_buffer;
 
-#define NR_OPQUADS 6
-/*Timestamps of when the last six opquads completed. The K6 scheduler retires
-  opquads in order, so this is needed to determine when the next can be scheduled*/
-static int opquad_completion_timestamp[NR_OPQUADS];
-static int next_opquad = 0;
+#define NR_OPSEQS 3
+/*Timestamps of when the last three op sequences completed. Technically this is incorrect,
+as the actual size of the opseq buffer is 20 bytes and not 18, but I'm restricted to multiples of 6*/
+static int opseq_completion_timestamp[NR_OPSEQS];
+static int next_opseq = 0;
 
 #define NR_REGS 8
 /*Timestamp of when last operation on an integer register completed*/
@@ -1838,50 +1899,48 @@ void decode_flush_p6()
 {
         int c;
         int uop_timestamp = 0;
-
-        /*Decoded opquad can not be submitted if there are no free spaces in the
-          opquad buffer*/
-        if (decode_timestamp < opquad_completion_timestamp[next_opquad])
-                decode_timestamp = opquad_completion_timestamp[next_opquad];
+	
+        /*Decoded opseq can not be submitted if there are no free spaces in the
+          opseq buffer*/
+        if (decode_timestamp < opseq_completion_timestamp[next_opseq])
+                decode_timestamp = opseq_completion_timestamp[next_opseq];
 
         /*Ensure that uops can not be submitted before they have been decoded*/
         if (decode_timestamp > last_uop_timestamp)
                 last_uop_timestamp = decode_timestamp;
 
         /*Submit uops to execution units, and determine the latest completion time*/
-        for (c = 0; c < decode_buffer.nr_uops; c++)
+        for (c = 0; c < (decode_buffer.nr_uops); c++)
         {
                 int start_timestamp;
                 
-                if (decode_buffer.earliest_start[c] == -1)
-                        start_timestamp = last_uop_timestamp;
-                else
-                        start_timestamp = decode_buffer.earliest_start[c];
+
+                start_timestamp = decode_buffer.earliest_start[c];
                 
                 last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp);
                 if (last_uop_timestamp > uop_timestamp)
                         uop_timestamp = last_uop_timestamp;
         }
 
-        /*Calculate opquad completion time. Since opquads complete in order, it
+        /*Calculate opseq completion time. Since opseqs complete in order, it
           must be after the last completion.*/
         if (uop_timestamp <= last_complete_timestamp)
                 last_complete_timestamp = last_complete_timestamp + 1;
         else
                 last_complete_timestamp = uop_timestamp;
 
-        /*Advance to next opquad in buffer*/
-        opquad_completion_timestamp[next_opquad] = last_complete_timestamp;
-        next_opquad++;
-        if (next_opquad == NR_OPQUADS)
-                next_opquad = 0;
+        /*Advance to next opseq in buffer*/
+        opseq_completion_timestamp[next_opseq] = last_complete_timestamp;
+        next_opseq++;
+        if (next_opseq == NR_OPSEQS)
+                next_opseq = 0;
 
         decode_timestamp++;
         decode_buffer.nr_uops = 0;
 }
 
 /*The instruction is only of interest here if it's longer than 7 bytes, as that's the
-  limit on K6 short decoding*/
+  limit on P6 simple decoding*/
 static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_32)
 {
         int len = prefixes + 1; /*Opcode*/
@@ -1933,8 +1992,9 @@ static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_
 static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8)
 {
         uint32_t regmask_required;
-        uint32_t regmask_modified;
-        int c, d;
+        uint32_t regmask_modified;	
+        int c;
+	int d = 0; /*Complex decoder uOPs*/
         int earliest_start = 0;
         decode_type_t decode_type = ins->decode_type;
         int instr_length = codegen_timing_instr_length(deps, fetchdat, op_32);
@@ -1964,87 +2024,68 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
                         earliest_start = fpu_st_timestamp[reg];
         }
 
-        /*Short decoders are limited to 7 bytes*/
-        if (decode_type == DECODE_SHORT && instr_length > 7)
-                decode_type = DECODE_LONG;
-        /*Long decoder is limited to 11 bytes*/
-        else if (instr_length > 11)
-                decode_type = DECODE_VECTOR;
+        /*Simple decoders are limited to 7 bytes & 1 uOP*/
+        if (decode_type == DECODE_SIMPLE && instr_length > 7)
+                decode_type = DECODE_COMPLEX;
+	else if (decode_type == DECODE_SIMPLE && ins->nr_uops > 1)
+		decode_type = DECODE_COMPLEX;
 
         switch (decode_type)
-        {
-                case DECODE_SHORT:
-                if (decode_buffer.nr_uops)
+        {		
+                case DECODE_SIMPLE:		
+                if (decode_buffer.nr_uops - d == 2)
+                {			
+                        decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
+                        decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
+                        decode_buffer.nr_uops = 3;
+                        decode_flush_p6();
+                }		
+                else if (decode_buffer.nr_uops - d == 1)
+                {			
+                        decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
+                        decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
+                        decode_buffer.nr_uops = 2+d;
+			if (d)
+                        decode_flush_p6();
+                }		
+                else if (decode_buffer.nr_uops)
                 {
                         decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
                         decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
-                        if (ins->nr_uops > 1)
-                        {
-                                decode_buffer.uops[decode_buffer.nr_uops+1] = &ins->uop[1];
-                                decode_buffer.earliest_start[decode_buffer.nr_uops+1] = -1;
-                        }
-                        decode_buffer.nr_uops += ins->nr_uops;
-
-                        decode_flush_p6();
+                        decode_buffer.nr_uops = 1+d;			
                 }
                 else
                 {
-                        decode_buffer.nr_uops = ins->nr_uops;
+                        decode_buffer.nr_uops = 1;
                         decode_buffer.uops[0] = &ins->uop[0];
                         decode_buffer.earliest_start[0] = earliest_start;
-                        if (ins->nr_uops > 1)
-                        {
-                                decode_buffer.uops[1] = &ins->uop[1];
-                                decode_buffer.earliest_start[1] = -1;
-                        }
-                }
+                }		
                 break;
                 
-                case DECODE_LONG:
+                case DECODE_COMPLEX:
                 if (decode_buffer.nr_uops)
-                        decode_flush_p6();
+                        decode_flush_p6(); /*The 4-1-1 arrangement implies that a complex ins. can't be decoded after a simple one*/
                         
-                decode_buffer.nr_uops = ins->nr_uops;
-                for (c = 0; c < ins->nr_uops; c++)
-                {
-                        decode_buffer.uops[c] = &ins->uop[c];
-                        if (c == 0)
-                                decode_buffer.earliest_start[c] = earliest_start;
-                        else
-                                decode_buffer.earliest_start[c] = -1;
-                }
-                decode_flush_p6();
-                break;
-                
-                case DECODE_VECTOR:
-                if (decode_buffer.nr_uops)
-                        decode_flush_p6();
-                        
-                decode_timestamp++;
                 d = 0;
-
+		
                 for (c = 0; c < ins->nr_uops; c++)
                 {
                         decode_buffer.uops[d] = &ins->uop[c];
-                        if (c == 0)
-                                decode_buffer.earliest_start[d] = earliest_start;
-                        else
-                                decode_buffer.earliest_start[d] = -1;
-                        d++;
+                        decode_buffer.earliest_start[c] = earliest_start;
+			d++;
                                 
-                        if (d == 4)
+                        if (d == 3 && ins->nr_uops > 4) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/
                         {
                                 d = 0;
-                                decode_buffer.nr_uops = 4;
-                                decode_flush_p6();
+                                decode_buffer.nr_uops = 3;
+                                decode_flush_p6(); /*The other two decoders are halted to preserve in-order issue*/
                         }
                 }
-                if (d)
-                {
-                        decode_buffer.nr_uops = d;
-                        decode_flush_p6();
-                }
-                break;
+			if (d)
+			{
+                        decode_buffer.nr_uops = d;	
+			}		
+                break;	
         }
 
         /*Update write timestamps for any output registers*/
@@ -2095,15 +2136,12 @@ void codegen_timing_p6_block_start()
         for (c = 0; c < nr_units; c++)
                 units[c].first_available_cycle = 0;
 
-        mul_first_available_cycle = 0;
-        shift_first_available_cycle = 0;
-
         decode_timestamp = 0;
         last_complete_timestamp = 0;
         
-        for (c = 0; c < NR_OPQUADS; c++)
-                opquad_completion_timestamp[c] = 0;
-        next_opquad = 0;
+        for (c = 0; c < NR_OPSEQS; c++)
+                opseq_completion_timestamp[c] = 0;
+        next_opseq = 0;
         
         for (c = 0; c < NR_REGS; c++)
                 reg_available_timestamp[c] = 0;
@@ -2295,7 +2333,7 @@ void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint
         if (ins_table[opcode])
                 decode_instruction(ins_table[opcode], deps[opcode], fetchdat, op_32, bit8);
         else
-                decode_instruction(&vector_alu1_op, 0, fetchdat, op_32, bit8);
+                decode_instruction(&complex_alu1_op, 0, fetchdat, op_32, bit8);
         codegen_block_cycles += (last_complete_timestamp - old_last_complete_timestamp);
 }
 
@@ -2324,4 +2362,4 @@ codegen_timing_t codegen_timing_p6 =
         codegen_timing_p6_block_start,
         codegen_timing_p6_block_end,
         codegen_timing_p6_jump_cycles
-};
+};
\ No newline at end of file

From 73b51bf5731257e16638b8a8447ded6e82183d2f Mon Sep 17 00:00:00 2001
From: tiseno100 <58827426+tiseno100@users.noreply.github.com>
Date: Sat, 25 Apr 2020 18:59:37 +0300
Subject: [PATCH 38/43] Dev branch all machines with missing SIO chips + added
 the VS440FX

This board returns D4 POST with no output. Needs further examination. Meant for the future PC87307 implementation.

Also all boards that miss their SIO chips got Dev Branched just in case 2.10 gets released while some miss their SIO.
---
 src/machine/m_at_slot1.c      |  6 +++++-
 src/machine/m_at_socket7_s7.c | 11 +++++++----
 src/machine/m_at_socket8.c    | 34 +++++++++++++++++++++++++++++++++-
 src/machine/machine_table.c   | 13 ++++++++++++-
 src/win/Makefile.mingw        | 10 ++++++++++
 src/win/Makefile_ndr.mingw    | 10 ++++++++++
 6 files changed, 77 insertions(+), 7 deletions(-)

diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c
index 800768ce8..46ebe4727 100644
--- a/src/machine/m_at_slot1.c
+++ b/src/machine/m_at_slot1.c
@@ -33,12 +33,14 @@
 #include <86box/intel_sio.h>
 #include <86box/piix.h>
 #include <86box/sio.h>
+#include <86box/intel_sio.h>
 #include <86box/sst_flash.h>
 #include <86box/hwm.h>
 #include <86box/spd.h>
 #include <86box/video.h>
 #include "cpu.h"
 #include <86box/machine.h>
+
 int
 machine_at_p6kfx_init(const machine_t *model)
 {
@@ -69,6 +71,7 @@ machine_at_p6kfx_init(const machine_t *model)
     return ret;
 }
 
+#if defined(DEV_BRANCH) && defined(NO_SIO)
 int
 machine_at_6bxc_init(const machine_t *model)
 {
@@ -93,12 +96,13 @@ machine_at_6bxc_init(const machine_t *model)
     device_add(&i440bx_device);
     device_add(&piix4e_device);
     device_add(&keyboard_ps2_pci_device);
-    device_add(&um8669f_device); /*Placeholder for ITE 8671*/
+    device_add(&um8669f_device); /*ITE 8671*/
     device_add(&sst_flash_39sf020_device);
     spd_register(SPD_TYPE_SDRAM, 0xF, 256);    
 
     return ret;
 }
+#endif
 
 int
 machine_at_p2bls_init(const machine_t *model)
diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c
index 4eb1f963b..3892109b9 100644
--- a/src/machine/m_at_socket7_s7.c
+++ b/src/machine/m_at_socket7_s7.c
@@ -549,6 +549,7 @@ machine_at_pb680_init(const machine_t *model)
     return ret;
 }
 
+#if defined(DEV_BRANCH) && defined(NO_SIO)
 int
 machine_at_p55xb2_init(const machine_t *model)
 {
@@ -577,7 +578,7 @@ machine_at_p55xb2_init(const machine_t *model)
 
     return ret;
 }
-
+#endif
 
 int
 machine_at_tx97_init(const machine_t *model)
@@ -702,7 +703,7 @@ machine_at_ym430tx_init(const machine_t *model)
     return ret;
 }
 
-
+#if defined(DEV_BRANCH) && defined(NO_SIO)
 int
 machine_at_586t2_init(const machine_t *model)
 {
@@ -796,7 +797,7 @@ machine_at_807ds_init(const machine_t *model)
 
     return ret;
 }
-
+#endif
 
 int
 machine_at_p5mms98_init(const machine_t *model)
@@ -862,6 +863,7 @@ machine_at_p5mms98_init(const machine_t *model)
     return ret;
 }
 
+#if defined(DEV_BRANCH) && defined(NO_SIO)
 int
 machine_at_tx100_init(const machine_t *model)
 {
@@ -919,4 +921,5 @@ machine_at_advanceii_init(const machine_t *model)
 	spd_register(SPD_TYPE_SDRAM, 0xF, 64);
 
     return ret;
-}
\ No newline at end of file
+}
+#endif
\ No newline at end of file
diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c
index 14b72dcc7..30c9f5c0a 100644
--- a/src/machine/m_at_socket8.c
+++ b/src/machine/m_at_socket8.c
@@ -156,4 +156,36 @@ machine_at_m6mi_init(const machine_t *model)
     device_add(&intel_flash_bxt_device);
 
     return ret;
-}
\ No newline at end of file
+}
+
+#if defined(DEV_BRANCH) && defined(NO_SIO)
+int
+machine_at_vs440fx_init(const machine_t *model)
+{
+    int ret;
+
+    ret = bios_load_linear_combined2(L"roms/machines/vs440fx/1011CS1_.BIO",
+				     L"roms/machines/vs440fx/1011CS1_.BI1",
+				     L"roms/machines/vs440fx/1011CS1_.BI2",
+				     L"roms/machines/vs440fx/1011CS1_.BI3",
+				     L"roms/machines/vs440fx/1011CS1_.RCV",
+				     0x3a000, 128);
+
+    if (bios_only || !ret)
+	return ret;
+
+    machine_at_common_init(model);
+
+    pci_init(PCI_CONFIG_TYPE_1);
+    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    device_add(&i440fx_device);
+    device_add(&piix3_device);
+    device_add(&keyboard_ps2_ami_pci_device);
+    //device_add(&pc87307_device);
+	device_add(&pc87306_device);
+    device_add(&intel_flash_bxt_ami_device);
+
+    return ret;
+}
+#endif
\ No newline at end of file
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index 8cc0dbfaf..fc2eeab91 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -254,18 +254,24 @@ const machine_t machines[] = {
 
     /* 430TX */
     { "[Socket 7 TX] ASUS TX97",		"tx97",			MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	         machine_at_tx97_init, NULL			},
+#if defined(DEV_BRANCH) && defined(NO_SIO)
     { "[Socket 7 TX] Gigabyte GA-586T2",        "586t2",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_586t2_init, NULL			},
+#endif
     { "[Socket 7 TX] Intel YM430TX",		"ym430tx",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_ym430tx_init, NULL			},
+#if defined(DEV_BRANCH) && defined(NO_SIO)
     { "[Socket 7 TX] Iwill P55XB2",		"p55xb2",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	       machine_at_p55xb2_init, NULL			},
     { "[Socket 7 TX] PC Partner TXA807DS",	"807ds",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	        machine_at_807ds_init, NULL			},
+#endif
     { "[Socket 7 TX] SuperMicro P5MMS98",	"p5mms98",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 255,	      machine_at_p5mms98_init, NULL			},
 
+#if defined(DEV_BRANCH) && defined(NO_SIO)
     /* Apollo VPX */
     { "[Socket 7 VPX] Zida Tomato TX100",	"tx100",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 127,	        machine_at_tx100_init, NULL			},
 
     /* Apollo VP3 */
     { "[Socket 7 VP3] QDI Advance II",		"advanceii",		MACHINE_CPUS_PENTIUM_S7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  128,   8, 127,	    machine_at_advanceii_init, NULL			},
-    
+#endif
+  
     /* Super Socket 7 machines */
     /* Apollo MVP3 */
     { "[Super 7 MVP3] AOpen AX59 Pro",		"ax59pro",		MACHINE_CPUS_PENTIUM_SS7,											    MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8, 1024,  8, 255,	      machine_at_ax59pro_init, NULL			},
@@ -277,6 +283,9 @@ const machine_t machines[] = {
     { "[Socket 8 FX] PC Partner MB600N",	"mb600n",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	       machine_at_mb600n_init, NULL			},
     { "[Socket 8 FX] Biostar MB-8500ttc",	"8500ttc",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  512,   8, 127,	      machine_at_8500ttc_init, NULL			},
     { "[Socket 8 FX] Micronics M6MI",		"m6mi",			{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  384,   8, 127,	         machine_at_m6mi_init, NULL			},
+#if defined(DEV_BRANCH) && defined(NO_SIO)
+    { "[Socket 8 FX] Intel Venus",			"vs440fx",		{{"Intel", cpus_PentiumPro},  {"",    NULL},         {"",      NULL},        {"",      NULL},     {"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,					  8,  256,   8, 127,	         machine_at_vs440fx_init, NULL		},
+#endif
 
     /* Slot 1 machines */
     /* 440FX */
@@ -285,7 +294,9 @@ const machine_t machines[] = {
     /* 440LX */
 
     /* 440BX */
+#if defined(DEV_BRANCH) && defined(NO_SIO)
     { "[Slot 1 BX] Gigabyte GA-6BXC",		"6bxc",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		 machine_at_6bxc_init, NULL			},
+#endif
     { "[Slot 1 BX] ASUS P2B-LS",		"p2bls",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		machine_at_p2bls_init, NULL			},
     { "[Slot 1 BX] ASUS P3B-F",			"p3bf",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_p3bf_init, NULL			},
     { "[Slot 1 BX] ABit BF6",			"bf6",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		  machine_at_bf6_init, NULL			},
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index f8044ddd5..4103f35c0 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -92,6 +92,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef XL24
   XL24		:= y
  endif
+ ifndef NO_SIO
+  NO_SIO	:= y
+ endif
 else
  ifndef DEBUG
   DEBUG		:= n
@@ -150,6 +153,9 @@ else
  ifndef XL24
   XL24		:= n
  endif
+ ifndef NO_SIO
+  NO_SIO	:= n
+ endif
 endif
 
 # Defaults for several build options (possibly defined in a chained file.)
@@ -484,6 +490,10 @@ ifeq ($(XL24), y)
 OPTS		+= -DUSE_XL24
 endif
 
+ifeq ($(NO_SIO), y)
+OPTS		+= -DNO_SIO
+endif
+
 endif
 
 
diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw
index 1a15963e6..b1ec42759 100644
--- a/src/win/Makefile_ndr.mingw
+++ b/src/win/Makefile_ndr.mingw
@@ -92,6 +92,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef XL24
   XL24		:= y
  endif
+ ifndef NO_SIO
+  NO_SIO	:= y
+ endif
 else
  ifndef DEBUG
   DEBUG		:= n
@@ -153,6 +156,9 @@ else
  ifndef XL24
   XL24		:= n
  endif
+ ifndef NO_SIO
+  NO_SIO	:= n
+ endif
 endif
 
 # Defaults for several build options (possibly defined in a chained file.)
@@ -493,6 +499,10 @@ ifeq ($(XL24), y)
 OPTS		+= -DUSE_XL24
 endif
 
+ifeq ($(NO_SIO), y)
+OPTS		+= -DNO_SIO
+endif
+
 endif
 
 

From d8f9a5528601716914cb84d4d244dfe8a5adb50b Mon Sep 17 00:00:00 2001
From: daviunic <simunic.david@outlook.com>
Date: Sat, 25 Apr 2020 18:12:30 +0200
Subject: [PATCH 39/43] Renamed logi bus mouse to logi/ms for clarity

---
 src/mouse_bus.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mouse_bus.c b/src/mouse_bus.c
index e2146a5af..c2b4afad7 100644
--- a/src/mouse_bus.c
+++ b/src/mouse_bus.c
@@ -832,7 +832,7 @@ static const device_config_t ms_config[] = {
 
 
 const device_t mouse_logibus_device = {
-    "Logitech Bus Mouse",
+    "Logitech/Microsoft Bus Mouse",
     DEVICE_ISA,
     MOUSE_TYPE_LOGIBUS,
     bm_init, bm_close, NULL,

From 6033f4480cc1641784e179213cae4890e322372f Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sat, 25 Apr 2020 22:02:48 +0200
Subject: [PATCH 40/43] Fixed P6 timings so they no longer fatal (and removed
 the 3DNow! stuff from them), and also fixed the Distributed DMA bug reported
 by TheCollector1995.

---
 src/cpu/codegen_timing_p6.c     | 243 ++------------------------------
 src/cpu_new/codegen_timing_p6.c | 243 ++------------------------------
 src/ddma.c                      |   4 +-
 3 files changed, 24 insertions(+), 466 deletions(-)

diff --git a/src/cpu/codegen_timing_p6.c b/src/cpu/codegen_timing_p6.c
index a0da30304..db0c965e1 100644
--- a/src/cpu/codegen_timing_p6.c
+++ b/src/cpu/codegen_timing_p6.c
@@ -1380,173 +1380,6 @@ static const risc86_instruction_t *opcode_timings_0f_mod3[256] =
         &mmx_op,                 &mmx_op,                 &mmx_op,                 INVALID,
 };
 
-static const risc86_instruction_t *opcode_timings_0f0f[256] =
-{
-/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,           	INVALID,                INVALID,
-
-/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,           	INVALID,                INVALID,
-
-/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*90*/  INVALID,          	INVALID,                INVALID,           	INVALID,
-        INVALID,          	INVALID,                INVALID,           	INVALID,
-        INVALID,                INVALID,                INVALID,           	INVALID,
-        INVALID,                INVALID,                INVALID,           	INVALID,
-
-/*a0*/  INVALID,           	INVALID,                INVALID,                INVALID,
-        INVALID,           	INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
-        INVALID,                INVALID,               	INVALID,          	INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*b0*/  INVALID,           	INVALID,                INVALID,                INVALID,
-        &load_mmx_mul_op,       INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                &load_mmx_op,
-
-/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-};
-static const risc86_instruction_t *opcode_timings_0f0f_mod3[256] =
-{
-/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*90*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-
-/*a0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                &mmx_mul_op,            &mmx_mul_op,
-        INVALID,                INVALID,                INVALID,               INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-
-/*b0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        &mmx_mul_op,            INVALID,                &mmx_mul_op,            &mmx_mul_op,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                &mmx_op,
-
-/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-};
-
 static const risc86_instruction_t *opcode_timings_shift[8] =
 {
         &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,
@@ -1876,11 +1709,11 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
 static struct
 {
         int nr_uops;
-        const risc86_uop_t *uops[6];	
+        const risc86_uop_t *uops[MAX_UOPS];
         /*Earliest time a uop can start. If the timestamp is -1, then the uop is
           part of a dependency chain and the start time is the completion time of
           the previous uop*/
-        int earliest_start[6];
+        int earliest_start[MAX_UOPS];
 } decode_buffer;
 
 #define NR_OPSEQS 3
@@ -1901,7 +1734,7 @@ static int last_uop_timestamp = 0;
 void decode_flush_p6()
 {
         int c;
-        int uop_timestamp = 0;
+        int start_timestamp, uop_timestamp = 0;
 	
         /*Decoded opseq can not be submitted if there are no free spaces in the
           opseq buffer*/
@@ -1915,9 +1748,6 @@ void decode_flush_p6()
         /*Submit uops to execution units, and determine the latest completion time*/
         for (c = 0; c < (decode_buffer.nr_uops); c++)
         {
-                int start_timestamp;
-                
-
                 start_timestamp = decode_buffer.earliest_start[c];
                 
                 last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp);
@@ -2037,7 +1867,7 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
         {		
                 case DECODE_SIMPLE:		
                 if (decode_buffer.nr_uops - d == 2)
-                {			
+                {
                         decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
                         decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
                         decode_buffer.nr_uops = 3;
@@ -2084,10 +1914,10 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
                                 decode_flush_p6(); /*The other two decoders are halted to preserve in-order issue*/
                         }
                 }
-			if (d)
-			{
-                        decode_buffer.nr_uops = d;	
-			}		
+		if (d)
+		{
+			decode_buffer.nr_uops = d;	
+		}		
                 break;	
         }
 
@@ -2188,59 +2018,8 @@ void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint
         switch (last_prefix)
         {
                 case 0x0f:
-                if (opcode == 0x0f)
-                {
-                        /*3DNow has the actual opcode after ModR/M, SIB and any offset*/
-                        uint32_t opcode_pc = op_pc + 1; /*Byte after ModR/M*/
-                        uint8_t modrm = fetchdat & 0xff;
-                        uint8_t sib = (fetchdat >> 8) & 0xff;
-
-                        if ((modrm & 0xc0) != 0xc0)
-                        {
-                                if (op_32 & 0x200)
-                                {
-                                        if ((modrm & 7) == 4)
-                                        {
-                                                /* Has SIB*/
-                                                opcode_pc++;
-                                                if ((modrm & 0xc0) == 0x40)
-                                                        opcode_pc++;
-                                                else if ((modrm & 0xc0) == 0x80)
-                                                        opcode_pc += 4;
-                                                else if ((sib & 0x07) == 0x05)
-                                                        opcode_pc += 4;
-                                        }
-                                        else
-                                        {
-                                                if ((modrm & 0xc0) == 0x40)
-                                                        opcode_pc++;
-                                                else if ((modrm & 0xc0) == 0x80)
-                                                        opcode_pc += 4;
-                                                else if ((modrm & 0xc7) == 0x05)
-                                                        opcode_pc += 4;
-                                        }
-                                }
-                                else
-                                {
-                                        if ((modrm & 0xc0) == 0x40)
-                                                opcode_pc++;
-                                        else if ((modrm & 0xc0) == 0x80)
-                                                opcode_pc += 2;
-                                        else if ((modrm & 0xc7) == 0x06)
-                                                opcode_pc += 2;
-                                }
-                        }
-                        
-                        opcode = fastreadb(cs + opcode_pc);
-
-                        ins_table = mod3 ? opcode_timings_0f0f_mod3 : opcode_timings_0f0f;
-                        deps = mod3 ? opcode_deps_0f0f_mod3 : opcode_deps_0f0f;
-                }
-                else
-                {
-                        ins_table = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
-                        deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
-                }
+		ins_table = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
+		deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
                 break;
 
                 case 0xd8:
@@ -2365,4 +2144,4 @@ codegen_timing_t codegen_timing_p6 =
         codegen_timing_p6_block_start,
         codegen_timing_p6_block_end,
         codegen_timing_p6_jump_cycles
-};
\ No newline at end of file
+};
diff --git a/src/cpu_new/codegen_timing_p6.c b/src/cpu_new/codegen_timing_p6.c
index 845f46803..d002631bc 100644
--- a/src/cpu_new/codegen_timing_p6.c
+++ b/src/cpu_new/codegen_timing_p6.c
@@ -1377,173 +1377,6 @@ static const risc86_instruction_t *opcode_timings_0f_mod3[256] =
         &mmx_op,                 &mmx_op,                 &mmx_op,                 INVALID,
 };
 
-static const risc86_instruction_t *opcode_timings_0f0f[256] =
-{
-/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,           	INVALID,                INVALID,
-
-/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,           	INVALID,                INVALID,
-
-/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*90*/  INVALID,          	INVALID,                INVALID,           	INVALID,
-        INVALID,          	INVALID,                INVALID,           	INVALID,
-        INVALID,                INVALID,                INVALID,           	INVALID,
-        INVALID,                INVALID,                INVALID,           	INVALID,
-
-/*a0*/  INVALID,           	INVALID,                INVALID,                INVALID,
-        INVALID,           	INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
-        INVALID,                INVALID,               	INVALID,          	INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*b0*/  INVALID,           	INVALID,                INVALID,                INVALID,
-        &load_mmx_mul_op,       INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                &load_mmx_op,
-
-/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-};
-static const risc86_instruction_t *opcode_timings_0f0f_mod3[256] =
-{
-/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*90*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-
-/*a0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                &mmx_mul_op,            &mmx_mul_op,
-        INVALID,                INVALID,                INVALID,               INVALID,
-        INVALID,                INVALID,                INVALID,               INVALID,
-
-/*b0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        &mmx_mul_op,            INVALID,                &mmx_mul_op,            &mmx_mul_op,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                &mmx_op,
-
-/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-        INVALID,                INVALID,                INVALID,                INVALID,
-
-};
-
 static const risc86_instruction_t *opcode_timings_shift[8] =
 {
         &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,   &complex_alu_store_op,
@@ -1873,11 +1706,11 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
 static struct
 {
         int nr_uops;
-        const risc86_uop_t *uops[6];	
+        const risc86_uop_t *uops[MAX_UOPS];
         /*Earliest time a uop can start. If the timestamp is -1, then the uop is
           part of a dependency chain and the start time is the completion time of
           the previous uop*/
-        int earliest_start[6];
+        int earliest_start[MAX_UOPS];
 } decode_buffer;
 
 #define NR_OPSEQS 3
@@ -1898,7 +1731,7 @@ static int last_uop_timestamp = 0;
 void decode_flush_p6()
 {
         int c;
-        int uop_timestamp = 0;
+        int start_timestamp, uop_timestamp = 0;
 	
         /*Decoded opseq can not be submitted if there are no free spaces in the
           opseq buffer*/
@@ -1912,9 +1745,6 @@ void decode_flush_p6()
         /*Submit uops to execution units, and determine the latest completion time*/
         for (c = 0; c < (decode_buffer.nr_uops); c++)
         {
-                int start_timestamp;
-                
-
                 start_timestamp = decode_buffer.earliest_start[c];
                 
                 last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp);
@@ -2034,7 +1864,7 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
         {		
                 case DECODE_SIMPLE:		
                 if (decode_buffer.nr_uops - d == 2)
-                {			
+                {
                         decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
                         decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
                         decode_buffer.nr_uops = 3;
@@ -2081,10 +1911,10 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
                                 decode_flush_p6(); /*The other two decoders are halted to preserve in-order issue*/
                         }
                 }
-			if (d)
-			{
-                        decode_buffer.nr_uops = d;	
-			}		
+		if (d)
+		{
+			decode_buffer.nr_uops = d;	
+		}		
                 break;	
         }
 
@@ -2185,59 +2015,8 @@ void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint
         switch (last_prefix)
         {
                 case 0x0f:
-                if (opcode == 0x0f)
-                {
-                        /*3DNow has the actual opcode after ModR/M, SIB and any offset*/
-                        uint32_t opcode_pc = op_pc + 1; /*Byte after ModR/M*/
-                        uint8_t modrm = fetchdat & 0xff;
-                        uint8_t sib = (fetchdat >> 8) & 0xff;
-
-                        if ((modrm & 0xc0) != 0xc0)
-                        {
-                                if (op_32 & 0x200)
-                                {
-                                        if ((modrm & 7) == 4)
-                                        {
-                                                /* Has SIB*/
-                                                opcode_pc++;
-                                                if ((modrm & 0xc0) == 0x40)
-                                                        opcode_pc++;
-                                                else if ((modrm & 0xc0) == 0x80)
-                                                        opcode_pc += 4;
-                                                else if ((sib & 0x07) == 0x05)
-                                                        opcode_pc += 4;
-                                        }
-                                        else
-                                        {
-                                                if ((modrm & 0xc0) == 0x40)
-                                                        opcode_pc++;
-                                                else if ((modrm & 0xc0) == 0x80)
-                                                        opcode_pc += 4;
-                                                else if ((modrm & 0xc7) == 0x05)
-                                                        opcode_pc += 4;
-                                        }
-                                }
-                                else
-                                {
-                                        if ((modrm & 0xc0) == 0x40)
-                                                opcode_pc++;
-                                        else if ((modrm & 0xc0) == 0x80)
-                                                opcode_pc += 2;
-                                        else if ((modrm & 0xc7) == 0x06)
-                                                opcode_pc += 2;
-                                }
-                        }
-                        
-                        opcode = fastreadb(cs + opcode_pc);
-
-                        ins_table = mod3 ? opcode_timings_0f0f_mod3 : opcode_timings_0f0f;
-                        deps = mod3 ? opcode_deps_0f0f_mod3 : opcode_deps_0f0f;
-                }
-                else
-                {
-                        ins_table = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
-                        deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
-                }
+		ins_table = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
+		deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
                 break;
 
                 case 0xd8:
@@ -2362,4 +2141,4 @@ codegen_timing_t codegen_timing_p6 =
         codegen_timing_p6_block_start,
         codegen_timing_p6_block_end,
         codegen_timing_p6_jump_cycles
-};
\ No newline at end of file
+};
diff --git a/src/ddma.c b/src/ddma.c
index 98e4da293..92ee1f4d3 100644
--- a/src/ddma.c
+++ b/src/ddma.c
@@ -107,9 +107,9 @@ ddma_reg_write(uint16_t addr, uint8_t val, void *p)
 		break;
 	case 0x02:
 		if (ch >= 4)
-			outb(0x88 + page_regs[ch], val);
+			outb(0x88 + page_regs[ch & 3], val);
 		else
-			outb(0x80 + page_regs[ch], val);
+			outb(0x80 + page_regs[ch & 3], val);
 		break;
 	case 0x04:
 		dma[ch].cb = (dma[ch].cb & 0xffff00) | val;

From 20cf306d44dbc15d70f6fab1f1ca5fe94b91d5d7 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sat, 25 Apr 2020 22:14:43 +0200
Subject: [PATCH 41/43] Better fix for the P6 timings.

---
 src/cpu/codegen_timing_p6.c     | 8 ++++----
 src/cpu_new/codegen_timing_p6.c | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/cpu/codegen_timing_p6.c b/src/cpu/codegen_timing_p6.c
index db0c965e1..ec5c54640 100644
--- a/src/cpu/codegen_timing_p6.c
+++ b/src/cpu/codegen_timing_p6.c
@@ -1709,11 +1709,11 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
 static struct
 {
         int nr_uops;
-        const risc86_uop_t *uops[MAX_UOPS];
+        const risc86_uop_t *uops[6];
         /*Earliest time a uop can start. If the timestamp is -1, then the uop is
           part of a dependency chain and the start time is the completion time of
           the previous uop*/
-        int earliest_start[MAX_UOPS];
+        int earliest_start[6];
 } decode_buffer;
 
 #define NR_OPSEQS 3
@@ -1904,10 +1904,10 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
                 for (c = 0; c < ins->nr_uops; c++)
                 {
                         decode_buffer.uops[d] = &ins->uop[c];
-                        decode_buffer.earliest_start[c] = earliest_start;
+                        decode_buffer.earliest_start[d] = earliest_start;
 			d++;
                                 
-                        if (d == 3 && ins->nr_uops > 4) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/
+                        if ((d == 3) && (ins->nr_uops > 4)) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/
                         {
                                 d = 0;
                                 decode_buffer.nr_uops = 3;
diff --git a/src/cpu_new/codegen_timing_p6.c b/src/cpu_new/codegen_timing_p6.c
index d002631bc..a51b4df32 100644
--- a/src/cpu_new/codegen_timing_p6.c
+++ b/src/cpu_new/codegen_timing_p6.c
@@ -1706,11 +1706,11 @@ static int uop_run(const risc86_uop_t *uop, int decode_time)
 static struct
 {
         int nr_uops;
-        const risc86_uop_t *uops[MAX_UOPS];
+        const risc86_uop_t *uops[6];
         /*Earliest time a uop can start. If the timestamp is -1, then the uop is
           part of a dependency chain and the start time is the completion time of
           the previous uop*/
-        int earliest_start[MAX_UOPS];
+        int earliest_start[6];
 } decode_buffer;
 
 #define NR_OPSEQS 3
@@ -1901,10 +1901,10 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u
                 for (c = 0; c < ins->nr_uops; c++)
                 {
                         decode_buffer.uops[d] = &ins->uop[c];
-                        decode_buffer.earliest_start[c] = earliest_start;
+                        decode_buffer.earliest_start[d] = earliest_start;
 			d++;
                                 
-                        if (d == 3 && ins->nr_uops > 4) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/
+                        if ((d == 3) && (ins->nr_uops > 4)) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/
                         {
                                 d = 0;
                                 decode_buffer.nr_uops = 3;

From e6ccbd2406b741d6a5b73e5139f6258451bf7367 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sat, 25 Apr 2020 22:37:07 +0200
Subject: [PATCH 42/43] Bumped maximum UDMA mode from 2 (ATA 33) to 4 (ATA 66)
 so it can be used where supported.

---
 src/disk/hdc_ide.c    | 2 +-
 src/disk/mo.c         | 2 +-
 src/disk/zip.c        | 2 +-
 src/scsi/scsi_cdrom.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c
index 2b6104ee8..0c0453cb1 100644
--- a/src/disk/hdc_ide.c
+++ b/src/disk/hdc_ide.c
@@ -410,7 +410,7 @@ ide_get_max(ide_t *ide, int type)
 		return -1;
 	case TYPE_UDMA:	/* UDMA */
 		if (!ide_boards[ide->board]->force_ata3 && (ide_bm[ide->board] != NULL))
-			return 2;
+			return 4 /*2*/;
 
 		return -1;
 	default:
diff --git a/src/disk/mo.c b/src/disk/mo.c
index 289a3d187..1687d37f3 100644
--- a/src/disk/mo.c
+++ b/src/disk/mo.c
@@ -1983,7 +1983,7 @@ mo_get_max(int ide_has_dma, int type)
 		ret = ide_has_dma ? 1 : -1;
 		break;
 	case TYPE_UDMA:
-		ret = ide_has_dma ? 2 : -1;
+		ret = ide_has_dma ? 4 /*2*/ : -1;
 		break;
     }
 
diff --git a/src/disk/zip.c b/src/disk/zip.c
index 850468573..8a6253100 100644
--- a/src/disk/zip.c
+++ b/src/disk/zip.c
@@ -2243,7 +2243,7 @@ zip_get_max(int ide_has_dma, int type)
 		ret = ide_has_dma ? 1 : -1;
 		break;
 	case TYPE_UDMA:
-		ret = ide_has_dma ? 2 : -1;
+		ret = ide_has_dma ? 4 /*2*/ : -1;
 		break;
     }
 
diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c
index 2944335ee..106e2bb87 100644
--- a/src/scsi/scsi_cdrom.c
+++ b/src/scsi/scsi_cdrom.c
@@ -2595,7 +2595,7 @@ scsi_cdrom_get_max(int ide_has_dma, int type)
 		ret = ide_has_dma ? 2 : -1;
 		break;
 	case TYPE_UDMA:
-		ret = ide_has_dma ? 2 : -1;
+		ret = ide_has_dma ? 4 /*2*/ : -1;
 		break;
 	default:
 		ret = -1;

From 3aaf9ac6fe241d5a81277f890dff11fad0f3e9cd Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sun, 26 Apr 2020 00:49:46 +0200
Subject: [PATCH 43/43] More ACPI improvements, implementation of VIA ACPI (yet
 to be hooked to the southbridges), removed ISABugger stuff from acpi.h,
 apm.h, dma.h, and usb.h, and updated the descriptions in piix.c and piix.h.

---
 src/acpi.c               | 412 ++++++++++++++++++++++++++++++++++++---
 src/apm.c                |  18 +-
 src/include/86box/acpi.h |  30 +--
 src/include/86box/apm.h  |   9 +-
 src/include/86box/ddma.h |   7 -
 src/include/86box/piix.h |   3 +-
 src/include/86box/usb.h  |   7 -
 src/intel_piix.c         |  23 ++-
 8 files changed, 437 insertions(+), 72 deletions(-)

diff --git a/src/acpi.c b/src/acpi.c
index 26855a743..d8555cb95 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -32,6 +32,7 @@
 #include <86box/keyboard.h>
 #include <86box/nvr.h>
 #include <86box/pit.h>
+#include <86box/apm.h>
 #include <86box/acpi.h>
 
 
@@ -77,8 +78,28 @@ acpi_update_irq(void *priv)
 }
 
 
+static void
+acpi_raise_smi(void *priv)
+{
+    acpi_t *dev = (acpi_t *) priv;
+
+    if (dev->vendor == VEN_VIA) {
+	    if ((dev->regs.glbctl & 0x01) && (!dev->regs.smi_lock || !dev->regs.smi_active)) {
+		smi_line = 1;
+		dev->regs.smi_active = 1;
+    	}
+    } else {
+	if (dev->regs.glbctl & 0x01) {
+		smi_line = 1;
+		/* Clear bit 16 of GLBCTL. */
+		dev->regs.glbctl &= ~0x00010000;
+	}
+    }
+}
+
+
 static uint32_t
-acpi_reg_read_common(int size, uint16_t addr, void *p)
+acpi_reg_read_intel(int size, uint16_t addr, void *p)
 {
     acpi_t *dev = (acpi_t *) p;
     uint32_t ret = 0x00000000;
@@ -117,16 +138,6 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
 		/* PCNTRL - Processor Control Register (IO) */
 		ret = (dev->regs.pcntrl >> shift32) & 0xff;
 		break;
-	case 0x14:
-		/* PLVL2 - Processor Level 2 Register (IO) */
-		if (size == 1)
-			ret = dev->regs.plvl2;
-		break;
-	case 0x15:
-		/* PLVL3 - Processor Level 3 Register (IO) */
-		if (size == 1)
-			ret = dev->regs.plvl3;
-		break;
 	case 0x18: case 0x19:
 		/* GLBSTS - Global Status Register (IO) */
 		ret = (dev->regs.glbsts >> shift16) & 0xff;
@@ -173,8 +184,118 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
 }
 
 
+static uint32_t
+acpi_reg_read_via(int size, uint16_t addr, void *p)
+{
+    acpi_t *dev = (acpi_t *) p;
+    uint32_t ret = 0x00000000;
+    int shift16, shift32;
+
+    addr &= 0xff;
+    shift16 = (addr & 1) << 3;
+    shift32 = (addr & 3) << 3;
+
+    switch (addr) {
+	case 0x00: case 0x01:
+		/* PMSTS - Power Management Status Register (IO) */
+		ret = (dev->regs.pmsts >> shift16) & 0xff;
+		break;
+	case 0x02: case 0x03:
+		/* PMEN - Power Management Resume Enable Register (IO) */
+		ret = (dev->regs.pmen >> shift16) & 0xff;
+		break;
+	case 0x04: case 0x05:
+		/* PMCNTRL - Power Management Control Register (IO) */
+		ret = (dev->regs.pmcntrl >> shift16) & 0xff;
+		break;
+	case 0x08: case 0x09: case 0x0a: case 0x0b:
+		/* PMTMR - Power Management Timer Register (IO) */
+		ret = (dev->regs.timer_val >> shift32) & 0xff;
+		break;
+	case 0x10: case 0x11: case 0x12: case 0x13:
+		/* PCNTRL - Processor Control Register (IO) */
+		ret = (dev->regs.pcntrl >> shift32) & 0xff;
+		break;
+	case 0x20: case 0x21:
+		/* GPSTS - General Purpose Status Register (IO) */
+		ret = (dev->regs.gpsts >> shift16) & 0xff;
+		break;
+	case 0x22: case 0x23:
+		/* General Purpose SCI Enable */
+		ret = (dev->regs.gpscien >> shift16) & 0xff;
+		break;
+	case 0x24: case 0x25:
+		/* General Purpose SMI Enable */
+		ret = (dev->regs.gpsmien >> shift16) & 0xff;
+		break;
+	case 0x26: case 0x27:
+		/* Power Supply Control */
+		ret = (dev->regs.pscntrl >> shift16) & 0xff;
+		break;
+	case 0x28: case 0x29:
+		/* GLBSTS - Global Status Register (IO) */
+		ret = (dev->regs.glbsts >> shift16) & 0xff;
+		break;
+	case 0x2a: case 0x2b:
+		/* GLBEN - Global Enable Register (IO) */
+		ret = (dev->regs.glben >> shift16) & 0xff;
+		break;
+	case 0x2c: case 0x2d:
+		/* GLBCTL - Global Control Register (IO) */
+		ret = (dev->regs.glbctl >> shift16) & 0xff;
+		ret &= ~0x0110;
+		ret |= (dev->regs.smi_lock ? 0x10 : 0x00);
+		ret |= (dev->regs.smi_active ? 0x01 : 0x00);
+		break;
+	case 0x2f:
+		/* SMI Command */
+		if (size == 1)
+			ret = dev->regs.smicmd & 0xff;
+		break;
+	case 0x30: case 0x31: case 0x32: case 0x33:
+		/* Primary Activity Detect Status */
+		ret = (dev->regs.padsts >> shift32) & 0xff;
+		break;
+	case 0x34: case 0x35: case 0x36: case 0x37:
+		/* Primary Activity Detect Enable */
+		ret = (dev->regs.paden >> shift32) & 0xff;
+		break;
+	case 0x38: case 0x39: case 0x3a: case 0x3b:
+		/* GP Timer Reload Enable */
+		ret = (dev->regs.gptren >> shift32) & 0xff;
+		break;
+	case 0x40:
+		/* GPIO Direction Control */
+		if (size == 1)
+			ret = dev->regs.gpio_dir & 0xff;
+		break;
+	case 0x42:
+		/* GPIO port Output Value */
+		if (size == 1)
+			ret = dev->regs.gpio_val & 0xff;
+		break;
+	case 0x44:
+		/* GPIO port Output Value */
+		if (size == 1)
+			ret = dev->regs.extsmi_val & 0xff;
+		break;
+	case 0x46: case 0x47:
+		/* GPO Port Output Value */
+		ret = (dev->regs.gpo_val >> shift16) & 0xff;
+		break;
+	case 0x48: case 0x49:
+		/* GPO Port Input Value */
+		ret = (dev->regs.gpi_val >> shift16) & 0xff;
+		break;
+    }
+
+    acpi_log("(%i) ACPI Read  (%i) %02X: %02X\n", in_smm, size, addr, ret);
+    return ret;
+}
+
+
 static void
-acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
 {
     acpi_t *dev = (acpi_t *) p;
     int shift16, shift32;
@@ -199,6 +320,12 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
 	case 0x04: case 0x05:
 		/* PMCNTRL - Power Management Control Register (IO) */
 		dev->regs.pmcntrl = ((dev->regs.pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3c07;
+		/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
+		if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
+			dev->regs.glbsts |= 0x01;
+			if (dev->regs.glben & 0x02)
+				acpi_raise_smi(dev);
+		}
 		if (dev->regs.pmcntrl & 0x2000) {
 			sus_typ = (dev->regs.pmcntrl >> 10) & 7;
 			switch (sus_typ) {
@@ -240,16 +367,6 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
 		/* PCNTRL - Processor Control Register (IO) */
 		dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00023e1e;
 		break;
-	case 0x14:
-		/* PLVL2 - Processor Level 2 Register (IO) */
-		if (size == 1)
-			dev->regs.plvl2 = val;
-		break;
-	case 0x15:
-		/* PLVL3 - Processor Level 3 Register (IO) */
-		if (size == 1)
-			dev->regs.plvl3 = val;
-		break;
 	case 0x18: case 0x19:
 		/* GLBSTS - Global Status Register (IO) */
 		dev->regs.glbsts &= ~((val << shift16) & 0x0df7);
@@ -264,8 +381,13 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
 		break;
 	case 0x28: case 0x29: case 0x2a: case 0x2b:
 		/* GLBCTL - Global Control Register (IO) */
-		// dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0701ff07;
-		dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0700ff07;
+		dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0701ff07;
+		/* Setting BIOS_RLS also sets GBL_STS and generates SMI. */
+		if (dev->regs.glbctl & 0x00000002) {
+			dev->regs.pmsts |= 0x20;
+			if (dev->regs.pmen & 0x20)
+				acpi_update_irq(dev);
+		}
 		break;
 	case 0x2c: case 0x2d: case 0x2e: case 0x2f:
 		/* DEVCTL - Device Control Register (IO) */
@@ -280,6 +402,180 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
 }
 
 
+static void
+acpi_reg_write_via(int size, uint16_t addr, uint8_t val, void *p)
+{
+    acpi_t *dev = (acpi_t *) p;
+    int shift16, shift32;
+    int sus_typ;
+
+    addr &= 0xff;
+    acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);
+    shift16 = (addr & 1) << 3;
+    shift32 = (addr & 3) << 3;
+
+    switch (addr) {
+	case 0x00: case 0x01:
+		/* PMSTS - Power Management Status Register (IO) */
+		dev->regs.pmsts &= ~((val << shift16) & 0x8d31);
+		acpi_update_irq(dev);
+		if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
+			dev->regs.glbctl &= ~0x0002;
+		break;
+	case 0x02: case 0x03:
+		/* PMEN - Power Management Resume Enable Register (IO) */
+		dev->regs.pmen = ((dev->regs.pmen & ~(0xff << shift16)) | (val << shift16)) & 0x0521;
+		acpi_update_irq(dev);
+		break;
+	case 0x04: case 0x05:
+		/* PMCNTRL - Power Management Control Register (IO) */
+		dev->regs.pmcntrl = ((dev->regs.pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3c07;
+		/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
+		if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
+			dev->regs.glbsts |= 0x20;
+			if (dev->regs.glben & 0x20)
+				acpi_raise_smi(dev);
+		}
+		if (dev->regs.pmcntrl & 0x2000) {
+			sus_typ = (dev->regs.pmcntrl >> 10) & 7;
+			switch (sus_typ) {
+				case 0:
+					/* Soft power off. */
+					exit(-1);
+					break;
+				case 1:
+					/* Suspend to RAM. */
+					nvr_reg_write(0x000f, 0xff, dev->nvr);
+
+					/* Do a hard reset. */
+					device_reset_all_pci();
+
+					cpu_alt_reset = 0;
+
+					pci_reset();
+					keyboard_at_reset();
+
+					mem_a20_alt = 0;
+					mem_a20_recalc();
+
+					flushmmucache();
+
+					resetx86();
+					break;
+			}
+		}
+		break;
+	case 0x10: case 0x11: case 0x12: case 0x13:
+		/* PCNTRL - Processor Control Register (IO) */
+		dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x0000001e;
+		break;
+	case 0x20: case 0x21:
+		/* GPSTS - General Purpose Status Register (IO) */
+		dev->regs.gpsts &= ~((val << shift16) & 0x03ff);
+		break;
+	case 0x22: case 0x23:
+		/* General Purpose SCI Enable */
+		dev->regs.gpscien = ((dev->regs.gpscien & ~(0xff << shift16)) | (val << shift16)) & 0x03ff;
+		break;
+	case 0x24: case 0x25:
+		/* General Purpose SMI Enable */
+		dev->regs.gpsmien = ((dev->regs.gpsmien & ~(0xff << shift16)) | (val << shift16)) & 0x03ff;
+		break;
+	case 0x26: case 0x27:
+		/* Power Supply Control */
+		dev->regs.pscntrl = ((dev->regs.pscntrl & ~(0xff << shift16)) | (val << shift16)) & 0x0701;
+		break;
+	case 0x28: case 0x29:
+		/* GLBSTS - Global Status Register (IO) */
+		dev->regs.glbsts &= ~((val << shift16) & 0x007f);
+		break;
+	case 0x2a: case 0x2b:
+		/* GLBEN - Global Enable Register (IO) */
+		dev->regs.glben = ((dev->regs.glben & ~(0xff << shift16)) | (val << shift16)) & 0x007f;
+		break;
+	case 0x2c:
+		/* GLBCTL - Global Control Register (IO) */
+		dev->regs.glbctl = (dev->regs.glbctl & ~0xff) | (val & 0xff);
+		dev->regs.smi_lock = !!(dev->regs.glbctl & 0x0010);
+		/* Setting BIOS_RLS also sets GBL_STS and generates SMI. */
+		if (dev->regs.glbctl & 0x0002) {
+			dev->regs.pmsts |= 0x20;
+			if (dev->regs.pmen & 0x20)
+				acpi_update_irq(dev);
+		}
+		break;
+	case 0x2d:
+		/* GLBCTL - Global Control Register (IO) */
+		dev->regs.glbctl &= ~((val << 8) & 0x0100);
+		if (val & 0x01)
+			dev->regs.smi_active = 0;
+		break;
+	case 0x2f:
+		/* SMI Command */
+		if (size == 1) {
+			dev->regs.smicmd = val & 0xff;
+			dev->regs.glbsts |= 0x40;
+			if (dev->regs.glben & 0x40)
+				acpi_raise_smi(dev);
+		}
+		break;
+	case 0x30: case 0x31: case 0x32: case 0x33:
+		/* Primary Activity Detect Status */
+		dev->regs.padsts &= ~((val << shift32) & 0x000000fd);
+		break;
+	case 0x34: case 0x35: case 0x36: case 0x37:
+		/* Primary Activity Detect Enable */
+		dev->regs.paden = ((dev->regs.paden & ~(0xff << shift32)) | (val << shift32)) & 0x000000fd;
+		break;
+	case 0x38: case 0x39: case 0x3a: case 0x3b:
+		/* GP Timer Reload Enable */
+		dev->regs.gptren = ((dev->regs.gptren & ~(0xff << shift32)) | (val << shift32)) & 0x000000d9;
+		break;
+	case 0x40:
+		/* GPIO Direction Control */
+		if (size == 1)
+			dev->regs.gpio_dir = val & 0xff;
+		break;
+	case 0x42:
+		/* GPIO port Output Value */
+		if (size == 1)
+			dev->regs.gpio_val = val & 0xff;
+		break;
+	case 0x46: case 0x47:
+		/* GPO Port Output Value */
+		dev->regs.gpo_val = ((dev->regs.gpo_val & ~(0xff << shift16)) | (val << shift16)) & 0xffff;
+		break;
+    }
+}
+
+
+static uint32_t
+acpi_reg_read_common(int size, uint16_t addr, void *p)
+{
+    acpi_t *dev = (acpi_t *) p;
+    uint8_t ret = 0xff;
+
+    if (dev->vendor == VEN_VIA)
+	ret = acpi_reg_read_via(size, addr, p);
+    else
+	ret = acpi_reg_read_intel(size, addr, p);
+
+    return ret;
+}
+
+
+static void
+acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
+{
+    acpi_t *dev = (acpi_t *) p;
+
+    if (dev->vendor == VEN_VIA)
+	acpi_reg_write_via(size, addr, val, p);
+    else
+	acpi_reg_write_intel(size, addr, val, p);
+}
+
+
 static uint32_t
 acpi_reg_readl(uint16_t addr, void *p)
 {
@@ -440,6 +736,46 @@ acpi_set_nvr(acpi_t *dev, nvr_t *nvr)
 }
 
 
+static void
+acpi_apm_out(uint16_t port, uint8_t val, void *p)
+{
+    acpi_t *dev = (acpi_t *) p;
+
+    acpi_log("[%04X:%08X] APM write: %04X = %02X (BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, BX, CX);
+
+    port &= 0x0001;
+
+    if (port == 0x0000) {
+	dev->apm->cmd = val;
+	if (dev->apm->do_smi) {
+		if (dev->vendor == VEN_INTEL)
+			dev->regs.glbsts |= 0x20;
+		acpi_raise_smi(dev);
+	}
+    } else
+	dev->apm->stat = val;
+}
+
+
+static uint8_t
+acpi_apm_in(uint16_t port, void *p)
+{
+    acpi_t *dev = (acpi_t *) p;
+    uint8_t ret = 0xff;
+
+    port &= 0x0001;
+
+    if (port == 0x0000)
+	ret = dev->apm->cmd;
+    else
+	ret = dev->apm->stat;
+
+    acpi_log("[%04X:%08X] APM read: %04X = %02X\n", CS, cpu_state.pc, port, ret);
+
+    return ret;
+}
+
+
 static void
 acpi_reset(void *priv)
 {
@@ -482,6 +818,13 @@ acpi_init(const device_t *info)
     if (dev == NULL) return(NULL);
     memset(dev, 0x00, sizeof(acpi_t));
 
+    dev->vendor = info->local;
+
+    if (dev->vendor == VEN_INTEL) {
+	dev->apm = device_add(&apm_pci_acpi_device);
+	io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
+    }
+
     timer_add(&dev->timer, acpi_timer_count, dev, 0);
     timer_set_delay_u64(&dev->timer, ACPICONST);
 
@@ -489,11 +832,26 @@ acpi_init(const device_t *info)
 }
 
 
-const device_t acpi_device =
+const device_t acpi_intel_device =
 {
-    "ACPI",
+    "ACPI v1.0",
     DEVICE_PCI,
-    0,
+    VEN_INTEL,
+    acpi_init, 
+    acpi_close, 
+    acpi_reset,
+    NULL,
+    acpi_speed_changed,
+    NULL,
+    NULL
+};
+
+
+const device_t acpi_via_device =
+{
+    "ACPI v1.2",
+    DEVICE_PCI,
+    VEN_VIA,
     acpi_init, 
     acpi_close, 
     acpi_reset,
diff --git a/src/apm.c b/src/apm.c
index b197c0964..38d223e88 100644
--- a/src/apm.c
+++ b/src/apm.c
@@ -116,7 +116,8 @@ static void
     apm_t *dev = (apm_t *) malloc(sizeof(apm_t));
     memset(dev, 0, sizeof(apm_t));
 
-    io_sethandler(0x00b2, 0x0002, apm_in, NULL, NULL, apm_out, NULL, NULL, dev);
+    if (info->local == 0)
+	io_sethandler(0x00b2, 0x0002, apm_in, NULL, NULL, apm_out, NULL, NULL, dev);
 
     return dev;
 }
@@ -150,3 +151,18 @@ const device_t apm_pci_device =
     NULL,
     NULL
 };
+
+
+const device_t apm_pci_acpi_device =
+{
+    "Advanced Power Management (PCI)",
+    DEVICE_PCI,
+    1,
+    apm_init,
+    apm_close, 
+    apm_reset,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
diff --git a/src/include/86box/acpi.h b/src/include/86box/acpi.h
index ca0cb3b93..fa10aaa2f 100644
--- a/src/include/86box/acpi.h
+++ b/src/include/86box/acpi.h
@@ -6,13 +6,6 @@
  *
  *		This file is part of the 86Box distribution.
  *
- *		Implementation of the ISA Bus (de)Bugger expansion card
- *		sold as a DIY kit in the late 1980's in The Netherlands.
- *		This card was a assemble-yourself 8bit ISA addon card for
- *		PC and AT systems that had several tools to aid in low-
- *		level debugging (mostly for faulty BIOSes, bootloaders
- *		and system kernels...)
- *
  *		Definitions for the ACPI emulation.
  *
  *
@@ -46,21 +39,31 @@ extern "C" {
 #define ACPI_ENABLE	0xf1
 #define	ACPI_DISABLE	0xf0
 
+#define VEN_INTEL	0x8086
+#define VEN_VIA		0x1106
+
 
 typedef struct
 {
     uint8_t		plvl2, plvl3,
+			smicmd, gpio_dir,
+			gpio_val, extsmi_val,
 			timer32,
 			gpireg[3], gporeg[4];
     uint16_t		pmsts, pmen,
 			pmcntrl, gpsts,
-			gpen, io_base;
-    int			slot,
-			irq_mode, irq_pin;
+			gpen, io_base,
+			gpscien, gpsmien,
+			pscntrl, gpo_val,
+			gpi_val;
+    int			slot, irq_mode,
+			irq_pin, smi_lock,
+			smi_active;
     uint32_t		pcntrl, glbsts,
 			devsts, glben,
 			glbctl, devctl,
-			timer_val;
+			padsts, paden,
+			gptren, timer_val;
     uint64_t		tmr_overflow_time;
 } acpi_regs_t;
 
@@ -69,13 +72,16 @@ typedef struct
 {
     acpi_regs_t		regs;
     uint8_t		gporeg_default[4];
+    int			vendor;
     pc_timer_t		timer;
     nvr_t		*nvr;
+    apm_t		*apm;
 } acpi_t;
 
 
 /* Global variables. */
-extern const device_t	acpi_device;
+extern const device_t	acpi_intel_device;
+extern const device_t	acpi_via_device;
 
 
 /* Functions. */
diff --git a/src/include/86box/apm.h b/src/include/86box/apm.h
index b7754f78a..1fd985951 100644
--- a/src/include/86box/apm.h
+++ b/src/include/86box/apm.h
@@ -6,13 +6,6 @@
  *
  *		This file is part of the 86Box distribution.
  *
- *		Implementation of the ISA Bus (de)Bugger expansion card
- *		sold as a DIY kit in the late 1980's in The Netherlands.
- *		This card was a assemble-yourself 8bit ISA addon card for
- *		PC and AT systems that had several tools to aid in low-
- *		level debugging (mostly for faulty BIOSes, bootloaders
- *		and system kernels...)
- *
  *		Definitions for the Advanced Power Management emulation.
  *
  *
@@ -38,7 +31,9 @@ typedef struct
 
 /* Global variables. */
 extern const device_t	apm_device;
+
 extern const device_t	apm_pci_device;
+extern const device_t	apm_pci_acpi_device;
 
 
 /* Functions. */
diff --git a/src/include/86box/ddma.h b/src/include/86box/ddma.h
index 2d0a9f8d9..64642f2ae 100644
--- a/src/include/86box/ddma.h
+++ b/src/include/86box/ddma.h
@@ -6,13 +6,6 @@
  *
  *		This file is part of the 86Box distribution.
  *
- *		Implementation of the ISA Bus (de)Bugger expansion card
- *		sold as a DIY kit in the late 1980's in The Netherlands.
- *		This card was a assemble-yourself 8bit ISA addon card for
- *		PC and AT systems that had several tools to aid in low-
- *		level debugging (mostly for faulty BIOSes, bootloaders
- *		and system kernels...)
- *
  *		Definitions for the Distributed DMA emulation.
  *
  *
diff --git a/src/include/86box/piix.h b/src/include/86box/piix.h
index e07607606..9f6724fae 100644
--- a/src/include/86box/piix.h
+++ b/src/include/86box/piix.h
@@ -4,7 +4,8 @@
  *		PC systems and compatibles from 1981 through fairly recent
  *		system designs based on the PCI bus.
  *
- *		Emulation of the Intel PIIX and PIIX3 Xcelerators.
+ *		Emulation of the Intel PIIX, PIIX3, PIIX4, PIIX4E, and SMSC
+ *		SLC90E66 (Victory66) Xcelerators.
  *
  *		Emulation core dispatcher.
  *
diff --git a/src/include/86box/usb.h b/src/include/86box/usb.h
index b027796a2..aced538c8 100644
--- a/src/include/86box/usb.h
+++ b/src/include/86box/usb.h
@@ -6,13 +6,6 @@
  *
  *		This file is part of the 86Box distribution.
  *
- *		Implementation of the ISA Bus (de)Bugger expansion card
- *		sold as a DIY kit in the late 1980's in The Netherlands.
- *		This card was a assemble-yourself 8bit ISA addon card for
- *		PC and AT systems that had several tools to aid in low-
- *		level debugging (mostly for faulty BIOSes, bootloaders
- *		and system kernels...)
- *
  *		Definitions for the Distributed DMA emulation.
  *
  *
diff --git a/src/intel_piix.c b/src/intel_piix.c
index 257b9be9a..4a9a80f1e 100644
--- a/src/intel_piix.c
+++ b/src/intel_piix.c
@@ -4,7 +4,8 @@
  *		PC systems and compatibles from 1981 through fairly recent
  *		system designs based on the PCI bus.
  *
- *		Emulation of the Intel PIIX and PIIX3 Xcelerators.
+ *		Emulation of the Intel PIIX, PIIX3, PIIX4, PIIX4E, and SMSC
+ *		SLC90E66 (Victory66) Xcelerators.
  *
  *		PRD format :
  *		    word 0 - base address
@@ -779,7 +780,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0x04:
 		fregs[0x04] = (val & 0x01);
 		smbus_update_io_mapping(dev);
-		apm_set_do_smi(dev->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01));
+		apm_set_do_smi(dev->acpi->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01));
 		break;
 	case 0x07:
 		if (val & 0x08)
@@ -844,7 +845,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 		break;
 	case 0x5b:
 		fregs[addr] = val & 0x03;
-		apm_set_do_smi(dev->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01));
+		apm_set_do_smi(dev->acpi->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01));
 		break;
 	case 0x63:
 		fregs[addr] = val & 0xf7;
@@ -1109,9 +1110,7 @@ piix_apm_out(uint16_t port, uint8_t val, void *p)
     piix_t *dev = (piix_t *) p;
 
     if (dev->apm->do_smi) {
-	if (dev->type > 3)
-		dev->acpi->regs.glbsts |= 0x20;
-	else
+	if (dev->type < 4)
 		dev->regs[0][0xaa] |= 0x80;
     }
 }
@@ -1189,7 +1188,7 @@ static void
 	dev->nvr = device_add(&piix4_nvr_device);
 	dev->smbus = device_add(&piix4_smbus_device);
 
-	dev->acpi = device_add(&acpi_device);
+	dev->acpi = device_add(&acpi_intel_device);
 	acpi_set_slot(dev->acpi, dev->pci_slot);
 	acpi_set_nvr(dev->acpi, dev->nvr);
 
@@ -1206,9 +1205,13 @@ static void
     } else
 	cpu_fast_off_val = cpu_fast_off_count = 0;
 
-    dev->apm = device_add(&apm_pci_device);
-    /* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */
-    io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev);
+    /* On PIIX4, PIIX4E, and SMSC, APM is added by the ACPI device. */
+    if (dev->type < 4) {
+    	dev->apm = device_add(&apm_pci_device);
+	/* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */
+	io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev);
+    }
+
     dev->port_92 = device_add(&port_92_pci_device);
 
     dma_alias_set();