Implement TSS debug trap bit

2026-02-25 04:45:31 -07:00 · 2024-01-14 04:04:04 +06:00
parent b1c292a9e9
commit a13a8efb39
3 changed files with 23 additions and 3 deletions
--- a/src/cpu/386.c
+++ b/src/cpu/386.c
@@ -311,12 +311,12 @@ exec386_2386(int32_t cycs)
                }
            } else if (trap) {
                flags_rebuild();
+                dr[6] |= (trap == 2) ? 0x8000 : 0x4000;
                trap = 0;
 #ifndef USE_NEW_DYNAREC
                oldcs = CS;
 #endif
                cpu_state.oldpc = cpu_state.pc;
-                dr[6] |= 0x4000;
                x86_int(1);
            }