From b170c51307f29d4074a884c73c344d94ac7ffd7f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 02:05:36 +0000 Subject: [PATCH] fix the bsod (I hate bitfields). --- src/include/86box/nv/vid_nv3.h | 14 +++---- .../nv/nv3/classes/nv3_class_shared_methods.c | 9 +++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 41 ++++++++++++++++--- src/video/nv/nv3/subsystems/nv3_pgraph.c | 5 --- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 1 - 5 files changed, 49 insertions(+), 21 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index d7d7dc144..16fcee485 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -266,7 +266,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_PUSH0 0x3000 +#define NV3_PFIFO_CACHE0_PUSH0 0x3000 #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 @@ -309,11 +309,11 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULL0 0x3240 +#define NV3_PFIFO_CACHE1_PULL0 0x3240 //todo: merge stuff -#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware +#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE 0x3250 #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 @@ -997,8 +997,8 @@ typedef struct nv3_pfifo_cache_s typedef struct nv3_pfifo_cache_entry_s { - uint8_t subchannel : 3; - uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin) + uint16_t method; // method id depending on class (offset from entry channel start in ramin) + uint8_t subchannel; uint32_t data; // is this the context } nv3_pfifo_cache_entry_t; diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 7338c45ad..0bb12a2eb 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -33,8 +33,13 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t { switch (method_id) { - // set up the current notification request/object] - // check for double notifiers. + /* mthdCreate in software(?)*/ + case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: + nv_log("mthdCreate\n"); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + break; + // set up the current notification request/object + // and check for double notifiers. case NV3_SET_NOTIFY: if (nv3->pgraph.notify_pending) { diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index f9e72c71f..81b13e5bf 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -295,28 +295,57 @@ uint32_t nv3_pfifo_read(uint32_t address) { nv_log("PFIFO Cache0 Read\n"); - if (address & 4) + // See if we want the object name or the channel/subchannel information. + if (address & 4) + { + nv_log("Data=0x%08x\n", nv3->pfifo.cache0_entry.data); return nv3->pfifo.cache0_entry.data; + } else + { + uint32_t method = nv3->pfifo.cache0_entry.method; + uint32_t subchannel = nv3->pfifo.cache0_entry.subchannel; + uint32_t final = nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + + nv_log("Method=0x%08x, ", nv3->pfifo.cache0_entry.method); + nv_log("Subchannel=0x%08x\n", nv3->pfifo.cache0_entry.subchannel); + nv_log("Final=0x%08x\n", final); + return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + } } else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) { // Not sure if REV C changes this. It should... uint32_t slot = 0; + // shift right by 3, convert from address, to slot. if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) slot = (address >> 3) & 0x3F; else slot = (address >> 3) & 0x1F; - nv_log("PFIFO Cache1 Read slot=%d\n", slot); + nv_log("PFIFO Cache1 Read slot=%d", slot); // See if we want the object name or the channel/subchannel information. if (address & 4) + { + nv_log("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data); return nv3->pfifo.cache1_entries[slot].data; + } else + { + uint32_t method = nv3->pfifo.cache1_entries[slot].method; + uint32_t subchannel = nv3->pfifo.cache1_entries[slot].subchannel; + uint32_t final = nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + + nv_log("Method=0x%08x, ", nv3->pfifo.cache1_entries[slot].method); + nv_log("Subchannel=0x%08x\n", nv3->pfifo.cache1_entries[slot].subchannel); + nv_log("Final=0x%08x\n", final); + return nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + } + } else { @@ -556,7 +585,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) } else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { - nv_log("PFIFO Cache0 Write"); + nv_log("PFIFO Cache0 Write\n"); // 3104 always written after 3100 if (address & 4) @@ -736,7 +765,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel) // NV_USER writes go here! // Pushes graphics objects into cache1 -void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) +void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) { bool oh_shit = false; // RAMRO needed nv3_ramin_ramro_reason oh_shit_reason = 0x00; // It's all good for now @@ -811,7 +840,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) uint32_t current_put_address = nv3->pfifo.cache1_settings.put_address >> 2; nv3->pfifo.cache1_entries[current_put_address].subchannel = subchannel; nv3->pfifo.cache1_entries[current_put_address].method = method_offset; - nv3->pfifo.cache1_entries[current_put_address].data = object_name; + nv3->pfifo.cache1_entries[current_put_address].data = param; // now we have to recalculate the cache1 put address uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address); @@ -825,7 +854,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; nv_log("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", - channel, subchannel, object_name, method_offset, nv3->pfifo.cache1_settings.put_address); + channel, subchannel, param, method_offset, nv3->pfifo.cache1_settings.put_address); // Now we're done. Phew! } diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index eddf61dea..993232c9d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -613,11 +613,6 @@ void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t switch (method) { - // This method is how we figure out which methods exist. - case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("I'm an Nvidia Object! channel=%d.%d class=0x%02x (%s) method=0x%04x parameter=0x%08x, context=0x%08x\n", - channel, subchannel, class_id, nv3_class_names[class_id], method, param, context); - break; default: // Object Method orchestration nv3_pgraph_arbitrate_method(param, method, channel, subchannel, class_id, context); diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index e46b46618..cce1d74a9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -32,7 +32,6 @@ It is used to get the offset within RAMHT of a graphics object. */ - uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) { // the official nvidia hash algorithm, tweaked for readability