From efd5a6a47483e454d2cf496c87488aee939c2f34 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 14 Jan 2025 02:38:44 +0100 Subject: [PATCH 01/43] SCAMP: Fixed EMS memory states, fixes #1966. --- src/chipset/scamp.c | 140 ++++++++++++++++++++++++++++---------------- 1 file changed, 88 insertions(+), 52 deletions(-) diff --git a/src/chipset/scamp.c b/src/chipset/scamp.c index 122318862..00f9798cb 100644 --- a/src/chipset/scamp.c +++ b/src/chipset/scamp.c @@ -101,6 +101,8 @@ typedef struct scamp_t { int ram_interleaved[2]; int ibank_shift[2]; + int ram_flags[24]; + port_92_t *port_92; } scamp_t; @@ -593,6 +595,35 @@ scamp_ems_write(uint32_t addr, uint8_t val, void *priv) ram[addr] = val; } +static void +scamp_mem_update_state(scamp_t *dev, uint32_t addr, uint32_t size) +{ + uint8_t flags; + + if ((addr >= 0x000a0000) && (addr < 0x00100000)) { + flags = dev->ram_flags[(addr - 0x000a0000) >> 14]; + + if (flags & 4) + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else switch (flags & 3) { + case 0: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 3: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + default: + break; + } + } +} + static void recalc_ems(scamp_t *dev) { @@ -630,34 +661,48 @@ recalc_ems(scamp_t *dev) if (new_mappings[segment] < (mem_size * 1024)) { mem_mapping_set_exec(&dev->ems_mappings[segment], ram + dev->mappings[segment]); mem_mapping_enable(&dev->ems_mappings[segment]); - } else + dev->ram_flags[segment] |= 0x04; + } else { mem_mapping_disable(&dev->ems_mappings[segment]); + dev->ram_flags[segment] &= 0xfb; + } + + scamp_mem_update_state(dev, 0xa0000 + segment * 0x4000, 0x4000); } } + + flushmmucache_nopc(); } static void -shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable) +shadow_control(scamp_t *dev, uint32_t addr, uint32_t size, int state) { - if (ems_enable) - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else - switch (state) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - default: - break; - } + dev->ram_flags[(addr - 0x000a0000) >> 14] &= 0xfc; + dev->ram_flags[(addr - 0x000a0000) >> 14] |= state; + + if (size == 0x8000) { + dev->ram_flags[((addr - 0x000a0000) >> 14) + 1] &= 0xfc; + dev->ram_flags[((addr - 0x000a0000) >> 14) + 1] |= state; + } + + switch (state) { + case 0: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 3: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + default: + break; + } + + scamp_mem_update_state(dev, addr, size); flushmmucache_nopc(); } @@ -669,47 +714,38 @@ shadow_recalc(scamp_t *dev) uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_CAXS]; uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_DAXS]; uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_FEAXS]; - uint32_t ems_enable; - - if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) { - if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSMAP) /*Axxx/Bxxx/Dxxx*/ - ems_enable = (dev->cfg_regs[CFG_EMSEN2] & 0xf) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 4) | ((dev->cfg_regs[CFG_EMSEN2] & 0xf0) << 8); - else /*Cxxx/Dxxx/Exxx*/ - ems_enable = (dev->cfg_regs[CFG_EMSEN2] << 8) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 16); - } else - ems_enable = 0; /*Enabling remapping will disable all shadowing*/ if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) mem_remap_top(384); - shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00001); - shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00002); - shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00004); - shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00008); + shadow_control(dev, 0xa0000, 0x4000, abaxs & 3); + shadow_control(dev, 0xa0000, 0x4000, abaxs & 3); + shadow_control(dev, 0xa8000, 0x4000, (abaxs >> 2) & 3); + shadow_control(dev, 0xa8000, 0x4000, (abaxs >> 2) & 3); - shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00010); - shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00020); - shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00040); - shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00080); + shadow_control(dev, 0xb0000, 0x4000, (abaxs >> 4) & 3); + shadow_control(dev, 0xb0000, 0x4000, (abaxs >> 4) & 3); + shadow_control(dev, 0xb8000, 0x4000, (abaxs >> 6) & 3); + shadow_control(dev, 0xb8000, 0x4000, (abaxs >> 6) & 3); - shadow_control(0xc0000, 0x4000, caxs & 3, ems_enable & 0x00100); - shadow_control(0xc4000, 0x4000, (caxs >> 2) & 3, ems_enable & 0x00200); - shadow_control(0xc8000, 0x4000, (caxs >> 4) & 3, ems_enable & 0x00400); - shadow_control(0xcc000, 0x4000, (caxs >> 6) & 3, ems_enable & 0x00800); + shadow_control(dev, 0xc0000, 0x4000, caxs & 3); + shadow_control(dev, 0xc4000, 0x4000, (caxs >> 2) & 3); + shadow_control(dev, 0xc8000, 0x4000, (caxs >> 4) & 3); + shadow_control(dev, 0xcc000, 0x4000, (caxs >> 6) & 3); - shadow_control(0xd0000, 0x4000, daxs & 3, ems_enable & 0x01000); - shadow_control(0xd4000, 0x4000, (daxs >> 2) & 3, ems_enable & 0x02000); - shadow_control(0xd8000, 0x4000, (daxs >> 4) & 3, ems_enable & 0x04000); - shadow_control(0xdc000, 0x4000, (daxs >> 6) & 3, ems_enable & 0x08000); + shadow_control(dev, 0xd0000, 0x4000, daxs & 3); + shadow_control(dev, 0xd4000, 0x4000, (daxs >> 2) & 3); + shadow_control(dev, 0xd8000, 0x4000, (daxs >> 4) & 3); + shadow_control(dev, 0xdc000, 0x4000, (daxs >> 6) & 3); - shadow_control(0xe0000, 0x4000, feaxs & 3, ems_enable & 0x10000); - shadow_control(0xe4000, 0x4000, feaxs & 3, ems_enable & 0x20000); - shadow_control(0xe8000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x40000); - shadow_control(0xec000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x80000); + shadow_control(dev, 0xe0000, 0x4000, feaxs & 3); + shadow_control(dev, 0xe4000, 0x4000, feaxs & 3); + shadow_control(dev, 0xe8000, 0x4000, (feaxs >> 2) & 3); + shadow_control(dev, 0xec000, 0x4000, (feaxs >> 2) & 3); - shadow_control(0xf0000, 0x8000, (feaxs >> 4) & 3, 0); - shadow_control(0xf8000, 0x8000, (feaxs >> 6) & 3, 0); + shadow_control(dev, 0xf0000, 0x8000, (feaxs >> 4) & 3); + shadow_control(dev, 0xf8000, 0x8000, (feaxs >> 6) & 3); } static void From c36e6be6e248da16b2828a84a76dc57364e912d9 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 14 Jan 2025 06:27:41 +0100 Subject: [PATCH 02/43] NEAT: Fix EMS and implement Shadow RAM and top 128K of conventional memory on/off, closes #1375. --- src/chipset/neat.c | 367 +++++++++++++++++++++++++++++---------------- 1 file changed, 238 insertions(+), 129 deletions(-) diff --git a/src/chipset/neat.c b/src/chipset/neat.c index 97c4b8f1a..94f0d66e1 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -37,6 +37,9 @@ #define EMS_MAXPAGE 4 #define EMS_PGSIZE 16384 +#define EMS_PGMASK 16383 + +#define REG_MASK 0x0f /* CS8221 82C211 controller registers. */ #define REG_RA0 0x60 /* PROCCLK selector */ @@ -194,37 +197,47 @@ #define RB10_P0EXT 0xc0 /* page 0 extension */ #define RB10_P0EXT_SH 6 -#define REG_RB11 0x6f /* Miscellaneous */ -#define RB11_MASK 0xe6 /* 111R R11R */ -#define RB11_GA20 0x02 /* gate for A20 */ -#define RB11_RASTMO 0x04 /* enable RAS timeout counter */ -#define RB11_EMSLEN 0xe0 /* EMS memory chunk size */ -#define RB11_EMSLEN_SH 5 +#define REG_RB12 0x6f /* Miscellaneous */ +#define RB12_MASK 0xe6 /* 111R R11R */ +#define RB12_GA20 0x02 /* gate for A20 */ +#define RB12_RASTMO 0x04 /* enable RAS timeout counter */ +#define RB12_EMSLEN 0xe0 /* EMS memory chunk size */ +#define RB12_EMSLEN_SH 5 -typedef struct emspage_t { - int8_t enabled; /* 1=ENABLED */ +#define RAM_FLAG_EMS 0x08 +#define RAM_FLAG_ROMCS 0x04 +#define RAM_FLAG_SHREAD 0x02 +#define RAM_FLAG_SHWRITE 0x01 +#define RAM_FMASK_EMS 0x08 +#define RAM_FMASK_SHADOW 0x07 + +typedef struct ram_page_t { + int8_t enabled; /* 1=ENABLED */ char pad; - uint16_t page; /* selected page in EMS block */ - uint32_t start; /* start of EMS in RAM */ - uint8_t *addr; /* start addr in EMS RAM */ - mem_mapping_t mapping; /* mapping entry for page */ -} emspage_t; + uint32_t phys_base; + uint32_t virt_base; + mem_mapping_t mapping; /* mapping entry for page */ +} ram_page_t; typedef struct neat_t { - uint8_t regs[128]; /* all the CS8221 registers */ - uint8_t indx; /* programmed index into registers */ + uint8_t ram_flags[32]; + uint8_t regs[128]; /* all the CS8221 registers */ + uint8_t indx; /* programmed index into registers */ - char pad; + char pad; - uint16_t ems_base; /* configured base address */ - uint16_t ems_oldbase; - uint32_t ems_frame; /* configured frame address */ - uint32_t ems_oldframe; - uint16_t ems_size; /* EMS size in KB */ - uint16_t ems_pages; /* EMS size in pages */ - emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */ + uint16_t ems_base; /* configured base address */ + uint32_t ems_frame; /* configured frame address */ + uint16_t ems_size; /* EMS size in KB */ + uint16_t ems_pages; /* EMS size in pages */ + + ram_page_t ems[EMS_MAXPAGE]; /* EMS page registers */ + ram_page_t shadow[32]; /* Shadow RAM pages */ } neat_t; +static uint8_t defaults[16] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0xa0, 0x63, 0x10, 0x00, 0x00, 0x12 }; + #ifdef ENABLE_NEAT_LOG int neat_do_log = ENABLE_NEAT_LOG; @@ -247,11 +260,11 @@ neat_log(const char *fmt, ...) static uint8_t ems_readb(uint32_t addr, void *priv) { - neat_t *dev = (neat_t *) priv; - uint8_t ret = 0xff; + ram_page_t *dev = (ram_page_t *) priv; + uint8_t ret = 0xff; /* Grab the data. */ - ret = *(uint8_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff)); + ret = *(uint8_t *) &(ram[addr - dev->virt_base + dev->phys_base]); return ret; } @@ -260,11 +273,11 @@ ems_readb(uint32_t addr, void *priv) static uint16_t ems_readw(uint32_t addr, void *priv) { - neat_t *dev = (neat_t *) priv; - uint16_t ret = 0xffff; + ram_page_t *dev = (ram_page_t *) priv; + uint16_t ret = 0xffff; /* Grab the data. */ - ret = *(uint16_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff)); + ret = *(uint16_t *) &(ram[addr - dev->virt_base + dev->phys_base]); return ret; } @@ -273,40 +286,113 @@ ems_readw(uint32_t addr, void *priv) static void ems_writeb(uint32_t addr, uint8_t val, void *priv) { - neat_t *dev = (neat_t *) priv; + ram_page_t *dev = (ram_page_t *) priv; /* Write the data. */ - *(uint8_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff)) = val; + *(uint8_t *) &(ram[addr - dev->virt_base + dev->phys_base]) = val; } /* Write one word to paged RAM. */ static void ems_writew(uint32_t addr, uint16_t val, void *priv) { - neat_t *dev = (neat_t *) priv; + ram_page_t *dev = (ram_page_t *) priv; /* Write the data. */ - *(uint16_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff)) = val; + *(uint16_t *) &(ram[addr - dev->virt_base + dev->phys_base]) = val; +} + +static void +neat_mem_update_state(neat_t *dev, uint32_t addr, uint32_t size, uint8_t new_flags, uint8_t mask) +{ + if ((addr >= 0x00080000) && (addr < 0x00100000) && + ((new_flags ^ dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE]) & mask)) { + dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE] &= ~mask; + dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE] |= new_flags; + + new_flags = dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE]; + + neat_log("neat_mem_update_state(): %08X-%08X: %02X\n", addr, addr + size - 1, new_flags); + + if (new_flags & RAM_FLAG_EMS) + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else if (new_flags & RAM_FLAG_ROMCS) + mem_set_mem_state(addr, size, MEM_READ_ROMCS | MEM_WRITE_ROMCS); + else switch (new_flags & (RAM_FLAG_SHREAD | RAM_FLAG_SHWRITE)) { + case 0: + mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); + break; + case 1: + mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); + break; + case 3: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + default: + break; + } + } + + flushmmucache_nopc(); +} + +static void +shadow_recalc(neat_t *dev) +{ + for (uint8_t i = 8; i < 32; i++) { + int romcs = 0; + int write = 1; + int shadow_reg = REG_RB3 + ((i - 8) >> 3); + int shadow_bit = i & 7; + int ram_flags; + int read; + + if (i > 16) { + int rb1_romcs_bit = 7 - (i >> 2); + int rb1_write_bit = rb1_romcs_bit + 4; + + romcs = !(dev->regs[REG_RB1] & (1 << rb1_romcs_bit)); + write = !(dev->regs[REG_RB1] & (1 << rb1_write_bit)); + } else if (i <= 8) + shadow_bit ^= 4; + + read = dev->regs[shadow_reg] & (1 << shadow_bit); + write = write && read; + + ram_flags = romcs ? RAM_FLAG_ROMCS : 0x00; + ram_flags |= read ? RAM_FLAG_SHREAD : 0x00; + ram_flags |= write ? RAM_FLAG_SHWRITE : 0x00; + + if ((ram_flags > 0x00) && !(ram_flags & RAM_FLAG_ROMCS)) + mem_mapping_set_addr(&(dev->shadow[i].mapping), dev->shadow[i].virt_base, EMS_PGSIZE); + else + mem_mapping_disable(&(dev->shadow[i].mapping)); + + neat_mem_update_state(dev, dev->shadow[i].virt_base, EMS_PGSIZE, ram_flags, RAM_FMASK_SHADOW); + } } /* Re-calculate the active-page physical address. */ static void -ems_recalc(neat_t *dev, emspage_t *ems) +ems_recalc(neat_t *dev, ram_page_t *ems) { - if (ems->page >= dev->ems_pages) { - /* That page does not exist. */ - ems->enabled = 0; - } + uint32_t page = ems->phys_base / EMS_PGSIZE; - /* Pre-calculate the page address in EMS RAM. */ - ems->addr = ram + ems->start + (ems->page * EMS_PGSIZE); + if ((dev->regs[REG_RB7] & RB7_EMSEN) && ems->enabled && + (page >= 0x40) && (page < (0x40 + dev->ems_pages))) { + neat_log("ems_recalc(): %08X-%08X -> %08X-%08X\n", + ems->virt_base, ems->virt_base + EMS_PGSIZE - 1, + ems->phys_base, ems->phys_base + EMS_PGSIZE - 1); + mem_mapping_set_addr(&ems->mapping, ems->virt_base, EMS_PGSIZE); - if (ems->enabled) { /* Update the EMS RAM address for this page. */ - mem_mapping_set_exec(&ems->mapping, ems->addr); + mem_mapping_set_exec(&ems->mapping, ram + ems->phys_base); - /* Enable this page. */ - mem_mapping_enable(&ems->mapping); + if ((ems->virt_base >= 0x00080000) && (ems->virt_base < 0x00100000)) + neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, RAM_FLAG_EMS, RAM_FMASK_EMS); #if NEAT_DEBUG > 1 neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n", @@ -315,15 +401,18 @@ ems_recalc(neat_t *dev, emspage_t *ems) } else { /* Disable this page. */ mem_mapping_disable(&ems->mapping); + + if ((ems->virt_base >= 0x00080000) && (ems->virt_base < 0x00100000)) + neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, 0x00, RAM_FMASK_EMS); } } static void ems_write(uint16_t port, uint8_t val, void *priv) { - neat_t *dev = (neat_t *) priv; - emspage_t *ems; - int vpage; + neat_t *dev = (neat_t *) priv; + ram_page_t *ems; + int vpage; #if NEAT_DEBUG > 1 neat_log("NEAT: ems_write(%04x, %02x)\n", port, val); @@ -337,8 +426,7 @@ ems_write(uint16_t port, uint8_t val, void *priv) case 0x0008: case 0x0009: ems->enabled = !!(val & 0x80); - ems->page &= 0x0180; /* clear lower bits */ - ems->page |= (val & 0x7f); /* add new bits */ + ems->phys_base = (ems->phys_base & 0xffe00000) | ((val & 0x7f) * EMS_PGSIZE); ems_recalc(dev, ems); break; default: @@ -358,7 +446,7 @@ ems_read(uint16_t port, void *priv) switch (port & 0x000f) { case 0x0008: /* page number register */ - ret = dev->ems[vpage].page & 0x7f; + ret = (dev->ems[vpage].phys_base / EMS_PGSIZE) & 0x7f; if (dev->ems[vpage].enabled) ret |= 0x80; break; @@ -373,68 +461,21 @@ ems_read(uint16_t port, void *priv) return ret; } -/* Initialize the EMS module. */ static void -ems_init(neat_t *dev, int en) +ems_update(neat_t *dev, int en) { - uint8_t j; - - /* Remove if needed. */ - if (!en) { - if (dev->ems_base > 0) - for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { - /* Disable for now. */ - mem_mapping_disable(&dev->ems[i].mapping); - - /* Remove I/O handler. */ - io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2, - ems_read, NULL, NULL, ems_write, NULL, NULL, dev); - } - -#ifdef ENABLE_NEAT_LOG - neat_log("NEAT: EMS disabled\n"); -#endif - - return; - } - - /* Get configured I/O address. */ - j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; - dev->ems_base = 0x0208 + (0x10 * j); - - /* Get configured frame address. */ - j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; - dev->ems_frame = 0xC0000 + (EMS_PGSIZE * j); - - /* - * For each supported page (we can have a maximum of 4), - * create, initialize and disable the mappings, and set - * up the I/O control handler. - */ for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { - /* Create and initialize a page mapping. */ - mem_mapping_add(&dev->ems[i].mapping, - dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE, - ems_readb, ems_readw, NULL, - ems_writeb, ems_writew, NULL, - ram, MEM_MAPPING_EXTERNAL, - dev); - - /* Disable for now. */ - mem_mapping_disable(&dev->ems[i].mapping); - /* Set up an I/O port handler. */ - io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2, - ems_read, NULL, NULL, ems_write, NULL, NULL, dev); + io_handler(en, dev->ems_base + (i * EMS_PGSIZE), 2, + ems_read, NULL, NULL, ems_write, NULL, NULL, dev); - /* - * TODO: update the 'high_mem' mapping to reflect that we now - * have NN MB less extended memory available.. - */ + if (en) + dev->ems[i].virt_base = dev->ems_frame + (i * EMS_PGSIZE); + + ems_recalc(dev, &(dev->ems[i])); } - neat_log("NEAT: EMS enabled, I/O=%04xH, Frame=%05XH\n", - dev->ems_base, dev->ems_frame); + flushmmucache_nopc(); } static void @@ -442,6 +483,7 @@ neat_write(uint16_t port, uint8_t val, void *priv) { neat_t *dev = (neat_t *) priv; uint8_t xval; + uint8_t j; uint8_t *reg; int i; @@ -493,6 +535,7 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RB1: val &= RB1_MASK; *reg = (*reg & ~RB1_MASK) | val; + shadow_recalc(dev); #if NEAT_DEBUG > 1 neat_log("NEAT: RB1=%02x(%02x)\n", val, *reg); #endif @@ -501,6 +544,10 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RB2: val &= RB2_MASK; *reg = (*reg & ~RB2_MASK) | val; + if (val & RB2_TOP128) + neat_mem_update_state(dev, 0x00080000, 0x00020000, RAM_FLAG_SHREAD | RAM_FLAG_SHWRITE, RAM_FMASK_SHADOW); + else + neat_mem_update_state(dev, 0x00080000, 0x00020000, 0x00, RAM_FMASK_SHADOW); #if NEAT_DEBUG > 1 neat_log("NEAT: RB2=%02x(%02x)\n", val, *reg); #endif @@ -509,6 +556,7 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RB3: val &= RB3_MASK; *reg = (*reg & ~RB3_MASK) | val; + shadow_recalc(dev); #if NEAT_DEBUG > 1 neat_log("NEAT: RB3=%02x(%02x)\n", val, *reg); #endif @@ -517,6 +565,7 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RB4: val &= RB4_MASK; *reg = (*reg & ~RB4_MASK) | val; + shadow_recalc(dev); #if NEAT_DEBUG > 1 neat_log("NEAT: RB4=%02x(%02x)\n", val, *reg); #endif @@ -525,6 +574,7 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RB5: val &= RB5_MASK; *reg = (*reg & ~RB5_MASK) | val; + shadow_recalc(dev); #if NEAT_DEBUG > 1 neat_log("NEAT: RB5=%02x(%02x)\n", val, *reg); #endif @@ -544,10 +594,9 @@ neat_write(uint16_t port, uint8_t val, void *priv) #if NEAT_DEBUG > 1 neat_log("NEAT: RB7=%02x(%02x)\n", val, *reg); #endif - if (val & RB7_EMSEN) - ems_init(dev, 1); - else if (xval & RB7_EMSEN) - ems_init(dev, 0); + + if (xval & RB7_EMSEN) + ems_update(dev, !!(val & RB7_EMSEN)); if (xval & RB7_UMAREL) { if (val & RB7_UMAREL) @@ -571,10 +620,19 @@ neat_write(uint16_t port, uint8_t val, void *priv) #if NEAT_DEBUG > 1 neat_log("NEAT: RB9=%02x(%02x)\n", val, *reg); #endif - if (dev->regs[REG_RB7] & RB7_EMSEN) { - ems_init(dev, 0); - ems_init(dev, 1); - } + + ems_update(dev, 0); + + /* Get configured I/O address. */ + j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; + dev->ems_base = 0x0208 + (0x10 * j); + + /* Get configured frame address. */ + j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; + dev->ems_frame = 0xc0000 + (EMS_PGSIZE * j); + + if (dev->regs[REG_RB7] & RB7_EMSEN) + ems_update(dev, 1); break; case REG_RB10: @@ -584,23 +642,29 @@ neat_write(uint16_t port, uint8_t val, void *priv) neat_log("NEAT: RB10=%02x(%02x)\n", val, *reg); #endif - dev->ems[3].start = ((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21; - dev->ems[2].start = ((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21; - dev->ems[1].start = ((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21; - dev->ems[0].start = ((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21; - for (i = 0; i < EMS_MAXPAGE; i++) - ems_recalc(dev, &dev->ems[i]); + dev->ems[3].phys_base = (dev->ems[3].phys_base & 0x001fffff) | + (((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21); + dev->ems[2].phys_base = (dev->ems[2].phys_base & 0x001fffff) | + (((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21); + dev->ems[1].phys_base = (dev->ems[1].phys_base & 0x001fffff) | + (((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21); + dev->ems[0].phys_base = (dev->ems[0].phys_base & 0x001fffff) | + (((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21); + + if (dev->regs[REG_RB7] & RB7_EMSEN) + for (i = 0; i < EMS_MAXPAGE; i++) + ems_recalc(dev, &dev->ems[i]); break; - case REG_RB11: - val &= RB11_MASK; - *reg = (*reg & ~RB11_MASK) | val; + case REG_RB12: + val &= RB12_MASK; + *reg = (*reg & ~RB12_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB11=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB12=%02x(%02x)\n", val, *reg); #endif - i = (val & RB11_EMSLEN) >> RB11_EMSLEN_SH; + i = (val & RB12_EMSLEN) >> RB12_EMSLEN_SH; switch (i) { - case 0: /* "less than 2MB" */ + case 0: /* "less than 1MB" */ dev->ems_size = 512; break; @@ -617,10 +681,18 @@ neat_write(uint16_t port, uint8_t val, void *priv) break; } dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE; + + if (dev->regs[REG_RB7] & RB7_EMSEN) + for (i = 0; i < EMS_MAXPAGE; i++) + ems_recalc(dev, &dev->ems[i]); + if (dev->regs[REG_RB7] & RB7_EMSEN) { neat_log("NEAT: EMS %iKB (%i pages)\n", dev->ems_size, dev->ems_pages); } + + mem_a20_key = val & RB12_GA20; + mem_a20_recalc(); break; default: @@ -629,6 +701,7 @@ neat_write(uint16_t port, uint8_t val, void *priv) break; } break; + default: break; } @@ -646,8 +719,10 @@ neat_read(uint16_t port, void *priv) break; case 0x23: - if ((dev->indx >= 0x60) && (dev->indx <= 0x6f)) + if ((dev->indx >= 0x60) && (dev->indx <= 0x6e)) ret = dev->regs[dev->indx]; + else if (dev->indx == 0x6f) + ret = (dev->regs[dev->indx] & 0xfd) | (mem_a20_key & 2); break; default: @@ -674,16 +749,50 @@ neat_init(UNUSED(const device_t *info)) { neat_t *dev; uint8_t dram_mode = 0; - uint8_t i; + uint8_t j; /* Create an instance. */ dev = (neat_t *) malloc(sizeof(neat_t)); memset(dev, 0x00, sizeof(neat_t)); + /* Get configured I/O address. */ + j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; + dev->ems_base = 0x0208 + (0x10 * j); + + /* Get configured frame address. */ + j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; + dev->ems_frame = 0xc0000 + (EMS_PGSIZE * j); + + mem_mapping_disable(&ram_mid_mapping); + + /* + * For each supported page (we can have a maximum of 4), + * create, initialize and disable the mappings, and set + * up the I/O control handler. + */ + for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { + /* Create and initialize a page mapping. */ + mem_mapping_add(&dev->ems[i].mapping, + dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE, + ems_readb, ems_readw, NULL, + ems_writeb, ems_writew, NULL, + ram, MEM_MAPPING_INTERNAL, + &(dev->ems[i])); + + /* Disable for now. */ + mem_mapping_disable(&dev->ems[i].mapping); + } + + for (uint8_t i = 0; i < 32; i++) { + dev->shadow[i].virt_base = dev->shadow[i].phys_base = + (i * EMS_PGSIZE) + 0x00080000; + dev->shadow[i].enabled = 1; + } + /* Initialize some of the registers to specific defaults. */ - for (i = REG_RA0; i <= REG_RB11; i++) { + for (uint8_t i = REG_RA0; i <= REG_RB12; i++) { dev->indx = i; - neat_write(0x0023, 0x00, dev); + neat_write(0x0023, defaults[i & REG_MASK], dev); } /* From b36d2c5abad252cb073cf382120762c22d7daccf Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 16:59:53 +0100 Subject: [PATCH 03/43] Few corrections to Quantum Fireball series --- src/disk/hdd.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index 5243f016b..035bc83c6 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -448,13 +448,6 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-2] Quantum Fireball 640AT", .internal_name = "FB64A341", .model = "QUANTUM FIREBALL 640AT", .zones = 2, .avg_spt = 120, .heads = 2, .rpm = 5400, .full_stroke_ms = 24, .track_seek_ms = 3.1, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, { .name = "[ATA-2] Quantum Fireball TM1080AT", .internal_name = "TM10A462", .model = "QUANTUM FIREBALL TM1.0A", .zones = 2, .avg_spt = 120, .heads = 2, .rpm = 4500, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 8 }, { .name = "[ATA-2] Quantum Fireball TM1.2AT", .internal_name = "TM12A012", .model = "QUANTUM FIREBALL TM1.2A", .zones = 4, .avg_spt = 120, .heads = 2, .rpm = 4500, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Quantum Fireball SE8.4A", .internal_name = "SE84A011", .model = "QUANTUM FIREBALL SE8.4A", .zones = 4, .avg_spt = 100, .heads = 8, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, - { .name = "[ATA-2] Quantum Fireball SE6.4A", .internal_name = "SE64A011", .model = "QUANTUM FIREBALL SE6.4A", .zones = 3, .avg_spt = 100, .heads = 6, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, - { .name = "[ATA-2] Quantum Fireball ST3.2AT", .internal_name = "ST32A461", .model = "QUANTUM FIREBALL ST3.2A", .zones = 4, .avg_spt = 100, .heads = 4, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, - { .name = "[ATA-2] Quantum Fireball CR4.3AT", .internal_name = "CR43A013", .model = "QUANTUM FIREBALL CR4.3A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 22, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-2] Quantum Fireball EX5.1A", .internal_name = "EX51A012", .model = "QUANTUM FIREBALL EX5.1A", .zones = 8, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 22, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-2] Quantum Fireball EX10.2A", .internal_name = "EX10A011", .model = "QUANTUM FIREBALL EX10.2A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-2] Quantum Fireball EX12.7A", .internal_name = "EX12A011", .model = "QUANTUM FIREBALL EX12.7A", .zones = 4, .avg_spt = 110, .heads = 8, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-2] Samsung PLS-31274A", .internal_name = "PLS31274A", .model = "SAMSUNG PLS-31274A", .zones = 4, .avg_spt = 110, .heads = 4, .rpm = 4500, .full_stroke_ms = 45, .track_seek_ms = 4.5, .rcache_num_seg = 4, .rcache_seg_size = 256, .max_multiple = 8 }, { .name = "[ATA-2] Samsung Winner-1", .internal_name = "WNR31601A", .model = "SAMSUNG WNR-31601A", .zones = 8, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 22, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-2] Seagate Medalist (ST3780A)", .internal_name = "ST3780A", .model = "ST3780A", .zones = 8, .avg_spt = 120, .heads = 4, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.5, .rcache_num_seg = 4, .rcache_seg_size = 256, .max_multiple = 16 }, @@ -501,6 +494,9 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-4] Maxtor DiamondMax Plus 6800 (92049U6)", .internal_name = "92049U6", .model = "Maxtor 92049U6", .zones = 16, .avg_spt = 90, .heads = 6, .rpm = 7200, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, { .name = "[ATA-4] Maxtor DiamondMax Plus 6800 (92732U8)", .internal_name = "92732U8", .model = "Maxtor 92732U8", .zones = 16, .avg_spt = 90, .heads = 8, .rpm = 7200, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, { .name = "[ATA-4] Quantum Bigfoot TX4.3AT", .internal_name = "TX043A011", .model = "QUANTUM BIGFOOT TX4.3A", .zones = 2, .avg_spt = 120, .heads = 2, .rpm = 4000, .full_stroke_ms = 30, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 32 }, + { .name = "[ATA-4] Quantum Fireball ST3.2AT", .internal_name = "ST32A461", .model = "QUANTUM FIREBALL ST3.2A", .zones = 4, .avg_spt = 100, .heads = 4, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, + { .name = "[ATA-4] Quantum Fireball SE6.4A", .internal_name = "SE64A011", .model = "QUANTUM FIREBALL SE6.4A", .zones = 3, .avg_spt = 100, .heads = 6, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, + { .name = "[ATA-4] Quantum Fireball SE8.4A", .internal_name = "SE84A011", .model = "QUANTUM FIREBALL SE8.4A", .zones = 4, .avg_spt = 100, .heads = 8, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Seagate Medalist 2122", .internal_name = "ST32122A", .model = "ST32122A", .zones = 16, .avg_spt = 115, .heads = 2, .rpm = 4500, .full_stroke_ms = 23, .track_seek_ms = 3.8, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Seagate Medalist 3321", .internal_name = "ST33221A", .model = "ST33221A", .zones = 16, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1.7, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Seagate Medalist 4321", .internal_name = "ST34321A", .model = "ST34321A", .zones = 16, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2.2, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, @@ -513,9 +509,15 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-4] Western Digital Caviar 33200", .internal_name = "AC33200", .model = "WDC AC33200-00LA", .zones = 16, .avg_spt = 110, .heads = 5, .rpm = 5200, .full_stroke_ms = 40, .track_seek_ms = 3, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, { .name = "[ATA-5] IBM Travelstar 6GN", .internal_name = "DARA206000", .model = "IBM-DARA-206000", .zones = 12, .avg_spt = 92, .heads = 2, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] IBM Travelstar 9GN", .internal_name = "DARA209000", .model = "IBM-DARA-209000", .zones = 12, .avg_spt = 92, .heads = 3, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, - { .name = "[ATA-5] IBM/Hitachi Travelstar 12GN", .internal_name = "DARA212000", .model = "IBM-DARA-212000", .zones = 12, .avg_spt = 92, .heads = 4, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, // Either Hitachi or IBM OEM + { .name = "[ATA-5] IBM/Hitachi Travelstar 12GN", .internal_name = "DARA212000", .model = "IBM-DARA-212000", .zones = 12, .avg_spt = 92, .heads = 4, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, // Either Hitachi or IBM OEM { .name = "[ATA-5] Maxtor DiamondMax VL 17", .internal_name = "90871U2", .model = "Maxtor 90871U2", .zones = 16, .avg_spt = 90, .heads = 3, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 0.9, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, { .name = "[ATA-5] Maxtor DiamondMax VL 20", .internal_name = "91021U2", .model = "Maxtor 91021U2", .zones = 16, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Quantum Fireball EX3.2A", .internal_name = "EX32A012", .model = "QUANTUM FIREBALL EX3.2A", .zones = 1, .avg_spt = 110, .heads = 2, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball EX5.1A", .internal_name = "EX51A012", .model = "QUANTUM FIREBALL EX5.1A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball EX6.4A", .internal_name = "EX64A012", .model = "QUANTUM FIREBALL EX6.4A", .zones = 2, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball EX10.2A", .internal_name = "EX10A011", .model = "QUANTUM FIREBALL EX10.2A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball EX12.7A", .internal_name = "EX12A011", .model = "QUANTUM FIREBALL EX12.7A", .zones = 4, .avg_spt = 110, .heads = 8, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR4.3AT", .internal_name = "CR43A013", .model = "QUANTUM FIREBALL CR4.3A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 22, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV0682D)", .internal_name = "SV0682D", .model = "SAMSUNG SV0682D", .zones = 8, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1023D)", .internal_name = "SV1023D", .model = "SAMSUNG SV1023D", .zones = 8, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 4.3gb", .internal_name = "ST34313A", .model = "ST34313A", .zones = 16, .avg_spt = 89, .heads = 1, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, From 46426d5e929bb9d2d24f2e85118c412ce4d2aa3f Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 17:16:04 +0100 Subject: [PATCH 04/43] Update cdrom.h for TEAC CD-532E/NEC CDR-1900A --- src/include/86box/cdrom.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index efb45ecfb..7272f5e8c 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -95,6 +95,7 @@ enum CDROM_TYPE_NEC_77_106, CDROM_TYPE_NEC_211_100, CDROM_TYPE_NEC_464_105, + CDROM_TYPE_NEC_CDR_1900A_100, CDROM_TYPE_ShinaKen_DM3x1S_104, CDROM_TYPE_SONY_CDU541_10i, CDROM_TYPE_SONY_CDU561_18k, @@ -102,6 +103,7 @@ enum CDROM_TYPE_PHILIPS_CDD2600_107, CDROM_TYPE_PIONEER_DRM604X_2403, CDROM_TYPE_PLEXTOR_PX32TS_103, + CDROM_TYPE_TEAC_CD532E_20A, CDROM_TYPE_TEAC_CD50_100, CDROM_TYPE_TEAC_R55S_10R, CDROM_TYPE_TEXEL_DM3024_100, @@ -145,9 +147,11 @@ static const struct { "NEC", "CD-ROM DRIVE:273", "4.20", "NEC CD-ROM DRIVE:273 4.20", "NEC_CD-ROM_DRIVE273_4.20", BUS_TYPE_IDE }, { "NEC", "CD-ROM DRIVE:280", "1.05", "NEC CD-ROM DRIVE:280 1.05", "NEC_CD-ROM_DRIVE280_1.05", BUS_TYPE_IDE }, { "NEC", "CD-ROM DRIVE:280", "3.08", "NEC CD-ROM DRIVE:280 3.08", "NEC_CD-ROM_DRIVE280_3.08", BUS_TYPE_IDE }, + { "NEC", "CDR-1900A", "1.00", "NEC CDR-1900A 1.00", "NEC_CDR-1900A_1.00", BUS_TYPE_IDE }, { "PHILIPS", "CD-ROM PCA403CD", "U31P", "PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE }, { "SONY", "CD-ROM CDU76", "1.0i", "SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE }, { "SONY", "CD-ROM CDU311", "3.0h", "SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE }, + { "TEAC", "CD-532E", "2.0A", "TEAC CD-532E 2.0A", "TEAC_CD_532E_2.0A", BUS_TYPE_IDE }, { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, { "CHINON", "CD-ROM CDS-431", "H42 ", "[SCSI-1] CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI }, From 68a8392baf2cbd5d94554ac43099c4f59949bd9a Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 17:31:21 +0100 Subject: [PATCH 05/43] Add TEAC CD-532E (32X)/NEC CDR-1900A (32X) --- src/scsi/scsi_cdrom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index ad7f0d1c0..ddbb65849 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -4097,6 +4097,10 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "3.08 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "NEC CD-ROM DRIVE:280 ", 40); /* Model */ break; + case CDROM_TYPE_NEC_CDR_1900A_100: + ide_padstr((char *) (ide->buffer + 23), "1.00 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "NEC CDR-1900A ", 40); /* Model */ + break; case CDROM_TYPE_PHILIPS_PCA403CD_U31P: ide_padstr((char *) (ide->buffer + 23), "U31P ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "PHILIPS CD-ROM PCA403CD ", 40); /* Model */ @@ -4109,6 +4113,10 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "3.0h ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "SONY CD-ROM CDU311 ", 40); /* Model */ break; + case CDROM_TYPE_TEAC_CD_532E_20A: + ide_padstr((char *) (ide->buffer + 23), "2.0A ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TEAC CD-532E ", 40); /* Model */ + break; case CDROM_TYPE_TOSHIBA_5302TA_0305: ide_padstr((char *) (ide->buffer + 23), "0305 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-5302TA ", 40); /* Model */ From 514abd4abde47b7e968d9f93194e3756964ba634 Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 17:42:49 +0100 Subject: [PATCH 06/43] Update scsi_cdrom.c --- src/scsi/scsi_cdrom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index ddbb65849..cdf653626 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -4113,7 +4113,7 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "3.0h ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "SONY CD-ROM CDU311 ", 40); /* Model */ break; - case CDROM_TYPE_TEAC_CD_532E_20A: + case CDROM_TYPE_TEAC_CD532E_20A: ide_padstr((char *) (ide->buffer + 23), "2.0A ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "TEAC CD-532E ", 40); /* Model */ break; From 1aee794ae1cae4f684fed8251bd4ccef0bc09d27 Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 17:58:29 +0100 Subject: [PATCH 07/43] Update cdrom.h From 9bb96bd836eae91c53725ae162f5d0c8fdd46e41 Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 18:47:54 +0100 Subject: [PATCH 08/43] Fireball EX/CR now complete --- src/disk/hdd.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index 035bc83c6..e79f0f6c0 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -495,6 +495,7 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-4] Maxtor DiamondMax Plus 6800 (92732U8)", .internal_name = "92732U8", .model = "Maxtor 92732U8", .zones = 16, .avg_spt = 90, .heads = 8, .rpm = 7200, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, { .name = "[ATA-4] Quantum Bigfoot TX4.3AT", .internal_name = "TX043A011", .model = "QUANTUM BIGFOOT TX4.3A", .zones = 2, .avg_spt = 120, .heads = 2, .rpm = 4000, .full_stroke_ms = 30, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 32 }, { .name = "[ATA-4] Quantum Fireball ST3.2AT", .internal_name = "ST32A461", .model = "QUANTUM FIREBALL ST3.2A", .zones = 4, .avg_spt = 100, .heads = 4, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, + { .name = "[ATA-4] Quantum Fireball SE4.3A", .internal_name = "SE43A011", .model = "QUANTUM FIREBALL SE4.3A", .zones = 2, .avg_spt = 100, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Quantum Fireball SE6.4A", .internal_name = "SE64A011", .model = "QUANTUM FIREBALL SE6.4A", .zones = 3, .avg_spt = 100, .heads = 6, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Quantum Fireball SE8.4A", .internal_name = "SE84A011", .model = "QUANTUM FIREBALL SE8.4A", .zones = 4, .avg_spt = 100, .heads = 8, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Seagate Medalist 2122", .internal_name = "ST32122A", .model = "ST32122A", .zones = 16, .avg_spt = 115, .heads = 2, .rpm = 4500, .full_stroke_ms = 23, .track_seek_ms = 3.8, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, @@ -517,7 +518,10 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-5] Quantum Fireball EX6.4A", .internal_name = "EX64A012", .model = "QUANTUM FIREBALL EX6.4A", .zones = 2, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball EX10.2A", .internal_name = "EX10A011", .model = "QUANTUM FIREBALL EX10.2A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball EX12.7A", .internal_name = "EX12A011", .model = "QUANTUM FIREBALL EX12.7A", .zones = 4, .avg_spt = 110, .heads = 8, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-5] Quantum Fireball CR4.3AT", .internal_name = "CR43A013", .model = "QUANTUM FIREBALL CR4.3A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 22, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR4.3A", .internal_name = "CR43A013", .model = "QUANTUM FIREBALL CR4.3A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR6.4A", .internal_name = "CR64A011", .model = "QUANTUM FIREBALL CR6.4A", .zones = 2, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR8.4A", .internal_name = "CR84A011", .model = "QUANTUM FIREBALL CR8.4A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR13.0A", .internal_name = "CR13A011", .model = "QUANTUM FIREBALL CR13.0A", .zones = 4, .avg_spt = 110, .heads = 8, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV0682D)", .internal_name = "SV0682D", .model = "SAMSUNG SV0682D", .zones = 8, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1023D)", .internal_name = "SV1023D", .model = "SAMSUNG SV1023D", .zones = 8, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 4.3gb", .internal_name = "ST34313A", .model = "ST34313A", .zones = 16, .avg_spt = 89, .heads = 1, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, From 70891ffdb5b944c907b85f094a747c1ccdc3a303 Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 18:59:31 +0100 Subject: [PATCH 09/43] Updated INQUIRY --- src/include/86box/cdrom.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index 7272f5e8c..07ca72d36 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -80,9 +80,11 @@ enum CDROM_TYPE_NEC_273_420, CDROM_TYPE_NEC_280_105, CDROM_TYPE_NEC_280_308, + CDROM_TYPE_NEC_CDR_1900A_100 CDROM_TYPE_PHILIPS_PCA403CD_U31P, CDROM_TYPE_SONY_CDU76_10i, CDROM_TYPE_SONY_CDU311_30h, + CDROM_TYPE_TEAC_CD532E_20A, CDROM_TYPE_TOSHIBA_5302TA_0305, CDROM_TYPE_TOSHIBA_5702B_TA70, CDROM_TYPE_CHINON_CDS431_H42, From 1d6a49d7494c4a5cb3251161e286d3004bf5b9a8 Mon Sep 17 00:00:00 2001 From: unreal9010 <84349460+unreal9010@users.noreply.github.com> Date: Tue, 14 Jan 2025 19:11:56 +0100 Subject: [PATCH 10/43] Update cdrom.h --- src/include/86box/cdrom.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index 07ca72d36..5d90d84a4 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -80,7 +80,7 @@ enum CDROM_TYPE_NEC_273_420, CDROM_TYPE_NEC_280_105, CDROM_TYPE_NEC_280_308, - CDROM_TYPE_NEC_CDR_1900A_100 + CDROM_TYPE_NEC_CDR_1900A_100, CDROM_TYPE_PHILIPS_PCA403CD_U31P, CDROM_TYPE_SONY_CDU76_10i, CDROM_TYPE_SONY_CDU311_30h, @@ -97,7 +97,6 @@ enum CDROM_TYPE_NEC_77_106, CDROM_TYPE_NEC_211_100, CDROM_TYPE_NEC_464_105, - CDROM_TYPE_NEC_CDR_1900A_100, CDROM_TYPE_ShinaKen_DM3x1S_104, CDROM_TYPE_SONY_CDU541_10i, CDROM_TYPE_SONY_CDU561_18k, @@ -105,7 +104,6 @@ enum CDROM_TYPE_PHILIPS_CDD2600_107, CDROM_TYPE_PIONEER_DRM604X_2403, CDROM_TYPE_PLEXTOR_PX32TS_103, - CDROM_TYPE_TEAC_CD532E_20A, CDROM_TYPE_TEAC_CD50_100, CDROM_TYPE_TEAC_R55S_10R, CDROM_TYPE_TEXEL_DM3024_100, From bf3be9c0c7837e730b93cc2d5837c87c2602d3c9 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 14 Jan 2025 16:27:54 -0500 Subject: [PATCH 11/43] Correct EV-165A's name --- src/device/isamem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/isamem.c b/src/device/isamem.c index a3baf466d..94f554473 100644 --- a/src/device/isamem.c +++ b/src/device/isamem.c @@ -1622,7 +1622,7 @@ static const device_config_t ev165a_config[] = { }; static const device_t ev165a_device = { - .name = "Everex Magi Magic EV-165A", + .name = "Everex Maxi Magic EV-165A", .internal_name = "ev165a", .flags = DEVICE_ISA, .local = ISAMEM_EV165A_CARD, From 7eef0665b5db8eba65e08f9dbbf76e427f038f3e Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 14 Jan 2025 16:45:07 -0500 Subject: [PATCH 12/43] Fix EV-165A config --- src/device/isamem.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/device/isamem.c b/src/device/isamem.c index 94f554473..83e938abd 100644 --- a/src/device/isamem.c +++ b/src/device/isamem.c @@ -1547,12 +1547,12 @@ static const device_config_t ev165a_config[] = { .description = "Memory size", .type = CONFIG_SPINNER, .default_string = "", - .default_int = 512, + .default_int = 256, .file_filter = "", .spinner = { .min = 0, .max = 2048, - .step = 512 + .step = 256 }, .selection = { { 0 } } }, @@ -1561,12 +1561,12 @@ static const device_config_t ev165a_config[] = { .description = "Start Address", .type = CONFIG_SPINNER, .default_string = "", - .default_int = 0, + .default_int = 64, .file_filter = "", .spinner = { - .min = 0, - .max = 896, - .step = 128 + .min = 64, + .max = 640, + .step = 64 }, .selection = { { 0 } } }, @@ -1579,8 +1579,8 @@ static const device_config_t ev165a_config[] = { .file_filter = "", .spinner = { .min = 0, - .max = 16384, - .step = 128 + .max = 2048, + .step = 256 }, .selection = { { 0 } } }, From 4e8802c23ee9e7d771328398aa91863edf98f282 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 15 Jan 2025 00:37:02 +0100 Subject: [PATCH 13/43] Fix maximum amount of RAM on a few NEAT machine where it was set unrealistically high. --- src/machine/machine_table.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 330b7d52a..47a33fa8c 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -3597,7 +3597,7 @@ const machine_t machines[] = { .flags = MACHINE_IDE | MACHINE_VIDEO, .ram = { .min = 512, - .max = 16384, + .max = 5120, .step = 128 }, .nvrmask = 127, @@ -3637,7 +3637,7 @@ const machine_t machines[] = { .flags = MACHINE_FLAGS_NONE, .ram = { .min = 512, - .max = 16384, + .max = 8192, .step = 128 }, .nvrmask = 127, From 7bc89f6feb0bf631294382c4c1945555696b0c12 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 07:13:21 +0700 Subject: [PATCH 14/43] Added a plenty of IDE CD-ROM models -Added other four ATA-3 models -Corrections to Western Digital pre-ATA-4 HDD models --- src/disk/hdd.c | 30 ++++++++++++++------------ src/include/86box/cdrom.h | 22 ++++++++++++++++++++ src/scsi/scsi_cdrom.c | 44 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 13 deletions(-) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index e79f0f6c0..328d8dcb0 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -431,10 +431,10 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-1] Quantum ProDrive LPS 105", .internal_name = "LPS105AT", .model = "QUANTUM PRODRIVE 105", .zones = 1, .avg_spt = 170, .heads = 2, .rpm = 3662, .full_stroke_ms = 45, .track_seek_ms = 5, .rcache_num_seg = 1, .rcache_seg_size = 64, .max_multiple = 8 }, { .name = "[ATA-1] Quantum ProDrive LPS 120AT", .internal_name = "GM12A012", .model = "QUANTUM PRODRIVE 120AT", .zones = 1, .avg_spt = 150, .heads = 2, .rpm = 3605, .full_stroke_ms = 45, .track_seek_ms = 4, .rcache_num_seg = 1, .rcache_seg_size = 64, .max_multiple = 8 }, { .name = "[ATA-1] Seagate ST3243A", .internal_name = "ST3243A", .model = "ST3243A", .zones = 1, .avg_spt = 140, .heads = 4, .rpm = 3811, .full_stroke_ms = 32, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 32, .max_multiple = 8 }, - { .name = "[ATA-1] Western Digital Caviar 140", .internal_name = "WDAC140", .model = "WDC WDAC140-50", .zones = 4, .avg_spt = 170, .heads = 2, .rpm = 3551, .full_stroke_ms = 28, .track_seek_ms = 6, .rcache_num_seg = 8, .rcache_seg_size = 8, .max_multiple = 8 }, - { .name = "[ATA-1] Western Digital Caviar 280", .internal_name = "WDAC280", .model = "WDC WDAC280-00", .zones = 4, .avg_spt = 170, .heads = 4, .rpm = 3595, .full_stroke_ms = 28, .track_seek_ms = 6, .rcache_num_seg = 8, .rcache_seg_size = 32, .max_multiple = 8 }, - { .name = "[ATA-1] Western Digital Caviar 1210", .internal_name = "WDAC1210", .model = "WDC WDAC1210-21F", .zones = 4, .avg_spt = 130, .heads = 2, .rpm = 3314, .full_stroke_ms = 33, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-1] Western Digital Caviar 2120", .internal_name = "WDAC2120", .model = "WDC WDAC2120-00M", .zones = 4, .avg_spt = 140, .heads = 2, .rpm = 3605, .full_stroke_ms = 28, .track_seek_ms = 2.8, .rcache_num_seg = 8, .rcache_seg_size = 32, .max_multiple = 8 }, + { .name = "[ATA-1] Western Digital Caviar 140", .internal_name = "AC140", .model = "WDC AC140", .zones = 4, .avg_spt = 170, .heads = 2, .rpm = 3551, .full_stroke_ms = 28, .track_seek_ms = 6, .rcache_num_seg = 8, .rcache_seg_size = 8, .max_multiple = 8 }, + { .name = "[ATA-1] Western Digital Caviar 280", .internal_name = "AC280", .model = "WDC AC280", .zones = 4, .avg_spt = 170, .heads = 4, .rpm = 3595, .full_stroke_ms = 28, .track_seek_ms = 6, .rcache_num_seg = 8, .rcache_seg_size = 32, .max_multiple = 8 }, + { .name = "[ATA-1] Western Digital Caviar 1210", .internal_name = "AC1210", .model = "WDC AC1210F", .zones = 4, .avg_spt = 130, .heads = 2, .rpm = 3314, .full_stroke_ms = 33, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-1] Western Digital Caviar 2120", .internal_name = "AC2120", .model = "WDC AC2120M", .zones = 4, .avg_spt = 140, .heads = 2, .rpm = 3605, .full_stroke_ms = 28, .track_seek_ms = 2.8, .rcache_num_seg = 8, .rcache_seg_size = 32, .max_multiple = 8 }, { .name = "[ATA-2] IBM DBOA-2720", .internal_name = "DBOA2720", .model = "IBM-DBOA-2720", .zones = 2, .avg_spt = 135, .heads = 2, .rpm = 4000, .full_stroke_ms = 30, .track_seek_ms = 5, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 8 }, { .name = "[ATA-2] IBM DeskStar 4 (DCAA-32880)", .internal_name = "DCAA32880", .model = "IBM-DCAA-32880", .zones = 8, .avg_spt = 85, .heads = 2, .rpm = 5400, .full_stroke_ms = 19, .track_seek_ms = 1.7, .rcache_num_seg = 4, .rcache_seg_size = 96, .max_multiple = 16 }, { .name = "[ATA-2] IBM DeskStar 4 (DCAA-33610)", .internal_name = "DCAA33610", .model = "IBM-DCAA-33610", .zones = 8, .avg_spt = 85, .heads = 3, .rpm = 5400, .full_stroke_ms = 19, .track_seek_ms = 1.7, .rcache_num_seg = 4, .rcache_seg_size = 96, .max_multiple = 16 }, @@ -460,14 +460,15 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-2] Seagate Medalist 1270SL", .internal_name = "ST51270A", .model = "ST51270A", .zones = 8, .avg_spt = 105, .heads = 3, .rpm = 5736, .full_stroke_ms = 25, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-2] Seagate Medalist 3240", .internal_name = "ST33240A", .model = "ST33240A", .zones = 16, .avg_spt = 125, .heads = 8, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-2] Toshiba MK2101MAN (HDD2616)", .internal_name = "HDD2616", .model = "TOSHIBA MK2101MAN", .zones = 8, .avg_spt = 130, .heads = 10, .rpm = 4200, .full_stroke_ms = 36, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 16 }, - { .name = "[ATA-2] Western Digital Caviar 2540", .internal_name = "WDAC2540", .model = "WDC WDAC2540-00H", .zones = 4, .avg_spt = 250, .heads = 2, .rpm = 4500, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Western Digital Caviar 2850", .internal_name = "WDAC2850", .model = "WDC WDAC2850-00F", .zones = 4, .avg_spt = 230, .heads = 2, .rpm = 5200, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Western Digital Caviar 11000", .internal_name = "WDAC11000", .model = "WDC WDAC11000-00H", .zones = 4, .avg_spt = 120, .heads = 2, .rpm = 5200, .full_stroke_ms = 12, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Western Digital Caviar 21200", .internal_name = "WDAC21200", .model = "WDC WDAC21200-00H", .zones = 4, .avg_spt = 110, .heads = 4, .rpm = 5200, .full_stroke_ms = 39, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Western Digital Caviar 21600", .internal_name = "WDAC21600", .model = "WDC WDAC21600-00H", .zones = 8, .avg_spt = 140, .heads = 4, .rpm = 5200, .full_stroke_ms = 30, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Western Digital Caviar 22000", .internal_name = "AC22000", .model = "WDC AC22000-32LA", .zones = 8, .avg_spt = 130, .heads = 3, .rpm = 5200, .full_stroke_ms = 33, .track_seek_ms = 3.5, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, - { .name = "[ATA-2] Western Digital Caviar 22100", .internal_name = "WDAC22100", .model = "WDC WDAC22100-18H", .zones = 8, .avg_spt = 140, .heads = 4, .rpm = 5200, .full_stroke_ms = 30, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, - { .name = "[ATA-2] Western Digital Caviar 31200", .internal_name = "WDAC31200", .model = "WDC WDAC31200-00F", .zones = 8, .avg_spt = 110, .heads = 4, .rpm = 4500, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 8, .rcache_seg_size = 64, .max_multiple = 16 }, + { .name = "[ATA-2] Western Digital Caviar 2540", .internal_name = "AC2540", .model = "WDC AC2540H", .zones = 4, .avg_spt = 250, .heads = 2, .rpm = 4500, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-2] Western Digital Caviar 2850", .internal_name = "AC2850", .model = "WDC AC2850F", .zones = 4, .avg_spt = 230, .heads = 2, .rpm = 5200, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-2] Western Digital Caviar 11000", .internal_name = "AC11000", .model = "WDC AC11000H", .zones = 4, .avg_spt = 120, .heads = 2, .rpm = 5200, .full_stroke_ms = 12, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-2] Western Digital Caviar 21200", .internal_name = "AC21200", .model = "WDC AC21200H", .zones = 4, .avg_spt = 110, .heads = 4, .rpm = 5200, .full_stroke_ms = 39, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-2] Western Digital Caviar 21600", .internal_name = "AC21600", .model = "WDC AC21600H", .zones = 8, .avg_spt = 140, .heads = 4, .rpm = 5200, .full_stroke_ms = 30, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-2] Western Digital Caviar 22000", .internal_name = "AC22000", .model = "WDC AC22000LA", .zones = 8, .avg_spt = 130, .heads = 3, .rpm = 5200, .full_stroke_ms = 33, .track_seek_ms = 3.5, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, + { .name = "[ATA-2] Western Digital Caviar 22100", .internal_name = "AC22100", .model = "WDC AC22100H", .zones = 8, .avg_spt = 140, .heads = 4, .rpm = 5200, .full_stroke_ms = 30, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, + { .name = "[ATA-2] Western Digital Caviar 31200", .internal_name = "AC31200", .model = "WDC AC31200F", .zones = 8, .avg_spt = 110, .heads = 4, .rpm = 4500, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 8, .rcache_seg_size = 64, .max_multiple = 16 }, + { .name = "[ATA-3] Connor CFS1275A", .internal_name = "CFS1275A", .model = "Connor Peripherals 1275MB - CFS1275A", .zones = 4, .avg_spt = 130, .heads = 2, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.8, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 16 }, { .name = "[ATA-3] Fujitsu MPA3017AT", .internal_name = "MPA3017AT", .model = "FUJITSU MPA3017AT", .zones = 5, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-3] Fujitsu MPA3026AT", .internal_name = "MPA3026AT", .model = "FUJITSU MPA3026AT", .zones = 8, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-3] Fujitsu MPA3035AT", .internal_name = "MPA3035AT", .model = "FUJITSU MPA3035AT", .zones = 11, .avg_spt = 95, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, @@ -475,9 +476,12 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-3] Fujitsu MPA3052AT", .internal_name = "MPA3052AT", .model = "FUJITSU MPA3052AT", .zones = 16, .avg_spt = 95, .heads = 6, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-3] Samsung Voyager 6", .internal_name = "SV0844A", .model = "SAMSUNG SV0844A", .zones = 8, .avg_spt = 105, .heads = 4, .rpm = 5400, .full_stroke_ms = 22, .track_seek_ms = 2, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-3] Samsung Winner 5X", .internal_name = "WU33205A", .model = "SAMSUNG WU33205A", .zones = 16, .avg_spt = 100, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, + { .name = "[ATA-3] Seagate Medalist 636", .internal_name = "ST3636A", .model = "Seagate Technology 636MB - ST3636A", .zones = 2, .avg_spt = 130, .heads = 2, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.8, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 8 }, + { .name = "[ATA-3] Seagate Medalist 1082", .internal_name = "ST31082A", .model = "Seagate Technology 1082MB - ST31082A", .zones = 4, .avg_spt = 130, .heads = 3, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.8, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 8 }, + { .name = "[ATA-3] Seagate Medalist 1276", .internal_name = "ST31276A", .model = "Seagate Technology 1275MB - ST31276A", .zones = 4, .avg_spt = 130, .heads = 3, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.8, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 16 }, { .name = "[ATA-3] Seagate Medalist 1720", .internal_name = "ST31720A", .model = "ST31720A", .zones = 4, .avg_spt = 120, .heads = 4, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 2, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-3] Seagate Medalist 2132", .internal_name = "ST32132A", .model = "ST32132A", .zones = 8, .avg_spt = 125, .heads = 6, .rpm = 4500, .full_stroke_ms = 30, .track_seek_ms = 2.3, .rcache_num_seg = 8, .rcache_seg_size = 120, .max_multiple = 16 }, - { .name = "[ATA-3] Western Digital Caviar 21700", .internal_name = "WDAC21700", .model = "WDC WDAC21700-40H", .zones = 8, .avg_spt = 85, .heads = 3, .rpm = 5200, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, // Apple Computer OEM only, not retail version + { .name = "[ATA-3] Western Digital Caviar 21700", .internal_name = "AC21700", .model = "WDC AC21700H", .zones = 8, .avg_spt = 85, .heads = 3, .rpm = 5200, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, // Apple Computer OEM only, not retail version { .name = "[ATA-4] Fujitsu MPB3021AT", .internal_name = "MPB3021AT", .model = "FUJITSU MPB3021AT", .zones = 7, .avg_spt = 100, .heads = 3, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 256, .max_multiple = 16 }, { .name = "[ATA-4] Fujitsu MPD3043AT", .internal_name = "MPD3043AT", .model = "FUJITSU MPD3043AT", .zones = 5, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 29, .track_seek_ms = 1.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-4] Fujitsu MPD3064AT", .internal_name = "MPD3064AT", .model = "FUJITSU MPD3064AT", .zones = 7, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 30, .track_seek_ms = 1.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index 5d90d84a4..d7868951e 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -65,11 +65,17 @@ enum { enum { CDROM_TYPE_86BOX_100, + CDROM_TYPE_ASUS_CDS500_141, + CDROM_TYPE_ASUS_CDS520_132, CDROM_TYPE_AZT_CDA46802I_115, CDROM_TYPE_BTC_BCD36XH_U10, CDROM_TYPE_GOLDSTAR_CRD_8160B_314, CDROM_TYPE_HITACHI_CDR_8130_0020, + CDROM_TYPE_HLDTST_GCE8525B_101, CDROM_TYPE_KENWOOD_UCR_421_208E, + CDROM_TYPE_LG_CRN8245B_120, + CDROM_TYPE_LTN48125S_1S07, + CDROM_TYPE_MATSHITA_585_Z18P, CDROM_TYPE_MATSHITA_587_7S13, CDROM_TYPE_MATSHITA_588_LS15, CDROM_TYPE_MATSHITA_571_10e, @@ -84,9 +90,14 @@ enum CDROM_TYPE_PHILIPS_PCA403CD_U31P, CDROM_TYPE_SONY_CDU76_10i, CDROM_TYPE_SONY_CDU311_30h, + CDROM_TYPE_SONY_CDU5225_NYS4, + CDROM_TYPE_TEAC_CD516E_10G, + CDROM_TYPE_TEAC_CD524EA_30D, CDROM_TYPE_TEAC_CD532E_20A, CDROM_TYPE_TOSHIBA_5302TA_0305, CDROM_TYPE_TOSHIBA_5702B_TA70, + CDROM_TYPE_TOSHIBA_6702B_1007, + CDROM_TYPE_TOSHIBA_M1802_1051, CDROM_TYPE_CHINON_CDS431_H42, CDROM_TYPE_CHINON_CDX435_M62, CDROM_TYPE_DEC_RRD45_0436, @@ -132,11 +143,17 @@ static const struct const int bus_type; } cdrom_drive_types[] = { { "86BOX", "CD-ROM", "1.00", "86BOX CD-ROM 1.00", "86BOX_CD-ROM_1.00", BUS_TYPE_BOTH }, + { "ASUS", "CD-S500/A", "1.41", "ASUS CD-S500/A 1.15", "ASUS_CD-S500A_1.41", BUS_TYPE_IDE }, + { "ASUS", "CD-S520/A4", "1.32", "ASUS CD-S520/A4 1.32", "ASUS_CD-S520A4_1.32", BUS_TYPE_IDE }, { "AZT", "CDA46802I", "1.15", "AZT CDA46802I 1.15", "AZT_CDA46802I_1.15", BUS_TYPE_IDE }, { "BTC", "CD-ROM BCD36XH", "U1.0", "BTC CD-ROM BCD36XH U1.0", "BTC_CD-ROM_BCD36XH_U1.0", BUS_TYPE_IDE }, { "GOLDSTAR", "CRD-8160B", "3.14", "GOLDSTAR CRD-8160B 3.14", "GOLDSTAR_CRD-8160B_3.14", BUS_TYPE_IDE }, { "HITACHI", "CDR-8130", "0020", "HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE }, + { "HL-DT-ST", "GCE-8525B", "1.01", "HL-DT-ST GCE-8525B 1.01", "HL-DT-ST_GCE-8525B_1.01", BUS_TYPE_IDE }, { "KENWOOD", "CD-ROM UCR-421", "208E", "KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE }, + { "LG", "CRN-8245B", "1.20", "LG CRN-8245B 1.20", "LG_CRN-8245B_1.20", BUS_TYPE_IDE }, + { "LITE-ON", "LTN48125S", "1S07", "LITE-ON LTN48125S 1S07", "LITE-ON_LTN48125S_1S07", BUS_TYPE_IDE }, + { "MATSHITA", "CD-ROM CR-585", "Z18P", "MATSHITA CD-ROM CR-585 Z18P", "MATSHITA_CD-ROM_CR-585_Z18P", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-587", "7S13", "MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-588", "LS15", "MATSHITA CD-ROM CR-588 LS15", "MATSHITA_CD-ROM_CR-588_LS15", BUS_TYPE_IDE }, { "MATSHITA", "CR-571", "1.0e", "MATSHITA CR-571 1.0e", "MATSHITA_CR-571_1.0e", BUS_TYPE_IDE }, @@ -151,9 +168,14 @@ static const struct { "PHILIPS", "CD-ROM PCA403CD", "U31P", "PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE }, { "SONY", "CD-ROM CDU76", "1.0i", "SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE }, { "SONY", "CD-ROM CDU311", "3.0h", "SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE }, + { "SONY", "CD-ROM CDU5225", "NYS4", "SONY CD-ROM CDU5225 NYS4", "SONY_CD-ROM_CDU5225_NYS4", BUS_TYPE_IDE }, + { "TEAC", "CD-516E", "1.0G", "TEAC CD-516E 1.0G", "TEAC_CD-516E_1.0G", BUS_TYPE_IDE }, + { "TEAC", "CD-524EA", "3.0D", "TEAC CD-524EA 3.0D", "TEAC_CD-524EA_3.0D", BUS_TYPE_IDE }, { "TEAC", "CD-532E", "2.0A", "TEAC CD-532E 2.0A", "TEAC_CD_532E_2.0A", BUS_TYPE_IDE }, { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6702B", "1007", "TOSHIBA CD-ROM XM-6702B 1007", "TOSHIBA_CD-ROM_XM-6702B_1007", BUS_TYPE_IDE }, + { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1.15", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, { "CHINON", "CD-ROM CDS-431", "H42 ", "[SCSI-1] CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI }, { "CHINON", "CD-ROM CDX-435", "M62 ", "[SCSI-1] CHINON CD-ROM CDX-435 M62", "CHINON_CD-ROM_CDX-435_M62", BUS_TYPE_SCSI }, { "DEC", "RRD45 (C) DEC", "0436", "[SCSI-1] DEC RRD45 0436", "DEC_RRD45_0436", BUS_TYPE_SCSI }, diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index cdf653626..9f8a86fc9 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -4037,6 +4037,14 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 27), device_identify, 40); /* Model */ } else { switch (dev->drv->type) { + case CDROM_TYPE_ASUS_CDS500_141: + ide_padstr((char *) (ide->buffer + 23), "1.41 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "ASUS CD-S500/A ", 40); /* Model */ + break; + case CDROM_TYPE_ASUS_CDS520_132: + ide_padstr((char *) (ide->buffer + 23), "1.32 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "ASUS CD-S520/A4 ", 40); /* Model */ + break; case CDROM_TYPE_AZT_CDA46802I_115: ide_padstr((char *) (ide->buffer + 23), "1.15 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "AZT CDA46802I ", 40); /* Model */ @@ -4053,10 +4061,26 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "0020 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "HITACHI CDR-8130 ", 40); /* Model */ break; + case CDROM_TYPE_HLDTST_GCE8525B_101: + ide_padstr((char *) (ide->buffer + 23), "1.01 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "HL-DT-ST GCE-8525B ", 40); /* Model */ + break; case CDROM_TYPE_KENWOOD_UCR_421_208E: ide_padstr((char *) (ide->buffer + 23), "208E ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "KENWOOD CD-ROM UCR-421 ", 40); /* Model */ break; + case CDROM_TYPE_LG_CRN8245B_120: + ide_padstr((char *) (ide->buffer + 23), "1.20 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "LG CD-ROM CRN-8245B ", 40); /* Model */ + break; + case CDROM_TYPE_LTN48125S_1S07: + ide_padstr((char *) (ide->buffer + 23), "1S07 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "LTN48125S ", 40); /* Model */ + break; + case CDROM_TYPE_MATSHITA_585_Z18P: + ide_padstr((char *) (ide->buffer + 23), "Z18P ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "MATSHITA CD-ROM CR-585 ", 40); /* Model */ + break; case CDROM_TYPE_MATSHITA_587_7S13: ide_padstr((char *) (ide->buffer + 23), "7S13 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "MATSHITA CD-ROM CR-587 ", 40); /* Model */ @@ -4113,6 +4137,18 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "3.0h ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "SONY CD-ROM CDU311 ", 40); /* Model */ break; + case CDROM_TYPE_SONY_CDU5225_NYS4: + ide_padstr((char *) (ide->buffer + 23), "NYS4 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "SONY CD-ROM CDU5225 ", 40); /* Model */ + break; + case CDROM_TYPE_TEAC_CD516E_10G: + ide_padstr((char *) (ide->buffer + 23), "1.0G ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TEAC CD-516E ", 40); /* Model */ + break; + case CDROM_TYPE_TEAC_CD524EA_30D: + ide_padstr((char *) (ide->buffer + 23), "3.0D ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TEAC CD-524EA ", 40); /* Model */ + break; case CDROM_TYPE_TEAC_CD532E_20A: ide_padstr((char *) (ide->buffer + 23), "2.0A ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "TEAC CD-532E ", 40); /* Model */ @@ -4125,6 +4161,14 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "TA70 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-5702B ", 40); /* Model */ break; + case CDROM_TYPE_TOSHIBA_6702B_1007: + ide_padstr((char *) (ide->buffer + 23), "1007 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-6702B ", 40); /* Model */ + break; + case CDROM_TYPE_TOSHIBA_M1802_1051: + ide_padstr((char *) (ide->buffer + 23), "1051 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TOSHIBA DVD-ROM SD-M1802 ", 40); /* Model */ + break; } } From 6b89a2e74d39373474cfb0b2148aa74006c90f64 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 07:30:48 +0700 Subject: [PATCH 15/43] Small name fixes to CDR-1900A --- src/include/86box/cdrom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index d7868951e..f579c8dc0 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -164,7 +164,7 @@ static const struct { "NEC", "CD-ROM DRIVE:273", "4.20", "NEC CD-ROM DRIVE:273 4.20", "NEC_CD-ROM_DRIVE273_4.20", BUS_TYPE_IDE }, { "NEC", "CD-ROM DRIVE:280", "1.05", "NEC CD-ROM DRIVE:280 1.05", "NEC_CD-ROM_DRIVE280_1.05", BUS_TYPE_IDE }, { "NEC", "CD-ROM DRIVE:280", "3.08", "NEC CD-ROM DRIVE:280 3.08", "NEC_CD-ROM_DRIVE280_3.08", BUS_TYPE_IDE }, - { "NEC", "CDR-1900A", "1.00", "NEC CDR-1900A 1.00", "NEC_CDR-1900A_1.00", BUS_TYPE_IDE }, + { "NEC", "CDR-1900A", "1.00", "NEC CDR-1900A 1.00", "NEC_CDR-1900A_1.00", BUS_TYPE_IDE }, { "PHILIPS", "CD-ROM PCA403CD", "U31P", "PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE }, { "SONY", "CD-ROM CDU76", "1.0i", "SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE }, { "SONY", "CD-ROM CDU311", "3.0h", "SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE }, From 75b99232839aec74dee4a6e13db5ee3a1bba2b08 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 07:45:13 +0700 Subject: [PATCH 16/43] Correct the revision names --- src/include/86box/cdrom.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index f579c8dc0..3895833a6 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -143,7 +143,7 @@ static const struct const int bus_type; } cdrom_drive_types[] = { { "86BOX", "CD-ROM", "1.00", "86BOX CD-ROM 1.00", "86BOX_CD-ROM_1.00", BUS_TYPE_BOTH }, - { "ASUS", "CD-S500/A", "1.41", "ASUS CD-S500/A 1.15", "ASUS_CD-S500A_1.41", BUS_TYPE_IDE }, + { "ASUS", "CD-S500/A", "1.41", "ASUS CD-S500/A 1.41", "ASUS_CD-S500A_1.41", BUS_TYPE_IDE }, { "ASUS", "CD-S520/A4", "1.32", "ASUS CD-S520/A4 1.32", "ASUS_CD-S520A4_1.32", BUS_TYPE_IDE }, { "AZT", "CDA46802I", "1.15", "AZT CDA46802I 1.15", "AZT_CDA46802I_1.15", BUS_TYPE_IDE }, { "BTC", "CD-ROM BCD36XH", "U1.0", "BTC CD-ROM BCD36XH U1.0", "BTC_CD-ROM_BCD36XH_U1.0", BUS_TYPE_IDE }, @@ -175,7 +175,7 @@ static const struct { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, { "TOSHIBA", "CD-ROM XM-6702B", "1007", "TOSHIBA CD-ROM XM-6702B 1007", "TOSHIBA_CD-ROM_XM-6702B_1007", BUS_TYPE_IDE }, - { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1.15", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, + { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1051", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, { "CHINON", "CD-ROM CDS-431", "H42 ", "[SCSI-1] CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI }, { "CHINON", "CD-ROM CDX-435", "M62 ", "[SCSI-1] CHINON CD-ROM CDX-435 M62", "CHINON_CD-ROM_CDX-435_M62", BUS_TYPE_SCSI }, { "DEC", "RRD45 (C) DEC", "0436", "[SCSI-1] DEC RRD45 0436", "DEC_RRD45_0436", BUS_TYPE_SCSI }, From 6d1d6d8830e1bc9caf11c9e1f6475edd5c1bb0eb Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 15 Jan 2025 04:30:59 +0100 Subject: [PATCH 17/43] NEAT: More fixes, closes #5145. --- src/chipset/neat.c | 252 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 193 insertions(+), 59 deletions(-) diff --git a/src/chipset/neat.c b/src/chipset/neat.c index 94f0d66e1..3b223bed4 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -231,6 +231,8 @@ typedef struct neat_t { uint16_t ems_size; /* EMS size in KB */ uint16_t ems_pages; /* EMS size in pages */ + uint32_t remap_base; + ram_page_t ems[EMS_MAXPAGE]; /* EMS page registers */ ram_page_t shadow[32]; /* Shadow RAM pages */ } neat_t; @@ -238,6 +240,9 @@ typedef struct neat_t { static uint8_t defaults[16] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x63, 0x10, 0x00, 0x00, 0x12 }; +static uint8_t masks[4] = { RB10_P0EXT, RB10_P1EXT, RB10_P2EXT, RB10_P3EXT }; +static uint8_t shifts[4] = { RB10_P0EXT_SH, RB10_P1EXT_SH, RB10_P2EXT_SH, RB10_P3EXT_SH }; + #ifdef ENABLE_NEAT_LOG int neat_do_log = ENABLE_NEAT_LOG; @@ -262,10 +267,17 @@ ems_readb(uint32_t addr, void *priv) { ram_page_t *dev = (ram_page_t *) priv; uint8_t ret = 0xff; +#ifdef ENABLE_NEAT_LOG + uint32_t old = addr; +#endif /* Grab the data. */ - ret = *(uint8_t *) &(ram[addr - dev->virt_base + dev->phys_base]); + addr = addr - dev->virt_base + dev->phys_base; + if (addr < (mem_size << 10)) + ret = *(uint8_t *) &(ram[addr]); + + neat_log("[R08] %08X -> %08X (%08X): ret = %02X\n", old, addr, (mem_size << 10), ret); return ret; } @@ -275,10 +287,17 @@ ems_readw(uint32_t addr, void *priv) { ram_page_t *dev = (ram_page_t *) priv; uint16_t ret = 0xffff; +#ifdef ENABLE_NEAT_LOG + uint32_t old = addr; +#endif /* Grab the data. */ - ret = *(uint16_t *) &(ram[addr - dev->virt_base + dev->phys_base]); + addr = addr - dev->virt_base + dev->phys_base; + if (addr < (mem_size << 10)) + ret = *(uint16_t *) &(ram[addr]); + + neat_log("[R16] %08X -> %08X (%08X): ret = %04X\n", old, addr, (mem_size << 10), ret); return ret; } @@ -287,9 +306,16 @@ static void ems_writeb(uint32_t addr, uint8_t val, void *priv) { ram_page_t *dev = (ram_page_t *) priv; +#ifdef ENABLE_NEAT_LOG + uint32_t old = addr; +#endif /* Write the data. */ - *(uint8_t *) &(ram[addr - dev->virt_base + dev->phys_base]) = val; + addr = addr - dev->virt_base + dev->phys_base; + neat_log("[W08] %08X -> %08X (%08X): val = %02X\n", old, addr, (mem_size << 10), val); + + if (addr < (mem_size << 10)) + *(uint8_t *) &(ram[addr]) = val; } /* Write one word to paged RAM. */ @@ -297,9 +323,16 @@ static void ems_writew(uint32_t addr, uint16_t val, void *priv) { ram_page_t *dev = (ram_page_t *) priv; +#ifdef ENABLE_NEAT_LOG + uint32_t old = addr; +#endif /* Write the data. */ - *(uint16_t *) &(ram[addr - dev->virt_base + dev->phys_base]) = val; + addr = addr - dev->virt_base + dev->phys_base; + neat_log("[W16] %08X -> %08X (%08X): val = %04X\n", old, addr, (mem_size << 10), val); + + if (addr < (mem_size << 10)) + *(uint16_t *) &(ram[addr]) = val; } static void @@ -379,10 +412,11 @@ shadow_recalc(neat_t *dev) static void ems_recalc(neat_t *dev, ram_page_t *ems) { - uint32_t page = ems->phys_base / EMS_PGSIZE; + uint32_t page = ems->phys_base / EMS_PGSIZE; - if ((dev->regs[REG_RB7] & RB7_EMSEN) && ems->enabled && - (page >= 0x40) && (page < (0x40 + dev->ems_pages))) { + neat_log("ems_recalc(): %08X, %04X, %04X\n", ems->virt_base, page, dev->ems_pages); + + if ((dev->regs[REG_RB7] & RB7_EMSEN) && ems->enabled && (page < dev->ems_pages)) { neat_log("ems_recalc(): %08X-%08X -> %08X-%08X\n", ems->virt_base, ems->virt_base + EMS_PGSIZE - 1, ems->phys_base, ems->phys_base + EMS_PGSIZE - 1); @@ -405,14 +439,20 @@ ems_recalc(neat_t *dev, ram_page_t *ems) if ((ems->virt_base >= 0x00080000) && (ems->virt_base < 0x00100000)) neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, 0x00, RAM_FMASK_EMS); } + + flushmmucache_nopc(); } static void ems_write(uint16_t port, uint8_t val, void *priv) { - neat_t *dev = (neat_t *) priv; + neat_t *dev = (neat_t *) priv; ram_page_t *ems; int vpage; + int8_t old_enabled; + uint32_t old_phys_base; + int8_t new_enabled; + uint32_t new_phys_base; #if NEAT_DEBUG > 1 neat_log("NEAT: ems_write(%04x, %02x)\n", port, val); @@ -422,12 +462,29 @@ ems_write(uint16_t port, uint8_t val, void *priv) vpage = (port / EMS_PGSIZE); ems = &dev->ems[vpage]; + neat_log("Port: %04X, val: %02X\n", port, val); + switch (port & 0x000f) { case 0x0008: case 0x0009: - ems->enabled = !!(val & 0x80); - ems->phys_base = (ems->phys_base & 0xffe00000) | ((val & 0x7f) * EMS_PGSIZE); - ems_recalc(dev, ems); + old_enabled = ems->enabled; + old_phys_base = ems->phys_base; + new_enabled = !!(val & 0x80); + new_phys_base = (ems->phys_base & 0xffe00000) | ((val & 0x7f) * EMS_PGSIZE); + + if ((old_enabled != new_enabled) || (old_phys_base != new_phys_base)) { + if (old_enabled && (old_enabled == new_enabled)) { + ems->enabled = 0; + ems_recalc(dev, ems); + } + + ems->enabled = !!(val & 0x80); + + if (old_phys_base != new_phys_base) + ems->phys_base = (ems->phys_base & 0xffe00000) | ((val & 0x7f) * EMS_PGSIZE); + + ems_recalc(dev, ems); + } break; default: break; @@ -454,6 +511,8 @@ ems_read(uint16_t port, void *priv) break; } + neat_log("Port: %04X, ret: %02X\n", port, ret); + #if NEAT_DEBUG > 1 neat_log("NEAT: ems_read(%04x) = %02x\n", port, ret); #endif @@ -462,20 +521,76 @@ ems_read(uint16_t port, void *priv) } static void -ems_update(neat_t *dev, int en) +ems_recalc_all(neat_t *dev) +{ + for (uint8_t i = 0; i < EMS_MAXPAGE; i++) + ems_recalc(dev, &(dev->ems[i])); +} + +static void +ems_update_virt_base(neat_t *dev) +{ + for (uint8_t i = 0; i < EMS_MAXPAGE; i++) + dev->ems[i].virt_base = dev->ems_frame + (i * EMS_PGSIZE); +} + +static void +ems_remove_handlers(neat_t *dev) { for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { + neat_log("Removing I/O handler at %04X-%04X\n", + dev->ems_base + (i * EMS_PGSIZE), dev->ems_base + (i * EMS_PGSIZE) + 1); + /* Clean up any previous I/O port handler. */ + io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2, + ems_read, NULL, NULL, ems_write, NULL, NULL, dev); + } +} + +static void +ems_set_handlers(neat_t *dev) +{ + for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { + neat_log("Setting up I/O handler at %04X-%04X\n", + dev->ems_base + (i * EMS_PGSIZE), dev->ems_base + (i * EMS_PGSIZE) + 1); /* Set up an I/O port handler. */ - io_handler(en, dev->ems_base + (i * EMS_PGSIZE), 2, - ems_read, NULL, NULL, ems_write, NULL, NULL, dev); - - if (en) - dev->ems[i].virt_base = dev->ems_frame + (i * EMS_PGSIZE); - - ems_recalc(dev, &(dev->ems[i])); + io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2, + ems_read, NULL, NULL, ems_write, NULL, NULL, dev); } - flushmmucache_nopc(); + ems_recalc_all(dev); +} + +static void +remap_update(neat_t *dev, uint8_t val) +{ + if (dev->regs[REG_RB7] & RB7_UMAREL) { + mem_remap_top_ex(0, (dev->remap_base >= 1024) ? dev->remap_base : 1024); + neat_log("0 kB at %08X\n", ((dev->remap_base >= 1024) ? dev->remap_base : 1024) << 10); + } + + if (val & RB7_EMSEN) + dev->remap_base = mem_size - dev->ems_size; + else + dev->remap_base = mem_size; + neat_log("Total contiguous memory now: %i kB\n", dev->remap_base); + + if (dev->remap_base >= 640) + mem_mapping_set_addr(&ram_low_mapping, 0x00000000, 0x000a0000); + else + mem_mapping_set_addr(&ram_low_mapping, 0x00000000, dev->remap_base << 10); + + if (dev->remap_base > 1024) + mem_mapping_set_addr(&ram_high_mapping, 0x00100000, (dev->remap_base << 10) - 0x00100000); + else + mem_mapping_disable(&ram_high_mapping); + + if (val & RB7_UMAREL) { + mem_remap_top_ex(384, (dev->remap_base >= 1024) ? dev->remap_base : 1024); + neat_log("384 kB at %08X\n", ((dev->remap_base >= 1024) ? dev->remap_base : 1024) << 10); + } + + /* Yes, this has to be done on every step because mem_remap_top_ex() reenables it. */ + mem_mapping_disable(&ram_mid_mapping); } static void @@ -590,20 +705,21 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RB7: val &= RB7_MASK; - *reg = val; + + if (xval & (RB7_EMSEN | RB7_UMAREL)) + remap_update(dev, val); + + dev->regs[REG_RB7] = val; + + if (xval & RB7_EMSEN) + ems_remove_handlers(dev); + + if ((xval & RB7_EMSEN) && (val & RB7_EMSEN)) + ems_set_handlers(dev); + #if NEAT_DEBUG > 1 neat_log("NEAT: RB7=%02x(%02x)\n", val, *reg); #endif - - if (xval & RB7_EMSEN) - ems_update(dev, !!(val & RB7_EMSEN)); - - if (xval & RB7_UMAREL) { - if (val & RB7_UMAREL) - mem_remap_top(384); - else - mem_remap_top(0); - } break; case REG_RB8: @@ -621,18 +737,20 @@ neat_write(uint16_t port, uint8_t val, void *priv) neat_log("NEAT: RB9=%02x(%02x)\n", val, *reg); #endif - ems_update(dev, 0); + ems_remove_handlers(dev); /* Get configured I/O address. */ - j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; - dev->ems_base = 0x0208 + (0x10 * j); + j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; + dev->ems_base = 0x0208 + (0x10 * j); /* Get configured frame address. */ j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; dev->ems_frame = 0xc0000 + (EMS_PGSIZE * j); + ems_update_virt_base(dev); + if (dev->regs[REG_RB7] & RB7_EMSEN) - ems_update(dev, 1); + ems_set_handlers(dev); break; case REG_RB10: @@ -642,18 +760,32 @@ neat_write(uint16_t port, uint8_t val, void *priv) neat_log("NEAT: RB10=%02x(%02x)\n", val, *reg); #endif - dev->ems[3].phys_base = (dev->ems[3].phys_base & 0x001fffff) | - (((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21); - dev->ems[2].phys_base = (dev->ems[2].phys_base & 0x001fffff) | - (((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21); - dev->ems[1].phys_base = (dev->ems[1].phys_base & 0x001fffff) | - (((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21); - dev->ems[0].phys_base = (dev->ems[0].phys_base & 0x001fffff) | - (((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21); + for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { + ram_page_t *ems = &(dev->ems[i]); + + uint32_t old_phys_base = ems->phys_base & 0xffe00000; + uint32_t new_phys_base = (((val & masks[i]) >> shifts[i]) << 21); - if (dev->regs[REG_RB7] & RB7_EMSEN) - for (i = 0; i < EMS_MAXPAGE; i++) - ems_recalc(dev, &dev->ems[i]); + if (new_phys_base != old_phys_base) { + int8_t old_enabled = ems->enabled; + + if ((dev->regs[REG_RB7] & RB7_EMSEN) && old_enabled) { + ems->enabled = 0; + ems_recalc(dev, &(dev->ems[i])); + } + + ems->phys_base = ems->phys_base - old_phys_base + new_phys_base; + + if ((dev->regs[REG_RB7] & RB7_EMSEN) && old_enabled) { + ems->enabled = old_enabled; + ems_recalc(dev, &(dev->ems[i])); + } + } + } + + neat_log("%08X, %08X, %08X, %08X\n", + dev->ems[0].phys_base, dev->ems[1].phys_base, + dev->ems[2].phys_base, dev->ems[3].phys_base); break; case REG_RB12: @@ -680,15 +812,12 @@ neat_write(uint16_t port, uint8_t val, void *priv) default: break; } - dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE; - - if (dev->regs[REG_RB7] & RB7_EMSEN) - for (i = 0; i < EMS_MAXPAGE; i++) - ems_recalc(dev, &dev->ems[i]); if (dev->regs[REG_RB7] & RB7_EMSEN) { - neat_log("NEAT: EMS %iKB (%i pages)\n", - dev->ems_size, dev->ems_pages); + remap_update(dev, dev->regs[REG_RB7]); + + neat_log("NEAT: EMS %iKB\n", + dev->ems_size); } mem_a20_key = val & RB12_GA20; @@ -756,12 +885,17 @@ neat_init(UNUSED(const device_t *info)) memset(dev, 0x00, sizeof(neat_t)); /* Get configured I/O address. */ - j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; - dev->ems_base = 0x0208 + (0x10 * j); + j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; + dev->ems_base = 0x0208 + (0x10 * j); /* Get configured frame address. */ - j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; - dev->ems_frame = 0xc0000 + (EMS_PGSIZE * j); + j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; + dev->ems_frame = 0xc0000 + (EMS_PGSIZE * j); + + ems_update_virt_base(dev); + + dev->ems_pages = (mem_size << 10) / EMS_PGSIZE; + dev->remap_base = mem_size; mem_mapping_disable(&ram_mid_mapping); @@ -773,10 +907,10 @@ neat_init(UNUSED(const device_t *info)) for (uint8_t i = 0; i < EMS_MAXPAGE; i++) { /* Create and initialize a page mapping. */ mem_mapping_add(&dev->ems[i].mapping, - dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE, + 0x00000000, 0x00000000, ems_readb, ems_readw, NULL, ems_writeb, ems_writew, NULL, - ram, MEM_MAPPING_INTERNAL, + ram + dev->ems[i].virt_base, MEM_MAPPING_INTERNAL, &(dev->ems[i])); /* Disable for now. */ From 0063a9f4039fac7dd8ee35820ed9228788c3f0b5 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 12:33:26 +0700 Subject: [PATCH 18/43] Name corrections to LG CRN-8245B --- src/include/86box/cdrom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index 3895833a6..008f0ddc4 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -151,7 +151,7 @@ static const struct { "HITACHI", "CDR-8130", "0020", "HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE }, { "HL-DT-ST", "GCE-8525B", "1.01", "HL-DT-ST GCE-8525B 1.01", "HL-DT-ST_GCE-8525B_1.01", BUS_TYPE_IDE }, { "KENWOOD", "CD-ROM UCR-421", "208E", "KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE }, - { "LG", "CRN-8245B", "1.20", "LG CRN-8245B 1.20", "LG_CRN-8245B_1.20", BUS_TYPE_IDE }, + { "LG", "CD-ROM CRN-8245B", "1.20", "LG CD-ROM CRN-8245B 1.20", "LG_CD-ROM_CRN-8245B_1.20", BUS_TYPE_IDE }, { "LITE-ON", "LTN48125S", "1S07", "LITE-ON LTN48125S 1S07", "LITE-ON_LTN48125S_1S07", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-585", "Z18P", "MATSHITA CD-ROM CR-585 Z18P", "MATSHITA_CD-ROM_CR-585_Z18P", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-587", "7S13", "MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE }, From 72571d6211877d5b5934f74d0ca540b757f2d852 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 14:26:31 +0700 Subject: [PATCH 19/43] Added other two models (1x DVD/1x CD) Also updated the revision on CRN-8245B --- src/include/86box/cdrom.h | 8 ++++++-- src/scsi/scsi_cdrom.c | 12 ++++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index 008f0ddc4..7acfa2cc3 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -72,9 +72,11 @@ enum CDROM_TYPE_GOLDSTAR_CRD_8160B_314, CDROM_TYPE_HITACHI_CDR_8130_0020, CDROM_TYPE_HLDTST_GCE8525B_101, + CDROM_TYPE_HLDTST_GSA4160_A302, CDROM_TYPE_KENWOOD_UCR_421_208E, - CDROM_TYPE_LG_CRN8245B_120, + CDROM_TYPE_LG_CRN8245B_130, CDROM_TYPE_LTN48125S_1S07, + CDROM_TYPE_LTN526D_YSR5, CDROM_TYPE_MATSHITA_585_Z18P, CDROM_TYPE_MATSHITA_587_7S13, CDROM_TYPE_MATSHITA_588_LS15, @@ -150,9 +152,11 @@ static const struct { "GOLDSTAR", "CRD-8160B", "3.14", "GOLDSTAR CRD-8160B 3.14", "GOLDSTAR_CRD-8160B_3.14", BUS_TYPE_IDE }, { "HITACHI", "CDR-8130", "0020", "HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE }, { "HL-DT-ST", "GCE-8525B", "1.01", "HL-DT-ST GCE-8525B 1.01", "HL-DT-ST_GCE-8525B_1.01", BUS_TYPE_IDE }, + { "HL-DT-ST", "DVDRAM GSA-4160", "A302", "HL-DT-ST DVDRAM GSA-4160 A302", "HL-DT-ST_DVDRAM_GSA-4160_A302", BUS_TYPE_IDE }, { "KENWOOD", "CD-ROM UCR-421", "208E", "KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE }, - { "LG", "CD-ROM CRN-8245B", "1.20", "LG CD-ROM CRN-8245B 1.20", "LG_CD-ROM_CRN-8245B_1.20", BUS_TYPE_IDE }, + { "LG", "CD-ROM CRN-8245B", "1.30", "LG CD-ROM CRN-8245B 1.30", "LG_CD-ROM_CRN-8245B_1.30", BUS_TYPE_IDE }, { "LITE-ON", "LTN48125S", "1S07", "LITE-ON LTN48125S 1S07", "LITE-ON_LTN48125S_1S07", BUS_TYPE_IDE }, + { "LITE-ON", "LTN526D", "YSR5", "LITE-ON LTN526D YSR5", "LITE-ON_LTN526D_YSR5", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-585", "Z18P", "MATSHITA CD-ROM CR-585 Z18P", "MATSHITA_CD-ROM_CR-585_Z18P", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-587", "7S13", "MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE }, { "MATSHITA", "CD-ROM CR-588", "LS15", "MATSHITA CD-ROM CR-588 LS15", "MATSHITA_CD-ROM_CR-588_LS15", BUS_TYPE_IDE }, diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index 9f8a86fc9..1eabc59f6 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -4065,18 +4065,26 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "1.01 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "HL-DT-ST GCE-8525B ", 40); /* Model */ break; + case CDROM_TYPE_HLDTST_GSA4160_A302: + ide_padstr((char *) (ide->buffer + 23), "A302 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "HL-DT-ST DVDRAM GSA-4160 ", 40); /* Model */ + break; case CDROM_TYPE_KENWOOD_UCR_421_208E: ide_padstr((char *) (ide->buffer + 23), "208E ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "KENWOOD CD-ROM UCR-421 ", 40); /* Model */ break; - case CDROM_TYPE_LG_CRN8245B_120: - ide_padstr((char *) (ide->buffer + 23), "1.20 ", 8); /* Firmware */ + case CDROM_TYPE_LG_CRN8245B_130: + ide_padstr((char *) (ide->buffer + 23), "1.30 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "LG CD-ROM CRN-8245B ", 40); /* Model */ break; case CDROM_TYPE_LTN48125S_1S07: ide_padstr((char *) (ide->buffer + 23), "1S07 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "LTN48125S ", 40); /* Model */ break; + case CDROM_TYPE_LTN526D_YSR5: + ide_padstr((char *) (ide->buffer + 23), "YSR5 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "LTN526D ", 40); /* Model */ + break; case CDROM_TYPE_MATSHITA_585_Z18P: ide_padstr((char *) (ide->buffer + 23), "Z18P ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "MATSHITA CD-ROM CR-585 ", 40); /* Model */ From 2a16c3cea657753ce1bc1d0ba0e6a2c0204adee4 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 16:42:13 +0700 Subject: [PATCH 20/43] Added other five models I have forgotten Also changed the HL-DT-ST CD-ROM to reflect the model revision. --- src/include/86box/cdrom.h | 84 ++++++++++++++++++++++----------------- src/scsi/scsi_cdrom.c | 24 ++++++++++- 2 files changed, 69 insertions(+), 39 deletions(-) diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index 7acfa2cc3..bd50604bb 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -71,12 +71,15 @@ enum CDROM_TYPE_BTC_BCD36XH_U10, CDROM_TYPE_GOLDSTAR_CRD_8160B_314, CDROM_TYPE_HITACHI_CDR_8130_0020, - CDROM_TYPE_HLDTST_GCE8525B_101, + CDROM_TYPE_HITACHI_GD7500_A1, + CDROM_TYPE_HLDTST_GCR8526B_101, CDROM_TYPE_HLDTST_GSA4160_A302, CDROM_TYPE_KENWOOD_UCR_421_208E, CDROM_TYPE_LG_CRN8245B_130, + CDROM_TYPE_LG_CRD8322B_106, CDROM_TYPE_LTN48125S_1S07, CDROM_TYPE_LTN526D_YSR5, + CDROM_TYPE_MATSHITA_583_107, CDROM_TYPE_MATSHITA_585_Z18P, CDROM_TYPE_MATSHITA_587_7S13, CDROM_TYPE_MATSHITA_588_LS15, @@ -98,6 +101,8 @@ enum CDROM_TYPE_TEAC_CD532E_20A, CDROM_TYPE_TOSHIBA_5302TA_0305, CDROM_TYPE_TOSHIBA_5702B_TA70, + CDROM_TYPE_TOSHIBA_6202B_1512, + CDROM_TYPE_TOSHIBA_6402B_1008, CDROM_TYPE_TOSHIBA_6702B_1007, CDROM_TYPE_TOSHIBA_M1802_1051, CDROM_TYPE_CHINON_CDS431_H42, @@ -144,42 +149,47 @@ static const struct const char *internal_name; const int bus_type; } cdrom_drive_types[] = { - { "86BOX", "CD-ROM", "1.00", "86BOX CD-ROM 1.00", "86BOX_CD-ROM_1.00", BUS_TYPE_BOTH }, - { "ASUS", "CD-S500/A", "1.41", "ASUS CD-S500/A 1.41", "ASUS_CD-S500A_1.41", BUS_TYPE_IDE }, - { "ASUS", "CD-S520/A4", "1.32", "ASUS CD-S520/A4 1.32", "ASUS_CD-S520A4_1.32", BUS_TYPE_IDE }, - { "AZT", "CDA46802I", "1.15", "AZT CDA46802I 1.15", "AZT_CDA46802I_1.15", BUS_TYPE_IDE }, - { "BTC", "CD-ROM BCD36XH", "U1.0", "BTC CD-ROM BCD36XH U1.0", "BTC_CD-ROM_BCD36XH_U1.0", BUS_TYPE_IDE }, - { "GOLDSTAR", "CRD-8160B", "3.14", "GOLDSTAR CRD-8160B 3.14", "GOLDSTAR_CRD-8160B_3.14", BUS_TYPE_IDE }, - { "HITACHI", "CDR-8130", "0020", "HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE }, - { "HL-DT-ST", "GCE-8525B", "1.01", "HL-DT-ST GCE-8525B 1.01", "HL-DT-ST_GCE-8525B_1.01", BUS_TYPE_IDE }, - { "HL-DT-ST", "DVDRAM GSA-4160", "A302", "HL-DT-ST DVDRAM GSA-4160 A302", "HL-DT-ST_DVDRAM_GSA-4160_A302", BUS_TYPE_IDE }, - { "KENWOOD", "CD-ROM UCR-421", "208E", "KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE }, - { "LG", "CD-ROM CRN-8245B", "1.30", "LG CD-ROM CRN-8245B 1.30", "LG_CD-ROM_CRN-8245B_1.30", BUS_TYPE_IDE }, - { "LITE-ON", "LTN48125S", "1S07", "LITE-ON LTN48125S 1S07", "LITE-ON_LTN48125S_1S07", BUS_TYPE_IDE }, - { "LITE-ON", "LTN526D", "YSR5", "LITE-ON LTN526D YSR5", "LITE-ON_LTN526D_YSR5", BUS_TYPE_IDE }, - { "MATSHITA", "CD-ROM CR-585", "Z18P", "MATSHITA CD-ROM CR-585 Z18P", "MATSHITA_CD-ROM_CR-585_Z18P", BUS_TYPE_IDE }, - { "MATSHITA", "CD-ROM CR-587", "7S13", "MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE }, - { "MATSHITA", "CD-ROM CR-588", "LS15", "MATSHITA CD-ROM CR-588 LS15", "MATSHITA_CD-ROM_CR-588_LS15", BUS_TYPE_IDE }, - { "MATSHITA", "CR-571", "1.0e", "MATSHITA CR-571 1.0e", "MATSHITA_CR-571_1.0e", BUS_TYPE_IDE }, - { "MATSHITA", "CR-572", "1.0j", "MATSHITA CR-572 1.0j", "MATSHITA_CR-572_1.0j", BUS_TYPE_IDE }, - { "MITSUMI", "CRMC-FX4820T", "D02A", "MITSUMI CRMC-FX4820T D02A", "MITSUMI_CRMC-FX4820T_D02A", BUS_TYPE_IDE }, - { "NEC", "CD-ROM DRIVE:260", "1.00", "NEC CD-ROM DRIVE:260 1.00", "NEC_CD-ROM_DRIVE260_1.00", BUS_TYPE_IDE }, - { "NEC", "CD-ROM DRIVE:260", "1.01", "NEC CD-ROM DRIVE:260 1.01", "NEC_CD-ROM_DRIVE260_1.01", BUS_TYPE_IDE }, - { "NEC", "CD-ROM DRIVE:273", "4.20", "NEC CD-ROM DRIVE:273 4.20", "NEC_CD-ROM_DRIVE273_4.20", BUS_TYPE_IDE }, - { "NEC", "CD-ROM DRIVE:280", "1.05", "NEC CD-ROM DRIVE:280 1.05", "NEC_CD-ROM_DRIVE280_1.05", BUS_TYPE_IDE }, - { "NEC", "CD-ROM DRIVE:280", "3.08", "NEC CD-ROM DRIVE:280 3.08", "NEC_CD-ROM_DRIVE280_3.08", BUS_TYPE_IDE }, - { "NEC", "CDR-1900A", "1.00", "NEC CDR-1900A 1.00", "NEC_CDR-1900A_1.00", BUS_TYPE_IDE }, - { "PHILIPS", "CD-ROM PCA403CD", "U31P", "PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE }, - { "SONY", "CD-ROM CDU76", "1.0i", "SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE }, - { "SONY", "CD-ROM CDU311", "3.0h", "SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE }, - { "SONY", "CD-ROM CDU5225", "NYS4", "SONY CD-ROM CDU5225 NYS4", "SONY_CD-ROM_CDU5225_NYS4", BUS_TYPE_IDE }, - { "TEAC", "CD-516E", "1.0G", "TEAC CD-516E 1.0G", "TEAC_CD-516E_1.0G", BUS_TYPE_IDE }, - { "TEAC", "CD-524EA", "3.0D", "TEAC CD-524EA 3.0D", "TEAC_CD-524EA_3.0D", BUS_TYPE_IDE }, - { "TEAC", "CD-532E", "2.0A", "TEAC CD-532E 2.0A", "TEAC_CD_532E_2.0A", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-6702B", "1007", "TOSHIBA CD-ROM XM-6702B 1007", "TOSHIBA_CD-ROM_XM-6702B_1007", BUS_TYPE_IDE }, - { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1051", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, + { "86BOX", "CD-ROM", "1.00", "86BOX CD-ROM 1.00", "86BOX_CD-ROM_1.00", BUS_TYPE_BOTH }, + { "ASUS", "CD-S500/A", "1.41", "ASUS CD-S500/A 1.41", "ASUS_CD-S500A_1.41", BUS_TYPE_IDE }, + { "ASUS", "CD-S520/A4", "1.32", "ASUS CD-S520/A4 1.32", "ASUS_CD-S520A4_1.32", BUS_TYPE_IDE }, + { "AZT", "CDA46802I", "1.15", "AZT CDA46802I 1.15", "AZT_CDA46802I_1.15", BUS_TYPE_IDE }, + { "BTC", "CD-ROM BCD36XH", "U1.0", "BTC CD-ROM BCD36XH U1.0", "BTC_CD-ROM_BCD36XH_U1.0", BUS_TYPE_IDE }, + { "GOLDSTAR", "CRD-8160B", "3.14", "GOLDSTAR CRD-8160B 3.14", "GOLDSTAR_CRD-8160B_3.14", BUS_TYPE_IDE }, + { "HITACHI", "CDR-8130", "0020", "HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE }, + { "HITACHI", "GD-7500", "A1 ", "HITACHI GD-7500 A1", "HITACHI_GD-7500_A1", BUS_TYPE_IDE }, + { "HL-DT-ST", "CD-ROM GCR-8526B", "1.01", "HL-DT-ST CD-ROM GCR-8526B 1.01", "HL-DT-ST_CD-ROM_GCR-8526B_1.01", BUS_TYPE_IDE }, + { "HL-DT-ST", "DVDRAM GSA-4160", "A302", "HL-DT-ST DVDRAM GSA-4160 A302", "HL-DT-ST_DVDRAM_GSA-4160_A302", BUS_TYPE_IDE }, + { "KENWOOD", "CD-ROM UCR-421", "208E", "KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE }, + { "LG", "CD-ROM CRN-8245B", "1.30", "LG CD-ROM CRN-8245B 1.30", "LG_CD-ROM_CRN-8245B_1.30", BUS_TYPE_IDE }, + { "LG", "CD-ROM CRD-8322B", "1.06", "LG CD-ROM CRD-8322B 1.06", "LG_CD-ROM_CRD-8322B_1.06", BUS_TYPE_IDE }, + { "LITE-ON", "LTN48125S", "1S07", "LITE-ON LTN48125S 1S07", "LITE-ON_LTN48125S_1S07", BUS_TYPE_IDE }, + { "LITE-ON", "LTN526D", "YSR5", "LITE-ON LTN526D YSR5", "LITE-ON_LTN526D_YSR5", BUS_TYPE_IDE }, + { "MATSHITA", "CD-ROM CR-583", "1.07", "MATSHITA CD-ROM CR-583 1.07", "MATSHITA_CD-ROM_CR-583_1.07", BUS_TYPE_IDE }, + { "MATSHITA", "CD-ROM CR-585", "Z18P", "MATSHITA CD-ROM CR-585 Z18P", "MATSHITA_CD-ROM_CR-585_Z18P", BUS_TYPE_IDE }, + { "MATSHITA", "CD-ROM CR-587", "7S13", "MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE }, + { "MATSHITA", "CD-ROM CR-588", "LS15", "MATSHITA CD-ROM CR-588 LS15", "MATSHITA_CD-ROM_CR-588_LS15", BUS_TYPE_IDE }, + { "MATSHITA", "CR-571", "1.0e", "MATSHITA CR-571 1.0e", "MATSHITA_CR-571_1.0e", BUS_TYPE_IDE }, + { "MATSHITA", "CR-572", "1.0j", "MATSHITA CR-572 1.0j", "MATSHITA_CR-572_1.0j", BUS_TYPE_IDE }, + { "MITSUMI", "CRMC-FX4820T", "D02A", "MITSUMI CRMC-FX4820T D02A", "MITSUMI_CRMC-FX4820T_D02A", BUS_TYPE_IDE }, + { "NEC", "CD-ROM DRIVE:260", "1.00", "NEC CD-ROM DRIVE:260 1.00", "NEC_CD-ROM_DRIVE260_1.00", BUS_TYPE_IDE }, + { "NEC", "CD-ROM DRIVE:260", "1.01", "NEC CD-ROM DRIVE:260 1.01", "NEC_CD-ROM_DRIVE260_1.01", BUS_TYPE_IDE }, + { "NEC", "CD-ROM DRIVE:273", "4.20", "NEC CD-ROM DRIVE:273 4.20", "NEC_CD-ROM_DRIVE273_4.20", BUS_TYPE_IDE }, + { "NEC", "CD-ROM DRIVE:280", "1.05", "NEC CD-ROM DRIVE:280 1.05", "NEC_CD-ROM_DRIVE280_1.05", BUS_TYPE_IDE }, + { "NEC", "CD-ROM DRIVE:280", "3.08", "NEC CD-ROM DRIVE:280 3.08", "NEC_CD-ROM_DRIVE280_3.08", BUS_TYPE_IDE }, + { "NEC", "CDR-1900A", "1.00", "NEC CDR-1900A 1.00", "NEC_CDR-1900A_1.00", BUS_TYPE_IDE }, + { "PHILIPS", "CD-ROM PCA403CD", "U31P", "PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE }, + { "SONY", "CD-ROM CDU76", "1.0i", "SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE }, + { "SONY", "CD-ROM CDU311", "3.0h", "SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE }, + { "SONY", "CD-ROM CDU5225", "NYS4", "SONY CD-ROM CDU5225 NYS4", "SONY_CD-ROM_CDU5225_NYS4", BUS_TYPE_IDE }, + { "TEAC", "CD-516E", "1.0G", "TEAC CD-516E 1.0G", "TEAC_CD-516E_1.0G", BUS_TYPE_IDE }, + { "TEAC", "CD-524EA", "3.0D", "TEAC CD-524EA 3.0D", "TEAC_CD-524EA_3.0D", BUS_TYPE_IDE }, + { "TEAC", "CD-532E", "2.0A", "TEAC CD-532E 2.0A", "TEAC_CD_532E_2.0A", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6202B", "1512", "TOSHIBA CD-ROM XM-6202B 1512", "TOSHIBA_CD-ROM_XM-6202B_1512", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6402B", "1008", "TOSHIBA CD-ROM XM-6402B 1008", "TOSHIBA_CD-ROM_XM-6402B_1008", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6702B", "1007", "TOSHIBA CD-ROM XM-6702B 1007", "TOSHIBA_CD-ROM_XM-6702B_1007", BUS_TYPE_IDE }, + { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1051", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, { "CHINON", "CD-ROM CDS-431", "H42 ", "[SCSI-1] CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI }, { "CHINON", "CD-ROM CDX-435", "M62 ", "[SCSI-1] CHINON CD-ROM CDX-435 M62", "CHINON_CD-ROM_CDX-435_M62", BUS_TYPE_SCSI }, { "DEC", "RRD45 (C) DEC", "0436", "[SCSI-1] DEC RRD45 0436", "DEC_RRD45_0436", BUS_TYPE_SCSI }, diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index 1eabc59f6..91773c62c 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -4061,9 +4061,13 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "0020 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "HITACHI CDR-8130 ", 40); /* Model */ break; - case CDROM_TYPE_HLDTST_GCE8525B_101: + case CDROM_TYPE_HITACHI_GD7500_A1: + ide_padstr((char *) (ide->buffer + 23), "A1 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "HITACHI GD-7500 ", 40); /* Model */ + break; + case CDROM_TYPE_HLDTST_GCR8526B_101: ide_padstr((char *) (ide->buffer + 23), "1.01 ", 8); /* Firmware */ - ide_padstr((char *) (ide->buffer + 27), "HL-DT-ST GCE-8525B ", 40); /* Model */ + ide_padstr((char *) (ide->buffer + 27), "HL-DT-ST CD-ROM GCR-8526B ", 40); /* Model */ break; case CDROM_TYPE_HLDTST_GSA4160_A302: ide_padstr((char *) (ide->buffer + 23), "A302 ", 8); /* Firmware */ @@ -4077,6 +4081,10 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "1.30 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "LG CD-ROM CRN-8245B ", 40); /* Model */ break; + case CDROM_TYPE_LG_CRD8322B_106: + ide_padstr((char *) (ide->buffer + 23), "1.06 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "LG CD-ROM CRD-8322B ", 40); /* Model */ + break; case CDROM_TYPE_LTN48125S_1S07: ide_padstr((char *) (ide->buffer + 23), "1S07 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "LTN48125S ", 40); /* Model */ @@ -4085,6 +4093,10 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "YSR5 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "LTN526D ", 40); /* Model */ break; + case CDROM_TYPE_MATSHITA_583_107: + ide_padstr((char *) (ide->buffer + 23), "1.07 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "MATSHITA CD-ROM CR-583 ", 40); /* Model */ + break; case CDROM_TYPE_MATSHITA_585_Z18P: ide_padstr((char *) (ide->buffer + 23), "Z18P ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "MATSHITA CD-ROM CR-585 ", 40); /* Model */ @@ -4169,6 +4181,14 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma) ide_padstr((char *) (ide->buffer + 23), "TA70 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-5702B ", 40); /* Model */ break; + case CDROM_TYPE_TOSHIBA_6202B_1512: + ide_padstr((char *) (ide->buffer + 23), "1512 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-6202B ", 40); /* Model */ + break; + case CDROM_TYPE_TOSHIBA_6402B_1008: + ide_padstr((char *) (ide->buffer + 23), "1008 ", 8); /* Firmware */ + ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-6402B ", 40); /* Model */ + break; case CDROM_TYPE_TOSHIBA_6702B_1007: ide_padstr((char *) (ide->buffer + 23), "1007 ", 8); /* Firmware */ ide_padstr((char *) (ide->buffer + 27), "TOSHIBA CD-ROM XM-6702B ", 40); /* Model */ From cd5ad1f6c145386d0f0a902307123d52da4752d7 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Wed, 15 Jan 2025 20:12:29 +0700 Subject: [PATCH 21/43] Added one recently-added ATA-1 HDD model --- src/disk/hdd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index 328d8dcb0..90d01bf9c 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -419,6 +419,7 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-1] Conner CP3024", .internal_name = "CP3024", .model = "Conner Peripherals 20MB - CP3024", .zones = 1, .avg_spt = 33, .heads = 2, .rpm = 3500, .full_stroke_ms = 50, .track_seek_ms = 8, .rcache_num_seg = 1, .rcache_seg_size = 8, .max_multiple = 8 }, // Needed for GRiDcase 1520 to work { .name = "[ATA-1] Conner CP3044", .internal_name = "CP3044", .model = "Conner Peripherals 40MB - CP3044", .zones = 1, .avg_spt = 40, .heads = 2, .rpm = 3500, .full_stroke_ms = 50, .track_seek_ms = 8, .rcache_num_seg = 1, .rcache_seg_size = 8, .max_multiple = 8 }, // Needed for GRiDcase 1520 to work { .name = "[ATA-1] Conner CP3104", .internal_name = "CP3104", .model = "Conner Peripherals 104MB - CP3104", .zones = 1, .avg_spt = 33, .heads = 8, .rpm = 3500, .full_stroke_ms = 45, .track_seek_ms = 8, .rcache_num_seg = 4, .rcache_seg_size = 8, .max_multiple = 8 }, // Needed for GRiDcase 1520 to work + { .name = "[ATA-1] Conner CFS420A", .internal_name = "CFS420A", .model = "Conner Peripherals 420MB - CFS420A", .zones = 1, .avg_spt = 140, .heads = 2, .rpm = 3600, .full_stroke_ms = 33, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 32, .max_multiple = 8 }, { .name = "[ATA-1] HP Kittyhawk", .internal_name = "C3014A", .model = "HP C3014A", .zones = 6, .avg_spt = 180, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 16, .max_multiple = 8 }, { .name = "[ATA-1] IBM H3256-A3", .internal_name = "H3256A3", .model = "IBM-H3256-A3", .zones = 1, .avg_spt = 140, .heads = 2, .rpm = 3600, .full_stroke_ms = 32, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 96, .max_multiple = 8 }, { .name = "[ATA-1] IBM H3342-A4", .internal_name = "H3342A4", .model = "IBM-H3342-A4", .zones = 1, .avg_spt = 140, .heads = 2, .rpm = 3600, .full_stroke_ms = 30, .track_seek_ms = 4, .rcache_num_seg = 4, .rcache_seg_size = 96, .max_multiple = 8 }, From 2f5940fee34ca0f77b390cb718d6669f1b7c0c32 Mon Sep 17 00:00:00 2001 From: greblosdier <51314920+greblosdier@users.noreply.github.com> Date: Wed, 15 Jan 2025 12:57:51 -0800 Subject: [PATCH 22/43] Update 386_dynarec.c Changed exec386_dynarec_dyn from inline to noinline to resolve NEW_DYNAREC build issue on Linux x86_64. --- src/cpu/386_dynarec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index 590d6f5c7..d86412103 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -386,7 +386,7 @@ block_ended: cpu_end_block_after_ins = 0; } -static __inline void +static void __attribute__((noinline)) exec386_dynarec_dyn(void) { uint32_t start_pc = 0; From a582223e41c68b7d3dc79e317e4ea528e8a35c44 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 00:58:53 +0100 Subject: [PATCH 23/43] NEAT: Actually properly initialize the shadow RAM mappings, fixes #5148. --- src/chipset/neat.c | 47 +++++++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/src/chipset/neat.c b/src/chipset/neat.c index 3b223bed4..057a9a246 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -345,23 +345,27 @@ neat_mem_update_state(neat_t *dev, uint32_t addr, uint32_t size, uint8_t new_fla new_flags = dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE]; - neat_log("neat_mem_update_state(): %08X-%08X: %02X\n", addr, addr + size - 1, new_flags); - - if (new_flags & RAM_FLAG_EMS) + if (new_flags & RAM_FLAG_EMS) { + neat_log("neat_mem_update_state(): %08X-%08X: %02X (EMS)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else if (new_flags & RAM_FLAG_ROMCS) + } else if (new_flags & RAM_FLAG_ROMCS) { + neat_log("neat_mem_update_state(): %08X-%08X: %02X (ROMCS)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_ROMCS | MEM_WRITE_ROMCS); - else switch (new_flags & (RAM_FLAG_SHREAD | RAM_FLAG_SHWRITE)) { + } else switch (new_flags & (RAM_FLAG_SHREAD | RAM_FLAG_SHWRITE)) { case 0: + neat_log("neat_mem_update_state(): %08X-%08X: %02X (RE | WE)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); break; case 1: + neat_log("neat_mem_update_state(): %08X-%08X: %02X (RE | WI)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL); break; case 2: + neat_log("neat_mem_update_state(): %08X-%08X: %02X (RI | WE)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); break; case 3: + neat_log("neat_mem_update_state(): %08X-%08X: %02X (RI | WI)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); break; default: @@ -383,14 +387,24 @@ shadow_recalc(neat_t *dev) int ram_flags; int read; - if (i > 16) { + if (i >= 16) { int rb1_romcs_bit = 7 - (i >> 2); int rb1_write_bit = rb1_romcs_bit + 4; romcs = !(dev->regs[REG_RB1] & (1 << rb1_romcs_bit)); write = !(dev->regs[REG_RB1] & (1 << rb1_write_bit)); - } else if (i <= 8) + neat_log("Shadow %08X-%08X: [%02X, %02X] %02X:%02X, %02X, %02X\n", + dev->shadow[i].virt_base, dev->shadow[i].virt_base + EMS_PGSIZE - 1, + dev->regs[REG_RB1], dev->regs[shadow_reg], + shadow_reg, shadow_bit, + rb1_romcs_bit, rb1_write_bit); + } else { shadow_bit ^= 4; + neat_log("Shadow %08X-%08X: [--, %02X] %02X:%02X, shadow bit ^= 4\n", + dev->shadow[i].virt_base, dev->shadow[i].virt_base + EMS_PGSIZE - 1, + dev->regs[shadow_reg], + shadow_reg, shadow_bit); + } read = dev->regs[shadow_reg] & (1 << shadow_bit); write = write && read; @@ -425,8 +439,7 @@ ems_recalc(neat_t *dev, ram_page_t *ems) /* Update the EMS RAM address for this page. */ mem_mapping_set_exec(&ems->mapping, ram + ems->phys_base); - if ((ems->virt_base >= 0x00080000) && (ems->virt_base < 0x00100000)) - neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, RAM_FLAG_EMS, RAM_FMASK_EMS); + neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, RAM_FLAG_EMS, RAM_FMASK_EMS); #if NEAT_DEBUG > 1 neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n", @@ -436,11 +449,8 @@ ems_recalc(neat_t *dev, ram_page_t *ems) /* Disable this page. */ mem_mapping_disable(&ems->mapping); - if ((ems->virt_base >= 0x00080000) && (ems->virt_base < 0x00100000)) - neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, 0x00, RAM_FMASK_EMS); + neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, 0x00, RAM_FMASK_EMS); } - - flushmmucache_nopc(); } static void @@ -921,6 +931,17 @@ neat_init(UNUSED(const device_t *info)) dev->shadow[i].virt_base = dev->shadow[i].phys_base = (i * EMS_PGSIZE) + 0x00080000; dev->shadow[i].enabled = 1; + + /* Create and initialize a page mapping. */ + mem_mapping_add(&dev->shadow[i].mapping, + dev->shadow[i].virt_base, EMS_PGSIZE, + ems_readb, ems_readw, NULL, + ems_writeb, ems_writew, NULL, + ram + dev->shadow[i].virt_base, MEM_MAPPING_INTERNAL, + &(dev->shadow[i])); + + /* Disable for now. */ + mem_mapping_disable(&dev->shadow[i].mapping); } /* Initialize some of the registers to specific defaults. */ From fbafb7507b22d0c5b265b29de37f7025ed74ec82 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 01:14:23 +0100 Subject: [PATCH 24/43] Dynamic recompiler: Only disable inline if not on Windows or MacOS. --- src/cpu/386_dynarec.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index d86412103..7ad4f30c5 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -386,7 +386,11 @@ block_ended: cpu_end_block_after_ins = 0; } +#if defined(_WIN32) || defined(__APPLE__) +static __inline void +#else static void __attribute__((noinline)) +#endif exec386_dynarec_dyn(void) { uint32_t start_pc = 0; From 48b3bbb7971827d7481b7a2c77f9ca6763f10cb9 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 03:34:38 +0100 Subject: [PATCH 25/43] NEAT: RA0-RA2 defaults and RA0 alt. reset. --- src/chipset/neat.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/chipset/neat.c b/src/chipset/neat.c index 057a9a246..3c9838e06 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -237,7 +237,7 @@ typedef struct neat_t { ram_page_t shadow[32]; /* Shadow RAM pages */ } neat_t; -static uint8_t defaults[16] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, +static uint8_t defaults[16] = { 0x0a, 0x45, 0xfc, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x63, 0x10, 0x00, 0x00, 0x12 }; static uint8_t masks[4] = { RB10_P0EXT, RB10_P1EXT, RB10_P2EXT, RB10_P3EXT }; @@ -628,6 +628,8 @@ neat_write(uint16_t port, uint8_t val, void *priv) case REG_RA0: val &= RA0_MASK; *reg = (*reg & ~RA0_MASK) | val | (RA0_REV_ID << RA0_REV_SH); + if ((xval & 0x20) && (val & 0x20)) + outb(0x64, 0xfe); #if NEAT_DEBUG > 1 neat_log("NEAT: RA0=%02x(%02x)\n", val, *reg); #endif From a94a5bb0b54e20294fbaaec6b667843dc30ecb6e Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 05:48:37 +0100 Subject: [PATCH 26/43] Improved the Linux new dynamic recompiler freeze workaround per patch by Dax. --- src/cpu/386_dynarec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index 7ad4f30c5..5991cf100 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -386,10 +386,10 @@ block_ended: cpu_end_block_after_ins = 0; } -#if defined(_WIN32) || defined(__APPLE__) -static __inline void +#if defined(__linux__) && !defined(__clang__) && defined(USE_NEW_DYNAREC) +static inline void __attribute__((optimize("O2"))) #else -static void __attribute__((noinline)) +static __inline void #endif exec386_dynarec_dyn(void) { From d8eb77849ca146965e05da889855b02ed6f523bd Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 5 May 2024 23:27:31 -0400 Subject: [PATCH 27/43] Corrections to the SixPakPlus --- src/device/isamem.c | 2 +- src/device/isartc.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/device/isamem.c b/src/device/isamem.c index 83e938abd..f63a5a5a1 100644 --- a/src/device/isamem.c +++ b/src/device/isamem.c @@ -1310,7 +1310,7 @@ static const device_config_t a6pak_config[] = { .file_filter = "", .spinner = { .min = 0, - .max = 576, + .max = 384, .step = 64 }, .selection = { { 0 } } diff --git a/src/device/isartc.c b/src/device/isartc.c index 7721d9885..b56718400 100644 --- a/src/device/isartc.c +++ b/src/device/isartc.c @@ -714,8 +714,9 @@ static const device_config_t a6pak_config[] = { { { "Disabled", -1 }, { "IRQ2", 2 }, - { "IRQ3", 3 }, + { "IRQ4", 4 }, { "IRQ5", 5 }, + { "IRQ7", 7 }, { "" } }, }, From 3f3b921831cf689b532f93d7ef51b5e32f37ec2f Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Mon, 6 May 2024 06:40:57 -0400 Subject: [PATCH 28/43] Add Generic MM58167 RTC --- src/device/isartc.c | 122 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 111 insertions(+), 11 deletions(-) diff --git a/src/device/isartc.c b/src/device/isartc.c index b56718400..61b07dc1a 100644 --- a/src/device/isartc.c +++ b/src/device/isartc.c @@ -76,17 +76,23 @@ #include <86box/machine.h> #include <86box/io.h> #include <86box/device.h> +#include <86box/mem.h> #include <86box/nvr.h> +#include <86box/rom.h> #include <86box/ui.h> #include <86box/plat.h> #include <86box/pic.h> #include <86box/isartc.h> -#define ISARTC_EV170 0 -#define ISARTC_DTK 1 -#define ISARTC_P5PAK 2 -#define ISARTC_A6PAK 3 -#define ISARTC_VENDEX 4 +#define ISARTC_EV170 0 +#define ISARTC_DTK 1 +#define ISARTC_P5PAK 2 +#define ISARTC_A6PAK 3 +#define ISARTC_VENDEX 4 +#define ISARTC_MM58167 10 + +#define ISARTC_ROM_MM58167_1 "roms/rtc/glatick/GLaTICK_0.8.5_NS_RP.ROM" +#define ISARTC_ROM_MM58167_2 "roms/rtc/glatick/GLaTICK_0.8.5_86B.ROM" #define ISARTC_DEBUG 0 @@ -101,6 +107,7 @@ typedef struct rtcdev_t { int8_t irq; /* configured IRQ channel */ int8_t base_addrsz; uint32_t base_addr; /* configured I/O address */ + rom_t rom; /* BIOS ROM, If configured */ /* Fields for the specific driver. */ void (*f_wr)(uint16_t, uint8_t, void *); @@ -524,6 +531,14 @@ isartc_init(const device_t *info) /* Do per-board initialization. */ switch (dev->board) { + case ISARTC_MM58167: /* Generic MM58167 RTC */ + { + int rom_addr = device_get_config_hex20("bios_addr"); + if (rom_addr != -1) + rom_init(&dev->rom, ISARTC_ROM_MM58167_1, + rom_addr, 0x0800, 0x7ff, 0, MEM_MAPPING_EXTERNAL); + + } case ISARTC_EV170: /* Everex EV-170 Magic I/O */ dev->flags |= FLAG_YEAR80; dev->base_addr = device_get_config_hex16("base"); @@ -738,6 +753,90 @@ static const device_t a6pak_device = { .config = a6pak_config }; +static const device_config_t mm58167_config[] = { + // clang-format off + { + .name = "base", + .description = "Address", + .type = CONFIG_HEX16, + .default_string = "", + .default_int = 0x02C0, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { "240H", 0x0240 }, + { "2C0H", 0x02c0 }, + { "340H", 0x0340 }, + { "" } + }, + }, + { + .name = "irq", + .description = "IRQ", + .type = CONFIG_SELECTION, + .default_string = "", + .default_int = -1, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { "Disabled", -1 }, + { "IRQ2", 2 }, + { "IRQ5", 5 }, + { "IRQ7", 7 }, + { "" } + }, + }, + { + .name = "bios_addr", + .description = "BIOS Address", + .type = CONFIG_HEX20, + .default_string = "", + .default_int = 0xcc000, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { .description = "Disabled", .value = -1 }, + { .description = "C800H", .value = 0xc8000 }, + { .description = "CA00H", .value = 0xca000 }, + { .description = "CC00H", .value = 0xcc000 }, + { .description = "CE00H", .value = 0xce000 }, + { .description = "D000H", .value = 0xd0000 }, + { .description = "D200H", .value = 0xd2000 }, + { .description = "D400H", .value = 0xd4000 }, + { .description = "D600H", .value = 0xd6000 }, + { .description = "D800H", .value = 0xd8000 }, + { .description = "DA00H", .value = 0xda000 }, + { .description = "DC00H", .value = 0xdc000 }, + { .description = "DE00H", .value = 0xde000 }, + { .description = "E000H", .value = 0xe0000 }, + { .description = "E200H", .value = 0xe2000 }, + { .description = "E400H", .value = 0xe4000 }, + { .description = "E600H", .value = 0xe6000 }, + { .description = "E800H", .value = 0xe8000 }, + { .description = "EA00H", .value = 0xea000 }, + { .description = "EC00H", .value = 0xec000 }, + { .description = "EE00H", .value = 0xee000 }, + { .description = "" } + }, + }, + { .name = "", .description = "", .type = CONFIG_END } + // clang-format on +}; + +static const device_t mm58167_device = { + .name = "Generic MM58167 RTC", + .internal_name = "rtc_mm58167", + .flags = DEVICE_ISA, + .local = ISARTC_MM58167, + .init = isartc_init, + .close = isartc_close, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = mm58167_config +}; + /* Onboard RTC devices */ const device_t vendex_xt_rtc_onboard_device = { .name = "National Semiconductor MM58167 (Vendex)", @@ -757,12 +856,13 @@ static const struct { const device_t *dev; } boards[] = { // clang-format off - { &device_none }, - { &ev170_device }, - { &pii147_device }, - { &p5pak_device }, - { &a6pak_device }, - { NULL }, + { &device_none }, + { &ev170_device }, + { &pii147_device }, + { &p5pak_device }, + { &a6pak_device }, + { &mm58167_device }, + { NULL } // clang-format on }; From 3189bf7fb8eea58c3654b8875d3378e5e1ae8169 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Mon, 13 Jan 2025 22:06:59 -0500 Subject: [PATCH 29/43] Cleanups in isartc --- src/device/isartc.c | 111 ++++++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 41 deletions(-) diff --git a/src/device/isartc.c b/src/device/isartc.c index 61b07dc1a..77f35ffc7 100644 --- a/src/device/isartc.c +++ b/src/device/isartc.c @@ -629,24 +629,36 @@ isartc_close(void *priv) static const device_config_t ev170_config[] = { // clang-format off { - "base", "Address", CONFIG_HEX16, "", 0x02C0, "", { 0 }, - { - { "240H", 0x0240 }, - { "2C0H", 0x02c0 }, - { "" } + .name = "base", + .description = "Address", + .type = CONFIG_HEX16, + .default_string = "", + .default_int = 0x02C0, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { .description = "240H", .value = 0x0240 }, + { .description = "2C0H", .value = 0x02c0 }, + { .description = "" } }, }, { - "irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 }, - { - { "Disabled", -1 }, - { "IRQ2", 2 }, - { "IRQ5", 5 }, - { "IRQ7", 7 }, - { "" } + .name = "irq", + .description = "IRQ", + .type = CONFIG_SELECTION, + .default_string = "", + .default_int = -1, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { .description = "Disabled", .value = -1 }, + { .description = "IRQ2", .value = 2 }, + { .description = "IRQ5", .value = 5 }, + { .description = "IRQ7", .value = 7 }, + { .description = "" } }, }, - { "", "", -1 } + { .name = "", .description = "", .type = CONFIG_END } // clang-format on }; @@ -658,7 +670,7 @@ static const device_t ev170_device = { .init = isartc_init, .close = isartc_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = ev170_config @@ -667,14 +679,20 @@ static const device_t ev170_device = { static const device_config_t pii147_config[] = { // clang-format off { - "base", "Address", CONFIG_HEX16, "", 0x0240, "", { 0 }, - { - { "Clock 1", 0x0240 }, - { "Clock 2", 0x0340 }, - { "" } + .name = "base", + .description = "Address", + .type = CONFIG_HEX16, + .default_string = "", + .default_int = 0x0240, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { .description = "Clock 1", .value = 0x0240 }, + { .description = "Clock 2", .value = 0x0340 }, + { .description = "" } }, }, - { "", "", -1 } + { .name = "", .description = "", .type = CONFIG_END } // clang-format on }; @@ -686,7 +704,7 @@ static const device_t pii147_device = { .init = isartc_init, .close = isartc_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = pii147_config @@ -695,16 +713,22 @@ static const device_t pii147_device = { static const device_config_t p5pak_config[] = { // clang-format off { - "irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 }, - { - { "Disabled", -1 }, - { "IRQ2", 2 }, - { "IRQ3", 3 }, - { "IRQ5", 5 }, - { "" } + .name = "irq", + .description = "IRQ", + .type = CONFIG_SELECTION, + .default_string = "", + .default_int = -1, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { .description = "Disabled", -1 }, + { .description = "IRQ2", 2 }, + { .description = "IRQ3", 3 }, + { .description = "IRQ5", 5 }, + { .description = "" } }, }, - { "", "", -1 } + { .name = "", .description = "", .type = CONFIG_END } // clang-format on }; @@ -716,7 +740,7 @@ static const device_t p5pak_device = { .init = isartc_init, .close = isartc_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = p5pak_config @@ -725,17 +749,22 @@ static const device_t p5pak_device = { static const device_config_t a6pak_config[] = { // clang-format off { - "irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 }, - { - { "Disabled", -1 }, - { "IRQ2", 2 }, - { "IRQ4", 4 }, - { "IRQ5", 5 }, - { "IRQ7", 7 }, - { "" } + .name = "irq", + .description = "IRQ", + .type = CONFIG_SELECTION, + .default_string = "", + .default_int = -1, + .file_filter = "", + .spinner = { 0 }, + .selection = { + { .description = "Disabled", .value = -1 }, + { .description = "IRQ2", .value = 2 }, + { .description = "IRQ3", .value = 3 }, + { .description = "IRQ5", .value = 5 }, + { .description = "" } }, }, - { "", "", -1 } + { .name = "", .description = "", .type = CONFIG_END } // clang-format on }; @@ -747,7 +776,7 @@ static const device_t a6pak_device = { .init = isartc_init, .close = isartc_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = a6pak_config @@ -846,7 +875,7 @@ const device_t vendex_xt_rtc_onboard_device = { .init = isartc_init, .close = isartc_close, .reset = NULL, - { .available = NULL }, + .available = NULL, .speed_changed = NULL, .force_redraw = NULL, .config = NULL From b61751a6d0944482dfe2526a2538d0d40f6416ff Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Wed, 15 Jan 2025 23:45:00 -0500 Subject: [PATCH 30/43] CONFIG_BIOS for ibmat (5170) --- src/machine/m_at.c | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/src/machine/m_at.c b/src/machine/m_at.c index fea87c8f6..93d111510 100644 --- a/src/machine/m_at.c +++ b/src/machine/m_at.c @@ -153,6 +153,29 @@ machine_at_ps2_ide_init(const machine_t *model) static const device_config_t ibmat_config[] = { // clang-format off + { + .name = "bios", + .description = "BIOS Version", + .type = CONFIG_BIOS, + .default_string = "ibm5170_111585", + .default_int = 0, + .file_filter = "", + .spinner = { 0 }, + .bios = { + { .name = "62X082x (11/15/85)", .internal_name = "ibm5170_111585", .bios_type = BIOS_NORMAL, + .files_no = 2, .local = 0, .size = 65536, .files = { "roms/machines/ibmat/BIOS_5170_15NOV85_U27.BIN", "roms/machines/ibmat/BIOS_5170_15NOV85_U47.BIN", "" } }, + + { .name = "61X9266 (11/15/85) (Alt)", .internal_name = "ibm5170_111585_alt", .bios_type = BIOS_NORMAL, + .files_no = 2, .local = 0, .size = 65536, .files = { "roms/machines/ibmat/BIOS_5170_15NOV85_U27_61X9266.BIN", "roms/machines/ibmat/BIOS_5170_15NOV85_U47_61X9265.BIN", "" } }, + + { .name = "648009x (06/10/85)", .internal_name = "ibm5170_061085", .bios_type = BIOS_NORMAL, + .files_no = 2, .local = 0, .size = 65536, .files = { "roms/machines/ibmat/BIOS_5170_10JUN85_U27.BIN", "roms/machines/ibmat/BIOS_5170_10JUN85_U47.BIN", "" } }, + + { .name = "618102x (01/10/84)", .internal_name = "ibm5170_011084", .bios_type = BIOS_NORMAL, + .files_no = 2, .local = 0, .size = 65536, .files = { "roms/machines/ibmat/BIOS_5170_10JAN84_U27.BIN", "roms/machines/ibmat/BIOS_5170_10JAN84_U47.BIN", "" } }, + { .files_no = 0 } + }, + }, { .name = "enable_5161", .description = "IBM 5161 Expansion Unit", @@ -180,17 +203,21 @@ const device_t ibmat_device = { int machine_at_ibm_init(const machine_t *model) { - int ret; - uint8_t enable_5161; + int ret; + uint8_t enable_5161; + const char *fn[2]; + + /* No ROMs available. */ + if (!device_available(model->device)) + return ret; device_context(model->device); enable_5161 = machine_get_config_int("enable_5161"); + fn[0] = device_get_bios_file(model->device, device_get_config_bios("bios"), 0); + fn[1] = device_get_bios_file(model->device, device_get_config_bios("bios"), 1); + ret = bios_load_interleaved(fn[0], fn[1], 0x000f0000, 65536, 0); device_context_restore(); - ret = bios_load_interleaved("roms/machines/ibmat/62x0820.u27", - "roms/machines/ibmat/62x0821.u47", - 0x000f0000, 65536, 0); - if (bios_only || !ret) return ret; From 2eb65625f93338ce3da36cc2b90f6d80c54013c8 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Thu, 16 Jan 2025 00:36:23 -0500 Subject: [PATCH 31/43] GlaBIOS for 5150/5160 --- src/machine/m_xt.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/machine/m_xt.c b/src/machine/m_xt.c index 7b59686d6..2988ec201 100644 --- a/src/machine/m_xt.c +++ b/src/machine/m_xt.c @@ -74,6 +74,13 @@ static const device_config_t ibmpc_config[] = { .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/ibmpc/BIOS_IBM5150_19OCT81_5700671_U33.BIN", "" } }, { .name = "5700051 (04/24/81)", .internal_name = "ibm5150_5700051", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/ibmpc/BIOS_IBM5150_24APR81_5700051_U33.BIN", "" } }, + + // GlaBIOS for IBM PC + { .name = "GlaBIOS 0.2.5 (8088)", .internal_name = "glabios_025_8088", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_8P.ROM", "" } }, + { .name = "GlaBIOS 0.2.5 (V20)", .internal_name = "glabios_025_v20", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_VP.ROM", "" } }, + // The following are Diagnostic ROMs. { .name = "Supersoft Diagnostics", .internal_name = "diag_supersoft", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/diagnostic/Supersoft_PCXT_8KB.bin", "" } }, @@ -177,6 +184,13 @@ static const device_config_t ibmpc82_config[] = { .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/ibmpc82/BIOS_5150_27OCT82_1501476_U33.BIN", "" } }, { .name = "5000024 (08/16/82)", .internal_name = "ibm5150_5000024", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/ibmpc82/BIOS_5150_16AUG82_5000024_U33.BIN", "" } }, + + // GlaBIOS for IBM PC + { .name = "GlaBIOS 0.2.5 (8088)", .internal_name = "glabios_025_8088", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_8P.ROM", "" } }, + { .name = "GlaBIOS 0.2.5 (V20)", .internal_name = "glabios_025_v20", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_VP.ROM", "" } }, + // The following are Diagnostic ROMs. { .name = "Supersoft Diagnostics", .internal_name = "diag_supersoft", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/diagnostic/Supersoft_PCXT_8KB.bin", "" } }, @@ -283,6 +297,12 @@ static const device_config_t ibmxt_config[] = { { .name = "5000026 (08/16/82)", .internal_name = "ibm5160_5000026_5000027", .bios_type = BIOS_NORMAL, .files_no = 2, .local = 0, .size = 65536, .files = { "roms/machines/ibmxt/BIOS_5160_16AUG82_U18_5000026.BIN", "roms/machines/ibmxt/BIOS_5160_16AUG82_U19_5000027.BIN", "" } }, #if 0 + // GlaBIOS for IBM XT + { .name = "GlaBIOS 0.2.5 (8088)", .internal_name = "glabios_025_8088", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_8X.ROM", "" } }, + { .name = "GlaBIOS 0.2.5 (V20)", .internal_name = "glabios_025_v20", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_VX.ROM", "" } }, + // The following are Diagnostic ROMs. { .name = "Supersoft Diagnostics", .internal_name = "diag_supersoft", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 65536, .files = { "roms/machines/diagnostic/Supersoft_PCXT_8KB.bin", "" } }, @@ -399,6 +419,12 @@ static const device_config_t ibmxt86_config[] = { { .name = "1501512 (01/10/86) (Alt)", .internal_name = "ibm5160_011086_alt", .bios_type = BIOS_NORMAL, .files_no = 2, .local = 0, .size = 65536, .files = { "roms/machines/ibmxt86/BIOS_5160_10JAN86_U18_62X0852_27256_F800.BIN", "roms/machines/ibmxt86/BIOS_5160_10JAN86_U19_62X0853_27256_F000.BIN", "" } }, #if 0 + // GlaBIOS for IBM XT + { .name = "GlaBIOS 0.2.5 (8088)", .internal_name = "glabios_025_8088", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_8X.ROM", "" } }, + { .name = "GlaBIOS 0.2.5 (V20)", .internal_name = "glabios_025_v20", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 40960, .files = { "roms/machines/glabios/GLABIOS_0.2.5_VX.ROM", "" } }, + // The following are Diagnostic ROMs. { .name = "Supersoft Diagnostics", .internal_name = "diag_supersoft", .bios_type = BIOS_NORMAL, .files_no = 1, .local = 0, .size = 65536, .files = { "roms/machines/diagnostic/Supersoft_PCXT_8KB.bin", "" } }, From 43cf6e0b51b537ef708f531edb2b2de340f7154f Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Thu, 16 Jan 2025 13:07:23 +0700 Subject: [PATCH 32/43] Added 9 more ATA-4/ATA-5 HDD models -Small corrections to ATA-4 Western Digital HDD models -Line fixes to cdrom.h --- src/disk/hdd.c | 27 ++++++++++++++++++--------- src/include/86box/cdrom.h | 12 ++++++------ 2 files changed, 24 insertions(+), 15 deletions(-) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index 90d01bf9c..6872c7ae1 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -507,30 +507,39 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-4] Seagate Medalist 3321", .internal_name = "ST33221A", .model = "ST33221A", .zones = 16, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1.7, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Seagate Medalist 4321", .internal_name = "ST34321A", .model = "ST34321A", .zones = 16, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2.2, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-4] Seagate Medalist 6531", .internal_name = "ST36531A", .model = "ST36531A", .zones = 16, .avg_spt = 115, .heads = 6, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1.7, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 16 }, - { .name = "[ATA-4] Seagate Medalist 8420", .internal_name = "ST38420A", .model = "ST38420A", .zones = 16, .avg_spt = 90, .heads = 2, .rpm = 5400, .full_stroke_ms = 16, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-4] Seagate Medalist 8420", .internal_name = "ST38420A", .model = "ST38420A", .zones = 16, .avg_spt = 90, .heads = 4, .rpm = 5400, .full_stroke_ms = 16, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-4] Seagate Medalist 13030", .internal_name = "ST313030A", .model = "ST313030A", .zones = 16, .avg_spt = 90, .heads = 6, .rpm = 5400, .full_stroke_ms = 16, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-4] Seagate Medalist 17240", .internal_name = "ST317240A", .model = "ST317240A", .zones = 16, .avg_spt = 90, .heads = 8, .rpm = 5400, .full_stroke_ms = 16, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-4] Toshiba MK4006MAV", .internal_name = "MK4006MAV", .model = "TOSHIBA MK4006MAV", .zones = 8, .avg_spt = 130, .heads = 6, .rpm = 4200, .full_stroke_ms = 25, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 32 }, - { .name = "[ATA-4] Western Digital Caviar 14300", .internal_name = "AC14300", .model = "WDC AC14300-00RT", .zones = 16, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 5.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-4] Western Digital Caviar 23200", .internal_name = "AC23200", .model = "WDC AC23200-00LB", .zones = 16, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 256, .max_multiple = 32 }, - { .name = "[ATA-4] Western Digital Caviar 26400", .internal_name = "AC26400", .model = "WDC AC26400-00RN", .zones = 16, .avg_spt = 95, .heads = 5, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 32 }, - { .name = "[ATA-4] Western Digital Caviar 33200", .internal_name = "AC33200", .model = "WDC AC33200-00LA", .zones = 16, .avg_spt = 110, .heads = 5, .rpm = 5200, .full_stroke_ms = 40, .track_seek_ms = 3, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, + { .name = "[ATA-4] Western Digital Caviar 14300", .internal_name = "AC14300", .model = "WDC AC14300RT", .zones = 16, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 5.5, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-4] Western Digital Caviar 23200", .internal_name = "AC23200", .model = "WDC AC23200LB", .zones = 16, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 256, .max_multiple = 32 }, + { .name = "[ATA-4] Western Digital Caviar 26400", .internal_name = "AC26400", .model = "WDC AC26400RN", .zones = 16, .avg_spt = 95, .heads = 5, .rpm = 5400, .full_stroke_ms = 21, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-4] Western Digital Caviar 33200", .internal_name = "AC33200", .model = "WDC AC33200LA", .zones = 16, .avg_spt = 110, .heads = 5, .rpm = 5200, .full_stroke_ms = 40, .track_seek_ms = 3, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, { .name = "[ATA-5] IBM Travelstar 6GN", .internal_name = "DARA206000", .model = "IBM-DARA-206000", .zones = 12, .avg_spt = 92, .heads = 2, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] IBM Travelstar 9GN", .internal_name = "DARA209000", .model = "IBM-DARA-209000", .zones = 12, .avg_spt = 92, .heads = 3, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] IBM/Hitachi Travelstar 12GN", .internal_name = "DARA212000", .model = "IBM-DARA-212000", .zones = 12, .avg_spt = 92, .heads = 4, .rpm = 4200, .full_stroke_ms = 31, .track_seek_ms = 4, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, // Either Hitachi or IBM OEM { .name = "[ATA-5] Maxtor DiamondMax VL 17", .internal_name = "90871U2", .model = "Maxtor 90871U2", .zones = 16, .avg_spt = 90, .heads = 3, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 0.9, .rcache_num_seg = 16, .rcache_seg_size = 256, .max_multiple = 32 }, - { .name = "[ATA-5] Maxtor DiamondMax VL 20", .internal_name = "91021U2", .model = "Maxtor 91021U2", .zones = 16, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Maxtor DiamondMax VL 20 (91021U2)", .internal_name = "91021U2", .model = "Maxtor 91021U2", .zones = 16, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Maxtor DiamondMax VL 20 (91531U3)", .internal_name = "91531U3", .model = "Maxtor 91531U3", .zones = 16, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Maxtor DiamondMax VL 20 (92041U4)", .internal_name = "92041U4", .model = "Maxtor 92041U4", .zones = 16, .avg_spt = 95, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 1, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Quantum Fireball EX3.2A", .internal_name = "EX32A012", .model = "QUANTUM FIREBALL EX3.2A", .zones = 1, .avg_spt = 110, .heads = 2, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball EX5.1A", .internal_name = "EX51A012", .model = "QUANTUM FIREBALL EX5.1A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball EX6.4A", .internal_name = "EX64A012", .model = "QUANTUM FIREBALL EX6.4A", .zones = 2, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball EX10.2A", .internal_name = "EX10A011", .model = "QUANTUM FIREBALL EX10.2A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball EX12.7A", .internal_name = "EX12A011", .model = "QUANTUM FIREBALL EX12.7A", .zones = 4, .avg_spt = 110, .heads = 8, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-5] Quantum Fireball CR4.3A", .internal_name = "CR43A013", .model = "QUANTUM FIREBALL CR4.3A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-5] Quantum Fireball CR6.4A", .internal_name = "CR64A011", .model = "QUANTUM FIREBALL CR6.4A", .zones = 2, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, - { .name = "[ATA-5] Quantum Fireball CR8.4A", .internal_name = "CR84A011", .model = "QUANTUM FIREBALL CR8.4A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR4.3A", .internal_name = "CR43A013", .model = "QUANTUM FIREBALL CR4.3A", .zones = 2, .avg_spt = 110, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR6.4A", .internal_name = "CR64A011", .model = "QUANTUM FIREBALL CR6.4A", .zones = 2, .avg_spt = 110, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, + { .name = "[ATA-5] Quantum Fireball CR8.4A", .internal_name = "CR84A011", .model = "QUANTUM FIREBALL CR8.4A", .zones = 3, .avg_spt = 110, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Quantum Fireball CR13.0A", .internal_name = "CR13A011", .model = "QUANTUM FIREBALL CR13.0A", .zones = 4, .avg_spt = 110, .heads = 8, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 512, .max_multiple = 16 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV0682D)", .internal_name = "SV0682D", .model = "SAMSUNG SV0682D", .zones = 8, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1023D)", .internal_name = "SV1023D", .model = "SAMSUNG SV1023D", .zones = 8, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1364D)", .internal_name = "SV1364D", .model = "SAMSUNG SV1364D", .zones = 8, .avg_spt = 95, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1705D)", .internal_name = "SV1705D", .model = "SAMSUNG SV1705D", .zones = 8, .avg_spt = 95, .heads = 5, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Samsung SpinPoint V6800 (SV2046D)", .internal_name = "SV2046D", .model = "SAMSUNG SV1023D", .zones = 8, .avg_spt = 95, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 4.3gb", .internal_name = "ST34313A", .model = "ST34313A", .zones = 16, .avg_spt = 89, .heads = 1, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 8.4gb", .internal_name = "ST38410A", .model = "ST38410A", .zones = 16, .avg_spt = 89, .heads = 2, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Seagate U8 - 13gb", .internal_name = "ST313021A", .model = "ST313021A", .zones = 16, .avg_spt = 89, .heads = 4, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Seagate U8 - 17.2gb", .internal_name = "ST317221A", .model = "ST317221A", .zones = 16, .avg_spt = 89, .heads = 3, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Western Digital Caviar 102AA", .internal_name = "WD102AA", .model = "WDC WD102AA-00ANA0", .zones = 16, .avg_spt = 95, .heads = 8, .rpm = 5400, .full_stroke_ms = 12, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Western Digital Expert", .internal_name = "WD135BA", .model = "WDC WD135BA-60AK", .zones = 16, .avg_spt = 350, .heads = 6, .rpm = 7200, .full_stroke_ms = 15, .track_seek_ms = 2, .rcache_num_seg = 16, .rcache_seg_size = 1920, .max_multiple = 32 }, // clang-format on diff --git a/src/include/86box/cdrom.h b/src/include/86box/cdrom.h index bd50604bb..f28bba517 100644 --- a/src/include/86box/cdrom.h +++ b/src/include/86box/cdrom.h @@ -184,12 +184,12 @@ static const struct { "TEAC", "CD-516E", "1.0G", "TEAC CD-516E 1.0G", "TEAC_CD-516E_1.0G", BUS_TYPE_IDE }, { "TEAC", "CD-524EA", "3.0D", "TEAC CD-524EA 3.0D", "TEAC_CD-524EA_3.0D", BUS_TYPE_IDE }, { "TEAC", "CD-532E", "2.0A", "TEAC CD-532E 2.0A", "TEAC_CD_532E_2.0A", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-6202B", "1512", "TOSHIBA CD-ROM XM-6202B 1512", "TOSHIBA_CD-ROM_XM-6202B_1512", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-6402B", "1008", "TOSHIBA CD-ROM XM-6402B 1008", "TOSHIBA_CD-ROM_XM-6402B_1008", BUS_TYPE_IDE }, - { "TOSHIBA", "CD-ROM XM-6702B", "1007", "TOSHIBA CD-ROM XM-6702B 1007", "TOSHIBA_CD-ROM_XM-6702B_1007", BUS_TYPE_IDE }, - { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1051", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-5302TA", "0305", "TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-5702B", "TA70", "TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6202B", "1512", "TOSHIBA CD-ROM XM-6202B 1512", "TOSHIBA_CD-ROM_XM-6202B_1512", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6402B", "1008", "TOSHIBA CD-ROM XM-6402B 1008", "TOSHIBA_CD-ROM_XM-6402B_1008", BUS_TYPE_IDE }, + { "TOSHIBA", "CD-ROM XM-6702B", "1007", "TOSHIBA CD-ROM XM-6702B 1007", "TOSHIBA_CD-ROM_XM-6702B_1007", BUS_TYPE_IDE }, + { "TOSHIBA", "DVD-ROM SD-M1802", "1051", "TOSHIBA DVD-ROM SD-M1802 1051", "TOSHIBA_DVD-ROM_SD-M1802_1051", BUS_TYPE_IDE }, { "CHINON", "CD-ROM CDS-431", "H42 ", "[SCSI-1] CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI }, { "CHINON", "CD-ROM CDX-435", "M62 ", "[SCSI-1] CHINON CD-ROM CDX-435 M62", "CHINON_CD-ROM_CDX-435_M62", BUS_TYPE_SCSI }, { "DEC", "RRD45 (C) DEC", "0436", "[SCSI-1] DEC RRD45 0436", "DEC_RRD45_0436", BUS_TYPE_SCSI }, From 15684d6665d671ab59d163d2d4d3d9ab80341b09 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Thu, 16 Jan 2025 01:18:00 -0500 Subject: [PATCH 33/43] Initialized ret to 0 --- src/machine/m_at.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/m_at.c b/src/machine/m_at.c index 93d111510..3f5e88011 100644 --- a/src/machine/m_at.c +++ b/src/machine/m_at.c @@ -203,7 +203,7 @@ const device_t ibmat_device = { int machine_at_ibm_init(const machine_t *model) { - int ret; + int ret = 0; uint8_t enable_5161; const char *fn[2]; From fceca8d1db0829939b637e6b6b810a378c641f85 Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Thu, 16 Jan 2025 20:51:32 +0700 Subject: [PATCH 34/43] Added note on CFS1275A --- src/disk/hdd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index 6872c7ae1..f10d1f3bf 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -469,7 +469,7 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-2] Western Digital Caviar 22000", .internal_name = "AC22000", .model = "WDC AC22000LA", .zones = 8, .avg_spt = 130, .heads = 3, .rpm = 5200, .full_stroke_ms = 33, .track_seek_ms = 3.5, .rcache_num_seg = 4, .rcache_seg_size = 128, .max_multiple = 8 }, { .name = "[ATA-2] Western Digital Caviar 22100", .internal_name = "AC22100", .model = "WDC AC22100H", .zones = 8, .avg_spt = 140, .heads = 4, .rpm = 5200, .full_stroke_ms = 30, .track_seek_ms = 3, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-2] Western Digital Caviar 31200", .internal_name = "AC31200", .model = "WDC AC31200F", .zones = 8, .avg_spt = 110, .heads = 4, .rpm = 4500, .full_stroke_ms = 12, .track_seek_ms = 4, .rcache_num_seg = 8, .rcache_seg_size = 64, .max_multiple = 16 }, - { .name = "[ATA-3] Connor CFS1275A", .internal_name = "CFS1275A", .model = "Connor Peripherals 1275MB - CFS1275A", .zones = 4, .avg_spt = 130, .heads = 2, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.8, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 16 }, + { .name = "[ATA-3] Connor CFS1275A", .internal_name = "CFS1275A", .model = "Connor Peripherals 1275MB - CFS1275A", .zones = 4, .avg_spt = 130, .heads = 2, .rpm = 4500, .full_stroke_ms = 25, .track_seek_ms = 3.8, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 16 }, // Either ATA-2 or ATA-3 { .name = "[ATA-3] Fujitsu MPA3017AT", .internal_name = "MPA3017AT", .model = "FUJITSU MPA3017AT", .zones = 5, .avg_spt = 95, .heads = 2, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-3] Fujitsu MPA3026AT", .internal_name = "MPA3026AT", .model = "FUJITSU MPA3026AT", .zones = 8, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, { .name = "[ATA-3] Fujitsu MPA3035AT", .internal_name = "MPA3035AT", .model = "FUJITSU MPA3035AT", .zones = 11, .avg_spt = 95, .heads = 4, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 3.2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 16 }, From 7696b1c13126c70ccc4de8a8c39748488667c72b Mon Sep 17 00:00:00 2001 From: MaxwellS04 Date: Fri, 17 Jan 2025 03:02:19 +0700 Subject: [PATCH 35/43] A small fix to SV2046D --- src/disk/hdd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/disk/hdd.c b/src/disk/hdd.c index f10d1f3bf..c17f64863 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -535,7 +535,7 @@ static hdd_preset_t hdd_speed_presets[] = { { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1023D)", .internal_name = "SV1023D", .model = "SAMSUNG SV1023D", .zones = 8, .avg_spt = 95, .heads = 3, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1364D)", .internal_name = "SV1364D", .model = "SAMSUNG SV1364D", .zones = 8, .avg_spt = 95, .heads = 4, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Samsung SpinPoint V6800 (SV1705D)", .internal_name = "SV1705D", .model = "SAMSUNG SV1705D", .zones = 8, .avg_spt = 95, .heads = 5, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, - { .name = "[ATA-5] Samsung SpinPoint V6800 (SV2046D)", .internal_name = "SV2046D", .model = "SAMSUNG SV1023D", .zones = 8, .avg_spt = 95, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, + { .name = "[ATA-5] Samsung SpinPoint V6800 (SV2046D)", .internal_name = "SV2046D", .model = "SAMSUNG SV2046D", .zones = 8, .avg_spt = 95, .heads = 6, .rpm = 5400, .full_stroke_ms = 18, .track_seek_ms = 1.3, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 4.3gb", .internal_name = "ST34313A", .model = "ST34313A", .zones = 16, .avg_spt = 89, .heads = 1, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 8.4gb", .internal_name = "ST38410A", .model = "ST38410A", .zones = 16, .avg_spt = 89, .heads = 2, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, { .name = "[ATA-5] Seagate U8 - 13gb", .internal_name = "ST313021A", .model = "ST313021A", .zones = 16, .avg_spt = 89, .heads = 4, .rpm = 5400, .full_stroke_ms = 25, .track_seek_ms = 1.5, .rcache_num_seg = 16, .rcache_seg_size = 512, .max_multiple = 32 }, From ba86e5116f67dba7756f6451bfa59e4b3b67bc53 Mon Sep 17 00:00:00 2001 From: Ectoplasm Date: Thu, 16 Jan 2025 22:28:34 +0200 Subject: [PATCH 36/43] GlaBIOS for Juko ST --- src/machine/m_xt.c | 52 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 3 deletions(-) diff --git a/src/machine/m_xt.c b/src/machine/m_xt.c index 2988ec201..ef3a84e24 100644 --- a/src/machine/m_xt.c +++ b/src/machine/m_xt.c @@ -594,13 +594,59 @@ machine_xt_dtk_init(const machine_t *model) return ret; } +static const device_config_t jukopc_config[] = { + // clang-format off + { + .name = "bios", + .description = "BIOS Version", + .type = CONFIG_BIOS, + .default_string = "jukost", + .default_int = 0, + .file_filter = "", + .spinner = { 0 }, + .bios = { + { .name = "Bios 2.30", .internal_name = "jukost", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 8192, .files = { "roms/machines/jukopc/000o001.bin", "" } }, + // GlaBIOS for Juko ST + { .name = "GlaBIOS 0.2.5 (8088)", .internal_name = "glabios_025_8088", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 8192, .files = { "roms/machines/glabios/GLABIOS_0.2.5_8S_2.ROM", "" } }, + { .name = "GlaBIOS 0.2.5 (V20)", .internal_name = "glabios_025_v20", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 8192, .files = { "roms/machines/glabios/GLABIOS_0.2.5_VS_2.ROM", "" } }, + { .files_no = 0 } + }, + }, + { .name = "", .description = "", .type = CONFIG_END } + // clang-format on +}; + +const device_t jukopc_device = { + .name = "Juko ST Devices", + .internal_name = "jukopc_device", + .flags = 0, + .local = 0, + .init = NULL, + .close = NULL, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = jukopc_config +}; + int machine_xt_jukopc_init(const machine_t *model) { - int ret; + int ret = 0; + const char *fn; - ret = bios_load_linear("roms/machines/jukopc/000o001.bin", - 0x000fe000, 8192, 0); + /* No ROMs available. */ + if (!device_available(model->device)) + return ret; + + device_context(model->device); + fn = device_get_bios_file(model->device, device_get_config_bios("bios"), 0); + ret = bios_load_linear(fn, 0x000fe000, 8192, 0); + device_context_restore(); if (bios_only || !ret) return ret; From b293aa518c03e91f0a926695ab1edadb966e8cc2 Mon Sep 17 00:00:00 2001 From: Ectoplasm Date: Thu, 16 Jan 2025 22:31:45 +0200 Subject: [PATCH 37/43] GlaBIOS for Juko ST --- src/machine/machine_table.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 47a33fa8c..14ad58f95 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -64,6 +64,7 @@ extern const device_t ibmxt86_device; extern const device_t ibmat_device; extern const device_t ibmxt286_device; extern const device_t pb450_device; +extern const device_t jukopc_device; const machine_filter_t machine_types[] = { { "None", MACHINE_TYPE_NONE }, @@ -954,7 +955,7 @@ const machine_t machines[] = { .kbc_p1 = 0xff, .gpio = 0xffffffff, .gpio_acpi = 0xffffffff, - .device = NULL, + .device = &jukopc_device, .fdc_device = NULL, .sio_device = NULL, .vid_device = NULL, From 54a0bb8522dbf2a061f762b43f6846e1dae1d160 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Thu, 16 Jan 2025 22:37:52 +0100 Subject: [PATCH 38/43] 1st set of changes (video-related) of the day (January 16th, 2025) ATI Mach8-based (add-on only): Do not override the clone VGA banked mapping with the standard VGA when needed. Fixes issues with banked mapping with ATI 8514/A enabled on cards with clone mappings such as Cirrus, Video7, Paradise/WD, etc. --- src/video/vid_ati_mach8.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/video/vid_ati_mach8.c b/src/video/vid_ati_mach8.c index 558f37f5b..d294f61e9 100644 --- a/src/video/vid_ati_mach8.c +++ b/src/video/vid_ati_mach8.c @@ -3493,14 +3493,17 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8 dev->vendor_mode = 1; } svga_recalctimings(svga); - mach32_updatemapping(mach, svga); + if ((dev->local & 0xff) >= 0x01) + mach32_updatemapping(mach, svga); + mach_log("ATI 8514/A: (0x%04x) val=0x%02x, extended 8514/A mode=%02x.\n", port, val, mach->regs[0xb0] & 0x20); break; case 0x32ee: case 0x32ef: WRITE8(port, mach->local_cntl, val); - mach32_updatemapping(mach, svga); + if ((dev->local & 0xff) >= 0x01) + mach32_updatemapping(mach, svga); break; case 0x36ee: @@ -3546,7 +3549,8 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8 mach_log("ATI 8514/A: (0x%04x): ON=%d, val=%04x, hdisp=%d, vdisp=%d.\n", port, mach->accel.clock_sel & 0x01, val, dev->hdisp, dev->vdisp); mach_log("Vendor ATI mode set %s resolution.\n", (dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480"); svga_recalctimings(svga); - mach32_updatemapping(mach, svga); + if ((dev->local & 0xff) >= 0x01) + mach32_updatemapping(mach, svga); break; case 0x52ee: @@ -3580,7 +3584,8 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8 if (!mach->pci_bus) mach->linear_base = (mach->memory_aperture & 0xff00) << 12; - mach32_updatemapping(mach, svga); + if ((dev->local & 0xff) >= 0x01) + mach32_updatemapping(mach, svga); break; case 0x62ee: From 9a13eb7413bbe655a5ffd4de8481cc2e2cc7ad74 Mon Sep 17 00:00:00 2001 From: greblosdier <51314920+greblosdier@users.noreply.github.com> Date: Thu, 16 Jan 2025 13:46:01 -0800 Subject: [PATCH 39/43] Fix incorrect chipset for MVI486 Changes the chipset of the Mylex MVI486 from Opti 82C895 to 82C495 --- src/machine/machine_table.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 47a33fa8c..58ad404f4 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -5962,10 +5962,10 @@ const machine_t machines[] = { /* Uses some variant of Phoenix MultiKey/42 as the Intel 8242 chip has a Phoenix copyright. */ { - .name = "[OPTi 895] Mylex MVI486", + .name = "[OPTi 495] Mylex MVI486", .internal_name = "mvi486", .type = MACHINE_TYPE_486, - .chipset = MACHINE_CHIPSET_OPTI_895_802G, + .chipset = MACHINE_CHIPSET_OPTI_495, .init = machine_at_mvi486_init, .p1_handler = NULL, .gpio_handler = NULL, From 5d25309027fac853bb8a2d890fe889c4c8f6e561 Mon Sep 17 00:00:00 2001 From: greblosdier <51314920+greblosdier@users.noreply.github.com> Date: Thu, 16 Jan 2025 13:49:43 -0800 Subject: [PATCH 40/43] Fixes incorrect chipset model for MVI486 Fixes MVI486 to use Opti 495 chipset --- src/machine/m_at_386dx_486.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index d3c7a21d2..656db503b 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -834,7 +834,7 @@ machine_at_mvi486_init(const machine_t *model) machine_at_common_init(model); - device_add(&opti895_device); + device_add(&opti495_device); device_add(&keyboard_at_device); device_add(&pc87311_ide_device); From ef8a3d8d427bfbc327331fc9d4f72c39f9dce6c8 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 23:18:41 +0100 Subject: [PATCH 41/43] SCAMP: Reworked a lot of stuff, backfill EMS should now also work. --- src/chipset/scamp.c | 848 +++++++++++++++++++++++++++----------------- 1 file changed, 520 insertions(+), 328 deletions(-) diff --git a/src/chipset/scamp.c b/src/chipset/scamp.c index 00f9798cb..31e24eeba 100644 --- a/src/chipset/scamp.c +++ b/src/chipset/scamp.c @@ -47,13 +47,35 @@ #define ID_VL82C311 0xd6 -#define RAMMAP_REMP386 (1 << 4) +#define RAMMAP_ROMMOV 0x60 +#define RAMMAP_ROMMOV1 (1 << 6) +#define RAMMAP_ROMMOV0 (1 << 5) +#define RAMMAP_REMP384 (1 << 4) #define EMSEN1_EMSMAP (1 << 4) +#define EMSEN1_BFENAB (1 << 6) #define EMSEN1_EMSENAB (1 << 7) #define NR_ELEMS(x) (sizeof(x) / sizeof(x[0])) +#define EMS_MAXPAGE 4 +#define EMS_PGSIZE 16384 +#define EMS_PGMASK 16383 + +#define MEM_FLAG_SLOTBUS 0x40 +#define MEM_FLAG_REMAP 0x20 +#define MEM_FLAG_MEMCARD 0x10 +#define MEM_FLAG_EMS 0x08 +#define MEM_FLAG_ROMCS 0x04 +#define MEM_FLAG_READ 0x02 +#define MEM_FLAG_WRITE 0x01 +#define MEM_FMASK_SLOTBUS 0x40 +#define MEM_FMASK_REMAP 0x20 +#define MEM_FMASK_MEMCARD 0x10 +#define MEM_FMASK_EMS 0x08 +#define MEM_FMASK_ROMCS 0x04 +#define MEM_FMASK_RW 0x03 + /*Commodore SL386SX requires proper memory slot decoding to detect memory size. Therefore we emulate the SCAMP memory address decoding, and therefore are limited to the DRAM combinations supported by the actual chip*/ @@ -72,38 +94,43 @@ typedef struct ram_struct_t { int bank; } ram_struct_t; -typedef struct ems_struct_t { - void *parent; - int segment; -} ems_struct_t; +typedef struct card_mem_t { + int in_ram; + uint32_t virt_addr; + uint32_t phys_addr; + uint8_t *mem; +} mem_page_t; typedef struct scamp_t { - int cfg_index; - uint8_t cfg_regs[256]; - int cfg_enable; - int ram_config; + int cfg_index; + uint8_t cfg_regs[256]; + int cfg_enable; + int ram_config; int ems_index; int ems_autoinc; - uint16_t ems[0x24]; - mem_mapping_t ems_mappings[20]; /*a0000-effff*/ - uint32_t mappings[20]; + uint16_t ems[64]; mem_mapping_t ram_mapping[2]; ram_struct_t ram_struct[2]; - ems_struct_t ems_struct[20]; - uint32_t ram_virt_base[2]; - uint32_t ram_phys_base[2]; - uint32_t ram_mask[2]; - int row_virt_shift[2]; - int row_phys_shift[2]; - int ram_interleaved[2]; - int ibank_shift[2]; + uint32_t ram_virt_base[2]; + uint32_t ram_phys_base[2]; + uint32_t ram_mask[2]; + int row_virt_shift[2]; + int row_phys_shift[2]; + int ram_interleaved[2]; + int ibank_shift[2]; - int ram_flags[24]; + int mem_flags[64]; + mem_mapping_t mem_mappings[64]; /* The entire first 1 MB of memory space. */ + mem_page_t mem_pages[64]; - port_92_t *port_92; + uint32_t card_mem_size; + uint8_t *card_mem; + mem_page_t card_pages[4]; + + port_92_t *port_92; } scamp_t; static const struct { @@ -149,6 +176,70 @@ static const struct { { { BANK_1M_INTERLEAVED, BANK_4M_INTERLEAVED }, 0}, /*Undocumented - probably wrong!*/ }; +#ifdef ENABLE_SCAMP_LOG +int scamp_do_log = ENABLE_SCAMP_LOG; + +static void +scamp_log(const char *fmt, ...) +{ + va_list ap; + + if (scamp_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +# define scamp_log(fmt, ...) +#endif + +/* Read one byte from paged RAM. */ +static uint8_t +scamp_mem_readb(uint32_t addr, void *priv) +{ + mem_page_t *dev = (mem_page_t *) priv; + uint8_t ret = 0xff; + + if (dev->mem != NULL) + ret = *(uint8_t *) &(dev->mem[addr & EMS_PGMASK]); + + return ret; +} + +/* Read one word from paged RAM. */ +static uint16_t +scamp_mem_readw(uint32_t addr, void *priv) +{ + mem_page_t *dev = (mem_page_t *) priv; + uint16_t ret = 0xffff; + + if (dev->mem != NULL) + ret = *(uint16_t *) &(dev->mem[addr & EMS_PGMASK]); + + return ret; +} + +/* Write one byte to paged RAM. */ +static void +scamp_mem_writeb(uint32_t addr, uint8_t val, void *priv) +{ + mem_page_t *dev = (mem_page_t *) priv; + + if (dev->mem != NULL) + *(uint8_t *) &(dev->mem[addr & EMS_PGMASK]) = val; +} + +/* Write one word to paged RAM. */ +static void +scamp_mem_writew(uint32_t addr, uint16_t val, void *priv) +{ + mem_page_t *dev = (mem_page_t *) priv; + + if (dev->mem != NULL) + *(uint16_t *) &(dev->mem[addr & EMS_PGMASK]) = val; +} + /* The column bits masked when using 256kbit DRAMs in 4Mbit mode aren't contiguous, so we use separate routines for that special case */ static uint8_t @@ -334,208 +425,193 @@ recalc_mappings(void *priv) /* Once the BIOS programs the correct DRAM configuration, switch to regular linear memory mapping */ if (cur_rammap == ram_configs[dev->ram_config].rammap) { - mem_mapping_set_handler(&ram_low_mapping, - mem_read_ram, mem_read_ramw, mem_read_raml, - mem_write_ram, mem_write_ramw, mem_write_raml); - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_disable(&ram_low_mapping); + + for (uint8_t i = 0; i < 40; i++) + mem_mapping_enable(&(dev->mem_mappings[i])); + if (mem_size > 1024) mem_set_mem_state_both((1 << 20), (mem_size - 1024) << 10, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); mem_mapping_enable(&ram_high_mapping); - return; } else { mem_mapping_set_handler(&ram_low_mapping, ram_mirrored_read, NULL, NULL, ram_mirrored_write, NULL, NULL); + mem_mapping_disable(&ram_low_mapping); - } - if (rammap[cur_rammap].bank[0] == BANK_NONE) - bank_nr = 1; + for (uint8_t i = 0; i < 40; i++) + mem_mapping_disable(&(dev->mem_mappings[i])); - for (; bank_nr < 2; bank_nr++) { - old_virt_base = virt_base; - phys_bank = ram_configs[dev->ram_config].bank[bank_nr]; + if (rammap[cur_rammap].bank[0] == BANK_NONE) + bank_nr = 1; - dev->ram_virt_base[bank_nr] = virt_base; + for (; bank_nr < 2; bank_nr++) { + old_virt_base = virt_base; + phys_bank = ram_configs[dev->ram_config].bank[bank_nr]; - if (virt_base == 0) { - switch (rammap[cur_rammap].bank[bank_nr]) { - case BANK_NONE: - fatal(" Bank %i is empty!\n }\n}\n", bank_nr); - break; + dev->ram_virt_base[bank_nr] = virt_base; - case BANK_256K: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0x80000); - mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); - } - virt_base += (1 << 19); - dev->row_virt_shift[bank_nr] = 10; - break; + if (virt_base == 0) { + switch (rammap[cur_rammap].bank[bank_nr]) { + case BANK_NONE: + fatal(" Bank %i is empty!\n }\n}\n", bank_nr); + break; - case BANK_256K_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); - } - virt_base += (1 << 20); - dev->row_virt_shift[bank_nr] = 10; - break; + case BANK_256K: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0x80000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + } + virt_base += (1 << 19); + dev->row_virt_shift[bank_nr] = 10; + break; - case BANK_1M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x100000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 21); - dev->row_virt_shift[bank_nr] = 11; - break; + case BANK_256K_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + } + virt_base += (1 << 20); + dev->row_virt_shift[bank_nr] = 10; + break; - case BANK_1M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x300000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (3 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 22); - dev->row_virt_shift[bank_nr] = 11; - break; + case BANK_1M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x100000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 21); + dev->row_virt_shift[bank_nr] = 11; + break; - case BANK_4M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x700000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (7 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 23); - dev->row_virt_shift[bank_nr] = 12; - break; + case BANK_1M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x300000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (3 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 22); + dev->row_virt_shift[bank_nr] = 11; + break; - case BANK_4M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0xf00000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (15 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 24); - dev->row_virt_shift[bank_nr] = 12; - break; + case BANK_4M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x700000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (7 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 23); + dev->row_virt_shift[bank_nr] = 12; + break; - default: - break; + case BANK_4M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0xf00000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (15 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 24); + dev->row_virt_shift[bank_nr] = 12; + break; + + default: + break; + } + } else { + switch (rammap[cur_rammap].bank[bank_nr]) { + case BANK_NONE: + break; + + case BANK_256K: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x80000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 19), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 19); + dev->row_virt_shift[bank_nr] = 10; + break; + + case BANK_256K_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x100000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 20); + dev->row_virt_shift[bank_nr] = 10; + break; + + case BANK_1M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x200000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 21), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 21); + dev->row_virt_shift[bank_nr] = 11; + break; + + case BANK_1M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x400000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 22), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 22); + dev->row_virt_shift[bank_nr] = 11; + break; + + case BANK_4M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x800000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 23), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 23); + dev->row_virt_shift[bank_nr] = 12; + break; + + case BANK_4M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x1000000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 24), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 24); + dev->row_virt_shift[bank_nr] = 12; + break; + + default: + break; + } } - } else { + switch (rammap[cur_rammap].bank[bank_nr]) { - case BANK_NONE: - break; - case BANK_256K: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x80000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 19), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 19); - dev->row_virt_shift[bank_nr] = 10; - break; - - case BANK_256K_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x100000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 20); - dev->row_virt_shift[bank_nr] = 10; - break; - case BANK_1M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x200000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 21), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 21); - dev->row_virt_shift[bank_nr] = 11; - break; - - case BANK_1M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x400000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 22), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 22); - dev->row_virt_shift[bank_nr] = 11; - break; - case BANK_4M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x800000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 23), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 23); - dev->row_virt_shift[bank_nr] = 12; - break; - - case BANK_4M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x1000000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 24), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 24); - dev->row_virt_shift[bank_nr] = 12; - break; - - default: - break; - } - } - switch (rammap[cur_rammap].bank[bank_nr]) { - case BANK_256K: - case BANK_1M: - case BANK_4M: - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_read, NULL, NULL, - ram_mirrored_write, NULL, NULL); - if (!old_virt_base) - mem_mapping_set_handler(&ram_low_mapping, + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], ram_mirrored_read, NULL, NULL, ram_mirrored_write, NULL, NULL); - break; - - case BANK_256K_INTERLEAVED: - case BANK_1M_INTERLEAVED: - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_interleaved_read, NULL, NULL, - ram_mirrored_interleaved_write, NULL, NULL); - if (!old_virt_base) - mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_interleaved_read, NULL, NULL, - ram_mirrored_interleaved_write, NULL, NULL); - break; - - case BANK_4M_INTERLEAVED: - if (phys_bank == BANK_256K || phys_bank == BANK_256K_INTERLEAVED) { - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_256k_in_4mi_read, NULL, NULL, - ram_mirrored_256k_in_4mi_write, NULL, NULL); if (!old_virt_base) mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_256k_in_4mi_read, NULL, NULL, - ram_mirrored_256k_in_4mi_write, NULL, NULL); - } else { + ram_mirrored_read, NULL, NULL, + ram_mirrored_write, NULL, NULL); + break; + + case BANK_256K_INTERLEAVED: + case BANK_1M_INTERLEAVED: mem_mapping_set_handler(&dev->ram_mapping[bank_nr], ram_mirrored_interleaved_read, NULL, NULL, ram_mirrored_interleaved_write, NULL, NULL); @@ -543,131 +619,137 @@ recalc_mappings(void *priv) mem_mapping_set_handler(&ram_low_mapping, ram_mirrored_interleaved_read, NULL, NULL, ram_mirrored_interleaved_write, NULL, NULL); - } - break; + break; - default: - break; + case BANK_4M_INTERLEAVED: + if (phys_bank == BANK_256K || phys_bank == BANK_256K_INTERLEAVED) { + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], + ram_mirrored_256k_in_4mi_read, NULL, NULL, + ram_mirrored_256k_in_4mi_write, NULL, NULL); + if (!old_virt_base) + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_256k_in_4mi_read, NULL, NULL, + ram_mirrored_256k_in_4mi_write, NULL, NULL); + } else { + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], + ram_mirrored_interleaved_read, NULL, NULL, + ram_mirrored_interleaved_write, NULL, NULL); + if (!old_virt_base) + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_interleaved_read, NULL, NULL, + ram_mirrored_interleaved_write, NULL, NULL); + } + break; + + default: + break; + } } } } static void -recalc_sltptr(scamp_t *dev) +scamp_mem_update_state(scamp_t *dev, uint32_t addr, uint32_t size, uint8_t new_flags, uint8_t mask) { - uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16; + int read_ext = MEM_READ_EXTERNAL; + int write_ext = MEM_WRITE_EXTERNAL; - if (sltptr >= 0xa0000 && sltptr < 0x100000) - sltptr = 0x100000; - if (sltptr > 0xfe0000) - sltptr = 0xfe0000; + if ((addr < 0x00100000) && ((new_flags ^ dev->mem_flags[addr / EMS_PGSIZE]) & mask)) { + dev->mem_flags[addr / EMS_PGSIZE] &= ~mask; + dev->mem_flags[addr / EMS_PGSIZE] |= new_flags; - if (sltptr >= 0xa0000) { - mem_set_mem_state(0, 0xa0000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } else { - mem_set_mem_state(0, sltptr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_set_mem_state(sltptr, 0xa0000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } -} + new_flags = dev->mem_flags[addr / EMS_PGSIZE]; -static uint8_t -scamp_ems_read(uint32_t addr, void *priv) -{ - const ems_struct_t *ems = (ems_struct_t *) priv; - const scamp_t *dev = ems->parent; - int segment = ems->segment; + if (new_flags & MEM_FLAG_ROMCS) { + read_ext = MEM_READ_ROMCS; + write_ext = MEM_WRITE_ROMCS; + } - addr = (addr & 0x3fff) | dev->mappings[segment]; - return ram[addr]; -} - -static void -scamp_ems_write(uint32_t addr, uint8_t val, void *priv) -{ - const ems_struct_t *ems = (ems_struct_t *) priv; - const scamp_t *dev = ems->parent; - int segment = ems->segment; - - addr = (addr & 0x3fff) | dev->mappings[segment]; - ram[addr] = val; -} - -static void -scamp_mem_update_state(scamp_t *dev, uint32_t addr, uint32_t size) -{ - uint8_t flags; - - if ((addr >= 0x000a0000) && (addr < 0x00100000)) { - flags = dev->ram_flags[(addr - 0x000a0000) >> 14]; - - if (flags & 4) + if (new_flags & (MEM_FLAG_REMAP | MEM_FLAG_SLOTBUS)) { + scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (REMAP)\n", addr, addr + size - 1, new_flags); + mem_set_mem_state(addr, size, read_ext | write_ext); + } else if (new_flags & (MEM_FLAG_EMS | MEM_FLAG_MEMCARD)) { + scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (EMS)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else switch (flags & 3) { + } else switch (new_flags & (MEM_FLAG_READ | MEM_FLAG_WRITE)) { case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RE | WE)\n", addr, addr + size - 1, new_flags); + mem_set_mem_state(addr, size, read_ext | write_ext); break; case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RE | WI)\n", addr, addr + size - 1, new_flags); + mem_set_mem_state(addr, size, read_ext | MEM_WRITE_INTERNAL); break; case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RI | WE)\n", addr, addr + size - 1, new_flags); + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | write_ext); break; case 3: + scamp_log("scamp_mem_update_state(): %08X-%08X: %02X (RI | WI)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); break; default: break; } } + + flushmmucache_nopc(); +} + +static int +is_seg_in_ram(scamp_t *dev, uint8_t s) +{ + mem_page_t *mp = (mem_page_t *) dev->mem_mappings[s].priv; + const int ret = mp->in_ram; + + return ret; } static void recalc_ems(scamp_t *dev) { - const uint32_t ems_base[12] = { - 0xc0000, 0xc4000, 0xc8000, 0xcc000, - 0xd0000, 0xd4000, 0xd8000, 0xdc000, - 0xe0000, 0xe4000, 0xe8000, 0xec000 - }; - uint32_t new_mappings[20]; - uint16_t ems_enable; + const uint8_t seg_xlat[12] = { 40, 41, 42, 43, 52, 53, 54, 55, 44, 45, 46, 47 }; + const uint16_t seg_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8); - for (int segment = 0; segment < 20; segment++) - new_mappings[segment] = 0xa0000 + segment * 0x4000; + for (uint8_t s = 40; s < 60; s++) { + dev->mem_pages[s].phys_addr = dev->mem_pages[s].virt_addr; + dev->mem_pages[s].mem = ram + dev->mem_pages[s].phys_addr; - if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) - ems_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8); - else - ems_enable = 0; + if (is_seg_in_ram(dev, s)) + mem_mapping_set_exec(&(dev->mem_mappings[s]), dev->mem_pages[s].mem); - for (int segment = 0; segment < 12; segment++) { - if (ems_enable & (1 << segment)) { - uint32_t phys_addr = dev->ems[segment] << 14; - - /*If physical address is in remapped memory then adjust down to a0000-fffff range*/ - if ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) && phys_addr >= (mem_size * 1024) - && phys_addr < ((mem_size + 384) * 1024)) - phys_addr = (phys_addr - mem_size * 1024) + 0xa0000; - new_mappings[(ems_base[segment] - 0xa0000) >> 14] = phys_addr; - } + scamp_mem_update_state(dev, s * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_EMS); } - for (int segment = 0; segment < 20; segment++) { - if (new_mappings[segment] != dev->mappings[segment]) { - dev->mappings[segment] = new_mappings[segment]; - if (new_mappings[segment] < (mem_size * 1024)) { - mem_mapping_set_exec(&dev->ems_mappings[segment], ram + dev->mappings[segment]); - mem_mapping_enable(&dev->ems_mappings[segment]); - dev->ram_flags[segment] |= 0x04; - } else { - mem_mapping_disable(&dev->ems_mappings[segment]); - dev->ram_flags[segment] &= 0xfb; - } + for (uint8_t i = 0; i < 36; i++) { + uint8_t s = (i < 12) ? (i + 48) : (i + 4); + uint8_t on = (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB); + uint32_t phys_addr = dev->ems[i] << 14; - scamp_mem_update_state(dev, 0xa0000 + segment * 0x4000, 0x4000); + if (i < 12) { + if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSMAP) + s = seg_xlat[i]; + + on = on && (seg_enable & (1 << i)); + } else + on = on && (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_BFENAB); + + if (on) { + dev->mem_pages[s].phys_addr = phys_addr; + dev->mem_pages[s].mem = ram + dev->mem_pages[s].phys_addr; + + if (is_seg_in_ram(dev, s)) + mem_mapping_set_exec(&(dev->mem_mappings[s]), dev->mem_pages[s].mem); + + scamp_mem_update_state(dev, s * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_EMS, MEM_FMASK_EMS); + } else if (i >= 12) { + dev->mem_pages[s].phys_addr = dev->mem_pages[s].virt_addr; + dev->mem_pages[s].mem = ram + dev->mem_pages[s].phys_addr; + + if (is_seg_in_ram(dev, s)) + mem_mapping_set_exec(&(dev->mem_mappings[s]), dev->mem_pages[s].mem); + + scamp_mem_update_state(dev, s * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_EMS); } } @@ -677,32 +759,11 @@ recalc_ems(scamp_t *dev) static void shadow_control(scamp_t *dev, uint32_t addr, uint32_t size, int state) { - dev->ram_flags[(addr - 0x000a0000) >> 14] &= 0xfc; - dev->ram_flags[(addr - 0x000a0000) >> 14] |= state; - if (size == 0x8000) { - dev->ram_flags[((addr - 0x000a0000) >> 14) + 1] &= 0xfc; - dev->ram_flags[((addr - 0x000a0000) >> 14) + 1] |= state; - } - - switch (state) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - default: - break; - } - - scamp_mem_update_state(dev, addr, size); + scamp_mem_update_state(dev, addr, EMS_PGSIZE, state, MEM_FMASK_RW); + scamp_mem_update_state(dev, addr + EMS_PGSIZE, EMS_PGSIZE, state, MEM_FMASK_RW); + } else + scamp_mem_update_state(dev, addr, size, state, MEM_FMASK_RW); flushmmucache_nopc(); } @@ -710,14 +771,23 @@ shadow_control(scamp_t *dev, uint32_t addr, uint32_t size, int state) static void shadow_recalc(scamp_t *dev) { - uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_ABAXS]; - uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_CAXS]; - uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_DAXS]; - uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_FEAXS]; + uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_ABAXS]; + uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_CAXS]; + uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_DAXS]; + uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) ? 0 : dev->cfg_regs[CFG_FEAXS]; /*Enabling remapping will disable all shadowing*/ - if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) - mem_remap_top(384); + if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) + mem_remap_top_nomid(384); + else + mem_remap_top_nomid(0); + + for (uint8_t i = 40; i < 64; i++) { + if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP384) + scamp_mem_update_state(dev, (i * EMS_PGSIZE), EMS_PGSIZE, MEM_FLAG_REMAP, MEM_FMASK_REMAP); + else + scamp_mem_update_state(dev, (i * EMS_PGSIZE), EMS_PGSIZE, 0x00, MEM_FMASK_REMAP); + } shadow_control(dev, 0xa0000, 0x4000, abaxs & 3); shadow_control(dev, 0xa0000, 0x4000, abaxs & 3); @@ -748,6 +818,97 @@ shadow_recalc(scamp_t *dev) shadow_control(dev, 0xf8000, 0x8000, (feaxs >> 6) & 3); } +static void +recalc_sltptr(scamp_t *dev) +{ + uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16; + + if (sltptr >= 0xa0000 && sltptr < 0x100000) + sltptr = 0x100000; + if (sltptr > 0xfe0000) + sltptr = 0xfe0000; + + if (sltptr >= 0xa0000) { + for (uint8_t i = 0; i < 40; i++) + scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_SLOTBUS); + + mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + + if ((sltptr >= 0x40000) && (sltptr <= 0x90000)) { + dev->cfg_regs[CFG_EMSEN1] &= ~EMSEN1_BFENAB; + recalc_ems(dev); + } + } else { + for (uint8_t i = 0; i < (sltptr / EMS_PGSIZE); i++) + scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_SLOTBUS); + + for (uint8_t i = (sltptr / EMS_PGSIZE); i < 40; i++) + scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_SLOTBUS, MEM_FMASK_SLOTBUS); + + mem_set_mem_state(sltptr, 0xa0000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } + + flushmmucache_nopc(); +} + +static void +recalc_rommov(scamp_t *dev) +{ + switch ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_ROMMOV) >> 5) { + case 0x00: + scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + + scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + break; + + case 0x01: + scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + + scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + break; + + case 0x02: + scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + + scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + break; + + case 0x03: + scamp_mem_update_state(dev, 0x000c0000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c4000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000c8000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000cc000, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + + scamp_mem_update_state(dev, 0x000e0000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e4000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000e8000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + scamp_mem_update_state(dev, 0x000ec000, EMS_PGSIZE, 0x00, MEM_FMASK_ROMCS); + break; + } + + flushmmucache_nopc(); +} + static void scamp_write(uint16_t addr, uint8_t val, void *priv) { @@ -755,7 +916,7 @@ scamp_write(uint16_t addr, uint8_t val, void *priv) switch (addr) { case 0xe8: - dev->ems_index = val & 0x1f; + dev->ems_index = val & 0x3f; dev->ems_autoinc = val & 0x40; break; @@ -785,12 +946,14 @@ scamp_write(uint16_t addr, uint8_t val, void *priv) switch (dev->cfg_index) { case CFG_SLTPTR: recalc_sltptr(dev); + recalc_ems(dev); break; case CFG_RAMMAP: recalc_mappings(dev); mem_mapping_disable(&ram_remapped_mapping); shadow_recalc(dev); + recalc_rommov(dev); break; case CFG_EMSEN1: @@ -914,9 +1077,8 @@ scamp_init(UNUSED(const device_t *info)) mem_mapping_set_handler(&ram_low_mapping, ram_mirrored_read, NULL, NULL, ram_mirrored_write, NULL, NULL); + mem_mapping_disable(&ram_mid_mapping); mem_mapping_disable(&ram_high_mapping); - mem_mapping_set_addr(&ram_mid_mapping, 0xf0000, 0x10000); - mem_mapping_set_exec(&ram_mid_mapping, ram + 0xf0000); addr = 0; for (uint8_t c = 0; c < 2; c++) { @@ -988,15 +1150,45 @@ scamp_init(UNUSED(const device_t *info)) mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - for (uint8_t c = 0; c < 20; c++) { - dev->ems_struct[c].parent = dev; - dev->ems_struct[c].segment = c; - mem_mapping_add(&dev->ems_mappings[c], - 0xa0000 + c * 0x4000, 0x4000, - scamp_ems_read, NULL, NULL, - scamp_ems_write, NULL, NULL, - ram + 0xa0000 + c * 0x4000, MEM_MAPPING_INTERNAL, (void *) &dev->ems_struct[c]); - dev->mappings[c] = 0xa0000 + c * 0x4000; + for (uint8_t i = 0; i < 12; i++) + dev->ems[i] = (0x000c0000 + (i * EMS_PGSIZE)) >> 14; + + for (uint8_t i = 0; i < 24; i++) + dev->ems[i + 12] = (0x00040000 + (i * EMS_PGSIZE)) >> 14; + + for (uint8_t i = 0; i < 64; i++) { + dev->mem_pages[i].in_ram = 1; + dev->mem_pages[i].virt_addr = i * EMS_PGSIZE; + dev->mem_pages[i].phys_addr = dev->mem_pages[i].virt_addr; + dev->mem_pages[i].mem = ram + dev->mem_pages[i].phys_addr; + + mem_mapping_add(&(dev->mem_mappings[i]), + i * EMS_PGSIZE, EMS_PGSIZE, + scamp_mem_readb, scamp_mem_readw, NULL, + scamp_mem_writeb, scamp_mem_writew, NULL, + dev->mem_pages[i].mem, MEM_MAPPING_INTERNAL, + &(dev->mem_pages[i])); + + if (i < 40) { + mem_mapping_disable(&(dev->mem_mappings[i])); + + scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_READ | MEM_FLAG_WRITE, MEM_FMASK_RW); + } else { + /* This is needed to the state update actually occurs. */ + dev->mem_flags[i] = MEM_FLAG_READ | MEM_FLAG_WRITE; + scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, 0x00, MEM_FMASK_RW); + + if (i >= 60) + scamp_mem_update_state(dev, i * EMS_PGSIZE, EMS_PGSIZE, MEM_FLAG_ROMCS, MEM_FMASK_ROMCS); + } + } + + dev->card_mem = NULL; + + for (uint8_t i = 0; i < 4; i++) { + dev->card_pages[i].virt_addr = i * EMS_PGSIZE; + dev->card_pages[i].phys_addr = dev->card_pages[i].virt_addr; + dev->card_pages[i].mem = dev->card_mem + dev->card_pages[i].phys_addr; } dev->port_92 = device_add(&port_92_device); From 458f7218979790471df07408ec47f0e703eaa3b6 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 23:27:44 +0100 Subject: [PATCH 42/43] The forgotten mem.c/h changes. --- src/include/86box/mem.h | 2 ++ src/mem/mem.c | 48 ++++++++++++++++++++++++++++++----------- 2 files changed, 38 insertions(+), 12 deletions(-) diff --git a/src/include/86box/mem.h b/src/include/86box/mem.h index 87be14d5b..19a331925 100644 --- a/src/include/86box/mem.h +++ b/src/include/86box/mem.h @@ -460,7 +460,9 @@ extern void mem_init(void); extern void mem_close(void); extern void mem_reset(void); extern void mem_remap_top_ex(int kb, uint32_t start); +extern void mem_remap_top_ex_nomid(int kb, uint32_t start); extern void mem_remap_top(int kb); +extern void mem_remap_top_nomid(int kb); extern void umc_smram_recalc(uint32_t start, int set); diff --git a/src/mem/mem.c b/src/mem/mem.c index aafd6223c..d1c6de49d 100644 --- a/src/mem/mem.c +++ b/src/mem/mem.c @@ -3019,8 +3019,8 @@ umc_smram_recalc(uint32_t start, int set) umc_page_recalc(c, set); } -void -mem_remap_top_ex(int kb, uint32_t start) +static void +mem_remap_top_ex_common(int kb, uint32_t start, int mid) { uint32_t c; int offset; @@ -3123,37 +3123,61 @@ mem_remap_top_ex(int kb, uint32_t start) mem_mapping_set_addr(&ram_remapped_mapping2, (start * 1024) + 0x00020000, 0x00020000); mem_mapping_set_exec(&ram_remapped_mapping2, ram + 0x000d0000); - mem_mapping_set_addr(&ram_mid_mapping, 0x000c0000, 0x00010000); - mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000c0000); - mem_mapping_set_addr(&ram_mid_mapping2, 0x000f0000, 0x00010000); - mem_mapping_set_exec(&ram_mid_mapping2, ram + 0x000f0000); + if (mid) { + mem_mapping_set_addr(&ram_mid_mapping, 0x000c0000, 0x00010000); + mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000c0000); + mem_mapping_set_addr(&ram_mid_mapping2, 0x000f0000, 0x00010000); + mem_mapping_set_exec(&ram_mid_mapping2, ram + 0x000f0000); + } } else { mem_mapping_set_addr(&ram_remapped_mapping, start * 1024, size * 1024); mem_mapping_set_exec(&ram_remapped_mapping, ram + start_addr); mem_mapping_disable(&ram_remapped_mapping2); - mem_mapping_set_addr(&ram_mid_mapping, 0x000a0000, 0x00060000); - mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000a0000); - mem_mapping_disable(&ram_mid_mapping2); + if (mid) { + mem_mapping_set_addr(&ram_mid_mapping, 0x000a0000, 0x00060000); + mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000a0000); + mem_mapping_disable(&ram_mid_mapping2); + } } } else { mem_mapping_disable(&ram_remapped_mapping); mem_mapping_disable(&ram_remapped_mapping2); - mem_mapping_set_addr(&ram_mid_mapping, 0x000a0000, 0x00060000); - mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000a0000); - mem_mapping_disable(&ram_mid_mapping2); + if (mid) { + mem_mapping_set_addr(&ram_mid_mapping, 0x000a0000, 0x00060000); + mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000a0000); + mem_mapping_disable(&ram_mid_mapping2); + } } flushmmucache(); } +void +mem_remap_top_ex(int kb, uint32_t start) +{ + mem_remap_top_ex_common(kb, start, 1); +} + +void +mem_remap_top_ex_nomid(int kb, uint32_t start) +{ + mem_remap_top_ex_common(kb, start, 0); +} + void mem_remap_top(int kb) { mem_remap_top_ex(kb, (mem_size >= 1024) ? mem_size : 1024); } +void +mem_remap_top_nomid(int kb) +{ + mem_remap_top_ex_nomid(kb, (mem_size >= 1024) ? mem_size : 1024); +} + void mem_reset_page_blocks(void) { From 1561b43fa9981945e4e638c9a811744608cdc8b2 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 16 Jan 2025 23:28:19 +0100 Subject: [PATCH 43/43] NEAT: A few clean-ups. --- src/chipset/neat.c | 75 +++++++++++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 31 deletions(-) diff --git a/src/chipset/neat.c b/src/chipset/neat.c index 3c9838e06..73bd1b4c2 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -204,12 +204,14 @@ #define RB12_EMSLEN 0xe0 /* EMS memory chunk size */ #define RB12_EMSLEN_SH 5 -#define RAM_FLAG_EMS 0x08 -#define RAM_FLAG_ROMCS 0x04 -#define RAM_FLAG_SHREAD 0x02 -#define RAM_FLAG_SHWRITE 0x01 -#define RAM_FMASK_EMS 0x08 -#define RAM_FMASK_SHADOW 0x07 +#define MEM_FLAG_REMAP 0x10 +#define MEM_FLAG_EMS 0x08 +#define MEM_FLAG_ROMCS 0x04 +#define MEM_FLAG_READ 0x02 +#define MEM_FLAG_WRITE 0x01 +#define MEM_FMASK_REMAP 0x10 +#define MEM_FMASK_EMS 0x08 +#define MEM_FMASK_SHADOW 0x07 typedef struct ram_page_t { int8_t enabled; /* 1=ENABLED */ @@ -220,7 +222,7 @@ typedef struct ram_page_t { } ram_page_t; typedef struct neat_t { - uint8_t ram_flags[32]; + uint8_t mem_flags[32]; uint8_t regs[128]; /* all the CS8221 registers */ uint8_t indx; /* programmed index into registers */ @@ -339,19 +341,22 @@ static void neat_mem_update_state(neat_t *dev, uint32_t addr, uint32_t size, uint8_t new_flags, uint8_t mask) { if ((addr >= 0x00080000) && (addr < 0x00100000) && - ((new_flags ^ dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE]) & mask)) { - dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE] &= ~mask; - dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE] |= new_flags; + ((new_flags ^ dev->mem_flags[(addr - 0x00080000) / EMS_PGSIZE]) & mask)) { + dev->mem_flags[(addr - 0x00080000) / EMS_PGSIZE] &= ~mask; + dev->mem_flags[(addr - 0x00080000) / EMS_PGSIZE] |= new_flags; - new_flags = dev->ram_flags[(addr - 0x00080000) / EMS_PGSIZE]; + new_flags = dev->mem_flags[(addr - 0x00080000) / EMS_PGSIZE]; - if (new_flags & RAM_FLAG_EMS) { - neat_log("neat_mem_update_state(): %08X-%08X: %02X (EMS)\n", addr, addr + size - 1, new_flags); - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } else if (new_flags & RAM_FLAG_ROMCS) { + if (new_flags & MEM_FLAG_ROMCS) { neat_log("neat_mem_update_state(): %08X-%08X: %02X (ROMCS)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_ROMCS | MEM_WRITE_ROMCS); - } else switch (new_flags & (RAM_FLAG_SHREAD | RAM_FLAG_SHWRITE)) { + } else if (new_flags & MEM_FLAG_REMAP) { + neat_log("neat_mem_update_state(): %08X-%08X: %02X (REMAP)\n", addr, addr + size - 1, new_flags); + mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); + } else if (new_flags & MEM_FLAG_EMS) { + neat_log("neat_mem_update_state(): %08X-%08X: %02X (EMS)\n", addr, addr + size - 1, new_flags); + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } else switch (new_flags & (MEM_FLAG_READ | MEM_FLAG_WRITE)) { case 0: neat_log("neat_mem_update_state(): %08X-%08X: %02X (RE | WE)\n", addr, addr + size - 1, new_flags); mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); @@ -384,7 +389,7 @@ shadow_recalc(neat_t *dev) int write = 1; int shadow_reg = REG_RB3 + ((i - 8) >> 3); int shadow_bit = i & 7; - int ram_flags; + int mem_flags; int read; if (i >= 16) { @@ -409,16 +414,16 @@ shadow_recalc(neat_t *dev) read = dev->regs[shadow_reg] & (1 << shadow_bit); write = write && read; - ram_flags = romcs ? RAM_FLAG_ROMCS : 0x00; - ram_flags |= read ? RAM_FLAG_SHREAD : 0x00; - ram_flags |= write ? RAM_FLAG_SHWRITE : 0x00; + mem_flags = romcs ? MEM_FLAG_ROMCS : 0x00; + mem_flags |= read ? MEM_FLAG_READ : 0x00; + mem_flags |= write ? MEM_FLAG_WRITE : 0x00; - if ((ram_flags > 0x00) && !(ram_flags & RAM_FLAG_ROMCS)) + if ((mem_flags > 0x00) && !(mem_flags & MEM_FLAG_ROMCS)) mem_mapping_set_addr(&(dev->shadow[i].mapping), dev->shadow[i].virt_base, EMS_PGSIZE); else mem_mapping_disable(&(dev->shadow[i].mapping)); - neat_mem_update_state(dev, dev->shadow[i].virt_base, EMS_PGSIZE, ram_flags, RAM_FMASK_SHADOW); + neat_mem_update_state(dev, dev->shadow[i].virt_base, EMS_PGSIZE, mem_flags, MEM_FMASK_SHADOW); } } @@ -439,7 +444,7 @@ ems_recalc(neat_t *dev, ram_page_t *ems) /* Update the EMS RAM address for this page. */ mem_mapping_set_exec(&ems->mapping, ram + ems->phys_base); - neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, RAM_FLAG_EMS, RAM_FMASK_EMS); + neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, MEM_FLAG_EMS, MEM_FMASK_EMS); #if NEAT_DEBUG > 1 neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n", @@ -449,7 +454,7 @@ ems_recalc(neat_t *dev, ram_page_t *ems) /* Disable this page. */ mem_mapping_disable(&ems->mapping); - neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, 0x00, RAM_FMASK_EMS); + neat_mem_update_state(dev, ems->virt_base, EMS_PGSIZE, 0x00, MEM_FMASK_EMS); } } @@ -570,11 +575,20 @@ ems_set_handlers(neat_t *dev) ems_recalc_all(dev); } +static void +remap_update_states(neat_t *dev, uint8_t flag) +{ + for (uint8_t i = 0; i < 24; i++) + neat_mem_update_state(dev, 0x000a0000 + (i * EMS_PGSIZE), EMS_PGSIZE, flag, MEM_FMASK_REMAP); +} + static void remap_update(neat_t *dev, uint8_t val) { if (dev->regs[REG_RB7] & RB7_UMAREL) { - mem_remap_top_ex(0, (dev->remap_base >= 1024) ? dev->remap_base : 1024); + mem_remap_top_ex_nomid(0, (dev->remap_base >= 1024) ? dev->remap_base : 1024); + + remap_update_states(dev, 0x00); neat_log("0 kB at %08X\n", ((dev->remap_base >= 1024) ? dev->remap_base : 1024) << 10); } @@ -595,12 +609,11 @@ remap_update(neat_t *dev, uint8_t val) mem_mapping_disable(&ram_high_mapping); if (val & RB7_UMAREL) { - mem_remap_top_ex(384, (dev->remap_base >= 1024) ? dev->remap_base : 1024); + mem_remap_top_ex_nomid(384, (dev->remap_base >= 1024) ? dev->remap_base : 1024); + + remap_update_states(dev, MEM_FLAG_REMAP); neat_log("384 kB at %08X\n", ((dev->remap_base >= 1024) ? dev->remap_base : 1024) << 10); } - - /* Yes, this has to be done on every step because mem_remap_top_ex() reenables it. */ - mem_mapping_disable(&ram_mid_mapping); } static void @@ -672,9 +685,9 @@ neat_write(uint16_t port, uint8_t val, void *priv) val &= RB2_MASK; *reg = (*reg & ~RB2_MASK) | val; if (val & RB2_TOP128) - neat_mem_update_state(dev, 0x00080000, 0x00020000, RAM_FLAG_SHREAD | RAM_FLAG_SHWRITE, RAM_FMASK_SHADOW); + neat_mem_update_state(dev, 0x00080000, 0x00020000, MEM_FLAG_READ | MEM_FLAG_WRITE, MEM_FMASK_SHADOW); else - neat_mem_update_state(dev, 0x00080000, 0x00020000, 0x00, RAM_FMASK_SHADOW); + neat_mem_update_state(dev, 0x00080000, 0x00020000, 0x00, MEM_FMASK_SHADOW); #if NEAT_DEBUG > 1 neat_log("NEAT: RB2=%02x(%02x)\n", val, *reg); #endif