From bdc47bf3eef66ede54d7e6b1d33ea2ad914a477d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 00:38:06 +0000 Subject: [PATCH] start working on the actual graphics objects. Since we figured out the pfifo/ramht/object class crap. --- doc/Memory map (RIVA 128).txt | 81 +++++++++ doc/PFIFO RAMHT RAMRO.txt | 38 +++++ doc/nv3 driver init status.txt | 1 + doc/nv3_object_classes.txt | 37 ++++ doc/nv3_object_classes_driver.txt | 57 +++++++ doc/nv3d3d_t.txt | 161 ++++++++++++++++++ .../86box/nv/classes/vid_nv3_classes.h | 66 +++++++ src/include/86box/nv/vid_nv.h | 21 ++- src/include/86box/nv/vid_nv3.h | 70 +++++++- src/video/CMakeLists.txt | 2 + src/video/nv/nv3/classes/nv3_class_names.c | 63 +++++++ src/video/nv/nv3/nv3_core.c | 1 - src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 1 + src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 10 ++ 15 files changed, 591 insertions(+), 20 deletions(-) create mode 100644 doc/Memory map (RIVA 128).txt create mode 100644 doc/PFIFO RAMHT RAMRO.txt create mode 100644 doc/nv3_object_classes.txt create mode 100644 doc/nv3_object_classes_driver.txt create mode 100644 doc/nv3d3d_t.txt create mode 100644 src/include/86box/nv/classes/vid_nv3_classes.h create mode 100644 src/video/nv/nv3/classes/nv3_class_names.c diff --git a/doc/Memory map (RIVA 128).txt b/doc/Memory map (RIVA 128).txt new file mode 100644 index 000000000..fbfe9074f --- /dev/null +++ b/doc/Memory map (RIVA 128).txt @@ -0,0 +1,81 @@ +Memory map (RIVA 128) + +32 megabytes of MMIO starting at 0x0000000-0x01FFFFFF + +MC (Master Control) 0x00000000-0x00000FFF + Config/Boot 0x00000000-0x000000FF + Master Config 0x00000100-0x00000FFF + Also used to define DMA channel IDs? + +MPU-401 I/O 0x00000330-0x00000331 Probably NV1 leftover, NV1 has mpu401 emulation -- no audio in nv3 +VGA emulated ports 0x000003B0-0x000003DF Emulated I/O ports for VGA + +Bus Control (PBUS) 0x00001000-0x00001FFF +FIFO (PFIFO) 0x00002000-0x00003FFF Submit starting at 0x00800000. Used to configure RAMHT,RAMFC,RAMRO structures & cache + +PRM 0x00004000-0x00005FFF Realmode DOS device support + +PRMIO 0x00007000-0x00007FFF Realmode access to PCI BAR (Base Address Register) + PCI I/O +PTIMER 0x00009000-0x00009FFF Timer + +VGA emulation 0x0000A000-0x0000BFFF + +VGA vram emulation 0x000A0000-0x000BFFFF (PRMVGA) +VGA 0x000C0000-0x000C7FFF VGA sequencer + graph controller registers (PRMVIO) + +(All of this up to 0x0000FFFF can be traced) + +PFB (Framebuffer) 0x00100000-0x00100FFF Interface to vram +PEXTDEV 0x00101000-0x00101FFF External device interface - contains straps + Straps 0x00101000 11 bits of cfg + +ROM (VBIOS?) 0x00110000-0x0011FFFF +PALT (?) 0x00120000-0x00120FFF + +PEXTDEV 0x00101000-0x00101FFF External Devices + +Media Engine (PME) 0x00200000-0x00200FFF Allows for external video capture according to envytools? + +PGRAPH (3D rendering) 0x00400000-0x00401FFF + +PGRAPH objects (using RAMHT???) +*i assume that when you submit an object these are the registers used to actually draw the current object + +Beta blending factor 0x00410000-0x00411FFF +ROP 0x00420000-0x00421FFF Global bitwise operation (Render OPeration) for filtering the final pixel +Color Key 0x00430000-0x00431FFF +Plane Switch 0x00440000-0x00441FFF Something to do with color formats and objects? +Clipping 0x00450000-0x00451FFF +Blend Pattern 0x00460000-0x00461FFF Used for specific blending modes +Quad [OBSOLETE] 0x00470000-0x00471FFF A rectangle. NV1 LEFTOVER, OBSOLETE +Point 0x00480000-0x00481FFF A single point +Line 0x00490000-0x00491FFF A line (with an optional colour). Can also draw a polygon made out of lines - polyline +Lin 0x004A0000-0x004A1FFF A line, without starting or ending pixel (with an optional colour). Can also draw a "polylin" +Triangle [OBSOLETE] 0x004B0000-0x004B1FFF A triangle. NV1 LEFTOVER, OBSOLETE? +Win95 GDI text 0x004C0000-0x004C1FFF Win95 text acceleration +Memory to memory xfer 0x004D0000-0x004D1FFF Represents a memory to memory transfer +Scaled image from vram 0x004E0000-0x004E1FFF Scaled image from GPU VRAM +Image blit from vram 0x00500000-0x00501FFF Image from GPU VRAM +Image blit from cpu 0x00510000-0x00511FFF Image from CPU +Bitmap from cpu 0x00520000-0x00521FFF Bitmap from CPU +Image to memory 0x00540000-0x00541FFF Image to GPU VRAM +Stretch image from cpu 0x00550000-0x00551FFF Stretched image from CPU +Direct3D 5.0 triangle 0x00570000-0x00571FFF A triangle optimised explicitly for directx3/directx5 rendering - supercedes UTRI +PointZ 0x00580000-0x00581FFF A single point with "zeta factor" (not sure what this is yet) +Image in memory 0x005C0000-0x005C0FFF Image in vram(?) + +PVIDEO (Video Control) 0x00680000-0x006802FF +External DAC 0x00680000-0x006800FF + +PRMCIO 0x00601000-0x00601FFF VGA emulation - CRTC + attribute controller + +PRAMDAC 0x00680300-0x00680FFF (used for color lookup tables, hardware cursor, video overlay, PLL for clocking and pixel generation) +"USER" DAC 0x00681200-0x00681FFF + +DMA submission w/FIFO 0x00800000-0x00FFFFFF NV_USER - uses FIFO buffer + +PNVM / PDFB / VRAM 0x01000000-0x017FFFFF (actual VRAM amount depends on card, but max is 8MB) + +RAMIN 0x01C00000-0x01FFFFFF (note that this is actually mapped in the last 1mb of vram) + +contains ramht that has obj parameters for submission, configurable \ No newline at end of file diff --git a/doc/PFIFO RAMHT RAMRO.txt b/doc/PFIFO RAMHT RAMRO.txt new file mode 100644 index 000000000..9b4c94718 --- /dev/null +++ b/doc/PFIFO RAMHT RAMRO.txt @@ -0,0 +1,38 @@ +PIO VS dma + +driver is DIRECTLY modifying pfifo + +8X8 channel setup + +Names are 32-bit integers >4096 + +RAMFC - DMA Context object 0,0 to 8,8 + +context = channel, render object, object type, offset in instance memory + +for a rectangle (type 0x47), object render = 1, channel 0, at 0x0400 in the ramht memory + +=0x00c70400 as the context + +the ramht hash : + +xor every byte of the hash individually and then xor that with the channel number + +so obj id 01020304 in channel 0 is 1 xor 2 xor 3 xor 4 xor 0 + +Store in RAMHT at + 4*16 = name +Store in RAMHT at + 4*16 + 4 = context + +then the ramin stuff starts at *0xc04000 since c00000 is the start of ramin [PCI BAR1] which is where you put the contents of the class struct + +nv_user + +Consider the 8x8 channels as 64 subchannels. +Now you can do: + +They seem to end at 0x880000 + +(0x880000)/64 = 0x2000 for each channel + +FAILURE -> RAMRO! + diff --git a/doc/nv3 driver init status.txt b/doc/nv3 driver init status.txt index 6ac794588..025e781a2 100644 --- a/doc/nv3 driver init status.txt +++ b/doc/nv3 driver init status.txt @@ -105,3 +105,4 @@ NvFindAdapter -> RmInitNvMapping Success 19:18 26/11/2024 NvFindAdapter -> RmPostNvDevice Success 17:32 27/11/2024 NvFindAdapter -> NVGetNVInfo Success 17:32 27/11/2024 NvFindAdapter -> NVMapFrameBuffer Success 17:32 27/11/2024 + diff --git a/doc/nv3_object_classes.txt b/doc/nv3_object_classes.txt new file mode 100644 index 000000000..3cb99882b --- /dev/null +++ b/doc/nv3_object_classes.txt @@ -0,0 +1,37 @@ +Object classes as understood by the GPU. + +(May be represented, in RAMFC, as 0x40+ 22:16) + +0x00 = Invalid +0x01 = beta factor +0x02 = ROP5 operation +0x03 = Chroma key +0x04 = Plane mask +0x05 = Clipping rectangle +0x06 = Pattern +0x07 = Rectangle +0x08 = Point +0x09 = Line +0x0A = Lin (line without starting or ending pixel) +0x0B = Triangle +0x0C = Windows 95 GDI text acceleration +0x0D = Memory to memory format +0x0E = Scaled image from memory +0x0F = INVALID +0x10 = Blit +0x11 = Image +0x12 = Bitmap +0x13 = INVALID +0x14 = Transfer to Memory +0x15 = Stretched image from CPU +0x16 = INVALID +0x17 = Direct3D 5.0 accelerated textured triangle w/zeta buffer +0x18 = INVALID +0x19 = INVALID +0x1A = INVALID +0x1B = INVALID +0x1C = Image in memory +0x1D = INVALID +0x1E = INVALID +0x1F = INVALID + \ No newline at end of file diff --git a/doc/nv3_object_classes_driver.txt b/doc/nv3_object_classes_driver.txt new file mode 100644 index 000000000..83b421335 --- /dev/null +++ b/doc/nv3_object_classes_driver.txt @@ -0,0 +1,57 @@ +Object classes + +NOT represented by the GPU. These are the ones the drivers recognise. Most of them are faked. + +Version 0.77_win95 (!!!) + +object class 1 = "general" methods shared across all objects +object class 2 = DMA from memory +object class 3 = DMA to memory +object class 4 = timer +object class 5 = chip ID +object class 6 = "context ordinal" +object class 10/0Ah = patchcord (links objects together) +object class 11/0Bh = video sink +object class 12/0Ch = video switch +object class 13/0Dh = video colormap +object class 14/0Eh = patchcord...again +object class 15/0Fh = image to video +object class 16/10h = image stencil buffer +object class 17/11h = image blending methods +object class 18/12h = beta solid +object class 19/13h = image -> render operation +object class 20/14h = ROP5 (2^5 = 32bit rop) +object class 21/15h = color key +object class 22/16h = plane switch +object class 23/17h = "solid image" +object class 24/18h = pattern +object class 25/19h = black rectangle +object class 26/1Ah = solid point +object class 27/1Bh = solid line +object class 28/1Ch = solid lin (line without its ending or starting pixel) +object class 29/1Dh = triangle +object class 30/1Eh = solid rectangle +object class 31/1Fh = blit image +object class 33/21h = get image from cpu +object class 34/22h = get image from cpu, monochrome +object class 37/25h = get image from local GPU memory +object class 49/31h and 51/33h = patchcord, again +object class 54/36h = get image from cpu, stretched +object class 55/37h = get image from vram, scaled +object class 56/38h = get image from vram, scaled, YUV 420 color space (probably internal colour space used for rendering) +object class 57/39h = convert image(?) between formats in place in vram, allows you to set an in and out buffer and all that jazz +object class 61/3Dh = In-Memory DMA (vram to vram?) +object class 62/3Eh = get image from vram +object class 63/3Fh = get video from vram +object class 64/40h = video scaler +object class 65/41h = video color key (as opposed to image) +object class 66/42h = capture video to memory +object class 67/43h = Solid ROP5 +object class 68/44h = zeta buffer (something to do with how the gpu internally renders 3d stuff) from CPU(?) +object class 69/45h = zeta buffer in VRAM +object class 70/46h = zeta buffer patchcord +object class 71/47h = render solid point into zeta buffer (Also rectangle0 +object class 72/48h = render Direct3D 5.x ("D3D0") accelerated triangle into zeta buffer +object class 73/49h = render Direct3D 5.x ("D3D0") accelerated triangle +object class 74/4Ah = video source +object class 75/4Bh = render Windows GDI accelerated rectangle and text \ No newline at end of file diff --git a/doc/nv3d3d_t.txt b/doc/nv3d3d_t.txt new file mode 100644 index 000000000..c8579fd6c --- /dev/null +++ b/doc/nv3d3d_t.txt @@ -0,0 +1,161 @@ +12=unk_int12 +16=unk_short16 +22=unk_short22 (seems to determine if nv_sys_ptr is valid) +24=unk_short24 +26=unk_short26 +44=unk_int44 +56=unk_int56 +60=unk_int60 +64=unk_short64 +66=unk_short66 + +82=unk_short82 + +362..822: + big_struct + (weird alignment?) + 477 + 489 + 505 + +1140=nv_sys_ptr + + +1156=unk_int1156 [start of structure] +1160=unk_int1160 + +1168=unk_int1168 [possibly a byte array of up to 16 bytes) + +1184=unk_int1184 + +1208=unk_int1208 +1212=unk_int1212 +1216=unk_int1216 +1220=unk_int1220 +1224=unk_int1224 + +1236=unk_int1236 +1240=unk_int1240 +1244=unk_int1244 +1248=unk_int1248 + +1256=unk_int1256 +1260=fog_table_enable +1264=unk_int1264 +1270=unk_int1270 +1272=unk_byte1272 +1273=unk_byte1273 +1274=unk_byte1274 (?) +1275=unk_byte1275 + +1316=unk_int1316 +1320=unk_int1320 + +1332=unk_int1332 + +1340=unk_int1340 +1344=unk_int1344 + +1356=unk_int1356 +1360=d3d_clear_enabled +1364=texture_enabled +1368=mipmap_size_max +1372=mipmap_levels +1376=user_mipmaps +1380=zoh_mode (bool) +1384=tex_heap +1388=text_size +1392=video_texture +1396=min_video_tex_size +1400=draw_prim +1404=spread_x +1408=spread_y +1412=size_adj +1416=turbo_adj +1420=dma_min_push_count +1424=dma_push_enable + +1436=unk_int1436 +1440=unk_int1440 + +1448=unk_int1448 +1452=unk_int1452 (set to value of unk_int1908) +1456=unk_int1456 (set to value of unk_int1956) +1460=unk_int1460 (set to value of unk_int2020) + +1516=unk_int1516 +1520=unk_int1520 +1524=unk_int1524 +1528=unk_int1528 +1532=unk_int1532 + +1548=unk_int1548 +1552=unk_int1552 +1556=unk_int1556 +1560=unk_int1560 +1564=unk_int1564 + +1600=unk_int1600 + +1612=unk_int1612 +1616=unk_int1616 +1620=unk_int1620 + +1632=unk_int1632 + +1640=unk_int1640 +1644=unk_ptr1644 + +1676=unk_int1676 +1680=unk_int1680 +1684=unk_int1684 +1688=unk_int1688 +1692=unk_int1692 +1696=unk_int1696 +1700=unk_int1700 + +1716=unk_int1716 +1720=unk_int1720 +1724=unk_int1724 +1728=unk_ptr1728 + +1848=unk_int1848 +1852=unk_int1852 +1856=unk_int1856 (unk_int1552 | 0x800) +1864=unk_func_ptr1864 +1868=unk_int1868 + +1884=unk_int1884 +1888=ptr_to_start_of_structure? +1892=hInstDll +1896=unk_int1896 +1900=unk_int1900 + +1908=unk_int1908 +1912=unk_int1912 +1916=unk_func_ptr1916 +1920=unk_func_ptr1920 + +1932=unk_func_ptr1932 +1936=unk_func_ptr1936 +1944=unk_func_ptr1944 + +1956..2020: Set of function pointrs + 1956=unk_int1956 + 1960=unk_int1960 + 1960=unk_func_ptr1960 + 1964=unk_func_ptr1964 + 1968=unk_func_ptr1968 + 1976=unk_func_ptr1976 + 1980=unk_func_ptr1980 + 1988=unk_func_ptr1988 + 1996=unk_func_ptr1996 + 2000=unk_func_ptr2000 + 2004=unk_func_ptr2004 + 2008=unk_func_ptr2008 + + 2020=unk_int2020 + +2024=unk_int2024 +2028=unk_int2028 +2032=unk_int2032 diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h new file mode 100644 index 000000000..e47b5eb71 --- /dev/null +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -0,0 +1,66 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Defines graphics objects for Nvidia NV3 architecture-based GPU (RIVA 128/RIVA 128 ZX), + * as well as for later GPUs if they use the same objects. + * + * + * + * Authors: Connor Hyde + * + * Copyright 2024-2025 Connor Hyde + */ + +#pragma once +#include +#include +#include +#include + +/* + Note: These uint32_ts are basically object methods that are being submitted + They have different names so the user can use them more easily but different versions of the same class can be distinguished + + ALL of these structures HAVE to be a size of exactly 0x2000 bytes because that's what the hashtable expects. + + Also, these class IDs don't relate to the internal architecture of the GPU. + Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of + classes recognised by the driver. + + The 3-bit DMA SUBCHANNEL is combined with a 4-bit CLASS ID to get the REAL CLASS ID. There are 32 CLASSES per subchannel and 8 SUBCHANNELS. + + This is why the Class IDs you see here are not the same as you may see in other places. +*/ + +extern const char* nv3_class_names[]; + +/* +Object Class 0x07 (real hardware) + 0x1E (drivers) +Also 0x47 in context IDs +A rectangle. Wahey! +*/ +typedef struct nv_object_class_007 +{ + uint8_t reserved[0xFF]; // Required for NV_CLASS Core Functionality + uint32_t set_notify_ctx_dma; // Set notifier context for DMA + uint32_t set_notify; // Set notifier + uint32_t set_image_output; // Set the image output type + uint8_t reserved2[0xF5]; // up to 0x200 + uint32_t set_zeta_output; // Zeta buffer input + uint32_t set_zeta_input; // Zeta buffer input + uint32_t set_color_format; // Color format: 0x100000=15bpp. + uint8_t reserved3[0xF5]; // up to 0x300 + + /* THESE ARE ALL THE SAME METHOD */ + uint32_t color_zeta32; // 32-bit zeta buffer color (?) + uint32_t point; // Draw a point i guess + uint8_t reserved4[0x4F3]; // up to 0x7fc + uint32_t control_out; // 7fd-7ff + uint8_t reserved5[0x1800]; // up to 0x2000 +} nv3_rectangle_t; diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index b7450338b..39e9a68d0 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -6,20 +6,23 @@ * * This file is part of the 86Box distribution. * - * JENSEN HUANG APPROVED !!!! + * Shared implementation file for all NVIDIA GPUs (hopefully to be) emulated by 86box. * * Credit to: * - * - fuel (PCBox developer) - * - Marcelina Kościelnicka (envytools) - * - nouveau developers - * - Utah GLX developers - * - XFree86 developers - * - xemu developers - * + * - Marcelina Kościelnicka (envytools) https://envytools.readthedocs.io/en/latest/ + * - fuel (PCBox developer) https://github.com/PCBox/PCBox + * - nouveau developers https://nouveau.freedesktop.org/ + * - Utah GLX developers https://utah-glx.sourceforge.net/ + * - XFree86 developers https://www.xfree86.org/ + * - xemu developers https://github.com/xemu-project/xemu + * - RivaTV developers https://rivatv.sourceforge.net (esp. https://rivatv.sourceforge.net/stuff/riva128.txt) + * - Nvidia for leaking their driver symbols numerous times ;^) https://nvidia.com + * - People who prevented me from giving up (various) + * * Authors: Connor Hyde / starfrost * - * Copyright 2024 Connor Hyde + * Copyright 2024-2025 Connor Hyde */ #ifdef EMU_DEVICE_H // what diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index d185cd408..b17423305 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -12,11 +12,11 @@ * * Authors: Connor Hyde * - * Copyright 2024 Connor Hyde + * Copyright 2024-2025 Connor Hyde */ // vid_nv3.h: NV3 Architecture Hardware Reference (open-source) -// Last updated 2 December 2024 +// Last updated 30 December 2024 // The GPU base structure extern const device_config_t nv3_config[]; @@ -28,13 +28,20 @@ extern const device_config_t nv3_config[]; #define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start #define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN +// DMA channels are basically the number of contexts that the gpu can deal with at once. +// Channel 0 is always taken up by NV drivers. + +// Subchannels deal with specific parts of the GPU and are manipulated by the driver to manipulate the gpu. +#define NV3_DMA_CHANNELS 8 +#define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8 + #define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. // Default value for the boot information register. // Depends on the chip -#define NV3_BOOT_REG_REV_A00 0x00030100 -#define NV3_BOOT_REG_REV_B00 0x00030110 -#define NV3_BOOT_REG_REV_C00 0x00030120 +#define NV3_BOOT_REG_REV_A00 0x00030100 +#define NV3_BOOT_REG_REV_B00 0x00030110 +#define NV3_BOOT_REG_REV_C00 0x00030120 // various vbioses for testing // Coming soon: MIROmagic Premium BIOS (when I get mine dumped) @@ -297,9 +304,9 @@ extern const device_config_t nv3_config[]; #define NV3_PSTRAPS_OVERWRITE_ENABLED 0x1 #define NV3_PEXTDEV_END 0x101FFF #define NV3_PROM_START 0x110000 // VBIOS? -#define NV3_PROM_END 0x110FFF +#define NV3_PROM_END 0x11FFFF #define NV3_PALT_START 0x120000 // ??? but it exists -#define NV3_PALT_END 0x120FFF +#define NV3_PALT_END 0x12FFFF #define NV3_PME_START 0x200000 // Mediaport #define NV3_PME_INTR 0x200100 // Mediaport: Interrupt Pending? #define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable @@ -459,7 +466,7 @@ extern const device_config_t nv3_config[]; #define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC -#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO +#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?) #define NV3_USER_END 0xFFFFFF // easier name @@ -478,6 +485,8 @@ extern const device_config_t nv3_config[]; // these all have configurable sizes, define them here #define NV3_PRAMIN_START 0x1C00000 + + #define NV3_PRAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects #define NV3_PRAMIN_RAMHT_END 0x1C00FFF #define NV3_PRAMIN_RAMHT_SIZE_0 0xFFF @@ -651,8 +660,15 @@ typedef struct nv_pfifo_s { uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable + uint32_t ramht_config; // RAMHT config + uint32_t ramfc_config; // RAMFC config + uint32_t ramro_config; // RAMRO config + uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? + } nv3_pfifo_t; +// create_object(uint32_t type) here + // RAMDAC typedef struct nv3_pramdac_s { @@ -761,12 +777,48 @@ typedef struct nv3_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; +typedef struct nv3_pramin_name_s +{ + union + { + uint32_t name; + uint8_t byte_high; + uint8_t byte_mid2; + uint8_t byte_mid1; + uint8_t byte_low; + }; +} nv3_pramin_name_t; + +typedef struct nv3_pramin_context_s +{ + union + { + uint32_t context; + uint8_t dma_channel; + uint8_t render_object; //0=sw, 1=render + uint8_t class_id; + uint8_t ramin_offset; //find + }; +} nv3_pramin_context_t; + +// Graphics object hashtable for specific DMA [channel, subchannel] pair +typedef struct nv3_pramin_ramht_subchannel_s +{ + nv3_pramin_name_t name; // must be >4096 + + // Contextual information. + // See the above union. + nv3_pramin_context_t context; +} nv3_pramin_ramht_subchannel_t; + // Graphics object hashtable typedef struct nv3_pramin_ramht_s { - + nv3_pramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; } nv3_pramin_ramht_t; +uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel); + // Anti-fuckup device typedef struct nv3_pramin_ramro_s { diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 4b927c9ea..b99f4fc4b 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -41,6 +41,8 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c nv/nv3/subsystems/nv3_ptimer.c nv/nv3/subsystems/nv3_pramin.c nv/nv3/subsystems/nv3_pramin_ramht.c nv/nv3/subsystems/nv3_pramin_ramfc.c nv/nv3/subsystems/nv3_pramin_ramro.c nv/nv3/subsystems/nv3_pvideo.c + + nv/nv3/classes/nv3_class_names.c ) if(G100) diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c new file mode 100644 index 000000000..48b85cab4 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -0,0 +1,63 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Defines core class names for debugging purposes + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ + +/* Taken from Win9x drivers 0.77, these had the best reversing potential */ + +#include <86Box/nv/classes/vid_nv3_classes.h> + + +/* These are the object classes AS RECOGNISED BY THE GRAPHICS HARDWARE. */ +/* The drivers implement a COMPLETELY DIFFERENT SET OF CLASSES. */ + +/* THERE CAN ONLY BE 32 CLASSES IN NV3 BECAUSE THE CLASS ID PART OF THE CONTEXT OF A GRAPHICS OBJECT IN PFIFO RAM HASH TABLE IS ONLY 5 BITS LONG! */ + +const char* nv3_class_names[] = +{ + "NV3 INVALID class 0x00", + "NV3 class 0x01: Beta factor", + "NV3 class 0x02: ROP5 (32-bit) operation", + "NV3 class 0x03: Chroma key", + "NV3 class 0x04: Plane mask", + "NV3 class 0x05: Clipping rectangle", + "NV3 class 0x06: Pattern", + "NV3 class 0x07: Rectangle", + "NV3 class 0x08: Point", + "NV3 class 0x09: Line", + "NV3 class 0x0A: Lin (line without starting or ending pixel)", + "NV3 class 0x0B: Triangle", + "NV3 class 0x0C: Windows 95 GDI text acceleration", + "NV3 class 0x0D: Memory to memory format", + "NV3 class 0x0E: Scaled image from memory", + "NV3 INVALID class 0x0F", + "NV3 class 0x10: Blit", + "NV3 class 0x11: Image", + "NV3 class 0x12: Bitmap", + "NV3 INVALID class 0x13", + "NV3 class 0x14: Transfer to Memory", + "NV3 class 0x15: Stretched image from CPU", + "NV3 INVALID class 0x16", + "NV3 class 0x17: Direct3D 5.0 accelerated textured triangle w/zeta buffer", + "NV3 INVALID class 0x18", + "NV3 INVALID class 0x19", + "NV3 INVALID class 0x1A", + "NV3 INVALID class 0x1B", + "NV3 class 0x1C: Image in Memory", + "NV3 INVALID class 0x1D", + "NV3 INVALID class 0x1E", + "NV3 INVALID class 0x1F", + +}; diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 0636a3c91..e736e0c79 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -614,7 +614,6 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) uint8_t old_value; // todo: - // RMA // Pixel formats (8bit vs 555 vs 565) // VBE 3.0? diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 1ce59171a..57d19fc42 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -28,3 +28,4 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +/* Nvidia DMA Engine */ \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 7448f77c7..08a2b48ff 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -115,7 +115,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) // Write 16-bit ramin void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) { - addr &= (nv3->nvbase.svga.vram_max- 1); + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line svga_t* svga = &nv3->nvbase.svga; diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index 7f80a1035..b77f18729 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -28,3 +28,13 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +/* This implements the hash that all the objects are stored within. +It is used to get the offset within RAMHT of a graphics object. + */ + +uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel) +{ + uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel); + nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)", name, channel); + return hash; +} \ No newline at end of file