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Merge branch 'master' into pc98x1

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TC1995
2025-05-29 20:25:51 +02:00
parent 6d4cbe09cb a1672190a6
commit c26ab74a8a
325 changed files with 21782 additions and 12437 deletions
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21
src/cpu/cpu.c
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@@ -2449,11 +2449,6 @@ cpu_CPUID(void)
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_DE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_CMOV | CPUID_MMX;
/*
Return anything non-zero in bits 32-63 of the BIOS signature MSR
to indicate there has been an update.
*/
msr.bbl_cr_dx[3] = 0xffffffff00000000ULL;
} else
EAX = EBX = ECX = EDX = 0;
break;
@@ -2468,6 +2463,11 @@ cpu_CPUID(void)
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
/*
Return anything non-zero in bits 32-63 of the BIOS signature MSR
to indicate there has been an update.
*/
msr.bbl_cr_dx[3] = 0xffffffff00000000ULL;
} else if (EAX == 2) {
EAX = 0x03020101; /* Instruction TLB: 4 KB pages, 4-way set associative, 32 entries
Instruction TLB: 4 MB pages, fully associative, 2 entries
@@ -2650,6 +2650,12 @@ cpu_ven_reset(void)
case CPU_PENTIUM2:
case CPU_PENTIUM2D:
msr.mtrr_cap = 0x00000508ULL;
/* 4 GB cacheable space on Deschutes 651h and later (including the 1632h
Overdrive) according to the Pentium II Processor Specification Update.
Covington 651h (no L2 cache) reports the same 512 MB value as Klamath. */
if (CPUID >= (!strncmp(cpu_f->internal_name, "celeron", 7) ? 0x660 : 0x651))
msr.bbl_cr_ctl3 |= 0x00300000;
break;
case CPU_CYRIX3S:
@@ -3296,7 +3302,6 @@ pentium_invalid_rdmsr:
case 0x88 ... 0x8b:
EAX = msr.bbl_cr_dx[ECX - 0x88] & 0xffffffff;
EDX = msr.bbl_cr_dx[ECX - 0x88] >> 32;
// EDX |= 0xffffffff;
break;
/* Unknown */
case 0xae:
@@ -4104,7 +4109,7 @@ pentium_invalid_wrmsr:
break;
/* BBL_CR_CTL3 - L2 Cache Control Register 3 */
case 0x11e:
msr.bbl_cr_ctl3 = EAX | ((uint64_t) EDX << 32);
msr.bbl_cr_ctl3 = (msr.bbl_cr_ctl3 & 0x02f00000) | (EAX & ~0x02f00000) | ((uint64_t) EDX << 32);
break;
/* Unknown */
case 0x131:
@@ -4260,7 +4265,7 @@ cpu_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
cyrix_addr = val;
else if (addr < 0xf1) switch (cyrix_addr) {
default:
if (cyrix_addr >= 0xc0)
if ((cyrix_addr >= 0xc0) && (cyrix_addr != 0xff))
fatal("Writing unimplemented Cyrix register %02X\n", cyrix_addr);
break;