diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx
index d43765e80..6fc2aaa74 100644
Binary files a/doc/nvidia_notes/status.xlsx and b/doc/nvidia_notes/status.xlsx differ
diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c
index e006c41f3..a32358912 100644
--- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c
+++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c
@@ -39,6 +39,16 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_
             nv3->pgraph.win95_gdi_text.color_a = param;
             nv_log("Method Execution: GDI-A Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a);
             break;
+        case NV3_W95TXT_B_CLIP_TOPLEFT:
+            nv3->pgraph.win95_gdi_text.clip_b.left = (param & 0xFFFF);
+            nv3->pgraph.win95_gdi_text.clip_b.top = ((param >> 16) & 0xFFFF);
+            nv_log("Method Execution: GDI-B Clip Left,Top %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.left, nv3->pgraph.win95_gdi_text.clip_b.top);
+            break;
+        case NV3_W95TXT_B_CLIP_BOTTOMRIGHT:
+            nv3->pgraph.win95_gdi_text.clip_b.bottom = (param & 0xFFFF);
+            nv3->pgraph.win95_gdi_text.clip_b.right = ((param >> 16) & 0xFFFF);
+            nv_log("Method Execution: GDI-B Clip Bottom,Right %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.left, nv3->pgraph.win95_gdi_text.clip_b.top);
+            break;
         /* Type B and C not implemented YET, as they are not used by NT GDI driver */
         case NV3_W95TXT_D_CLIP_TOPLEFT: 
             nv3->pgraph.win95_gdi_text.clip_d.left = (param & 0xFFFF);
diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c
index 204efaaa2..a365cab62 100644
--- a/src/video/nv/nv3/nv3_core.c
+++ b/src/video/nv/nv3/nv3_core.c
@@ -502,7 +502,7 @@ void nv3_recalc_timings(svga_t* svga)
     uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03;
 
     svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16;
-    
+
     // should these actually use separate values?
     // i don't we should force the top 2 bits to 1...
 
@@ -532,8 +532,18 @@ void nv3_recalc_timings(svga_t* svga)
             svga->render = svga_render_8bpp_highres;
             break;
         case NV3_CRTC_REGISTER_PIXELMODE_16BPP:
+            /* This is some sketchy shit that is an attempt at an educated guess
+            at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, this is what's causing it */
+            if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01)
+            {
+                svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2;
+            }
+            else 
+            {
+                svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3;
+            }
+
             /* sometimes it really renders in 15bpp, so you need to do this */
-            svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2;
             if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01)
             {
                 svga->bpp = 16;
@@ -545,11 +555,14 @@ void nv3_recalc_timings(svga_t* svga)
                 svga->bpp = 15;
                 svga->lowres = 0;
                 svga->render = svga_render_15bpp_highres;
+                
+                // fixes win2000, but breaks 9x?!
             }
         
             break;
         case NV3_CRTC_REGISTER_PIXELMODE_32BPP:
             svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3;
+            
             svga->bpp = 32;
             svga->lowres = 0;
             svga->render = svga_render_32bpp_highres;