From ca6a7c4f37d1a0dce73d80324ea841ff3f26f517 Mon Sep 17 00:00:00 2001
From: starfrost013 <mario64crashed@gmail.com>
Date: Tue, 11 Mar 2025 17:56:25 +0000
Subject: [PATCH] Workaround for 86box dynarec design allowing the riva to
 overwrite old graphics objects.

---
 src/video/nv/nv3/nv3_core.c             | 13 ++++++++++++-
 src/video/nv/nv3/subsystems/nv3_pfifo.c |  8 ++++++--
 src/video/nv/nv3/subsystems/nv3_user.c  |  4 ++++
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c
index 949ce53be..0876f7c89 100644
--- a/src/video/nv/nv3/nv3_core.c
+++ b/src/video/nv/nv3/nv3_core.c
@@ -127,7 +127,14 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv)
     }
 
 
-    return nv3_mmio_arbitrate_read(addr);
+    ret = nv3_mmio_arbitrate_read(addr);
+
+    // This may get around the riva shredding its own cache 
+    //nv3_pfifo_cache0_pull();
+    //nv3_pfifo_cache1_pull();
+
+    return ret; 
+
 }
 
 // Write 8-bit MMIO
@@ -206,6 +213,10 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
     }
 
     nv3_mmio_arbitrate_write(addr, val);
+
+    // This may get around the riva shredding its own cache 
+    //nv3_pfifo_cache0_pull();
+    //nv3_pfifo_cache1_pull();
 }
 
 // PCI stuff
diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c
index 9857afbd7..a9ae7dc61 100644
--- a/src/video/nv/nv3/subsystems/nv3_pfifo.c
+++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c
@@ -267,7 +267,7 @@ uint32_t nv3_pfifo_read(uint32_t address)
 
                     break;
                 
-                /* Cache1 is handled below */
+                /* Cache1 is handled below - cache0 only has one entry */
                 case NV3_PFIFO_CACHE0_CTX:
                     ret = nv3->pfifo.cache0_settings.context[0];
                     break;
@@ -293,7 +293,7 @@ uint32_t nv3_pfifo_read(uint32_t address)
     {
         nv_log("PFIFO Cache0 Read\n");
 
-        if (address & 4)
+        if (address & 4) 
             return nv3->pfifo.cache0_entry.data;
         else
             return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL);
@@ -545,8 +545,12 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
     }
     else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END)
     {
+        // 3104 always written after 3100
         if (address & 4)
+        {   
             nv3->pfifo.cache0_entry.data = val;
+            nv3_pfifo_cache0_pull(); // immediately pull out
+        }
         else
             nv3->pfifo.cache0_entry.method = (val & 0x1FFC);
             nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07;
diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c
index 4361abcd0..a6c9a588c 100644
--- a/src/video/nv/nv3/subsystems/nv3_user.c
+++ b/src/video/nv/nv3/subsystems/nv3_user.c
@@ -66,4 +66,8 @@ uint32_t nv3_user_read(uint32_t address)
 void nv3_user_write(uint32_t address, uint32_t value) 
 {
     nv3_pfifo_cache1_push(address, value);
+
+    // This isn't ideal, but otherwise, the dynarec causes the GPU to write so many objects into CACHE1, it starts overwriting the old objects
+    // This basically makes the fifo not a fifo, but oh well 
+    nv3_pfifo_cache1_pull();
 }
\ No newline at end of file