From ce207fef8520f9b490af44584399c1cc831427d2 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 18:06:57 +0000 Subject: [PATCH] remove some oboslete code --- src/video/nv/nv3/nv3_core.c | 4 ---- src/video/nv/nv3/nv3_core_arbiter.c | 6 +----- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 0876f7c89..c56551b14 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -213,10 +213,6 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) } nv3_mmio_arbitrate_write(addr, val); - - // This may get around the riva shredding its own cache - //nv3_pfifo_cache0_pull(); - //nv3_pfifo_cache1_pull(); } // PCI stuff diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 6e8e2b9a5..17cca15df 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -103,9 +103,6 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) ret = nv3_vram_read(address); else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); - // RAMIN is handled by a separate memory mapping in PCI BAR1 - //else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END) - //ret = nv3_ramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); @@ -167,8 +164,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) nv3_vram_write(address, value); else if (address >= NV3_USER_START && address <= NV3_USER_END) nv3_user_write(address, value); - else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END) - nv3_ramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions + //RAMIN is its own thing else { nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address);