From ce852caee13e778c34681b314757df3fcfde3353 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 26 Mar 2025 16:22:06 +0000 Subject: [PATCH] Clip images. Gate some ridiculous logging beyond ENABLE_NV_LOG_ULTRA. 2MB was real for at least one card, as well. --- .../nv3_class_005_clipping_rectangle.c | 4 +-- .../nv/nv3/classes/nv3_class_011_image.c | 17 ++++++----- src/video/nv/nv3/nv3_core.c | 29 +++++++++++++++---- src/video/nv/nv3/nv3_core_config.c | 5 ++-- src/video/nv/nv3/render/nv3_render_core.c | 5 ++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 7 +++++ 6 files changed, 48 insertions(+), 19 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 10136feac..5ad674b44 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -34,12 +34,12 @@ void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_CLIP_POSITION: nv3->pgraph.clip_start.x = (param >> 16) & 0xFFFF; nv3->pgraph.clip_start.y = (param) & 0xFFFF; - nv_log("Clip Position: %d,%d", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + nv_log("Clip Position: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; case NV3_CLIP_SIZE: nv3->pgraph.clip_size.x = (param >> 16) & 0xFFFF; nv3->pgraph.clip_size.y = (param) & 0xFFFF; - nv_log("Clip Size: %d,%d", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + nv_log("Clip Size: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index b05013f5a..c6aa1aceb 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -72,6 +72,9 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; + /* Some extra data is sent as padding, we need to clip it off using size_out */ + + uint16_t clip_x = nv3->pgraph.image_current_position.x + nv3->pgraph.image.size.w; /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) @@ -81,22 +84,22 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ //pixel3 pixel3 = param & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel2 = (param >> 8) & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel1 = (param >> 16) & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (param >> 24) & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -105,12 +108,12 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case 15: case 16: pixel1 = (param) & 0xFFFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (param >> 16) & 0xFFFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -118,7 +121,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // just one pixel in 32bpp case 32: pixel0 = param; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 09d8e093a..d9ca57ff0 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -68,7 +68,9 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3); - nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x\n", addr, ret); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + #endif return ret; } @@ -94,8 +96,9 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); + #ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - + #endif return ret; } @@ -121,7 +124,9 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x\n", addr, ret); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + #endif return ret; } @@ -146,7 +151,10 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; + #ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + #endif + nv3_svga_out(real_address, val & 0xFF, nv3); return; @@ -172,7 +180,10 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x\n", addr, val); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + #endif + nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -199,7 +210,9 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x\n", addr, val); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + #endif nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -992,7 +1005,7 @@ void nv3_update_mappings() } else { - fatal("NV3-2MB not implemented yet (It never existed anyway)"); + fatal("NV3 2MB not implemented yet"); } } @@ -1038,6 +1051,10 @@ void* nv3_init(const device_t *info) #endif nv_log("Initialising core\n"); +#ifdef ENABLE_NV_LOG_ULTRA + nv_log("ULTRA LOGGING enabled"); +#endif + // Figure out which vbios the user selected const char* vbios_id = device_get_config_bios("vbios"); const char* vbios_file = ""; diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index 256ae9dd9..a229ca3c7 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -144,9 +144,10 @@ const device_config_t nv3_config[] = .selection = { #ifndef RELEASE_BUILD - // This never existed officially but was planned. Debug only + // I thought this was never released, but it seems that at least one was released: + // The card was called the "NEC G7AGK" { - .description = "2 MB (Never officially sold)", + .description = "2 MB", .value = NV3_VRAM_SIZE_2MB, }, #endif diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index d1563cd76..7ae00efd6 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -219,6 +219,7 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj) { uint32_t vram_x = position.x; + uint32_t vram_y = position.y; uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; @@ -236,7 +237,7 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro break; } - uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * position.y) + nv3->pgraph.boffset[current_buffer]; + uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * vram_y) + nv3->pgraph.boffset[current_buffer]; pixel_addr_vram &= nv3->nvbase.svga.vram_mask; @@ -313,7 +314,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob return; } - /* TODO: Chroma Key, Pattern, Plane Mask...*/ + /* TODO: Plane Mask...*/ if (!nv3_render_chroma_test(grobj, color)) return; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index ef6af049e..55ec21e19 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -740,7 +740,9 @@ void nv3_pfifo_cache0_pull() nv3->pfifo.cache0_settings.get_address ^= 0x04; #ifndef RELEASE_BUILD + #ifdef ENABLE_NV_LOG_ULTRA nv_log("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n"); + #endif nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; @@ -936,6 +938,11 @@ void nv3_pfifo_cache1_pull() nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; #ifndef RELEASE_BUILD + + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n"); + #endif + nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; nv3_debug_ramin_print_context_info(current_param, context_structure);