From 8c9dd1d7c872bccd1b13699c89844037fb026740 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dan=20Hor=C3=A1k?= Date: Sat, 26 Nov 2022 16:58:31 +0100 Subject: [PATCH 1/8] fix build for non-dynarec platforms --- src/cpu/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index 58ddf8dc6..0d7858397 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -1170,7 +1170,9 @@ cpu_set(void) if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P)) { x86_opcodes_3DNOW = ops_3DNOWE; +#ifdef USE_DYNAREC x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOWE; +#endif } timing_rr = 1; /* register dest - register src */ From b89c397912f4bafb3974327de2ff9457beeba4eb Mon Sep 17 00:00:00 2001 From: OBattler Date: Sun, 27 Nov 2022 20:49:47 +0100 Subject: [PATCH 2/8] Added a missing break in optimc_read(). --- src/sound/snd_optimc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/sound/snd_optimc.c b/src/sound/snd_optimc.c index 9c3e4c133..d452301db 100644 --- a/src/sound/snd_optimc.c +++ b/src/sound/snd_optimc.c @@ -313,6 +313,7 @@ optimc_reg_read(uint16_t addr, void *p) case 3: /* MC4 */ case 4: /* MC5 */ temp = optimc->regs[addr - 0xF8D]; + break; case 5: /* MC6 */ temp = optimc->regs[5]; break; From f14535b389312d5592900a1599692b949f0f7234 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 28 Nov 2022 15:17:16 +0100 Subject: [PATCH 3/8] There's no need for MC6 readout to be a special case, given that it neatly fits in with the prceding 4 cases. --- src/sound/snd_optimc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/sound/snd_optimc.c b/src/sound/snd_optimc.c index d452301db..b54174ce0 100644 --- a/src/sound/snd_optimc.c +++ b/src/sound/snd_optimc.c @@ -312,10 +312,8 @@ optimc_reg_read(uint16_t addr, void *p) case 1: /* MC2 */ case 3: /* MC4 */ case 4: /* MC5 */ - temp = optimc->regs[addr - 0xF8D]; - break; case 5: /* MC6 */ - temp = optimc->regs[5]; + temp = optimc->regs[addr - 0xF8D]; break; case 2: /* MC3 */ temp = (optimc->regs[2] & ~0x3) | 0x2; From d05d988e349d6a9a2dd2a41b7f9e5ef942643328 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 30 Nov 2022 16:01:33 +0100 Subject: [PATCH 4/8] IDE/ATAPI: Don't overwrite data in packet writes during Phase Data In. Fixes Solaris 2.6 CD installation on ide/atapi. --- src/disk/hdc_ide.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c index a306c5288..2f544cfb9 100644 --- a/src/disk/hdc_ide.c +++ b/src/disk/hdc_ide.c @@ -1150,6 +1150,9 @@ ide_atapi_packet_write(ide_t *ide, uint32_t val, int length) bufferw = (uint16_t *) bufferb; bufferl = (uint32_t *) bufferb; + if (dev->packet_status == PHASE_DATA_IN) + return; + switch (length) { case 1: bufferb[dev->pos] = val & 0xff; From 898eb5c9506d77415623d93d446c273196afa6f0 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 30 Nov 2022 20:16:03 +0100 Subject: [PATCH 5/8] Fixed AHA-1640 MCA write handler I/O address calculation. --- src/scsi/scsi_aha154x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/scsi/scsi_aha154x.c b/src/scsi/scsi_aha154x.c index e7cd02884..669d050bf 100644 --- a/src/scsi/scsi_aha154x.c +++ b/src/scsi/scsi_aha154x.c @@ -519,7 +519,7 @@ aha_mca_write(int port, uint8_t val, void *priv) /* Get the new assigned I/O base address. */ dev->Base = (dev->pos_regs[3] & 7) << 8; - dev->Base |= ((dev->pos_regs[3] & 0xc0) ? 0x34 : 0x30); + dev->Base |= ((dev->pos_regs[3] & 0x40) ? 0x34 : 0x30); /* Save the new IRQ and DMA channel values. */ dev->Irq = (dev->pos_regs[4] & 0x07) + 8; From 136db56b990eeab453de81185130812db41e4a0e Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 30 Nov 2022 20:23:40 +0100 Subject: [PATCH 6/8] Fixed the WD8003 MCA IRQ selection. --- src/network/net_wd8003.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/network/net_wd8003.c b/src/network/net_wd8003.c index cb2d0bc35..c820e7444 100644 --- a/src/network/net_wd8003.c +++ b/src/network/net_wd8003.c @@ -548,7 +548,7 @@ wd_mca_write(int port, uint8_t val, void *priv) dev->base_address = (dev->pos_regs[2] & 0xfe) << 4; dev->ram_addr = (dev->pos_regs[3] & 0xfc) << 12; - dev->irq = irq[dev->pos_regs[5] & 0x02]; + dev->irq = irq[dev->pos_regs[5] & 0x03]; /* Initialize the device if fully configured. */ /* Register (new) I/O handler. */ From 6e3ffea3d483ecb9a49381ddfe94c23a1e0c57d2 Mon Sep 17 00:00:00 2001 From: Alexander Babikov <2708460+lemondrops@users.noreply.github.com> Date: Thu, 1 Dec 2022 22:33:55 +0500 Subject: [PATCH 7/8] Add the CR4 Page Global Enable bit support to Pentium Pro and Pentium II CPUs --- src/cpu/cpu.c | 9 +++++---- src/cpu/cpu.h | 1 + src/cpu/x86_ops_mov_ctrl.h | 4 ++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index 0d7858397..d667c743e 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -61,6 +61,7 @@ enum { CPUID_AMDSEP = (1 << 10), CPUID_SEP = (1 << 11), CPUID_MTRR = (1 << 12), + CPUID_PGE = (1 << 13), CPUID_MCA = (1 << 14), CPUID_CMOV = (1 << 15), CPUID_MMX = (1 << 23), @@ -1298,7 +1299,7 @@ cpu_set(void) if (cpu_s->cpu_type >= CPU_PENTIUM2) cpu_features |= CPU_FEATURE_MMX; msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21); - cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PAE | CR4_PCE; + cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PAE | CR4_PCE | CR4_PGE; if (cpu_s->cpu_type == CPU_PENTIUM2D) cpu_CR4_mask |= CR4_OSFXSR; @@ -1959,7 +1960,7 @@ cpu_CPUID(void) } else if (EAX == 1) { EAX = CPUID; EBX = ECX = 0; - EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_MCA | CPUID_SEP | CPUID_CMOV; + EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV; } else if (EAX == 2) { EAX = 0x00000001; EBX = ECX = 0; @@ -1977,7 +1978,7 @@ cpu_CPUID(void) } else if (EAX == 1) { EAX = CPUID; EBX = ECX = 0; - EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_MCA | CPUID_SEP | CPUID_CMOV; + EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV; } else if (EAX == 2) { EAX = 0x00000001; EBX = ECX = 0; @@ -1995,7 +1996,7 @@ cpu_CPUID(void) } else if (EAX == 1) { EAX = CPUID; EBX = ECX = 0; - EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_MCA | CPUID_SEP | CPUID_FXSR | CPUID_CMOV; + EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_FXSR | CPUID_CMOV; } else if (EAX == 2) { EAX = 0x00000001; EBX = ECX = 0; diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h index 11e1bc93c..a28618fe1 100644 --- a/src/cpu/cpu.h +++ b/src/cpu/cpu.h @@ -195,6 +195,7 @@ typedef struct { #define CR4_PVI (1 << 1) #define CR4_PSE (1 << 4) #define CR4_PAE (1 << 5) +#define CR4_PGE (1 << 7) #define CPL ((cpu_state.seg_cs.access >> 5) & 3) diff --git a/src/cpu/x86_ops_mov_ctrl.h b/src/cpu/x86_ops_mov_ctrl.h index 0cfa38095..d28033d5d 100644 --- a/src/cpu/x86_ops_mov_ctrl.h +++ b/src/cpu/x86_ops_mov_ctrl.h @@ -148,7 +148,7 @@ opMOV_CRx_r_a16(uint32_t fetchdat) break; case 4: if (cpu_has_feature(CPU_FEATURE_CR4)) { - if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & CR4_PAE) + if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & (CR4_PAE | CR4_PGE)) flushmmucache(); cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask; break; @@ -205,7 +205,7 @@ opMOV_CRx_r_a32(uint32_t fetchdat) break; case 4: if (cpu_has_feature(CPU_FEATURE_CR4)) { - if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & CR4_PAE) + if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & (CR4_PAE | CR4_PGE)) flushmmucache(); cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask; break; From 910265d670d01c740191a7e810d6fcb827a5a23a Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 1 Dec 2022 19:02:58 +0100 Subject: [PATCH 8/8] Initialize the BusLogic geometry register to have bit 4 set, fixes older versions of BTDOSM.SYS/BTCDROM.SYS. --- src/scsi/scsi_x54x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/scsi/scsi_x54x.c b/src/scsi/scsi_x54x.c index 6cac77e02..45854a0ba 100644 --- a/src/scsi/scsi_x54x.c +++ b/src/scsi/scsi_x54x.c @@ -1402,7 +1402,7 @@ x54x_reset(x54x_t *dev) clear_irq(dev); if (dev->flags & X54X_INT_GEOM_WRITABLE) - dev->Geometry = 0x80; + dev->Geometry = 0x90; else dev->Geometry = 0x00; dev->callback_phase = 0;