diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 71c636c78..79a420243 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -48,20 +48,20 @@ void nv_log(const char *fmt, ...); #define NV_PCI_NUM_CFG_REGS 256 // number of pci config registers // 0x0000 was probably the NV0 'Nvidia Hardware Simulator' -#define PCI_DEVICE_NV1 0x0008 // Nvidia NV1 -#define PCI_DEVICE_NV1_VGA 0x0009 // Nvidia NV1 VGA core -#define PCI_DEVICE_NV2 0x0010 // Nvidia NV2 / Mutara V08 (cancelled) -#define PCI_DEVICE_NV3 0x0018 // Nvidia NV3 (Riva 128) -#define PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) -#define PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) +#define NV_PCI_DEVICE_NV1 0x0008 // Nvidia NV1 +#define NV_PCI_DEVICE_NV1_VGA 0x0009 // Nvidia NV1 VGA core +#define NV_PCI_DEVICE_NV2 0x0010 // Nvidia NV2 / Mutara V08 (cancelled) +#define NV_PCI_DEVICE_NV3 0x0018 // Nvidia NV3 (Riva 128) +#define NV_PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) +#define NV_PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) -#define CHIP_REVISION_NV1_A0 0x0000 // 1994 -#define CHIP_REVISION_NV1_B0 0x0010 // 1995 -#define CHIP_REVISION_NV1_C0 0x0020 // +#define NV_CHIP_REVISION_NV1_A0 0x0000 // 1994 +#define NV_CHIP_REVISION_NV1_B0 0x0010 // 1995 +#define NV_CHIP_REVISION_NV1_C0 0x0020 // 1995-96? -#define CHIP_REVISION_NV3_A0 0x0000 // January 1997 -#define CHIP_REVISION_NV3_B0 0x0010 // October 1997 -#define CHIP_REVISION_NV3_C0 0x0020 // 1998 +#define NV_CHIP_REVISION_NV3_A0 0x0000 // January 1997 +#define NV_CHIP_REVISION_NV3_B0 0x0010 // October 1997 +#define NV_CHIP_REVISION_NV3_C0 0x0020 // 1998 // Architecture IDs #define NV_ARCHITECTURE_NV1 1 // NV1/STG2000 diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index ea886476d..30926020a 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -131,11 +131,13 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; + + // IN THIS ONE SPECIFIC PLACE, ****AND ONLY THIS ONE SPECIFIC PLACE****, X AND Y ARE SWAPPED???? */ // If the size is submitted, render it. if (method_id & 0x04) { - nv3->pgraph.win95_gdi_text.rect_a_size[index].w = param & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_size[index].h = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].w = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].h = param & 0xFFFF; nv_log("Method Execution: Rect GDI-A%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, nv3->pgraph.win95_gdi_text.rect_a_size[index].h, nv3->pgraph.win95_gdi_text.color_a); @@ -145,8 +147,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } else // position { - nv3->pgraph.win95_gdi_text.rect_a_position[index].x = param & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_position[index].y = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_position[index].x = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_position[index].y = param & 0xFFFF; nv_log("Method Execution: Rect GDI-A%d Position=%d,%d\n", index, nv3->pgraph.win95_gdi_text.rect_a_position[index].x, nv3->pgraph.win95_gdi_text.rect_a_position[index].y); diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 57184054d..7bae42184 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -54,7 +54,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y) return; - nv3_render_blit_screen2screen(grobj); + //nv3_render_blit_screen2screen(grobj); break; default: diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 1718b4e7f..5bab81bc4 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -27,6 +27,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> +/* Main device object pointer */ nv3_t* nv3; /* These are a ****PLACEHOLDER**** and are copied from 3dfx VoodooBanshee/Voodoo3*/ @@ -257,11 +258,11 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) // device id case NV3_PCI_CFG_DEVICE_ID: - ret = (PCI_DEVICE_NV3 & 0xFF); + ret = (NV_PCI_DEVICE_NV3 & 0xFF); break; case NV3_PCI_CFG_DEVICE_ID+1: - ret = (PCI_DEVICE_NV3 >> 8); + ret = (NV_PCI_DEVICE_NV3 >> 8); break; // various capabilities @@ -498,6 +499,7 @@ void nv3_recalc_timings(svga_t* svga) return; nv3_t* nv3 = (nv3_t*)svga->priv; + uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03; svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; @@ -506,18 +508,22 @@ void nv3_recalc_timings(svga_t* svga) // i don't we should force the top 2 bits to 1... // required for VESA resolutions, force parameters higher + // only fuck around with any of this in VGAmode? - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; - - if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) - svga->hdisp += 0x100; // large screen bit + if (pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA) + { + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) + svga->hdisp += 0x100; // large screen bit + } + // Set the pixel mode - switch (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03) + switch (pixel_mode) { case NV3_CRTC_REGISTER_PIXELMODE_8BPP: svga->bpp = 8; diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 9da3f05b1..032b23b47 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -55,7 +55,7 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) /* Some extra data is sent as padding, we need to clip it off using size_out */ - uint16_t clip_x = nv3->pgraph.image_current_position.x + nv3->pgraph.image.size.w; + uint16_t clip_x = nv3->pgraph.image.point.x + nv3->pgraph.image.size.w; /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) @@ -89,12 +89,12 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) case 15: case 16: pixel1 = (color) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + if (nv3->pgraph.image_current_position.x < (clip_x)) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (color >> 16) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < (clip_x)) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds();