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More cleanups

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This commit is contained in:
Jasmine Iwanek
2022-09-16 22:00:54 -04:00
parent e5324a0928
commit de7af0fe7e
6 changed files with 44 additions and 41 deletions
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18
src/device/keyboard_at.c
View File

@@ -1088,15 +1088,15 @@ write_output(atkbd_t *dev, uint8_t val)
/* 0 holds the CPU in the RESET state, 1 releases it. To simplify this,
we just do everything on release. */
if ((old ^ val) & 0x01) { /*Reset*/
if (! (val & 0x01)) { /* Pin 0 selected. */
/* Pin 0 selected. */
kbd_log("write_output(): Pulse reset!\n");
softresetx86(); /*Pulse reset!*/
cpu_set_edx();
flushmmucache();
if (kbc_ven == KBC_VEN_ALI)
smbase = 0x00030000;
}
if (! (val & 0x01)) { /* Pin 0 selected. */
/* Pin 0 selected. */
kbd_log("write_output(): Pulse reset!\n");
softresetx86(); /*Pulse reset!*/
cpu_set_edx();
flushmmucache();
if (kbc_ven == KBC_VEN_ALI)
smbase = 0x00030000;
}
}
/* Do this here to avoid an infinite reset loop. */

30
src/device/pci_bridge.c
View File

@@ -462,10 +462,10 @@ pci_bridge_reset(void *priv)
dev->regs[0x07] = dev->regs[0x08] = 0x02;
break;
case AGP_BRIDGE_INTEL_815EP:
dev->regs[0x06] = 0x20;
dev->regs[0x08] = 0x02;
break;
case AGP_BRIDGE_INTEL_815EP:
dev->regs[0x06] = 0x20;
dev->regs[0x08] = 0x02;
break;
case AGP_BRIDGE_VIA_597:
case AGP_BRIDGE_VIA_598:
@@ -535,25 +535,25 @@ pci_bridge_init(const device_t *info)
interrupt_count = sizeof(interrupts);
interrupt_mask = interrupt_count - 1;
if (dev->slot < 32) {
for (i = 0; i < interrupt_count; i++)
interrupts[i] = pci_get_int(dev->slot, PCI_INTA + i);
for (i = 0; i < interrupt_count; i++)
interrupts[i] = pci_get_int(dev->slot, PCI_INTA + i);
}
pci_bridge_log("PCI Bridge %d: upstream bus %02X slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, (dev->slot >> 5) & 0xff, dev->slot & 31, interrupts[0], interrupts[1], interrupts[2], interrupts[3]);
if (info->local == PCI_BRIDGE_DEC_21150)
slot_count = 9; /* 9 bus masters */
slot_count = 9; /* 9 bus masters */
else
slot_count = 1; /* AGP bridges always have 1 slot */
slot_count = 1; /* AGP bridges always have 1 slot */
for (i = 0; i < slot_count; i++) {
/* Interrupts for bridge slots are assigned in round-robin: ABCD, BCDA, CDAB and so on. */
pci_bridge_log("PCI Bridge %d: downstream slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, i, interrupts[i & interrupt_mask], interrupts[(i + 1) & interrupt_mask], interrupts[(i + 2) & interrupt_mask], interrupts[(i + 3) & interrupt_mask]);
pci_register_bus_slot(dev->bus_index, i, AGP_BRIDGE(dev->local) ? PCI_CARD_AGP : PCI_CARD_NORMAL,
interrupts[i & interrupt_mask],
interrupts[(i + 1) & interrupt_mask],
interrupts[(i + 2) & interrupt_mask],
interrupts[(i + 3) & interrupt_mask]);
/* Interrupts for bridge slots are assigned in round-robin: ABCD, BCDA, CDAB and so on. */
pci_bridge_log("PCI Bridge %d: downstream slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, i, interrupts[i & interrupt_mask], interrupts[(i + 1) & interrupt_mask], interrupts[(i + 2) & interrupt_mask], interrupts[(i + 3) & interrupt_mask]);
pci_register_bus_slot(dev->bus_index, i, AGP_BRIDGE(dev->local) ? PCI_CARD_AGP : PCI_CARD_NORMAL,
interrupts[i & interrupt_mask],
interrupts[(i + 1) & interrupt_mask],
interrupts[(i + 2) & interrupt_mask],
interrupts[(i + 3) & interrupt_mask]);
}
}

26
src/device/smbus_piix4.c
View File

@@ -244,26 +244,26 @@ smbus_piix4_write(uint16_t addr, uint8_t val, void *priv)
/* fall-through */
case 0xd: /* I2C block R/W */
if (dev->local == SMBUS_INTEL_ICH2) {
if (dev->local == SMBUS_INTEL_ICH2) {
if (!dev->byte_rw) {
i2c_write(i2c_smbus, smbus_addr, dev->cmd);
if(read)
dev->data0 = i2c_read(i2c_smbus, smbus_addr); // For byte reads, the count is recieved and stored at the DATA0 register
dev->data0 = i2c_read(i2c_smbus, smbus_addr); // For byte reads, the count is recieved and stored at the DATA0 register
else
i2c_write(i2c_smbus, smbus_addr, dev->data0);
dev->byte_rw = 1;
}
dev->byte_rw = 1;
}
if (read) {
dev->block_data_byte = i2c_read(i2c_smbus, smbus_addr);
dev->stat |= 0x80;
if (read) {
dev->block_data_byte = i2c_read(i2c_smbus, smbus_addr);
dev->stat |= 0x80;
smbus_piix4_raise_smi(dev);
if(dev->ctl & 0x20) { /* Finish the Transfer */
dev->byte_rw = 0;
dev->stat |= 2;
}
}
}
else {
i2c_write(i2c_smbus, smbus_addr, dev->cmd);
if (((dev->byte_rw >> 4) & 0xff) < dev->data0) {
@@ -273,8 +273,8 @@ smbus_piix4_write(uint16_t addr, uint8_t val, void *priv)
}
else dev->byte_rw = 0;
}
}
else {
}
else {
if (read) {
timer_bytes++;
/* block read [data0] (I2C) or [first byte] (SMBus) bytes */
@@ -372,9 +372,9 @@ unknown_protocol:
if (dev->local == SMBUS_INTEL_ICH2)
dev->block_data_byte = val;
else {
dev->data[dev->index++] = val;
if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
dev->index = 0;
dev->data[dev->index++] = val;
if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
dev->index = 0;
}
break;
}