diff --git a/src/acpi.c b/src/acpi.c
index e3dc2f970..9daf9c32b 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -372,66 +372,66 @@ acpi_reg_read_intel_ich2(int size, uint16_t addr, void *p)
     shift32 = (addr & 3) << 3;
 
     switch (addr) {
-    case 0x10: case 0x11: case 0x12: case 0x13:
-		/* PROC_CNT—Processor Control Register */
-        ret = (dev->regs.pcntrl >> shift32) & 0xff;
-        break;
-	case 0x28: case 0x29:
-		/* GPE0_STS—General Purpose Event 0 Status Register */
-		ret = (dev->regs.gpsts >> shift16) & 0xff;
-		break;
-	case 0x2a: case 0x2b:
-		/* GPE0_EN—General Purpose Event 0 Enables Register */
-		ret = (dev->regs.gpen >> shift16) & 0xff;
-		break;
-	case 0x2c: case 0x2d:
-		/* GPE1_STS—General Purpose Event 1 Status Register */
-		ret = (dev->regs.gpsts1 >> shift16) & 0xff;
-		break;
-	case 0x2e: case 0x2f:
-		/* GPE1_EN—General Purpose Event 1 Enable Register */
-		ret = (dev->regs.gpen1 >> shift16) & 0xff;
-		break;
-    case 0x30: case 0x31: case 0x32: case 0x33:
-		/* SMI_EN—SMI Control and Enable Register */
-		ret = (dev->regs.smi_en >> shift32) & 0xff;
-		break;
-    case 0x34: case 0x35: case 0x36: case 0x37:
-		/* SMI_STS—SMI Status Register */
-		ret = (dev->regs.smi_sts >> shift32) & 0xff;
-		break;
-	case 0x40: case 0x41:
-		/* MON_SMI—Device Monitor SMI Status and Enable Register */
-		ret = (dev->regs.mon_smi >> shift16) & 0xff;
-		break;
-	case 0x44: case 0x45:
-		/* DEVACT_STS—Device Activity Status Register */
-		ret = (dev->regs.devact_sts >> shift16) & 0xff;
-		break;
-	case 0x48: case 0x49:
-		/* DEVTRAP_EN—Device Trap Enable Register */
-		ret = (dev->regs.devtrap_en >> shift16) & 0xff;
-		break;
-    case 0x4c ... 0x4d:
-        /* BUS_ADDR_TRACK—Bus Address Tracker Register */
-        ret = (dev->regs.bus_addr_track >> shift16) & 0xff;
-        break;
-    case 0x4e:
-        /* BUS_CYC_TRACK—Bus Cycle Tracker Register */
-        ret = dev->regs.bus_cyc_track;
-        break;
-    case 0x60 ... 0x70:
-        /* TCO Registers */
-        ret = tco_read(addr, dev->tco);
-        break;
-	default:
-		ret = acpi_reg_read_common_regs(size, addr, p);
-		break;
+        case 0x10: case 0x11: case 0x12: case 0x13:
+            /* PROC_CNT—Processor Control Register */
+            ret = (dev->regs.pcntrl >> shift32) & 0xff;
+            break;
+        case 0x28: case 0x29:
+            /* GPE0_STS—General Purpose Event 0 Status Register */
+            ret = (dev->regs.gpsts >> shift16) & 0xff;
+            break;
+        case 0x2a: case 0x2b:
+            /* GPE0_EN—General Purpose Event 0 Enables Register */
+            ret = (dev->regs.gpen >> shift16) & 0xff;
+            break;
+        case 0x2c: case 0x2d:
+            /* GPE1_STS—General Purpose Event 1 Status Register */
+            ret = (dev->regs.gpsts1 >> shift16) & 0xff;
+            break;
+        case 0x2e: case 0x2f:
+            /* GPE1_EN—General Purpose Event 1 Enable Register */
+            ret = (dev->regs.gpen1 >> shift16) & 0xff;
+            break;
+        case 0x30: case 0x31: case 0x32: case 0x33:
+            /* SMI_EN—SMI Control and Enable Register */
+            ret = (dev->regs.smi_en >> shift32) & 0xff;
+            break;
+        case 0x34: case 0x35: case 0x36: case 0x37:
+            /* SMI_STS—SMI Status Register */
+            ret = (dev->regs.smi_sts >> shift32) & 0xff;
+            break;
+        case 0x40: case 0x41:
+            /* MON_SMI—Device Monitor SMI Status and Enable Register */
+            ret = (dev->regs.mon_smi >> shift16) & 0xff;
+            break;
+        case 0x44: case 0x45:
+            /* DEVACT_STS—Device Activity Status Register */
+            ret = (dev->regs.devact_sts >> shift16) & 0xff;
+            break;
+        case 0x48: case 0x49:
+            /* DEVTRAP_EN—Device Trap Enable Register */
+            ret = (dev->regs.devtrap_en >> shift16) & 0xff;
+            break;
+        case 0x4c ... 0x4d:
+            /* BUS_ADDR_TRACK—Bus Address Tracker Register */
+            ret = (dev->regs.bus_addr_track >> shift16) & 0xff;
+            break;
+        case 0x4e:
+            /* BUS_CYC_TRACK—Bus Cycle Tracker Register */
+            ret = dev->regs.bus_cyc_track;
+            break;
+        case 0x60 ... 0x70:
+            /* TCO Registers */
+            ret = tco_read(addr, dev->tco);
+            break;
+        default:
+            ret = acpi_reg_read_common_regs(size, addr, p);
+            break;
     }
 
 #ifdef ENABLE_ACPI_LOG
     // if (size != 1)
-		// acpi_log("(%i) ACPI Read  (%i) %02X: %02X\n", in_smm, size, addr, ret);
+        // acpi_log("(%i) ACPI Read  (%i) %02X: %02X\n", in_smm, size, addr, ret);
 #endif
     return ret;
 }
@@ -898,86 +898,85 @@ acpi_reg_write_intel_ich2(int size, uint16_t addr, uint8_t val, void *p)
     addr &= 0x7f;
 #ifdef ENABLE_ACPI_LOG
     if (size != 1)
-	acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);
+        acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);
 #endif
     shift16 = (addr & 1) << 3;
     shift32 = (addr & 3) << 3;
 
     switch (addr) {
-    case 0x10: case 0x11: case 0x12: case 0x13:
-		/* PROC_CNT—Processor Control Register */
-        dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x000201fe;
-        break;
-	case 0x28: case 0x29:
-		/* GPE0_STS—General Purpose Event 0 Status Register */
-		dev->regs.gpsts &= ~((val << shift16) & 0x09fb);
-		break;
-	case 0x2a: case 0x2b:
-		/* GPE0_EN—General Purpose Event 0 Enables Register */
-		dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
-		break;
-	case 0x2c: case 0x2d:
-		/* GPE1_STS—General Purpose Event 1 Status Register */
-		dev->regs.gpsts1 &= ~((val << shift16) & 0x09fb);
-		break;
-	case 0x2e: case 0x2f:
-		/* GPE1_EN—General Purpose Event 1 Enable Register */
-		dev->regs.gpen1 = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
-		break;
-    case 0x30: case 0x31: case 0x32: case 0x33:
-		/* SMI_EN—SMI Control and Enable Register */
-		dev->regs.smi_en = ((dev->regs.smi_en & ~(0xff << shift32)) | (val << shift32)) & 0x0000867f;
+        case 0x10: case 0x11: case 0x12: case 0x13:
+            /* PROC_CNT—Processor Control Register */
+            dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x000201fe;
+            break;
+        case 0x28: case 0x29:
+            /* GPE0_STS—General Purpose Event 0 Status Register */
+            dev->regs.gpsts &= ~((val << shift16) & 0x09fb);
+            break;
+        case 0x2a: case 0x2b:
+            /* GPE0_EN—General Purpose Event 0 Enables Register */
+           dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
+            break;
+        case 0x2c: case 0x2d:
+            /* GPE1_STS—General Purpose Event 1 Status Register */
+            dev->regs.gpsts1 &= ~((val << shift16) & 0x09fb);
+            break;
+        case 0x2e: case 0x2f:
+            /* GPE1_EN—General Purpose Event 1 Enable Register */
+            dev->regs.gpen1 = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
+            break;
+        case 0x30: case 0x31: case 0x32: case 0x33:
+            /* SMI_EN—SMI Control and Enable Register */
+            dev->regs.smi_en = ((dev->regs.smi_en & ~(0xff << shift32)) | (val << shift32)) & 0x0000867f;
 
-        if(addr == 0x30) {
-            apm_set_do_smi(dev->apm, !!(val & 0x20));
+            if(addr == 0x30) {
+                apm_set_do_smi(dev->apm, !!(val & 0x20));
 
-            if(val & 0x80) {
-                dev->regs.glbsts |= 0x0020;
-                acpi_update_irq(dev);
+                if(val & 0x80) {
+                    dev->regs.glbsts |= 0x0020;
+                    acpi_update_irq(dev);
+                }
+            }
+            break;
+        case 0x34: case 0x35: case 0x36: case 0x37:
+            /* SMI_STS—SMI Status Register */
+            dev->regs.smi_sts &= ~((val << shift32) & 0x0001ff7c);
+            break;
+        case 0x40: case 0x41:
+            /* MON_SMI—Device Monitor SMI Status and Enable Register */
+            dev->regs.mon_smi = ((dev->regs.mon_smi & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
+            break;
+        case 0x44: case 0x45:
+            /* DEVACT_STS—Device Activity Status Register */
+            dev->regs.devact_sts &= ~((val << shift16) & 0x3fef);
+            break;
+        case 0x48: case 0x49:
+            /* DEVTRAP_EN—Device Trap Enable Register */
+            dev->regs.devtrap_en = ((dev->regs.devtrap_en & ~(0xff << shift16)) | (val << shift16)) & 0x3c2f;
+            if (dev->trap_update)
+                dev->trap_update(dev->trap_priv);
+            break;
+        case 0x4c ... 0x4d:
+            /* BUS_ADDR_TRACK—Bus Address Tracker Register */
+            dev->regs.bus_addr_track = ((dev->regs.bus_addr_track & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
+            break;
+        case 0x4e:
+            /* BUS_CYC_TRACK—Bus Cycle Tracker Register */
+            dev->regs.bus_cyc_track = val;
+            break;
+        case 0x60 ... 0x70:
+            /* TCO Registers */
+            tco_write(addr, val, dev->tco);
+            break;
+        default:
+            acpi_reg_write_common_regs(size, addr, val, p);
+            if((addr == 0x04) && !!(val & 4) && !!(dev->regs.smi_en & 4)) {
+                dev->regs.smi_sts = 0x00000004;
+                acpi_raise_smi(dev, 1);
             }
-        }
-		break;
-    case 0x34: case 0x35: case 0x36: case 0x37:
-		/* SMI_STS—SMI Status Register */
-		dev->regs.smi_sts &= ~((val << shift32) & 0x0001ff7c);
-		break;
-	case 0x40: case 0x41:
-		/* MON_SMI—Device Monitor SMI Status and Enable Register */
-		dev->regs.mon_smi = ((dev->regs.mon_smi & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
-		break;
-	case 0x44: case 0x45:
-		/* DEVACT_STS—Device Activity Status Register */
-		dev->regs.devact_sts &= ~((val << shift16) & 0x3fef);
-		break;
-	case 0x48: case 0x49:
-		/* DEVTRAP_EN—Device Trap Enable Register */
-		dev->regs.devtrap_en = ((dev->regs.devtrap_en & ~(0xff << shift16)) | (val << shift16)) & 0x3c2f;
-		if (dev->trap_update)
-			dev->trap_update(dev->trap_priv);
-		break;
-    case 0x4c ... 0x4d:
-        /* BUS_ADDR_TRACK—Bus Address Tracker Register */
-        dev->regs.bus_addr_track = ((dev->regs.bus_addr_track & ~(0xff << shift16)) | (val << shift16)) & 0x097d;
-        break;
-    case 0x4e:
-        /* BUS_CYC_TRACK—Bus Cycle Tracker Register */
-        dev->regs.bus_cyc_track = val;
-        break;
-    case 0x60 ... 0x70:
-        /* TCO Registers */
-        tco_write(addr, val, dev->tco);
-        break;
-	default:
-		acpi_reg_write_common_regs(size, addr, val, p);
-        if((addr == 0x04) && !!(val & 4) && !!(dev->regs.smi_en & 4)) {
-            dev->regs.smi_sts = 0x00000004;
-            acpi_raise_smi(dev, 1);
-        }
 
-        if((addr == 0x02) || !!(val & 0x20) || !!(dev->regs.glbsts & 0x0020))
-            acpi_update_irq(dev);
-
-        break;
+            if((addr == 0x02) || !!(val & 0x20) || !!(dev->regs.glbsts & 0x0020))
+                acpi_update_irq(dev);
+            break;
     }
 }
 
diff --git a/src/chipset/intel_815ep.c b/src/chipset/intel_815ep.c
index 61a29f861..19008ac20 100644
--- a/src/chipset/intel_815ep.c
+++ b/src/chipset/intel_815ep.c
@@ -47,20 +47,19 @@ intel_815ep_log(const char *fmt, ...)
     va_list ap;
 
     if (intel_815ep_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define intel_815ep_log(fmt, ...)
+#    define intel_815ep_log(fmt, ...)
 #endif
 
-typedef struct intel_815ep_t
-{
-    uint8_t pci_conf[256];
+typedef struct intel_815ep_t {
+    uint8_t  pci_conf[256];
     smram_t *lsmm_segment, *h_segment, *usmm_segment;
-    void *agpgart;
+    void    *agpgart;
 
 } intel_815ep_t;
 
@@ -68,18 +67,18 @@ static void
 intel_815ep_agp_aperature(intel_815ep_t *dev)
 {
     uint32_t aperature_base, aperature_size_calc;
-    int aperature_size, aperature_enable;
+    int      aperature_size, aperature_enable;
 
-    aperature_base = dev->pci_conf[0x13] << 24;
-    aperature_size = !!(dev->pci_conf[0xb4] & 8);
+    aperature_base      = dev->pci_conf[0x13] << 24;
+    aperature_size      = !!(dev->pci_conf[0xb4] & 8);
     aperature_size_calc = 1 << (aperature_size ? 25 : 24); /* 815EP has the choice of 64 & 32MB only */
 
     aperature_enable = aperature_base != 0;
 
-    if(aperature_size)
+    if (aperature_size)
         dev->pci_conf[0x13] &= 0xfe;
 
-    if(aperature_enable)
+    if (aperature_enable)
         intel_815ep_log("Intel 815EP AGP Aperature: Enabled at size 0x%x and size of %dMB\n", aperature_base, aperature_size ? 64 : 32);
     else
         intel_815ep_log("Intel 815EP AGP Aperature: AGP Aperature disabled\n");
@@ -95,15 +94,15 @@ intel_usmm_segment_recalc(intel_815ep_t *dev, uint8_t val)
     smram_disable(dev->h_segment);
     smram_disable(dev->usmm_segment);
 
-    if(val != 0)
+    if (val != 0)
         smram_enable(dev->h_segment, 0xfeea0000, 0x000a0000, 0x20000, 0, 1);
 
-    if(val >= 2) { /* TOM recalc based on intel_4x0.c by OBattler */
-    uint32_t tom = (mem_size << 10);
-    mem_set_mem_state_smm(tom, 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
-    uint32_t size = (val != 3) ? 0x100000 : 0x80000;
-    smram_enable(dev->usmm_segment, tom + 0x10000000, tom, size, 0, 1);
-    mem_set_mem_state_smm(tom, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
+    if (val >= 2) { /* TOM recalc based on intel_4x0.c by OBattler */
+        uint32_t tom = (mem_size << 10);
+        mem_set_mem_state_smm(tom, 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+        uint32_t size = (val != 3) ? 0x100000 : 0x80000;
+        smram_enable(dev->usmm_segment, tom + 0x10000000, tom, size, 0, 1);
+        mem_set_mem_state_smm(tom, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
     }
 }
 
@@ -114,19 +113,18 @@ intel_lsmm_segment_recalc(intel_815ep_t *dev, uint8_t val)
 
     smram_disable(dev->lsmm_segment);
 
-    switch(val)
-    {
-    case 1:
-        smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 1, 0);
-    break;
+    switch (val) {
+        case 1:
+            smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 1, 0);
+            break;
 
-    case 2:
-        smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 0, 0);
-    break;
+        case 2:
+            smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 0, 0);
+            break;
 
-    case 3:
-        smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 0, 1);
-    break;
+        case 3:
+            smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 0, 1);
+            break;
     }
 
     flushmmucache();
@@ -137,10 +135,9 @@ intel_pam_recalc(int addr, uint8_t val)
 {
     int region = 0xc0000 + ((addr - 0x5a) << 15);
 
-    if(addr == 0x59)
+    if (addr == 0x59)
         mem_set_mem_state_both(0xf0000, 0x10000, ((val & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((val & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
-    else
-    {
+    else {
         mem_set_mem_state_both(region, 0x4000, ((val & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((val & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
         mem_set_mem_state_both(region + 0x4000, 0x4000, ((val & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((val & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
     }
@@ -161,40 +158,39 @@ intel_815ep_gart_table(intel_815ep_t *dev)
 static void
 intel_815ep_write(int func, int addr, uint8_t val, void *priv)
 {
-    intel_815ep_t *dev = (intel_815ep_t *)priv;
+    intel_815ep_t *dev = (intel_815ep_t *) priv;
 
     intel_815ep_log("Intel 815EP MCH: dev->regs[%02x] = %02x\n", addr, val);
 
-    if(func)
+    if (func)
         return;
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x05:
             dev->pci_conf[addr] = val & 3;
-        break;
+            break;
 
         case 0x07:
             dev->pci_conf[addr] &= val & 0x70;
-        break;
+            break;
 
         case 0x2c ... 0x2f:
-            if(dev->pci_conf[addr] != 0)
+            if (dev->pci_conf[addr] != 0)
                 dev->pci_conf[addr] = val;
-        break;
+            break;
 
         case 0x13:
             dev->pci_conf[addr] = val;
             intel_815ep_agp_aperature(dev);
-        break;
+            break;
 
         case 0x50:
             dev->pci_conf[addr] = val & 0xdc;
-        break;
+            break;
 
         case 0x51:
             dev->pci_conf[addr] = val & 2; // Brute force to AGP Mode
-        break;
+            break;
 
         case 0x52:
         case 0x54:
@@ -202,140 +198,137 @@ intel_815ep_write(int func, int addr, uint8_t val, void *priv)
                 dev->pci_conf[addr] = val & ((addr & 4) ? 0x0f : 0xff);
                 spd_write_drbs_intel_815ep(dev->pci_conf);
             }
-        break;
+            break;
 
         case 0x53:
             dev->pci_conf[addr] = val;
-        break;
+            break;
 
         case 0x58:
             dev->pci_conf[addr] = val & 0x80;
-        break;
+            break;
 
         case 0x59 ... 0x5f:
             dev->pci_conf[addr] = val;
             intel_pam_recalc(addr, val);
-        break;
+            break;
 
         case 0x70:
-            if(!(dev->pci_conf[0x70] & 2)) {
+            if (!(dev->pci_conf[0x70] & 2)) {
                 dev->pci_conf[addr] = val & 0xfe;
                 intel_usmm_segment_recalc(dev, (val >> 4) & 3);
-            }
-            else {
+            } else {
                 dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xfa) | (val & 4);
             }
 
             intel_lsmm_segment_recalc(dev, (val >> 2) & 3);
-        break;
+            break;
 
         case 0x72:
             dev->pci_conf[addr] = val & 0xfb;
-        break;
+            break;
 
         case 0x73:
             dev->pci_conf[addr] = val & 0xa8;
-        break;
+            break;
 
         case 0x92 ... 0x93:
             dev->pci_conf[addr] = val;
-        break;
+            break;
 
         case 0x94:
             dev->pci_conf[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x98:
             dev->pci_conf[addr] = val & 0x77;
-        break;
+            break;
 
         case 0x99:
             dev->pci_conf[addr] = val & 0x80;
-        break;
+            break;
 
         case 0x9a:
             dev->pci_conf[addr] = val & 0xef;
-        break;
+            break;
 
         case 0x9b:
         case 0x9d:
             dev->pci_conf[addr] = val & 0x80;
-        break;
+            break;
 
         case 0xa4:
             dev->pci_conf[addr] = val & 7;
-        break;
+            break;
 
         case 0xa8:
             dev->pci_conf[addr] = val & 0x37;
-        break;
+            break;
 
         case 0xa9:
             dev->pci_conf[addr] = (val & 2) | 1;
-        break;
+            break;
 
         case 0xb0:
             dev->pci_conf[addr] = val & 0x81;
-        break;
+            break;
 
         case 0xb4:
             dev->pci_conf[addr] = val & 8;
             intel_815ep_agp_aperature(dev);
-        break;
+            break;
 
         case 0xb9:
             dev->pci_conf[addr] = val & 0xf0;
             intel_815ep_gart_table(dev);
-        break;
+            break;
 
         case 0xba:
             dev->pci_conf[addr] = val;
             intel_815ep_gart_table(dev);
-        break;
+            break;
 
         case 0xbb:
             dev->pci_conf[addr] = val & 0x1f;
             intel_815ep_gart_table(dev);
-        break;
+            break;
 
         case 0xbc ... 0xbd:
             dev->pci_conf[addr] = val & 0xf8;
-        break;
+            break;
 
         case 0xbe:
             dev->pci_conf[addr] = val & 0x28;
-        break;
+            break;
 
         case 0xcb:
             dev->pci_conf[addr] = val & 0x3f;
-        break;
+            break;
     }
 }
 
-
 static uint8_t
 intel_815ep_read(int func, int addr, void *priv)
 {
-    intel_815ep_t *dev = (intel_815ep_t *)priv;
+    intel_815ep_t *dev = (intel_815ep_t *) priv;
 
     intel_815ep_log("Intel 815EP MCH: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
 
-    if(func)
+    if (func)
         return 0xff;
 
-    if(addr == 0x51) // Bit 2 is Write Only. It cannot be read.
+    if (addr == 0x51) // Bit 2 is Write Only. It cannot be read.
         return dev->pci_conf[addr] & 3;
-    else if(addr == 0x52)
+    else if (addr == 0x52)
         return intel_815ep_get_banking();
     else
         return dev->pci_conf[addr];
 }
 
-
 static void
 intel_815ep_reset(void *priv)
 {
-    intel_815ep_t *dev = (intel_815ep_t *)priv;
+    intel_815ep_t *dev = (intel_815ep_t *) priv;
     memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf)); /* Wash out the registers */
 
     dev->pci_conf[0x00] = 0x86;    /* Intel */
@@ -374,21 +367,19 @@ intel_815ep_reset(void *priv)
 
     intel_815ep_agp_aperature(dev); /* Configure AGP Aperature */
 
-    for(int i = 0x59; i <= 0x5f; i++)  /* Reset PAM to defaults */
+    for (int i = 0x59; i <= 0x5f; i++) /* Reset PAM to defaults */
         intel_pam_recalc(i, 0);
 
     intel_lsmm_segment_recalc(dev, 0); /* Reset LSMM SMRAM to defaults */
     intel_usmm_segment_recalc(dev, 0); /* Reset USMM SMRAM to defaults */
 
     intel_815ep_gart_table(dev); /* Reset AGP GART to defaults */
-
 }
 
-
 static void
 intel_815ep_close(void *priv)
 {
-    intel_815ep_t *dev = (intel_815ep_t *)priv;
+    intel_815ep_t *dev = (intel_815ep_t *) priv;
 
     smram_del(dev->lsmm_segment);
     smram_del(dev->h_segment);
@@ -396,15 +387,14 @@ intel_815ep_close(void *priv)
     free(dev);
 }
 
-
 static void *
 intel_815ep_init(const device_t *info)
 {
-    intel_815ep_t *dev = (intel_815ep_t *)malloc(sizeof(intel_815ep_t));
+    intel_815ep_t *dev = (intel_815ep_t *) malloc(sizeof(intel_815ep_t));
     memset(dev, 0, sizeof(intel_815ep_t));
 
     /* Bus Speed(815EP runs at 133Mhz) */
-    if(cpu_busspeed >= 133333333)
+    if (cpu_busspeed >= 133333333)
         cpu_set_pci_speed(133333333);
     else
         cpu_set_pci_speed(cpu_busspeed);
@@ -425,7 +415,7 @@ intel_815ep_init(const device_t *info)
 
     /* SMRAM Segments */
     dev->lsmm_segment = smram_add();
-    dev->h_segment = smram_add();
+    dev->h_segment    = smram_add();
     dev->usmm_segment = smram_add();
 
     intel_815ep_reset(dev);
@@ -433,15 +423,15 @@ intel_815ep_init(const device_t *info)
 }
 
 const device_t intel_815ep_device = {
-    .name = "Intel 815EP MCH Bridge",
+    .name          = "Intel 815EP MCH Bridge",
     .internal_name = "intel_815ep",
-    .flags = DEVICE_PCI,
-    .local = 0,
-    .init = intel_815ep_init,
-    .close = intel_815ep_close,
-    .reset = intel_815ep_reset,
+    .flags         = DEVICE_PCI,
+    .local         = 0,
+    .init          = intel_815ep_init,
+    .close         = intel_815ep_close,
+    .reset         = intel_815ep_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/chipset/intel_ich2.c b/src/chipset/intel_ich2.c
index 39e39bbb4..ac467007d 100644
--- a/src/chipset/intel_ich2.c
+++ b/src/chipset/intel_ich2.c
@@ -60,27 +60,26 @@ intel_ich2_log(const char *fmt, ...)
     va_list ap;
 
     if (intel_ich2_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define intel_ich2_log(fmt, ...)
+#    define intel_ich2_log(fmt, ...)
 #endif
 
-typedef struct intel_ich2_t
-{
+typedef struct intel_ich2_t {
     uint8_t pci_conf[7][256];
 
-    acpi_t *acpi;
+    acpi_t            *acpi;
     intel_ich2_gpio_t *gpio;
     intel_ich2_trap_t *trap_device[10];
-    nvr_t *nvr;
-    sff8038i_t *ide_drive[2];
-    smbus_piix4_t *smbus;
-    tco_t *tco;
-    usb_t *usb_hub[2];
+    nvr_t             *nvr;
+    sff8038i_t        *ide_drive[2];
+    smbus_piix4_t     *smbus;
+    tco_t             *tco;
+    usb_t             *usb_hub[2];
 
 } intel_ich2_t;
 
@@ -88,9 +87,9 @@ typedef struct intel_ich2_t
 static void
 intel_ich2_acpi_setup(intel_ich2_t *dev)
 {
-    uint32_t base = (dev->pci_conf[0][0x41] << 8) | (dev->pci_conf[0][0x40] & 0x80);
-    int acpi_irq = ((dev->pci_conf[0][0x44] & 7) < 3) ? (9 + (dev->pci_conf[0][0x44] & 7)) : 9; /* Under APIC you can set this even higher but */
-    int enable = !!(dev->pci_conf[0][0x44] & 0x10);                                             /* as we lack it we are restricted with low.   */
+    uint32_t base     = (dev->pci_conf[0][0x41] << 8) | (dev->pci_conf[0][0x40] & 0x80);
+    int      acpi_irq = ((dev->pci_conf[0][0x44] & 7) < 3) ? (9 + (dev->pci_conf[0][0x44] & 7)) : 9; /* Under APIC you can set this even higher but */
+    int      enable   = !!(dev->pci_conf[0][0x44] & 0x10);                                           /* as we lack it we are restricted with low.   */
 
     acpi_update_io_mapping(dev->acpi, base, enable);
     acpi_set_irq_line(dev->acpi, acpi_irq);
@@ -100,10 +99,10 @@ static void
 intel_ich2_bioswe(intel_ich2_t *dev)
 {
     int bios_lock_enable = dev->pci_conf[0][0x4e] & 2;
-    int bios_write = dev->pci_conf[0][0x4e] & 1;
+    int bios_write       = dev->pci_conf[0][0x4e] & 1;
 
-    if(bios_lock_enable)
-        if(bios_write) {
+    if (bios_lock_enable)
+        if (bios_write) {
             intel_ich2_log("Intel ICH2 BIOSWE: BIOSWE SMI was raised\n");
             smi_raise();
         }
@@ -120,8 +119,8 @@ intel_ich2_tco_interrupt(intel_ich2_t *dev)
 static void
 intel_ich2_gpio_setup(intel_ich2_t *dev)
 {
-    uint16_t base = (dev->pci_conf[0][0x59] << 8) | (dev->pci_conf[0][0x58] & 0xc0);
-    int enable = !!(dev->pci_conf[0][0x5c] & 0x10);
+    uint16_t base   = (dev->pci_conf[0][0x59] << 8) | (dev->pci_conf[0][0x58] & 0xc0);
+    int      enable = !!(dev->pci_conf[0][0x5c] & 0x10);
 
     intel_ich2_gpio_base(enable, base, dev->gpio);
 }
@@ -129,16 +128,15 @@ intel_ich2_gpio_setup(intel_ich2_t *dev)
 static int
 intel_ich2_pirq_table(uint8_t val)
 {
-switch(val)
-{
-    case 0 ... 2:
-    case 8:
-    case 13:
-    return PCI_IRQ_DISABLED;
+    switch (val) {
+        case 0 ... 2:
+        case 8:
+        case 13:
+            return PCI_IRQ_DISABLED;
 
-    default:
-    return val;
-}
+        default:
+            return val;
+    }
 }
 
 static void
@@ -146,12 +144,12 @@ intel_ich2_pirq_update(int reset, int addr, uint8_t val)
 {
     int pirq = (addr >= 0x68) ? (addr - 0x63) : (addr - 0x5f);
 
-    if(((val & 0x80) != 0x80) && !reset) {                                             /* 86Box doesn't have an APIC yet.                          */ 
+    if (((val & 0x80) != 0x80) && !reset) {                                            /* 86Box doesn't have an APIC yet.                          */
         intel_ich2_log("Intel ICH2 LPC: Update PIRQ %c to IRQ %d\n", '@' + pirq, val); /* Under normal circumstances on an APIC enabled motherboard*/
-        pci_set_irq_routing(pirq, intel_ich2_pirq_table(val));                         /* this remains disabled and the IRQ are handed by the APIC */  
+        pci_set_irq_routing(pirq, intel_ich2_pirq_table(val));                         /* this remains disabled and the IRQ are handed by the APIC */
     }                                                                                  /* itself.                                                  */
-    else if(reset)
-        for(int i = 1; i <= 8; i++)
+    else if (reset)
+        for (int i = 1; i <= 8; i++)
             pci_set_irq_routing(i, PCI_IRQ_DISABLED);
 }
 
@@ -167,8 +165,8 @@ intel_ich2_nvr_handler(intel_ich2_t *dev)
 static void
 intel_ich2_trap_update(void *priv)
 {
-    intel_ich2_t *dev = (intel_ich2_t *) priv;
-    uint16_t temp_addr = 0;
+    intel_ich2_t *dev       = (intel_ich2_t *) priv;
+    uint16_t      temp_addr = 0;
 
     /* Hard Drives */
     intel_ich2_device_trap_setup(0x48, 0x01, 0x1f0, 8, dev->trap_device[0]); // HDD's don't have a decode bit
@@ -178,93 +176,90 @@ intel_ich2_trap_update(void *priv)
     intel_ich2_device_trap_setup(0x48, 0x02, 0x376, 1, dev->trap_device[1]);
 
     /* COM A */
-    switch(dev->pci_conf[0][0xe0] & 7)
-    {
+    switch (dev->pci_conf[0][0xe0] & 7) {
         case 0:
             temp_addr = 0x3f8;
-        break;
+            break;
 
         case 1:
             temp_addr = 0x2f8;
-        break;
+            break;
 
         case 2:
             temp_addr = 0x220;
-        break;
+            break;
 
         case 3:
             temp_addr = 0x228;
-        break;
+            break;
 
         case 4:
             temp_addr = 0x238;
-        break;
+            break;
 
         case 5:
             temp_addr = 0x2e8;
-        break;
+            break;
 
         case 6:
             temp_addr = 0x338;
-        break;
+            break;
 
         case 7:
             temp_addr = 0x3e8;
-        break;
+            break;
     }
     intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[2]);
 
     /* COM B */
-    switch((dev->pci_conf[0][0xe0] >> 4) & 7)
-    {
+    switch ((dev->pci_conf[0][0xe0] >> 4) & 7) {
         case 0:
             temp_addr = 0x3f8;
-        break;
+            break;
 
         case 1:
             temp_addr = 0x2f8;
-        break;
+            break;
 
         case 2:
             temp_addr = 0x220;
-        break;
+            break;
 
         case 3:
             temp_addr = 0x228;
-        break;
+            break;
 
         case 4:
             temp_addr = 0x238;
-        break;
+            break;
 
         case 5:
             temp_addr = 0x2e8;
-        break;
+            break;
 
         case 6:
             temp_addr = 0x338;
-        break;
+            break;
 
         case 7:
             temp_addr = 0x3e8;
-        break;
+            break;
     }
     intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[3]);
 
     /* LPT */
-    switch(dev->pci_conf[0][0xe1] & 3)
-    {
+    switch (dev->pci_conf[0][0xe1] & 3) {
         case 0:
             temp_addr = 0x378;
-        break;
+            break;
 
         case 1:
             temp_addr = 0x278;
-        break;
+            break;
 
         case 2:
             temp_addr = 0x3bc;
-        break;
+            break;
     }
     intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[4]);
 
@@ -273,23 +268,22 @@ intel_ich2_trap_update(void *priv)
     intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[5]);
 
     /* MSS (Note: There's no clear explaination about the SB Trap so only the MSS Trap is implementated) */
-    switch((dev->pci_conf[0][0xe2] >> 4) & 3)
-    {
+    switch ((dev->pci_conf[0][0xe2] >> 4) & 3) {
         case 0:
             temp_addr = 0x530;
-        break;
+            break;
 
         case 1:
             temp_addr = 0x604;
-        break;
+            break;
 
         case 2:
             temp_addr = 0xe80;
-        break;
+            break;
 
         case 3:
             temp_addr = 0xf40;
-        break;
+            break;
     }
     intel_ich2_device_trap_setup(0x49, 0x04, temp_addr, 8, dev->trap_device[6]);
 
@@ -307,30 +301,30 @@ intel_ich2_trap_update(void *priv)
 static void
 intel_ich2_function_disable(intel_ich2_t *dev)
 {
-uint16_t smbus_addr = (dev->pci_conf[3][0x21] << 8) | (dev->pci_conf[3][0x20] & 0xf0); // Hold the SMBus Base Address value
+    uint16_t smbus_addr = (dev->pci_conf[3][0x21] << 8) | (dev->pci_conf[3][0x20] & 0xf0); // Hold the SMBus Base Address value
 
-/* Disable IDE */
-if(dev->pci_conf[0][0xf2] & 2) {
-    ide_pri_disable();
-    ide_sec_disable();
-    sff_bus_master_handler(dev->ide_drive[0], 0, 0);
-    sff_bus_master_handler(dev->ide_drive[1], 0, 0);
-}
+    /* Disable IDE */
+    if (dev->pci_conf[0][0xf2] & 2) {
+        ide_pri_disable();
+        ide_sec_disable();
+        sff_bus_master_handler(dev->ide_drive[0], 0, 0);
+        sff_bus_master_handler(dev->ide_drive[1], 0, 0);
+    }
 
-/* Disable USB Hub 1 */
-if(dev->pci_conf[0][0xf2] & 4) {
-    uhci_update_io_mapping(dev->usb_hub[0], dev->pci_conf[2][0x20] & 0xe0, dev->pci_conf[0][0x21], 0);
-}
+    /* Disable USB Hub 1 */
+    if (dev->pci_conf[0][0xf2] & 4) {
+        uhci_update_io_mapping(dev->usb_hub[0], dev->pci_conf[2][0x20] & 0xe0, dev->pci_conf[0][0x21], 0);
+    }
 
-/* Disable SMBus */
-if(dev->pci_conf[0][0xf2] & 8) { // ICH2 Supports the ability of the SMBus Controller to be active even if it's PCI device is disabled
-    smbus_piix4_remap(dev->smbus, smbus_addr, dev->pci_conf[0][0xf3] & 1);
-}
+    /* Disable SMBus */
+    if (dev->pci_conf[0][0xf2] & 8) { // ICH2 Supports the ability of the SMBus Controller to be active even if it's PCI device is disabled
+        smbus_piix4_remap(dev->smbus, smbus_addr, dev->pci_conf[0][0xf3] & 1);
+    }
 
-/* Disable USB Hub 2 */
-if(dev->pci_conf[0][0xf2] & 0x10) {
-    uhci_update_io_mapping(dev->usb_hub[1], 0, 0, 0);
-}
+    /* Disable USB Hub 2 */
+    if (dev->pci_conf[0][0xf2] & 0x10) {
+        uhci_update_io_mapping(dev->usb_hub[1], 0, 0, 0);
+    }
 }
 
 /* IDE Controller functions */
@@ -344,13 +338,13 @@ intel_ich2_ide_setup(intel_ich2_t *dev)
     sff_bus_master_handler(dev->ide_drive[0], 0, bm_base);
     sff_bus_master_handler(dev->ide_drive[1], 0, bm_base + 8);
 
-    if(dev->pci_conf[1][0x41] & 0x80) {
+    if (dev->pci_conf[1][0x41] & 0x80) {
         intel_ich2_log("Intel ICH2 IDE: Primary Channel is enabled with Bus Master Address 0x%x.\n", bm_base);
         ide_pri_enable();
         sff_bus_master_handler(dev->ide_drive[0], 1, bm_base);
     }
 
-    if(dev->pci_conf[1][0x43] & 0x80) {
+    if (dev->pci_conf[1][0x43] & 0x80) {
         intel_ich2_log("Intel ICH2 IDE: Secondary Channel is enabled with Bus Master Address 0x%x.\n", bm_base + 8);
         ide_sec_enable();
         sff_bus_master_handler(dev->ide_drive[1], 1, bm_base + 8);
@@ -359,10 +353,10 @@ intel_ich2_ide_setup(intel_ich2_t *dev)
 
 /* USB Controller functions */
 static void
-intel_ich2_usb_setup(int func, intel_ich2_t* dev)
+intel_ich2_usb_setup(int func, intel_ich2_t *dev)
 {
     int current_hub = (func == 4) ? 4 : 2;
-    int hub_num = (func == 4);
+    int hub_num     = (func == 4);
     uhci_update_io_mapping(dev->usb_hub[hub_num], dev->pci_conf[current_hub][0x20] & 0xe0, dev->pci_conf[current_hub][0x21], !!(dev->pci_conf[current_hub][0x04] & 1));
 }
 
@@ -372,7 +366,7 @@ intel_ich2_smbus_setup(intel_ich2_t *dev)
 {
     uint16_t base = (dev->pci_conf[3][0x21] << 8) | (dev->pci_conf[3][0x20] & 0xf0);
 
-    if((dev->pci_conf[3][0x40] & 1) && (dev->pci_conf[3][0x04] & 1))
+    if ((dev->pci_conf[3][0x40] & 1) && (dev->pci_conf[3][0x04] & 1))
         intel_ich2_log("Intel ICH2 SMBus: SMBus is enabled.\n");
 
     smbus_piix4_remap(dev->smbus, base, (dev->pci_conf[3][0x40] & 1) && (dev->pci_conf[3][0x04] & 1));
@@ -382,344 +376,332 @@ intel_ich2_smbus_setup(intel_ich2_t *dev)
 static void
 intel_ich2_write(int func, int addr, uint8_t val, void *priv)
 {
-    intel_ich2_t *dev = (intel_ich2_t *)priv;
+    intel_ich2_t *dev = (intel_ich2_t *) priv;
 
-    if(func == 0) {
+    if (func == 0) {
         intel_ich2_log("Intel ICH2 LPC: dev->regs[%02x] = %02x\n", addr, val);
-        switch(addr)
-        {
+        switch (addr) {
             case 0x04:
                 dev->pci_conf[func][addr] = (val & 0x40) | 0x0f;
-            break;
+                break;
 
             case 0x05:
                 dev->pci_conf[func][addr] = val & 0x01;
-            break;
+                break;
 
             case 0x07:
                 dev->pci_conf[func][addr] &= val & 0xf9;
-            break;
+                break;
 
             case 0x40 ... 0x41:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0xff : (0x80 | 1));
                 intel_ich2_acpi_setup(dev);
-            break;
+                break;
 
             case 0x44:
                 dev->pci_conf[func][addr] = val & 0x17;
                 intel_ich2_acpi_setup(dev);
-            break;
+                break;
 
             case 0x4e:
-                if(!(val & 2))
+                if (!(val & 2))
                     dev->pci_conf[func][addr] = val & 3;
                 else
                     dev->pci_conf[func][addr] = (val & 1) | 2;
 
                 intel_ich2_bioswe(dev);
-            break;
+                break;
 
             case 0x54:
                 dev->pci_conf[func][addr] = val & 0x0f;
                 intel_ich2_tco_interrupt(dev);
-            break;
+                break;
 
             case 0x58 ... 0x59:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0xff : (0xc0 | 1));
                 intel_ich2_gpio_setup(dev);
-            break;
+                break;
 
             case 0x5c:
                 dev->pci_conf[func][addr] = val & 0x10;
                 intel_ich2_gpio_setup(dev);
-            break;
+                break;
 
             case 0x60 ... 0x63:
             case 0x68 ... 0x6b:
                 dev->pci_conf[func][addr] = val & 0x8f;
                 intel_ich2_pirq_update(0, addr, val);
-            break;
+                break;
 
             case 0x64:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0x88:
                 dev->pci_conf[func][addr] = val & 6;
-            break;
+                break;
 
             case 0x8a:
                 dev->pci_conf[func][addr] &= val & 6;
-            break;
+                break;
 
             case 0x90:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0x91:
                 dev->pci_conf[func][addr] = val & 0xfc;
-            break;
+                break;
 
             case 0xa0:
                 dev->pci_conf[func][addr] = val & 0x6c;
-            break;
+                break;
 
             case 0xa1:
                 dev->pci_conf[func][addr] = val & 6;
-            break;
+                break;
 
             case 0xa2:
                 dev->pci_conf[func][addr] &= val & 3;
-            break;
+                break;
 
             case 0xa4:
                 dev->pci_conf[func][addr] = val & 1;
                 dev->pci_conf[func][addr] &= val & 6;
-            break;
+                break;
 
-            case 0xb8 ... 0xbb: 
+            case 0xb8 ... 0xbb:
                 dev->pci_conf[func][addr] = val; /* GPIO Routing */
-            break;
+                break;
 
             case 0xc0:
                 dev->pci_conf[func][addr] = val & 0xf0;
-            break;
+                break;
 
             case 0xc4 ... 0xcb:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0xcc ... 0xcd:
                 dev->pci_conf[func][addr] &= val;
-            break;
+                break;
 
             case 0xd0:
                 dev->pci_conf[func][addr] = val & 0x4f; /* Brute force APIC support as disabled */
-            break;
+                break;
 
             case 0xd1:
                 dev->pci_conf[func][addr] = val & 0x38; /* Brute force APIC support as disabled */
-            break;
+                break;
 
             case 0xd3:
                 dev->pci_conf[func][addr] = val & 0x03;
-            break;
+                break;
 
             case 0xd4:
                 dev->pci_conf[func][addr] = val & 0x02;
-            break;
+                break;
 
             case 0xd5:
                 dev->pci_conf[func][addr] = val & 0x3f;
-            break;
+                break;
 
             case 0xd8:
                 dev->pci_conf[func][addr] = val & 0x1c;
                 intel_ich2_nvr_handler(dev);
-            break;
+                break;
 
             case 0xe0:
                 dev->pci_conf[func][addr] = val & 0x77;
                 intel_ich2_trap_update(dev);
-            break;
+                break;
 
             case 0xe1:
                 dev->pci_conf[func][addr] = val & 0x13;
                 intel_ich2_trap_update(dev);
-            break;
+                break;
 
             case 0xe2:
                 dev->pci_conf[func][addr] = val & 0x3b;
                 intel_ich2_trap_update(dev);
-            break;
+                break;
 
             case 0xe3:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0xe4:
                 dev->pci_conf[func][addr] = val & 0x81;
-            break;
+                break;
 
             case 0xe5 ... 0xe6:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0xe7:
                 dev->pci_conf[func][addr] = val & 0x3f;
-            break;
+                break;
 
             case 0xe8 ... 0xeb:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0xec:
                 dev->pci_conf[func][addr] = val & 0xf1;
-            break;
+                break;
 
             case 0xed:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0xee ... 0xef:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0xf0:
                 dev->pci_conf[func][addr] = val & 0x0f;
-            break;
+                break;
 
             case 0xf2 ... 0xf3:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0x01 : 0xfe);
                 intel_ich2_function_disable(dev);
-            break;
+                break;
         }
-    }
-    else if((func == 1) && !(dev->pci_conf[0][0xf2] & 2)) {
+    } else if ((func == 1) && !(dev->pci_conf[0][0xf2] & 2)) {
         intel_ich2_log("Intel ICH2 IDE: dev->regs[%02x] = %02x\n", addr, val);
-        switch(addr)
-        {
+        switch (addr) {
             case 0x04:
                 dev->pci_conf[func][addr] = val & 5;
                 intel_ich2_ide_setup(dev);
-            break;
+                break;
 
             case 0x07:
                 dev->pci_conf[func][addr] &= val & 0x2e;
-            break;
+                break;
 
             case 0x20 ... 0x21:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0xff : (0xf0 | 1));
                 intel_ich2_ide_setup(dev);
-            break;
+                break;
 
             case 0x2c ... 0x2f:
-                if(dev->pci_conf[func][addr] != 0)
+                if (dev->pci_conf[func][addr] != 0)
                     dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0x40 ... 0x43:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0xf3 : 0xff);
 
-                if((addr == 0x41) || (addr == 0x43))
+                if ((addr == 0x41) || (addr == 0x43))
                     intel_ich2_ide_setup(dev);
-            break;
+                break;
 
             case 0x44:
                 dev->pci_conf[func][addr] = val;
-            break;
+                break;
 
             case 0x48:
                 dev->pci_conf[func][addr] = val & 0x0f;
-            break;
+                break;
 
             case 0x4a ... 0x4b:
                 dev->pci_conf[func][addr] = val & 0x33;
-            break;
+                break;
         }
-    }
-    else if(((func == 2) && !(dev->pci_conf[0][0xf2] & 4)) || ((func == 4) && !(dev->pci_conf[0][0xf2] & 0x10))) {
+    } else if (((func == 2) && !(dev->pci_conf[0][0xf2] & 4)) || ((func == 4) && !(dev->pci_conf[0][0xf2] & 0x10))) {
         intel_ich2_log("Intel ICH2 USB Hub %d: dev->regs[%02x] = %02x\n", (func == 4), addr, val);
-        switch(addr)
-        {
+        switch (addr) {
             case 0x04:
                 dev->pci_conf[func][addr] = val & 5;
                 intel_ich2_usb_setup(func, dev);
-            break;
+                break;
 
             case 0x07:
                 dev->pci_conf[func][addr] &= val & 0x2e;
-            break;
+                break;
 
             case 0x20 ... 0x21:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0xff : (0xf0 | 1));
                 intel_ich2_usb_setup(func, dev);
-            break;
+                break;
 
             case 0xc0:
                 dev->pci_conf[func][addr] = val & 0xbf;
-            break;
+                break;
 
             case 0xc1:
                 dev->pci_conf[func][addr] &= val & 0xaf;
-            break;
+                break;
 
             case 0xc4:
                 dev->pci_conf[func][addr] = val & 3;
-            break;
+                break;
         }
-    }
-    else if((func == 3) && !(dev->pci_conf[0][0xf2] & 8)) {
+    } else if ((func == 3) && !(dev->pci_conf[0][0xf2] & 8)) {
         intel_ich2_log("Intel ICH2 SMBus: dev->regs[%02x] = %02x\n", addr, val);
-        switch(addr)
-        {
+        switch (addr) {
             case 0x04:
                 dev->pci_conf[func][addr] = val & 1;
                 intel_ich2_smbus_setup(dev);
-            break;
+                break;
 
             case 0x07:
                 dev->pci_conf[func][addr] &= val & 0x0e;
-            break;
+                break;
 
             case 0x20 ... 0x21:
                 dev->pci_conf[func][addr] = val & ((addr & 1) ? 0xff : (0xf0 | 1));
                 intel_ich2_smbus_setup(dev);
-            break;
+                break;
 
             case 0x3c:
                 dev->pci_conf[func][addr] = val;                       /* 86Box doesn't give any capabilities to take the PCI IRQ pin, also */
                 smbus_piix4_get_irq(pci_get_int(0x1f, 2), dev->smbus); /* can't use pointers as whatever recieved from there is temporary.  */
                 intel_ich2_log("Intel ICH2 SMBus: Got IRQ %d\n", pci_get_int(0x1f, 2));
-            break;
+                break;
 
             case 0x40:
                 dev->pci_conf[func][addr] = val & 7;
                 intel_ich2_smbus_setup(dev);
                 smbus_piix4_smi_en(!!(val & 2), dev->smbus);
-            break;
+                break;
         }
     }
 }
 
-
 static uint8_t
 intel_ich2_read(int func, int addr, void *priv)
 {
-    intel_ich2_t *dev = (intel_ich2_t *)priv;
+    intel_ich2_t *dev = (intel_ich2_t *) priv;
 
-    if(func == 0) {
-    intel_ich2_log("Intel ICH2 LPC: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[func][addr]);
-    return dev->pci_conf[func][addr];
-    }
-    else if((func == 1) && !(dev->pci_conf[0][0xf2] & 2)) {
-    intel_ich2_log("Intel ICH2 IDE: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[func][addr]);
-    return dev->pci_conf[func][addr];
-    }
-    else if(((func == 2) && !(dev->pci_conf[0][0xf2] & 4)) || ((func == 4) && !(dev->pci_conf[0][0xf2] & 0x10))) {
-    intel_ich2_log("Intel ICH2 USB Hub %d: dev->regs[%02x] (%02x)\n", (func == 4), addr, dev->pci_conf[func][addr]);
+    if (func == 0) {
+        intel_ich2_log("Intel ICH2 LPC: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[func][addr]);
+        return dev->pci_conf[func][addr];
+    } else if ((func == 1) && !(dev->pci_conf[0][0xf2] & 2)) {
+        intel_ich2_log("Intel ICH2 IDE: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[func][addr]);
+        return dev->pci_conf[func][addr];
+    } else if (((func == 2) && !(dev->pci_conf[0][0xf2] & 4)) || ((func == 4) && !(dev->pci_conf[0][0xf2] & 0x10))) {
+        intel_ich2_log("Intel ICH2 USB Hub %d: dev->regs[%02x] (%02x)\n", (func == 4), addr, dev->pci_conf[func][addr]);
 
-    if((addr >= 0x2c) && (addr <= 0x2f)) /* USB shares the same subsystem vendor info as the IDE */
-        return dev->pci_conf[1][addr];
+        if ((addr >= 0x2c) && (addr <= 0x2f)) /* USB shares the same subsystem vendor info as the IDE */
+            return dev->pci_conf[1][addr];
 
-    return dev->pci_conf[func][addr];
-    }
-    else if((func == 3) && !(dev->pci_conf[0][0xf2] & 8)) {
-    intel_ich2_log("Intel ICH2 SMBus: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[func][addr]);
+        return dev->pci_conf[func][addr];
+    } else if ((func == 3) && !(dev->pci_conf[0][0xf2] & 8)) {
+        intel_ich2_log("Intel ICH2 SMBus: dev->regs[%02x] (%02x)\n", addr, dev->pci_conf[func][addr]);
 
-    if((addr >= 0x2c) && (addr <= 0x2f)) /* SMBus shares the same subsystem vendor info as the IDE */
-        return dev->pci_conf[1][addr];
+        if ((addr >= 0x2c) && (addr <= 0x2f)) /* SMBus shares the same subsystem vendor info as the IDE */
+            return dev->pci_conf[1][addr];
 
-    return dev->pci_conf[func][addr];
-    }
-    else return 0xff;
+        return dev->pci_conf[func][addr];
+    } else
+        return 0xff;
 }
 
-
 static void
 intel_ich2_reset(void *priv)
 {
-    intel_ich2_t *dev = (intel_ich2_t *)priv;
+    intel_ich2_t *dev = (intel_ich2_t *) priv;
     memset(dev->pci_conf, 0, sizeof(dev->pci_conf)); /* Wash out the Registers */
 
     /* Function 0: LPC Bridge */
@@ -771,11 +753,11 @@ intel_ich2_reset(void *priv)
 
     dev->pci_conf[0][0xf0] = 0x0f;
 
-    intel_ich2_acpi_setup(dev); /* Setup the ACPI Interface */
-    intel_ich2_tco_interrupt(dev); /* Configure the TCO Interrupt */
-    intel_ich2_gpio_setup(dev); /* Setup the GPIO */
-    intel_ich2_pirq_update(1, 0, 0);  /* Reset the PIRQ interrupts */
-    intel_ich2_nvr_handler(dev); /* Set the NVR aliases */
+    intel_ich2_acpi_setup(dev);      /* Setup the ACPI Interface */
+    intel_ich2_tco_interrupt(dev);   /* Configure the TCO Interrupt */
+    intel_ich2_gpio_setup(dev);      /* Setup the GPIO */
+    intel_ich2_pirq_update(1, 0, 0); /* Reset the PIRQ interrupts */
+    intel_ich2_nvr_handler(dev);     /* Set the NVR aliases */
 
     /* Function 1: IDE Controller */
     dev->pci_conf[1][0x00] = 0x86;
@@ -797,7 +779,7 @@ intel_ich2_reset(void *priv)
 
     dev->pci_conf[1][0x54] = 0xff; /* Hack: Fake Cable Conductor & UltraDMA details */
 
-    if(cpu_busspeed >= 100000000)  /* Go UltraDMA 100 if CPU is up for it. Not that it actually matters */
+    if (cpu_busspeed >= 100000000) /* Go UltraDMA 100 if CPU is up for it. Not that it actually matters */
         dev->pci_conf[1][0x55] = 0xf0;
 
     sff_bus_master_reset(dev->ide_drive[0], 0); /* Setup the IDE */
@@ -877,19 +859,17 @@ intel_ich2_reset(void *priv)
     intel_ich2_usb_setup(4, dev);
 }
 
-
 static void
 intel_ich2_close(void *priv)
 {
-    intel_ich2_t *dev = (intel_ich2_t *)priv;
+    intel_ich2_t *dev = (intel_ich2_t *) priv;
     free(dev);
 }
 
-
 static void *
 intel_ich2_init(const device_t *info)
 {
-    intel_ich2_t *dev = (intel_ich2_t *)malloc(sizeof(intel_ich2_t));
+    intel_ich2_t *dev = (intel_ich2_t *) malloc(sizeof(intel_ich2_t));
     memset(dev, 0, sizeof(intel_ich2_t));
     int slot;
 
@@ -949,15 +929,15 @@ intel_ich2_init(const device_t *info)
 }
 
 const device_t intel_ich2_device = {
-    .name = "Intel ICH2",
+    .name          = "Intel ICH2",
     .internal_name = "intel_ich2",
-    .flags = DEVICE_PCI,
-    .local = 0,
-    .init = intel_ich2_init,
-    .close = intel_ich2_close,
-    .reset = intel_ich2_reset,
+    .flags         = DEVICE_PCI,
+    .local         = 0,
+    .init          = intel_ich2_init,
+    .close         = intel_ich2_close,
+    .reset         = intel_ich2_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/device/hwm_nsc366.c b/src/device/hwm_nsc366.c
index 61b169925..34e5bd930 100644
--- a/src/device/hwm_nsc366.c
+++ b/src/device/hwm_nsc366.c
@@ -35,20 +35,23 @@
 #include <86box/nsc366.h>
 
 /* Fan Algorithms */
-#define FAN_TO_REG(val, div)	((val) <= 100 ? 0 : 480000 / ((val) * (div)))
-#define FAN_DIV_FROM_REG(val)	(1 << (((val) >> 5) & 0x03))
-#define FAN_FROM_REG(val, div)	((val) == 0 ? 0 : 480000 / ((val) * (div)))
+#define FAN_TO_REG(val, div)   ((val) <= 100 ? 0 : 480000 / ((val) * (div)))
+#define FAN_DIV_FROM_REG(val)  (1 << (((val) >> 5) & 0x03))
+#define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : 480000 / ((val) * (div)))
 
 /* Voltage Algorithms */
-#define IN_TO_REG(val, ref)		((val) < 0 ? 0 : (val) * 256 >= (ref) * 255 ? 255 : ((val) * 256 + (ref) / 2) / (ref))
-#define IN_FROM_REG(val, ref)	(((val) * (ref) + 128) / 256)
-#define VREF (dev->vlm_config_global[0x08] & 2) ? 3025 : 2966 //VREF taken from pc87360.c
-#define VLM_BANK dev->vlm_config_global[0x09]
+#define IN_TO_REG(val, ref) ((val) < 0 ? 0 : (val) *256 >= (ref) *255 ? 255 \
+                                                                      : ((val) *256 + (ref) / 2) / (ref))
+#define IN_FROM_REG(val, ref) (((val) * (ref) + 128) / 256)
+#define VREF                  (dev->vlm_config_global[0x08] & 2) ? 3025 : 2966 // VREF taken from pc87360.c
+#define VLM_BANK              dev->vlm_config_global[0x09]
 
 /* Temperature Algorithms */
-#define TEMP_TO_REG(val)		((val) < -55000 ? -55 : (val) > 127000 ? 127 : (val) < 0 ? ((val) - 500) / 1000 : ((val) + 500) / 1000)
-#define TEMP_FROM_REG(val)		((val) * 1000)
-#define TMS_BANK dev->tms_config_global[0x09]
+#define TEMP_TO_REG(val) ((val) < -55000 ? -55 : (val) > 127000 ? 127                 \
+                              : (val) < 0                       ? ((val) -500) / 1000 \
+                                                                : ((val) + 500) / 1000)
+#define TEMP_FROM_REG(val) ((val) *1000)
+#define TMS_BANK           dev->tms_config_global[0x09]
 
 #ifdef ENABLE_NSC366_HWM_LOG
 int nsc366_hwm_do_log = ENABLE_NSC366_HWM_LOG;
@@ -58,75 +61,73 @@ nsc366_hwm_log(const char *fmt, ...)
     va_list ap;
 
     if (nsc366_hwm_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define nsc366_hwm_log(fmt, ...)
+#    define nsc366_hwm_log(fmt, ...)
 #endif
 
 /* Fans */
 static void
 nsc366_fscm_write(uint16_t addr, uint8_t val, void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     addr &= 0x000f;
 
     nsc366_hwm_log("NSC366 Fan Control: Write 0x%02x to register 0x%02x\n", val, addr);
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x00:
         case 0x02:
         case 0x04:
             dev->fscm_config[addr] = val;
-        break;
-        
+            break;
+
         case 0x01:
         case 0x03:
         case 0x05:
             dev->fscm_config[addr] = val;
-        break;
+            break;
 
         case 0x06:
         case 0x09:
         case 0x0c:
             dev->fscm_config[addr] = val;
-        break;
+            break;
 
         case 0x08:
         case 0x0b:
         case 0x0d:
             dev->fscm_config[addr] = (val & 0x78) | 1;
-        break;
+            break;
     }
 }
 
 static uint8_t
 nsc366_fscm_read(uint16_t addr, void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     addr &= 0x000f;
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x00 ... 0x06:
         case 0x08 ... 0x09:
         case 0x0b ... 0x0c:
             return dev->fscm_config[addr];
-        
+
         case 0x07:
         case 0x0a:
         case 0x0d:
-            if(((addr == 0x07) && !!(dev->fscm_enable & 1)) || ((addr == 0x0a) && !!(dev->fscm_enable & 2)) || ((addr == 0x0d) && !!(dev->fscm_enable & 4))) {
+            if (((addr == 0x07) && !!(dev->fscm_enable & 1)) || ((addr == 0x0a) && !!(dev->fscm_enable & 2)) || ((addr == 0x0d) && !!(dev->fscm_enable & 4))) {
                 nsc366_hwm_log("NSC366 Fan Control: Reading %d RPM's from Bank %d\n", FAN_FROM_REG(dev->fscm_config[addr], FAN_DIV_FROM_REG(dev->fscm_config[0x06])), (addr - 7) / 3);
                 return dev->fscm_config[addr];
-            }
-            else return 0;
+            } else
+                return 0;
 
         default:
             return 0;
@@ -136,12 +137,12 @@ nsc366_fscm_read(uint16_t addr, void *priv)
 void
 nsc366_update_fscm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
 {
-    if(dev->fscm_addr != 0)
+    if (dev->fscm_addr != 0)
         io_removehandler(dev->fscm_addr, 15, nsc366_fscm_read, NULL, NULL, nsc366_fscm_write, NULL, NULL, dev);
 
     dev->fscm_addr = addr;
 
-    if((addr != 0) && enable)
+    if ((addr != 0) && enable)
         io_sethandler(addr, 15, nsc366_fscm_read, NULL, NULL, nsc366_fscm_write, NULL, NULL, dev);
 }
 
@@ -149,83 +150,78 @@ nsc366_update_fscm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
 static void
 nsc366_vlm_write(uint16_t addr, uint8_t val, void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     addr &= 0x000f;
 
-    if(addr <= 9)
+    if (addr <= 9)
         nsc366_hwm_log("NSC366 Voltage Monitor: Write 0x%02x to register 0x%02x\n", val, addr);
     else
         nsc366_hwm_log("NSC366 Voltage Monitor: Write 0x%02x to register 0x%02x of bank %d\n", val, addr, VLM_BANK);
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x02 ... 0x04:
             dev->vlm_config_global[addr] = val;
-        break;
+            break;
 
         case 0x05:
             dev->vlm_config_global[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x06:
             dev->vlm_config_global[addr] = val & 0xc0;
-        break;
+            break;
 
         case 0x07:
             dev->vlm_config_global[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x08:
             dev->vlm_config_global[addr] = val & 3;
-        break;
+            break;
 
         case 0x09:
             dev->vlm_config_global[addr] = val & 0x1f;
-        break;
+            break;
 
         case 0x0a:
-            if(VLM_BANK < 13)
+            if (VLM_BANK < 13)
                 dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val & 1;
-        break;
+            break;
 
         case 0x0c ... 0x0e:
-            if(VLM_BANK < 13)
-            dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val;
-        break;
+            if (VLM_BANK < 13)
+                dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val;
+            break;
     }
 }
 
-
 static uint8_t
 nsc366_vlm_read(uint16_t addr, void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     addr &= 0x000f;
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x00 ... 0x09:
             return dev->vlm_config_global[addr];
-        
+
         case 0x0a:
         case 0x0c ... 0x0e:
-            if(VLM_BANK < 13)
+            if (VLM_BANK < 13)
                 return dev->vlm_config_bank[VLM_BANK][addr - 0x0a];
             else
                 return 0;
-        
+
         case 0x0b:
             if (VLM_BANK < 13) {
                 if (dev->vlm_config_bank[VLM_BANK][0] & 1) {
                     nsc366_hwm_log("NSC366 Voltage Monitor: Reading %d Volts from Bank %d\n", IN_FROM_REG(dev->vlm_config_bank[VLM_BANK][1], VREF), VLM_BANK);
                     return dev->vlm_config_bank[VLM_BANK][1];
-                }
-                else
+                } else
                     return 0;
-            }
-            else
+            } else
                 return 0;
 
         default:
@@ -236,12 +232,12 @@ nsc366_vlm_read(uint16_t addr, void *priv)
 void
 nsc366_update_vlm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
 {
-    if(dev->vlm_addr != 0)
+    if (dev->vlm_addr != 0)
         io_removehandler(dev->vlm_addr, 15, nsc366_vlm_read, NULL, NULL, nsc366_vlm_write, NULL, NULL, dev);
 
     dev->vlm_addr = addr;
 
-    if((addr != 0) && enable)
+    if ((addr != 0) && enable)
         io_sethandler(addr, 15, nsc366_vlm_read, NULL, NULL, nsc366_vlm_write, NULL, NULL, dev);
 }
 
@@ -249,71 +245,69 @@ nsc366_update_vlm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
 static void
 nsc366_tms_write(uint16_t addr, uint8_t val, void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     addr &= 0x000f;
 
-    if(addr <= 9)
+    if (addr <= 9)
         nsc366_hwm_log("NSC366 Temperature Monitor: Write 0x%02x to register 0x%02x\n", val, addr);
     else
         nsc366_hwm_log("NSC366 Temperature Monitor: Write 0x%02x to register 0x%02x of bank %d\n", val, addr, TMS_BANK);
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x02:
             dev->tms_config_global[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x04:
             dev->tms_config_global[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x08:
             dev->tms_config_global[addr] = val & 3;
-        break;
+            break;
 
         case 0x09:
             dev->tms_config_global[addr] = val & 3;
-        break;
+            break;
 
         case 0x0a:
-            if(TMS_BANK < 3)
+            if (TMS_BANK < 3)
                 dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val & 1;
-        break;
+            break;
 
         case 0x0c ... 0x0e:
-            if(TMS_BANK < 3)
-            dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val;
-        break;
+            if (TMS_BANK < 3)
+                dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val;
+            break;
     }
 }
 
-
 static uint8_t
 nsc366_tms_read(uint16_t addr, void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     addr &= 0x000f;
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x00 ... 0x09:
             return dev->tms_config_global[addr];
-        
+
         case 0x0a:
         case 0x0c ... 0x0e:
-            if(TMS_BANK < 4)
+            if (TMS_BANK < 4)
                 return dev->tms_config_bank[TMS_BANK][addr - 0x0a];
-            else return 0;
-        
+            else
+                return 0;
+
         case 0x0b:
-            if(TMS_BANK < 4) {
-                if (dev->vlm_config_bank[VLM_BANK][0] & 1) { 
+            if (TMS_BANK < 4) {
+                if (dev->vlm_config_bank[VLM_BANK][0] & 1) {
                     nsc366_hwm_log("NSC366 Temperature Monitor: Reading %d Degrees Celsius from Bank %d\n", TEMP_FROM_REG(dev->tms_config_bank[TMS_BANK][1]), TMS_BANK);
                     return dev->tms_config_bank[TMS_BANK][1];
-                }
-                else return 0;
+                } else
+                    return 0;
             }
 
         default:
@@ -324,24 +318,24 @@ nsc366_tms_read(uint16_t addr, void *priv)
 void
 nsc366_update_tms_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
 {
-    if(dev->vlm_addr != 0)
+    if (dev->vlm_addr != 0)
         io_removehandler(dev->tms_addr, 15, nsc366_tms_read, NULL, NULL, nsc366_tms_write, NULL, NULL, dev);
 
     dev->tms_addr = addr;
 
-    if((addr != 0) && enable)
+    if ((addr != 0) && enable)
         io_sethandler(addr, 15, nsc366_tms_read, NULL, NULL, nsc366_tms_write, NULL, NULL, dev);
 }
 
- #define TEMP_FROM_REG(val)		((val) * 1000)
+#define TEMP_FROM_REG(val) ((val) *1000)
 
 static void
 nsc366_hwm_reset(void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
     memset(dev->fscm_config, 0, sizeof(dev->fscm_config));
     dev->fscm_enable = 0;
-    dev->fscm_addr = 0;
+    dev->fscm_addr   = 0;
 
     /* Get fan reports from defaults */
     dev->fscm_config[0x07] = FAN_TO_REG(dev->values->fans[0], FAN_DIV_FROM_REG(dev->fscm_config[0x06]));
@@ -350,38 +344,36 @@ nsc366_hwm_reset(void *priv)
 
     memset(dev->vlm_config_global, 0, sizeof(dev->vlm_config_global));
     memset(dev->vlm_config_bank, 0, sizeof(dev->vlm_config_bank));
-    dev->vlm_addr = 0;
+    dev->vlm_addr                = 0;
     dev->vlm_config_global[0x08] = 3;
 
     /* Get voltage reports from defaults */
-    for(int i = 0; i < 13; i++) {
+    for (int i = 0; i < 13; i++) {
         dev->vlm_config_bank[i][1] = IN_TO_REG(dev->values->voltages[i], VREF);
     }
 
     memset(dev->tms_config_global, 0, sizeof(dev->tms_config_global));
     memset(dev->tms_config_bank, 0, sizeof(dev->tms_config_bank));
-    dev->tms_addr = 0;
+    dev->tms_addr                = 0;
     dev->tms_config_global[0x08] = 3;
 
     /* Get temperature reports from defaults */
-    for(int i = 0; i < 4; i++)
+    for (int i = 0; i < 4; i++)
         dev->tms_config_bank[i][1] = TEMP_TO_REG(dev->values->temperatures[i]);
 }
 
-
 static void
 nsc366_hwm_close(void *priv)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
 
     free(dev);
 }
 
-
 static void *
 nsc366_hwm_init(const device_t *info)
 {
-    nsc366_hwm_t *dev = (nsc366_hwm_t *)malloc(sizeof(nsc366_hwm_t));
+    nsc366_hwm_t *dev = (nsc366_hwm_t *) malloc(sizeof(nsc366_hwm_t));
     memset(dev, 0, sizeof(nsc366_hwm_t));
 
     /* Initialize the default values (HWM is incomplete still) */
@@ -392,13 +384,13 @@ nsc366_hwm_init(const device_t *info)
             3000  /* FAN 2 */
         },
         {
-            30,   /* Temperatures which are broken */
+            30, /* Temperatures which are broken */
             30,
             30,
             30
         },
         {
-            0,    /* Voltages which are broken */
+            0, /* Voltages which are broken */
             0,
             0,
             0,
@@ -412,22 +404,22 @@ nsc366_hwm_init(const device_t *info)
             0
         }
     };
-    hwm_values = defaults;
+    hwm_values  = defaults;
     dev->values = &hwm_values;
 
     return dev;
 }
 
 const device_t nsc366_hwm_device = {
-    .name = "National Semiconductor NSC366 Hardware Monitor",
+    .name          = "National Semiconductor NSC366 Hardware Monitor",
     .internal_name = "nsc366_hwm",
-    .flags = 0,
-    .local = 0,
-    .init = nsc366_hwm_init,
-    .close = nsc366_hwm_close,
-    .reset = nsc366_hwm_reset,
+    .flags         = 0,
+    .local         = 0,
+    .init          = nsc366_hwm_init,
+    .close         = nsc366_hwm_close,
+    .reset         = nsc366_hwm_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/device/intel_ich2_gpio.c b/src/device/intel_ich2_gpio.c
index 6863e10b7..2c79ef87b 100644
--- a/src/device/intel_ich2_gpio.c
+++ b/src/device/intel_ich2_gpio.c
@@ -38,16 +38,15 @@ intel_ich2_gpio_log(const char *fmt, ...)
     va_list ap;
 
     if (intel_ich2_gpio_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define intel_ich2_gpio_log(fmt, ...)
+#    define intel_ich2_gpio_log(fmt, ...)
 #endif
 
-
 static void
 intel_ich2_gpio_write(uint16_t addr, uint8_t val, void *priv)
 {
@@ -57,53 +56,51 @@ intel_ich2_gpio_write(uint16_t addr, uint8_t val, void *priv)
 
     intel_ich2_gpio_log("Intel ICH2 GPIO: Write 0x%02x on GPIO Register 0x%02x\n", val, addr);
 
-    switch(addr)
-    {
+    switch (addr) {
         /* GPIO Use Enable */
         case 0x00:
             dev->gpio_regs[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x01:
             dev->gpio_regs[addr] = val & 8;
-        break;
+            break;
 
         case 0x02:
             dev->gpio_regs[addr] = val & 0x20;
-        break;
+            break;
 
         /* GPIO I/O Select */
         case 0x07:
             dev->gpio_regs[addr] = val & 0x1b;
-        break;
+            break;
 
         /* GPIO Level */
         case 0x0e:
             dev->gpio_regs[addr] = val;
-        break;
+            break;
 
         case 0x0f:
             dev->gpio_regs[addr] = val & 0x1b;
             dev->gpio_regs[addr] &= dev->gpio_regs[0x1b]; // Mask out whatever change if the bits aren't programmed as outputs.
-        break;
+            break;
 
         /* GPIO Blink which is not Utilized */
         case 0x1a:
             dev->gpio_regs[addr] = val & 6;
-        break;
+            break;
 
         case 0x1b:
             dev->gpio_regs[addr] = val & 0x1a;
-        break;
+            break;
 
         /* GPIO Signal Inverter */
         case 0x2d:
             dev->gpio_regs[addr] = val & 0x39;
-        break;
+            break;
     }
 }
 
-
 static uint8_t
 intel_ich2_gpio_read(uint16_t addr, void *priv)
 {
@@ -113,7 +110,7 @@ intel_ich2_gpio_read(uint16_t addr, void *priv)
 
     intel_ich2_gpio_log("Intel ICH2 GPIO: Reading 0x%02x from Register 0x%02x\n", dev->gpio_regs[addr], addr);
 
-    if(addr <= 0x2f)
+    if (addr <= 0x2f)
         return dev->gpio_regs[addr];
     else
         return 0xff;
@@ -122,12 +119,12 @@ intel_ich2_gpio_read(uint16_t addr, void *priv)
 void
 intel_ich2_gpio_base(int enable, uint16_t addr, intel_ich2_gpio_t *dev)
 {
-    if(dev->gpio_addr != 0)
+    if (dev->gpio_addr != 0)
         io_removehandler(dev->gpio_addr, 15, intel_ich2_gpio_read, NULL, NULL, intel_ich2_gpio_write, NULL, NULL, dev);
 
     dev->gpio_addr = addr;
 
-    if((addr != 0) && enable)
+    if ((addr != 0) && enable)
         io_sethandler(addr, 15, intel_ich2_gpio_read, NULL, NULL, intel_ich2_gpio_write, NULL, NULL, dev);
 }
 
@@ -135,7 +132,7 @@ static void
 intel_ich2_gpio_reset(void *priv)
 {
     intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) priv;
-    dev->gpio_addr = 0;
+    dev->gpio_addr         = 0;
 
     /* Enabled GPIO's */
     dev->gpio_regs[0x00] = 0x80;
@@ -153,7 +150,6 @@ intel_ich2_gpio_reset(void *priv)
     dev->gpio_regs[0x17] = 0x06;
 }
 
-
 static void
 intel_ich2_gpio_close(void *priv)
 {
@@ -162,7 +158,6 @@ intel_ich2_gpio_close(void *priv)
     free(dev);
 }
 
-
 static void *
 intel_ich2_gpio_init(const device_t *info)
 {
@@ -175,15 +170,15 @@ intel_ich2_gpio_init(const device_t *info)
 }
 
 const device_t intel_ich2_gpio_device = {
-    .name = "Intel ICH2 GPIO",
+    .name          = "Intel ICH2 GPIO",
     .internal_name = "intel_ich2_gpio",
-    .flags = 0,
-    .local = 0,
-    .init = intel_ich2_gpio_init,
-    .close = intel_ich2_gpio_close,
-    .reset = intel_ich2_gpio_reset,
+    .flags         = 0,
+    .local         = 0,
+    .init          = intel_ich2_gpio_init,
+    .close         = intel_ich2_gpio_close,
+    .reset         = intel_ich2_gpio_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/device/intel_ich2_trap.c b/src/device/intel_ich2_trap.c
index 084d791f9..856aff788 100644
--- a/src/device/intel_ich2_trap.c
+++ b/src/device/intel_ich2_trap.c
@@ -43,13 +43,13 @@ intel_ich2_trap_log(const char *fmt, ...)
     va_list ap;
 
     if (intel_ich2_trap_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define intel_ich2_trap_log(fmt, ...)
+#    define intel_ich2_trap_log(fmt, ...)
 #endif
 
 void
@@ -70,9 +70,9 @@ void
 intel_ich2_device_trap_setup(uint8_t acpi_reg, uint8_t acpi_reg_val, uint16_t addr, uint16_t size, intel_ich2_trap_t *dev)
 {
     uint8_t acpi_reg_recieve = dev->acpi->regs.devtrap_en >> ((acpi_reg & 1) * 8); /* Trap register is 16-bit on ranged ACPIBASE + 48h-49h */
-    int enable = !!(acpi_reg_recieve & acpi_reg_val); /* If enabled. Settle in the I/O trap */
+    int     enable           = !!(acpi_reg_recieve & acpi_reg_val);                /* If enabled. Settle in the I/O trap */
 
-    if(enable)
+    if (enable)
         intel_ich2_trap_log("Intel ICH2 Trap: A new trap was setted up on address 0x%x with the size of %d\n", addr, size);
 
     io_trap_remap(dev->trap, enable, addr, size);
@@ -101,15 +101,15 @@ intel_ich2_trap_init(const device_t *info)
 }
 
 const device_t intel_ich2_trap_device = {
-    .name = "Intel ICH2 Trap Hander",
+    .name          = "Intel ICH2 Trap Hander",
     .internal_name = "intel_ich2_trap",
-    .flags = 0,
-    .local = 0,
-    .init = intel_ich2_trap_init,
-    .close = intel_ich2_trap_close,
-    .reset = NULL,
+    .flags         = 0,
+    .local         = 0,
+    .init          = intel_ich2_trap_init,
+    .close         = intel_ich2_trap_close,
+    .reset         = NULL,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/device/pci_bridge.c b/src/device/pci_bridge.c
index a1bdd2c77..3ab6bdc78 100644
--- a/src/device/pci_bridge.c
+++ b/src/device/pci_bridge.c
@@ -531,8 +531,7 @@ pci_bridge_init(const device_t *info)
 
     dev->slot = pci_add_card(AGP_BRIDGE(dev->local) ? PCI_ADD_AGPBRIDGE : PCI_ADD_BRIDGE, pci_bridge_read, pci_bridge_write, dev);
 
-    if ((info->local != PCI_BRIDGE_INTEL_ICH2) && (info->local != AGP_BRIDGE_INTEL_815EP)) /* Let the machine configuration slot handle the absurd interrupt tables */
-    {
+    if ((info->local != PCI_BRIDGE_INTEL_ICH2) && (info->local != AGP_BRIDGE_INTEL_815EP)) { /* Let the machine configuration slot handle the absurd interrupt tables */
         interrupt_count = sizeof(interrupts);
         interrupt_mask = interrupt_count - 1;
         if (dev->slot < 32) {
diff --git a/src/device/tco.c b/src/device/tco.c
index aaad472fc..4072c0569 100644
--- a/src/device/tco.c
+++ b/src/device/tco.c
@@ -44,16 +44,15 @@ tco_log(const char *fmt, ...)
     va_list ap;
 
     if (tco_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define tco_log(fmt, ...)
+#    define tco_log(fmt, ...)
 #endif
 
-
 void
 tco_timer_handler(void *priv)
 {
@@ -61,7 +60,6 @@ tco_timer_handler(void *priv)
     // tco_t *dev = (tco_t *) priv;
 }
 
-
 void
 tco_irq_update(tco_t *dev, uint16_t new_irq)
 {
@@ -75,7 +73,7 @@ tco_write(uint16_t addr, uint8_t val, tco_t *dev)
     addr -= 0x60;
     tco_log("TCO: Write 0x%02x to Register 0x%02x\n", val, addr);
 
-    switch(addr) {
+    switch (addr) {
         case 0x00:
             dev->regs[addr] = val;
             break;
@@ -133,7 +131,6 @@ tco_write(uint16_t addr, uint8_t val, tco_t *dev)
     }
 }
 
-
 uint8_t
 tco_read(uint16_t addr, tco_t *dev)
 {
@@ -142,11 +139,10 @@ tco_read(uint16_t addr, tco_t *dev)
     if (addr <= 0x10) {
         tco_log("TCO: Read 0x%02x from Register 0x%02x\n", dev->regs[addr], addr);
         return dev->regs[addr];
-    }
-    else return 0;
+    } else
+        return 0;
 }
 
-
 static void
 tco_reset(void *priv)
 {
@@ -159,7 +155,6 @@ tco_reset(void *priv)
     dev->regs[0x10] = 0x03;
 }
 
-
 static void
 tco_close(void *priv)
 {
@@ -168,7 +163,6 @@ tco_close(void *priv)
     free(dev);
 }
 
-
 static void *
 tco_init(const device_t *info)
 {
@@ -181,15 +175,15 @@ tco_init(const device_t *info)
 }
 
 const device_t tco_device = {
-    .name = "Intel TCO",
+    .name          = "Intel TCO",
     .internal_name = "tco",
-    .flags = 0,
-    .local = 0,
-    .init = tco_init,
-    .close = tco_close,
-    .reset = tco_reset,
+    .flags         = 0,
+    .local         = 0,
+    .init          = tco_init,
+    .close         = tco_close,
+    .reset         = tco_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/dma.c b/src/dma.c
index bec16dbdd..2e589dd45 100644
--- a/src/dma.c
+++ b/src/dma.c
@@ -1178,21 +1178,21 @@ void
 dma_lpc_init(void) /* Addresses LPC DMA uses */
 {
     io_sethandler(0x1000, 16,
-		  dma_read,NULL,NULL, dma_write,NULL,NULL, NULL);
+          dma_read,NULL,NULL, dma_write,NULL,NULL, NULL);
     io_sethandler(0x1080, 8,
-		  dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
+          dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
     io_sethandler(0x10C0, 32,
-		  dma16_read,NULL,NULL, dma16_write,NULL,NULL, NULL);
+          dma16_read,NULL,NULL, dma16_write,NULL,NULL, NULL);
     io_sethandler(0x1088, 8,
-		  dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
+          dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
     io_sethandler(0x1090, 1,
-		  dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
+          dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
     io_sethandler(0x1094, 3,
-		  dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
+          dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
     io_sethandler(0x1098, 1,
-		  dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
+          dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
     io_sethandler(0x109C, 3,
-		  dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
+          dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
 }
 
 void
diff --git a/src/include/86box/acpi.h b/src/include/86box/acpi.h
index 4d84f0089..5174c1992 100644
--- a/src/include/86box/acpi.h
+++ b/src/include/86box/acpi.h
@@ -111,7 +111,7 @@ extern int		acpi_rtc_status;
 
 extern const device_t	acpi_ali_device;
 extern const device_t	acpi_intel_device;
-extern const device_t	acpi_intel_ich2_device;
+extern const device_t   acpi_intel_ich2_device;
 extern const device_t	acpi_smc_device;
 extern const device_t	acpi_via_device;
 extern const device_t	acpi_via_596b_device;
@@ -131,7 +131,7 @@ extern void		acpi_set_irq_line(acpi_t *dev, int irq_line);
 extern void		acpi_set_mirq_is_level(acpi_t *dev, int mirq_is_level);
 extern void		acpi_set_gpireg2_default(acpi_t *dev, uint8_t gpireg2_default);
 extern void		acpi_set_nvr(acpi_t *dev, nvr_t *nvr);
-extern void		acpi_set_tco(acpi_t *dev, tco_t *tco);
+extern void     acpi_set_tco(acpi_t *dev, tco_t *tco);
 extern void		acpi_set_trap_update(acpi_t *dev, void (*update)(void *priv), void *priv);
 extern uint8_t		acpi_ali_soft_smi_status_read(acpi_t *dev);
 extern void		acpi_ali_soft_smi_status_write(acpi_t *dev, uint8_t soft_smi);
diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h
index 578dcef1e..7417eee82 100644
--- a/src/include/86box/chipset.h
+++ b/src/include/86box/chipset.h
@@ -88,6 +88,7 @@ extern const device_t	i440gx_device;
 extern const device_t	i440zx_device;
 extern const device_t	i450kx_device;
 
+
 extern const device_t	sio_device;
 extern const device_t	sio_zb_device;
 
@@ -102,6 +103,10 @@ extern const device_t	slc90e66_device;
 
 extern const device_t	ioapic_device;
 
+/* Intel ICH2 */
+extern const device_t   intel_815ep_device;
+extern const device_t   intel_ich2_device;
+
 /* OPTi */
 extern const device_t	opti283_device;
 extern const device_t	opti291_device;
@@ -125,10 +130,6 @@ extern const device_t	sis_85c50x_device;
 extern const device_t	sis_5511_device;
 extern const device_t	sis_5571_device;
 
-/* Intel ICH2 */
-extern const device_t	intel_815ep_device;
-extern const device_t   intel_ich2_device;
-
 /* ST */
 extern const device_t	stpc_client_device;
 extern const device_t	stpc_consumer2_device;
diff --git a/src/include/86box/dma.h b/src/include/86box/dma.h
index 2c7f63d57..6a2bc72f2 100644
--- a/src/include/86box/dma.h
+++ b/src/include/86box/dma.h
@@ -93,7 +93,7 @@ extern void	dma_alias_set_piix(void);
 extern void	dma_alias_remove(void);
 extern void	dma_alias_remove_piix(void);
 
-extern void	dma_lpc_init(void);
+extern void dma_lpc_init(void);
 
 extern void	dma_bm_read(uint32_t PhysAddress, uint8_t *DataRead, uint32_t TotalSize, int TransferSize);
 extern void	dma_bm_write(uint32_t PhysAddress, const uint8_t *DataWrite, uint32_t TotalSize, int TransferSize);
diff --git a/src/include/86box/intel_ich2_gpio.h b/src/include/86box/intel_ich2_gpio.h
index 95db5d27b..86acf944f 100644
--- a/src/include/86box/intel_ich2_gpio.h
+++ b/src/include/86box/intel_ich2_gpio.h
@@ -17,24 +17,23 @@
  */
 
 #ifndef EMU_INTEL_ICH2_GPIO_H
-# define EMU_INTEL_ICH2_GPIO_H
+#define EMU_INTEL_ICH2_GPIO_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef struct intel_ich2_gpio_t
-{
+typedef struct intel_ich2_gpio_t {
     uint16_t gpio_addr;
-    uint8_t gpio_regs[48];
+    uint8_t  gpio_regs[48];
 } intel_ich2_gpio_t;
 
 void intel_ich2_gpio_base(int enable, uint16_t addr, intel_ich2_gpio_t *dev);
 
-extern const device_t   intel_ich2_gpio_device;
+extern const device_t intel_ich2_gpio_device;
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif	/*EMU_INTEL_ICH2_GPIO_H*/
+#endif /*EMU_INTEL_ICH2_GPIO_H*/
diff --git a/src/include/86box/intel_ich2_trap.h b/src/include/86box/intel_ich2_trap.h
index 153c4616f..fb6814450 100644
--- a/src/include/86box/intel_ich2_trap.h
+++ b/src/include/86box/intel_ich2_trap.h
@@ -17,25 +17,24 @@
  */
 
 #ifndef EMU_INTEL_ICH2_TRAP_H
-# define EMU_INTEL_ICH2_TRAP_H
+#define EMU_INTEL_ICH2_TRAP_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef struct intel_ich2_trap_t
-{
-    acpi_t  *acpi;
-    void *trap;
+typedef struct intel_ich2_trap_t {
+    acpi_t *acpi;
+    void   *trap;
 } intel_ich2_trap_t;
 
 extern void intel_ich2_trap_set_acpi(intel_ich2_trap_t *trap, acpi_t *acpi);
 extern void intel_ich2_device_trap_setup(uint8_t acpi_reg, uint8_t acpi_reg_val, uint16_t addr, uint16_t size, intel_ich2_trap_t *dev);
 
-extern const device_t   intel_ich2_trap_device;
+extern const device_t intel_ich2_trap_device;
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif	/*EMU_INTEL_ICH2_TRAP_H*/
+#endif /*EMU_INTEL_ICH2_TRAP_H*/
diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h
index d5ce76a4c..224ffe833 100644
--- a/src/include/86box/machine.h
+++ b/src/include/86box/machine.h
@@ -161,7 +161,6 @@ enum {
     MACHINE_TYPE_SLOT1_370,
     MACHINE_TYPE_SLOT2,
     MACHINE_TYPE_SOCKET370,
-    MACHINE_TYPE_ICH2,
     MACHINE_TYPE_MISC,
     MACHINE_TYPE_MAX
 };
diff --git a/src/include/86box/nsc366.h b/src/include/86box/nsc366.h
index f2e47bf1f..6f8c1b5f8 100644
--- a/src/include/86box/nsc366.h
+++ b/src/include/86box/nsc366.h
@@ -17,7 +17,7 @@
  */
 
 #ifndef EMU_NSC_366_H
-# define EMU_NSC_366_H
+#define EMU_NSC_366_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -27,17 +27,17 @@ typedef struct
 {
     hwm_values_t *values;
 
-    uint8_t fscm_enable;
+    uint8_t  fscm_enable;
     uint16_t fscm_addr;
-    uint8_t fscm_config[15];
+    uint8_t  fscm_config[15];
 
     uint16_t vlm_addr;
-    uint8_t vlm_config_global[10];
-    uint8_t vlm_config_bank[13][5];
+    uint8_t  vlm_config_global[10];
+    uint8_t  vlm_config_bank[13][5];
 
     uint16_t tms_addr;
-    uint8_t tms_config_global[10];
-    uint8_t tms_config_bank[4][5];
+    uint8_t  tms_config_global[10];
+    uint8_t  tms_config_bank[4][5];
 } nsc366_hwm_t;
 
 extern void nsc366_update_fscm_io(int enable, uint16_t addr, nsc366_hwm_t *dev);
@@ -45,10 +45,10 @@ extern void nsc366_update_vlm_io(int enable, uint16_t addr, nsc366_hwm_t *dev);
 extern void nsc366_update_tms_io(int enable, uint16_t addr, nsc366_hwm_t *dev);
 
 /* The Hardware Monitor */
-extern const device_t   nsc366_hwm_device;
+extern const device_t nsc366_hwm_device;
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif	/*EMU_NSC_366_H*/
+#endif /*EMU_NSC_366_H*/
diff --git a/src/include/86box/sio.h b/src/include/86box/sio.h
index c26e91dbf..3d8eb46fe 100644
--- a/src/include/86box/sio.h
+++ b/src/include/86box/sio.h
@@ -79,8 +79,8 @@ extern const device_t	sio_detect_device;
 #endif
 extern const device_t	um8669f_device;
 extern const device_t	via_vt82c686_sio_device;
-extern const device_t	w83627hf_device;
-extern const device_t	w83627hf_no_hwm_device;
+extern const device_t   w83627hf_device;
+extern const device_t   w83627hf_no_hwm_device;
 extern const device_t	w83787f_device;
 extern const device_t	w83787f_ide_device;
 extern const device_t	w83787f_ide_en_device;
diff --git a/src/include/86box/snd_ac97_intel.h b/src/include/86box/snd_ac97_intel.h
index 35a708e44..432a5dbf5 100644
--- a/src/include/86box/snd_ac97_intel.h
+++ b/src/include/86box/snd_ac97_intel.h
@@ -16,36 +16,34 @@
  *
  */
 
-
 /*
  * Note: The Intel AC'97 code is divided into three parts
  *
  * 1. intel_ac97.c The main AC'97 code handling configuration.
  * 3. intel_ac97_buffer.c The AC'97 buffer
- * 
- * 
+ *
+ *
  * The general AC'97 configures the buffer base address and capabilities like channels, reset, interrupts etc.
  * The AC'97 buffer is where all playback happens.
-*/
+ */
 
 #ifndef EMU_INTEL_AC97_H
-# define EMU_INTEL_AC97_H
+#define EMU_INTEL_AC97_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 #include <86box/mem.h>
 #include <86box/snd_ac97.h>
 
-typedef struct intel_ac97_t
-{
+typedef struct intel_ac97_t {
     uint16_t ac97_base;
     uint16_t mixer_base;
     uint32_t buffer_base;
 
     uint8_t regs[256];
-    int irq;
+    int     irq;
 
-    ac97_codec_t *mixer;
+    ac97_codec_t  *mixer;
     mem_mapping_t *buffer_location;
 } intel_ac97_t;
 
@@ -54,11 +52,11 @@ extern void intel_ac97_base(int enable, uint16_t addr, intel_ac97_t *dev);
 extern void intel_ac97_mixer_base(int enable, uint16_t addr, intel_ac97_t *dev);
 extern void intel_ac97_set_irq(int irq, intel_ac97_t *dev);
 
-extern const device_t   intel_ac97_device;
-extern const device_t   intel_ac97_mixer_device;
+extern const device_t intel_ac97_device;
+extern const device_t intel_ac97_mixer_device;
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif	/*EMU_INTEL_AC97_H*/
+#endif /*EMU_INTEL_AC97_H*/
diff --git a/src/include/86box/spd.h b/src/include/86box/spd.h
index 6b958a919..ad5e52bbb 100644
--- a/src/include/86box/spd.h
+++ b/src/include/86box/spd.h
@@ -92,26 +92,26 @@ typedef struct {
 } spd_sdram_t;
 
 typedef struct {
-    uint8_t	bytes_used, spd_size, mem_type,
-    		row_bits, col_bits, rows,
-    		data_width_lsb, data_width_msb,
-    		signal_level, tclk, tac,
-    		config, refresh_rate,
-    		sdram_width, ecc_width,
-    		tccd, burst, banks, cas, cslat, we,
-    		mod_attr, dev_attr,
-    		tclk2, tac2, tclk3, tac3,
-    		trp, trrd, trcd, tras,
-    		bank_density,
-    		ca_setup, ca_hold, data_setup, data_hold,
-    		reserved[26],
-    		spd_rev, checksum,
-    		mfg_jedec[8], mfg_loc;
-    char	part_no[18];
-    uint8_t	rev_code[2],
-    		mfg_year, mfg_week, serial[4], mfg_specific[27],
-    		other_data[127],
-    		checksum2;
+    uint8_t bytes_used, spd_size, mem_type,
+            row_bits, col_bits, rows,
+            data_width_lsb, data_width_msb,
+            signal_level, tclk, tac,
+            config, refresh_rate,
+            sdram_width, ecc_width,
+            tccd, burst, banks, cas, cslat, we,
+            mod_attr, dev_attr,
+            tclk2, tac2, tclk3, tac3,
+            trp, trrd, trcd, tras,
+            bank_density,
+            ca_setup, ca_hold, data_setup, data_hold,
+            reserved[26],
+            spd_rev, checksum,
+            mfg_jedec[8], mfg_loc;
+    char    part_no[18];
+    uint8_t rev_code[2],
+            mfg_year, mfg_week, serial[4], mfg_specific[27],
+            other_data[127],
+            checksum2;
 } spd_ddr_t;
 
 typedef struct {
@@ -124,7 +124,7 @@ typedef struct {
 	uint8_t	data[SPD_DATA_SIZE];
 	spd_edo_t edo_data;
 	spd_sdram_t sdram_data;
-	spd_ddr_t ddr_data;
+        spd_ddr_t ddr_data;
     };
     void	*eeprom;
 } spd_t;
diff --git a/src/include/86box/tco.h b/src/include/86box/tco.h
index 4d2ef21f4..aa2706560 100644
--- a/src/include/86box/tco.h
+++ b/src/include/86box/tco.h
@@ -17,7 +17,7 @@
  */
 
 #ifndef EMU_TCO_H
-# define EMU_TCO_H
+#define EMU_TCO_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,14 +25,14 @@ extern "C" {
 
 typedef struct
 {
-    uint8_t regs[17];
+    uint8_t  regs[17];
     uint16_t tco_irq;
 } tco_t;
 
-extern const device_t   tco_device;
+extern const device_t tco_device;
 
-extern void tco_irq_update(tco_t *dev, uint16_t new_irq);
-extern void tco_write(uint16_t addr, uint8_t val, tco_t *dev);
+extern void    tco_irq_update(tco_t *dev, uint16_t new_irq);
+extern void    tco_write(uint16_t addr, uint8_t val, tco_t *dev);
 extern uint8_t tco_read(uint16_t addr, tco_t *dev);
 
 #ifdef __cplusplus
diff --git a/src/machine/m_at_ich2.c b/src/machine/m_at_ich2.c
index 28b4d22e2..ac59fd05f 100644
--- a/src/machine/m_at_ich2.c
+++ b/src/machine/m_at_ich2.c
@@ -38,12 +38,12 @@
 
 /*
  * ASUS CUSL2-C
- * 
+ *
  * North Bridge: Intel 815EP
  * Super I/O: ITE IT8702
  * BIOS: Award Medallion 6.0
  * Notes: None
-*/
+ */
 int
 machine_at_cusl2c_init(const machine_t *model)
 {
@@ -69,25 +69,25 @@ machine_at_cusl2c_init(const machine_t *model)
     pci_register_bus_slot(2, 0x0d, PCI_CARD_NORMAL,      6, 7, 8, 5);
     pci_register_bus_slot(2, 0x0e, PCI_CARD_NORMAL,      3, 4, 1, 2);
 
-    device_add(&intel_815ep_device); /* Intel 815EP MCH */
-    device_add(&intel_ich2_device); /* Intel ICH2 */
-    device_add(&it8702_device); /* ITE IT8702 */
+    device_add(&intel_815ep_device);       /* Intel 815EP MCH */
+    device_add(&intel_ich2_device);        /* Intel ICH2 */
+    device_add(&it8702_device);            /* ITE IT8702 */
     device_add(&sst_flash_49lf002_device); /* SST 2Mbit Firmware Hub */
-    device_add(&as99127f_device); /* ASUS Hardware Monitor */
-    ics9xxx_get(ICS9150_08); /* ICS Clock Chip */
-    intel_815ep_spd_init(); /* SPD */
+    device_add(&as99127f_device);          /* ASUS Hardware Monitor */
+    ics9xxx_get(ICS9150_08);               /* ICS Clock Chip */
+    intel_815ep_spd_init();                /* SPD */
 
     return ret;
 }
 
 /*
  * Biostar M6TSL
- * 
+ *
  * North Bridge: Intel 815E
  * Super I/O: National Semiconductor NSC366 (PC87366)
  * BIOS: Award BIOS 6.00PG
  * Notes: No integrated ESS Solo & GPU
-*/
+ */
 int
 machine_at_m6tsl_init(const machine_t *model)
 {
@@ -112,9 +112,9 @@ machine_at_m6tsl_init(const machine_t *model)
     pci_register_bus_slot(2, 0x06, PCI_CARD_NORMAL,      5, 6, 7, 8);
     pci_register_bus_slot(2, 0x07, PCI_CARD_NORMAL,      6, 7, 8, 1);
 
-    device_add(&intel_815ep_device); /* Intel 815EP MCH */
-    device_add(&intel_ich2_device); /* Intel ICH2 */
-    device_add(&nsc366_device); /* National Semiconductor NSC366 */
+    device_add(&intel_815ep_device);       /* Intel 815EP MCH */
+    device_add(&intel_ich2_device);        /* Intel ICH2 */
+    device_add(&nsc366_device);            /* National Semiconductor NSC366 */
     device_add(&sst_flash_49lf004_device); /* SST 4Mbit Firmware Hub */
 //    device_add(ics9xxx_get(ICS9250_08)); /* ICS Clock Chip */
     spd_register(SPD_TYPE_SDRAM, 0x7, 512);
@@ -124,12 +124,12 @@ machine_at_m6tsl_init(const machine_t *model)
 
 /*
  * Biostar M6TSS
- * 
+ *
  * North Bridge: Intel 815EP
  * Super I/O: National Semiconductor NSC366 (PC87366)
  * BIOS: AwardBIOS 6.00PG
- * Notes: 
-*/
+ * Notes:
+ */
 int
 machine_at_m6tss_init(const machine_t *model)
 {
@@ -155,11 +155,11 @@ machine_at_m6tss_init(const machine_t *model)
     pci_register_bus_slot(2, 0x06, PCI_CARD_NORMAL,      4, 1, 2, 3); // 0x0a
     pci_register_bus_slot(2, 0x07, PCI_CARD_NORMAL,      1, 2, 3, 4);
 
-    device_add(&intel_815ep_device); /* Intel 815EP MCH */
-    device_add(&intel_ich2_device); /* Intel ICH2 */
-    device_add(&nsc366_device); /* National Semiconductor NSC366 */
+    device_add(&intel_815ep_device);       /* Intel 815EP MCH */
+    device_add(&intel_ich2_device);        /* Intel ICH2 */
+    device_add(&nsc366_device);            /* National Semiconductor NSC366 */
     device_add(&sst_flash_49lf004_device); /* SST 4Mbit Firmware Hub */
-    device_add(ics9xxx_get(ICS9250_08)); /* ICS Clock Chip */
+    device_add(ics9xxx_get(ICS9250_08));   /* ICS Clock Chip */
     spd_register(SPD_TYPE_SDRAM, 0x7, 512);
 
     return ret;
@@ -167,12 +167,12 @@ machine_at_m6tss_init(const machine_t *model)
 
 /*
  * Tyan Tomcat 815T (S2080)
- * 
+ *
  * North Bridge: Intel 815EP
  * Super I/O: National Semiconductor NSC366 (PC87366)
  * BIOS: AMIBIOS 7 (AMI Home BIOS Fork)
  * Notes: None
-*/
+ */
 int
 machine_at_s2080_init(const machine_t *model)
 {
@@ -197,9 +197,9 @@ machine_at_s2080_init(const machine_t *model)
     pci_register_bus_slot(2, 0x06, PCI_CARD_NORMAL,      4, 5, 6, 7);
     pci_register_bus_slot(2, 0x07, PCI_CARD_NORMAL,      5, 6, 7, 8);
 
-    device_add(&intel_815ep_device); /* Intel 815EP MCH */
-    device_add(&intel_ich2_device); /* Intel ICH2 */
-    device_add(&nsc366_device); /* National Semiconductor NSC366 */
+    device_add(&intel_815ep_device);       /* Intel 815EP MCH */
+    device_add(&intel_ich2_device);        /* Intel ICH2 */
+    device_add(&nsc366_device);            /* National Semiconductor NSC366 */
     device_add(&sst_flash_49lf004_device); /* SST 4Mbit Firmware Hub */
     spd_register(SPD_TYPE_SDRAM, 0x7, 512);
 
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index 0bb80c916..bd96f5f0e 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -77,7 +77,6 @@ const machine_filter_t machine_types[] = {
     { "Slot 1/Socket 370",         MACHINE_TYPE_SLOT1_370  },
     { "Slot 2",                    MACHINE_TYPE_SLOT2      },
     { "Socket 370",                MACHINE_TYPE_SOCKET370  },
-    { "Intel ICH2",                MACHINE_TYPE_ICH2       },
     { "Miscellaneous",             MACHINE_TYPE_MISC       }
 };
 
@@ -11713,11 +11712,12 @@ const machine_t machines[] = {
         .net_device = NULL
     },
 
-    /* Intel ICH2 */
+
+    /* Intel 815EP Motherboards */
     {
-        .name = "ASUS CUSL2-C",
+        .name = "[Intel i815EP] ASUS CUSL2-C",
         .internal_name = "cusl2c",
-        .type = MACHINE_TYPE_ICH2,
+        .type = MACHINE_TYPE_SOCKET370,
         .chipset = MACHINE_CHIPSET_INTEL_I815EP,
         .init = machine_at_cusl2c_init,
         .pad = 0,
@@ -11754,7 +11754,7 @@ const machine_t machines[] = {
     {
         .name = "[Intel i815E] Biostar M6TSL",
         .internal_name = "m6tsl",
-        .type = MACHINE_TYPE_ICH2,
+        .type = MACHINE_TYPE_SOCKET370,
         .chipset = MACHINE_CHIPSET_INTEL_I815EP,
         .init = machine_at_m6tsl_init,
         .pad = 0,
@@ -11790,7 +11790,7 @@ const machine_t machines[] = {
     {
         .name = "[Intel i815EP] Biostar M6TSS",
         .internal_name = "m6tss",
-        .type = MACHINE_TYPE_ICH2,
+        .type = MACHINE_TYPE_SOCKET370,
         .chipset = MACHINE_CHIPSET_INTEL_I815EP,
         .init = machine_at_m6tss_init,
         .pad = 0,
@@ -11826,7 +11826,7 @@ const machine_t machines[] = {
     {
         .name = "[Intel i815EP] Tyan Tomcat i815T",
         .internal_name = "s2080",
-        .type = MACHINE_TYPE_ICH2,
+        .type = MACHINE_TYPE_SOCKET370,
         .chipset = MACHINE_CHIPSET_INTEL_I815EP,
         .init = machine_at_s2080_init,
         .pad = 0,
@@ -11835,7 +11835,7 @@ const machine_t machines[] = {
         .pad2 = 0,
         .cpu = {
             .package = CPU_PKG_SOCKET370,
-            .block = CPU_BLOCK_NONE,
+            .block = CPU_BLOCK(CPU_CYRIX3S),
             .min_bus = 66666667,
             .max_bus = 133333333,
             .min_voltage = 1300,
@@ -11843,7 +11843,7 @@ const machine_t machines[] = {
             .min_multi = 1.5,
             .max_multi = 8.0
         },
-        .bus_flags = MACHINE_PS2_AGP,
+        .bus_flags = MACHINE_PS2_NOISA,
         .flags = MACHINE_IDE_DUAL,
         .ram = {
             .min = 32768,
diff --git a/src/mem/815ep_spd_hack.c b/src/mem/815ep_spd_hack.c
index 72872a15b..fef53cfe4 100644
--- a/src/mem/815ep_spd_hack.c
+++ b/src/mem/815ep_spd_hack.c
@@ -34,8 +34,7 @@
 uint8_t
 intel_815ep_get_banking()
 {
-    switch(MEM_SIZE_MB)
-    {
+    switch (MEM_SIZE_MB) {
         case 32:
             return 0x02;
 
@@ -74,50 +73,49 @@ intel_815ep_get_banking()
 void
 intel_815ep_spd_init()
 {
-    switch(MEM_SIZE_MB)
-    {
+    switch (MEM_SIZE_MB) {
         case 32:
             spd_register(SPD_TYPE_SDRAM, 1, 32);
-        break;
+            break;
 
         case 64:
             spd_register(SPD_TYPE_SDRAM, 3, 32);
-        break;
+            break;
 
         case 96:
             spd_register(SPD_TYPE_SDRAM, 7, 32);
-        break;
+            break;
 
         case 128:
             spd_register(SPD_TYPE_SDRAM, 3, 64);
-        break;
+            break;
 
         case 160:
             spd_register(SPD_TYPE_SDRAM, 7, 64);
-        break;
+            break;
 
         case 192:
             spd_register(SPD_TYPE_SDRAM, 3, 96);
-        break;
+            break;
 
         case 256:
             spd_register(SPD_TYPE_SDRAM, 3, 128);
-        break;
+            break;
 
         case 320:
             spd_register(SPD_TYPE_SDRAM, 7, 128);
-        break;
+            break;
 
         case 384:
             spd_register(SPD_TYPE_SDRAM, 7, 128);
-        break;
+            break;
 
         case 512:
             spd_register(SPD_TYPE_SDRAM, 3, 256);
-        break;
+            break;
 
         default:
             pclog("Intel 815EP SPD Hack: Illegal Size %dMB\n", MEM_SIZE_MB);
-        break;
+            break;
     }
 }
diff --git a/src/mem/spd.c b/src/mem/spd.c
index fa2c7ffe3..150a1fb60 100644
--- a/src/mem/spd.c
+++ b/src/mem/spd.c
@@ -203,9 +203,9 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
 		min_module_size = SPD_MIN_SIZE_SDRAM;
 		break;
 
-	case SPD_TYPE_DDR:
-		min_module_size = SPD_MIN_SIZE_DDR;
-		break;
+    case SPD_TYPE_DDR:
+        min_module_size = SPD_MIN_SIZE_DDR;
+        break;
 
 	default:
 		spd_log("SPD: unknown RAM type %02X\n", ram_type);
@@ -341,59 +341,59 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
 				sdram_data->checksum2 += spd_modules[slot]->data[i];
 			break;
 
-		case SPD_TYPE_DDR:
-			ddr_data = &spd_modules[slot]->ddr_data;
+        case SPD_TYPE_DDR:
+            ddr_data = &spd_modules[slot]->ddr_data;
 
-			ddr_data->bytes_used = 0x80;
-			ddr_data->spd_size = 0x08;
-			ddr_data->mem_type = ram_type;
-			ddr_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */
-			ddr_data->col_bits = 9;
-			if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
-				ddr_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */
-				ddr_data->col_bits |= 9 << 4; /* same as first row, but just in case */
-			}
-			ddr_data->rows = 2;
-			ddr_data->data_width_lsb = 64;
-			ddr_data->signal_level = SPD_SIGNAL_LVTTL;
-			ddr_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */
-			ddr_data->tac = 0x10;
-			ddr_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL;
-			ddr_data->sdram_width = 8;
-			ddr_data->tccd = 1;
-			ddr_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8;
-			ddr_data->banks = 4;
-			ddr_data->cas = 0x7f; /* CAS Latency */
-			ddr_data->cslat = ddr_data->we = 0x7f;
-			ddr_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST;
-			ddr_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */
-			ddr_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */
-			ddr_data->tac2 = ddr_data->tac3 = 0x10;
-			ddr_data->trp = ddr_data->trrd = ddr_data->trcd = ddr_data->tras = 1;
-			if (spd_modules[slot]->row1 != spd_modules[slot]->row2) {
-				/* Utilities interpret bank_density a bit differently on asymmetric modules. */
-				ddr_data->bank_density  = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */
-				ddr_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */
-			} else {
-				ddr_data->bank_density  = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */
-			}
-			ddr_data->ca_setup = ddr_data->data_setup = 0x15;
-			ddr_data->ca_hold = ddr_data->data_hold = 0x08;
+            ddr_data->bytes_used = 0x80;
+            ddr_data->spd_size = 0x08;
+            ddr_data->mem_type = ram_type;
+            ddr_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */
+            ddr_data->col_bits = 9;
+            if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
+                ddr_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */
+                ddr_data->col_bits |= 9 << 4; /* same as first row, but just in case */
+            }
+            ddr_data->rows = 2;
+            ddr_data->data_width_lsb = 64;
+            ddr_data->signal_level = SPD_SIGNAL_LVTTL;
+            ddr_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */
+            ddr_data->tac = 0x10;
+            ddr_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL;
+            ddr_data->sdram_width = 8;
+            ddr_data->tccd = 1;
+            ddr_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8;
+            ddr_data->banks = 4;
+            ddr_data->cas = 0x7f; /* CAS Latency */
+            ddr_data->cslat = ddr_data->we = 0x7f;
+            ddr_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST;
+            ddr_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */
+            ddr_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */
+            ddr_data->tac2 = ddr_data->tac3 = 0x10;
+            ddr_data->trp = ddr_data->trrd = ddr_data->trcd = ddr_data->tras = 1;
+            if (spd_modules[slot]->row1 != spd_modules[slot]->row2) {
+                /* Utilities interpret bank_density a bit differently on asymmetric modules. */
+                ddr_data->bank_density  = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */
+                ddr_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */
+            } else {
+                ddr_data->bank_density  = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */
+            }
+            ddr_data->ca_setup = ddr_data->data_setup = 0x15;
+            ddr_data->ca_hold = ddr_data->data_hold = 0x08;
 
-			ddr_data->spd_rev = 0x10;
-			for (i = spd_write_part_no(ddr_data->part_no, "DDR", rows[row]);
-			     i < sizeof(ddr_data->part_no); i++)
-				ddr_data->part_no[i] = ' '; /* part number should be space-padded */
-			ddr_data->rev_code[0] = BCD8(EMU_VERSION_MAJ);
-			ddr_data->rev_code[1] = BCD8(EMU_VERSION_MIN);
-			ddr_data->mfg_year = 20;
-			ddr_data->mfg_week = 13;
+            ddr_data->spd_rev = 0x10;
+            for (i = spd_write_part_no(ddr_data->part_no, "DDR", rows[row]);
+                 i < sizeof(ddr_data->part_no); i++)
+                 ddr_data->part_no[i] = ' '; /* part number should be space-padded */
+            ddr_data->rev_code[0] = BCD8(EMU_VERSION_MAJ);
+            ddr_data->rev_code[1] = BCD8(EMU_VERSION_MIN);
+            ddr_data->mfg_year = 20;
+            ddr_data->mfg_week = 13;
 
-			for (i = 0; i < 63; i++)
-				ddr_data->checksum += spd_modules[slot]->data[i];
-			for (i = 0; i < 129; i++)
-				ddr_data->checksum2 += spd_modules[slot]->data[i];
-			break;
+            for (i = 0; i < 63; i++)
+                ddr_data->checksum += spd_modules[slot]->data[i];
+            for (i = 0; i < 129; i++)
+                ddr_data->checksum2 += spd_modules[slot]->data[i];
+            break;
 	}
 
 	row++;
diff --git a/src/pic.c b/src/pic.c
index e33ad69a7..a6550ebe8 100644
--- a/src/pic.c
+++ b/src/pic.c
@@ -545,8 +545,8 @@ pic_set_pci(void)
     }
 
     for (i = 0xff20; i < 0xff40; i += 4) {
-	io_sethandler(i, 0x0002, pic_read, NULL, NULL, pic_write, NULL, NULL, &pic);
-	io_sethandler(i + 0x0080, 0x0002, pic_read, NULL, NULL, pic_write, NULL, NULL, &pic2);
+        io_sethandler(i, 0x0002, pic_read, NULL, NULL, pic_write, NULL, NULL, &pic);
+        io_sethandler(i + 0x0080, 0x0002, pic_read, NULL, NULL, pic_write, NULL, NULL, &pic2);
     }
 }
 
diff --git a/src/sio/sio_it8702.c b/src/sio/sio_it8702.c
index 504be0a3a..633057223 100644
--- a/src/sio/sio_it8702.c
+++ b/src/sio/sio_it8702.c
@@ -45,14 +45,14 @@ typedef struct
 {
     int ldn, unlock;
 
-    uint8_t	index, regs[15], sw_lock,
-            enable[11],
-            b_addr[4][11],
-            irq[11],
-            dma[11],
-            d_spec[15][11];
+    uint8_t index, regs[15], sw_lock,
+        enable[11],
+        b_addr[4][11],
+        irq[11],
+        dma[11],
+        d_spec[15][11];
 
-    fdc_t *fdc;
+    fdc_t    *fdc;
     serial_t *uart[2];
 } it8702_t;
 
@@ -64,22 +64,21 @@ it8702_log(const char *fmt, ...)
     va_list ap;
 
     if (it8702_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define it8702_log(fmt, ...)
+#    define it8702_log(fmt, ...)
 #endif
 
 static void it8702_reset(void *priv);
 
-
 static void
 it8702_unlock(uint8_t val, it8702_t *dev)
 {
-    if(val == 0x87) { /* The unlock mechanism of the CUSL2-C doesn't work as intended so we just unlock it with 87h only for now */
+    if (val == 0x87) { /* The unlock mechanism of the CUSL2-C doesn't work as intended so we just unlock it with 87h only for now */
         it8702_log("IT8702 Unlock: Unlocking\n");
         dev->unlock = 1;
     }
@@ -88,7 +87,7 @@ it8702_unlock(uint8_t val, it8702_t *dev)
 static void
 it8702_sw_lock(uint8_t val, it8702_t *dev)
 {
-    if(val & 0x80)
+    if (val & 0x80)
         dev->sw_lock = val;
     else
         dev->sw_lock = 0;
@@ -98,17 +97,17 @@ static void
 it8702_fdc(it8702_t *dev)
 {
     uint16_t base = ((dev->b_addr[0][0] & 0x0f) << 8) | (dev->b_addr[1][0] & 0xf8);
-    int irq = dev->irq[0];
-    int dma = dev->dma[0];
+    int      irq  = dev->irq[0];
+    int      dma  = dev->dma[0];
     fdc_remove(dev->fdc);
 
-    if(dev->enable[0] & 1) {
+    if (dev->enable[0] & 1) {
         it8702_log("IT8702 FDC: Enabled with Base: 0x%x IRQ: %d and DMA: %d\n", base, irq, dma);
         fdc_set_base(dev->fdc, base);
         fdc_set_irq(dev->fdc, irq);
         fdc_set_dma_ch(dev->fdc, dma);
 
-        if(dev->d_spec[0][0] & 1)
+        if (dev->d_spec[0][0] & 1)
             fdc_writeprotect(dev->fdc);
 
         fdc_update_drvrate(dev->fdc, 0, dev->d_spec[1][0] & 3);
@@ -120,11 +119,10 @@ static void
 it8702_uart(int uart, it8702_t *dev)
 {
     uint16_t base = ((dev->b_addr[0][2 + uart] & 0x0f) << 8) | (dev->b_addr[1][2 + uart] & 0xf8);
-    int irq = dev->irq[2 + uart];
+    int      irq  = dev->irq[2 + uart];
     serial_remove(dev->uart[uart]);
 
-    if(dev->enable[2 + uart])
-    {
+    if (dev->enable[2 + uart]) {
         it8702_log("IT8702 Serial %c: Enabled with Base: 0x%x IRQ: %d\n", 'A' + uart, base, irq);
         serial_setup(dev->uart[uart], base, irq);
         serial_set_clock_src(dev->uart[uart], 24444444 / ((dev->d_spec[0][2 + uart] >> 1) ? 12 : 13));
@@ -135,11 +133,11 @@ static void
 it8702_lpt(it8702_t *dev)
 {
     uint16_t base = ((dev->b_addr[0][1] & 0x0f) << 8) | (dev->b_addr[1][1] & 0xf8);
-    int irq = dev->irq[1];
+    int      irq  = dev->irq[1];
     lpt1_remove();
     lpt2_remove();
 
-    if(dev->enable[1] & 1) {
+    if (dev->enable[1] & 1) {
         it8702_log("IT8702 LPT1: Enabled with Base: 0x%x IRQ: %d\n", base, irq);
         lpt1_init(base);
         lpt1_irq(irq);
@@ -150,21 +148,18 @@ it8702_lpt(it8702_t *dev)
 static void
 it8702_ldn(it8702_t *dev)
 {
-    switch(dev->ldn)
-    {
+    switch (dev->ldn) {
         case 0:
             it8702_fdc(dev);
-        break;
+            break;
 
         case 1:
             it8702_lpt(dev);
-        break;
+            break;
 
         case 2 ... 3:
             it8702_uart((dev->ldn == 3), dev);
-        break;
-
-
+            break;
     }
 }
 
@@ -173,150 +168,147 @@ it8702_write(uint16_t addr, uint8_t val, void *priv)
 {
     it8702_t *dev = (it8702_t *) priv;
 
-    if(addr == 0x2e) {
-        if(dev->unlock)
+    if (addr == 0x2e) {
+        if (dev->unlock)
             dev->index = val;
         else
             it8702_unlock(val, dev);
-    }
-    else if(addr == 0x2f) {
-        switch(dev->index)
-        {
+    } else if (addr == 0x2f) {
+        switch (dev->index) {
             /* Global Registers */
             case 0x02: /* Configure Control */
-                if(val & 2) {
+                if (val & 2) {
                     it8702_log("IT8702 Unlock: Locking\n");
                     dev->unlock = 0;
                 }
 
-                if(val & 1) {
+                if (val & 1) {
                     it8702_log("IT8702: Resetting\n");
                     it8702_reset(dev);
                 }
-            break;
+                break;
 
             case 0x07:
                 dev->ldn = val;
-            break;
+                break;
 
             case 0x23:
-                if(!(dev->sw_lock & 0x80))
+                if (!(dev->sw_lock & 0x80))
                     dev->regs[dev->index - 0x20] = val & 0xd9;
-            break;
+                break;
 
             case 0x24:
                 dev->regs[dev->index - 0x20] = val & 0x00;
-            break;
+                break;
 
             case 0x25 ... 0x28:
-                if(dev->ldn == 7)
+                if (dev->ldn == 7)
                     dev->regs[dev->index - 0x20] = val;
-            break;
+                break;
 
             case 0x29:
-                if(dev->ldn == 7)
+                if (dev->ldn == 7)
                     dev->regs[dev->index - 0x20] = val & 0x3f;
-            break;
+                break;
 
             case 0x2a:
-                if(dev->ldn == 7)
+                if (dev->ldn == 7)
                     dev->regs[dev->index - 0x20] = val & 0x7f;
-            break;
+                break;
 
             case 0x2b:
-                if(!(dev->sw_lock & 0x80)) {
+                if (!(dev->sw_lock & 0x80)) {
                     dev->regs[dev->index - 0x20] = val;
                     it8702_sw_lock(val, dev);
                 }
-            break;
+                break;
 
             case 0x2c:
                 dev->regs[dev->index - 0x20] = val & 0x1c;
-            break;
+                break;
 
             case 0x30:
-                if(dev->ldn < 11)
+                if (dev->ldn < 11)
                     dev->enable[dev->ldn] = val & 1;
 
                 it8702_ldn(dev);
-            break;
+                break;
 
             case 0x60 ... 0x63:
-                if(dev->ldn < 11)
+                if (dev->ldn < 11)
                     dev->b_addr[dev->index & 3][dev->ldn] = val;
 
                 it8702_ldn(dev);
-            break;
+                break;
 
             case 0x70:
-                if(dev->ldn < 11)
+                if (dev->ldn < 11)
                     dev->irq[dev->ldn] = val & 0x0f;
 
                 it8702_ldn(dev);
-            break;
+                break;
 
             case 0x74:
-                if(dev->ldn < 11)
+                if (dev->ldn < 11)
                     dev->dma[dev->ldn] = val & 0x0f;
 
                 it8702_ldn(dev);
-            break;
+                break;
 
             case 0xf0 ... 0xf0:
-                if(dev->ldn < 11)
+                if (dev->ldn < 11)
                     dev->d_spec[dev->index & 0x0f][dev->ldn] = val;
 
                 it8702_ldn(dev);
-            break;
+                break;
         }
     }
 }
 
-
 static uint8_t
 it8702_read(uint16_t addr, void *priv)
 {
     it8702_t *dev = (it8702_t *) priv;
 
-    if(addr == 0x2e) {
+    if (addr == 0x2e) {
         return dev->index;
-    } else if(addr == 0x2f) {
-        if(dev->index == 0x02) { /* The Configure Control register is Write Only */
+    } else if (addr == 0x2f) {
+        if (dev->index == 0x02) { /* The Configure Control register is Write Only */
             return 0xff;
-		} else {
-            switch(dev->index) {
+        } else {
+            switch (dev->index) {
                 case 0x07:
                     return dev->ldn;
-                
+
                 case 0x20 ... 0x2f:
                     return dev->regs[dev->index - 0x20];
-                
+
                 case 0x30:
-                    if(dev->ldn < 11)
+                    if (dev->ldn < 11)
                         return dev->enable[dev->ldn];
                     else
                         return 0xff;
-                
+
                 case 0x60 ... 0x63:
-                    if(dev->ldn < 11)
+                    if (dev->ldn < 11)
                         return dev->b_addr[dev->index & 3][dev->ldn];
                     else
                         return 0xff;
-                
+
                 case 0x70:
-                    if(dev->ldn < 11)
+                    if (dev->ldn < 11)
                         return dev->irq[dev->ldn];
                     else
                         return 0xff;
 
                 case 0x74:
-                    if(dev->ldn < 11)
+                    if (dev->ldn < 11)
                         return dev->dma[dev->ldn];
                     else
                         return 0xff;
 
                 case 0xf0 ... 0xff:
-                    if(dev->ldn < 11)
+                    if (dev->ldn < 11)
                         return dev->d_spec[dev->index & 0x0f][dev->ldn];
                     else
                         return 0xff;
@@ -330,13 +322,12 @@ it8702_read(uint16_t addr, void *priv)
     return 0xff;
 }
 
-
 static void
 it8702_reset(void *priv)
 {
     it8702_t *dev = (it8702_t *) priv;
 
-    dev->ldn = 0;
+    dev->ldn     = 0;
     dev->sw_lock = 0; // Needs implementation
 
     dev->unlock = 0; /* Lock the chip */
@@ -349,23 +340,23 @@ it8702_reset(void *priv)
     /* Floppy Disk Controller */
     dev->b_addr[0][0] = 0x03;
     dev->b_addr[1][0] = 0xf0;
-    dev->irq[0] = 0x06;
-    dev->dma[0] = 0x02;
+    dev->irq[0]       = 0x06;
+    dev->dma[0]       = 0x02;
     fdc_reset(dev->fdc);
     it8702_fdc(dev);
 
     /* LPT */
     dev->b_addr[0][1] = 0x03;
     dev->b_addr[1][1] = 0x78;
-    dev->irq[1] = 0x07;
-    dev->dma[1] = 0x03;
+    dev->irq[1]       = 0x07;
+    dev->dma[1]       = 0x03;
     dev->d_spec[0][1] = 0x03;
     it8702_lpt(dev);
 
     /* UART Serial A */
     dev->b_addr[0][2] = 0x02;
     dev->b_addr[1][2] = 0xf8;
-    dev->irq[2] = 0x04;
+    dev->irq[2]       = 0x04;
     dev->d_spec[1][2] = 0x50;
     dev->d_spec[3][2] = 0x7f;
     it8702_uart(0, dev);
@@ -373,7 +364,7 @@ it8702_reset(void *priv)
     /* UART Serial B */
     dev->b_addr[0][3] = 0x02;
     dev->b_addr[1][3] = 0x78;
-    dev->irq[3] = 0x04;
+    dev->irq[3]       = 0x04;
     dev->d_spec[1][3] = 0x50;
     dev->d_spec[3][3] = 0x7f;
     it8702_uart(1, dev);
@@ -383,18 +374,18 @@ it8702_reset(void *priv)
     dev->b_addr[1][4] = 0x90;
     dev->b_addr[2][4] = 0x02;
     dev->b_addr[3][4] = 0x30;
-    dev->irq[4] = 0x09;
+    dev->irq[4]       = 0x09;
 
     /* Keyboard Controller */
     dev->b_addr[3][5] = 0x64;
-    dev->irq[5] = 0x01;
+    dev->irq[5]       = 0x01;
 
     /* PS/2 Mouse */
     dev->irq[6] = 0x0c;
 
     /* MIDI */
     dev->b_addr[0][8] = 0x03;
-    dev->irq[8] = 0x0a;
+    dev->irq[8]       = 0x0a;
 
     /* Gameport */
     dev->b_addr[0][9] = 0x02;
@@ -403,10 +394,9 @@ it8702_reset(void *priv)
     /* IR */
     dev->b_addr[0][10] = 0x03;
     dev->b_addr[1][10] = 0x10;
-    dev->irq[10] = 0x0b;
+    dev->irq[10]       = 0x0b;
 }
 
-
 static void
 it8702_close(void *priv)
 {
@@ -415,7 +405,6 @@ it8702_close(void *priv)
     free(dev);
 }
 
-
 static void *
 it8702_init(const device_t *info)
 {
@@ -443,15 +432,15 @@ it8702_init(const device_t *info)
 }
 
 const device_t it8702_device = {
-    .name = "ITE IT8702",
+    .name          = "ITE IT8702",
     .internal_name = "it8702",
-    .flags = 0,
-    .local = 0x2e,
-    .init = it8702_init,
-    .close = it8702_close,
-    .reset = it8702_reset,
+    .flags         = 0,
+    .local         = 0x2e,
+    .init          = it8702_init,
+    .close         = it8702_close,
+    .reset         = it8702_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/sio/sio_nsc366.c b/src/sio/sio_nsc366.c
index 8608d2c9c..30baf743d 100644
--- a/src/sio/sio_nsc366.c
+++ b/src/sio/sio_nsc366.c
@@ -29,6 +29,7 @@
 #include <86box/timer.h>
 #include <86box/device.h>
 #include <86box/hwm.h>
+#include <86box/io.h>
 #include <86box/keyboard.h>
 #include <86box/lpt.h>
 #include <86box/nsc366.h>
@@ -39,22 +40,21 @@
 #include <86box/port_92.h>
 #include <86box/sio.h>
 
-
 typedef struct
 {
-    fdc_t *fdc;
-    serial_t *uart[2];
+    fdc_t        *fdc;
+    serial_t     *uart[2];
     nsc366_hwm_t *hwm;
 
     uint8_t index, ldn, sio_config[14],
-    ld_activate[15],
-    io_base0[2][15],
-    io_base1[2][15],
-    int_num_irq[15],
-    irq[15],
-    dma_select0[15],
-    dma_select1[15],
-    dev_specific_config[3][15];
+        ld_activate[15],
+        io_base0[2][15],
+        io_base1[2][15],
+        int_num_irq[15],
+        irq[15],
+        dma_select0[15],
+        dma_select1[15],
+        dev_specific_config[3][15];
 
     int siofc_lock;
 } nsc366_t;
@@ -62,29 +62,27 @@ typedef struct
 #ifdef ENABLE_NSC366_LOG
 int nsc366_do_log = ENABLE_NSC366_LOG;
 
-
 void
 nsc366_log(const char *fmt, ...)
 {
     va_list ap;
 
     if (nsc366_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define nsc366_log(fmt, ...)
+#    define nsc366_log(fmt, ...)
 #endif
 
-
 static void
 nsc366_fdc(nsc366_t *dev)
 {
     fdc_remove(dev->fdc);
-    int base = ((dev->io_base0[0][0] & 7) << 8) | (dev->io_base0[1][0] & 0xf8);
-    int irq = dev->int_num_irq[0] & 0x0f;
+    int base   = ((dev->io_base0[0][0] & 7) << 8) | (dev->io_base0[1][0] & 0xf8);
+    int irq    = dev->int_num_irq[0] & 0x0f;
     int dma_ch = dev->dma_select0[0] & 7;
 
     if (dev->ld_activate[0]) {
@@ -98,31 +96,29 @@ nsc366_fdc(nsc366_t *dev)
     }
 }
 
-
 void
 nsc366_lpt(nsc366_t *dev)
 {
     lpt1_remove();
     int base = ((dev->io_base0[0][1] & 7) << 8) | (dev->io_base0[1][1] & 0xfc);
-    int irq = (dev->int_num_irq[1] & 0x0f);
+    int irq  = (dev->int_num_irq[1] & 0x0f);
 
     if (dev->ld_activate[1]) {
-        nsc366_log("NSC 366 LPT: Reconfigured with Base 0x%04x IRQ: %d\n", base ,irq);
+        nsc366_log("NSC 366 LPT: Reconfigured with Base 0x%04x IRQ: %d\n", base, irq);
         lpt1_init(base);
         lpt1_irq(irq);
     }
 }
 
-
 static void
 nsc366_uart(int uart, nsc366_t *dev)
 {
     serial_remove(dev->uart[uart]);
     int base = ((dev->io_base0[0][2 + uart] & 7) << 8) | (dev->io_base0[1][2 + uart] & 0xf8);
-    int irq = (dev->int_num_irq[2 + uart] & 0x0f);
+    int irq  = (dev->int_num_irq[2 + uart] & 0x0f);
 
     if (dev->ld_activate[2 + uart]) {
-        nsc366_log("NSC 366 UART Serial %d: Reconfigured with Base 0x%04x IRQ: %d\n", uart, base ,irq);
+        nsc366_log("NSC 366 UART Serial %d: Reconfigured with Base 0x%04x IRQ: %d\n", uart, base, irq);
         serial_setup(dev->uart[uart], base, irq);
     }
 }
@@ -151,7 +147,6 @@ nsc366_fscm(nsc366_t *dev)
     nsc366_update_fscm_io(dev->ld_activate[9], base, dev->hwm);
 }
 
-
 static void
 nsc366_vlm(nsc366_t *dev)
 {
@@ -163,7 +158,6 @@ nsc366_vlm(nsc366_t *dev)
     nsc366_update_vlm_io(dev->ld_activate[13], base, dev->hwm);
 }
 
-
 static void
 nsc366_tms(nsc366_t *dev)
 {
@@ -175,11 +169,10 @@ nsc366_tms(nsc366_t *dev)
     nsc366_update_tms_io(dev->ld_activate[14], base, dev->hwm);
 }
 
-
 static void
 nsc366_ldn_redirect(nsc366_t *dev)
 {
-    switch(dev->ldn) {
+    switch (dev->ldn) {
         case 0:
             nsc366_fdc(dev);
             break;
@@ -207,14 +200,13 @@ nsc366_ldn_redirect(nsc366_t *dev)
     }
 }
 
-
 static void
 nsc366_write(uint16_t addr, uint8_t val, void *priv)
 {
-    nsc366_t *dev = (nsc366_t *)priv;
+    nsc366_t *dev = (nsc366_t *) priv;
 
     if (addr & 1)
-        switch(dev->index) {
+        switch (dev->index) {
             /* LDN */
             case 0x07:
                 if (val <= 0x0e)
@@ -228,7 +220,7 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
                         if (!dev->siofc_lock) {
                             if (val & 0x80) {
                                 dev->sio_config[dev->index - 0x20] = val | 0x80;
-                                dev->siofc_lock = 1;
+                                dev->siofc_lock                    = 1;
                             } else {
                                 dev->sio_config[dev->index - 0x20] = val;
                             }
@@ -301,7 +293,7 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
                 nsc366_ldn_redirect(dev);
                 break;
 
-            case 0x74: 
+            case 0x74:
                 dev->dma_select0[dev->ldn] = val & 0x1f;
                 nsc366_ldn_redirect(dev);
                 break;
@@ -315,15 +307,15 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
                 dev->dev_specific_config[dev->index - 0xf0][dev->ldn] = val;
                 nsc366_ldn_redirect(dev);
                 break;
-    } else
+        }
+    else
         dev->index = val;
 }
 
-
 static uint8_t
 nsc366_read(uint16_t addr, void *priv)
 {
-    nsc366_t *dev = (nsc366_t *)priv;
+    nsc366_t *dev = (nsc366_t *) priv;
 
     if (addr & 1) {
         switch (dev->index) {
@@ -348,7 +340,7 @@ nsc366_read(uint16_t addr, void *priv)
             case 0x71:
                 return dev->irq[dev->ldn];
 
-            case 0x74: 
+            case 0x74:
                 return dev->dma_select0[dev->ldn];
 
             case 0x75:
@@ -360,18 +352,17 @@ nsc366_read(uint16_t addr, void *priv)
             default:
                 return 0;
         }
-    }
-    else return dev->index;
+    } else
+        return dev->index;
 }
 
-
 static void
 nsc366_reset(void *priv)
 {
-    nsc366_t *dev = (nsc366_t *)priv;
+    nsc366_t *dev = (nsc366_t *) priv;
 
     /* Basic Configuration */
-    dev->ldn = 0;
+    dev->ldn        = 0;
     dev->siofc_lock = 0;
     memset(dev->sio_config, 0, sizeof(dev->sio_config));
     memset(dev->ld_activate, 0, sizeof(dev->ld_activate));
@@ -389,106 +380,104 @@ nsc366_reset(void *priv)
 
     /* FDC */
     fdc_reset(dev->fdc);
-    dev->io_base0[0][0] = 0x03;
-    dev->io_base0[1][0] = 0xf2;
-    dev->int_num_irq[0] = 0x06;
-    dev->irq[0] = 0x03;
-    dev->dma_select0[0] = 0x02;
-    dev->dma_select1[0] = 0x04;
+    dev->io_base0[0][0]            = 0x03;
+    dev->io_base0[1][0]            = 0xf2;
+    dev->int_num_irq[0]            = 0x06;
+    dev->irq[0]                    = 0x03;
+    dev->dma_select0[0]            = 0x02;
+    dev->dma_select1[0]            = 0x04;
     dev->dev_specific_config[0][0] = 0x24;
-    
+
     nsc366_fdc(dev);
 
     /* LPT */
-    dev->io_base0[0][1] = 0x02;
-    dev->io_base0[1][1] = 0x78;
-    dev->int_num_irq[1] = 0x07;
-    dev->irq[1] = 0x02;
-    dev->dma_select0[1] = 0x04;
-    dev->dma_select1[1] = 0x04;
+    dev->io_base0[0][1]            = 0x02;
+    dev->io_base0[1][1]            = 0x78;
+    dev->int_num_irq[1]            = 0x07;
+    dev->irq[1]                    = 0x02;
+    dev->dma_select0[1]            = 0x04;
+    dev->dma_select1[1]            = 0x04;
     dev->dev_specific_config[0][1] = 0xf2;
 
     /* UART Serial 2 */
-    dev->io_base0[0][2] = 0x02;
-    dev->io_base0[1][2] = 0xf8;
-    dev->int_num_irq[2] = 0x03;
-    dev->irq[2] = 0x03;
-    dev->dma_select0[2] = 0x04;
-    dev->dma_select1[2] = 0x04;
+    dev->io_base0[0][2]            = 0x02;
+    dev->io_base0[1][2]            = 0xf8;
+    dev->int_num_irq[2]            = 0x03;
+    dev->irq[2]                    = 0x03;
+    dev->dma_select0[2]            = 0x04;
+    dev->dma_select1[2]            = 0x04;
     dev->dev_specific_config[0][2] = 0x02;
 
     nsc366_uart(1, dev);
 
     /* UART Serial 1 */
-    dev->io_base0[0][3] = 0x03;
-    dev->io_base0[1][3] = 0xf8;
-    dev->int_num_irq[3] = 0x04;
-    dev->irq[3] = 0x03;
-    dev->dma_select0[3] = 0x04;
-    dev->dma_select1[3] = 0x04;
+    dev->io_base0[0][3]            = 0x03;
+    dev->io_base0[1][3]            = 0xf8;
+    dev->int_num_irq[3]            = 0x04;
+    dev->irq[3]                    = 0x03;
+    dev->dma_select0[3]            = 0x04;
+    dev->dma_select1[3]            = 0x04;
     dev->dev_specific_config[0][3] = 0x02;
 
     /* SWC */
-    dev->irq[4] = 0x03;
+    dev->irq[4]         = 0x03;
     dev->dma_select0[4] = 0x04;
 
     /* Keyboard Controller */
     dev->int_num_irq[5] = 0x0c;
-    dev->irq[5] = 0x02;
+    dev->irq[5]         = 0x02;
 
     /* Mouse Controller */
-    dev->io_base0[1][6] = 0x60;
-    dev->io_base1[1][6] = 0x64;
-    dev->int_num_irq[6] = 0x01;
-    dev->irq[6] = 0x02;
-    dev->dma_select0[6] = 0x04;
-    dev->dma_select1[6] = 0x04;
+    dev->io_base0[1][6]            = 0x60;
+    dev->io_base1[1][6]            = 0x64;
+    dev->int_num_irq[6]            = 0x01;
+    dev->irq[6]                    = 0x02;
+    dev->dma_select0[6]            = 0x04;
+    dev->dma_select1[6]            = 0x04;
     dev->dev_specific_config[0][6] = 0x40;
 
     /* GPIO */
-    dev->irq[7] = 0x03;
+    dev->irq[7]         = 0x03;
     dev->dma_select0[7] = 0x04;
     dev->dma_select1[7] = 0x04;
 
     /* ACB */
-    dev->irq[8] = 0x03;
+    dev->irq[8]         = 0x03;
     dev->dma_select0[8] = 0x04;
     dev->dma_select1[8] = 0x04;
 
     /* Fan Speed Monitor & Control */
-    dev->irq[9] = 0x03;
+    dev->irq[9]         = 0x03;
     dev->dma_select0[9] = 0x04;
     dev->dma_select1[9] = 0x04;
     nsc366_fscm_enable(dev);
     nsc366_fscm(dev);
 
     /* Voltage Level Monitor */
-    dev->irq[13] = 0x03;
+    dev->irq[13]         = 0x03;
     dev->dma_select0[13] = 0x04;
     dev->dma_select1[13] = 0x04;
     nsc366_vlm(dev);
 
     /* Temperature Monitor */
-    dev->irq[14] = 0x03;
+    dev->irq[14]         = 0x03;
     dev->dma_select0[14] = 0x04;
     dev->dma_select1[14] = 0x04;
     nsc366_tms(dev);
 }
 
-
 static void
 nsc366_close(void *priv)
 {
-    nsc366_t *dev = (nsc366_t *)priv;
+    nsc366_t *dev = (nsc366_t *) priv;
 
     free(dev);
 }
 
-
 static void *
 nsc366_init(const device_t *info)
 {
-    nsc366_t *dev = (nsc366_t *)malloc(sizeof(nsc366_t));
+    nsc366_t *dev = (nsc366_t *) malloc(sizeof(nsc366_t));
     memset(dev, 0, sizeof(nsc366_t));
 
     io_sethandler(info->local, 2, nsc366_read, NULL, NULL, nsc366_write, NULL, NULL, dev); /* Ports 2E-2Fh(4E-4Fh if BADDR High): National Semiconductor NSC366 */
@@ -514,31 +503,30 @@ nsc366_init(const device_t *info)
     return dev;
 }
 
-
 const device_t nsc366_device = {
-    .name = "National Semiconductor NSC366",
+    .name          = "National Semiconductor NSC366",
     .internal_name = "nsc366",
-    .flags = 0,
-    .local = 0x2e,
-    .init = nsc366_init,
-    .close = nsc366_close,
-    .reset = nsc366_reset,
+    .flags         = 0,
+    .local         = 0x2e,
+    .init          = nsc366_init,
+    .close         = nsc366_close,
+    .reset         = nsc366_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
 
 const device_t nsc366_4f_device = {
-    .name = "National Semiconductor NSC366 (With BADDR Pin High)",
+    .name          = "National Semiconductor NSC366 (With BADDR Pin High)",
     .internal_name = "nsc366",
-    .flags = 0,
-    .local = 0x4e,
-    .init = nsc366_init,
-    .close = nsc366_close,
-    .reset = nsc366_reset,
+    .flags         = 0,
+    .local         = 0x4e,
+    .init          = nsc366_init,
+    .close         = nsc366_close,
+    .reset         = nsc366_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/sio/sio_w83627hf.c b/src/sio/sio_w83627hf.c
index aeacb9fb3..94fd6e377 100644
--- a/src/sio/sio_w83627hf.c
+++ b/src/sio/sio_w83627hf.c
@@ -107,7 +107,6 @@ Notes : ISAPnP is missing and the Hardware Monitor I2C is not implemented.
 #ifdef ENABLE_W83627HF_LOG
 int w83627hf_do_log = ENABLE_W83627HF_LOG;
 
-
 static void
 w83627hf_log(const char *fmt, ...)
 {
@@ -120,21 +119,20 @@ w83627hf_log(const char *fmt, ...)
     }
 }
 #else
-#define w83627hf_log(fmt, ...)
+#    define w83627hf_log(fmt, ...)
 #endif
 
-
 typedef struct
 {
     uint8_t hwm_index, hwm_regs[256];
 
-    uint8_t	index, cfg_unlocked,
-		    regs[48], dev_regs[12][256];
+    uint8_t index, cfg_unlocked,
+        regs[48], dev_regs[12][256];
 
-    int has_hwm;
-    fdc_t *fdc_controller;
+    int        has_hwm;
+    fdc_t     *fdc_controller;
     port_92_t *port_92;
-    serial_t *uart[2];
+    serial_t  *uart[2];
 } w83627hf_t;
 
 /* These differ per board and must be programmed manually */
@@ -144,122 +142,117 @@ void
 w83627hf_stabilizer(int vcoreb, int fan1, int fan2, int fan3)
 {
     vcoreb_voltage = vcoreb;
-    fan1_rpm = fan1;
-    fan2_rpm = fan2;
-    fan3_rpm = fan3;
+    fan1_rpm       = fan1;
+    fan2_rpm       = fan2;
+    fan3_rpm       = fan3;
 }
 
 static void
 w83627hf_hwm_write(uint16_t addr, uint8_t val, void *priv)
 {
-    w83627hf_t *dev = (w83627hf_t *)priv;
+    w83627hf_t *dev = (w83627hf_t *) priv;
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x295:
             dev->hwm_index = val;
-        break;
+            break;
 
         case 0x296:
             w83627hf_log("W83627HF-HWM: dev->regs[%02x] = %02x\n", dev->hwm_index, val);
-            switch(dev->hwm_index)
-            {
+            switch (dev->hwm_index) {
                 case 0x2b ... 0x3f:
                 case 0x6b ... 0x7f:
-                     dev->hwm_regs[dev->hwm_index & 0x1f] = val;
-                break;
+                    dev->hwm_regs[dev->hwm_index & 0x1f] = val;
+                    break;
 
                 case 0x40:
                     dev->hwm_regs[dev->hwm_index] = val & 0x8b;
-                break;
+                    break;
 
                 case 0x43:
                     dev->hwm_regs[dev->hwm_index] = val;
-                break;
+                    break;
 
                 case 0x44:
                     dev->hwm_regs[dev->hwm_index] = val & 0x3f;
-                break;
+                    break;
 
                 case 0x46:
                     dev->hwm_regs[dev->hwm_index] = val & 0x80;
-                        if(val & 0x80)
-                            dev->hwm_regs[dev->hwm_index] &= 0x10;
-                break;
+                    if (val & 0x80)
+                        dev->hwm_regs[dev->hwm_index] &= 0x10;
+                    break;
 
                 case 0x47:
                     dev->hwm_regs[dev->hwm_index] = val & 0x3f;
-                break;
+                    break;
 
                 case 0x48: /* Serial Bus Address */
                     dev->hwm_regs[dev->hwm_index] = val & 0x7f;
-                break;
+                    break;
 
                 case 0x49:
                     dev->hwm_regs[dev->hwm_index] = val & 1;
-                break;
+                    break;
 
                 case 0x4a:
                     dev->hwm_regs[dev->hwm_index] = val;
-                break;
+                    break;
 
                 case 0x4b:
                     dev->hwm_regs[dev->hwm_index] = val & 0xfc;
-                break;
+                    break;
 
                 case 0x4c:
                     dev->hwm_regs[dev->hwm_index] = val & 0x5c;
-                break;
+                    break;
 
                 case 0x4d:
                     dev->hwm_regs[dev->hwm_index] = val & 0xbf;
-                break;
+                    break;
 
                 case 0x4e:
                     dev->hwm_regs[dev->hwm_index] = val;
-                break;
+                    break;
 
                 case 0x56:
                     dev->hwm_regs[dev->hwm_index] = val;
-                break;
+                    break;
 
                 case 0x57:
                     dev->hwm_regs[dev->hwm_index] = val & 0xbf;
-                break;
+                    break;
 
                 case 0x59:
                     dev->hwm_regs[dev->hwm_index] = val & 0x70;
-                break;
+                    break;
 
                 case 0x5a ... 0x5b:
                     dev->hwm_regs[dev->hwm_index] = val;
-                break;
+                    break;
 
                 case 0x5c:
                     dev->hwm_regs[dev->hwm_index] = val & 0x77;
-                break;
+                    break;
             }
-        break;
+            break;
     }
 }
 
 static uint8_t
 w83627hf_hwm_read(uint16_t addr, void *priv)
 {
-    w83627hf_t *dev = (w83627hf_t *)priv;
+    w83627hf_t *dev = (w83627hf_t *) priv;
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x295:
             return dev->hwm_index;
 
         case 0x296:
-            switch(dev->hwm_index)
-            {
+            switch (dev->hwm_index) {
                 case 0x20 ... 0x3f:
                 case 0x60 ... 0x7f:
-                    switch(dev->hwm_index & 0x1f)
-                    {
+                    switch (dev->hwm_index & 0x1f) {
                         case 0x00: /* VCOREA */
                             return hwm_get_vcore() + 0x78;
 
@@ -295,7 +288,7 @@ w83627hf_hwm_read(uint16_t addr, void *priv)
                     }
 
                 case 0x4f:
-                    if(dev->hwm_regs[0x4e] & 0x80)
+                    if (dev->hwm_regs[0x4e] & 0x80)
                         return 0x5c;
                     else
                         return 0xa3;
@@ -319,51 +312,49 @@ w83627hf_fdc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 
     fdc_remove(dev->fdc_controller);
 
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[0][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x60 ... 0x61:
             dev->dev_regs[0][cur_reg] = val;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[0][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0x74:
             dev->dev_regs[0][cur_reg] = val & 7;
-        break;
+            break;
 
         case 0xf0:
             dev->dev_regs[0][cur_reg] = val;
-        break;
+            break;
 
         case 0xf1:
             dev->dev_regs[0][cur_reg] = val;
             fdc_update_boot_drive(dev->fdc_controller, (val & 0xc0) >> 6);
 
-            if(val & 2)
+            if (val & 2)
                 fdc_writeprotect(dev->fdc_controller);
 
             fdc_set_swwp(dev->fdc_controller, val & 1);
-        break;
+            break;
 
         case 0xf2:
             dev->dev_regs[0][cur_reg] = val;
-        break;
+            break;
 
         case 0xf4:
         case 0xf5:
             dev->dev_regs[0][cur_reg] = val & 0x5b;
             fdc_update_drvrate(dev->fdc_controller, cur_reg & 1, (val & 0x18) >> 3);
-        break;
+            break;
     }
 
-    if(dev->dev_regs[0][0x30] & 1)
-    {
+    if (dev->dev_regs[0][0x30] & 1) {
         fdc_set_irq(dev->fdc_controller, dev->dev_regs[0][0x70]);
         fdc_set_dma_ch(dev->fdc_controller, dev->dev_regs[0][0x74]);
         fdc_set_base(dev->fdc_controller, (dev->dev_regs[0][0x60] << 8) | (dev->dev_regs[0][0x61]));
@@ -377,27 +368,25 @@ w83627hf_lpt_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
     lpt1_remove();
 
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[1][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x60 ... 0x61:
             dev->dev_regs[1][cur_reg] = val;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[1][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xf0:
             dev->dev_regs[1][cur_reg] = val & 0x7f;
-        break;
+            break;
     }
 
-    if(dev->dev_regs[1][0x30] & 1)
-    {
+    if (dev->dev_regs[1][0x30] & 1) {
         lpt1_init((dev->dev_regs[1][0x60] << 8) | (dev->dev_regs[1][0x61]));
         lpt1_irq(dev->dev_regs[1][0x70]);
         w83627hf_log("W83627HF-LPT: BASE: %04x IRQ: %d\n", (dev->dev_regs[1][0x60] << 8) | (dev->dev_regs[1][0x61]), dev->dev_regs[1][0x70]);
@@ -411,50 +400,47 @@ w83627hf_uart_write(int uart, uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 
     serial_remove(dev->uart[uart]);
 
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[2 + uart][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x60 ... 0x61:
             dev->dev_regs[2 + uart][cur_reg] = val;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[2 + uart][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xf0:
             dev->dev_regs[2 + uart][cur_reg] = val & 3;
-            switch(val & 3)
-            {
+            switch (val & 3) {
                 case 0:
                     uart_clock = 24000000.0 / 13.0;
-                break;
+                    break;
 
                 case 1:
                     uart_clock = 24000000.0 / 12.0;
-                break;
+                    break;
 
                 case 2:
                     uart_clock = 24000000.0 / 1.625;
-                break;
+                    break;
 
                 case 3:
                     uart_clock = 24000000.0;
-                break;
+                    break;
             }
-        break;
+            break;
 
         case 0xf1:
-            if(uart)
+            if (uart)
                 dev->dev_regs[2 + uart][cur_reg] = val & 0x7f;
-        break;
+            break;
     }
 
-    if(dev->dev_regs[2 + uart][0x30] & 1)
-    {
+    if (dev->dev_regs[2 + uart][0x30] & 1) {
         serial_setup(dev->uart[uart], (dev->dev_regs[2 + uart][0x60] << 8) | (dev->dev_regs[2 + uart][0x61]), dev->dev_regs[2 + uart][0x70]);
         serial_set_clock_src(dev->uart[uart], uart_clock);
         w83627hf_log("W83627HF-UART%s: BASE: %04x IRQ: %d\n", uart ? "B" : "A", (dev->dev_regs[2 + uart][0x60] << 8) | (dev->dev_regs[2 + uart][0x61]), dev->dev_regs[2 + uart][0x70]);
@@ -464,35 +450,33 @@ w83627hf_uart_write(int uart, uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 static void
 w83627hf_kbc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[5][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x60 ... 0x61: /* See Notes on init */
             dev->dev_regs[5][cur_reg] = val;
-        break;
+            break;
 
         case 0x62 ... 0x63: /* See Notes on init */
             dev->dev_regs[5][cur_reg] = val;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[5][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0x72:
             dev->dev_regs[5][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xf0:
             dev->dev_regs[5][cur_reg] = val & 0xc7;
-        break;
+            break;
     }
 
-    if(dev->dev_regs[5][0x30] & 1)
-    {
+    if (dev->dev_regs[5][0x30] & 1) {
         /* We don't disable Port 92h as intended because the BIOSes never enable it back, causing issues. */
         port_92_set_features(dev->port_92, !!(dev->dev_regs[5][0xf0] & 1), !!(dev->dev_regs[5][0xf0] & 2));
         w83627hf_log("W83627HF-PORT92: FASTA20: %d FASTRESET: %d\n", !!(dev->dev_regs[5][0xf0] & 2), !!(dev->dev_regs[5][0xf0] & 1));
@@ -503,159 +487,153 @@ static void
 w83627hf_cir_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
     /* Unimplemented Functionality */
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[6][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x60 ... 0x61:
             dev->dev_regs[6][cur_reg] = val;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[6][cur_reg] = val & 0x0f;
-        break;
+            break;
     }
 }
 
 static void
 w83627hf_gameport_midi_gpio1_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[7][cur_reg] = val & 7;
-        break;
+            break;
 
         case 0x60 ... 0x63:
             dev->dev_regs[7][cur_reg] = val;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[7][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xf0 ... 0xf2:
             dev->dev_regs[7][cur_reg] = val;
-        break;
+            break;
     }
 }
 
 static void
 w83627hf_watchdog_timer_gpio2_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[8][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0xf0 ... 0xf2:
             dev->dev_regs[8][cur_reg] = val;
-        break;
+            break;
 
         case 0xf5:
             dev->dev_regs[8][cur_reg] = val & 0xcc;
-        break;
+            break;
 
         case 0xf6 ... 0xf7:
             dev->dev_regs[8][cur_reg] = val;
-        break;
+            break;
     }
 }
 
 static void
 w83627hf_gpio3_vsb_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[9][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0xf0 ... 0xf2:
             dev->dev_regs[9][cur_reg] = val;
-        break;
+            break;
 
         case 0xf3:
             dev->dev_regs[9][cur_reg] = val & 0xc0;
-        break;
+            break;
     }
 }
 
 static void
 w83627hf_acpi_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[0x0a][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[0x0a][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xe0:
             dev->dev_regs[0x0a][cur_reg] = val & 0xc0;
-        break;
+            break;
 
         case 0xe1 ... 0xe2:
             dev->dev_regs[0x0a][cur_reg] = val;
-        break;
+            break;
 
         case 0xe4:
             dev->dev_regs[0x0a][cur_reg] = val & 0xfc;
-        break;
+            break;
 
         case 0xe5 ... 0xe6:
             dev->dev_regs[0x0a][cur_reg] = val & 0x7f;
 
-            if(cur_reg == 0xe6)
-                if(val & 0x40)
+            if (cur_reg == 0xe6)
+                if (val & 0x40)
                     dev->hwm_regs[0x42] &= 0x10;
-        break;
+            break;
 
         case 0xe7:
             dev->dev_regs[0x0a][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xf0:
             dev->dev_regs[0x0a][cur_reg] = val;
-        break;
+            break;
 
         case 0xf1:
             dev->dev_regs[0x0a][cur_reg] = val & 0xef;
-        break;
+            break;
 
         case 0xf3 ... 0xf4:
             dev->dev_regs[0x0a][cur_reg] &= val & 0x3f;
-        break;
+            break;
 
         case 0xf5:
         case 0xf7:
             dev->dev_regs[0x0a][cur_reg] = val & 0x3f;
-        break;
+            break;
     }
 }
 
 static void
 w83627hf_hwm_lpc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
 {
-    switch(cur_reg)
-    {
+    switch (cur_reg) {
         case 0x30:
             dev->dev_regs[0x0b][cur_reg] = val & 1;
-        break;
+            break;
 
         case 0x70:
             dev->dev_regs[0x0b][cur_reg] = val & 0x0f;
-        break;
+            break;
 
         case 0xf0:
             dev->dev_regs[0x0b][cur_reg] = val & 1;
-        break;
+            break;
     }
 }
 
@@ -682,7 +660,7 @@ w83627hf_hwm_reset(w83627hf_t *dev)
 static void
 w83627hf_reset(void *priv)
 {
-    w83627hf_t *dev = (w83627hf_t *)priv;
+    w83627hf_t *dev = (w83627hf_t *) priv;
     memset(dev->regs, 0, sizeof(dev->regs));
     dev->cfg_unlocked = 0;
 
@@ -749,32 +727,29 @@ w83627hf_reset(void *priv)
     dev->dev_regs[9][0xf0] = 0xff;
 
     /* W83627HF Hardware Monitor */
-    if(dev->has_hwm)
+    if (dev->has_hwm)
         w83627hf_hwm_reset(dev);
 }
 
 static void
 w83627hf_write(uint16_t addr, uint8_t val, void *priv)
 {
-    w83627hf_t *dev = (w83627hf_t *)priv;
+    w83627hf_t *dev = (w83627hf_t *) priv;
 
-    switch(addr & 0x0f)
-    {
+    switch (addr & 0x0f) {
         case 0x0e:
-            if(!dev->cfg_unlocked)
-            {
+            if (!dev->cfg_unlocked) {
                 dev->cfg_unlocked = (val == 0x87) && (dev->index == 0x87);
+                dev->index        = val;
+            } else
                 dev->index = val;
-            }
-            else dev->index = val;
-        break;
+            break;
 
         case 0x0f:
-            if(dev->cfg_unlocked)
-                switch(dev->index)
-                {
+            if (dev->cfg_unlocked)
+                switch (dev->index) {
                     case 0x02: /* LDN */
-                        if(val & 1)
+                        if (val & 1)
                             w83627hf_reset(dev);
                         break;
 
@@ -813,94 +788,92 @@ w83627hf_write(uint16_t addr, uint8_t val, void *priv)
                     case 0x2a:
                     case 0x2b:
                         dev->regs[dev->index] = val;
-                    break;
+                        break;
 
                     case 0x30: /* Device Specific Registers */
                     case 0x60 ... 0x63:
-                    case 0x70: case 0x72:case 0x74:
+                    case 0x70:
+                    case 0x72:
+                    case 0x74:
                     case 0xe0 ... 0xe7:
                     case 0xf0 ... 0xf6:
-                        switch(dev->regs[7])
-                        {
+                        switch (dev->regs[7]) {
                             case 0: /* FDC */
                                 w83627hf_fdc_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 1: /* LPT */
                                 w83627hf_lpt_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 2: /* UART A */
                             case 3: /* UART B */
                                 w83627hf_uart_write(dev->regs[7] & 1, dev->index, val, dev);
-                            break;
+                                break;
 
                             case 5: /* KBC */
                                 w83627hf_kbc_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 6: /* CIR */
                                 w83627hf_cir_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 7: /* GAMEPORT, MIDI & GPIO1 */
                                 w83627hf_gameport_midi_gpio1_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 8: /* WATCHDOG TIMER & GPIO2 */
                                 w83627hf_watchdog_timer_gpio2_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 9: /* GPIO3 & VSB */
                                 w83627hf_gpio3_vsb_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 0x0a: /* ACPI */
                                 w83627hf_acpi_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             case 0x0b: /* HWM LPC */
                                 w83627hf_hwm_lpc_write(dev->index, val, dev);
-                            break;
+                                break;
 
                             default:
                                 w83627hf_log("W83627HF: Writings to unknown LDN: %02x\n", dev->regs[7]);
-                            break;
+                                break;
                         }
-                    break;
+                        break;
                 }
-        break;
+            break;
     }
 }
 
-
 static uint8_t
 w83627hf_read(uint16_t addr, void *priv)
 {
-    w83627hf_t *dev = (w83627hf_t *)priv;
+    w83627hf_t *dev = (w83627hf_t *) priv;
 
-    if((dev->index >= 0x00) && (dev->index <= 0x2f))
+    if ((dev->index >= 0x00) && (dev->index <= 0x2f))
         return dev->regs[dev->index];
-    else if((dev->index >= 0x30) && (dev->index <= 0xff) && (dev->regs[7] >= 0) && (dev->regs[7] <= 0x0b))
+    else if ((dev->index >= 0x30) && (dev->index <= 0xff) && (dev->regs[7] >= 0) && (dev->regs[7] <= 0x0b))
         return dev->dev_regs[dev->regs[7]][dev->index];
     else
         return 0xff;
 }
 
-
 static void
 w83627hf_close(void *priv)
 {
-    w83627hf_t *dev = (w83627hf_t *)priv;
+    w83627hf_t *dev = (w83627hf_t *) priv;
 
     free(dev);
 }
 
-
 static void *
 w83627hf_init(const device_t *info)
 {
-    w83627hf_t *dev = (w83627hf_t *)malloc(sizeof(w83627hf_t));
+    w83627hf_t *dev = (w83627hf_t *) malloc(sizeof(w83627hf_t));
     memset(dev, 0, sizeof(w83627hf_t));
 
     /* Knock out the Hardware Monitor if needed(Mainly for ASUS TUSL2-C) */
@@ -910,7 +883,7 @@ w83627hf_init(const device_t *info)
     io_sethandler(0x002e, 2, w83627hf_read, NULL, NULL, w83627hf_write, NULL, NULL, dev);
     io_sethandler(0x004e, 2, w83627hf_read, NULL, NULL, w83627hf_write, NULL, NULL, dev);
 
-    if(dev->has_hwm)
+    if (dev->has_hwm)
         io_sethandler(0x0295, 2, w83627hf_hwm_read, NULL, NULL, w83627hf_hwm_write, NULL, NULL, dev);
 
     /* Floppy Disk Controller */
@@ -934,29 +907,29 @@ w83627hf_init(const device_t *info)
 }
 
 const device_t w83627hf_device = {
-    .name = "Winbond W83627HF",
+    .name          = "Winbond W83627HF",
     .internal_name = "w83627hf",
-    .flags = 0,
-    .local = 1,
-    .init = w83627hf_init,
-    .close = w83627hf_close,
-    .reset = w83627hf_reset,
+    .flags         = 0,
+    .local         = 1,
+    .init          = w83627hf_init,
+    .close         = w83627hf_close,
+    .reset         = w83627hf_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
 
 const device_t w83627hf_no_hwm_device = {
-    .name = "Winbond W83627HF with no Hardware Monitor",
+    .name          = "Winbond W83627HF with no Hardware Monitor",
     .internal_name = "w83627hf_nohwm",
-    .flags = 0,
-    .local = 0,
-    .init = w83627hf_init,
-    .close = w83627hf_close,
-    .reset = w83627hf_reset,
+    .flags         = 0,
+    .local         = 0,
+    .init          = w83627hf_init,
+    .close         = w83627hf_close,
+    .reset         = w83627hf_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };
diff --git a/src/sound/snd_ac97_intel.c b/src/sound/snd_ac97_intel.c
index b415ddcaf..ede4b0715 100644
--- a/src/sound/snd_ac97_intel.c
+++ b/src/sound/snd_ac97_intel.c
@@ -19,7 +19,7 @@
 /*
  * Buffers, AC-Link and other things require understanding.
  * But I also need a functional board with AC'97 to continue.
-*/
+ */
 
 #include <stdarg.h>
 #include <stdint.h>
@@ -45,16 +45,15 @@ intel_ac97_log(const char *fmt, ...)
     va_list ap;
 
     if (intel_ac97_do_log) {
-	va_start(ap, fmt);
-	pclog_ex(fmt, ap);
-	va_end(ap);
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
     }
 }
 #else
-#define intel_ac97_log(fmt, ...)
+#    define intel_ac97_log(fmt, ...)
 #endif
 
-
 /* Mixer Configuration */
 static void
 intel_ac97_mixer_write(uint16_t addr, uint16_t val, void *priv)
@@ -77,17 +76,16 @@ intel_ac97_mixer_read(uint16_t addr, void *priv)
 void
 intel_ac97_mixer_base(int enable, uint16_t addr, intel_ac97_t *dev)
 {
-    if(dev->mixer_base != 0)
+    if (dev->mixer_base != 0)
         io_removehandler(dev->mixer_base, 256, NULL, intel_ac97_mixer_read, NULL, NULL, intel_ac97_mixer_write, NULL, dev);
 
     intel_ac97_log("Intel AC'97 Mixer: Base has been set on 0x%x\n", addr);
     dev->mixer_base = addr;
 
-    if((addr != 0) && enable)
+    if ((addr != 0) && enable)
         io_sethandler(addr, 256, NULL, intel_ac97_mixer_read, NULL, NULL, intel_ac97_mixer_write, NULL, dev);
 }
 
-
 /* AC'97 Configuration */
 void
 intel_ac97_set_irq(int irq, intel_ac97_t *dev)
@@ -105,68 +103,63 @@ intel_ac97_write(uint16_t addr, uint8_t val, void *priv)
 
     intel_ac97_log("Intel AC'97: dev->regs[%02x] = %02x\n", addr, val);
 
-    switch(addr)
-    {
+    switch (addr) {
         case 0x10 ... 0x13: /* Buffer BAR */
             dev->regs[addr] = val;
-        break;
+            break;
 
         case 0x15: /* Last Valid Index */
             dev->regs[addr] &= val;
-        break;
+            break;
 
         case 0x16: /* Status */
             dev->regs[addr] &= val;
-        break;
+            break;
 
         case 0x1b: /* Control */
             dev->regs[addr] = val & 0x1f;
-        break;
+            break;
 
         case 0x2c: /* Global Control */
             dev->regs[addr] = val & 0x3f;
-        break;
+            break;
 
         case 0x2e: /* Global Control */
             dev->regs[addr] = val & 0x30;
-        break;
+            break;
 
         case 0x34: /* Codec Access Semaphore */
             dev->regs[addr] = val & 1;
-        break;
+            break;
     }
 }
 
-
 static uint8_t
 intel_ac97_read(uint16_t addr, void *priv)
 {
     intel_ac97_t *dev = (intel_ac97_t *) priv;
     addr -= dev->ac97_base;
 
-    if(addr < 0x40) {
+    if (addr < 0x40) {
         intel_ac97_log("Intel AC'97: dev->regs[%02x] (%02x)\n", addr, dev->regs[addr]);
         return dev->regs[addr];
-    }
-    else
+    } else
         return 0xff;
 }
 
 void
 intel_ac97_base(int enable, uint16_t addr, intel_ac97_t *dev)
 {
-    if(dev->ac97_base != 0)
+    if (dev->ac97_base != 0)
         io_removehandler(dev->ac97_base, 64, intel_ac97_read, NULL, NULL, intel_ac97_write, NULL, NULL, dev);
 
     intel_ac97_log("Intel AC'97: Base has been set on 0x%x\n", addr);
     dev->ac97_base = addr;
 
-    if((addr != 0) && enable)
+    if ((addr != 0) && enable)
         io_sethandler(addr, 64, intel_ac97_read, NULL, NULL, intel_ac97_write, NULL, NULL, dev);
-
 }
 
-
 static void
 intel_ac97_reset(void *priv)
 {
@@ -176,7 +169,6 @@ intel_ac97_reset(void *priv)
     // We got nothing here yet
 }
 
-
 static void
 intel_ac97_close(void *priv)
 {
@@ -185,7 +177,6 @@ intel_ac97_close(void *priv)
     free(dev);
 }
 
-
 static void *
 intel_ac97_init(const device_t *info)
 {
@@ -201,15 +192,15 @@ intel_ac97_init(const device_t *info)
 }
 
 const device_t intel_ac97_device = {
-    .name = "Intel AC'97 Version 2.1",
+    .name          = "Intel AC'97 Version 2.1",
     .internal_name = "intel_ac97",
-    .flags = 0,
-    .local = 0,
-    .init = intel_ac97_init,
-    .close = intel_ac97_close,
-    .reset = intel_ac97_reset,
+    .flags         = 0,
+    .local         = 0,
+    .init          = intel_ac97_init,
+    .close         = intel_ac97_close,
+    .reset         = intel_ac97_reset,
     { .available = NULL },
     .speed_changed = NULL,
-    .force_redraw = NULL,
-    .config = NULL
+    .force_redraw  = NULL,
+    .config        = NULL
 };