From 15a2f6435c4989a425dc841a0e2f0e3bb91fdffa Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 27 Nov 2024 16:29:26 +0000 Subject: [PATCH 001/274] Nvidia NV3 initial implementation from the old repo when it was a fork. --- CMakeLists.txt | 5 + CMakePresets.json | 5 +- src/include/86box/nv/vid_nv.h | 494 +++++++++++ src/include/86box/nv/vid_nv3.h | 486 ++++++++++ src/include/86box/video.h | 2 + src/video/CMakeLists.txt | 16 +- src/video/nv/nv3/nv3_core.c | 837 ++++++++++++++++++ src/video/nv/nv3/nv3_core_arbiter.c | 198 +++++ src/video/nv/nv3/nv3_interrupt.c | 0 src/video/nv/nv3/subsystems/nv3_pbus.c | 249 ++++++ src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 31 + src/video/nv/nv3/subsystems/nv3_pextdev.c | 149 ++++ src/video/nv/nv3/subsystems/nv3_pfb.c | 109 +++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 146 +++ src/video/nv/nv3/subsystems/nv3_pgraph.c | 151 ++++ src/video/nv/nv3/subsystems/nv3_pmc.c | 236 +++++ src/video/nv/nv3/subsystems/nv3_pme.c | 123 +++ src/video/nv/nv3/subsystems/nv3_pramdac.c | 307 +++++++ src/video/nv/nv3/subsystems/nv3_pramin.c | 149 ++++ .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 31 + .../nv/nv3/subsystems/nv3_pramin_ramht.c | 31 + .../nv/nv3/subsystems/nv3_pramin_ramro.c | 31 + src/video/nv/nv3/subsystems/nv3_ptimer.c | 120 +++ src/video/nv/nv3/subsystems/nv3_pvideo.c | 121 +++ src/video/nv/nv_base.c | 47 + src/video/vid_table.c | 3 + 26 files changed, 4074 insertions(+), 3 deletions(-) create mode 100644 src/include/86box/nv/vid_nv.h create mode 100644 src/include/86box/nv/vid_nv3.h create mode 100644 src/video/nv/nv3/nv3_core.c create mode 100644 src/video/nv/nv3/nv3_core_arbiter.c create mode 100644 src/video/nv/nv3/nv3_interrupt.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pbus.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pbus_dma.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pextdev.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pfb.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pfifo.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pgraph.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pmc.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pme.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pramdac.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pramin.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pramin_ramht.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pramin_ramro.c create mode 100644 src/video/nv/nv3/subsystems/nv3_ptimer.c create mode 100644 src/video/nv/nv3/subsystems/nv3_pvideo.c create mode 100644 src/video/nv/nv_base.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 8d7b3f6f0..3e0527c60 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -138,6 +138,11 @@ option(GDBSTUB "Enable GDB stub server for debugging" option(DEV_BRANCH "Development branch" OFF) option(DISCORD "Discord Rich Presence support" ON) option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) +option(NV_LOG "NVidia RIVA 128 debug logging" OFF) + +if (NV_LOG) + add_compile_definitions(ENABLE_NV_LOG) +endif() if(WIN32) set(QT ON) diff --git a/CMakePresets.json b/CMakePresets.json index c19a7abc0..8d4873624 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -35,7 +35,8 @@ { "name": "debug", "cacheVariables": { - "CMAKE_BUILD_TYPE": "Debug" + "CMAKE_BUILD_TYPE": "Debug", + "NV_LOG": "ON" }, "inherits": "base" }, @@ -65,7 +66,7 @@ "NEW_DYNAREC": "ON", "QT": "ON", "USE_QT6": "OFF", - "Qt5_DIR": "/opt/homebrew/opt/qt@5/lib/cmake/Qt5", + "Qt5_DIR": "/opt/homebrew/opt/qt@5/lSib/cmake/Qt5", "MOLTENVK_DIR": "/opt/homebrew/opt/molten-vk", "Qt5LinguistTools_DIR": "/opt/homebrew/opt/qt@5/lib/cmake/Qt5LinguistTools", "OpenAL_ROOT": "/opt/homebrew/opt/openal-soft" diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h new file mode 100644 index 000000000..ca0922a44 --- /dev/null +++ b/src/include/86box/nv/vid_nv.h @@ -0,0 +1,494 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * JENSEN HUANG APPROVED !!!! + * + * Credit to: + * + * - fuel (PCBox developer) + * - Marcelina Kościelnicka (envytools) + * - nouveau developers + * - Utah GLX developers + * - XFree86 developers + * - xemu developers + * + * Authors: Connor Hyde / starfrost + * + * Copyright 2024 Connor Hyde + */ +#ifdef EMU_DEVICE_H // what + +//TODO: split this all into nv1, nv3, nv4... + +#include <86box/timer.h> +#include <86box/vid_svga.h> +#include <86box/vid_svga_render.h> + +void nv_log(const char *fmt, ...); + +// Defines common to all NV chip architectural generations + +// PCI IDs +#define PCI_VENDOR_NV 0x10DE // NVidia PCI ID +#define PCI_VENDOR_SGS 0x104A // SGS-Thompson +#define PCI_VENDOR_SGS_NV 0x12D2 // SGS-Thompson/NVidia joint venture + +#define NV_PCI_NUM_CFG_REGS 256 // number of pci config registers + +// 0x0000 was probably the NV0 'Nvidia Hardware Simulator' +#define PCI_DEVICE_NV1 0x0008 // Nvidia NV1 +#define PCI_DEVICE_NV1_VGA 0x0009 // Nvidia NV1 VGA core +#define PCI_DEVICE_NV2 0x0010 // Nvidia NV2 / Mutara V08 (cancelled) +#define PCI_DEVICE_NV3 0x0018 // Nvidia NV3 (Riva 128) +#define PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) +#define PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) + +#define CHIP_REVISION_NV1_A0 0x0000 +#define CHIP_REVISION_NV1_B0 0x0010 +#define CHIP_REVISION_NV1_C0 0x0020 + +#define CHIP_REVISION_NV3_A0 0x0000 // January 1997 +#define CHIP_REVISION_NV3_B0 0x0010 // October 1997 +#define CHIP_REVISION_NV3_C0 0x0020 // 1998 + +// Architecture IDs +#define NV_ARCHITECTURE_NV1 1 +#define NV_ARCHITECTURE_NV2 2 +#define NV_ARCHITECTURE_NV3 3 + + +typedef enum nv_bus_generation_e +{ + // NV1 + // NV3 + nv_bus_pci = 0, + + // NV3 + nv_bus_agp_1x = 1, + + // NV3T + // NV4 + nv_bus_agp_2x = 2, + +} nv_bus_generation; + +// NV Base +typedef struct nv_base_s +{ + rom_t vbios; // NVIDIA/OEm VBIOS + // move to nv3_cio_t? + svga_t svga; // SVGA core (separate to nv3) + // stuff that doesn't fit in the svga structure + uint32_t cio_read_bank; // SVGA read bank + uint32_t cio_write_bank; // SVGA write bank + + mem_mapping_t framebuffer_mapping; // Linear Framebuffer / NV_USER memory mapping + mem_mapping_t mmio_mapping; // mmio mapping (32MB unified MMIO) + mem_mapping_t framebuffer_mapping_mirror; // Mirror of LFB mapping + mem_mapping_t ramin_mapping; // RAM INput area mapping + mem_mapping_t ramin_mapping_mirror; // RAM INput area mapping (mirrored) + uint8_t pci_slot; // pci slot number + uint8_t pci_irq_state; // current PCI irq state + uint32_t bar0_mmio_base; // PCI Base Address Register 0 - MMIO Base + uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) + nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) +} nv_base_t; + +#define NV_REG_LIST_END 0xD15EA5E + +// The NV architectures are very complex. +// There are hundreds of registers at minimum, and implementing these in a standard way would lead to +// unbelievably large switch statements and horrifically unreadable code. +// So this is used to abstract it and allow for more readable code. +// This is mostly just used for logging and stuff. +// Optionally, you can provide a function that is run when you read to and write from the register. +// You can also implement this functionality in a traditional way such as a switch statement, for simpler registers. To do this, simply set both read and write functions to NULL. +// Typically, unless they are for a special purpose (and handled specially) e.g. vga all register reads and writes are also 32-bit aligned +typedef struct nv_register_s +{ + int32_t address; // MMIO Address + char* friendly_name; // Friendly name + // reg_ptr not needed as a parameter, because we implicitly know which register si being tiwddled + uint32_t (*on_read)(); // Optional on-read function + void (*on_write)(uint32_t value);// Optional on-write fucntion +} nv_register_t; + +nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs); + +#define NV3_BOOT_REG_DEFAULT 0x00300111 + +// Master Control +typedef struct nv3_pmc_s +{ + /* + Holds chip manufacturing information at bootup. + Current specification (may change later): pre-packed for convenience + + FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?) + 31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001 + little endian 00000000 00000011 00000001 00010001 = 0x00300111 + */ + int32_t boot; + int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems. + int32_t interrupt_enable; // Determines if interrupts are actually enabled. + int32_t enable; // Determines which subsystems are enabled. + +} nv3_pmc_t; + +typedef struct nv3_pci_config_s +{ + uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability) + bool vbios_enabled; // is the vbios enabled? + uint8_t int_line; +} nv3_pci_config_t; + +// add enums for eac +// Chip configuration +typedef struct nv3_straps_s +{ + uint32_t straps; +} nv3_straps_t; + +// Framebuffer +typedef struct nv3_pfb_s +{ + uint32_t boot; +} nv3_pfb_t; + +#define NV3_RMA_NUM_REGS 4 +// Access the GPU from real-mode +typedef struct nv3_pbus_rma_s +{ + uint32_t addr; // Address to RMA to + uint32_t data; // Data to send to MMIO + uint8_t mode; // the current state of the rma shifting engin + uint8_t rma_regs[NV3_RMA_NUM_REGS]; // The rma registers (saved) +} nv3_pbus_rma_t; + +// Bus Configuration +typedef struct nv3_pbus_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable + nv3_pbus_rma_t rma; +} nv3_pbus_t; + +// Command submission to PGRAPH +typedef struct nv_pfifo_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable +} nv3_pfifo_t; + +// RAMDAC +typedef struct nv3_pramdac_s +{ + // these should be uint8_t but C math is a lot better with this + uint32_t memory_clock_m; // memory clock M-divider + uint32_t memory_clock_n; // memory clock N-divider + uint32_t memory_clock_p; // memory clock P-divider + uint32_t pixel_clock_m; // pixel clock M-divider + uint32_t pixel_clock_n; // pixel clock N-divider + uint32_t pixel_clock_p; // pixel clock P-divider + uint32_t coeff_select; // coefficient select + + uint32_t general_control; // general control register + + // this could duplicate SVGA state but I tihnk it's more readable, + // we'll just modify both + uint32_t vserr_width; // vertical sync error width + uint32_t vequ_end; // vequ end (not sure what this is) + uint32_t vbblank_end; // vbblank end (not sure what this is) + uint32_t vblank_end; // vblank end + uint32_t vblank_start; // vblank start + uint32_t vequ_start; // vequ start (not sure what this is) + uint32_t vtotal; // vertical total lines + uint32_t hsync_width; // horizontal sync width + uint32_t hburst_start; // horizontal burst signal start (in lines) + uint32_t hburst_end; // horizontal burst signal end (in lines) + uint32_t hblank_start; // horizontal blank start (in lines) + uint32_t hblank_end; // horizontal blank end (in lines) + uint32_t htotal; // horizontal total lines + uint32_t hequ_width; // horizontal equ width (not sure what this is) + uint32_t hserr_width; // horizontal sync error width +} nv3_pramdac_t; + +// Graphics Subsystem +typedef struct nv3_pgraph_s +{ + uint32_t interrupt_status_0; // Interrupt status 0 + uint32_t interrupt_enable_0; // Interrupt enable 0 + uint32_t interrupt_status_1; // Interrupt status 1 + uint32_t interrupt_enable_1; // Interrupt enable 1 +} nv3_pgraph_t; + +// GPU Manufacturing Configuration (again) +// In the future this will be configurable +typedef struct nv3_pextdev_s +{ + /* + // Disabled 33Mhz + // Enabled 66Mhz + bool bus_speed; + + // Disabled No BIOS + // Enabled BIOS + bool bios; + + // RAM Type #1 + // Disabled 16Mbit (2MB) module size + // Enabled 8Mbit (1MB) module size + bool ram_type_1; + + // NEC Mode + bool nec_mode; + + // Disabled 64-bit + // Enabled 128-bit + bool bus_width; + + // Disabled PCI + // Enabled AGP + bool bus_type; + + // Disabled 13500 + // Enabled 14318180 + bool crystal; + + // TV Mode + // 0 - SECAM, 1 - NTSC, 2 - PAL, 3 - none + uint8_t tv_mode; + + // AGP 2X mode + // Disabled AGP 1X + // Enabled AGP 2X + bool agp_is_2x; + + bool unused; + + // Overwrite enable + bool overwrite; + + See defines in vid_nv3.h + */ + uint32_t straps; + + // more ram type stuff here but not used? +} nv3_pextdev_t; + +typedef struct nv3_ptimer_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable +} nv3_ptimer_t; + +// Graphics object hashtable +typedef struct nv3_pramin_ramht_s +{ + +} nv3_pramin_ramht_t; + +// Anti-fuckup device +typedef struct nv3_pramin_ramro_s +{ + +} nv3_pramin_ramro_t; + +// context for unused channels +typedef struct nv3_pramin_ramfc_s +{ + +} nv3_pramin_ramfc_t; + +// ????? ram auxillary +typedef struct nv_pramin_ramau_s +{ + +} nv3_pramin_ramau_t; + +typedef struct nv3_pramin_s +{ + +} nv3_pramin_t; + +typedef struct nv3_pvideo_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable +} nv3_pvideo_t; + +typedef struct nv3_pme_s // Mediaport +{ + uint32_t interrupt_status; + uint32_t interrupt_enable; +} nv3_pme_t; + +typedef struct nv3_s +{ + nv_base_t nvbase; // Base Nvidia structure + + // Config + nv3_straps_t straps; + nv3_pci_config_t pci_config; + + // Subsystems + nv3_pmc_t pmc; // Master Control + nv3_pfb_t pfb; // Framebuffer/VRAM + nv3_pbus_t pbus; // Bus Control + nv3_pfifo_t pfifo; // FIFO for command submisison + + nv3_pramdac_t pramdac; // RAMDAC (CLUT etc) + nv3_pgraph_t pgraph; // 2D/3D Graphics + nv3_pextdev_t pextdev; // Chip configuration + nv3_ptimer_t ptimer; // programmable interval timer + nv3_pramin_ramht_t ramht; // hashtable for PGRAPH objects + nv3_pramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission + nv3_pramin_ramfc_t ramfc; // context for unused channels + nv3_pramin_ramau_t ramau; // auxillary weirdnes + nv3_pramin_t pramin; // Ram for INput of DMA objects. Very important! + nv3_pvideo_t pvideo; // Video overlay + nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface + //more here + +} nv3_t; + +// device objects +extern nv3_t* nv3; + +// Address of this returned by unimplemented registers to prevent a crash +extern uint32_t unimplemented_dummy; + +// NV3 stuff + +// Device Core +void* nv3_init(const device_t *info); +void nv3_close(void* priv); +void nv3_speed_changed(void *priv); +void nv3_force_redraw(void* priv); + +// Memory Mapping +void nv3_update_mappings(); +uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO +uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO +uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO +void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit MMIO +void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit MMIO +void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit MMIO + +uint8_t nv3_svga_in(uint16_t addr, void* priv); // Read SVGA compatibility registers +void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); // Write SVGA registers +uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv); // Read PCI configuration registers +void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers + +uint8_t nv3_ramin_read8(uint32_t addr, void* priv); // Read 8-bit RAMIN +uint16_t nv3_ramin_read16(uint32_t addr, void* priv); // Read 16-bit RAMIN +uint32_t nv3_ramin_read32(uint32_t addr, void* priv); // Read 32-bit RAMIN +void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit RAMIN +void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN +void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN + +// MMIO Arbitration +// Determine where the hell in this mess our reads or writes are going +uint32_t nv3_mmio_arbitrate_read(uint32_t address); +void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value); + +// Read and Write functions for GPU subsystems +// Remove the ones that aren't used here eventually, have all of htem for now +uint32_t nv3_pmc_read(uint32_t address); +void nv3_pmc_write(uint32_t address, uint32_t value); +uint32_t nv3_cio_read(uint32_t address); +void nv3_cio_write(uint32_t address, uint32_t value); +uint32_t nv3_pbus_read(uint32_t address); +void nv3_pbus_write(uint32_t address, uint32_t value); +uint32_t nv3_pfifo_read(uint32_t address); +void nv3_pfifo_write(uint32_t address, uint32_t value); +uint32_t nv3_prm_read(uint32_t address); +void nv3_prm_write(uint32_t address, uint32_t value); +uint32_t nv3_prmio_read(uint32_t address); +void nv3_prmio_write(uint32_t address, uint32_t value); +uint32_t nv3_ptimer_read(uint32_t address); +void nv3_ptimer_write(uint32_t address, uint32_t value); +uint32_t nv3_pfb_read(uint32_t address); +void nv3_pfb_write(uint32_t address, uint32_t value); +uint32_t nv3_pextdev_read(uint32_t address); +void nv3_pextdev_write(uint32_t address, uint32_t value); + +// Special consideration for straps +#define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS) +#define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x) + +uint32_t nv3_prom_read(uint32_t address); +void nv3_prom_write(uint32_t address, uint32_t value); +uint32_t nv3_palt_read(uint32_t address); +void nv3_palt_write(uint32_t address, uint32_t value); +uint32_t nv3_pme_read(uint32_t address); +void nv3_pme_write(uint32_t address, uint32_t value); +uint32_t nv3_pgraph_read(uint32_t address); +void nv3_pgraph_write(uint32_t address, uint32_t value); + +// TODO: PGRAPH class registers + +uint32_t nv3_prmcio_read(uint32_t address); +void nv3_prmcio_write(uint32_t address, uint32_t value); +uint32_t nv3_pvideo_read(uint32_t address); +void nv3_pvideo_write(uint32_t address, uint32_t value); +uint32_t nv3_pramdac_read(uint32_t address); +void nv3_pramdac_write(uint32_t address, uint32_t value); +uint32_t nv3_vram_read(uint32_t address); +void nv3_vram_write(uint32_t address, uint32_t value); +#define nv3_nvm_read nv3_vram_read +#define nv3_nvm_write nv3_vram_write +uint32_t nv3_user_read(uint32_t address); +void nv3_user_write(uint32_t address, uint32_t value); +#define nv3_object_submit_start nv3_user_read +#define nv3_object_submit_end nv3_user_write +uint32_t nv3_pramin_read(uint32_t address); +void nv3_pramin_write(uint32_t address, uint32_t value); +// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* + +// GPU subsystems + +// NV3 PMC +void nv3_pmc_init(); +uint32_t nv3_pmc_clear_interrupts(); +uint32_t nv3_pmc_handle_interrupts(bool send_now); + +// NV3 PGRAPH +void nv3_pgraph_init(); + +// NV3 PFIFO +void nv3_pfifo_init(); + + +// NV3 PFB +void nv3_pfb_init(); + +// NV3 PEXTDEV/PSTRAPS +void nv3_pextdev_init(); + +// NV3 PBUS +void nv3_pbus_init(); + +// NV3 PBUS RMA - Real Mode Access for VBIOS +uint8_t nv3_pbus_rma_read(uint16_t addr); +void nv3_pbus_rma_write(uint16_t addr, uint8_t val); + +// NV3 PRAMDAC +void nv3_pramdac_init(); +void nv3_pramdac_set_vram_clock(); +void nv3_pramdac_set_pixel_clock(); + +// NV3 PTIMER +void nv3_ptimer_init(); + +// NV3 PVIDEO +void nv3_pvideo_init(); + +// NV3 PMEDIA +void nv3_pmedia_init(); +#endif \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h new file mode 100644 index 000000000..a9a4884d9 --- /dev/null +++ b/src/include/86box/nv/vid_nv3.h @@ -0,0 +1,486 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * JENSEN HUANG APPROVED !!!! + * + * + * + * Authors: Connor Hyde + * + * Copyright 2024 Connor Hyde + */ + +// vid_nv3.h: NV3 Architecture Hardware Reference (open-source) +// Last updated 26 November 2024 + +// The GPU base structure +extern nv3_t* nv3; + +#define NV3_MMIO_SIZE 0x1000000 // Max MMIO size + +// various vbioses for testing +// Coming soon: MIROmagic Premium BIOS (when I get mine dumped) +//todo: move to hash system + +// Oldest one of these - September 6, 1997 +#define NV3_VBIOS_ERAZOR_V14700 "roms/video/nvidia/nv3/OLD_0000.BIN" // ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00) +#define NV3_VBIOS_ERAZOR_V15403 "roms/video/nvidia/nv3/VCERAZOR.BIN" // ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS] +#define NV3_VBIOS_ERAZOR_V15500 "roms/video/nvidia/nv3/Ver15500.rv_" // ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS] +#define NV3_VBIOS_DIAMOND_V330_V162 "roms/video/nvidia/nv3/diamond_v330_rev-e.vbi" // Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO +#define NV3_VBIOS_ASUS_V3000_V151 "roms/video/nvidia/nv3/riva128_asus.vbi" // ASUS AGP/3DP-V3000 BIOS 1.51B +#define NV3_VBIOS_STB_V128_V182 "roms/video/nvidia/nv3/riva128_stb.vbi" // STB Velocity 128 (RIVA 128) Ver.1.82 + +// Temporary, will be loaded from settings +#define VRAM_SIZE_2MB 0x200000 // 2MB +#define VRAM_SIZE_4MB 0x400000 // 4MB +#define VRAM_SIZE_8MB 0x800000 // NV3T only + + +// PCI config +#define NV3_PCI_CFG_VENDOR_ID 0x0 +#define NV3_PCI_CFG_DEVICE_ID 0x2 +#define NV3_PCI_CFG_CAPABILITIES 0x4 + +#define NV3_PCI_COMMAND_L_IO 1 +#define NV3_PCI_COMMAND_L_IO_ENABLED 0x1 +#define NV3_PCI_COMMAND_L_MEMORY 2 +#define NV3_PCI_COMMAND_L_MEMORY_ENABLED 0x1 + +#define NV3_PCI_COMMAND_H_FAST_BACK2BACK 0x01 + +#define NV3_PCI_STATUS_L_66MHZ_CAPABLE 0x20 +#define NV3_PCI_STATUS_H_DEVSEL_TIMING 5 +#define NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING 0x00 + +#define NV3_PCI_CFG_REVISION 0x8 + +#define NV3_PCI_CFG_REVISION_A00 0x00 // nv3a January 1997 - engineering sample, had NV1 PAUDIO and other minor incompatibilities +#define NV3_PCI_CFG_REVISION_B00 0x10 // nv3b September 1997 +#define NV3_PCI_CFG_REVISION_C00 0x20 // todo: verify this - nv3c (nv3t?) / RIVA 128 ZX + +#define NV3_PCI_CFG_PROGRAMMING_INTERFACE 0x9 +#define NV3_PCI_CFG_SUBCLASS_CODE 0x0A +#define NV3_PCI_CFG_CLASS_CODE 0x0B +#define NV3_PCI_CFG_CLASS_CODE_VGA 0x03 + +#define NV3_PCI_CFG_CACHE_LINE_SIZE 0x0C +#define NV3_PCI_CFG_CACHE_LINE_SIZE_DEFAULT_FROM_VBIOS 0x40 + +#define NV3_PCI_CFG_LATENCY_TIMER 0x0D +#define NV3_PCI_CFG_HEADER_TYPE 0x0E +#define NV3_PCI_CFG_BIST 0x0F + +// PCI Bars +#define NV3_PCI_CFG_BAR_PREFETCHABLE 3 +#define NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED 0x1 + +#define NV3_PCI_CFG_BAR0_L 0x10 +#define NV3_PCI_CFG_BAR0_BYTE1 0x11 +#define NV3_PCI_CFG_BAR0_BYTE2 0x12 +#define NV3_PCI_CFG_BAR0_BASE_ADDRESS 0x13 +#define NV3_PCI_CFG_BAR1_L 0x14 +#define NV3_PCI_CFG_BAR1_BYTE1 0x15 +#define NV3_PCI_CFG_BAR1_BYTE2 0x16 +#define NV3_PCI_CFG_BAR1_BASE_ADDRESS 0x17 +#define NV3_PCI_CFG_BAR_INVALID_START 0x18 +#define NV3_PCI_CFG_BAR_INVALID_END 0x27 +#define NV3_PCI_CFG_SUBSYSTEM_ID 0x2C + +#define NV3_PCI_CFG_ENABLE_VBIOS 0x30 +#define NV3_PCI_CFG_VBIOS_BASE 0x32 ... 0x33 +#define NV3_PCI_CFG_VBIOS_BASE_L 0x32 +#define NV3_PCI_CFG_VBIOS_BASE_H 0x33 + +#define NV3_PCI_CFG_INT_LINE 0x3C +#define NV3_PCI_CFG_INT_PIN 0x3D + +#define NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START 0x40 +#define NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END 0x43 + +#define NV3_PCI_CFG_MIN_GRANT 0x3E +#define NV3_PCI_CFG_MIN_GRANT_DEFAULT 0x03 +#define NV3_PCI_CFG_MAX_LATENCY 0x3F +#define NV3_PCI_CFG_MAX_LATENCY_DEFAULT 0x01 + +// GPU Subsystems +// These most likely correspond to functional blocks in the original design + +#define NV3_PMC_START 0x0 // Chip Master Control Subsystem + +#define NV3_PMC_BOOT 0x0 // Boot Configuration +#define NV3_PMC_INTERRUPT_STATUS 0x100 // Interrupt Control +#define NV3_PMC_INTERRUPT_PAUDIO 0 // Unused, NV3A only +#define NV3_PMC_INTERRUPT_PAUDIO_PENDING 0x1 // Unused, NV3A only +#define NV3_PMC_INTERRUPT_PMEDIA 4 +#define NV3_PMC_INTERRUPT_PMEDIA_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PFIFO 8 +#define NV3_PMC_INTERRUPT_PFIFO_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PGRAPH0 12 +#define NV3_PMC_INTERRUPT_PGRAPH0_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PGRAPH1 13 +#define NV3_PMC_INTERRUPT_PGRAPH1_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PVIDEO 16 +#define NV3_PMC_INTERRUPT_PVIDEO_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PTIMER 20 +#define NV3_PMC_INTERRUPT_PTIMER_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PFB 24 +#define NV3_PMC_INTERRUPT_PFB_PENDING 0x1 +#define NV3_PMC_INTERRUPT_PBUS 28 +#define NV3_PMC_INTERRUPT_PBUS_PENDING 0x1 +#define NV3_PMC_INTERRUPT_SOFTWARE 31 +#define NV3_PMC_INTERRUPT_SOFTWARE_PENDING 0x1 +#define NV3_PMC_INTERRUPT_ENABLE 0x140 // Controls global interrupt enable state +#define NV3_PMC_INTERRUPT_ENABLE_HARDWARE 0x1 // Determines if hardware interrupts are enabled +#define NV3_PMC_INTERRUPT_ENABLE_SOFTWARE 0x2 // Determinse if software interrupts were enabled +#define NV3_PMC_ENABLE 0x200 // Determines which gpu subsystems were enabled + +#define NV3_PMC_END 0xfff // overlaps with CIO +#define NV3_CIO_START 0x3b0 // Legacy SVGA Emulation Subsystem +#define NV3_CIO_END 0x3df +#define NV3_PBUS_START 0x1000 // Bus Control Subsystem +#define NV3_PBUS_INTR 0x1100 // Bus Control - Interrupt Status +#define NV3_PBUS_INTR_EN 0x1140 // Bus Control - Interrupt Enable +#define NV3_PBUS_PCI_START 0x1800 // PCI mirror start +#define NV3_PBUS_PCI_END 0x18FF // PCI mirror end +#define NV3_PBUS_END 0x1FFF +#define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects) +#define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status +#define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable +#define NV3_PFIFO_END 0x3FFF +#define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem +#define NV3_PRM_INTR 0x4100 +#define NV3_PRM_INTR_EN 0x4140 +#define NV3_PRM_END 0x4FFF +#define NV3_PRAM_START 0x6000 // Local ram/cache? +#define NV3_PRAM_END 0x6FFF +#define NV3_PRMIO_START 0x7000 // Real-Mode I/O Subsystem +#define NV3_PRMIO_END 0x7FFF +#define NV3_PTIMER_START 0x9000 // Programmable Interval Timer +#define NV3_PTIMER_INTR 0x9100 +#define NV3_PTIMER_INTR_EN 0x9140 +#define NV3_PTIMER_END 0x9FFF +#define NV3_VGA_VRAM_START 0xA0000 // VGA Emulation VRAM +#define NV3_VGA_VRAM_END 0xBFFFF +#define NV3_VGA_START 0xC0000 // VGA Emulation Registers +#define NV3_VGA_END 0xC7FFF +#define NV3_PRMVIO_START NV3_VGA_START +#define NV3_PRMVIO_END NV3_VGA_END +#define NV3_PFB_START 0x100000 // GPU Interface to VRAM +#define NV3_PFB_BOOT 0x100000 // Boot registration +#define NV3_PFB_BOOT_RAM_AMOUNT 0 // The amount of ram +#define NV3_PFB_BOOT_RAM_AMOUNT_8MB 0x0 // 1mb in NV3A +#define NV3_PFB_BOOT_RAM_AMOUNT_2MB 0x1 +#define NV3_PFB_BOOT_RAM_AMOUNT_4MB 0x2 +#define NV3_PFB_BOOT_RAM_AMOUNT_UNDEFINED 0x3 // i assume this is used for debug +#define NV3_PFB_BOOT_RAM_WIDTH 2 // the bus width of the gpu's vram +#define NV3_PFB_BOOT_RAM_WIDTH_64 0x0 // 64bit +#define NV3_PFB_BOOT_RAM_WIDTH_128 0x1 // 128bit +#define NV3_PFB_BOOT_RAM_BANKS 3 // the number of banks +#define NV3_PFB_BOOT_RAM_BANKS_2 0x0 // 2 banks (seems to be used for 2mb) +#define NV3_PFB_BOOT_RAM_BANKS_4 0x1 // 4 banks (seems to be used for 4mb) +#define NV3_PFB_BOOT_RAM_DATA_TWIDDLE 4 +#define NV3_PFB_BOOT_RAM_DATA_TWIDDLE_OFF 0x0 +#define NV3_PFB_BOOT_RAM_DATA_TWIDDLE_ON 0x1 +#define NV3_PFB_BOOT_RAM_EXTENSION 5 +#define NV3_PFB_BOOT_RAM_EXTENSION_NONE 0x0 +#define NV3_PFB_BOOT_RAM_EXTENSION_8MB 0x1 +#define NV3_PFB_END 0x100FFF +#define NV3_PEXTDEV_START 0x101000 // External Devices +#define NV3_PSTRAPS 0x101000 // Straps Bits +#define NV3_PSTRAPS_BUS_SPEED 0 // Configured bus speed +#define NV3_PSTRAPS_BUS_SPEED_33MHZ 0x0 +#define NV3_PSTRAPS_BUS_SPEED_66MHZ 0x1 +#define NV3_PSTRAPS_BIOS 1 // Is a VBIOS present? +#define NV3_PSTRAPS_BIOS_NOT_PRESENT 0x0 +#define NV3_PSTRAPS_BIOS_PRESENT 1 +#define NV3_PSTRAPS_RAM_TYPE 2 // Type of RAM module +#define NV3_PSTRAPS_RAM_TYPE_16MBIT 0x0 +#define NV3_PSTRAPS_RAM_TYPE_8MBIT 0x1 +#define NV3_PSTRAPS_NEC_MODE 3 // PC98? +#define NV3_PSTRAPS_NEC_MODE_DISABLED 0x0 +#define NV3_PSTRAPS_NEC_MODE_ENABLED 0x1 +#define NV3_PSTRAPS_BUS_WIDTH 4 // Bus width +#define NV3_PSTRAPS_BUS_WIDTH_64BIT 0x0 +#define NV3_PSTRAPS_BUS_WIDTH_128BIT 0x0 +#define NV3_PSTRAPS_BUS_TYPE 5 // Determines if this is a PCI or AGP card +#define NV3_PSTRAPS_BUS_TYPE_PCI 0x0 +#define NV3_PSTRAPS_BUS_TYPE_AGP 0x1 +#define NV3_PSTRAPS_CRYSTAL 6 // type of clock crystal +#define NV3_PSTRAPS_CRYSTAL_13500K 0x0 // 13.5 Mhz +#define NV3_PSTRAPS_CRYSTAL_14318180 0x1 // 14.318180 Mhz clock crystal +#define NV3_PSTRAPS_TVMODE 7 // Type of TV signal to put out +#define NV3_PSTRAPS_TVMODE_SECAM 0x0 +#define NV3_PSTRAPS_TVMODE_NTSC 0x1 +#define NV3_PSTRAPS_TVMODE_PAL 0x2 +#define NV3_PSTRAPS_TVMODE_NONE 0x3 +#define NV3_PSTRAPS_AGP2X 9 +#define NV3_PSTRAPS_AGP2X_ENABLED 0x0 +#define NV3_PSTRAPS_AGP2X_DISABLED 0x1 +#define NV3_PSTRAPS_UNUSED 10 +#define NV3_PSTRAPS_OVERWRITE 11 +#define NV3_PSTRAPS_OVERWRITE_DISABLED 0x0 +#define NV3_PSTRAPS_OVERWRITE_ENABLED 0x1 +#define NV3_PEXTDEV_END 0x101FFF +#define NV3_PROM_START 0x110000 // VBIOS? +#define NV3_PROM_END 0x110FFF +#define NV3_PALT_START 0x120000 // ??? but it exists +#define NV3_PALT_END 0x120FFF +#define NV3_PME_START 0x200000 // Mediaport +#define NV3_PME_INTR 0x200100 // Mediaport: Interrupt Pending? +#define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable +#define NV3_PME_END 0x200FFF +#define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part +#define NV3_PGRAPH_INTR_0 0x400100 +#define NV3_PGRAPH_INTR_1 0x400104 +#define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 +//todo: add what this does +#define NV3_PGRAPH_INTR_EN_1 0x400180 // Interrupt Control for PGRAPH #2 (it can receive two at onc) + +// not sure about the class ids +// these are NOT what each class is, just uSed to manipulate it (there isn't a one to one class->reg mapping anyway) +#define NV3_PGRAPH_CLASS18_BETA_START 0x410000 // Beta blending factor +#define NV3_PGRAPH_CLASS18_BETA_END 0x411FFF +#define NV3_PGRAPH_CLASS20_ROP_START 0x420000 // Blending render operation used at final pixel/fragment generation stage +#define NV3_PGRAPH_CLASS20_ROP_END 0x421FFF +#define NV3_PGRAPH_CLASS21_COLORKEY_START 0x430000 // Color key for image +#define NV3_PGRAPH_CLASS21_COLORKEY_END 0x431FFF +#define NV3_PGRAPH_CLASS22_PLANEMASK_START 0x440000 // Plane mask (for clipping?) +#define NV3_PGRAPH_CLASS22_PLANEMASK_END 0x441FFF +#define NV3_PGRAPH_CLASSXX_CLIP_START 0x450000 // clipping, probably class 23 +#define NV3_PGRAPH_CLASSXX_CLIP_END 0x451FFF +#define NV3_PGRAPH_CLASS24_PATTERN_START 0x460000 // presumably a blend pattern +#define NV3_PGRAPH_CLASS24_PATTERN_END 0x461FFF +#define NV3_PGRAPH_CLASS30_RECTANGLE_START 0x470000 // also class 25 - that's black [NV1] +#define NV3_PGRAPH_CLASS30_RECTANGLE_END 0x471FFF // also class 25 - that's black [NV1] +#define NV3_PGRAPH_CLASS26_POINT_START 0x480000 // A single point +#define NV3_PGRAPH_CLASS26_POINT_END 0x481FFF +#define NV3_PGRAPH_CLASS27_LINE_START 0x490000 // A line +#define NV3_PGRAPH_CLASS27_LINE_END 0x491FFF +#define NV3_PGRAPH_CLASS28_LIN_START 0x4A0000 // A lin - a line without its starting or ending pixels +#define NV3_PGRAPH_CLASS28_LIN_END 0x4A1FFF +#define NV3_PGRAPH_CLASS29_TRIANGLE_START 0x4B0000 // A triangle [NV1 variant] - in NV1 this was converted to a quad patch +#define NV3_PGRAPH_CLASS29_TRIANGLE_END 0x4B1FFF +#define NV3_PGRAPH_CLASS75_GDITEXT_START 0x4C0000 // Windows 95/NT GDI text acceleration +#define NV3_PGRAPH_CLASS75_GDITEXT_END 0x4C1FFF + +#define NV3_PGRAPH_CLASS61_MEM2MEM_XFER_START 0x4D0000 // memory to memory transfer (not sure about which class this is) +#define NV3_PGRAPH_CLASS61_MEM2MEM_XFER_END 0x4D1FFF +#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_SCALED_START 0x4E0000 // class 55, 56 +#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_SCALED_END 0x4E1FFF + +#define NV3_PGRAPH_CLASS31_BLIT_START 0x500000 // Blit 2d image from memory +#define NV3_PGRAPH_CLASS31_BLIT_END 0x501FFF + +#define NV3_PGRAPH_CLASSXX_CPU2MEM_IMAGE_START 0x510000 // Used for class 33, 34, 54 +#define NV3_PGRAPH_CLASSXX_CPU2MEM_IMAGE_END 0x511FFF +#define NV3_PGRAPH_CLASSXX_CPU2MEM_BITMAP_START 0x520000 // not sure, might depend on format +#define NV3_PGRAPH_CLASSXX_CPU2MEM_BITMAP_END 0x521FFF + +#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_START 0x540000 // send image to vram, not sure what class +#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_END 0x541FFF +#define NV3_PGRAPH_CLASS54_CPU2MEM_STRETCHED_START 0x550000 // stretched cpu->vram transfer, 54 +#define NV3_PGRAPH_CLASS54_CPU2MEM_STRETCHED_END 0x551FFF + +#define NV3_PGRAPH_CLASS72_D3D5TRI_ZETA_START 0x570000 // [NV3] Copy a direct3d 5.0 accelerated triangle to the zeta buffer +#define NV3_PGRAPH_CLASS72_D3D5TRI_ZETA_END 0x571FFF +#define NV3_PGRAPH_CLASSXX_POINTZETA_START 0x580000 // possibly class 69 +#define NV3_PGRAPH_CLASSXX_POINTZETA_END 0x581FFF + +#define NV3_PGRAPH_CLASS62_MEM2IMAGE_START 0x5C0000 // class 55, 56, 62, 63? +#define NV3_PGRAPH_CLASS62_MEM2IMAGE_END 0x5C1FFF + +#define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers +#define NV3_PGRAPH_REAL_END 0x5C1FFF + +#define NV3_PRMCIO_START 0x601000 +#define NV3_PRMCIO_END 0x601FFF + +#define NV3_PDAC_START 0x680000 // OPTIONAL external DAC +#define NV3_PVIDEO_START 0x680000 // Video Generation / overlay configuration +#define NV3_PVIDEO_INTR 0x680100 +#define NV3_PVIDEO_INTR_EN 0x680140 +#define NV3_PVIDEO_END 0x6802FF +#define NV3_PRAMDAC_START 0x680300 + +#define NV3_PRAMDAC_CLOCK_MEMORY 0x680504 +#define NV3_PRAMDAC_CLOCK_MEMORY_VDIV 7:0 +#define NV3_PRAMDAC_CLOCK_MEMORY_NDIV 15:8 +#define NV3_PRAMDAC_CLOCK_MEMORY_PDIV 18:16 +#define NV3_PRAMDAC_CLOCK_PIXEL 0x680508 +#define NV3_PRAMDAC_COEFF_SELECT 0x68050C + +#define NV3_PRAMDAC_GENERAL_CONTROL 0x680600 + +// These are all 10-bit values, but aligned to 32bits +// so treating them as 32bit should be fine +#define NV3_PRAMDAC_VSERR_WIDTH 0x680700 +#define NV3_PRAMDAC_VEQU_END 0x680704 +#define NV3_PRAMDAC_VBBLANK_END 0x680708 +#define NV3_PRAMDAC_VBLANK_END 0x68070C +#define NV3_PRAMDAC_VBLANK_START 0x680710 +#define NV3_PRAMDAC_VBBLANK_START 0x680714 +#define NV3_PRAMDAC_VEQU_START 0x680718 +#define NV3_PRAMDAC_VTOTAL 0x68071C +#define NV3_PRAMDAC_HSYNC_WIDTH 0x680720 +#define NV3_PRAMDAC_HBURST_START 0x680724 +#define NV3_PRAMDAC_HBURST_END 0x680728 +#define NV3_PRAMDAC_HBLANK_START 0x68072C +#define NV3_PRAMDAC_HBLANK_END 0x680730 +#define NV3_PRAMDAC_HTOTAL 0x680734 +#define NV3_PRAMDAC_HEQU_WIDTH 0x680738 +#define NV3_PRAMDAC_HSERR_WIDTH 0x68073C + +#define NV3_PRAMDAC_END 0x680FFF +#define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC + + +#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO +#define NV3_USER_END 0xFFFFFF + +// easier name +#define NV3_OBJECT_SUBMIT_START NV3_USER_START +#define NV3_OBJECT_SUBMIT_END NV3_USER_END + +// also PDFB (Debug Framebuffer?) +#define NV3_PNVM_START 0x1000000 // VRAM access (max 8MB) +#define NV3_PNVM_END 0x17FFFFF + +// to be less confusing - NVM = "NV Memory" +#define NV3_VRAM_START NV3_PNVM_START +#define NV3_VRAM_END NV3_PNVM_END + +// control structures for dma'd in graphics objects from pfifo +// these all have configurable sizes, define them here +#define NV3_PRAMIN_START 0x1C00000 + +#define NV3_PRAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects +#define NV3_PRAMIN_RAMHT_END 0x1C00FFF +#define NV3_PRAMIN_RAMHT_SIZE_0 0xFFF +#define NV3_PRAMIN_RAMHT_SIZE_1 0x1FFF +#define NV3_PRAMIN_RAMHT_SIZE_2 0x3FFF +#define NV3_PRAMIN_RAMHT_SIZE_3 0x7FFF + +#define NV3_PRAMIN_RAMAU_START 0x1C01000 // Auxillary area +#define NV3_PRAMIN_RAMAU_END 0x1C01BFF +#define NV3_PRAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels +#define NV3_PRAMIN_RAMFC_END 0x1C01DFF +#define NV3_PRAMIN_RAMFC_SIZE_0 0x1FF +#define NV3_PRAMIN_RAMFC_SIZE_1 0xFFF +#define NV3_PRAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions +#define NV3_PRAMIN_RAMRO_SIZE_0 0x1FF +#define NV3_PRAMIN_RAMRO_SIZE_1 0x1FFF +#define NV3_PRAMIN_RAMRO_END 0x1C01FFF +#define NV3_PRAMIN_RAMRM_START 0x1C02000 +#define NV3_PRAMIN_RAMRM_END 0x1C02FFF + +#define NV3_PRAMIN_END 0x1FFFFFF + +// not done + +// Master Control + +#define NV3_PMC_BOOT 0x0 +#define NV3_PMC_INTERRUPT 0x100 +#define NV3_PMC_INTERRUPT_ENABLE 0x140 +#define NV3_PMC_ENABLE 0x200 +#define NV3_PMC_ENABLE_PAUDIO 0 // UNUSED - PAudio removed in NV3 Stepping B0 +#define NV3_PMC_ENABLE_PAUDIO_ENABLED 0x1 // UNUSED - PAudio removed in NV3 Stepping B0 +#define NV3_PMC_ENABLE_PMEDIA 4 +#define NV3_PMC_ENABLE_PMEDIA_ENABLED 0x1 +#define NV3_PMC_ENABLE_PFIFO 8 +#define NV3_PMC_ENABLE_PFIFO_ENABLED 0x1 +#define NV3_PMC_ENABLE_PGRAPH 12 +#define NV3_PMC_ENABLE_PGRAPH_ENABLED 0x1 +#define NV3_PMC_ENABLE_PPMI 16 +#define NV3_PMC_ENABLE_PPMI_ENABLED 0x1 +#define NV3_PMC_ENABLE_PFB 20 +#define NV3_PMC_ENABLE_PFB_ENABLED 0x1 +#define NV3_PMC_ENABLE_PCRTC 24 +#define NV3_PMC_ENABLE_PCRTC_ENABLED 0x1 +#define NV3_PMC_ENABLE_PVIDEO 28 +#define NV3_PMC_ENABLE_PVIDEO_ENABLED 0x1 + +// CRTC/CIO (0x3b0-0x3df) + +#define NV3_CRTC_DATA_OUT 0x3C0 +#define NV3_CRTC_MISCOUT 0x3C2 + +// These are standard (0-18h) +#define NV3_CRTC_REGISTER_HTOTAL 0x00 +#define NV3_CRTC_REGISTER_HDISPEND 0x01 +#define NV3_CRTC_REGISTER_HBLANKSTART 0x02 +#define NV3_CRTC_REGISTER_HBLANKEND 0x03 +#define NV3_CRTC_REGISTER_HRETRACESTART 0x04 +#define NV3_CRTC_REGISTER_HRETRACEEND 0x05 +#define NV3_CRTC_REGISTER_VTOTAL 0x06 +#define NV3_CRTC_REGISTER_OVERFLOW 0x07 +#define NV3_CRTC_REGISTER_PRESETROWSCAN 0x08 +#define NV3_CRTC_REGISTER_MAXSCAN 0x09 +#define NV3_CRTC_REGISTER_CURSOR_START 0x0A +#define NV3_CRTC_REGISTER_CURSOR_END 0x0B +#define NV3_CRTC_REGISTER_STARTADDR_HIGH 0x0C +#define NV3_CRTC_REGISTER_STARTADDR_LOW 0x0D +#define NV3_CRTC_REGISTER_CURSORLOCATION_HIGH 0x0E +#define NV3_CRTC_REGISTER_CURSORLOCATION_LOW 0x0F +#define NV3_CRTC_REGISTER_VRETRACESTART 0x10 +#define NV3_CRTC_REGISTER_VRETRACEEND 0x11 +#define NV3_CRTC_REGISTER_VDISPEND 0x12 +#define NV3_CRTC_REGISTER_OFFSET 0x13 +#define NV3_CRTC_REGISTER_UNDERLINELOCATION 0x14 +#define NV3_CRTC_REGISTER_STARTVBLANK 0x15 +#define NV3_CRTC_REGISTER_ENDVBLANK 0x16 +#define NV3_CRTC_REGISTER_CRTCCONTROL 0x17 +#define NV3_CRTC_REGISTER_LINECOMP 0x18 +#define NV3_CRTC_REGISTER_STANDARDVGA_END 0x18 + + +// These are nvidia (25-63) +#define NV3_CRTC_REGISTER_RPC0 0x19 // What does this mean? +#define NV3_CRTC_REGISTER_RPC1 0x1A // What does this mean? +#define NV3_CRTC_REGISTER_READ_BANK 0x1D +#define NV3_CRTC_REGISTER_WRITE_BANK 0x1E +#define NV3_CRTC_REGISTER_FORMAT 0x25 +#define NV3_CRTC_REGISTER_FORMAT_VDT10 0 // Use 10 bit vtotal value instead of 8 bit +#define NV3_CRTC_REGISTER_FORMAT_VDE10 1 // Use 10 bit dispend value instead of 8 bit +#define NV3_CRTC_REGISTER_FORMAT_VRS10 2 // Use 10 bit vblank start value instead of 8 bit +#define NV3_CRTC_REGISTER_FORMAT_VBS10 3 // Use 10 bit vsync start value instead of 8 bit +#define NV3_CRTC_REGISTER_FORMAT_HBE6 4 // Use 6 bit hsync start value +#define NV3_CRTC_REGISTER_PIXELMODE 0x28 + +#define NV3_CRTC_REGISTER_HEB 0x2D // HRS most significant bit + +#define NV3_CRTC_REGISTER_PIXELMODE_VGA 0x00 // vga textmode +#define NV3_CRTC_REGISTER_PIXELMODE_8BPP 0x01 +#define NV3_CRTC_REGISTER_PIXELMODE_16BPP 0x02 +#define NV3_CRTC_REGISTER_PIXELMODE_32BPP 0x03 + +#define NV3_CRTC_REGISTER_RMA 0x38 // REAL MODE ACCESS! + +// where the fuck is GDC? +#define NV3_CRTC_BANKED_128K_A0000 0x00 +#define NV3_CRTC_BANKED_64K_A0000 0x04 +#define NV3_CRTC_BANKED_32K_B0000 0x08 +#define NV3_CRTC_BANKED_32K_B8000 0x0C + + +#define NV3_RMA_REGISTER_START 0x3D0 +#define NV3_RMA_REGISTER_END 0x3D3 + +#define NV3_CRTC_REGISTER_NVIDIA_END 0x3F +// for 86box 8bit addressing +// get rid of this asap, replace with 32->8 macros +#define NV3_RMA_SIGNATURE_MSB 0x65 +#define NV3_RMA_SIGNATURE_BYTE2 0xD0 +#define NV3_RMA_SIGNATURE_BYTE1 0x16 +#define NV3_RMA_SIGNATURE_LSB 0x2B + +#define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F + + +//todo: pixel format + diff --git a/src/include/86box/video.h b/src/include/86box/video.h index 9ee710592..f9cf9cfec 100644 --- a/src/include/86box/video.h +++ b/src/include/86box/video.h @@ -589,6 +589,8 @@ extern const device_t voodoo_3_3500_se_agp_device; extern const device_t voodoo_3_3500_si_agp_device; extern const device_t velocity_100_agp_device; extern const device_t velocity_200_agp_device; +extern const device_t nv3_device_pci; +extern const device_t nv3_device_agp; /* Wyse 700 */ extern const device_t wy700_device; diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index bbd329b7e..1aec0e98d 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -27,7 +27,21 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c vid_tkd8001_ramdac.c vid_att20c49x_ramdac.c vid_s3.c vid_s3_virge.c vid_ibm_rgb528_ramdac.c vid_sdac_ramdac.c vid_ogc.c vid_mga.c vid_nga.c vid_tvp3026_ramdac.c vid_att2xc498_ramdac.c vid_xga.c - vid_bochs_vbe.c) + vid_bochs_vbe.c + nv/nv_base.c + nv/nv3/nv3_core.c nv/nv3/nv3_core_arbiter.c nv/nv3/nv3_interrupt.c + nv/nv3/subsystems/nv3_pramdac.c + nv/nv3/subsystems/nv3_pfifo.c + nv/nv3/subsystems/nv3_pgraph.c + nv/nv3/subsystems/nv3_pmc.c + nv/nv3/subsystems/nv3_pme.c + nv/nv3/subsystems/nv3_pextdev.c + nv/nv3/subsystems/nv3_pfb.c + nv/nv3/subsystems/nv3_pbus.c nv/nv3/subsystems/nv3_pbus_dma.c + nv/nv3/subsystems/nv3_ptimer.c + nv/nv3/subsystems/nv3_pramin.c nv/nv3/subsystems/nv3_pramin_ramht.c nv/nv3/subsystems/nv3_pramin_ramfc.c nv/nv3/subsystems/nv3_pramin_ramro.c + nv/nv3/subsystems/nv3_pvideo.c + ) if(G100) target_compile_definitions(vid PRIVATE USE_G100) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c new file mode 100644 index 000000000..3b4394561 --- /dev/null +++ b/src/video/nv/nv3/nv3_core.c @@ -0,0 +1,837 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 bringup and device emulation. + * + * Notes: + * xfree86 ref has INVERTED bit numbering? What? + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +nv3_t* nv3; + +// Prototypes for functions only used in this translation unit +void nv3_init_mappings_mmio(); +void nv3_init_mappings_svga(); +void nv3_shutdown_mappings_mmio(); +void nv3_shutdown_mappings_svga(); + +uint8_t nv3_svga_in(uint16_t addr, void* priv); +void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); + +// All MMIO regs are 32-bit i believe internally +// so we have to do some munging to get this to read + +// Read 8-bit MMIO +uint8_t nv3_mmio_read8(uint32_t addr, void* priv) +{ + // see if unaligned reads are a problem + uint32_t ret = nv3_mmio_read32(addr, priv); + return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFF); +} + +// Read 16-bit MMIO +uint16_t nv3_mmio_read16(uint32_t addr, void* priv) +{ + uint32_t ret = nv3_mmio_read32(addr, priv); + return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFFFF); +} + +// Read 32-bit MMIO +uint32_t nv3_mmio_read32(uint32_t addr, void* priv) +{ + return nv3_mmio_arbitrate_read(addr); +} + +// Write 8-bit MMIO +void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) +{ + // overwrite first 8bits of a 32 bit value + uint32_t new_val = nv3_mmio_read32(addr, NULL); + + new_val &= (~0xFF << (addr & 3) << 3); + new_val |= (val << ((addr & 3) << 3)); + + nv3_mmio_write32(addr, new_val, priv); +} + +// Write 16-bit MMIO +void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) +{ + // overwrite first 16bits of a 32 bit value + uint32_t new_val = nv3_mmio_read32(addr, NULL); + + new_val &= (~0xFFFF << (addr & 3) << 3); + new_val |= (val << ((addr & 3) << 3)); + + nv3_mmio_write32(addr, new_val, priv); +} + +// Write 32-bit MMIO +void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) +{ + nv3_mmio_arbitrate_write(addr, val); +} + +// PCI stuff +// BAR0 Pointer to MMIO space +// BAR1 Pointer to Linear Framebuffer (NV_USER) + +uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) +{ + uint8_t ret = 0x00; + + // figure out what size this gets read as first + // seems func does not matter at least here? + switch (addr) + { + // Get the pci vendor id.. + + case NV3_PCI_CFG_VENDOR_ID: + ret = (PCI_VENDOR_SGS_NV & 0xFF); + break; + + case NV3_PCI_CFG_VENDOR_ID + 1: // all access 8bit + ret = (PCI_VENDOR_SGS_NV >> 8); + break; + + // device id + + case NV3_PCI_CFG_DEVICE_ID: + ret = (PCI_DEVICE_NV3 & 0xFF); + break; + + case NV3_PCI_CFG_DEVICE_ID+1: + ret = (PCI_DEVICE_NV3 >> 8); + break; + + // various capabilities + // IO space enabled + // Memory space enabled + // Bus master enabled + // Write/inval enabled + // Pal snoop enabled + // Capabiliies list enabled + // 66Mhz FSB capable + + case PCI_REG_COMMAND_L: + ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L]; // we actually respond to the fucking + break; + + case PCI_REG_COMMAND_H: + ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] | NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back + break; + + // pci status register + case PCI_REG_STATUS_L: + if (nv3->pextdev.straps + & NV3_PSTRAPS_BUS_SPEED_66MHZ) + ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE); + else + ret = nv3->pci_config.pci_regs[PCI_REG_STATUS_L]; + + break; + + case PCI_REG_STATUS_H: + ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); + break; + + case NV3_PCI_CFG_REVISION: + ret = NV3_PCI_CFG_REVISION_B00; // Commercial release + break; + + case PCI_REG_PROG_IF: + ret = 0x00; + break; + + case NV3_PCI_CFG_SUBCLASS_CODE: + ret = 0x00; // nothing + break; + + case NV3_PCI_CFG_CLASS_CODE: + ret = NV3_PCI_CFG_CLASS_CODE_VGA; // CLASS_CODE_VGA + break; + + case NV3_PCI_CFG_CACHE_LINE_SIZE: + ret = NV3_PCI_CFG_CACHE_LINE_SIZE_DEFAULT_FROM_VBIOS; + break; + + case NV3_PCI_CFG_LATENCY_TIMER: + case NV3_PCI_CFG_HEADER_TYPE: + case NV3_PCI_CFG_BIST: + ret = 0x00; + break; + + // BARs are marked as prefetchable per the datasheet + case NV3_PCI_CFG_BAR0_L: + case NV3_PCI_CFG_BAR1_L: + // only bit that matters is bit 3 (prefetch bit) + ret =(NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED << NV3_PCI_CFG_BAR_PREFETCHABLE); + break; + + // These registers are hardwired to zero per the datasheet + // Writes have no effect, we can just handle it here though + case NV3_PCI_CFG_BAR0_BYTE1 ... NV3_PCI_CFG_BAR0_BYTE2: + case NV3_PCI_CFG_BAR1_BYTE1 ... NV3_PCI_CFG_BAR1_BYTE2: + ret = 0x00; + break; + + // MMIO base address + case NV3_PCI_CFG_BAR0_BASE_ADDRESS: + ret = nv3->nvbase.bar0_mmio_base >> 24;//8bit value + break; + + case NV3_PCI_CFG_BAR1_BASE_ADDRESS: + ret = nv3->nvbase.bar1_lfb_base >> 24; //8bit value + break; + + case NV3_PCI_CFG_ENABLE_VBIOS: + ret = nv3->pci_config.vbios_enabled; + break; + + case NV3_PCI_CFG_INT_LINE: + ret = nv3->pci_config.int_line; + break; + + case NV3_PCI_CFG_INT_PIN: + ret = PCI_INTA; + break; + + case NV3_PCI_CFG_MIN_GRANT: + ret = NV3_PCI_CFG_MIN_GRANT_DEFAULT; + break; + + case NV3_PCI_CFG_MAX_LATENCY: + ret = NV3_PCI_CFG_MAX_LATENCY_DEFAULT; + break; + + //bar2-5 are not used and hardwired to 0 + case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END: + ret = 0x00; + break; + + case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START: + case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END: + ret = nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)]; + break; + + default: // by default just return pci_config.pci_regs + ret = nv3->pci_config.pci_regs[addr]; + break; + + } + + nv_log("NV3: nv3_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret); + return ret; +} + +void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) +{ + + // TOTAL IRRELEVANCY + + // some addresses are not writable so can't have any effect and can't be allowed to be modified using this code + // only the most significant byte of the PCI BARs can be modified + if (addr >= NV3_PCI_CFG_BAR0_L && addr <= NV3_PCI_CFG_BAR0_BYTE2 + && addr >= NV3_PCI_CFG_BAR1_L && addr <= NV3_PCI_CFG_BAR1_BYTE2) + return; + + nv_log("NV3: nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); + + nv3->pci_config.pci_regs[addr] = val; + + switch (addr) + { + // standard pci command stuff + case PCI_REG_COMMAND_L: + nv3->pci_config.pci_regs[PCI_REG_COMMAND_L] = val; + // actually update the mappings + nv3_update_mappings(); + break; + // pci status register + case PCI_REG_STATUS_L: + nv3->pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE); + break; + case PCI_REG_STATUS_H: + nv3->pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); + break; + //TODO: ACTUALLY REMAP THE MMIO AND NV_USER + case NV3_PCI_CFG_BAR0_BASE_ADDRESS: + nv3->nvbase.bar0_mmio_base = val << 24; + nv3_update_mappings(); + break; + case NV3_PCI_CFG_BAR1_BASE_ADDRESS: + nv3->nvbase.bar1_lfb_base = val << 24; + nv3_update_mappings(); + break; + case NV3_PCI_CFG_ENABLE_VBIOS: + case NV3_PCI_CFG_VBIOS_BASE: + + // make sure we are actually toggling the vbios, not the rom base + if (addr == NV3_PCI_CFG_ENABLE_VBIOS) + nv3->pci_config.vbios_enabled = (val & 0x01); + + if (nv3->pci_config.vbios_enabled) + { + // First see if we simply wanted to change the VBIOS location + + // Enable it in case it was disabled before + mem_mapping_enable(&nv3->nvbase.vbios.mapping); + + if (addr != NV3_PCI_CFG_ENABLE_VBIOS) + { + uint32_t old_addr = nv3->nvbase.vbios.mapping.base; + // 9bit register + uint32_t new_addr = nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 | + nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16; + + // move it + mem_mapping_set_addr(&nv3->nvbase.vbios.mapping, new_addr, 0x8000); + + nv_log("...i like to move it move it (VBIOS Relocation) 0x%04x -> 0x%04x\n", old_addr, new_addr); + + } + else + { + nv_log("...VBIOS Enable\n"); + } + } + else + { + nv_log("...VBIOS Disable\n"); + mem_mapping_disable(&nv3->nvbase.vbios.mapping); + + } + break; + case NV3_PCI_CFG_INT_LINE: + nv3->pci_config.int_line = val; + break; + //bar2-5 are not used and can't be written to + case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END: + break; + + // these are mirrored to the subsystem id and also stored in the ROMBIOS + case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START: + case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END: + nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val; + break; + + default: + + } +} + +void nv3_close(void* priv) +{ + svga_close(&nv3->nvbase.svga); + free(nv3); +} + + +// +// SVGA functions +// +void nv3_recalc_timings(svga_t* svga) +{ + nv3_t* nv3 = (nv3_t*)svga->priv; + + svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; + + // should these actually use separate values? + // i don't we should force the top 2 bits to 1... + + // required for VESA resolutions, force parameters higher + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; + + if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) + svga->hdisp += 0x100; // large screen bit + + // Set the pixel mode + switch (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03) + { + ///0x0 is VGA textmode + case NV3_CRTC_REGISTER_PIXELMODE_8BPP: + svga->bpp = 8; + svga->lowres = 0; + svga->render = svga_render_8bpp_highres; + break; + case NV3_CRTC_REGISTER_PIXELMODE_16BPP: + svga->bpp = 16; + svga->lowres = 0; + svga->render = svga_render_16bpp_highres; + break; + case NV3_CRTC_REGISTER_PIXELMODE_32BPP: + svga->bpp = 32; + svga->lowres = 0; + svga->render = svga_render_32bpp_highres; + break; + } + + // from nv_riva128 + if (((svga->miscout >> 2) & 2) == 2) + { + // set clocks + nv3_pramdac_set_pixel_clock(); + nv3_pramdac_set_vram_clock(); + } +} + +void nv3_speed_changed(void* priv) +{ + nv3_recalc_timings(&nv3->nvbase.svga); +} + +// Force Redraw +// Reset etc. +void nv3_force_redraw(void* priv) +{ + nv3->nvbase.svga.fullchange = changeframecount; +} + +// Read from SVGA core memory +uint8_t nv3_svga_in(uint16_t addr, void* priv) +{ + nv3_t* nv3 = (nv3_t*)priv; + + uint8_t ret = 0x00; + + // If we need to RMA from GPU MMIO, go do that + if (addr >= NV3_RMA_REGISTER_START + && addr <= NV3_RMA_REGISTER_END) + { + if (!(nv3->pbus.rma.mode & 0x01)) + return ret; + + // must be dword aligned + uint32_t real_rma_read_addr = ((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX - 1) << 1) + (addr & 0x03); + ret = nv3_pbus_rma_read(real_rma_read_addr); + return ret; + } + + // mask off b0/d0 registers + if ((((addr & 0xFFF0) == 0x3D0 + || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) + && !(nv3->nvbase.svga.miscout & 1)) + addr ^= 0x60; + + switch (addr) + { + // Alias for "get current SVGA CRTC register ID" + case 0x3D4: + ret = nv3->nvbase.svga.crtcreg; + break; + case 0x3D5: + // Support the extended NVIDIA CRTC register range + switch (nv3->nvbase.svga.crtcreg) + { + default: + ret = nv3->nvbase.svga.crtc[nv3->nvbase.svga.crtcreg]; + } + break; + default: + ret = svga_in(addr, &nv3->nvbase.svga); + break; + } + + return ret; //TEMP +} + +// Write to SVGA core memory +void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) +{ + + // If we need to RMA to GPU MMIO, go do that + if (addr >= NV3_RMA_REGISTER_START + && addr <= NV3_RMA_REGISTER_END) + { + // we don't need to store these registers... + nv3->pbus.rma.rma_regs[addr & 3] = val; + + if (!(nv3->pbus.rma.mode & 0x01)) // we are halfway through sending something + return; + + uint32_t real_rma_write_addr = ((nv3->pbus.rma.mode & (NV3_CRTC_REGISTER_RMA_MODE_MAX - 1)) << 1) + (addr & 0x03); + + nv3_pbus_rma_write(real_rma_write_addr, nv3->pbus.rma.rma_regs[addr & 3]); + return; + } + + // mask off b0/d0 registers + if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) + && addr < 0x3de) + && !(nv3->nvbase.svga.miscout & 1))//miscout bit 7 controls mappping + addr ^= 0x60; + + uint8_t crtcreg = nv3->nvbase.svga.crtcreg; + uint8_t old_value; + + // todo: + // RMA + // Pixel formats (8bit vs 555 vs 565) + // VBE 3.0? + + switch (addr) + { + case 0x3D4: + // real mode access to GPU MMIO space... + nv3->nvbase.svga.crtcreg = val; + break; + // support the extended crtc regs and debug this out + case 0x3D5: + + // Implements the VGA Protect register + if ((nv3->nvbase.svga.crtcreg < NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80)) + return; + + // Ignore certain bits when VGA Protect register set and we are writing to CRTC register=07h + if ((nv3->nvbase.svga.crtcreg == NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80)) + val = (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_OVERFLOW] & ~0x10) | (val & 0x10); + + // set the register value... + nv3->nvbase.svga.crtc[crtcreg] = val; + // ...now act on it + + // Handle nvidia extended Bank0/Bank1 IDs + switch (crtcreg) + { + case NV3_CRTC_REGISTER_READ_BANK: + nv3->nvbase.cio_read_bank = val; + if (nv3->nvbase.svga.chain4) // chain4 addressing (planar?) + nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 15; + else + nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 13; // extended bank numbers + break; + case NV3_CRTC_REGISTER_WRITE_BANK: + nv3->nvbase.cio_write_bank = val; + if (nv3->nvbase.svga.chain4) + nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 15; + else + nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 13; + break; + case NV3_CRTC_REGISTER_RMA: + nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX; + break; + } + + break; + default: + svga_out(addr, val, &nv3->nvbase.svga); + break; + } + +} + +void nv3_draw_cursor(svga_t* svga, int32_t drawline) +{ + nv_log("nv3_draw_cursor drawline=0x%04x", drawline); +} + +// Initialise the MMIO mappings +void nv3_init_mappings_mmio() +{ + nv_log("NV3: Initialising 32MB MMIO area\n"); + + // 0x0 - 1000000: regs + // 0x1000000-2000000 + + // initialize the mmio mapping + mem_mapping_add(&nv3->nvbase.mmio_mapping, 0, 0, + nv3_mmio_read8, + nv3_mmio_read16, + nv3_mmio_read32, + nv3_mmio_write8, + nv3_mmio_write16, + nv3_mmio_write32, + NULL, MEM_MAPPING_EXTERNAL, nv3); + + // initialize the mmio mapping + mem_mapping_add(&nv3->nvbase.ramin_mapping, 0, 0, + nv3_ramin_read8, + nv3_ramin_read16, + nv3_ramin_read32, + nv3_ramin_write8, + nv3_ramin_write16, + nv3_ramin_write32, + NULL, MEM_MAPPING_EXTERNAL, nv3); + + + mem_mapping_add(&nv3->nvbase.ramin_mapping_mirror, 0, 0, + nv3_ramin_read8, + nv3_ramin_read16, + nv3_ramin_read32, + nv3_ramin_write8, + nv3_ramin_write16, + nv3_ramin_write32, + NULL, MEM_MAPPING_EXTERNAL, nv3); + + +} + +void nv3_init_mappings_svga() +{ + nv_log("NV3: Initialising SVGA core memory mapping\n"); + + // setup the svga mappings + mem_mapping_set(&nv3->nvbase.framebuffer_mapping, 0, 0, + svga_read_linear, + svga_readw_linear, + svga_readl_linear, + svga_write_linear, + svga_writew_linear, + svga_writel_linear, + NULL, 0, &nv3->nvbase.svga); + + // the SVGA/LFB mapping is also mirrored + mem_mapping_set(&nv3->nvbase.framebuffer_mapping_mirror, 0, 0, + svga_read_linear, + svga_readw_linear, + svga_readl_linear, + svga_write_linear, + svga_writew_linear, + svga_writel_linear, + NULL, 0, &nv3->nvbase.svga); + + io_sethandler(0x03c0, 0x0020, + nv3_svga_in, NULL, NULL, + nv3_svga_out, NULL, NULL, + nv3); +} + +void nv3_init_mappings() +{ + nv3_init_mappings_mmio(); + nv3_init_mappings_svga(); +} + +// Updates the mappings after initialisation. +void nv3_update_mappings() +{ + + // setting this to 0 doesn't seem to disable it, based on the datasheet + + nv_log("\nMemory Mapping Config Change:\n"); + + (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); + + io_removehandler(0x03c0, 0x0020, + nv3_svga_in, NULL, NULL, + nv3_svga_out, NULL, NULL, + nv3); + + if (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) + io_sethandler(0x03c0, 0x0020, + nv3_svga_in, NULL, NULL, + nv3_svga_out, NULL, NULL, + nv3); + + // turn off bar0 and bar1 by defualt + mem_mapping_disable(&nv3->nvbase.mmio_mapping); + mem_mapping_disable(&nv3->nvbase.framebuffer_mapping); + mem_mapping_disable(&nv3->nvbase.framebuffer_mapping_mirror); + mem_mapping_disable(&nv3->nvbase.ramin_mapping); + mem_mapping_disable(&nv3->nvbase.ramin_mapping_mirror); + + if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM) + { + nv_log("NV3: The memory was turned off, not much is going to happen.\n"); + return; + } + + mem_mapping_enable(&nv3->nvbase.mmio_mapping); + mem_mapping_enable(&nv3->nvbase.framebuffer_mapping); + mem_mapping_enable(&nv3->nvbase.framebuffer_mapping_mirror); + mem_mapping_enable(&nv3->nvbase.ramin_mapping); + mem_mapping_enable(&nv3->nvbase.ramin_mapping_mirror); + + // first map bar0 + + nv_log("NV3: BAR0 (MMIO Base) = 0x%08x\n", nv3->nvbase.bar0_mmio_base); + + //mem_mapping_enable(&nv3->nvbase.mmio_mapping); // should have no effect if already enabled + + mem_mapping_set_addr(&nv3->nvbase.mmio_mapping, nv3->nvbase.bar0_mmio_base, NV3_MMIO_SIZE); + + + // if this breaks anything, remove it + // skeptical that 0 is used to disable... + nv_log("NV3: BAR1 (Linear Framebuffer / NV_USER Base & RAMIN) = 0x%08x\n", nv3->nvbase.bar1_lfb_base); + + // this is likely mirrored + // 4x on 2mb cards + // 2x on 4mb cards + // and not at all on 8mb + mem_mapping_enable(&nv3->nvbase.framebuffer_mapping); + mem_mapping_enable(&nv3->nvbase.framebuffer_mapping_mirror); + mem_mapping_enable(&nv3->nvbase.ramin_mapping); + mem_mapping_enable(&nv3->nvbase.ramin_mapping_mirror); + + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_MMIO_SIZE); + // 4MB VRAM memory map: + // LFB_BASE+VRAM_SIZE=RAMIN Mirror(?) 0x1400000 (VERIFY PCBOX) + // LFB_BASE+VRAM_SIZE*2=LFB Mirror(?) 0x1800000 + // LFB_BASE+VRAM_SIZE*3=Definitely RAMIN (then it ends, the total ram space is 16mb) 0x1C00000 + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + VRAM_SIZE_4MB, VRAM_SIZE_4MB); + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + (VRAM_SIZE_4MB * 2), VRAM_SIZE_4MB); + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + (VRAM_SIZE_4MB * 3), VRAM_SIZE_4MB); + // TODO: RAMIN and its mirror + + // Did we change the banked SVGA mode? + switch (nv3->nvbase.svga.gdcreg[0x06] & 0x0c) + { + case NV3_CRTC_BANKED_128K_A0000: + nv_log("NV3: SVGA Banked Mode = 128K @ A0000h\n"); + mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000 + nv3->nvbase.svga.banked_mask = 0x1FFFF; + break; + case NV3_CRTC_BANKED_64K_A0000: + nv_log("NV3: SVGA Banked Mode = 64K @ A0000h\n"); + mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000 + nv3->nvbase.svga.banked_mask = 0xFFFF; + break; + case NV3_CRTC_BANKED_32K_B0000: + nv_log("NV3: SVGA Banked Mode = 32K @ B0000h\n"); + mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000 + nv3->nvbase.svga.banked_mask = 0x7FFF; + break; + case NV3_CRTC_BANKED_32K_B8000: + nv_log("NV3: SVGA Banked Mode = 32K @ B8000h\n"); + mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000 + nv3->nvbase.svga.banked_mask = 0x7FFF; + break; + } +} + +// +// Init code +// +void* nv3_init(const device_t *info) +{ + nv_log("NV3: initialising core\n"); + + // currently using ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS] + // ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS] seems to be broken :( + + int32_t err = rom_init(&nv3->nvbase.vbios, NV3_VBIOS_ERAZOR_V15403, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); + + if (err) + nv_log("NV3: failed to load VBIOS err=%d\n", err); + else + nv_log("NV3: Successfully loaded VBIOS %s\n", NV3_VBIOS_ERAZOR_V15403); + + // set up the bus and start setting up SVGA core + if (nv3->nvbase.bus_generation == nv_bus_pci) + { + nv_log("NV3: using PCI bus\n"); + + pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); + + svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, VRAM_SIZE_4MB, + nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); + } + else if (nv3->nvbase.bus_generation == nv_bus_agp_1x) + { + nv_log("NV3: using AGP 1X bus\n"); + + pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); + + svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, VRAM_SIZE_4MB, + nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); + } + + // set vram + nv_log("NV3: VRAM=%d bytes\n", nv3->nvbase.svga.vram_max); + + // init memory mappings + nv3_init_mappings(); + + // make us actually exist + nv3->pci_config.int_line = 0xFF; // per datasheet + nv3->pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM; + + // svga is done, so now initialise the real gpu + nv_log("NV3: Initialising GPU core...\n"); + + nv3_pextdev_init(); // Initialise Straps + nv3_pmc_init(); // Initialise Master Control + nv3_pbus_init(); // Initialise Bus (the 128 part of riva) + nv3_pfb_init(); // Initialise Framebuffer Interface + nv3_pramdac_init(); // Initialise RAMDAC (CLUT, final pixel presentation etc) + nv3_pfifo_init(); // Initialise FIFO for graphics object submission + nv3_pgraph_init(); // Initialise accelerated graphics engine + nv3_ptimer_init(); // Initialise programmable interval timer + nv3_pvideo_init(); // Initialise video overlay engines + + return nv3; +} + +// This function simply allocates ram and sets the bus to pci before initialising. +void* nv3_init_pci(const device_t* info) +{ + nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); + nv3->nvbase.bus_generation = nv_bus_pci; + nv3_init(info); +} + +// This function simply allocates ram and sets the bus to agp before initialising. +void* nv3_init_agp(const device_t* info) +{ + nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); + nv3->nvbase.bus_generation = nv_bus_agp_1x; + nv3_init(info); +} + +// NV3 (RIVA 128) +// PCI +// 2MB or 4MB VRAM +const device_t nv3_device_pci = +{ + .name = "NVidia RIVA 128 (NV3) PCI", + .internal_name = "nv3", + .flags = DEVICE_PCI, + .local = 0, + .init = nv3_init_pci, + .close = nv3_close, + .speed_changed = nv3_speed_changed, + .force_redraw = nv3_force_redraw +}; + +// NV3 (RIVA 128) +// AGP +// 2MB or 4MB VRAM +const device_t nv3_device_agp = +{ + .name = "NVidia RIVA 128 (NV3) AGP", + .internal_name = "nv3_agp", + .flags = DEVICE_AGP, + .local = 0, + .init = nv3_init_agp, + .close = nv3_close, + .speed_changed = nv3_speed_changed, + .force_redraw = nv3_force_redraw +}; \ No newline at end of file diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c new file mode 100644 index 000000000..0b307e84a --- /dev/null +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -0,0 +1,198 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * The insane NV3 MMIO arbiter. + * Writes to ALL sections of the GPU based on the write position + * All writes are internally considered to be 32-bit! Be careful... + * + * Also handles interrupt dispatch + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +// STANDARD NV3 includes +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Gets a register... +// move this somewhere else when we have more models +nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs) +{ + for (int32_t reg_num = 0; reg_num < num_regs; reg_num++) + { + if (register_list[reg_num].address == NV_REG_LIST_END) + break; //unimplemented + + if (register_list[reg_num].address == address) + return ®ister_list[reg_num]; + } + + return NULL; +} + +// Arbitrates an MMIO read +uint32_t nv3_mmio_arbitrate_read(uint32_t address) +{ + uint32_t ret = 0x00; + + // note: some registers are byte aligned not dword aligned + // only very few are though, so they can be handled specially, using the register list most likely + address &= 0xFFFFFC; + + // gigantic set of if statements to send the write to the right subsystem + if (address >= NV3_PMC_START && address <= NV3_PMC_END) + ret = nv3_pmc_read(address); + else if (address >= NV3_CIO_START && address <= NV3_CIO_END) + ret = nv3_cio_read(address); + else if (address >= NV3_PBUS_PCI_START && address <= NV3_PBUS_PCI_END) + ret = nv3_pci_read(0x00, address & 0xFF, NULL); + else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END) + ret = nv3_pbus_read(address); + else if (address >= NV3_PFB_START && address <= NV3_PFB_END) + ret = nv3_pfb_read(address); + else if (address >= NV3_PRM_START && address <= NV3_PRM_END) + ret = nv3_prm_read(address); + else if (address >= NV3_PRMIO_START && address <= NV3_PRMIO_END) + ret = nv3_prmio_read(address); + else if (address >= NV3_PTIMER_START && address <= NV3_PTIMER_END) + ret = nv3_ptimer_read(address); + else if (address >= NV3_PFB_START && address <= NV3_PFB_END) + ret = nv3_pfb_read(address); + else if (address >= NV3_PEXTDEV_START && address <= NV3_PEXTDEV_END) + ret = nv3_pextdev_read(address); + else if (address >= NV3_PROM_START && address <= NV3_PROM_END) + ret = nv3_prom_read(address); + else if (address >= NV3_PALT_START && address <= NV3_PALT_END) + ret = nv3_palt_read(address); + else if (address >= NV3_PME_START && address <= NV3_PME_END) + ret = nv3_pme_read(address); + else if (address >= NV3_PGRAPH_START && address <= NV3_PGRAPH_REAL_END) // what we're actually doing here determined by nv3_pgraph_* func + ret = nv3_pgraph_read(address); + else if (address >= NV3_PRMCIO_START && address <= NV3_PRMCIO_END) + ret = nv3_prmcio_read(address); + else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END) + ret = nv3_pvideo_read(address); + else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) + ret = nv3_pramdac_read(address); + else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) + ret = nv3_vram_read(address); + else if (address >= NV3_USER_START && address <= NV3_USER_END) + ret = nv3_user_read(address); + else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) + ret = nv3_pramin_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function + else + { + nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); + return 0x00; + } + + nv_log("NV3: MMIO read, 0x%08x <- 0x%08x\n", ret, address); + return ret; +} + +void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) +{ + // note: some registers are byte aligned not dword aligned + // only very few are though, so they can be handled specially, using the register list most likely + address &= 0xFFFFFC; + + // gigantic set of if statements to send the write to the right subsystem + if (address >= NV3_PMC_START && address <= NV3_PMC_END) + nv3_pmc_write(address, value); + else if (address >= NV3_CIO_START && address <= NV3_CIO_END) + nv3_cio_write(address, value); + else if (address >= NV3_PBUS_PCI_START && address <= NV3_PBUS_PCI_END) // PCI mirrored at 0x1800 in MMIO + nv3_pci_write(0x00, address & 0xFF, value, NULL); // priv does not matter + else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END) + nv3_pbus_write(address, value); + else if (address >= NV3_PFIFO_START && address <= NV3_PFIFO_END) + nv3_pfifo_write(address, value); + else if (address >= NV3_PRM_START && address <= NV3_PRM_END) + nv3_prm_write(address, value); + else if (address >= NV3_PRMIO_START && address <= NV3_PRMIO_END) + nv3_prmio_write(address, value); + else if (address >= NV3_PTIMER_START && address <= NV3_PTIMER_END) + nv3_ptimer_write(address, value); + else if (address >= NV3_PFB_START && address <= NV3_PFB_END) + nv3_pfb_write(address, value); + else if (address >= NV3_PEXTDEV_START && address <= NV3_PEXTDEV_END) + nv3_pextdev_write(address, value); + else if (address >= NV3_PROM_START && address <= NV3_PROM_END) + nv3_prom_write(address, value); + else if (address >= NV3_PALT_START && address <= NV3_PALT_END) + nv3_palt_write(address, value); + else if (address >= NV3_PME_START && address <= NV3_PME_END) + nv3_pme_write(address, value); + else if (address >= NV3_PGRAPH_START && address <= NV3_PGRAPH_REAL_END) // what we're actually doing here is determined by the nv3_pgraph_* functions + nv3_pgraph_write(address, value); + else if (address >= NV3_PRMCIO_START && address <= NV3_PRMCIO_END) + nv3_prmcio_write(address, value); + else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END) + nv3_pvideo_write(address, value); + else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) + nv3_pramdac_write(address, value); + else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) + nv3_vram_write(address, value); + else if (address >= NV3_USER_START && address <= NV3_USER_END) + nv3_user_write(address, value); + else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) + nv3_pramin_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions + else + { + nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); + return; + } + + nv_log("NV3: MMIO write, 0x%08x -> 0x%08x\n", value, address); +} + + +// // +// ******* DUMMY FUNCTIONS FOR UNIMPLEMENTED SUBSYSTEMS ******* // +// // + +// Read and Write functions for GPU subsystems +// Remove the ones that aren't used here eventually, have all of htem for now +uint32_t nv3_cio_read(uint32_t address) { return 0; }; +void nv3_cio_write(uint32_t address, uint32_t value) {}; +uint32_t nv3_prm_read(uint32_t address) { return 0; }; +void nv3_prm_write(uint32_t address, uint32_t value) {}; +uint32_t nv3_prmio_read(uint32_t address) { return 0; }; +void nv3_prmio_write(uint32_t address, uint32_t value) {}; +uint32_t nv3_ptimer_read(uint32_t address) { return 0; }; +void nv3_ptimer_write(uint32_t address, uint32_t value) {}; +uint32_t nv3_prom_read(uint32_t address) { return 0; }; +void nv3_prom_write(uint32_t address, uint32_t value) {}; +uint32_t nv3_palt_read(uint32_t address) { return 0; }; +void nv3_palt_write(uint32_t address, uint32_t value) {}; + +// TODO: PGRAPH class registers +uint32_t nv3_prmcio_read(uint32_t address) { return 0; }; +void nv3_prmcio_write(uint32_t address, uint32_t value) {}; + +uint32_t nv3_vram_read(uint32_t address) { return 0; }; +void nv3_vram_write(uint32_t address, uint32_t value) {}; + +uint32_t nv3_user_read(uint32_t address) { return 0; }; +void nv3_user_write(uint32_t address, uint32_t value) {}; +uint32_t nv3_pramin_read(uint32_t address) { return 0; }; +void nv3_pramin_write(uint32_t address, uint32_t value) {}; \ No newline at end of file diff --git a/src/video/nv/nv3/nv3_interrupt.c b/src/video/nv/nv3/nv3_interrupt.c new file mode 100644 index 000000000..e69de29bb diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c new file mode 100644 index 000000000..a344d8627 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -0,0 +1,249 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PBUS: 128-bit unified bus + * + * + * + * Authors: Connor Hyde, I need a better email dataess ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// NV3 PBUS RMA - Real Mode Access for VBIOS +// This basically works like a shifter, you write one byte at a time from [0x3d0...0x3d3] and it shifts it in to build a 32-bit MMIO address... +// Putting this in pbus because imo it makes the most sense (related to memory access/memory interface) + +nv_register_t pbus_registers[] = { + { NV3_PBUS_INTR, "PBUS - Interrupt Status", NULL, NULL}, + { NV3_PBUS_INTR_EN, "PBUS - Interrupt Enable", NULL, NULL,}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +void nv3_pbus_init() +{ + nv_log("NV3: Initialising PBUS..."); + + nv_log("Done\n"); +} + +uint32_t nv3_pbus_read(uint32_t address) +{ + nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PBUS Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + switch (reg->address) + { + case NV3_PBUS_INTR: + return nv3->pbus.interrupt_status; + break; + case NV3_PBUS_INTR_EN: + return nv3->pbus.interrupt_enable; + break; + } + + } + } + + return 0x0; +} + +void nv3_pbus_write(uint32_t address, uint32_t value) +{ + nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); + + nv_log("NV3: PBUS Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + // Interrupt registers + // Interrupt state: + // Bit 0 - PCI Bus Error + case NV3_PBUS_INTR: + nv3->pbus.interrupt_status &= ~value; + nv3_pmc_clear_interrupts(); + break; + case NV3_PBUS_INTR_EN: + nv3->pbus.interrupt_enable = value & 0x00000001; + break; + } + + } + } +} + +uint8_t nv3_pbus_rma_read(uint16_t addr) +{ + addr &= 0xFF; + uint32_t real_final_address; + uint8_t ret; + + switch (addr) + { + // signature so you know reads work + case 0x00: + ret = NV3_RMA_SIGNATURE_MSB; + break; + case 0x01: + ret = NV3_RMA_SIGNATURE_BYTE2; + break; + case 0x02: + ret = NV3_RMA_SIGNATURE_BYTE1; + break; + case 0x03: + ret = NV3_RMA_SIGNATURE_LSB; + break; + case 0x08 ... 0x0B: + // reads must be dword aligned + real_final_address = (nv3->pbus.rma.addr + (addr & 0x03)); + + if (nv3->pbus.rma.addr < NV3_MMIO_SIZE) + ret = nv3_mmio_read8(real_final_address, NULL); + else + { + // ABOVE CODE IS TEMPORARY UNTIL PNVM EXISTS!!!!! + // would svga->fast work? + nv3->nvbase.svga.chain4 = true; + nv3->nvbase.svga.packed_chain4 = true; + ret = svga_read_linear((real_final_address - NV3_MMIO_SIZE) & (VRAM_SIZE_4MB - 1), &nv3->nvbase.svga); + nv3->nvbase.svga.chain4 = false; + nv3->nvbase.svga.packed_chain4 = false; + } + + // log current location for vbios RE + nv_log("NV3: MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + addr, real_final_address, ret); + + break; + } + + return ret; +} + +// Implements a 32-bit write using 16 bit port number +void nv3_pbus_rma_write(uint16_t addr, uint8_t val) +{ + uint8_t ret = 0x00; + + // addresses are in reality 8bit so just mask it to be safe + addr &= 0xFF; + + // format: + // 0x00 ID + // 0x04 Pointer to data + // 0x08 Data port(?) + // 0x0B Data - 32bit. SENT IN THE RIGHT ORDER FOR ONCE WAHOO! + // 0x10 Increment (?) data - implemented the same as data for now + + if (addr < 0x08) + { + switch (addr % 0x04) + { + case 0x00: // lowest byte + nv3->pbus.rma.addr &= ~0xff; + nv3->pbus.rma.addr |= val; + break; + case 0x01: // 2nd highest byte + nv3->pbus.rma.addr &= ~0xff00; + nv3->pbus.rma.addr |= (val << 8); + break; + case 0x02: // 3rd highest byte + nv3->pbus.rma.addr &= ~0xff0000; + nv3->pbus.rma.addr |= (val << 16); + break; + case 0x03: // 4th highest byte + nv3->pbus.rma.addr &= ~0xff000000; + nv3->pbus.rma.addr |= (val << 24); + break; + } + } + // Data to send to MMIO + else + { + switch (addr % 0x04) + { + case 0x00: // lowest byte + nv3->pbus.rma.data &= ~0xff; + nv3->pbus.rma.data |= val; + break; + case 0x01: // 2nd highest byte + nv3->pbus.rma.data &= ~0xff00; + nv3->pbus.rma.data |= (val << 8); + break; + case 0x02: // 3rd highest byte + nv3->pbus.rma.data &= ~0xff0000; + nv3->pbus.rma.data |= (val << 16); + break; + case 0x03: // 4th highest byte + nv3->pbus.rma.data &= ~0xff000000; + nv3->pbus.rma.data |= (val << 24); + + nv_log("NV3: MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + addr, nv3->pbus.rma.addr, nv3->pbus.rma.data); + + if (nv3->pbus.rma.addr < NV3_MMIO_SIZE) + nv3_mmio_write32(nv3->pbus.rma.addr, nv3->pbus.rma.data, NULL); + else // failsafe code, i don't think you will ever write outside of VRAM? + { + nv3->nvbase.svga.chain4 = true; + nv3->nvbase.svga.packed_chain4 = true; + svga_writel_linear((nv3->pbus.rma.addr - NV3_MMIO_SIZE) & (VRAM_SIZE_4MB - 1), nv3->pbus.rma.data, &nv3->nvbase.svga); + nv3->nvbase.svga.chain4 = false; + nv3->nvbase.svga.packed_chain4 = false; + } + + + break; + } + } + + if (addr & 0x10) + nv3->pbus.rma.addr += 0x04; // Alignment +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c new file mode 100644 index 000000000..825f326f2 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -0,0 +1,31 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PBUS DMA: DMA Engine + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c new file mode 100644 index 000000000..761bacdb3 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -0,0 +1,149 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PEXTDEV - External Devices + * Including straps + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +void nv3_pextdev_init() +{ + nv_log("NV3: Initialising PEXTDEV....\n"); + + // Set the chip straps + // Make these configurable in the future... + + // Current settings + // AGP2X Disabled + // TV Mode NTSC + // Crystal 13.5 Mhz + // Bus width 128-Bit (some gpus were sold as 64bit for cost reduction) + // + + nv_log("NV3: Initialising straps...\n"); + + nv3->pextdev.straps = + (NV3_PSTRAPS_AGP2X_DISABLED << NV3_PSTRAPS_AGP2X) | + (NV3_PSTRAPS_TVMODE_NTSC << NV3_PSTRAPS_TVMODE) | + (NV3_PSTRAPS_CRYSTAL_13500K << NV3_PSTRAPS_CRYSTAL); + + // figure out the bus + if (nv3->nvbase.bus_generation == nv_bus_pci) + nv3->pextdev.straps |= (NV3_PSTRAPS_BUS_TYPE_PCI << NV3_PSTRAPS_BUS_TYPE); + else + nv3->pextdev.straps |= (NV3_PSTRAPS_BUS_TYPE_AGP << NV3_PSTRAPS_BUS_TYPE); + + // now the lower bits + nv3->pextdev.straps |= + (NV3_PSTRAPS_BUS_WIDTH_128BIT << NV3_PSTRAPS_BUS_WIDTH) | + (NV3_PSTRAPS_BIOS_PRESENT << NV3_PSTRAPS_BIOS) | + (NV3_PSTRAPS_BUS_SPEED_66MHZ << NV3_PSTRAPS_BUS_SPEED); + + nv_log("NV3: Straps = 0x%04x\n", nv3->pextdev.straps); + nv_log("NV3: Initialising PEXTDEV: Done\n"); +} + +// +// ****** PEXTDEV register list START ****** +// + +nv_register_t pextdev_registers[] = { + { NV3_PSTRAPS, "Straps - Chip Configuration", NULL, NULL }, + { NV_REG_LIST_END, NULL, NULL, NULL }, // sentinel value +}; + + +// +// ****** Read/Write functions start ****** +// + +uint32_t nv3_pextdev_read(uint32_t address) +{ + nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); + + // todo: friendly logging + + // special consideration for straps + if (address == NV3_PSTRAPS) + { + nv_log("NV3: Straps Read (current value=0x%08x)\n", nv3->pextdev.straps); + } + else + { + nv_log("NV3: PEXTDEV Read from 0x%08x", address); + + } + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + switch (reg->address) + { + case NV3_PSTRAPS: + return nv3->pextdev.straps; + } + } + } + + return 0x0; +} + +void nv3_pextdev_write(uint32_t address, uint32_t value) +{ + nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); + + nv_log("NV3: PEXTDEV Write 0x%08x -> 0x%08x\n", value, address); + + // special consideration for straps + if (address == NV3_PSTRAPS) + { + nv_log("NV3: Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps); + return; + } + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c new file mode 100644 index 000000000..d644185a2 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -0,0 +1,109 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PFB: Framebuffer + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +nv_register_t pfb_registers[] = { + { NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +void nv3_pfb_init() +{ + nv_log("NV3: Initialising PFB..."); + + // initial configuration: + // ram 4mb + // bus width 128bit + // extension ram none (was this ever used?) + // ram banks 4 (based on observation of physical RIVA 128 with 4mb, does 1 bank = 1chip?) + // twiddle off (check this on a real card once it's actually installed) + nv3->pfb.boot = (NV3_PFB_BOOT_RAM_EXTENSION_NONE << (NV3_PFB_BOOT_RAM_EXTENSION) + | (NV3_PFB_BOOT_RAM_DATA_TWIDDLE_OFF << NV3_PFB_BOOT_RAM_DATA_TWIDDLE) + | (NV3_PFB_BOOT_RAM_BANKS_4 << NV3_PFB_BOOT_RAM_BANKS) + | (NV3_PFB_BOOT_RAM_WIDTH_128 << NV3_PFB_BOOT_RAM_WIDTH) + | (NV3_PFB_BOOT_RAM_AMOUNT_4MB << NV3_PFB_BOOT_RAM_AMOUNT) + ); + + nv_log("Done\n"); +} + +uint32_t nv3_pfb_read(uint32_t address) +{ + nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PFB Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + switch (reg->address) + { + case NV3_PFB_BOOT: + return nv3->pfb.boot; + break; + } + } + } + + return 0x0; +} + +void nv3_pfb_write(uint32_t address, uint32_t value) +{ + nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); + + nv_log("NV3: PFB Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + + } + +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c new file mode 100644 index 000000000..8f8abbac4 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -0,0 +1,146 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 pfifo (FIFO for graphics object submission) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... + +// +// ****** pfifo register list START ****** +// + +nv_register_t pfifo_registers[] = { + { NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL}, + { NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +// PFIFO init code +void nv3_pfifo_init() +{ + nv_log("NV3: Initialising PFIFO..."); + + nv_log("Done!\n"); +} + +uint32_t nv3_pfifo_read(uint32_t address) +{ + // before doing anything, check the subsystem enablement state + + if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO) + & NV3_PMC_ENABLE_PFIFO_ENABLED) + { + nv_log("NV3: Repressing PFIFO read. The subsystem is disabled according to pmc_enable, returning 0\n"); + return 0x00; + } + + nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PFIFO Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + // Interrupt state: + // Bit 0 - Cache Error + // Bit 4 - RAMRO Triggered + // Bit 8 - RAMRO Overflow (too many invalid dma objects) + // Bit 12 - DMA Pusher + // Bit 16 - DMA Page Table Entry (pagefault?) + switch (reg->address) + { + case NV3_PFIFO_INTR: + return nv3->pfifo.interrupt_status; + case NV3_PFIFO_INTR_EN: + return nv3->pfifo.interrupt_enable; + } + } + } + return 0x0; +} + +void nv3_pfifo_write(uint32_t address, uint32_t value) +{ + // before doing anything, check the subsystem enablement + + if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO) + & NV3_PMC_ENABLE_PFIFO_ENABLED) + { + nv_log("NV3: Repressing PFIFO write. The subsystem is disabled according to pmc_enable\n"); + return; + } + + nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); + + nv_log("NV3: pfifo Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + // Interrupt state: + // Bit 0 - Cache Error + // Bit 4 - RAMRO Triggered + // Bit 8 - RAMRO Overflow (too many invalid dma objects) + // Bit 12 - DMA Pusher + // Bit 16 - DMA Page Table Entry (pagefault?) + case NV3_PFIFO_INTR: + nv3->pfifo.interrupt_status &= ~value; + nv3_pmc_clear_interrupts(); + break; + case NV3_PFIFO_INTR_EN: + nv3->pbus.interrupt_enable = value & 0x00001111; + break; + } + } + } + +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c new file mode 100644 index 000000000..d37ccdf9f --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -0,0 +1,151 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PGRAPH (Scene Graph for 2D/3D Accelerated Graphics) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... + +// +// ****** PGRAPH register list START ****** +// + +void nv3_pgraph_init() +{ + nv_log("NV3: Initialising PGRAPH..."); + + nv_log("Done!\n"); +} + +nv_register_t pgraph_registers[] = { + { NV3_PGRAPH_INTR_0, "PGRAPH Interrupt Status 0", NULL, NULL }, + { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL }, + { NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL }, + { NV3_PGRAPH_INTR_EN_1, "PGRAPH Interrupt Enable 1", NULL, NULL }, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +uint32_t nv3_pgraph_read(uint32_t address) +{ + // before doing anything, check that this is even enabled.. + + if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH) + & NV3_PMC_ENABLE_PGRAPH_ENABLED) + { + nv_log("NV3: Repressing PGRAPH read. The subsystem is disabled according to pmc_enable, returning 0\n"); + return 0x00; + } + + nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PGRAPH Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + switch (reg->address) + { + //interrupt status and enable regs + case NV3_PGRAPH_INTR_0: + return nv3->pgraph.interrupt_status_0; + case NV3_PGRAPH_INTR_1: + return nv3->pgraph.interrupt_status_1; + case NV3_PGRAPH_INTR_EN_0: + return nv3->pgraph.interrupt_enable_0; + case NV3_PGRAPH_INTR_EN_1: + return nv3->pgraph.interrupt_enable_1; + } + } + + } + + return 0x0; +} + +void nv3_pgraph_write(uint32_t address, uint32_t value) +{ + if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH) + & NV3_PMC_ENABLE_PGRAPH_ENABLED) + { + nv_log("NV3: Repressing PGRAPH write. The subsystem is disabled according to pmc_enable\n"); + return; + } + + nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); + + nv_log("NV3: pgraph Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + //interrupt status and enable regs + case NV3_PGRAPH_INTR_0: + nv3->pgraph.interrupt_status_0 &= ~value; + //we changed interrupt state + nv3_pmc_clear_interrupts(); + break; + case NV3_PGRAPH_INTR_1: + nv3->pgraph.interrupt_status_1 &= ~value; + //we changed interrupt state + nv3_pmc_clear_interrupts(); + break; + // Only bits divisible by 4 matter + // and only bit0-16 is defined in intr_1 + case NV3_PGRAPH_INTR_EN_0: + nv3->pgraph.interrupt_enable_0 = value & 0x11111111; + break; + case NV3_PGRAPH_INTR_EN_1: + nv3->pgraph.interrupt_enable_1 = value & 0x00011111; + break; + } + } + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c new file mode 100644 index 000000000..10717f7bc --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -0,0 +1,236 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PMC - Master control for the chip + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... + +void nv3_pmc_init() +{ + nv_log("NV3: Initialising PMC....\n"); + + nv3->pmc.boot = NV3_BOOT_REG_DEFAULT; + + nv_log("NV3: Initialising PMC: Done\n"); +} + +// +// ****** PMC register list START ****** +// + +nv_register_t pmc_registers[] = { + { NV3_PMC_BOOT, "PMC: Boot Manufacturing Information", NULL, NULL }, + { NV3_PMC_INTERRUPT_STATUS, "PMC: Current Pending Subsystem Interrupts", NULL, NULL}, + { NV3_PMC_INTERRUPT_ENABLE, "PMC: Global Interrupt Enable", NULL, NULL,}, + { NV3_PMC_ENABLE, "PMC: Global Subsystem Enable", NULL, NULL }, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +uint32_t nv3_pmc_clear_interrupts() +{ + nv_log("NV3: Clearing IRQs\n"); + pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); +} + +// Handle hardware interrupts +// We only clear when we need to, in other functions... +uint32_t nv3_pmc_handle_interrupts(bool send_now) +{ + // TODO: + // PGRAPH DMA INTR_EN (there is no DMA engine yet) + // PRM Real-Mode Compatibility Interrupts + + uint32_t new_intr_value; + + // set the new interrupt value + // PAUDIO not used + // IF NV3 REV A EMULATION IS ADDED, ADD THIS COMPONENT! + + // the registers are designed to line up so you can enable specific interrupts + + // Check Mediaport interrupts + if (nv3->pme.interrupt_status & nv3->pme.interrupt_enable) + new_intr_value |= (NV3_PMC_INTERRUPT_PMEDIA_PENDING << NV3_PMC_INTERRUPT_PMEDIA); + + // Check FIFO interrupts + if (nv3->pfifo.interrupt_status & nv3->pfifo.interrupt_enable) + new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO); + + // PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...clean this up once we verify it + if (nv3->pgraph.interrupt_status_0 & (1 << 8)) + new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB); + else if (nv3->pgraph.interrupt_status_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt + new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0); + + // Check second pgraph interrupt register + if (nv3->pgraph.interrupt_status_1 & nv3->pgraph.interrupt_enable_1) + new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH1_PENDING << NV3_PMC_INTERRUPT_PGRAPH1); + + // check video overlay interrupts + if (nv3->pvideo.interrupt_status & nv3->pvideo.interrupt_enable) + new_intr_value |= (NV3_PMC_INTERRUPT_PVIDEO_PENDING << NV3_PMC_INTERRUPT_PVIDEO); + + // check PIT interrupts + if (nv3->ptimer.interrupt_status & nv3->ptimer.interrupt_enable) + new_intr_value |= (NV3_PMC_INTERRUPT_PTIMER_PENDING << NV3_PMC_INTERRUPT_PTIMER); + + // check bus interrupts + if (nv3->pbus.interrupt_status & nv3->pbus.interrupt_enable) + new_intr_value |= (NV3_PMC_INTERRUPT_PBUS_PENDING << NV3_PMC_INTERRUPT_PBUS); + + // check SW interrupts + if (nv3->pmc.interrupt_status & (1 << NV3_PMC_INTERRUPT_SOFTWARE)) + new_intr_value |= (NV3_PMC_INTERRUPT_SOFTWARE_PENDING << NV3_PMC_INTERRUPT_SOFTWARE); + + nv3->pmc.interrupt_status = new_intr_value; + + // ***TODO: DOes INTR still change if INTR_EN=0???*** + // If interrupts are disabled don't bother + + if (!nv3->pmc.interrupt_enable) + nv3_pmc_clear_interrupts(); + + // if we actually need to send the interrupt (i.e. this is a write) send it now + if (send_now) + { + if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF)) + { + if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE) + { + nv_log("NV3: Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); + pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); + } + else + nv_log("NV3: NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); + } + else + { + if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_SOFTWARE) + { + nv_log("NV3: Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); + pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); + } + else + nv_log("NV3: NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); + } + } + + return nv3->pmc.interrupt_status; +} + + + +// +// ****** Read/Write functions start ****** +// + +uint32_t nv3_pmc_read(uint32_t address) +{ + nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); + + // todo: friendly logging + nv_log("NV3: PMC Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + switch (reg->address) + { + case NV3_PMC_BOOT: + return nv3->pmc.boot; + case NV3_PMC_INTERRUPT_STATUS: + nv3_pmc_clear_interrupts(); + + return nv3_pmc_handle_interrupts(false); + case NV3_PMC_INTERRUPT_ENABLE: + //TODO: ACTUALLY CHANGE THE INTERRUPT STATE + return nv3->pmc.interrupt_enable; + case NV3_PMC_ENABLE: + return nv3->pmc.enable; + + } + } + } + + return 0x0; +} + +void nv3_pmc_write(uint32_t address, uint32_t value) +{ + nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); + + nv_log("NV3: PMC Write 0x%08x -> 0x%08x", value, address); + + // if the register actually exists... + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // ... call its on-write function + if (reg->on_write) + reg->on_write(value); + else + { + // if it doesn't have one fallback to a switch statement + switch (reg->address) + { + case NV3_PMC_INTERRUPT_STATUS: + // this + if (!(nv3->pmc.interrupt_status & (NV3_PMC_INTERRUPT_SOFTWARE - 1))) + { + nv_log("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger " + " an interrupt on, rather than writing to NV3_PMC_INTERRUPT_STATUS (Or this is a bug)...NV3_PMC_INTERRUPT_STATUS=0x%08x)\n", nv3->pmc.interrupt_enable); + return; + } + + nv3_pmc_handle_interrupts(true); + nv3->pmc.interrupt_status = value; + break; + case NV3_PMC_INTERRUPT_ENABLE: + nv3->pmc.interrupt_enable = value; + break; + case NV3_PMC_ENABLE: + nv3->pmc.enable = value; + break; + } + } + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c new file mode 100644 index 000000000..9683ff5ab --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -0,0 +1,123 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 pme: Nvidia Mediaport - External MPEG Decode Interface + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +nv_register_t pme_registers[] = { + { NV3_PME_INTR, "PME - Interrupt Status", NULL, NULL}, + { NV3_PME_INTR_EN, "PME - Interrupt Enable", NULL, NULL,}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +void nv3_pme_init() +{ + nv_log("NV3: Initialising PME..."); + + nv_log("Done\n"); +} + +uint32_t nv3_pme_read(uint32_t address) +{ + nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PME Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + // Interrupt state: + // Bit 0 - Image Notifier + // Bit 4 - Vertical Blank Interfal Notifier + // Bit 8 - Video Notifier + // Bit 12 - Audio Notifier + // Bit 16 - VMI Notifer + switch (reg->address) + { + case NV3_PME_INTR: + return nv3->pme.interrupt_status; + case NV3_PME_INTR_EN: + return nv3->pme.interrupt_enable; + } + } + } + + return 0x0; +} + +void nv3_pme_write(uint32_t address, uint32_t value) +{ + nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); + + nv_log("NV3: PME Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + // Interrupt state: + // Bit 0 - Image Notifier + // Bit 4 - Vertical Blank Interfal Notifier + // Bit 8 - Video Notifier + // Bit 12 - Audio Notifier + // Bit 16 - VMI Notifer + + case NV3_PME_INTR: + nv3->pme.interrupt_status &= ~value; + nv3_pmc_clear_interrupts(); + break; + case NV3_PME_INTR_EN: + nv3->pme.interrupt_enable = value & 0x00001111; + break; + } + } + + } + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c new file mode 100644 index 000000000..a2a39b6cb --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -0,0 +1,307 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 bringup and device emulation. + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +// nv3_pramdac.c: NV3 RAMDAC +// Todo: Allow overridability using 68050C register... + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +void nv3_pramdac_init() +{ + nv_log("NV3: Initialising PRAMDAC\n"); + + // defaults, these come from vbios in reality + // driver defaults are nonsensical(?), or the algorithm is wrong + // munged this to 100mhz for now + nv3->pramdac.memory_clock_m = nv3->pramdac.pixel_clock_m = 0x07; + nv3->pramdac.memory_clock_n = nv3->pramdac.pixel_clock_n = 0xc8; + nv3->pramdac.memory_clock_p = nv3->pramdac.pixel_clock_p = 0x0c; + + nv3_pramdac_set_pixel_clock(); + nv3_pramdac_set_vram_clock(); + + nv_log("NV3: Initialising PRAMDAC: Done\n"); +} + +uint32_t nv3_pramdac_get_vram_clock_register() +{ + // pack into 19 bits + // M divisor [7-0] + // N divisor [16-8] + // P divisor [18-16] + return (nv3->pramdac.memory_clock_m << 16) & 0xFF; + + (nv3->pramdac.memory_clock_n << 8) & 0xFF; + + (nv3->pramdac.memory_clock_p) & 0x07; // 0-3 +} + +uint32_t nv3_pramdac_get_pixel_clock_register() +{ + return (nv3->pramdac.pixel_clock_m << 16) & 0xFF; + + (nv3->pramdac.pixel_clock_n << 8) & 0xFF; + + (nv3->pramdac.pixel_clock_p) & 0x07; // 0-3 +} + +void nv3_pramdac_set_vram_clock_register(uint32_t value) +{ + nv3->pramdac.memory_clock_m = value & 0xFF; + nv3->pramdac.memory_clock_n = (value >> 8) & 0xFF; + nv3->pramdac.memory_clock_p = (value >> 16) & 0x07; + + nv3_pramdac_set_vram_clock(); +} + +void nv3_pramdac_set_pixel_clock_register(uint32_t value) +{ + nv3->pramdac.pixel_clock_m = value & 0xFF; + nv3->pramdac.pixel_clock_n = (value >> 8) & 0xFF; + nv3->pramdac.pixel_clock_p = (value >> 16) & 0x07; + + nv3_pramdac_set_pixel_clock(); +} + +void nv3_pramdac_set_vram_clock() +{ + // from driver and vbios source + float frequency = 13500000.0f; + + // prevent division by 0 + if (nv3->pramdac.memory_clock_m == 0) + nv3->pramdac.memory_clock_m == 1; + else + frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); + + nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f); +} + +void nv3_pramdac_set_pixel_clock() +{ + // frequency divider algorithm from old varcem/86box/pcbox riva driver, + // verified by reversing NT drivers v1.50e CalcMNP [symbols] function + + // todo: actually implement it + + // missing section + // not really needed. + // if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500) + // { + // freq = 13500000.0f; + // } + // else + // + // { + // freq = 14318000.0f; + // } + + float frequency = 13500000.0f; + + // prevent division by 0 + if (nv3->pramdac.pixel_clock_m == 0) + nv3->pramdac.pixel_clock_m == 1; + else + frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p); + + nv3->nvbase.svga.clock = cpuclock / frequency; + + nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f); +} + +// +// ****** PRAMDAC register list START ****** +// + +// NULL means handle in read functions +nv_register_t pramdac_registers[] = +{ + { NV3_PRAMDAC_CLOCK_PIXEL, "PRAMDAC - NV3 GPU Core - Pixel clock", nv3_pramdac_get_pixel_clock_register, nv3_pramdac_set_pixel_clock_register }, + { NV3_PRAMDAC_CLOCK_MEMORY, "PRAMDAC - NV3 GPU Core - Memory clock", nv3_pramdac_get_vram_clock_register, nv3_pramdac_set_vram_clock_register }, + { NV3_PRAMDAC_COEFF_SELECT, "PRAMDAC - PLL Clock Coefficient Select", NULL, NULL}, + { NV3_PRAMDAC_GENERAL_CONTROL, "PRAMDAC - General Control", NULL, NULL }, + { NV3_PRAMDAC_VSERR_WIDTH, "PRAMDAC - Vertical Sync Error Width", NULL, NULL}, + { NV3_PRAMDAC_VEQU_END, "PRAMDAC - VEqu End", NULL, NULL}, + { NV3_PRAMDAC_VBBLANK_END, "PRAMDAC - VBBlank End", NULL, NULL}, + { NV3_PRAMDAC_VBLANK_END, "PRAMDAC - Vertical Blanking Interval End", NULL, NULL}, + { NV3_PRAMDAC_VBLANK_START, "PRAMDAC - Vertical Blanking Interval Start", NULL, NULL}, + { NV3_PRAMDAC_VEQU_START, "PRAMDAC - VEqu Start", NULL, NULL}, + { NV3_PRAMDAC_VTOTAL, "PRAMDAC - Total Vertical Lines", NULL, NULL}, + { NV3_PRAMDAC_HSYNC_WIDTH, "PRAMDAC - Horizontal Sync Pulse Width", NULL, NULL}, + { NV3_PRAMDAC_HBURST_START, "PRAMDAC - Horizontal Burst Signal Start", NULL, NULL}, + { NV3_PRAMDAC_HBURST_END, "PRAMDAC - Horizontal Burst Signal Start", NULL, NULL}, + { NV3_PRAMDAC_HTOTAL, "PRAMDAC - Total Horizontal Lines", NULL, NULL}, + { NV3_PRAMDAC_HEQU_WIDTH, "PRAMDAC - HEqu End", NULL, NULL}, + { NV3_PRAMDAC_HSERR_WIDTH, "PRAMDAC - Horizontal Sync Error", NULL, NULL}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +// +// ****** Read/Write functions start ****** +// + +uint32_t nv3_pramdac_read(uint32_t address) +{ + nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PRAMDAC Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + //s hould be pretty easy to understand + switch (reg->address) + { + case NV3_PRAMDAC_COEFF_SELECT: + return nv3->pramdac.coeff_select; + case NV3_PRAMDAC_GENERAL_CONTROL: + return nv3->pramdac.general_control; + case NV3_PRAMDAC_VSERR_WIDTH: + return nv3->pramdac.vserr_width; + case NV3_PRAMDAC_VBBLANK_END: + return nv3->pramdac.vbblank_end; + case NV3_PRAMDAC_VBLANK_END: + return nv3->pramdac.vblank_end; + case NV3_PRAMDAC_VBLANK_START: + return nv3->pramdac.vblank_start; + case NV3_PRAMDAC_VEQU_START: + return nv3->pramdac.vequ_start; + case NV3_PRAMDAC_VTOTAL: + return nv3->pramdac.vtotal; + case NV3_PRAMDAC_HSYNC_WIDTH: + return nv3->pramdac.hsync_width; + case NV3_PRAMDAC_HBURST_START: + return nv3->pramdac.hburst_start; + case NV3_PRAMDAC_HBURST_END: + return nv3->pramdac.hburst_end; + case NV3_PRAMDAC_HBLANK_START: + return nv3->pramdac.hblank_start; + case NV3_PRAMDAC_HBLANK_END: + return nv3->pramdac.hblank_end; + case NV3_PRAMDAC_HTOTAL: + return nv3->pramdac.htotal; + case NV3_PRAMDAC_HEQU_WIDTH: + return nv3->pramdac.hequ_width; + case NV3_PRAMDAC_HSERR_WIDTH: + return nv3->pramdac.hserr_width; + } + } + } + + return 0x0; +} + +void nv3_pramdac_write(uint32_t address, uint32_t value) +{ + nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); + + nv_log("NV3: PRAMDAC Write 0x%08x -> 0x%08x", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + //s hould be pretty easy to understand + // we also update the SVGA state here + switch (reg->address) + { + case NV3_PRAMDAC_COEFF_SELECT: + nv3->pramdac.coeff_select = value; + break; + case NV3_PRAMDAC_GENERAL_CONTROL: + nv3->pramdac.general_control = value; + break; + case NV3_PRAMDAC_VSERR_WIDTH: + //vslines? + nv3->pramdac.vserr_width = value; + break; + case NV3_PRAMDAC_VBBLANK_END: + nv3->pramdac.vbblank_end = value; + break; + case NV3_PRAMDAC_VBLANK_END: + nv3->pramdac.vblank_end = value; + break; + case NV3_PRAMDAC_VBLANK_START: + nv3->nvbase.svga.vblankstart = value; + nv3->pramdac.vblank_start = value; + break; + case NV3_PRAMDAC_VEQU_START: + nv3->pramdac.vequ_start = value; + break; + case NV3_PRAMDAC_VTOTAL: + nv3->pramdac.vtotal = value; + nv3->nvbase.svga.vtotal = value; + break; + case NV3_PRAMDAC_HSYNC_WIDTH: + nv3->pramdac.hsync_width = value; + break; + case NV3_PRAMDAC_HBURST_START: + nv3->pramdac.hburst_start = value; + break; + case NV3_PRAMDAC_HBURST_END: + nv3->pramdac.hburst_end = value; + break; + case NV3_PRAMDAC_HBLANK_START: + nv3->nvbase.svga.hblankstart = value; + nv3->pramdac.hblank_start = value; + break; + case NV3_PRAMDAC_HBLANK_END: + nv3->nvbase.svga.hblank_end_val = value; + nv3->pramdac.hblank_end = value; + break; + case NV3_PRAMDAC_HTOTAL: + nv3->pramdac.htotal = value; + nv3->nvbase.svga.htotal = value; + break; + case NV3_PRAMDAC_HEQU_WIDTH: + nv3->pramdac.hequ_width = value; + break; + case NV3_PRAMDAC_HSERR_WIDTH: + nv3->pramdac.hserr_width = value; + break; + } + } + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c new file mode 100644 index 000000000..cef9597c9 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -0,0 +1,149 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PRAMIN - Basically, this is how we know what to render. + * Has a giant hashtable of all the submitted DMA objects using a pseudo-C++ class system + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// i believe the main loop is to walk the hashtable in RAMIN (last 0.5 MB of VRAM), +// find the objects that were submitted from DMA +// (going from software -> nvidia d3d / ogl implementation -> resource manager client -> nvapi -> nvrm -> GPU PFIFO -> GPU PBUS -> GPU PFB RAMIN -> PGRAPH) +// and then rendering each of those using PGRAPH + +// Notes for all of these functions: +// Structures in RAMIN are stored from the bottom of vram up in reverse order +// this can be explained without bitwise math like so: +// real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) +// reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) + +// Read 8-bit ramin +uint8_t nv3_ramin_read8(uint32_t addr, void* priv) +{ + addr &= (VRAM_SIZE_4MB - 1); + uint32_t raw_addr = addr; // saved after and + + addr ^= (VRAM_SIZE_4MB - 0x10); + + uint8_t val = nv3->nvbase.svga.vram[addr]; + + nv_log("NV3: Read byte from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + + return val; +} + +// Read 16-bit ramin +uint16_t nv3_ramin_read16(uint32_t addr, void* priv) +{ + addr &= (VRAM_SIZE_4MB - 1); + + // why does this not work in one line + svga_t* svga = &nv3->nvbase.svga; + uint16_t* vram_16bit = (uint16_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (VRAM_SIZE_4MB - 0x10); + addr >>= 1; // what + + uint16_t val = vram_16bit[addr]; // what + + nv_log("NV3: Read word from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + + return val; +} + +// Read 32-bit ramin +uint32_t nv3_ramin_read32(uint32_t addr, void* priv) +{ + addr &= (VRAM_SIZE_4MB - 1); + + // why does this not work in one line + svga_t* svga = &nv3->nvbase.svga; + uint32_t* vram_32bit = (uint32_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (VRAM_SIZE_4MB - 0x10); + addr >>= 2; // what + + uint32_t val = vram_32bit[addr]; + + nv_log("NV3: Read dword from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + + return val; +} + +// Write 8-bit ramin +void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) +{ + addr &= (VRAM_SIZE_4MB - 1); + uint32_t raw_addr = addr; // saved after and + + // Structures in RAMIN are stored from the bottom of vram up in reverse order + // this can be explained without bitwise math like so: + // real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) + // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) + addr ^= (VRAM_SIZE_4MB - 0x10); + + nv3->nvbase.svga.vram[addr] = val; + + nv_log("NV3: Write byte to ramin addr=0x%08x val=0x%08x (raw address=0x%08x)", addr, val, raw_addr); +} + +// Write 16-bit ramin +void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) +{ + addr &= (VRAM_SIZE_4MB - 1); + + // why does this not work in one line + svga_t* svga = &nv3->nvbase.svga; + uint16_t* vram_16bit = (uint16_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (VRAM_SIZE_4MB - 0x10); + addr >>= 1; // what + + vram_16bit[addr] = val; + + nv_log("NV3: Write word to ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); +} + +// Write 32-bit ramin +void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) +{ + addr &= (VRAM_SIZE_4MB - 1); + + // why does this not work in one line + svga_t* svga = &nv3->nvbase.svga; + uint32_t* vram_32bit = (uint32_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (VRAM_SIZE_4MB - 0x10); + addr >>= 2; // what + + vram_32bit[addr] = val; + + nv_log("NV3: Write dword to ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); +} diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c new file mode 100644 index 000000000..9a397c8d7 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -0,0 +1,31 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PFIFO RAMFC area: Stores context unused DMA channels + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c new file mode 100644 index 000000000..baadb9666 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -0,0 +1,31 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PFIFO hashtable (Quickly access submitted DMA objects) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c new file mode 100644 index 000000000..46c95deac --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -0,0 +1,31 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PFIFO ram runout area (you fucked up) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c new file mode 100644 index 000000000..9e15a1035 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -0,0 +1,120 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PTIMER - PIT emulation + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + + +nv_register_t ptimer_registers[] = { + { NV3_PTIMER_INTR, "PTIMER - Interrupt Status", NULL, NULL}, + { NV3_PTIMER_INTR_EN, "PTIMER - Interrupt Enable", NULL, NULL,}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +// ptimer init code +void nv3_ptimer_init() +{ + nv_log("NV3: Initialising PTIMER..."); + + nv_log("Done!\n"); +} + +uint32_t nv3_ptimer_read(uint32_t address) +{ + // before doing anything, check the subsystem enablement + + nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PTIMER Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + // Interrupt state: + // Bit 0: Alarm + + switch (reg->address) + { + case NV3_PTIMER_INTR: + return nv3->ptimer.interrupt_status; + case NV3_PTIMER_INTR_EN: + return nv3->ptimer.interrupt_enable; + } + } + } + + return 0x00; +} + +void nv3_ptimer_write(uint32_t address, uint32_t value) +{ + // before doing anything, check the subsystem enablement + nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); + + nv_log("NV3: PTIMER Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + // Interrupt state: + // Bit 0 - Alarm + + case NV3_PTIMER_INTR: + nv3->ptimer.interrupt_status &= ~value; + nv3_pmc_clear_interrupts(); + break; + case NV3_PTIMER_INTR_EN: + nv3->ptimer.interrupt_enable = value & 0x00000001; + break; + } + } + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c new file mode 100644 index 000000000..1aede7b0c --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -0,0 +1,121 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 PVIDEO - Video Overlay + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + + +nv_register_t pvideo_registers[] = { + { NV3_PVIDEO_INTR, "PVIDEO - Interrupt Status", NULL, NULL}, + { NV3_PVIDEO_INTR_EN, "PVIDEO - Interrupt Enable", NULL, NULL,}, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +// ptimer init code +void nv3_pvideo_init() +{ + nv_log("Initialising PVIDEO..."); + + nv_log("Done!\n"); +} + +uint32_t nv3_pvideo_read(uint32_t address) +{ + // before doing anything, check the subsystem enablement + + nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); + + // todo: friendly logging + + nv_log("NV3: PVIDEO Read from 0x%08x", address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_read) + return reg->on_read(); + else + { + // Interrupt state: + // Bit 0 - Notifier + + switch (reg->address) + { + case NV3_PVIDEO_INTR: + return nv3->pvideo.interrupt_status; + case NV3_PVIDEO_INTR_EN: + return nv3->pvideo.interrupt_enable; + } + } + } + + return 0x0; +} + +void nv3_pvideo_write(uint32_t address, uint32_t value) +{ + // before doing anything, check the subsystem enablement + nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); + + nv_log("NV3: PVIDEO Write 0x%08x -> 0x%08x\n", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + // Interrupt state: + // Bit 0 - Notifier + + case NV3_PVIDEO_INTR: + nv3->pvideo.interrupt_status &= ~value; + nv3_pmc_clear_interrupts(); + break; + case NV3_PVIDEO_INTR_EN: + nv3->pvideo.interrupt_enable = value & 0x00000001; + break; + } + } + } + +} \ No newline at end of file diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c new file mode 100644 index 000000000..b67c65dc2 --- /dev/null +++ b/src/video/nv/nv_base.c @@ -0,0 +1,47 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Base file for emulation of NVidia video cards. + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ + +// Common NV1/3/4... init +#define HAVE_STDARG_H // wtf is this crap +#include +#include +#include +#include <86box/86box.h> +#include <86box/nv/vid_nv.h> + + +// Common logging +#ifdef ENABLE_NV_LOG +int nv_do_log = ENABLE_NV_LOG; + +void nv_log(const char *fmt, ...) +{ + va_list ap; + + if (nv_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +void +nv_log(const char *fmt, ...) +{ + +} +#endif \ No newline at end of file diff --git a/src/video/vid_table.c b/src/video/vid_table.c index 859712357..d10727d04 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -249,6 +249,9 @@ video_cards[] = { { &compaq_voodoo_3_3500_agp_device }, { &voodoo_3_3500_se_agp_device }, { &voodoo_3_3500_si_agp_device }, + { &nv3_device_agp }, + { &nv3_device_pci }, + { NULL } // clang-format on }; From baeca30c6d7c199978175b27ef735d973e02f88b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 27 Nov 2024 17:41:54 +0000 Subject: [PATCH 002/274] Fix PRAMDAC. Now it shows as working in Windows 2000? --- doc/nv3 driver init status.txt | 105 ++++++++++++++++++++++ src/video/nv/nv3/subsystems/nv3_pramdac.c | 12 +-- 2 files changed, 111 insertions(+), 6 deletions(-) create mode 100644 doc/nv3 driver init status.txt diff --git a/doc/nv3 driver init status.txt b/doc/nv3 driver init status.txt new file mode 100644 index 000000000..b6f470f92 --- /dev/null +++ b/doc/nv3 driver init status.txt @@ -0,0 +1,105 @@ +Driver version: Windows 2000 Version 3.37 (23 March 1999) - SDK: Windows 2000 build 1996.1 +Features: + +Resource Manager Yes +DirectDraw Yes +OpenGL Yes +Direct3D No + + +get started: +MUST USE X86 WINDBG +Does older windbg support coff??? + +sxe ld nv3_mini.sys +bp nv3_mini + 0x409ac - 0x10000 (nv3_mini+0x309ac) + +offset purpose +30a1a RmInitRm call + +6be7 initClientInfo call +6878 initClientInfo +6bec Check for initClientInfo success +6bf4 initGrPatchPool call +6bf9 Check for initGrPatchPool success +6c01 initDmaListElementPool call +6c06 Check for initDmaListElementPool +6c1c initDisplayInfo call + +6c26 rmInitRm End + Success: eax=FFFFFFFFh / -1 +6c26 Fail eax=0 + +30c8b NvFindAdapter +30cb6 NvFindAdapter -> NVIsPresent call +1010 NVIsPresent function +102f NVIsPresent VideoPortGetAccessRanges call +103b NVIsPresent VideoPortGetAccessRanges call success check (only possible way to fail) +127c NVIsPresent end +30cbb NvFindAdapter -> NVIsPresent success check + Success: al=1 + Failure: al=0 +30cca NVIsPresent NVMapMemoryRanges call +e9e NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #1 [PCI Space] +ea4 NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #1 success check [PCI Space] +ebd NVIsPresent NVMapMemoryRanges VideoPortFreeDeviceBase [conditional] +ec3 NVIsPresent NVMapMemoryRanges VideoPortFreeDeviceBase [conditional] success check +ed6 NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #2 [MMIO] +edc NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #2 success check [MMIO] +f0c NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #3 [LFB/RAMIN?] +f12 NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #3 success check [LFB/RAMIN?] + +30ccf NvFindAdapter NVMapMemoryRanges success check + Success: eax=0 + Failure: eax=87 +30cf1 NvFindAdapter RmInitNvMapping call +6ce6 NvFindAdapter RmInitNvMapping +30cf6 NVIsPresent RmInitNvMapping success check + Success: eax!=0 (in practice 0xFFFFFFFF/-1) + Failure: eax=0 +30d5c NvFindAdapter +30d64 NvFindAdapter RmPostNvDevice call +6d88 RmPostNvDevice function +6d91 NvFindAdapter DevinitInitializeDevice call +6d96 NvFindAdapter DevinitInitializeDevice success check + Success: eax=0 (?) + Failure: eax=1 +e546 DevinitInitializeDevice function + [very complicated] + [several register reads] +e61d DevinitPrepDeviceForInit call +e641 DevinitPrepDeviceForInit function +e627 InitNV call +e67a InitNV function + +30d64 NVIsPresent RmPostNvDevice success check + Success: eax=0 (?) + Failure: eax=1 +30d78 NVIsPresent NVGetNVInfo call +30d7d NVIsPresent NVGetNVInfo success check + +3e9a NvFindAdapter end + Success: eax=0 + Fail eax=55 (RmInitNvMapping or NVIsPresent failed) + Fail eax=87 (NVMapMemoryRanges or NVMapFrameBuffer failed) + +30ea3 NVInitialize +30f02 NVStartIO +2aa6 NVInterrupt +30a2d NVGetChildDescriptor +30a9c NVGetPowerState +30b20 NVSetPowerState + + +Driver Init Status: +DriverEntry Success +rmInitRm -> initClientInfo Success +rmInitRm -> initGrPatchPool Success +rmInitRm -> initDmaListElementPool Success +rmInitRm -> initDisplayInfo Success +rmInitRm overall Success +NvFindAdapter Failing (EAX=87) +NvFindAdapter -> NvIsPresent Success 16:19 24/11/2024 +NvFindAdapter -> NvMapMemoryRanges Success 19:15 26/11/2024 +NvFindAdapter -> RmInitNvMapping Success 19:18 26/11/2024 +NvFindAdapter -> RmPostNvDevice diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index a2a39b6cb..1716fd3ef 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -54,16 +54,16 @@ uint32_t nv3_pramdac_get_vram_clock_register() // M divisor [7-0] // N divisor [16-8] // P divisor [18-16] - return (nv3->pramdac.memory_clock_m << 16) & 0xFF; - + (nv3->pramdac.memory_clock_n << 8) & 0xFF; - + (nv3->pramdac.memory_clock_p) & 0x07; // 0-3 + return (nv3->pramdac.memory_clock_m); + + (nv3->pramdac.memory_clock_n << 8); + + (nv3->pramdac.memory_clock_p << 16); // 0-3 } uint32_t nv3_pramdac_get_pixel_clock_register() { - return (nv3->pramdac.pixel_clock_m << 16) & 0xFF; - + (nv3->pramdac.pixel_clock_n << 8) & 0xFF; - + (nv3->pramdac.pixel_clock_p) & 0x07; // 0-3 + return (nv3->pramdac.pixel_clock_m); + + (nv3->pramdac.pixel_clock_n << 8); + + (nv3->pramdac.pixel_clock_p << 16); // 0-3 } void nv3_pramdac_set_vram_clock_register(uint32_t value) From 1c1471867761210c8cf63cc589fda90bfa8c7c0d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 27 Nov 2024 18:15:54 +0000 Subject: [PATCH 003/274] anti-stupidity --- src/video/nv/nv3/subsystems/nv3_pramdac.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 1716fd3ef..39b5b918f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -54,15 +54,15 @@ uint32_t nv3_pramdac_get_vram_clock_register() // M divisor [7-0] // N divisor [16-8] // P divisor [18-16] - return (nv3->pramdac.memory_clock_m); - + (nv3->pramdac.memory_clock_n << 8); + return (nv3->pramdac.memory_clock_m) + + (nv3->pramdac.memory_clock_n << 8) + (nv3->pramdac.memory_clock_p << 16); // 0-3 } uint32_t nv3_pramdac_get_pixel_clock_register() { - return (nv3->pramdac.pixel_clock_m); - + (nv3->pramdac.pixel_clock_n << 8); + return (nv3->pramdac.pixel_clock_m) + + (nv3->pramdac.pixel_clock_n << 8) + (nv3->pramdac.pixel_clock_p << 16); // 0-3 } From b816a7d3796d57de961ac21241df2853a1835b8f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 1 Dec 2024 20:56:42 +0000 Subject: [PATCH 004/274] Initial VBLANK draft. Still fucked up --- doc/NV_PFB_CONFIG_0.txt | 29 ++++++++++ doc/nv3 driver init status.txt | 6 ++- src/include/86box/nv/vid_nv.h | 3 ++ src/include/86box/nv/vid_nv3.h | 67 +++++++++++++++++------- src/video/nv/nv3/nv3_core_arbiter.c | 2 + src/video/nv/nv3/subsystems/nv3_pfb.c | 48 +++++++++++++++-- src/video/nv/nv3/subsystems/nv3_pgraph.c | 33 +++++++++--- src/video/nv/nv3/subsystems/nv3_pmc.c | 20 +++++-- 8 files changed, 171 insertions(+), 37 deletions(-) create mode 100644 doc/NV_PFB_CONFIG_0.txt diff --git a/doc/NV_PFB_CONFIG_0.txt b/doc/NV_PFB_CONFIG_0.txt new file mode 100644 index 000000000..dee3b646c --- /dev/null +++ b/doc/NV_PFB_CONFIG_0.txt @@ -0,0 +1,29 @@ +NV_PFB_CONFIG_0 + +Observed Valus: +Drivers 0x1000 +BIOS 0x1114 + +Bits +5:0 Resolution +9:8 Pixel depth +12:12 Tiling +13:13 Tiling Debug +14:14 Tiling Debug Tile Size +17:15 "Tetris" tiling +19:18 "Tetris" tiling shift +22:20 Bank Swap +23 Unused + +NV_PFB_CONFIG_1 +2:0 CAS Latency +3:3 NEC Mode (PC-98?) +7:4 RAS Default / 9 Cycles +10:8 RAS PCHG +14:12 RAS Low +18:16 MRS to RAS +22:20 Write to Read +26:24 RAS to CAS +30:28 Read to Write +31:31 Read to PCFg + diff --git a/doc/nv3 driver init status.txt b/doc/nv3 driver init status.txt index b6f470f92..6ac794588 100644 --- a/doc/nv3 driver init status.txt +++ b/doc/nv3 driver init status.txt @@ -98,8 +98,10 @@ rmInitRm -> initGrPatchPool Success rmInitRm -> initDmaListElementPool Success rmInitRm -> initDisplayInfo Success rmInitRm overall Success -NvFindAdapter Failing (EAX=87) +NvFindAdapter Success 17:32 27/11/2024 NvFindAdapter -> NvIsPresent Success 16:19 24/11/2024 NvFindAdapter -> NvMapMemoryRanges Success 19:15 26/11/2024 NvFindAdapter -> RmInitNvMapping Success 19:18 26/11/2024 -NvFindAdapter -> RmPostNvDevice +NvFindAdapter -> RmPostNvDevice Success 17:32 27/11/2024 +NvFindAdapter -> NVGetNVInfo Success 17:32 27/11/2024 +NvFindAdapter -> NVMapFrameBuffer Success 17:32 27/11/2024 diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index ca0922a44..cabd9f46b 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -158,6 +158,8 @@ typedef struct nv3_straps_s typedef struct nv3_pfb_s { uint32_t boot; + uint32_t config_0; + uint32_t config_1; } nv3_pfb_t; #define NV3_RMA_NUM_REGS 4 @@ -460,6 +462,7 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now); // NV3 PGRAPH void nv3_pgraph_init(); +void nv3_pgraph_vblank_start(svga_t* svga); // NV3 PFIFO void nv3_pfifo_init(); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index a9a4884d9..bd8d373b7 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -34,6 +34,8 @@ extern nv3_t* nv3; #define NV3_VBIOS_DIAMOND_V330_V162 "roms/video/nvidia/nv3/diamond_v330_rev-e.vbi" // Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO #define NV3_VBIOS_ASUS_V3000_V151 "roms/video/nvidia/nv3/riva128_asus.vbi" // ASUS AGP/3DP-V3000 BIOS 1.51B #define NV3_VBIOS_STB_V128_V182 "roms/video/nvidia/nv3/riva128_stb.vbi" // STB Velocity 128 (RIVA 128) Ver.1.82 +#define NV3T_VBIOS_REFERENCE_CEK_V171 "roms/video/nvidia/nv3/BIOS_49_Riva 128" // Reference BIOS: RIVA 128 ZX BIOS - V1.71B-N (C) 1996-98 NVidia Corporation +#define NV3T_VBIOS_DIAMOND_V330_V182B "roms/video/nvidia/nv3/nv3t182b.rom" // Diamond Multimedia Viper V330 8M BIOS - Version 1.82B // Temporary, will be loaded from settings #define VRAM_SIZE_2MB 0x200000 // 2MB @@ -113,6 +115,7 @@ extern nv3_t* nv3; #define NV3_PMC_START 0x0 // Chip Master Control Subsystem #define NV3_PMC_BOOT 0x0 // Boot Configuration + #define NV3_PMC_INTERRUPT_STATUS 0x100 // Interrupt Control #define NV3_PMC_INTERRUPT_PAUDIO 0 // Unused, NV3A only #define NV3_PMC_INTERRUPT_PAUDIO_PENDING 0x1 // Unused, NV3A only @@ -138,6 +141,23 @@ extern nv3_t* nv3; #define NV3_PMC_INTERRUPT_ENABLE_HARDWARE 0x1 // Determines if hardware interrupts are enabled #define NV3_PMC_INTERRUPT_ENABLE_SOFTWARE 0x2 // Determinse if software interrupts were enabled #define NV3_PMC_ENABLE 0x200 // Determines which gpu subsystems were enabled +#define NV3_PMC_ENABLE_PAUDIO 0 // UNUSED - PAudio removed in NV3 Stepping B0 +#define NV3_PMC_ENABLE_PAUDIO_ENABLED 0x1 // UNUSED - PAudio removed in NV3 Stepping B0 +#define NV3_PMC_ENABLE_PMEDIA 4 +#define NV3_PMC_ENABLE_PMEDIA_ENABLED 0x1 +#define NV3_PMC_ENABLE_PFIFO 8 +#define NV3_PMC_ENABLE_PFIFO_ENABLED 0x1 +#define NV3_PMC_ENABLE_PGRAPH 12 // Determines if PGRAPH is enabled. +#define NV3_PMC_ENABLE_PGRAPH_ENABLED 0x1 +#define NV3_PMC_ENABLE_PPMI 16 +#define NV3_PMC_ENABLE_PPMI_ENABLED 0x1 +#define NV3_PMC_ENABLE_PFB 20 +#define NV3_PMC_ENABLE_PFB_ENABLED 0x1 +#define NV3_PMC_ENABLE_PCRTC 24 +#define NV3_PMC_ENABLE_PCRTC_ENABLED 0x1 +#define NV3_PMC_ENABLE_PVIDEO 28 +#define NV3_PMC_ENABLE_PVIDEO_ENABLED 0x1 + #define NV3_PMC_END 0xfff // overlaps with CIO #define NV3_CIO_START 0x3b0 // Legacy SVGA Emulation Subsystem @@ -189,6 +209,32 @@ extern nv3_t* nv3; #define NV3_PFB_BOOT_RAM_EXTENSION 5 #define NV3_PFB_BOOT_RAM_EXTENSION_NONE 0x0 #define NV3_PFB_BOOT_RAM_EXTENSION_8MB 0x1 +#define NV3_PFB_CONFIG_0 0x100200 // Framebuffer interface config register 0 +#define NV3_PFB_CONFIG_0_RESOLUTION 0 +// 1=40 horiz. resolution +// i assume it can be divided by some kind of divisor to produce the vertical resolution (e.g. 3/2 or multiply by 2/3) to get the final +// horiz is 32*value +// theoretically it should support resolutions from 40-2560 horiz + +// WHAT ARE THE TIMINGS: ARE THEY IN THE VBIOS? +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_320 0xA +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_400 0xD +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_480 0xF +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_512 0x10 +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_640 0x14 +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_800 0x19 +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_960 0x1E +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1024 0x20 +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1152 0x24 +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1280 0x28 +#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1600 0x32 + +#define NV3_PFB_CONFIG_0_PIXEL_DEPTH 8 +#define NV3_PFB_CONFIG_0_DEPTH_8BPP 0x1 +#define NV3_PFB_CONFIG_0_DEPTH_16BPP 0x2 +#define NV3_PFB_CONFIG_0_DEPTH_32BPP 0x3 + +#define NV3_PFB_CONFIG_1 0x100204 // Framebuffer interface config register 1 #define NV3_PFB_END 0x100FFF #define NV3_PEXTDEV_START 0x101000 // External Devices #define NV3_PSTRAPS 0x101000 // Straps Bits @@ -238,6 +284,7 @@ extern nv3_t* nv3; #define NV3_PGRAPH_INTR_0 0x400100 #define NV3_PGRAPH_INTR_1 0x400104 #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 +#define NV3_PGRAPH_INTR_EN_0_VBLANK 8 // Fired every frame //todo: add what this does #define NV3_PGRAPH_INTR_EN_1 0x400180 // Interrupt Control for PGRAPH #2 (it can receive two at onc) @@ -384,26 +431,6 @@ extern nv3_t* nv3; // Master Control -#define NV3_PMC_BOOT 0x0 -#define NV3_PMC_INTERRUPT 0x100 -#define NV3_PMC_INTERRUPT_ENABLE 0x140 -#define NV3_PMC_ENABLE 0x200 -#define NV3_PMC_ENABLE_PAUDIO 0 // UNUSED - PAudio removed in NV3 Stepping B0 -#define NV3_PMC_ENABLE_PAUDIO_ENABLED 0x1 // UNUSED - PAudio removed in NV3 Stepping B0 -#define NV3_PMC_ENABLE_PMEDIA 4 -#define NV3_PMC_ENABLE_PMEDIA_ENABLED 0x1 -#define NV3_PMC_ENABLE_PFIFO 8 -#define NV3_PMC_ENABLE_PFIFO_ENABLED 0x1 -#define NV3_PMC_ENABLE_PGRAPH 12 -#define NV3_PMC_ENABLE_PGRAPH_ENABLED 0x1 -#define NV3_PMC_ENABLE_PPMI 16 -#define NV3_PMC_ENABLE_PPMI_ENABLED 0x1 -#define NV3_PMC_ENABLE_PFB 20 -#define NV3_PMC_ENABLE_PFB_ENABLED 0x1 -#define NV3_PMC_ENABLE_PCRTC 24 -#define NV3_PMC_ENABLE_PCRTC_ENABLED 0x1 -#define NV3_PMC_ENABLE_PVIDEO 28 -#define NV3_PMC_ENABLE_PVIDEO_ENABLED 0x1 // CRTC/CIO (0x3b0-0x3df) diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 0b307e84a..1ef1c0e36 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -67,6 +67,8 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) ret = nv3_pci_read(0x00, address & 0xFF, NULL); else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END) ret = nv3_pbus_read(address); + else if (address >= NV3_PFIFO_START && address <= NV3_PFIFO_END) + ret = nv3_pfifo_read(address); else if (address >= NV3_PFB_START && address <= NV3_PFB_END) ret = nv3_pfb_read(address); else if (address >= NV3_PRM_START && address <= NV3_PRM_END) diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index d644185a2..e1d1c8352 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -28,8 +28,14 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +// Functions only used in this translation unit +uint32_t nv3_pfb_config0_read(); +void nv3_pfb_config0_write(uint32_t val); + nv_register_t pfb_registers[] = { { NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL}, + { NV3_PFB_CONFIG_0, "PFB Framebuffer Config 0", nv3_pfb_config0_read, nv3_pfb_config0_write }, + { NV3_PFB_CONFIG_1, "PFB Framebuffer Config 1", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -78,7 +84,8 @@ uint32_t nv3_pfb_read(uint32_t address) { case NV3_PFB_BOOT: return nv3->pfb.boot; - break; + case NV3_PFB_CONFIG_1: + return nv3->pfb.config_1; } } } @@ -90,7 +97,7 @@ void nv3_pfb_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); - nv_log("NV3: PFB Write 0x%08x -> 0x%08x\n", value, address); + nv_log("NV3: PFB Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) @@ -103,7 +110,40 @@ void nv3_pfb_write(uint32_t address, uint32_t value) // on-read function if (reg->on_write) reg->on_write(value); - + else + { + switch (reg->address) + { + case NV3_PFB_CONFIG_1: // Config Register 1 + nv3->pfb.config_1 = value; + } + } } - +} + +uint32_t nv3_pfb_config0_read() +{ + return nv3->pfb.config_0; + +} + +void nv3_pfb_config0_write(uint32_t val) +{ + nv3->pfb.config_0 = val; + + // i think the actual size and pixel depth are set in PRAMDAC + // so we don't update things here for now + + uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; + uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; + nv_log("NV3: Framebuffer Config Change\n"); + nv_log("NV3: Horizontal Size=%d pixels\n", new_pfb_htotal); + + if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) + nv_log("NV3: Bit Depth=8bpp\n"); + else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP) + nv_log("NV3: Bit Depth=16bpp\n"); + else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_32BPP) + nv_log("NV3: Bit Depth=32bpp\n"); + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index d37ccdf9f..ac2970e35 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -28,19 +28,20 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... + +// Initialise the PGRAPH subsystem. +void nv3_pgraph_init() +{ + nv_log("NV3: Initialising PGRAPH..."); + // Set up the vblank interrupt + nv3->nvbase.svga.vblank_start = nv3_pgraph_vblank_start; + nv_log("Done!\n"); +} // // ****** PGRAPH register list START ****** // -void nv3_pgraph_init() -{ - nv_log("NV3: Initialising PGRAPH..."); - - nv_log("Done!\n"); -} - nv_register_t pgraph_registers[] = { { NV3_PGRAPH_INTR_0, "PGRAPH Interrupt Status 0", NULL, NULL }, { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL }, @@ -141,11 +142,27 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // and only bit0-16 is defined in intr_1 case NV3_PGRAPH_INTR_EN_0: nv3->pgraph.interrupt_enable_0 = value & 0x11111111; + nv3_pmc_handle_interrupts(true); break; case NV3_PGRAPH_INTR_EN_1: nv3->pgraph.interrupt_enable_1 = value & 0x00011111; + nv3_pmc_handle_interrupts(true); + break; } } } +} + +// Fire a VALID Pgraph interrupt: num is the bit# of the interrupt in the GPU subsystem INTR_EN register. +void nv3_pgraph_interrupt_valid(uint32_t num) +{ + nv3->pgraph.interrupt_enable_0 |= (1 << num); + nv3_pmc_handle_interrupts(true); +} + +// VBlank. Fired every single frame. +void nv3_pgraph_vblank_start(svga_t* svga) +{ + nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_EN_0_VBLANK); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 10717f7bc..63b37f11c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -35,6 +35,7 @@ void nv3_pmc_init() nv_log("NV3: Initialising PMC....\n"); nv3->pmc.boot = NV3_BOOT_REG_DEFAULT; + nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_HARDWARE; nv_log("NV3: Initialising PMC: Done\n"); } @@ -113,11 +114,23 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) // If interrupts are disabled don't bother if (!nv3->pmc.interrupt_enable) + { nv3_pmc_clear_interrupts(); + return nv3->pmc.interrupt_status; + } + // if we actually need to send the interrupt (i.e. this is a write) send it now if (send_now) { + // no interrupts to send + if (!(nv3->pmc.interrupt_status) + || !(nv3->pmc.interrupt_status - 0x80000000)) + { + nv3_pmc_clear_interrupts(); + return nv3->pmc.interrupt_status; + } + if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF)) { if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE) @@ -213,8 +226,8 @@ void nv3_pmc_write(uint32_t address, uint32_t value) switch (reg->address) { case NV3_PMC_INTERRUPT_STATUS: - // this - if (!(nv3->pmc.interrupt_status & (NV3_PMC_INTERRUPT_SOFTWARE - 1))) + // This can only be done by software interrupts... + if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF)) { nv_log("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger " " an interrupt on, rather than writing to NV3_PMC_INTERRUPT_STATUS (Or this is a bug)...NV3_PMC_INTERRUPT_STATUS=0x%08x)\n", nv3->pmc.interrupt_enable); @@ -225,7 +238,8 @@ void nv3_pmc_write(uint32_t address, uint32_t value) nv3->pmc.interrupt_status = value; break; case NV3_PMC_INTERRUPT_ENABLE: - nv3->pmc.interrupt_enable = value; + nv3->pmc.interrupt_enable = value & 0x03; + nv3_pmc_handle_interrupts(value != 0); break; case NV3_PMC_ENABLE: nv3->pmc.enable = value; From 9753b0eca5a861e9017ce23d25878f4b77b23453 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 2 Dec 2024 17:40:31 +0000 Subject: [PATCH 005/274] Make it so you can switch vbioses --- src/include/86box/nv/vid_nv3.h | 10 +++- src/video/CMakeLists.txt | 2 +- src/video/nv/nv3/nv3_core.c | 23 ++++--- src/video/nv/nv3/nv3_core_config.c | 96 ++++++++++++++++++++++++++++++ 4 files changed, 121 insertions(+), 10 deletions(-) create mode 100644 src/video/nv/nv3/nv3_core_config.c diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index bd8d373b7..8f136944c 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -16,10 +16,11 @@ */ // vid_nv3.h: NV3 Architecture Hardware Reference (open-source) -// Last updated 26 November 2024 +// Last updated 2 December 2024 // The GPU base structure extern nv3_t* nv3; +extern const device_config_t nv3_config[]; #define NV3_MMIO_SIZE 0x1000000 // Max MMIO size @@ -34,8 +35,13 @@ extern nv3_t* nv3; #define NV3_VBIOS_DIAMOND_V330_V162 "roms/video/nvidia/nv3/diamond_v330_rev-e.vbi" // Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO #define NV3_VBIOS_ASUS_V3000_V151 "roms/video/nvidia/nv3/riva128_asus.vbi" // ASUS AGP/3DP-V3000 BIOS 1.51B #define NV3_VBIOS_STB_V128_V182 "roms/video/nvidia/nv3/riva128_stb.vbi" // STB Velocity 128 (RIVA 128) Ver.1.82 -#define NV3T_VBIOS_REFERENCE_CEK_V171 "roms/video/nvidia/nv3/BIOS_49_Riva 128" // Reference BIOS: RIVA 128 ZX BIOS - V1.71B-N (C) 1996-98 NVidia Corporation #define NV3T_VBIOS_DIAMOND_V330_V182B "roms/video/nvidia/nv3/nv3t182b.rom" // Diamond Multimedia Viper V330 8M BIOS - Version 1.82B +#define NV3T_VBIOS_ASUS_V170 "roms/video/nvidia/nv3/A170D03T.rom" // ASUS AGP-V3000 ZXTV BIOS - V1.70D.03 (C) 1996-98 Nvidia Corporation +#define NV3T_VBIOS_REFERENCE_CEK_V171 "roms/video/nvidia/nv3/BIOS_49_Riva 128" // Reference BIOS: RIVA 128 ZX BIOS - V1.71B-N (C) 1996-98 NVidia Corporation +#define NV3T_VBIOS_REFERENCE_CEK_V172 "roms/video/nvidia/nv3/vgasgram.rom" // Reference(?) BIOS: RIVA 128 ZX BIOS - V1.72B (C) 1996-98 NVidia Corporation + +// The default VBIOS to use +#define NV3_VBIOS_DEFAULT NV3_VBIOS_ERAZOR_V15403 // Temporary, will be loaded from settings #define VRAM_SIZE_2MB 0x200000 // 2MB diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 1aec0e98d..a7bc62326 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -29,7 +29,7 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c vid_tvp3026_ramdac.c vid_att2xc498_ramdac.c vid_xga.c vid_bochs_vbe.c nv/nv_base.c - nv/nv3/nv3_core.c nv/nv3/nv3_core_arbiter.c nv/nv3/nv3_interrupt.c + nv/nv3/nv3_core.c nv/nv3/nv3_core_config.c nv/nv3/nv3_core_arbiter.c nv/nv3/nv3_interrupt.c nv/nv3/subsystems/nv3_pramdac.c nv/nv3/subsystems/nv3_pfifo.c nv/nv3/subsystems/nv3_pgraph.c diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 3b4394561..83b198461 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -734,15 +734,22 @@ void* nv3_init(const device_t *info) { nv_log("NV3: initialising core\n"); - // currently using ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS] - // ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS] seems to be broken :( - - int32_t err = rom_init(&nv3->nvbase.vbios, NV3_VBIOS_ERAZOR_V15403, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); + // Figure out which vbios the user selected + const char* vbios_id = device_get_config_bios("VBIOS"); + const char* vbios_file = ""; + + // depends on the bus we are using + if (nv3->nvbase.bus_generation == nv_bus_pci) + vbios_file = device_get_bios_file(&nv3_device_pci, vbios_id, 0); + else + vbios_file = device_get_bios_file(&nv3_device_agp, vbios_id, 0); + + int32_t err = rom_init(&nv3->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); if (err) nv_log("NV3: failed to load VBIOS err=%d\n", err); else - nv_log("NV3: Successfully loaded VBIOS %s\n", NV3_VBIOS_ERAZOR_V15403); + nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); // set up the bus and start setting up SVGA core if (nv3->nvbase.bus_generation == nv_bus_pci) @@ -818,7 +825,8 @@ const device_t nv3_device_pci = .init = nv3_init_pci, .close = nv3_close, .speed_changed = nv3_speed_changed, - .force_redraw = nv3_force_redraw + .force_redraw = nv3_force_redraw, + .config = nv3_config, }; // NV3 (RIVA 128) @@ -833,5 +841,6 @@ const device_t nv3_device_agp = .init = nv3_init_agp, .close = nv3_close, .speed_changed = nv3_speed_changed, - .force_redraw = nv3_force_redraw + .force_redraw = nv3_force_redraw, + .config = nv3_config, }; \ No newline at end of file diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c new file mode 100644 index 000000000..f30df0afa --- /dev/null +++ b/src/video/nv/nv3/nv3_core_config.c @@ -0,0 +1,96 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Provides NV3 configuration + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024 starfrost + */ +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +const device_config_t nv3_config[] = +{ + { + .name = "VBIOS", + .description = "VBIOS", + .type = CONFIG_BIOS, + .default_string = "NV3_VBIOS_ERAZOR_V15403", + .default_int = 0, + .bios = + { + { + .name = "[NV3 - 1997-09-30] ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00)", .files_no = 1, + .internal_name = "NV3_VBIOS_ERAZOR_V14700", + .files = {NV3_VBIOS_ERAZOR_V14700, ""} + }, + { + .name = "[NV3 - 1998-02-06] ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, + .internal_name = "NV3_VBIOS_ERAZOR_V15403", + .files = {NV3_VBIOS_ERAZOR_V15403, ""} + }, + { + .name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, + .internal_name = "NV3_VBIOS_ERAZOR_V15500", + .files = {NV3_VBIOS_ERAZOR_V15500, ""} + }, + { + .name = "[NV3 - 1998-01-14] Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO", .files_no = 1, + .internal_name = "NV3_VBIOS_DIAMOND_V330_V162", + .files = {NV3_VBIOS_DIAMOND_V330_V162, ""}, + }, + { + .name = "[NV3 - 1997-09-06] ASUS AGP/3DP-V3000 BIOS 1.51B", .files_no = 1, + .internal_name = "NV3_VBIOS_ASUS_V3000_V151", + .files = {NV3_VBIOS_ASUS_V3000_V151, ""}, + }, + { + .name = "[NV3 - 1997-12-17] STB Velocity 128 (RIVA 128) Ver.1.82", .files_no = 1, + .internal_name = "NV3_VBIOS_STB_V128_V182", + .files = {NV3_VBIOS_STB_V128_V182, ""}, + }, + { + .name = "[NV3T - 1998-09-15] Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1, + .internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B", + .files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""}, + }, + { + .name = "[NV3T - 1998-08-04] ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1, + .internal_name = "NV3T_VBIOS_ASUS_V170", + .files = {NV3T_VBIOS_ASUS_V170, ""}, + }, + { + .name = "[NV3T - 1998-07-30] RIVA 128 ZX BIOS - V1.71B-N", .files_no = 1, + .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171", + .files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""}, + }, + + { + .name = "[NV3T+SGRAM - 1998-08-15] RIVA 128 ZX BIOS - V1.72B", .files_no = 1, + .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172", + .files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""}, + }, + } + }, + { + .type = CONFIG_END + } +}; \ No newline at end of file From b51420307929c77eb0eb8431d8f6ccfa50c9ea96 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 2 Dec 2024 21:15:16 +0000 Subject: [PATCH 006/274] correctly set interrupt_enable at boot + start working on vram config --- src/video/nv/nv3/nv3_core_config.c | 25 +++++++++++++++++++++++++ src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index f30df0afa..7a5bf10ea 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -29,6 +29,7 @@ const device_config_t nv3_config[] = { + // VBIOS type configuration { .name = "VBIOS", .description = "VBIOS", @@ -90,6 +91,30 @@ const device_config_t nv3_config[] = }, } }, + // Memory configuration + { + .name = "VRAM", + .description = "VRAM", + .type = CONFIG_SELECTION, + .selection = + { + // This never existed officially but was planned. Same for 64-bit bus. Debug only + { + .description = "2 MB (Never officially sold)", + .value = VRAM_SIZE_2MB, + }, + + { + .description = "4 MB", + .value = VRAM_SIZE_4MB, + }, + { + .description = "8 MB", + .value = VRAM_SIZE_8MB, + }, + } + + }, { .type = CONFIG_END } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 63b37f11c..c2d010cfd 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -35,7 +35,7 @@ void nv3_pmc_init() nv_log("NV3: Initialising PMC....\n"); nv3->pmc.boot = NV3_BOOT_REG_DEFAULT; - nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_HARDWARE; + nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_SOFTWARE; nv_log("NV3: Initialising PMC: Done\n"); } From e7ca410d36b96fc7d0a58c654c5db5687b07aced Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 5 Dec 2024 22:30:20 +0000 Subject: [PATCH 007/274] added the ability to switch between different amounts of vram --- src/include/86box/nv/vid_nv3.h | 5 +++++ src/video/nv/nv3/nv3_core.c | 13 ++++++++----- src/video/nv/nv3/nv3_core_config.c | 1 + src/video/nv/nv3/subsystems/nv3_pbus.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pramin.c | 24 ++++++++++++------------ 5 files changed, 28 insertions(+), 19 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 8f136944c..1e9b8064c 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -24,6 +24,11 @@ extern const device_config_t nv3_config[]; #define NV3_MMIO_SIZE 0x1000000 // Max MMIO size +#define NV3_LFB_RAMIN_MIRROR_START 0x400000 // Mirror of ramin (VERIFY ON HARDWARE) +#define NV3_LFB_2NDHALF_START 0x800000 // The second half of LFB(?) +#define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start +#define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN + // various vbioses for testing // Coming soon: MIROmagic Premium BIOS (when I get mine dumped) //todo: move to hash system diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 83b198461..c185200f4 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -696,9 +696,10 @@ void nv3_update_mappings() // LFB_BASE+VRAM_SIZE=RAMIN Mirror(?) 0x1400000 (VERIFY PCBOX) // LFB_BASE+VRAM_SIZE*2=LFB Mirror(?) 0x1800000 // LFB_BASE+VRAM_SIZE*3=Definitely RAMIN (then it ends, the total ram space is 16mb) 0x1C00000 - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + VRAM_SIZE_4MB, VRAM_SIZE_4MB); - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + (VRAM_SIZE_4MB * 2), VRAM_SIZE_4MB); - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + (VRAM_SIZE_4MB * 3), VRAM_SIZE_4MB); + + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_MIRROR_START, NV3_LFB_MAPPING_SIZE); + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_2NDHALF_START, NV3_LFB_MAPPING_SIZE); + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_START, NV3_LFB_MAPPING_SIZE); // TODO: RAMIN and its mirror // Did we change the banked SVGA mode? @@ -751,6 +752,8 @@ void* nv3_init(const device_t *info) else nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); + uint32_t vram_amount = device_get_config_int("VRAM"); + // set up the bus and start setting up SVGA core if (nv3->nvbase.bus_generation == nv_bus_pci) { @@ -758,7 +761,7 @@ void* nv3_init(const device_t *info) pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, VRAM_SIZE_4MB, + svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, vram_amount, nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); } else if (nv3->nvbase.bus_generation == nv_bus_agp_1x) @@ -767,7 +770,7 @@ void* nv3_init(const device_t *info) pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, VRAM_SIZE_4MB, + svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, vram_amount, nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); } diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index 7a5bf10ea..f23286693 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -96,6 +96,7 @@ const device_config_t nv3_config[] = .name = "VRAM", .description = "VRAM", .type = CONFIG_SELECTION, + .default_int = VRAM_SIZE_4MB, .selection = { // This never existed officially but was planned. Same for 64-bit bus. Debug only diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index a344d8627..fddedd5cf 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -152,7 +152,7 @@ uint8_t nv3_pbus_rma_read(uint16_t addr) // would svga->fast work? nv3->nvbase.svga.chain4 = true; nv3->nvbase.svga.packed_chain4 = true; - ret = svga_read_linear((real_final_address - NV3_MMIO_SIZE) & (VRAM_SIZE_4MB - 1), &nv3->nvbase.svga); + ret = svga_read_linear((real_final_address - NV3_MMIO_SIZE) & (nv3->nvbase.svga.vram_max - 1), &nv3->nvbase.svga); nv3->nvbase.svga.chain4 = false; nv3->nvbase.svga.packed_chain4 = false; } @@ -234,7 +234,7 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val) { nv3->nvbase.svga.chain4 = true; nv3->nvbase.svga.packed_chain4 = true; - svga_writel_linear((nv3->pbus.rma.addr - NV3_MMIO_SIZE) & (VRAM_SIZE_4MB - 1), nv3->pbus.rma.data, &nv3->nvbase.svga); + svga_writel_linear((nv3->pbus.rma.addr - NV3_MMIO_SIZE) & (nv3->nvbase.svga.vram_max - 1), nv3->pbus.rma.data, &nv3->nvbase.svga); nv3->nvbase.svga.chain4 = false; nv3->nvbase.svga.packed_chain4 = false; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index cef9597c9..9750e2f4c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -43,10 +43,10 @@ // Read 8-bit ramin uint8_t nv3_ramin_read8(uint32_t addr, void* priv) { - addr &= (VRAM_SIZE_4MB - 1); + addr &= (nv3->nvbase.svga.vram_max - 1); uint32_t raw_addr = addr; // saved after and - addr ^= (VRAM_SIZE_4MB - 0x10); + addr ^= (nv3->nvbase.svga.vram_max- 0x10); uint8_t val = nv3->nvbase.svga.vram[addr]; @@ -58,14 +58,14 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) // Read 16-bit ramin uint16_t nv3_ramin_read16(uint32_t addr, void* priv) { - addr &= (VRAM_SIZE_4MB - 1); + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line svga_t* svga = &nv3->nvbase.svga; uint16_t* vram_16bit = (uint16_t*)svga->vram; uint32_t raw_addr = addr; // saved after and - addr ^= (VRAM_SIZE_4MB - 0x10); + addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 1; // what uint16_t val = vram_16bit[addr]; // what @@ -78,14 +78,14 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) // Read 32-bit ramin uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { - addr &= (VRAM_SIZE_4MB - 1); + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line svga_t* svga = &nv3->nvbase.svga; uint32_t* vram_32bit = (uint32_t*)svga->vram; uint32_t raw_addr = addr; // saved after and - addr ^= (VRAM_SIZE_4MB - 0x10); + addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 2; // what uint32_t val = vram_32bit[addr]; @@ -98,14 +98,14 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) // Write 8-bit ramin void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) { - addr &= (VRAM_SIZE_4MB - 1); + addr &= (nv3->nvbase.svga.vram_max - 1); uint32_t raw_addr = addr; // saved after and // Structures in RAMIN are stored from the bottom of vram up in reverse order // this can be explained without bitwise math like so: // real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) - addr ^= (VRAM_SIZE_4MB - 0x10); + addr ^= (nv3->nvbase.svga.vram_max - 0x10); nv3->nvbase.svga.vram[addr] = val; @@ -115,14 +115,14 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) // Write 16-bit ramin void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) { - addr &= (VRAM_SIZE_4MB - 1); + addr &= (nv3->nvbase.svga.vram_max- 1); // why does this not work in one line svga_t* svga = &nv3->nvbase.svga; uint16_t* vram_16bit = (uint16_t*)svga->vram; uint32_t raw_addr = addr; // saved after and - addr ^= (VRAM_SIZE_4MB - 0x10); + addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 1; // what vram_16bit[addr] = val; @@ -133,14 +133,14 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) // Write 32-bit ramin void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) { - addr &= (VRAM_SIZE_4MB - 1); + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line svga_t* svga = &nv3->nvbase.svga; uint32_t* vram_32bit = (uint32_t*)svga->vram; uint32_t raw_addr = addr; // saved after and - addr ^= (VRAM_SIZE_4MB - 0x10); + addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 2; // what vram_32bit[addr] = val; From 831afb5fa16c78c1c0c1759113cd625c8b60e91b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 5 Dec 2024 23:10:50 +0000 Subject: [PATCH 008/274] GPU revision switch, pmc_boot fixes --- src/include/86box/nv/vid_nv.h | 7 ++++++- src/video/nv/nv3/nv3_core.c | 6 ++++-- src/video/nv/nv3/nv3_core_config.c | 23 ++++++++++++++++++++++- src/video/nv/nv3/subsystems/nv3_pmc.c | 8 +++++++- 4 files changed, 39 insertions(+), 5 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index cabd9f46b..bac0220ea 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -97,6 +97,7 @@ typedef struct nv_base_s uint32_t bar0_mmio_base; // PCI Base Address Register 0 - MMIO Base uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) + uint32_t gpu_revision; // GPU Stepping } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E @@ -120,7 +121,11 @@ typedef struct nv_register_s nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs); -#define NV3_BOOT_REG_DEFAULT 0x00300111 +// Default value for the boot information register. +// Depends on the chip +#define NV3_BOOT_REG_REV_A00 0x00030100 +#define NV3_BOOT_REG_REV_B00 0x00030110 +#define NV3_BOOT_REG_REV_C00 0x00030120 // Master Control typedef struct nv3_pmc_s diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index c185200f4..033563998 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -158,7 +158,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) break; case NV3_PCI_CFG_REVISION: - ret = NV3_PCI_CFG_REVISION_B00; // Commercial release + ret = nv3->nvbase.gpu_revision; // Commercial release break; case PCI_REG_PROG_IF: @@ -752,8 +752,10 @@ void* nv3_init(const device_t *info) else nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); + // set the vram amount and gpu revision uint32_t vram_amount = device_get_config_int("VRAM"); - + nv3->nvbase.gpu_revision = device_get_config_int("Chip Revision"); + // set up the bus and start setting up SVGA core if (nv3->nvbase.bus_generation == nv_bus_pci) { diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index f23286693..d7944b69c 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -94,7 +94,7 @@ const device_config_t nv3_config[] = // Memory configuration { .name = "VRAM", - .description = "VRAM", + .description = "VRAM Size", .type = CONFIG_SELECTION, .default_int = VRAM_SIZE_4MB, .selection = @@ -116,6 +116,27 @@ const device_config_t nv3_config[] = } }, + { + .name = "Chip Revision", + .description = "Chip Revision", + .type = CONFIG_SELECTION, + .default_int = NV3_PCI_CFG_REVISION_B00, + .selection = + { + { + .description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997)", + .value = NV3_PCI_CFG_REVISION_A00, + }, + { + .description = "RIVA 128 (NV3) / Stepping B0 (August 1997)", + .value = NV3_PCI_CFG_REVISION_B00, + }, + { + .description = "RIVA 128 ZX (NV3T) / Stepping C0 (March 1998)", + .value = NV3_PCI_CFG_REVISION_C00, + }, + } + }, { .type = CONFIG_END } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index c2d010cfd..50eccfae3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -34,7 +34,13 @@ void nv3_pmc_init() { nv_log("NV3: Initialising PMC....\n"); - nv3->pmc.boot = NV3_BOOT_REG_DEFAULT; + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_A00) + nv3->pmc.boot = NV3_BOOT_REG_REV_A00; + else if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_B00) + nv3->pmc.boot = NV3_BOOT_REG_REV_B00; + else + nv3->pmc.boot = NV3_BOOT_REG_REV_C00; + nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_SOFTWARE; nv_log("NV3: Initialising PMC: Done\n"); From 4c2477a4cf05c040f4368e6149034dd6a7c849f5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 9 Dec 2024 11:57:54 +0000 Subject: [PATCH 009/274] Add read and write PTIMER registers. Doesn't actually do anything as a timer yet. Fix software and hardware interrupts being the wrong way around --- src/include/86box/nv/vid_nv.h | 8 +++- src/include/86box/nv/vid_nv3.h | 5 +++ src/video/nv/nv3/nv3_core.c | 2 +- src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- src/video/nv/nv3/subsystems/nv3_ptimer.c | 47 +++++++++++++++++++++++- 5 files changed, 59 insertions(+), 5 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index bac0220ea..31191833f 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -290,8 +290,12 @@ typedef struct nv3_pextdev_s typedef struct nv3_ptimer_s { - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable + uint32_t interrupt_status; // PTIMER Interrupt status + uint32_t interrupt_enable; // PTIMER Interrupt enable + uint32_t clock_numerator; // PTIMER (tick?) numerator + uint32_t clock_denominator; // PTIMER (tick?) denominator + uint64_t time; // time + uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; // Graphics object hashtable diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 1e9b8064c..1a2f75d0b 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -194,6 +194,11 @@ extern const device_config_t nv3_config[]; #define NV3_PTIMER_START 0x9000 // Programmable Interval Timer #define NV3_PTIMER_INTR 0x9100 #define NV3_PTIMER_INTR_EN 0x9140 +#define NV3_PTIMER_NUMERATOR 0x9200 +#define NV3_PTIMER_DENOMINATOR 0x9210 +#define NV3_PTIMER_TIME_0_NSEC 0x9400 // nanoseconds [31:5] +#define NV3_PTIMER_TIME_1_NSEC 0x9410 // nanoseconds [28:0] +#define NV3_PTIMER_ALARM_NSEC 0x9420 // nanoseconds [31:5] #define NV3_PTIMER_END 0x9FFF #define NV3_VGA_VRAM_START 0xA0000 // VGA Emulation VRAM #define NV3_VGA_VRAM_END 0xBFFFF diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 033563998..d0cbdae3b 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -797,7 +797,7 @@ void* nv3_init(const device_t *info) nv3_pfifo_init(); // Initialise FIFO for graphics object submission nv3_pgraph_init(); // Initialise accelerated graphics engine nv3_ptimer_init(); // Initialise programmable interval timer - nv3_pvideo_init(); // Initialise video overlay engines + nv3_pvideo_init(); // Initialise video overlay engine return nv3; } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 50eccfae3..379c4ed7c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -137,7 +137,7 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) return nv3->pmc.interrupt_status; } - if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF)) + if ((nv3->pmc.interrupt_status & 0x7FFFFFFF)) { if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE) { diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 9e15a1035..1a6c9d73d 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -32,6 +32,11 @@ nv_register_t ptimer_registers[] = { { NV3_PTIMER_INTR, "PTIMER - Interrupt Status", NULL, NULL}, { NV3_PTIMER_INTR_EN, "PTIMER - Interrupt Enable", NULL, NULL,}, + { NV3_PTIMER_NUMERATOR, "PTIMER - Numerator", NULL, NULL, }, + { NV3_PTIMER_DENOMINATOR, "PTIMER - Denominator", NULL, NULL, }, + { NV3_PTIMER_TIME_0_NSEC, "PTIMER - Time0", NULL, NULL, }, + { NV3_PTIMER_TIME_1_NSEC, "PTIMER - Time1", NULL, NULL, }, + { NV3_PTIMER_ALARM_NSEC, "PTIMER - Alarm", NULL, NULL, }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -75,6 +80,24 @@ uint32_t nv3_ptimer_read(uint32_t address) return nv3->ptimer.interrupt_status; case NV3_PTIMER_INTR_EN: return nv3->ptimer.interrupt_enable; + case NV3_PTIMER_NUMERATOR: + return nv3->ptimer.clock_denominator; // 15:0 + break; + case NV3_PTIMER_DENOMINATOR: + return nv3->ptimer.clock_denominator ; //15:0 + break; + // 64-bit value + // High part + case NV3_PTIMER_TIME_0_NSEC: + return nv3->ptimer.time & 0xFFFFFFFF; //28:0 + break; + // Low part + case NV3_PTIMER_TIME_1_NSEC: + return nv3->ptimer.time >> 32; // 31:5 + break; + case NV3_PTIMER_ALARM_NSEC: + return nv3->ptimer.alarm; // 31:5 + break; } } } @@ -112,7 +135,29 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) nv3_pmc_clear_interrupts(); break; case NV3_PTIMER_INTR_EN: - nv3->ptimer.interrupt_enable = value & 0x00000001; + nv3->ptimer.interrupt_enable = value & 0x1; + break; + case NV3_PTIMER_NUMERATOR: + nv3->ptimer.clock_denominator = value & 0xFFFF; // 15:0 + break; + case NV3_PTIMER_DENOMINATOR: + // prevent Div0 + if (!value) + value = 1; + + nv3->ptimer.clock_denominator = value & 0xFFFF; //15:0 + break; + // 64-bit value + // High part + case NV3_PTIMER_TIME_0_NSEC: + nv3->ptimer.time = (value >> 32) & 0xFFFFFFE0; //28:0 + break; + // Low part + case NV3_PTIMER_TIME_1_NSEC: + nv3->ptimer.time = ((value & 0xFFFFFFE0) << 32); // 31:5 + break; + case NV3_PTIMER_ALARM_NSEC: + nv3->ptimer.alarm = value & 0xFFFFFFE0; // 31:5 break; } } From 2f1cac86a77b9fd4b7e3d6c82ab9f68b1c7f5474 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 13 Dec 2024 18:33:37 +0000 Subject: [PATCH 010/274] This is just sot hat we can sync --- src/include/86box/nv/vid_nv3.h | 2 ++ src/video/nv/nv3/subsystems/nv3_ptimer.c | 20 +++++++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 1a2f75d0b..f95d1c5f4 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -193,6 +193,7 @@ extern const device_config_t nv3_config[]; #define NV3_PRMIO_END 0x7FFF #define NV3_PTIMER_START 0x9000 // Programmable Interval Timer #define NV3_PTIMER_INTR 0x9100 +#define NV3_PTIMER_INTR_ALARM 0 // Alarm interrupt #define NV3_PTIMER_INTR_EN 0x9140 #define NV3_PTIMER_NUMERATOR 0x9200 #define NV3_PTIMER_DENOMINATOR 0x9210 @@ -301,6 +302,7 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_INTR_1 0x400104 #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 #define NV3_PGRAPH_INTR_EN_0_VBLANK 8 // Fired every frame +#define NV3_PGRAPH_INTR_EN_0_VBLANK_ENABLED 0x1 // Is the vblank interrupt enabled? //todo: add what this does #define NV3_PGRAPH_INTR_EN_1 0x400180 // Interrupt Control for PGRAPH #2 (it can receive two at onc) diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 1a6c9d73d..1acebc98f 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -48,14 +48,28 @@ void nv3_ptimer_init() nv_log("Done!\n"); } +// Handles the PTIMER alarm interrupt +void nv3_ptimer_interrupt(uint32_t num) +{ + nv3->ptimer.interrupt_enable |= (1 << num); + nv3_pmc_handle_interrupts(true); +} + +// Ticks the timer. +void nv3_ptimer_tick() +{ + if (nv3->ptimer.time >= nv3->ptimer.alarm) + { + nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM); + } +} + uint32_t nv3_ptimer_read(uint32_t address) { - // before doing anything, check the subsystem enablement + // always enabled nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - // todo: friendly logging - nv_log("NV3: PTIMER Read from 0x%08x", address); // if the register actually exists From 6a1979bef82c81616b44c5a0e05633e1ad71adf3 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 20 Dec 2024 18:05:34 +0000 Subject: [PATCH 011/274] Actually add the memory and pixel clocks --- src/include/86box/nv/vid_nv.h | 5 ++++- src/video/nv/nv3/nv3_core.c | 20 ++++++++++++++++++++ src/video/nv/nv3/nv3_core_arbiter.c | 2 -- src/video/nv/nv3/subsystems/nv3_ptimer.c | 10 +++++++++- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 31191833f..e9bd9041c 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -82,7 +82,7 @@ typedef struct nv_base_s { rom_t vbios; // NVIDIA/OEm VBIOS // move to nv3_cio_t? - svga_t svga; // SVGA core (separate to nv3) + svga_t svga; // SVGA core (separate to nv3) - Weitek licensed // stuff that doesn't fit in the svga structure uint32_t cio_read_bank; // SVGA read bank uint32_t cio_write_bank; // SVGA write bank @@ -98,6 +98,8 @@ typedef struct nv_base_s uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping + pc_timer_t pixel_clock_timer; // Pixel Clock Timer + pc_timer_t memory_clock_timer; // Memory Clock Timer } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E @@ -497,6 +499,7 @@ void nv3_pramdac_set_pixel_clock(); // NV3 PTIMER void nv3_ptimer_init(); +void nv3_ptimer_tick(); // NV3 PVIDEO void nv3_pvideo_init(); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index d0cbdae3b..fa85b6f7e 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -728,6 +728,20 @@ void nv3_update_mappings() } } +// Polls the pixel clock. +// This updates the 2D/3D engine PGRAPH +void nv3_pixel_clock_poll(void* priv) +{ + +} + +// Polls the memory clock. +void nv3_memory_clock_poll(void* poll) +{ + // Let's hope qeeg was right here. + nv3_ptimer_tick(); +} + // // Init code // @@ -799,6 +813,12 @@ void* nv3_init(const device_t *info) nv3_ptimer_init(); // Initialise programmable interval timer nv3_pvideo_init(); // Initialise video overlay engine + nv_log("NV3: Starting timers..."); + + // Add the + timer_add(&nv3->nvbase.pixel_clock_timer, nv3_pixel_clock_poll, nv3, true); + timer_add(&nv3->nvbase.memory_clock_timer, nv3_memory_clock_poll, nv3, true); + return nv3; } diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 1ef1c0e36..c52be55e2 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -180,8 +180,6 @@ uint32_t nv3_prm_read(uint32_t address) { return 0; }; void nv3_prm_write(uint32_t address, uint32_t value) {}; uint32_t nv3_prmio_read(uint32_t address) { return 0; }; void nv3_prmio_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_ptimer_read(uint32_t address) { return 0; }; -void nv3_ptimer_write(uint32_t address, uint32_t value) {}; uint32_t nv3_prom_read(uint32_t address) { return 0; }; void nv3_prom_write(uint32_t address, uint32_t value) {}; uint32_t nv3_palt_read(uint32_t address) { return 0; }; diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 1acebc98f..990f9a7fb 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -51,13 +51,21 @@ void nv3_ptimer_init() // Handles the PTIMER alarm interrupt void nv3_ptimer_interrupt(uint32_t num) { - nv3->ptimer.interrupt_enable |= (1 << num); + nv3->ptimer.interrupt_status |= (1 << num); + nv3_pmc_handle_interrupts(true); } // Ticks the timer. void nv3_ptimer_tick() { + // get the current time + double current_time = ((double)nv3->ptimer.clock_numerator) / (double)nv3->ptimer.clock_denominator; // *10.0? + + // truncate it + nv3->ptimer.time += (uint64_t)current_time; + + // Check if the alarm has actually triggered... if (nv3->ptimer.time >= nv3->ptimer.alarm) { nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM); From 60f2828aebb361fbe93f5226608828bbbda52c37 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 20 Dec 2024 19:00:59 +0000 Subject: [PATCH 012/274] fix ptimer numerator and time registers --- src/video/nv/nv3/subsystems/nv3_ptimer.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 990f9a7fb..75b1a3988 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -103,23 +103,18 @@ uint32_t nv3_ptimer_read(uint32_t address) case NV3_PTIMER_INTR_EN: return nv3->ptimer.interrupt_enable; case NV3_PTIMER_NUMERATOR: - return nv3->ptimer.clock_denominator; // 15:0 - break; + return nv3->ptimer.clock_numerator; // 15:0 case NV3_PTIMER_DENOMINATOR: return nv3->ptimer.clock_denominator ; //15:0 - break; // 64-bit value // High part case NV3_PTIMER_TIME_0_NSEC: return nv3->ptimer.time & 0xFFFFFFFF; //28:0 - break; // Low part case NV3_PTIMER_TIME_1_NSEC: return nv3->ptimer.time >> 32; // 31:5 - break; case NV3_PTIMER_ALARM_NSEC: return nv3->ptimer.alarm; // 31:5 - break; } } } @@ -156,11 +151,14 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) nv3->ptimer.interrupt_status &= ~value; nv3_pmc_clear_interrupts(); break; + + // Interrupt enablement state case NV3_PTIMER_INTR_EN: nv3->ptimer.interrupt_enable = value & 0x1; break; + // case NV3_PTIMER_NUMERATOR: - nv3->ptimer.clock_denominator = value & 0xFFFF; // 15:0 + nv3->ptimer.clock_numerator = value & 0xFFFF; // 15:0 break; case NV3_PTIMER_DENOMINATOR: // prevent Div0 @@ -172,11 +170,11 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) // 64-bit value // High part case NV3_PTIMER_TIME_0_NSEC: - nv3->ptimer.time = (value >> 32) & 0xFFFFFFE0; //28:0 + nv3->ptimer.time |= (value) & 0xFFFFFFE0; //28:0 break; // Low part case NV3_PTIMER_TIME_1_NSEC: - nv3->ptimer.time = ((value & 0xFFFFFFE0) << 32); // 31:5 + nv3->ptimer.time |= ((uint64_t)(value & 0xFFFFFFE0) << 32); // 31:5 break; case NV3_PTIMER_ALARM_NSEC: nv3->ptimer.alarm = value & 0xFFFFFFE0; // 31:5 From 2f2fb2724de873e9fe123eadd998126b1005270e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 20 Dec 2024 20:14:38 +0000 Subject: [PATCH 013/274] Correctly set the timers, but setting it all breaks? --- src/include/86box/nv/vid_nv.h | 4 ++ src/include/86box/nv/vid_nv3.h | 3 + src/video/nv/nv3/nv3_core.c | 23 ++----- src/video/nv/nv3/subsystems/nv3_pramdac.c | 75 ++++++++++++++++------- src/video/nv/nv3/subsystems/nv3_ptimer.c | 13 +++- 5 files changed, 76 insertions(+), 42 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index e9bd9041c..930244584 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -98,7 +98,9 @@ typedef struct nv_base_s uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping + double pixel_clock_period; // Period in seconds for pixel clock pc_timer_t pixel_clock_timer; // Pixel Clock Timer + double memory_clock_period; // Period in seconds for pixel clock pc_timer_t memory_clock_timer; // Memory Clock Timer } nv_base_t; @@ -496,6 +498,8 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val); void nv3_pramdac_init(); void nv3_pramdac_set_vram_clock(); void nv3_pramdac_set_pixel_clock(); +void nv3_pramdac_pixel_clock_poll(void* priv); +void nv3_pramdac_memory_clock_poll(void* priv); // NV3 PTIMER void nv3_ptimer_init(); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index f95d1c5f4..ef7041505 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -29,6 +29,9 @@ extern const device_config_t nv3_config[]; #define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start #define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN +#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 100 // The amount by which we have to ration out the memory clock because it's not fast enough... + // Multiply by this value to get the real clock speed. + // various vbioses for testing // Coming soon: MIROmagic Premium BIOS (when I get mine dumped) //todo: move to hash system diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index fa85b6f7e..9d7894f0c 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -728,19 +728,7 @@ void nv3_update_mappings() } } -// Polls the pixel clock. -// This updates the 2D/3D engine PGRAPH -void nv3_pixel_clock_poll(void* priv) -{ -} - -// Polls the memory clock. -void nv3_memory_clock_poll(void* poll) -{ - // Let's hope qeeg was right here. - nv3_ptimer_tick(); -} // // Init code @@ -813,12 +801,13 @@ void* nv3_init(const device_t *info) nv3_ptimer_init(); // Initialise programmable interval timer nv3_pvideo_init(); // Initialise video overlay engine - nv_log("NV3: Starting timers..."); - - // Add the - timer_add(&nv3->nvbase.pixel_clock_timer, nv3_pixel_clock_poll, nv3, true); - timer_add(&nv3->nvbase.memory_clock_timer, nv3_memory_clock_poll, nv3, true); + nv_log("NV3: Initialising timers...\n"); + // These only get turned on when the requisite registers are twiddled + timer_add(&nv3->nvbase.pixel_clock_timer, nv3_pramdac_pixel_clock_poll, nv3, false); + nv_log("NV3: Pixel clock OK. Will be started when the VBIOS tells us to start\n"); + timer_add(&nv3->nvbase.memory_clock_timer, nv3_pramdac_memory_clock_poll, nv3, false); + nv_log("NV3: Memory clock OK. Will be started when the VBIOS tells us to start\n"); return nv3; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 39b5b918f..08270aa8b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -42,15 +42,34 @@ void nv3_pramdac_init() nv3->pramdac.memory_clock_n = nv3->pramdac.pixel_clock_n = 0xc8; nv3->pramdac.memory_clock_p = nv3->pramdac.pixel_clock_p = 0x0c; + nv3_pramdac_set_pixel_clock(); nv3_pramdac_set_vram_clock(); nv_log("NV3: Initialising PRAMDAC: Done\n"); } +// Polls the pixel clock. +// This updates the 2D/3D engine PGRAPH +void nv3_pramdac_pixel_clock_poll(void* priv) +{ + timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period); + +} + +// Polls the memory clock. +void nv3_pramdac_memory_clock_poll(void* poll) +{ + // Let's hope qeeg was right here. + nv3_ptimer_tick(); + + timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period); +} + +// Gets the vram clock register. uint32_t nv3_pramdac_get_vram_clock_register() { - // pack into 19 bits + // the clock format is packed into 19 bits // M divisor [7-0] // N divisor [16-8] // P divisor [18-16] @@ -95,39 +114,51 @@ void nv3_pramdac_set_vram_clock() else frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); + double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box + nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f); + + nv3->nvbase.memory_clock_period = time; + //Breaks everything? + //timer_set_delay_u64(&nv3->nvbase.memory_clock_timer, time * TIMER_USEC); // do we need to decrease } void nv3_pramdac_set_pixel_clock() { - // frequency divider algorithm from old varcem/86box/pcbox riva driver, - // verified by reversing NT drivers v1.50e CalcMNP [symbols] function + // frequency divider algorithm from old varcem/86box/pcbox riva driver, + // verified by reversing NT drivers v1.50e CalcMNP [symbols] function - // todo: actually implement it + // todo: actually implement it - // missing section - // not really needed. - // if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500) - // { - // freq = 13500000.0f; - // } - // else - // - // { - // freq = 14318000.0f; - // } + // missing section + // not really needed. + // if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500) + // { + // freq = 13500000.0f; + // } + // else + // + // { + // freq = 14318000.0f; + // } - float frequency = 13500000.0f; + float frequency = 13500000.0f; - // prevent division by 0 - if (nv3->pramdac.pixel_clock_m == 0) - nv3->pramdac.pixel_clock_m == 1; - else + // prevent division by 0 + if (nv3->pramdac.pixel_clock_m == 0) + nv3->pramdac.pixel_clock_m == 1; + else frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p); - nv3->nvbase.svga.clock = cpuclock / frequency; + nv3->nvbase.svga.clock = cpuclock / frequency; - nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f); + double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box + + nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f); + + nv3->nvbase.pixel_clock_period = time; + //Breaks everything? + //timer_set_delay_u64(&nv3->nvbase.pixel_clock_timer, time * TIMER_USEC); // do we need to decrease } // diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 75b1a3988..ca86716c0 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -59,8 +59,15 @@ void nv3_ptimer_interrupt(uint32_t num) // Ticks the timer. void nv3_ptimer_tick() { + // do not divide by zero + if (nv3->ptimer.clock_numerator == 0 + || nv3->ptimer.clock_denominator == 0) + return; + // get the current time - double current_time = ((double)nv3->ptimer.clock_numerator) / (double)nv3->ptimer.clock_denominator; // *10.0? + // Due to timer system limitations, the timer system is not capable of running at 100 megahertz. Therefore, we have to scale it down and then scale up the level of changes + // to the state. + double current_time = ((double)nv3->ptimer.clock_numerator * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)nv3->ptimer.clock_denominator; // *10.0? // truncate it nv3->ptimer.time += (uint64_t)current_time; @@ -127,7 +134,7 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) // before doing anything, check the subsystem enablement nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - nv_log("NV3: PTIMER Write 0x%08x -> 0x%08x\n", value, address); + nv_log("NV3: PTIMER Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) @@ -156,7 +163,7 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) case NV3_PTIMER_INTR_EN: nv3->ptimer.interrupt_enable = value & 0x1; break; - // + // nUMERATOR case NV3_PTIMER_NUMERATOR: nv3->ptimer.clock_numerator = value & 0xFFFF; // 15:0 break; From a1a15a83d4e34b784968e554730f666ca7458cf9 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 20 Dec 2024 20:16:58 +0000 Subject: [PATCH 014/274] how do you even manage that --- CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakePresets.json b/CMakePresets.json index 94dfd3d79..c7bcba52a 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -66,7 +66,7 @@ "NEW_DYNAREC": "ON", "QT": "ON", "USE_QT6": "OFF", - "Qt5_DIR": "/opt/homebrew/opt/qt@5/lSib/cmake/Qt5", + "Qt5_DIR": "/opt/homebrew/opt/qt@5/lib/cmake/Qt5", "MOLTENVK_DIR": "/opt/homebrew/opt/molten-vk", "Qt5LinguistTools_DIR": "/opt/homebrew/opt/qt@5/lib/cmake/Qt5LinguistTools", "OpenAL_ROOT": "/opt/homebrew/opt/openal-soft", From d2d08d16c184304e86a3f9b62774e06b551a824a Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 20 Dec 2024 21:20:03 +0000 Subject: [PATCH 015/274] Fix the timers...but they run slow. --- src/include/86box/nv/vid_nv.h | 2 ++ src/include/86box/nv/vid_nv3.h | 2 +- src/video/nv/nv3/nv3_core.c | 1 + src/video/nv/nv3/subsystems/nv3_pramdac.c | 32 ++++++++++++++++------- 4 files changed, 27 insertions(+), 10 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 930244584..b7c5fa29a 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -100,8 +100,10 @@ typedef struct nv_base_s uint32_t gpu_revision; // GPU Stepping double pixel_clock_period; // Period in seconds for pixel clock pc_timer_t pixel_clock_timer; // Pixel Clock Timer + bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times double memory_clock_period; // Period in seconds for pixel clock pc_timer_t memory_clock_timer; // Memory Clock Timer + bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index ef7041505..336f6e67b 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -29,7 +29,7 @@ extern const device_config_t nv3_config[]; #define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start #define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN -#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 100 // The amount by which we have to ration out the memory clock because it's not fast enough... +#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1000 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. // various vbioses for testing diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 9d7894f0c..cf4946c44 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -346,6 +346,7 @@ void nv3_close(void* priv) { svga_close(&nv3->nvbase.svga); free(nv3); + nv3 = NULL; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 08270aa8b..3dec7329a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -53,17 +53,20 @@ void nv3_pramdac_init() // This updates the 2D/3D engine PGRAPH void nv3_pramdac_pixel_clock_poll(void* priv) { - timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period); + nv3_t* nv3_poll = (nv3_t*)priv; + timer_on_auto(&nv3_poll->nvbase.pixel_clock_timer, nv3_poll->nvbase.pixel_clock_period); } // Polls the memory clock. -void nv3_pramdac_memory_clock_poll(void* poll) +void nv3_pramdac_memory_clock_poll(void* priv) { + nv3_t* nv3_poll = (nv3_t*)priv; + // Let's hope qeeg was right here. nv3_ptimer_tick(); - timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period); + timer_on_auto(&nv3_poll->nvbase.memory_clock_timer, nv3_poll->nvbase.memory_clock_period); } // Gets the vram clock register. @@ -110,15 +113,21 @@ void nv3_pramdac_set_vram_clock() // prevent division by 0 if (nv3->pramdac.memory_clock_m == 0) - nv3->pramdac.memory_clock_m == 1; - else - frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); + nv3->pramdac.memory_clock_m = 1; + + if (nv3->pramdac.memory_clock_n == 0) + nv3->pramdac.memory_clock_n = 1; + + frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f); nv3->nvbase.memory_clock_period = time; + + timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period); + //Breaks everything? //timer_set_delay_u64(&nv3->nvbase.memory_clock_timer, time * TIMER_USEC); // do we need to decrease } @@ -146,9 +155,12 @@ void nv3_pramdac_set_pixel_clock() // prevent division by 0 if (nv3->pramdac.pixel_clock_m == 0) - nv3->pramdac.pixel_clock_m == 1; - else - frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p); + nv3->pramdac.pixel_clock_m = 1; + + if (nv3->pramdac.memory_clock_n == 0) + nv3->pramdac.memory_clock_n = 1; + + frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p); nv3->nvbase.svga.clock = cpuclock / frequency; @@ -157,6 +169,8 @@ void nv3_pramdac_set_pixel_clock() nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f); nv3->nvbase.pixel_clock_period = time; + + timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period); //Breaks everything? //timer_set_delay_u64(&nv3->nvbase.pixel_clock_timer, time * TIMER_USEC); // do we need to decrease } From 692efc3f0f8e23c9abc3b74cb21df5eaa811c961 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 22 Dec 2024 22:51:08 +0000 Subject: [PATCH 016/274] add a bunch more pgraph headers --- src/include/86box/nv/vid_nv3.h | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 336f6e67b..48ba92526 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -301,13 +301,40 @@ extern const device_config_t nv3_config[]; #define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable #define NV3_PME_END 0x200FFF #define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part +// PGRAPH Core +#define NV3_PGRAPH_DEBUG_0 0x400080 +#define NV3_PGRAPH_DEBUG_1 0x400084 +#define NV3_PGRAPH_DEBUG_2 0x400088 +#define NV3_PGRAPH_DEBUG_3 0x40008C #define NV3_PGRAPH_INTR_0 0x400100 #define NV3_PGRAPH_INTR_1 0x400104 #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 #define NV3_PGRAPH_INTR_EN_0_VBLANK 8 // Fired every frame #define NV3_PGRAPH_INTR_EN_0_VBLANK_ENABLED 0x1 // Is the vblank interrupt enabled? //todo: add what this does -#define NV3_PGRAPH_INTR_EN_1 0x400180 // Interrupt Control for PGRAPH #2 (it can receive two at onc) +#define NV3_PGRAPH_INTR_EN_1 0x400144 // Interrupt Control for PGRAPH #2 (it can receive two at onc) +#define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // DMA context switcher +#define NV3_PGRAPH_CONTEXT_CONTROL 0x400190 // DMA context control +#define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename +#define NV3_PGRAPH_CONTEXT_CACHE(i) 0x4001A0+(i*4) // Context Cache +#define NV3_PGRAPH_CONTEXT_CACHE_SIZE 8 +#define NV3_PGRAPH_SRC_CANVAS_MIN 0x440550 // Minimum Source Canvas for Blit, X,Y position +#define NV3_PGRAPH_SRC_CANVAS_MAX 0x440554 // Maximum Source Canvas for Blit, X,Y position +#define NV3_PGRAPH_DST_CANVAS_MIN 0x440558 // Minimum Destination Canvas for Blit, X,Y position +#define NV3_PGRAPH_DST_CANVAS_MAX 0x44055C // Maximum Destination Canvas for Blit, X,Y position +#define NV3_PGRAPH_CLIP0_MIN 0x440690 // Clip for Blitting 0 Min +#define NV3_PGRAPH_CLIP0_MAX 0x440694 // Clip for Blitting 0 Max +#define NV3_PGRAPH_CLIP1_MIN 0x440698 // Clip for Blitting 1 Min +#define NV3_PGRAPH_CLIP1_MAX 0x44069C // Clip for Blitting 1 Max +#define NV3_PGRAPH_FIFO_ACCESS 0x4006A4 // Is PGRAPH enabled? +#define NV3_PGRAPH_FIFO_ACCESS_DISABLED 0x0 +#define NV3_PGRAPH_FIFO_ACCESS_ENABLED 0x1 +#define NV3_PGRAPH_CLIP_MISC 0x4006A0 // Miscellaneous clipping information +#define NV3_PGRAPH_STATUS 0x4006B0 // Current PGRAPH status +#define NV3_PGRAPH_TRAPPED_ADDRESS 0x4006B4 +#define NV3_PGRAPH_TRAPPED_DATA 0x4006B8 +#define NV3_PGRAPH_TRAPPED_INSTANCE 0x4006BC + // not sure about the class ids // these are NOT what each class is, just uSed to manipulate it (there isn't a one to one class->reg mapping anyway) From 86c52e657b73e0c0c2bf566a2654dae8cc04e07f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 25 Dec 2024 22:22:46 +0000 Subject: [PATCH 017/274] add sanity checks --- src/video/nv/nv3/nv3_core.c | 42 ++++++++++++++++++++++++++--- src/video/nv/nv3/nv3_core_arbiter.c | 8 ++++++ 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index cf4946c44..85abf5ba9 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -100,6 +100,10 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) { + // sanity check + if (!nv3) + return; + uint8_t ret = 0x00; // figure out what size this gets read as first @@ -249,10 +253,12 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) { - // TOTAL IRRELEVANCY + // sanity check + if (!nv3) + return; // some addresses are not writable so can't have any effect and can't be allowed to be modified using this code - // only the most significant byte of the PCI BARs can be modified + // as an example, only the most significant byte of the PCI BARs can be modified if (addr >= NV3_PCI_CFG_BAR0_L && addr <= NV3_PCI_CFG_BAR0_BYTE2 && addr >= NV3_PCI_CFG_BAR1_L && addr <= NV3_PCI_CFG_BAR1_BYTE2) return; @@ -354,7 +360,11 @@ void nv3_close(void* priv) // SVGA functions // void nv3_recalc_timings(svga_t* svga) -{ +{ + // sanity check + if (!nv3) + return; + nv3_t* nv3 = (nv3_t*)svga->priv; svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; @@ -405,6 +415,10 @@ void nv3_recalc_timings(svga_t* svga) void nv3_speed_changed(void* priv) { + // sanity check + if (!nv3) + return; + nv3_recalc_timings(&nv3->nvbase.svga); } @@ -412,12 +426,20 @@ void nv3_speed_changed(void* priv) // Reset etc. void nv3_force_redraw(void* priv) { + // sanity check + if (!nv3) + return; + nv3->nvbase.svga.fullchange = changeframecount; } // Read from SVGA core memory uint8_t nv3_svga_in(uint16_t addr, void* priv) { + // sanity check + if (!nv3) + return; + nv3_t* nv3 = (nv3_t*)priv; uint8_t ret = 0x00; @@ -466,6 +488,9 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv) // Write to SVGA core memory void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) { + // sanity check + if (!nv3) + return; // If we need to RMA to GPU MMIO, go do that if (addr >= NV3_RMA_REGISTER_START @@ -550,6 +575,12 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) void nv3_draw_cursor(svga_t* svga, int32_t drawline) { + // sanity check + if (!nv3) + return; + + // this is a 2kb bitmap in vram...somewhere... + nv_log("nv3_draw_cursor drawline=0x%04x", drawline); } @@ -633,7 +664,10 @@ void nv3_init_mappings() // Updates the mappings after initialisation. void nv3_update_mappings() { - + // sanity check + if (!nv3) + return; + // setting this to 0 doesn't seem to disable it, based on the datasheet nv_log("\nMemory Mapping Config Change:\n"); diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index c52be55e2..9f13f29d5 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -52,6 +52,10 @@ nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, u // Arbitrates an MMIO read uint32_t nv3_mmio_arbitrate_read(uint32_t address) { + // sanity check + if (!nv3) + return; + uint32_t ret = 0x00; // note: some registers are byte aligned not dword aligned @@ -113,6 +117,10 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) { + // sanity check + if (!nv3) + return; + // note: some registers are byte aligned not dword aligned // only very few are though, so they can be handled specially, using the register list most likely address &= 0xFFFFFC; From a426db895607bd46ae8c2a9fdcf45da70e7dc3c2 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 25 Dec 2024 22:24:41 +0000 Subject: [PATCH 018/274] fix build --- src/video/nv/nv3/nv3_core.c | 15 ++++++++------- src/video/nv/nv3/nv3_core_arbiter.c | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 85abf5ba9..e78d624e1 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -100,11 +100,11 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) { + uint8_t ret = 0x00; + // sanity check if (!nv3) - return; - - uint8_t ret = 0x00; + return ret; // figure out what size this gets read as first // seems func does not matter at least here? @@ -436,14 +436,15 @@ void nv3_force_redraw(void* priv) // Read from SVGA core memory uint8_t nv3_svga_in(uint16_t addr, void* priv) { - // sanity check - if (!nv3) - return; nv3_t* nv3 = (nv3_t*)priv; uint8_t ret = 0x00; + // sanity check + if (!nv3) + return ret; + // If we need to RMA from GPU MMIO, go do that if (addr >= NV3_RMA_REGISTER_START && addr <= NV3_RMA_REGISTER_END) @@ -667,7 +668,7 @@ void nv3_update_mappings() // sanity check if (!nv3) return; - + // setting this to 0 doesn't seem to disable it, based on the datasheet nv_log("\nMemory Mapping Config Change:\n"); diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 9f13f29d5..41799c760 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -54,7 +54,7 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) { // sanity check if (!nv3) - return; + return 0x00; uint32_t ret = 0x00; From 8e21fa55459a6b43799d3adbb4479b67655014b8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 15:57:55 +0000 Subject: [PATCH 019/274] Accumulated changes. Update copyright year in anticipation of 2025. More PGRAPH stuff. Start working on guest CPU independent timer (RivaTimer) but not really tested or used yet. Add more docs --- doc/RIVA fansites.txt | 24 ++ doc/Versions.txt | 8 + doc/gpucompanies.txt | 63 +++++ src/86box.c | 4 + src/include/86box/nv/vid_nv3.h | 34 ++- src/include/86box/nv/vid_nv_rivatimer.h | 83 ++++++ src/timer.c | 4 + src/video/CMakeLists.txt | 4 +- src/video/nv/nv3/nv3_core.c | 2 +- src/video/nv/nv3/nv3_core_arbiter.c | 2 +- src/video/nv/nv3/nv3_core_config.c | 2 +- src/video/nv/nv3/nv3_interrupt.c | 0 src/video/nv/nv3/subsystems/nv3_pbus.c | 2 +- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 2 +- src/video/nv/nv3/subsystems/nv3_pextdev.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfb.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 +- src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- src/video/nv/nv3/subsystems/nv3_pme.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 2 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 2 +- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 2 +- src/video/nv/nv3/subsystems/nv3_ptimer.c | 2 +- src/video/nv/nv3/subsystems/nv3_pvideo.c | 2 +- src/video/nv/nv_base.c | 2 +- src/video/nv/nv_rivatimer.c | 248 ++++++++++++++++++ 29 files changed, 481 insertions(+), 29 deletions(-) create mode 100644 doc/RIVA fansites.txt create mode 100644 doc/Versions.txt create mode 100644 doc/gpucompanies.txt create mode 100644 src/include/86box/nv/vid_nv_rivatimer.h delete mode 100644 src/video/nv/nv3/nv3_interrupt.c create mode 100644 src/video/nv/nv_rivatimer.c diff --git a/doc/RIVA fansites.txt b/doc/RIVA fansites.txt new file mode 100644 index 000000000..5a3104837 --- /dev/null +++ b/doc/RIVA fansites.txt @@ -0,0 +1,24 @@ +RIVA fansites (?????): +RIVA User's Group http://tiger.tnstate.edu:8080/ +RIVA 128 Homepage http://pages.prodigy.net/babblin5/Main.html -> Riva3D (riva3d.com) +Zone 128 http://www.tc.umn.edu/~reda0003/zone128/ +RIVAZone https://web.archive.org/web/19981212032348/http://www.rivazone.com/ (Launched January 2, 1998) +Dimension 128 (early domain name that was never archived) -> d128.com (1999-2001) +Riva3D https://web.archive.org/web/20000525110305/http://riva3d.gxnetwork.com/s3.html +nVNews https://web.archive.org/web/20001205171202/http://www.nvnews.net/ (1999-2015) + +BluesNews has stuff https://www.bluesnews.com/archives/ +(July 1996-present!) + +https://www.bluesnews.com/archives/july97-3.html July 21, 1997 ("unreleased nvidia RIVA chipset is indeed faster than 3dfx" (carmack) + +"However, using the nvidia RIVA 128 chip it runs 1 f/s faster" + +https://web.archive.org/web/19980615024744/http://www.ogr.com/columns/techtalk/technology_talk_0611_2.shtml First mention of NV10 (June 1998) + +"RIVA 128 Turbo" early ZX name +"Riva4" early TNT name + +https://web.archive.org/web/20001002193706/http://www.rivazone.com/files/rivalog.txt + +https://web.archive.org/web/20010422044820/http://www.rivazone.com/finger/finger.cgi?nick@finger.nvidia.com nvidia .plan files \ No newline at end of file diff --git a/doc/Versions.txt b/doc/Versions.txt new file mode 100644 index 000000000..052de854f --- /dev/null +++ b/doc/Versions.txt @@ -0,0 +1,8 @@ +Name Base Version Notes Date API Support Platform +0.75_nt4 Version 0.75 No Resource Manager (miniport) 1997-08-15 GDI NT4.0 +0.77_win9x Version 0.77 Symbols (COFF/VXD) 1997-09-02 GDI, D3D5 +nv3quake.zip Version 1.21 OpenGL Alpha 1 1997-11-14 GDI, D3D5, OpenGL 1.1 (alpha; Build 151) Win9x +quakea2f.zip Version 1.21 OpenGL Alpha 2 1997-12-02 GDI, D3D5, OpenGL 1.1 (alpha; Build 258) Win9x +win95_131.zip Version 1.31 OpenGL Beta 1 1998-02-04 GDI, D3D5, OpenGL 1.1 (beta; Build 661) Win9x + + diff --git a/doc/gpucompanies.txt b/doc/gpucompanies.txt new file mode 100644 index 000000000..08a6c61c5 --- /dev/null +++ b/doc/gpucompanies.txt @@ -0,0 +1,63 @@ +GPU companies (the period they made gpus) + +DEC 19xx-1998 +HP 19xx-2000+ (possibly until present) +IBM 19xx-2002+ (possibly until present) +E&S 1968-2006 +Intergraph 1969-2000 +Apple 1976-present (some break) +Motorola 1977-1994+ (???) +TI 1979-1988+ +Matrox 1979-2014 +Hitachi 1981-1986 +SGI 1981-2009 +Intel 1983-present +Number Nine 1983-2000 +Tseng Labs 1983-1997 +Cirrus Logic 1984-1998 +Video 7 1985-1991 +C&T 1985-1999 +Imagination 1985-present +NCR 1986-1993 +Paradise/WD 1986-1996 +Gemini 1987-1990 +Genoa Systems 1987-1991 +Trident 1987-2003 +Oak Technology 1988-1997 +Realtek 1988-1997 +Compaq 1989-1991 +Sun 1989-2002(+?) +S3 Graphics 1989-2010 +Macronix 1989-1998 +Winbond 1989-1996+ +Tamarack 198x-1991+ +UMC 198x-1993 +Sigma Designs 198x-1996 +Acer 198x-1998 (roughly) +Fujitsu 198x-1998 +AMD 1991-present (really starting in 2006) +HMC 1991-1994 +Avance Logic 1991-1995 +Weitek <1991-1996 +Bitboys 1991-2006 +IIT 1992-1994 +Weitek 1992-1996(?) +Rendition 1993-1998 +ARK Logic 1993-1999 +S-MOS/Stellar 1994-1999 +Nvidia 1993-present +Alliance 1994-1997 +iGS 1994-1999 +3dfx 1994-2000 +3dlabs 1994-2006 +Silicon Motion 1995-200? +SiS 1995-2007 +Dynamic Pictures1996-1997 +NeoMagic 1996-2000 +GigaPixel 1997-2000 +Philips 1997-199x +Tatung 199x-199x +ASPEED 2004-present +Jingjia 2006-present + + diff --git a/src/86box.c b/src/86box.c index 5e1f58413..1bb24b055 100644 --- a/src/86box.c +++ b/src/86box.c @@ -103,6 +103,7 @@ #include <86box/machine_status.h> #include <86box/apm.h> #include <86box/acpi.h> +#include <86box/nv/vid_nv_rivatimer.h> // Disable c99-designator to avoid the warnings about int ng #ifdef __clang__ @@ -1421,6 +1422,9 @@ pc_run(void) pc_reset_hard_init(); } + /* Update the guest-CPU independent timer for devices with independent clock speed */ + rivatimer_update_all(); + /* Run a block of code. */ startblit(); cpu_exec((int32_t) cpu_s->rspeed / 100); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 48ba92526..7e8f6f7c1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -318,14 +318,30 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename #define NV3_PGRAPH_CONTEXT_CACHE(i) 0x4001A0+(i*4) // Context Cache #define NV3_PGRAPH_CONTEXT_CACHE_SIZE 8 -#define NV3_PGRAPH_SRC_CANVAS_MIN 0x440550 // Minimum Source Canvas for Blit, X,Y position -#define NV3_PGRAPH_SRC_CANVAS_MAX 0x440554 // Maximum Source Canvas for Blit, X,Y position -#define NV3_PGRAPH_DST_CANVAS_MIN 0x440558 // Minimum Destination Canvas for Blit, X,Y position -#define NV3_PGRAPH_DST_CANVAS_MAX 0x44055C // Maximum Destination Canvas for Blit, X,Y position -#define NV3_PGRAPH_CLIP0_MIN 0x440690 // Clip for Blitting 0 Min -#define NV3_PGRAPH_CLIP0_MAX 0x440694 // Clip for Blitting 0 Max -#define NV3_PGRAPH_CLIP1_MIN 0x440698 // Clip for Blitting 1 Min -#define NV3_PGRAPH_CLIP1_MAX 0x44069C // Clip for Blitting 1 Max +#define NV3_PGRAPH_ABS_UCLIP_XMIN 0x40053C // Clip X minimum +#define NV3_PGRAPH_ABS_UCLIP_XMAX 0x400540 // Clip X maximum +#define NV3_PGRAPH_ABS_UCLIP_YMIN 0x400544 // Clip Y minimum +#define NV3_PGRAPH_ABS_UCLIP_YMAX 0x400548 // Clip Y maximum +#define NV3_PGRAPH_SRC_CANVAS_MIN 0x400550 // Minimum Source Canvas for Blit, X,Y position +#define NV3_PGRAPH_SRC_CANVAS_MAX 0x400554 // Maximum Source Canvas for Blit, X,Y position +#define NV3_PGRAPH_DST_CANVAS_MIN 0x400558 // Minimum Destination Canvas for Blit, X,Y position +#define NV3_PGRAPH_DST_CANVAS_MAX 0x40055C // Maximum Destination Canvas for Blit, X,Y position +#define NV3_PGRAPH_PATTERN_COLOR_0_0 0x400600 +#define NV3_PGRAPH_PATTERN_COLOR_0_1 0x400604 +#define NV3_PGRAPH_PATTERN_COLOR_1_0 0x400608 +#define NV3_PGRAPH_PATTERN_COLOR_1_1 0x40060C // pattern color +#define NV3_PGRAPH_PATTERN_BITMAP_HIGH 0x400610 // pattern bitmap [31:0] +#define NV3_PGRAPH_PATTERN_BITMAP_LOW 0x400614 // pattern bitmap [63:32] +#define NV3_PGRAPH_PATTERN_SHAPE 0x400618 +#define NV3_PGRAPH_ROP3 0x400624 // ROP3 +#define NV3_PGRAPH_PLANE_MASK 0x400628 +#define NV3_PGRAPH_CHROMA_KEY 0x40062C +#define NV3_PGRAPH_BETA 0x400640 // Beta factor (30:23 fractional, 22:0 before fraction) +#define NV3_PGRAPH_NOTIFY 0x400684 // Notifier for PGRAPH +#define NV3_PGRAPH_CLIP0_MIN 0x400690 // Clip for Blitting 0 Min +#define NV3_PGRAPH_CLIP0_MAX 0x400694 // Clip for Blitting 0 Max +#define NV3_PGRAPH_CLIP1_MIN 0x400698 // Clip for Blitting 1 Min +#define NV3_PGRAPH_CLIP1_MAX 0x40069C // Clip for Blitting 1 Max #define NV3_PGRAPH_FIFO_ACCESS 0x4006A4 // Is PGRAPH enabled? #define NV3_PGRAPH_FIFO_ACCESS_DISABLED 0x0 #define NV3_PGRAPH_FIFO_ACCESS_ENABLED 0x1 @@ -335,6 +351,8 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_TRAPPED_DATA 0x4006B8 #define NV3_PGRAPH_TRAPPED_INSTANCE 0x4006BC +#define NV3_PGRAPH_DMA_INTR_0 0x401000 // PGRAPH DMA Interrupt Status +#define NV3_PGRAPH_DMA_INTR_EN_0 0x401140 // PGRAPH DMA Interrupt Enable 0 // not sure about the class ids // these are NOT what each class is, just uSed to manipulate it (there isn't a one to one class->reg mapping anyway) diff --git a/src/include/86box/nv/vid_nv_rivatimer.h b/src/include/86box/nv/vid_nv_rivatimer.h new file mode 100644 index 000000000..00e94cd97 --- /dev/null +++ b/src/include/86box/nv/vid_nv_rivatimer.h @@ -0,0 +1,83 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Fast, high-frequency, guest CPU-independent timer for Riva emulation. + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ + +/* +RivaTimer + +This is a fast, high-frequency, guest CPU-independent timer. + +The main 86box timer is dependent on the TSC (time-stamp counter) register of the emulated CPU core. +This is fine for most purposes and has advantages in the fields of synchronisation and integrates neatly with +the clock dividers of the PC architecture, but in the case of the RIVA 128 it does not particularly suffice +(although it can be made to work with various techniques) since the clock source on the RIVA 128 is on the board itself +and the GPU has several different clocks that control different parts of the GPU (e.g., PTIMER runs on the memory clock but the core gpu is using the pixel clock). + +As faster graphics cards that offload more and more of the 3D graphics pipeline are emulated in the future, more and more work needs to be done by the emulator and +issues of synchronisation with a host CPU will simply make that work harder. Some features that are required for + +Architecture Brand Name 3D Features +NV1 (1995) NV1 Some weird URBS rectangle crap but feature set generally similar to nv3 but a bit worse +NV3 (1997) RIVA 128 (ZX) Triangle setup, edge-slope calculations, edge interpolation, span-slope calculations, span interpolation (Color-buffer, z-buffer, texture mapping, filtering) +NV4 (1998) RIVA TNT NV3 + 2x1 pixel pipelines + 32-bit colour + larger textures + trilinear + more ram (16mb) +NV5 (1999) RIVA TNT2 NV4 + higher clock speed +NV10 (1999) GeForce 256 NV5 + initial geometry transformation + lighting (8x lights) + MPEG-2 motion compensation + 4x1 pixel pipelines +NV15 (2000) GeForce 2 NV10 + First attempt at programmability + 4x2 pixel pipelines +NV20 (2001) GeForce 3 Programmable shaders! + +As you can see, the performance basically exponentially increases over a period of only 4 years. + +So I decided to create this timer that is completely separate from the CPU Core. +*/ + +#pragma once +#include +#include +#include +#include +#include <86Box\86box.h> + +#ifdef _WIN32 +#include +// Linux & MacOS should have the same API since OSX 10.12 +#else +#include +#endif + +typedef struct rivatimer_s +{ + struct rivatimer_s* prev; // Previous Rivatimer + double period; // Period in uS before firing + double value; // The current value of the rivatimer + bool running; // Is this RivaTimer running? + struct rivatimer_s* next; // Next RivaTimer + void (*callback)(); // Callback to call on fire + #ifdef _WIN32 + LARGE_INTEGER starting_time; // Starting time. + #else + struct timespec starting_time; // Starting time. + #endif + double time; // Accumulated time in uS. +} rivatimer_t; + +void rivatimer_init(); // Initialise the Rivatimer. +rivatimer_t* rivatimer_create(double period, void (*callback)()); +void rivatimer_destroy(rivatimer_t* rivatimer_ptr); + +void rivatimer_update_all(); +void rivatimer_start(rivatimer_t* rivatimer_ptr); +void rivatimer_stop(rivatimer_t* rivatimer_ptr); +double rivatimer_get_time(rivatimer_t* rivatimer_ptr); +void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()); \ No newline at end of file diff --git a/src/timer.c b/src/timer.c index 6ddf8ebb5..2b92a1958 100644 --- a/src/timer.c +++ b/src/timer.c @@ -4,6 +4,7 @@ #include #include <86box/86box.h> #include <86box/timer.h> +#include <86Box/nv/vid_nv_rivatimer.h> uint64_t TIMER_USEC; uint32_t timer_target; @@ -168,6 +169,9 @@ timer_init(void) timer_target = 0ULL; tsc = 0; + /* Initialise the CPU-independent timer */ + rivatimer_init(); + timer_inited = 1; } diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index a7bc62326..4b927c9ea 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -28,8 +28,8 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c vid_ibm_rgb528_ramdac.c vid_sdac_ramdac.c vid_ogc.c vid_mga.c vid_nga.c vid_tvp3026_ramdac.c vid_att2xc498_ramdac.c vid_xga.c vid_bochs_vbe.c - nv/nv_base.c - nv/nv3/nv3_core.c nv/nv3/nv3_core_config.c nv/nv3/nv3_core_arbiter.c nv/nv3/nv3_interrupt.c + nv/nv_base.c nv/nv_rivatimer.c + nv/nv3/nv3_core.c nv/nv3/nv3_core_config.c nv/nv3/nv3_core_arbiter.c nv/nv3/subsystems/nv3_pramdac.c nv/nv3/subsystems/nv3_pfifo.c nv/nv3/subsystems/nv3_pgraph.c diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index e78d624e1..f0ff0f028 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -13,7 +13,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include #include diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 41799c760..48c0c93db 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -16,7 +16,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ // STANDARD NV3 includes diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index d7944b69c..3bc8692b9 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -11,7 +11,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include #include diff --git a/src/video/nv/nv3/nv3_interrupt.c b/src/video/nv/nv3/nv3_interrupt.c deleted file mode 100644 index e69de29bb..000000000 diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index fddedd5cf..5d50bf2fb 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email dataess ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 825f326f2..8043fd758 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 761bacdb3..485763696 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -13,7 +13,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index e1d1c8352..9711f3c9a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 8f8abbac4..772839128 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index ac2970e35..b1696f950 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 379c4ed7c..f69b2b430 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index 9683ff5ab..8e0b7ddb5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 3dec7329a..ed89f9448 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ // nv3_pramdac.c: NV3 RAMDAC diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 9750e2f4c..7448f77c7 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -13,7 +13,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index 9a397c8d7..0d141a222 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index baadb9666..5cb9e9d86 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 46c95deac..dd96adb40 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index ca86716c0..1eb53409a 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index 1aede7b0c..ea929ad2c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ #include diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index b67c65dc2..da776a721 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024 starfrost + * Copyright 2024-2025 starfrost */ // Common NV1/3/4... init diff --git a/src/video/nv/nv_rivatimer.c b/src/video/nv/nv_rivatimer.c new file mode 100644 index 000000000..27c63088d --- /dev/null +++ b/src/video/nv/nv_rivatimer.c @@ -0,0 +1,248 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Fast, high-frequency, CPU-independent timer. + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ + +/* See vid_nv_rivatimer.h comments for rationale behind not using the regular timer system + +Notes applicable to this file: +Since Windows XP, QueryPerformanceCounter and QueryPerformanceFrequency cannot fail so they are not checked. + +*/ + +#include <86Box/nv/vid_nv_rivatimer.h> + +#ifdef _WIN32 +LARGE_INTEGER performance_frequency; +#endif + +rivatimer_t* rivatimer_head; // The head of the rivatimer list. +rivatimer_t* rivatimer_tail; // The tail of the rivatimer list. + +/* Functions only used in this translation unit */ +bool rivatimer_really_exists(rivatimer_t* rivatimer); // Determine if a rivatimer really exists in the linked list. + +void rivatimer_init() +{ + // Destroy all the rivatimers. + rivatimer_t* rivatimer_ptr = rivatimer_head; + + if (!rivatimer_ptr) + return; + + while (rivatimer_ptr->next) + rivatimer_destroy(rivatimer_ptr); + + #ifdef _WIN32 + // Query the performance frequency. + QueryPerformanceFrequency(&performance_frequency); + #endif +} + +// Creates a rivatimer. +rivatimer_t* rivatimer_create(double period, void (*callback)()) +{ + rivatimer_t* new_rivatimer = NULL; + + // See i + if (period <= 0 + || !callback) + { + fatal("Invalid rivatimer_create call: period <= 0 or no callback"); + } + + // If there are no rivatimers, create one + if (!rivatimer_head) + { + rivatimer_head = calloc(1, sizeof(rivatimer_t)); + rivatimer_head->prev = NULL; // indicate this is the first in the list even if we don't strictly need to + rivatimer_tail = rivatimer_head; + new_rivatimer = rivatimer_head; + } + else // Otherwise add a new one to the list + { + rivatimer_tail->next = calloc(1, sizeof(rivatimer_t)); + rivatimer_tail = rivatimer_tail->next; + new_rivatimer = rivatimer_tail; + } + + // sanity check + if (new_rivatimer) + { + new_rivatimer->running = false; + new_rivatimer->period = period; + new_rivatimer->next = NULL; // indicate this is the last in the list + new_rivatimer->callback = callback; + } + + return new_rivatimer; +} + +// Determines if a rivatimer really exists. +bool rivatimer_really_exists(rivatimer_t* rivatimer) +{ + rivatimer_t* current = rivatimer_head; + + if (!current) + return false; + + while (current->next != NULL) + { + if (current == rivatimer) + return true; + } + + return false; +} + +// Destroy a rivatimer. +void rivatimer_destroy(rivatimer_t* rivatimer_ptr) +{ + if (!rivatimer_really_exists(rivatimer_ptr)) + fatal("rivatimer_destroy: The timer was already destroyed, or never existed in the first place. Punch starfrost in the face"); + + // Case: We are destroying the head + if (rivatimer_ptr == rivatimer_head) + { + // This is the only rivatimer + if (rivatimer_ptr->next == NULL) + { + rivatimer_head = NULL; + rivatimer_tail = NULL; + } + // This is not the only rivatimer + else + { + rivatimer_head = rivatimer_ptr->next; + rivatimer_head->prev = NULL; + // This is the only rivatimer and now there is only one + if (!rivatimer_head->next) + rivatimer_tail = rivatimer_head; + } + } + // Case: We are destroying the tail + else if (rivatimer_ptr == rivatimer_tail) + { + // We already covered the case where there is only one item above + rivatimer_tail = rivatimer_ptr->prev; + rivatimer_tail->next = NULL; + } + // Case: This is not the first or last rivatimer, so we don't need to set the head or tail + else + { + // Fix the break in the chain that this + if (rivatimer_ptr->next) + rivatimer_ptr->prev->next = rivatimer_ptr->next; + if (rivatimer_ptr->prev) + rivatimer_ptr->next->prev = rivatimer_ptr->prev; + } + + free(rivatimer_ptr); + rivatimer_ptr = NULL; //explicitly set to null +} + +void rivatimer_update_all() +{ + rivatimer_t* rivatimer_ptr = rivatimer_head; + + if (!rivatimer_ptr) + return; + + while (rivatimer_ptr->next) + { + if (!rivatimer_ptr->running) + continue; + + #ifdef _WIN32 + LARGE_INTEGER current_time; + + QueryPerformanceCounter(¤t_time); + + double microseconds = ((double)current_time.QuadPart / 1000000.0) - (rivatimer_ptr->starting_time.QuadPart / 1000000.0); + #else + struct timespec current_time; + + clock_gettime(CLOCK_REALTIME, ¤t_time); + + double microseconds = ((double)current_time.tv_sec * 1000000.0) + ((double)current_time.tv_nsec / 1000.0); + #endif + + rivatimer_ptr->time += microseconds; + + // Reset the current time so we can actually restart + #ifdef _WIN32 + QueryPerformanceCounter(&rivatimer_ptr->starting_time); + #else + clock_gettime(CLOCK_REALTIME, &rivatimer_ptr->starting_time); + #endif + + // Time to fire + if (microseconds > rivatimer_ptr->period) + { + if (!rivatimer_ptr->callback) + { + pclog("Eh? No callback in RivaTimer?"); + continue; + } + + rivatimer_ptr->callback(); + } + } + +} + +void rivatimer_start(rivatimer_t* rivatimer_ptr) +{ + if (!rivatimer_really_exists(rivatimer_ptr)) + fatal("rivatimer_start: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + + if (rivatimer_ptr->period <= 0) + fatal("rivatimer_start: Zero period!"); + + rivatimer_ptr->running = true; + + // Start off so rivatimer_update_all can actually update. + #ifdef _WIN32 + QueryPerformanceCounter(&rivatimer_ptr->starting_time); + #else + clock_gettime(CLOCK_REALTIME, &rivatimer_ptr->starting_time); + #endif +} + +void rivatimer_stop(rivatimer_t* rivatimer_ptr) +{ + if (!rivatimer_really_exists(rivatimer_ptr)) + fatal("rivatimer_stop: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + + rivatimer_ptr->running = false; +} + +// Get the current time value of a rivatimer +double rivatimer_get_time(rivatimer_t* rivatimer_ptr) +{ + if (!rivatimer_really_exists(rivatimer_ptr)) + fatal("rivatimer_get_time: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); +} + +void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()) +{ + if (!rivatimer_really_exists(rivatimer_ptr)) + fatal("rivatimer_set_callback: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + + if (!callback) + fatal("rivatimer_set_callback: No callback!"); + + rivatimer_ptr->callback = callback; +} \ No newline at end of file From 54cc969852c4039d4d1ac6eca74c451a6d94939c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 15:59:55 +0000 Subject: [PATCH 020/274] Implement rivatimer_get_time and reset time on rivatimer_stop. --- src/video/nv/nv_rivatimer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/video/nv/nv_rivatimer.c b/src/video/nv/nv_rivatimer.c index 27c63088d..1ccde5a2f 100644 --- a/src/video/nv/nv_rivatimer.c +++ b/src/video/nv/nv_rivatimer.c @@ -227,6 +227,7 @@ void rivatimer_stop(rivatimer_t* rivatimer_ptr) fatal("rivatimer_stop: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); rivatimer_ptr->running = false; + rivatimer_ptr->time = 0; } // Get the current time value of a rivatimer @@ -234,6 +235,8 @@ double rivatimer_get_time(rivatimer_t* rivatimer_ptr) { if (!rivatimer_really_exists(rivatimer_ptr)) fatal("rivatimer_get_time: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + + return rivatimer_ptr->time; } void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()) From 260323e9a6b8acbb5b3b6641142389e456f6affb Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 16:55:56 +0000 Subject: [PATCH 021/274] Architecture specific registers. Remove duplicate logging. Define the pgraph registers we have being written to so far. --- src/include/86box/nv/vid_nv.h | 384 ---------------------- src/include/86box/nv/vid_nv3.h | 397 ++++++++++++++++++++++- src/video/nv/nv3/nv3_core_arbiter.c | 3 - src/video/nv/nv3/subsystems/nv3_pgraph.c | 58 ++++ 4 files changed, 450 insertions(+), 392 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index b7c5fa29a..9a4a7c55b 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -127,389 +127,5 @@ typedef struct nv_register_s nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs); -// Default value for the boot information register. -// Depends on the chip -#define NV3_BOOT_REG_REV_A00 0x00030100 -#define NV3_BOOT_REG_REV_B00 0x00030110 -#define NV3_BOOT_REG_REV_C00 0x00030120 -// Master Control -typedef struct nv3_pmc_s -{ - /* - Holds chip manufacturing information at bootup. - Current specification (may change later): pre-packed for convenience - - FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?) - 31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001 - little endian 00000000 00000011 00000001 00010001 = 0x00300111 - */ - int32_t boot; - int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems. - int32_t interrupt_enable; // Determines if interrupts are actually enabled. - int32_t enable; // Determines which subsystems are enabled. - -} nv3_pmc_t; - -typedef struct nv3_pci_config_s -{ - uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability) - bool vbios_enabled; // is the vbios enabled? - uint8_t int_line; -} nv3_pci_config_t; - -// add enums for eac -// Chip configuration -typedef struct nv3_straps_s -{ - uint32_t straps; -} nv3_straps_t; - -// Framebuffer -typedef struct nv3_pfb_s -{ - uint32_t boot; - uint32_t config_0; - uint32_t config_1; -} nv3_pfb_t; - -#define NV3_RMA_NUM_REGS 4 -// Access the GPU from real-mode -typedef struct nv3_pbus_rma_s -{ - uint32_t addr; // Address to RMA to - uint32_t data; // Data to send to MMIO - uint8_t mode; // the current state of the rma shifting engin - uint8_t rma_regs[NV3_RMA_NUM_REGS]; // The rma registers (saved) -} nv3_pbus_rma_t; - -// Bus Configuration -typedef struct nv3_pbus_s -{ - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable - nv3_pbus_rma_t rma; -} nv3_pbus_t; - -// Command submission to PGRAPH -typedef struct nv_pfifo_s -{ - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable -} nv3_pfifo_t; - -// RAMDAC -typedef struct nv3_pramdac_s -{ - // these should be uint8_t but C math is a lot better with this - uint32_t memory_clock_m; // memory clock M-divider - uint32_t memory_clock_n; // memory clock N-divider - uint32_t memory_clock_p; // memory clock P-divider - uint32_t pixel_clock_m; // pixel clock M-divider - uint32_t pixel_clock_n; // pixel clock N-divider - uint32_t pixel_clock_p; // pixel clock P-divider - uint32_t coeff_select; // coefficient select - - uint32_t general_control; // general control register - - // this could duplicate SVGA state but I tihnk it's more readable, - // we'll just modify both - uint32_t vserr_width; // vertical sync error width - uint32_t vequ_end; // vequ end (not sure what this is) - uint32_t vbblank_end; // vbblank end (not sure what this is) - uint32_t vblank_end; // vblank end - uint32_t vblank_start; // vblank start - uint32_t vequ_start; // vequ start (not sure what this is) - uint32_t vtotal; // vertical total lines - uint32_t hsync_width; // horizontal sync width - uint32_t hburst_start; // horizontal burst signal start (in lines) - uint32_t hburst_end; // horizontal burst signal end (in lines) - uint32_t hblank_start; // horizontal blank start (in lines) - uint32_t hblank_end; // horizontal blank end (in lines) - uint32_t htotal; // horizontal total lines - uint32_t hequ_width; // horizontal equ width (not sure what this is) - uint32_t hserr_width; // horizontal sync error width -} nv3_pramdac_t; - -// Graphics Subsystem -typedef struct nv3_pgraph_s -{ - uint32_t interrupt_status_0; // Interrupt status 0 - uint32_t interrupt_enable_0; // Interrupt enable 0 - uint32_t interrupt_status_1; // Interrupt status 1 - uint32_t interrupt_enable_1; // Interrupt enable 1 -} nv3_pgraph_t; - -// GPU Manufacturing Configuration (again) -// In the future this will be configurable -typedef struct nv3_pextdev_s -{ - /* - // Disabled 33Mhz - // Enabled 66Mhz - bool bus_speed; - - // Disabled No BIOS - // Enabled BIOS - bool bios; - - // RAM Type #1 - // Disabled 16Mbit (2MB) module size - // Enabled 8Mbit (1MB) module size - bool ram_type_1; - - // NEC Mode - bool nec_mode; - - // Disabled 64-bit - // Enabled 128-bit - bool bus_width; - - // Disabled PCI - // Enabled AGP - bool bus_type; - - // Disabled 13500 - // Enabled 14318180 - bool crystal; - - // TV Mode - // 0 - SECAM, 1 - NTSC, 2 - PAL, 3 - none - uint8_t tv_mode; - - // AGP 2X mode - // Disabled AGP 1X - // Enabled AGP 2X - bool agp_is_2x; - - bool unused; - - // Overwrite enable - bool overwrite; - - See defines in vid_nv3.h - */ - uint32_t straps; - - // more ram type stuff here but not used? -} nv3_pextdev_t; - -typedef struct nv3_ptimer_s -{ - uint32_t interrupt_status; // PTIMER Interrupt status - uint32_t interrupt_enable; // PTIMER Interrupt enable - uint32_t clock_numerator; // PTIMER (tick?) numerator - uint32_t clock_denominator; // PTIMER (tick?) denominator - uint64_t time; // time - uint32_t alarm; // The value of time when there should be an alarm -} nv3_ptimer_t; - -// Graphics object hashtable -typedef struct nv3_pramin_ramht_s -{ - -} nv3_pramin_ramht_t; - -// Anti-fuckup device -typedef struct nv3_pramin_ramro_s -{ - -} nv3_pramin_ramro_t; - -// context for unused channels -typedef struct nv3_pramin_ramfc_s -{ - -} nv3_pramin_ramfc_t; - -// ????? ram auxillary -typedef struct nv_pramin_ramau_s -{ - -} nv3_pramin_ramau_t; - -typedef struct nv3_pramin_s -{ - -} nv3_pramin_t; - -typedef struct nv3_pvideo_s -{ - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable -} nv3_pvideo_t; - -typedef struct nv3_pme_s // Mediaport -{ - uint32_t interrupt_status; - uint32_t interrupt_enable; -} nv3_pme_t; - -typedef struct nv3_s -{ - nv_base_t nvbase; // Base Nvidia structure - - // Config - nv3_straps_t straps; - nv3_pci_config_t pci_config; - - // Subsystems - nv3_pmc_t pmc; // Master Control - nv3_pfb_t pfb; // Framebuffer/VRAM - nv3_pbus_t pbus; // Bus Control - nv3_pfifo_t pfifo; // FIFO for command submisison - - nv3_pramdac_t pramdac; // RAMDAC (CLUT etc) - nv3_pgraph_t pgraph; // 2D/3D Graphics - nv3_pextdev_t pextdev; // Chip configuration - nv3_ptimer_t ptimer; // programmable interval timer - nv3_pramin_ramht_t ramht; // hashtable for PGRAPH objects - nv3_pramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission - nv3_pramin_ramfc_t ramfc; // context for unused channels - nv3_pramin_ramau_t ramau; // auxillary weirdnes - nv3_pramin_t pramin; // Ram for INput of DMA objects. Very important! - nv3_pvideo_t pvideo; // Video overlay - nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface - //more here - -} nv3_t; - -// device objects -extern nv3_t* nv3; - -// Address of this returned by unimplemented registers to prevent a crash -extern uint32_t unimplemented_dummy; - -// NV3 stuff - -// Device Core -void* nv3_init(const device_t *info); -void nv3_close(void* priv); -void nv3_speed_changed(void *priv); -void nv3_force_redraw(void* priv); - -// Memory Mapping -void nv3_update_mappings(); -uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO -uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO -uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO -void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit MMIO -void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit MMIO -void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit MMIO - -uint8_t nv3_svga_in(uint16_t addr, void* priv); // Read SVGA compatibility registers -void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); // Write SVGA registers -uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv); // Read PCI configuration registers -void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers - -uint8_t nv3_ramin_read8(uint32_t addr, void* priv); // Read 8-bit RAMIN -uint16_t nv3_ramin_read16(uint32_t addr, void* priv); // Read 16-bit RAMIN -uint32_t nv3_ramin_read32(uint32_t addr, void* priv); // Read 32-bit RAMIN -void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit RAMIN -void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN -void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN - -// MMIO Arbitration -// Determine where the hell in this mess our reads or writes are going -uint32_t nv3_mmio_arbitrate_read(uint32_t address); -void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value); - -// Read and Write functions for GPU subsystems -// Remove the ones that aren't used here eventually, have all of htem for now -uint32_t nv3_pmc_read(uint32_t address); -void nv3_pmc_write(uint32_t address, uint32_t value); -uint32_t nv3_cio_read(uint32_t address); -void nv3_cio_write(uint32_t address, uint32_t value); -uint32_t nv3_pbus_read(uint32_t address); -void nv3_pbus_write(uint32_t address, uint32_t value); -uint32_t nv3_pfifo_read(uint32_t address); -void nv3_pfifo_write(uint32_t address, uint32_t value); -uint32_t nv3_prm_read(uint32_t address); -void nv3_prm_write(uint32_t address, uint32_t value); -uint32_t nv3_prmio_read(uint32_t address); -void nv3_prmio_write(uint32_t address, uint32_t value); -uint32_t nv3_ptimer_read(uint32_t address); -void nv3_ptimer_write(uint32_t address, uint32_t value); -uint32_t nv3_pfb_read(uint32_t address); -void nv3_pfb_write(uint32_t address, uint32_t value); -uint32_t nv3_pextdev_read(uint32_t address); -void nv3_pextdev_write(uint32_t address, uint32_t value); - -// Special consideration for straps -#define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS) -#define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x) - -uint32_t nv3_prom_read(uint32_t address); -void nv3_prom_write(uint32_t address, uint32_t value); -uint32_t nv3_palt_read(uint32_t address); -void nv3_palt_write(uint32_t address, uint32_t value); -uint32_t nv3_pme_read(uint32_t address); -void nv3_pme_write(uint32_t address, uint32_t value); -uint32_t nv3_pgraph_read(uint32_t address); -void nv3_pgraph_write(uint32_t address, uint32_t value); - -// TODO: PGRAPH class registers - -uint32_t nv3_prmcio_read(uint32_t address); -void nv3_prmcio_write(uint32_t address, uint32_t value); -uint32_t nv3_pvideo_read(uint32_t address); -void nv3_pvideo_write(uint32_t address, uint32_t value); -uint32_t nv3_pramdac_read(uint32_t address); -void nv3_pramdac_write(uint32_t address, uint32_t value); -uint32_t nv3_vram_read(uint32_t address); -void nv3_vram_write(uint32_t address, uint32_t value); -#define nv3_nvm_read nv3_vram_read -#define nv3_nvm_write nv3_vram_write -uint32_t nv3_user_read(uint32_t address); -void nv3_user_write(uint32_t address, uint32_t value); -#define nv3_object_submit_start nv3_user_read -#define nv3_object_submit_end nv3_user_write -uint32_t nv3_pramin_read(uint32_t address); -void nv3_pramin_write(uint32_t address, uint32_t value); -// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* - -// GPU subsystems - -// NV3 PMC -void nv3_pmc_init(); -uint32_t nv3_pmc_clear_interrupts(); -uint32_t nv3_pmc_handle_interrupts(bool send_now); - -// NV3 PGRAPH -void nv3_pgraph_init(); -void nv3_pgraph_vblank_start(svga_t* svga); - -// NV3 PFIFO -void nv3_pfifo_init(); - - -// NV3 PFB -void nv3_pfb_init(); - -// NV3 PEXTDEV/PSTRAPS -void nv3_pextdev_init(); - -// NV3 PBUS -void nv3_pbus_init(); - -// NV3 PBUS RMA - Real Mode Access for VBIOS -uint8_t nv3_pbus_rma_read(uint16_t addr); -void nv3_pbus_rma_write(uint16_t addr, uint8_t val); - -// NV3 PRAMDAC -void nv3_pramdac_init(); -void nv3_pramdac_set_vram_clock(); -void nv3_pramdac_set_pixel_clock(); -void nv3_pramdac_pixel_clock_poll(void* priv); -void nv3_pramdac_memory_clock_poll(void* priv); - -// NV3 PTIMER -void nv3_ptimer_init(); -void nv3_ptimer_tick(); - -// NV3 PVIDEO -void nv3_pvideo_init(); - -// NV3 PMEDIA -void nv3_pmedia_init(); #endif \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 7e8f6f7c1..db9474602 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -19,7 +19,6 @@ // Last updated 2 December 2024 // The GPU base structure -extern nv3_t* nv3; extern const device_config_t nv3_config[]; #define NV3_MMIO_SIZE 0x1000000 // Max MMIO size @@ -31,6 +30,11 @@ extern const device_config_t nv3_config[]; #define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1000 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. +// Default value for the boot information register. +// Depends on the chip +#define NV3_BOOT_REG_REV_A00 0x00030100 +#define NV3_BOOT_REG_REV_B00 0x00030110 +#define NV3_BOOT_REG_REV_C00 0x00030120 // various vbioses for testing // Coming soon: MIROmagic Premium BIOS (when I get mine dumped) @@ -318,14 +322,15 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename #define NV3_PGRAPH_CONTEXT_CACHE(i) 0x4001A0+(i*4) // Context Cache #define NV3_PGRAPH_CONTEXT_CACHE_SIZE 8 +// TODO: CLIP0/CLIP1 (8 clips min/max in 32bits) #define NV3_PGRAPH_ABS_UCLIP_XMIN 0x40053C // Clip X minimum #define NV3_PGRAPH_ABS_UCLIP_XMAX 0x400540 // Clip X maximum #define NV3_PGRAPH_ABS_UCLIP_YMIN 0x400544 // Clip Y minimum #define NV3_PGRAPH_ABS_UCLIP_YMAX 0x400548 // Clip Y maximum -#define NV3_PGRAPH_SRC_CANVAS_MIN 0x400550 // Minimum Source Canvas for Blit, X,Y position -#define NV3_PGRAPH_SRC_CANVAS_MAX 0x400554 // Maximum Source Canvas for Blit, X,Y position -#define NV3_PGRAPH_DST_CANVAS_MIN 0x400558 // Minimum Destination Canvas for Blit, X,Y position -#define NV3_PGRAPH_DST_CANVAS_MAX 0x40055C // Maximum Destination Canvas for Blit, X,Y position +#define NV3_PGRAPH_SRC_CANVAS_MIN 0x400550 // Minimum Source Canvas for Blit, Y=30:16, X=10:0 +#define NV3_PGRAPH_SRC_CANVAS_MAX 0x400554 // Maximum Source Canvas for Blit, Y=30:16, X=10:0 +#define NV3_PGRAPH_DST_CANVAS_MIN 0x400558 // Minimum Destination Canvas for Blit, Y=30:16, X=10:0 +#define NV3_PGRAPH_DST_CANVAS_MAX 0x40055C // Maximum Destination Canvas for Blit, Y=30:16, X=10:0 #define NV3_PGRAPH_PATTERN_COLOR_0_0 0x400600 #define NV3_PGRAPH_PATTERN_COLOR_0_1 0x400604 #define NV3_PGRAPH_PATTERN_COLOR_1_0 0x400608 @@ -575,5 +580,387 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F +/* + STRUCTURES FOR THE GPU START HERE +*/ + //todo: pixel format +// Master Control +typedef struct nv3_pmc_s +{ + /* + Holds chip manufacturing information at bootup. + Current specification (may change later): pre-packed for convenience + + FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?) + 31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001 + little endian 00000000 00000011 00000001 00010001 = 0x00300111 + */ + int32_t boot; + int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems. + int32_t interrupt_enable; // Determines if interrupts are actually enabled. + int32_t enable; // Determines which subsystems are enabled. + +} nv3_pmc_t; + +typedef struct nv3_pci_config_s +{ + uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability) + bool vbios_enabled; // is the vbios enabled? + uint8_t int_line; +} nv3_pci_config_t; + +// add enums for eac +// Chip configuration +typedef struct nv3_straps_s +{ + uint32_t straps; +} nv3_straps_t; + +// Framebuffer +typedef struct nv3_pfb_s +{ + uint32_t boot; + uint32_t config_0; + uint32_t config_1; +} nv3_pfb_t; + +#define NV3_RMA_NUM_REGS 4 +// Access the GPU from real-mode +typedef struct nv3_pbus_rma_s +{ + uint32_t addr; // Address to RMA to + uint32_t data; // Data to send to MMIO + uint8_t mode; // the current state of the rma shifting engin + uint8_t rma_regs[NV3_RMA_NUM_REGS]; // The rma registers (saved) +} nv3_pbus_rma_t; + +// Bus Configuration +typedef struct nv3_pbus_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable + nv3_pbus_rma_t rma; +} nv3_pbus_t; + +// Command submission to PGRAPH +typedef struct nv_pfifo_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable +} nv3_pfifo_t; + +// RAMDAC +typedef struct nv3_pramdac_s +{ + // these should be uint8_t but C math is a lot better with this + uint32_t memory_clock_m; // memory clock M-divider + uint32_t memory_clock_n; // memory clock N-divider + uint32_t memory_clock_p; // memory clock P-divider + uint32_t pixel_clock_m; // pixel clock M-divider + uint32_t pixel_clock_n; // pixel clock N-divider + uint32_t pixel_clock_p; // pixel clock P-divider + uint32_t coeff_select; // coefficient select + + uint32_t general_control; // general control register + + // this could duplicate SVGA state but I tihnk it's more readable, + // we'll just modify both + uint32_t vserr_width; // vertical sync error width + uint32_t vequ_end; // vequ end (not sure what this is) + uint32_t vbblank_end; // vbblank end (not sure what this is) + uint32_t vblank_end; // vblank end + uint32_t vblank_start; // vblank start + uint32_t vequ_start; // vequ start (not sure what this is) + uint32_t vtotal; // vertical total lines + uint32_t hsync_width; // horizontal sync width + uint32_t hburst_start; // horizontal burst signal start (in lines) + uint32_t hburst_end; // horizontal burst signal end (in lines) + uint32_t hblank_start; // horizontal blank start (in lines) + uint32_t hblank_end; // horizontal blank end (in lines) + uint32_t htotal; // horizontal total lines + uint32_t hequ_width; // horizontal equ width (not sure what this is) + uint32_t hserr_width; // horizontal sync error width +} nv3_pramdac_t; + +// Graphics Subsystem +typedef struct nv3_pgraph_s +{ + uint32_t interrupt_status_0; // Interrupt status 0 + uint32_t interrupt_enable_0; // Interrupt enable 0 + uint32_t interrupt_status_1; // Interrupt status 1 + uint32_t interrupt_enable_1; // Interrupt enable 1 + + uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE]; // DMA context cache +} nv3_pgraph_t; + +// GPU Manufacturing Configuration (again) +// In the future this will be configurable +typedef struct nv3_pextdev_s +{ + /* + // Disabled 33Mhz + // Enabled 66Mhz + bool bus_speed; + + // Disabled No BIOS + // Enabled BIOS + bool bios; + + // RAM Type #1 + // Disabled 16Mbit (2MB) module size + // Enabled 8Mbit (1MB) module size + bool ram_type_1; + + // NEC Mode + bool nec_mode; + + // Disabled 64-bit + // Enabled 128-bit + bool bus_width; + + // Disabled PCI + // Enabled AGP + bool bus_type; + + // Disabled 13500 + // Enabled 14318180 + bool crystal; + + // TV Mode + // 0 - SECAM, 1 - NTSC, 2 - PAL, 3 - none + uint8_t tv_mode; + + // AGP 2X mode + // Disabled AGP 1X + // Enabled AGP 2X + bool agp_is_2x; + + bool unused; + + // Overwrite enable + bool overwrite; + + See defines in vid_nv3.h + */ + uint32_t straps; + + // more ram type stuff here but not used? +} nv3_pextdev_t; + +typedef struct nv3_ptimer_s +{ + uint32_t interrupt_status; // PTIMER Interrupt status + uint32_t interrupt_enable; // PTIMER Interrupt enable + uint32_t clock_numerator; // PTIMER (tick?) numerator + uint32_t clock_denominator; // PTIMER (tick?) denominator + uint64_t time; // time + uint32_t alarm; // The value of time when there should be an alarm +} nv3_ptimer_t; + +// Graphics object hashtable +typedef struct nv3_pramin_ramht_s +{ + +} nv3_pramin_ramht_t; + +// Anti-fuckup device +typedef struct nv3_pramin_ramro_s +{ + +} nv3_pramin_ramro_t; + +// context for unused channels +typedef struct nv3_pramin_ramfc_s +{ + +} nv3_pramin_ramfc_t; + +// ????? ram auxillary +typedef struct nv_pramin_ramau_s +{ + +} nv3_pramin_ramau_t; + +typedef struct nv3_pramin_s +{ + +} nv3_pramin_t; + +typedef struct nv3_pvideo_s +{ + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable +} nv3_pvideo_t; + +typedef struct nv3_pme_s // Mediaport +{ + uint32_t interrupt_status; + uint32_t interrupt_enable; +} nv3_pme_t; + +typedef struct nv3_s +{ + nv_base_t nvbase; // Base Nvidia structure + + // Config + nv3_straps_t straps; + nv3_pci_config_t pci_config; + + // Subsystems + nv3_pmc_t pmc; // Master Control + nv3_pfb_t pfb; // Framebuffer/VRAM + nv3_pbus_t pbus; // Bus Control + nv3_pfifo_t pfifo; // FIFO for command submisison + + nv3_pramdac_t pramdac; // RAMDAC (CLUT etc) + nv3_pgraph_t pgraph; // 2D/3D Graphics + nv3_pextdev_t pextdev; // Chip configuration + nv3_ptimer_t ptimer; // programmable interval timer + nv3_pramin_ramht_t ramht; // hashtable for PGRAPH objects + nv3_pramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission + nv3_pramin_ramfc_t ramfc; // context for unused channels + nv3_pramin_ramau_t ramau; // auxillary weirdnes + nv3_pramin_t pramin; // Ram for INput of DMA objects. Very important! + nv3_pvideo_t pvideo; // Video overlay + nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface + //more here + +} nv3_t; + +// device objects +extern nv3_t* nv3; + +// NV3 stuff + +// Device Core +void* nv3_init(const device_t *info); +void nv3_close(void* priv); +void nv3_speed_changed(void *priv); +void nv3_force_redraw(void* priv); + +// Memory Mapping +void nv3_update_mappings(); +uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO +uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO +uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO +void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit MMIO +void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit MMIO +void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit MMIO + +uint8_t nv3_svga_in(uint16_t addr, void* priv); // Read SVGA compatibility registers +void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); // Write SVGA registers +uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv); // Read PCI configuration registers +void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers + +uint8_t nv3_ramin_read8(uint32_t addr, void* priv); // Read 8-bit RAMIN +uint16_t nv3_ramin_read16(uint32_t addr, void* priv); // Read 16-bit RAMIN +uint32_t nv3_ramin_read32(uint32_t addr, void* priv); // Read 32-bit RAMIN +void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit RAMIN +void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN +void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN + +// MMIO Arbitration +// Determine where the hell in this mess our reads or writes are going +uint32_t nv3_mmio_arbitrate_read(uint32_t address); +void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value); + +// Read and Write functions for GPU subsystems +// Remove the ones that aren't used here eventually, have all of htem for now +uint32_t nv3_pmc_read(uint32_t address); +void nv3_pmc_write(uint32_t address, uint32_t value); +uint32_t nv3_cio_read(uint32_t address); +void nv3_cio_write(uint32_t address, uint32_t value); +uint32_t nv3_pbus_read(uint32_t address); +void nv3_pbus_write(uint32_t address, uint32_t value); +uint32_t nv3_pfifo_read(uint32_t address); +void nv3_pfifo_write(uint32_t address, uint32_t value); +uint32_t nv3_prm_read(uint32_t address); +void nv3_prm_write(uint32_t address, uint32_t value); +uint32_t nv3_prmio_read(uint32_t address); +void nv3_prmio_write(uint32_t address, uint32_t value); +uint32_t nv3_ptimer_read(uint32_t address); +void nv3_ptimer_write(uint32_t address, uint32_t value); +uint32_t nv3_pfb_read(uint32_t address); +void nv3_pfb_write(uint32_t address, uint32_t value); +uint32_t nv3_pextdev_read(uint32_t address); +void nv3_pextdev_write(uint32_t address, uint32_t value); + +// Special consideration for straps +#define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS) +#define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x) + +uint32_t nv3_prom_read(uint32_t address); +void nv3_prom_write(uint32_t address, uint32_t value); +uint32_t nv3_palt_read(uint32_t address); +void nv3_palt_write(uint32_t address, uint32_t value); +uint32_t nv3_pme_read(uint32_t address); +void nv3_pme_write(uint32_t address, uint32_t value); +uint32_t nv3_pgraph_read(uint32_t address); +void nv3_pgraph_write(uint32_t address, uint32_t value); + +// TODO: PGRAPH class registers + +uint32_t nv3_prmcio_read(uint32_t address); +void nv3_prmcio_write(uint32_t address, uint32_t value); +uint32_t nv3_pvideo_read(uint32_t address); +void nv3_pvideo_write(uint32_t address, uint32_t value); +uint32_t nv3_pramdac_read(uint32_t address); +void nv3_pramdac_write(uint32_t address, uint32_t value); +uint32_t nv3_vram_read(uint32_t address); +void nv3_vram_write(uint32_t address, uint32_t value); +#define nv3_nvm_read nv3_vram_read +#define nv3_nvm_write nv3_vram_write +uint32_t nv3_user_read(uint32_t address); +void nv3_user_write(uint32_t address, uint32_t value); +#define nv3_object_submit_start nv3_user_read +#define nv3_object_submit_end nv3_user_write +uint32_t nv3_pramin_read(uint32_t address); +void nv3_pramin_write(uint32_t address, uint32_t value); +// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* + +// GPU subsystems + +// NV3 PMC +void nv3_pmc_init(); +uint32_t nv3_pmc_clear_interrupts(); +uint32_t nv3_pmc_handle_interrupts(bool send_now); + +// NV3 PGRAPH +void nv3_pgraph_init(); +void nv3_pgraph_vblank_start(svga_t* svga); + +// NV3 PFIFO +void nv3_pfifo_init(); + + +// NV3 PFB +void nv3_pfb_init(); + +// NV3 PEXTDEV/PSTRAPS +void nv3_pextdev_init(); + +// NV3 PBUS +void nv3_pbus_init(); + +// NV3 PBUS RMA - Real Mode Access for VBIOS +uint8_t nv3_pbus_rma_read(uint16_t addr); +void nv3_pbus_rma_write(uint16_t addr, uint8_t val); + +// NV3 PRAMDAC (Final presentation) +void nv3_pramdac_init(); +void nv3_pramdac_set_vram_clock(); +void nv3_pramdac_set_pixel_clock(); +void nv3_pramdac_pixel_clock_poll(void* priv); +void nv3_pramdac_memory_clock_poll(void* priv); + +// NV3 PTIMER +void nv3_ptimer_init(); +void nv3_ptimer_tick(); + +// NV3 PVIDEO +void nv3_pvideo_init(); + +// NV3 PMEDIA (Mediaport) +void nv3_pmedia_init(); diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 48c0c93db..e74e6a93d 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -111,7 +111,6 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) return 0x00; } - nv_log("NV3: MMIO read, 0x%08x <- 0x%08x\n", ret, address); return ret; } @@ -171,8 +170,6 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); return; } - - nv_log("NV3: MMIO write, 0x%08x -> 0x%08x\n", value, address); } diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index b1696f950..9fa06d019 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -47,6 +47,39 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL }, { NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL }, { NV3_PGRAPH_INTR_EN_1, "PGRAPH Interrupt Enable 1", NULL, NULL }, + { NV3_PGRAPH_CONTEXT_SWITCH, "PGRAPH DMA Context Switch", NULL, NULL }, + { NV3_PGRAPH_CONTEXT_CONTROL, "PGRAPH DMA Context Control", NULL, NULL }, + { NV3_PGRAPH_CONTEXT_USER, "PGRAPH DMA Context User", NULL, NULL }, + //{ NV3_PGRAPH_CONTEXT_CACHE(0), "PGRAPH DMA Context Cache", NULL, NULL }, + { NV3_PGRAPH_ABS_UCLIP_XMIN, "PGRAPH Absolute Clip Minimum X [17:0]", NULL, NULL }, + { NV3_PGRAPH_ABS_UCLIP_XMAX, "PGRAPH Absolute Clip Maximum X [17:0]", NULL, NULL }, + { NV3_PGRAPH_ABS_UCLIP_YMIN, "PGRAPH Absolute Clip Minimum Y [17:0]", NULL, NULL }, + { NV3_PGRAPH_ABS_UCLIP_YMAX, "PGRAPH Absolute Clip Maximum Y [17:0]", NULL, NULL }, + { NV3_PGRAPH_SRC_CANVAS_MIN, "PGRAPH Source Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_SRC_CANVAS_MAX, "PGRAPH Source Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_DST_CANVAS_MIN, "PGRAPH Destination Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_DST_CANVAS_MAX, "PGRAPH Destination Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_PATTERN_COLOR_0_0, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_0_1, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_1_0, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_1_1, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_BITMAP_HIGH, "PGRAPH Pattern Bitmap (High 32bits)", NULL, NULL}, + { NV3_PGRAPH_PATTERN_BITMAP_LOW, "PGRAPH Pattern Bitmap (Low 32bits)", NULL, NULL}, + { NV3_PGRAPH_PATTERN_SHAPE, "PGRAPH Pattern Shape (1:0 - 0=8x8, 1=64x1, 2=1x64)", NULL, NULL}, + { NV3_PGRAPH_ROP3, "PGRAPH Render Operation ROP3 (2^3 bits = 256 possible operations)", NULL, NULL}, + { NV3_PGRAPH_PLANE_MASK, "PGRAPH Current Plane Mask (7:0)", NULL, NULL}, + { NV3_PGRAPH_CHROMA_KEY, "PGRAPH Chroma Key (17:0) (Bit 30 = Alpha, 29:20 = Red, 19:10 = Green, 9:0 = Blue)", NULL, NULL}, + { NV3_PGRAPH_NOTIFY, "PGRAPH Notifier (Wip...)", NULL, NULL}, + { NV3_PGRAPH_CLIP0_MIN, "PGRAPH Clip0 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_CLIP0_MAX, "PGRAPH Clip0 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_CLIP1_MIN, "PGRAPH Clip1 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_CLIP1_MAX, "PGRAPH Clip1 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, + { NV3_PGRAPH_FIFO_ACCESS, "PGRAPH - Can we access PFIFO?", NULL, NULL, }, + { NV3_PGRAPH_STATUS, "PGRAPH Status", NULL, NULL }, + { NV3_PGRAPH_TRAPPED_ADDRESS, "PGRAPH Trapped Address", NULL, NULL }, + { NV3_PGRAPH_TRAPPED_DATA, "PGRAPH Trapped Data", NULL, NULL }, + { NV3_PGRAPH_TRAPPED_INSTANCE, "PGRAPH Trapped Object Instance", NULL, NULL }, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -95,6 +128,18 @@ uint32_t nv3_pgraph_read(uint32_t address) } } + else + { + /* Special exception for memory areas */ + if (address >= NV3_PGRAPH_CONTEXT_CACHE(0) + && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE)) + { + // Addresses should be aligned to 4 bytes. + uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); + + nv_log("NV3: PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); + } + } return 0x0; } @@ -152,6 +197,19 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) } } } + else + { + /* Special exception for memory areas */ + if (address >= NV3_PGRAPH_CONTEXT_CACHE(0) + && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE)) + { + // Addresses should be aligned to 4 bytes. + uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); + + nv_log("NV3: PGRAPH Context Cache Write (Entry=%04x Value=%04x)\n", entry, value); + nv3->pgraph.context_cache[entry] = value; + } + } } // Fire a VALID Pgraph interrupt: num is the bit# of the interrupt in the GPU subsystem INTR_EN register. From 378af452d654fdca740a64524a717f6eaf787e4d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 17:18:14 +0000 Subject: [PATCH 022/274] Refactor the read functions --- src/video/nv/nv3/subsystems/nv3_pbus.c | 25 ++++++---- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 1 - src/video/nv/nv3/subsystems/nv3_pextdev.c | 23 +++++---- src/video/nv/nv3/subsystems/nv3_pfb.c | 27 +++++++---- src/video/nv/nv3/subsystems/nv3_pfifo.c | 26 ++++++---- src/video/nv/nv3/subsystems/nv3_pgraph.c | 27 ++++++----- src/video/nv/nv3/subsystems/nv3_pmc.c | 30 +++++++----- src/video/nv/nv3/subsystems/nv3_pme.c | 19 ++++++-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 47 ++++++++++++------- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 1 - .../nv/nv3/subsystems/nv3_pramin_ramht.c | 1 - .../nv/nv3/subsystems/nv3_pramin_ramro.c | 1 - src/video/nv/nv3/subsystems/nv3_ptimer.c | 29 ++++++++---- src/video/nv/nv3/subsystems/nv3_pvideo.c | 20 ++++++-- 14 files changed, 175 insertions(+), 102 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 5d50bf2fb..b61c36e52 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -49,6 +49,8 @@ uint32_t nv3_pbus_read(uint32_t address) { nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); + uint32_t ret = 0x00; + // todo: friendly logging nv_log("NV3: PBUS Read from 0x%08x", address); @@ -56,30 +58,33 @@ uint32_t nv3_pbus_read(uint32_t address) // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { switch (reg->address) { case NV3_PBUS_INTR: - return nv3->pbus.interrupt_status; + ret = nv3->pbus.interrupt_status; break; case NV3_PBUS_INTR_EN: - return nv3->pbus.interrupt_enable; + ret = nv3->pbus.interrupt_enable; break; } - } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pbus_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 8043fd758..1ce59171a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -28,4 +28,3 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 485763696..452550ad9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -84,7 +84,7 @@ uint32_t nv3_pextdev_read(uint32_t address) { nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); - // todo: friendly logging + uint32_t ret = 0x00; // special consideration for straps if (address == NV3_PSTRAPS) @@ -94,31 +94,34 @@ uint32_t nv3_pextdev_read(uint32_t address) else { nv_log("NV3: PEXTDEV Read from 0x%08x", address); - } // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { switch (reg->address) { case NV3_PSTRAPS: - return nv3->pextdev.straps; + ret = nv3->pextdev.straps; } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pextdev_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 9711f3c9a..02f3618ff 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -63,6 +63,8 @@ uint32_t nv3_pfb_read(uint32_t address) { nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); + uint32_t ret = 0x00; + // todo: friendly logging nv_log("NV3: PFB Read from 0x%08x", address); @@ -70,27 +72,32 @@ uint32_t nv3_pfb_read(uint32_t address) // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { switch (reg->address) { case NV3_PFB_BOOT: - return nv3->pfb.boot; + ret = nv3->pfb.boot; + // Config 0 has a read/write function case NV3_PFB_CONFIG_1: - return nv3->pfb.config_1; + ret = nv3->pfb.config_1; } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pfb_write(uint32_t address, uint32_t value) @@ -114,6 +121,7 @@ void nv3_pfb_write(uint32_t address, uint32_t value) { switch (reg->address) { + // Config 0 has a read/write function case NV3_PFB_CONFIG_1: // Config Register 1 nv3->pfb.config_1 = value; } @@ -124,7 +132,6 @@ void nv3_pfb_write(uint32_t address, uint32_t value) uint32_t nv3_pfb_config0_read() { return nv3->pfb.config_0; - } void nv3_pfb_config0_write(uint32_t val) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 772839128..e5453a348 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -28,7 +28,7 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... + // // ****** pfifo register list START ****** @@ -59,6 +59,8 @@ uint32_t nv3_pfifo_read(uint32_t address) return 0x00; } + uint32_t ret = 0x00; + nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); // todo: friendly logging @@ -68,14 +70,10 @@ uint32_t nv3_pfifo_read(uint32_t address) // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { // Interrupt state: @@ -87,13 +85,23 @@ uint32_t nv3_pfifo_read(uint32_t address) switch (reg->address) { case NV3_PFIFO_INTR: - return nv3->pfifo.interrupt_status; + ret = nv3->pfifo.interrupt_status; case NV3_PFIFO_INTR_EN: - return nv3->pfifo.interrupt_enable; + ret = nv3->pfifo.interrupt_enable; } } + + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); } - return 0x0; + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + } + + return ret; } void nv3_pfifo_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 9fa06d019..68ba20509 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -94,6 +94,8 @@ uint32_t nv3_pgraph_read(uint32_t address) return 0x00; } + uint32_t ret = 0x00; + nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); // todo: friendly logging @@ -103,30 +105,29 @@ uint32_t nv3_pgraph_read(uint32_t address) // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { switch (reg->address) { //interrupt status and enable regs case NV3_PGRAPH_INTR_0: - return nv3->pgraph.interrupt_status_0; + ret = nv3->pgraph.interrupt_status_0; case NV3_PGRAPH_INTR_1: - return nv3->pgraph.interrupt_status_1; + ret = nv3->pgraph.interrupt_status_1; case NV3_PGRAPH_INTR_EN_0: - return nv3->pgraph.interrupt_enable_0; + ret = nv3->pgraph.interrupt_enable_0; case NV3_PGRAPH_INTR_EN_1: - return nv3->pgraph.interrupt_enable_1; + ret = nv3->pgraph.interrupt_enable_1; } } + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); } else { @@ -139,9 +140,13 @@ uint32_t nv3_pgraph_read(uint32_t address) nv_log("NV3: PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); } + else /* Completely unknown */ + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + } } - return 0x0; + return ret; } void nv3_pgraph_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index f69b2b430..e8c3fe0e1 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -28,7 +28,7 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... + void nv3_pmc_init() { @@ -172,41 +172,47 @@ uint32_t nv3_pmc_read(uint32_t address) { nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); + uint32_t ret = 0x00; + // todo: friendly logging nv_log("NV3: PMC Read from 0x%08x", address); // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { switch (reg->address) { case NV3_PMC_BOOT: - return nv3->pmc.boot; + ret = nv3->pmc.boot; case NV3_PMC_INTERRUPT_STATUS: nv3_pmc_clear_interrupts(); - return nv3_pmc_handle_interrupts(false); + ret = nv3_pmc_handle_interrupts(false); case NV3_PMC_INTERRUPT_ENABLE: //TODO: ACTUALLY CHANGE THE INTERRUPT STATE - return nv3->pmc.interrupt_enable; + ret = nv3->pmc.interrupt_enable; case NV3_PMC_ENABLE: - return nv3->pmc.enable; + ret = nv3->pmc.enable; } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pmc_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index 8e0b7ddb5..b55ed4df0 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -45,6 +45,8 @@ uint32_t nv3_pme_read(uint32_t address) { nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); + uint32_t ret = 0x00; + // todo: friendly logging nv_log("NV3: PME Read from 0x%08x", address); @@ -59,7 +61,7 @@ uint32_t nv3_pme_read(uint32_t address) // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { // Interrupt state: @@ -71,14 +73,23 @@ uint32_t nv3_pme_read(uint32_t address) switch (reg->address) { case NV3_PME_INTR: - return nv3->pme.interrupt_status; + ret = nv3->pme.interrupt_status; case NV3_PME_INTR_EN: - return nv3->pme.interrupt_enable; + ret = nv3->pme.interrupt_enable; } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pme_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index ed89f9448..46ccde970 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -210,6 +210,8 @@ uint32_t nv3_pramdac_read(uint32_t address) { nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); + uint32_t ret = 0x00; + // todo: friendly logging nv_log("NV3: PRAMDAC Read from 0x%08x", address); @@ -224,49 +226,58 @@ uint32_t nv3_pramdac_read(uint32_t address) // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { //s hould be pretty easy to understand switch (reg->address) { case NV3_PRAMDAC_COEFF_SELECT: - return nv3->pramdac.coeff_select; + ret = nv3->pramdac.coeff_select; case NV3_PRAMDAC_GENERAL_CONTROL: - return nv3->pramdac.general_control; + ret = nv3->pramdac.general_control; case NV3_PRAMDAC_VSERR_WIDTH: - return nv3->pramdac.vserr_width; + ret = nv3->pramdac.vserr_width; case NV3_PRAMDAC_VBBLANK_END: - return nv3->pramdac.vbblank_end; + ret = nv3->pramdac.vbblank_end; case NV3_PRAMDAC_VBLANK_END: - return nv3->pramdac.vblank_end; + ret = nv3->pramdac.vblank_end; case NV3_PRAMDAC_VBLANK_START: - return nv3->pramdac.vblank_start; + ret = nv3->pramdac.vblank_start; case NV3_PRAMDAC_VEQU_START: - return nv3->pramdac.vequ_start; + ret = nv3->pramdac.vequ_start; case NV3_PRAMDAC_VTOTAL: - return nv3->pramdac.vtotal; + ret = nv3->pramdac.vtotal; case NV3_PRAMDAC_HSYNC_WIDTH: - return nv3->pramdac.hsync_width; + ret = nv3->pramdac.hsync_width; case NV3_PRAMDAC_HBURST_START: - return nv3->pramdac.hburst_start; + ret = nv3->pramdac.hburst_start; case NV3_PRAMDAC_HBURST_END: - return nv3->pramdac.hburst_end; + ret = nv3->pramdac.hburst_end; case NV3_PRAMDAC_HBLANK_START: - return nv3->pramdac.hblank_start; + ret = nv3->pramdac.hblank_start; case NV3_PRAMDAC_HBLANK_END: - return nv3->pramdac.hblank_end; + ret = nv3->pramdac.hblank_end; case NV3_PRAMDAC_HTOTAL: - return nv3->pramdac.htotal; + ret = nv3->pramdac.htotal; case NV3_PRAMDAC_HEQU_WIDTH: - return nv3->pramdac.hequ_width; + ret = nv3->pramdac.hequ_width; case NV3_PRAMDAC_HSERR_WIDTH: - return nv3->pramdac.hserr_width; + ret = nv3->pramdac.hserr_width; } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pramdac_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index 0d141a222..5c6d3a54c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -28,4 +28,3 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index 5cb9e9d86..7f80a1035 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -28,4 +28,3 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index dd96adb40..865bc46ec 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -28,4 +28,3 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> -// Single unified write function... \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 1eb53409a..2a722e4e1 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -87,6 +87,8 @@ uint32_t nv3_ptimer_read(uint32_t address) nv_log("NV3: PTIMER Read from 0x%08x", address); + uint32_t ret = 0x00; + // if the register actually exists if (reg) { @@ -97,7 +99,7 @@ uint32_t nv3_ptimer_read(uint32_t address) // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { // Interrupt state: @@ -106,27 +108,36 @@ uint32_t nv3_ptimer_read(uint32_t address) switch (reg->address) { case NV3_PTIMER_INTR: - return nv3->ptimer.interrupt_status; + ret = nv3->ptimer.interrupt_status; case NV3_PTIMER_INTR_EN: - return nv3->ptimer.interrupt_enable; + ret = nv3->ptimer.interrupt_enable; case NV3_PTIMER_NUMERATOR: - return nv3->ptimer.clock_numerator; // 15:0 + ret = nv3->ptimer.clock_numerator; // 15:0 case NV3_PTIMER_DENOMINATOR: - return nv3->ptimer.clock_denominator ; //15:0 + ret = nv3->ptimer.clock_denominator ; //15:0 // 64-bit value // High part case NV3_PTIMER_TIME_0_NSEC: - return nv3->ptimer.time & 0xFFFFFFFF; //28:0 + ret = nv3->ptimer.time & 0xFFFFFFFF; //28:0 // Low part case NV3_PTIMER_TIME_1_NSEC: - return nv3->ptimer.time >> 32; // 31:5 + ret = nv3->ptimer.time >> 32; // 31:5 case NV3_PTIMER_ALARM_NSEC: - return nv3->ptimer.alarm; // 31:5 + ret = nv3->ptimer.alarm; // 31:5 } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x00; + return ret; } void nv3_ptimer_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index ea929ad2c..6e0a725a4 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -48,7 +48,8 @@ uint32_t nv3_pvideo_read(uint32_t address) // before doing anything, check the subsystem enablement nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); - + uint32_t ret = 0x00; + // todo: friendly logging nv_log("NV3: PVIDEO Read from 0x%08x", address); @@ -63,7 +64,7 @@ uint32_t nv3_pvideo_read(uint32_t address) // on-read function if (reg->on_read) - return reg->on_read(); + ret = reg->on_read(); else { // Interrupt state: @@ -72,14 +73,23 @@ uint32_t nv3_pvideo_read(uint32_t address) switch (reg->address) { case NV3_PVIDEO_INTR: - return nv3->pvideo.interrupt_status; + ret = nv3->pvideo.interrupt_status; case NV3_PVIDEO_INTR_EN: - return nv3->pvideo.interrupt_enable; + ret = nv3->pvideo.interrupt_enable; } } + + if (reg->friendly_name) + nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } + else + { + nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); } - return 0x0; + return ret; } void nv3_pvideo_write(uint32_t address, uint32_t value) From 88cc5f07f7b8d1937f69002fb99c9bfa6db6212f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 17:24:17 +0000 Subject: [PATCH 023/274] sort out the logging but there are still regressions (driver fail to boot) --- src/video/nv/nv3/nv3_core.c | 2 ++ src/video/nv/nv3/subsystems/nv3_pbus.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pextdev.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pfb.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pmc.c | 7 ++++--- src/video/nv/nv3/subsystems/nv3_pme.c | 9 ++------- src/video/nv/nv3/subsystems/nv3_pramdac.c | 11 +++-------- src/video/nv/nv3/subsystems/nv3_ptimer.c | 11 +++-------- src/video/nv/nv3/subsystems/nv3_pvideo.c | 4 ++-- 11 files changed, 25 insertions(+), 37 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index f0ff0f028..dde1043c4 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -842,8 +842,10 @@ void* nv3_init(const device_t *info) // These only get turned on when the requisite registers are twiddled timer_add(&nv3->nvbase.pixel_clock_timer, nv3_pramdac_pixel_clock_poll, nv3, false); nv_log("NV3: Pixel clock OK. Will be started when the VBIOS tells us to start\n"); + timer_add(&nv3->nvbase.memory_clock_timer, nv3_pramdac_memory_clock_poll, nv3, false); nv_log("NV3: Memory clock OK. Will be started when the VBIOS tells us to start\n"); + return nv3; } diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index b61c36e52..84df73169 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -75,13 +75,13 @@ uint32_t nv3_pbus_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 452550ad9..d4c1ce353 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -112,13 +112,13 @@ uint32_t nv3_pextdev_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 02f3618ff..3172f30d3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -88,13 +88,13 @@ uint32_t nv3_pfb_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index e5453a348..6b6ab2aaf 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -98,7 +98,7 @@ uint32_t nv3_pfifo_read(uint32_t address) } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 68ba20509..070eabd62 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -125,7 +125,7 @@ uint32_t nv3_pgraph_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } @@ -142,7 +142,7 @@ uint32_t nv3_pgraph_read(uint32_t address) } else /* Completely unknown */ { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index e8c3fe0e1..d94798152 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -190,9 +190,10 @@ uint32_t nv3_pmc_read(uint32_t address) case NV3_PMC_BOOT: ret = nv3->pmc.boot; case NV3_PMC_INTERRUPT_STATUS: + nv_log("\n"); // clear_interrupts logs nv3_pmc_clear_interrupts(); - ret = nv3_pmc_handle_interrupts(false); + ret = nv3_pmc_handle_interrupts(false); case NV3_PMC_INTERRUPT_ENABLE: //TODO: ACTUALLY CHANGE THE INTERRUPT STATE ret = nv3->pmc.interrupt_enable; @@ -203,13 +204,13 @@ uint32_t nv3_pmc_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index b55ed4df0..11b84a040 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -54,11 +54,6 @@ uint32_t nv3_pme_read(uint32_t address) // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) ret = reg->on_read(); @@ -80,13 +75,13 @@ uint32_t nv3_pme_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 46ccde970..8d162fe2b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -211,7 +211,7 @@ uint32_t nv3_pramdac_read(uint32_t address) nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); uint32_t ret = 0x00; - + // todo: friendly logging nv_log("NV3: PRAMDAC Read from 0x%08x", address); @@ -219,11 +219,6 @@ uint32_t nv3_pramdac_read(uint32_t address) // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) ret = reg->on_read(); @@ -268,13 +263,13 @@ uint32_t nv3_pramdac_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 2a722e4e1..1d714222a 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -88,15 +88,10 @@ uint32_t nv3_ptimer_read(uint32_t address) nv_log("NV3: PTIMER Read from 0x%08x", address); uint32_t ret = 0x00; - + // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_read) ret = reg->on_read(); @@ -128,13 +123,13 @@ uint32_t nv3_ptimer_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index 6e0a725a4..f5e1ee4e8 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -80,13 +80,13 @@ uint32_t nv3_pvideo_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = %04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); } return ret; From 3914a00f9b7d5a92f0649ba13c1b94e29a62b87c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 17:58:02 +0000 Subject: [PATCH 024/274] Local idiot forgets break; wonders why code does not work? --- src/video/nv/nv3/subsystems/nv3_pbus.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pextdev.c | 5 +++-- src/video/nv/nv3/subsystems/nv3_pfb.c | 6 ++++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 4 +++- src/video/nv/nv3/subsystems/nv3_pgraph.c | 8 ++++++-- src/video/nv/nv3/subsystems/nv3_pmc.c | 12 ++++++++---- src/video/nv/nv3/subsystems/nv3_pme.c | 6 ++++-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 20 ++++++++++++++++++-- src/video/nv/nv3/subsystems/nv3_ptimer.c | 12 ++++++++++-- src/video/nv/nv3/subsystems/nv3_pvideo.c | 6 ++++-- 10 files changed, 62 insertions(+), 21 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 84df73169..cf5b698a1 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -75,13 +75,13 @@ uint32_t nv3_pbus_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index d4c1ce353..2fbbd3489 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -108,17 +108,18 @@ uint32_t nv3_pextdev_read(uint32_t address) { case NV3_PSTRAPS: ret = nv3->pextdev.straps; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 3172f30d3..4de4d5069 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -81,20 +81,22 @@ uint32_t nv3_pfb_read(uint32_t address) { case NV3_PFB_BOOT: ret = nv3->pfb.boot; + break; // Config 0 has a read/write function case NV3_PFB_CONFIG_1: ret = nv3->pfb.config_1; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 6b6ab2aaf..c5868ef10 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -86,8 +86,10 @@ uint32_t nv3_pfifo_read(uint32_t address) { case NV3_PFIFO_INTR: ret = nv3->pfifo.interrupt_status; + break; case NV3_PFIFO_INTR_EN: ret = nv3->pfifo.interrupt_enable; + break; } } @@ -98,7 +100,7 @@ uint32_t nv3_pfifo_read(uint32_t address) } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 070eabd62..d7b7bfb01 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -115,17 +115,21 @@ uint32_t nv3_pgraph_read(uint32_t address) //interrupt status and enable regs case NV3_PGRAPH_INTR_0: ret = nv3->pgraph.interrupt_status_0; + break; case NV3_PGRAPH_INTR_1: ret = nv3->pgraph.interrupt_status_1; + break; case NV3_PGRAPH_INTR_EN_0: ret = nv3->pgraph.interrupt_enable_0; + break; case NV3_PGRAPH_INTR_EN_1: ret = nv3->pgraph.interrupt_enable_1; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } @@ -142,7 +146,7 @@ uint32_t nv3_pgraph_read(uint32_t address) } else /* Completely unknown */ { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index d94798152..6b2b51b09 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -189,28 +189,32 @@ uint32_t nv3_pmc_read(uint32_t address) { case NV3_PMC_BOOT: ret = nv3->pmc.boot; + break; case NV3_PMC_INTERRUPT_STATUS: nv_log("\n"); // clear_interrupts logs nv3_pmc_clear_interrupts(); ret = nv3_pmc_handle_interrupts(false); + break; case NV3_PMC_INTERRUPT_ENABLE: //TODO: ACTUALLY CHANGE THE INTERRUPT STATE - ret = nv3->pmc.interrupt_enable; + ret = nv3->pmc.interrupt_enable; + break; case NV3_PMC_ENABLE: - ret = nv3->pmc.enable; + ret = nv3->pmc.enable; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index 11b84a040..2ba4af426 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -69,19 +69,21 @@ uint32_t nv3_pme_read(uint32_t address) { case NV3_PME_INTR: ret = nv3->pme.interrupt_status; + break; case NV3_PME_INTR_EN: ret = nv3->pme.interrupt_enable; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 8d162fe2b..d30900d43 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -229,47 +229,63 @@ uint32_t nv3_pramdac_read(uint32_t address) { case NV3_PRAMDAC_COEFF_SELECT: ret = nv3->pramdac.coeff_select; + break; case NV3_PRAMDAC_GENERAL_CONTROL: ret = nv3->pramdac.general_control; + break; case NV3_PRAMDAC_VSERR_WIDTH: ret = nv3->pramdac.vserr_width; + break; case NV3_PRAMDAC_VBBLANK_END: ret = nv3->pramdac.vbblank_end; + break; case NV3_PRAMDAC_VBLANK_END: ret = nv3->pramdac.vblank_end; + break; case NV3_PRAMDAC_VBLANK_START: ret = nv3->pramdac.vblank_start; + break; case NV3_PRAMDAC_VEQU_START: ret = nv3->pramdac.vequ_start; + break; case NV3_PRAMDAC_VTOTAL: ret = nv3->pramdac.vtotal; + break; case NV3_PRAMDAC_HSYNC_WIDTH: ret = nv3->pramdac.hsync_width; + break; case NV3_PRAMDAC_HBURST_START: ret = nv3->pramdac.hburst_start; + break; case NV3_PRAMDAC_HBURST_END: ret = nv3->pramdac.hburst_end; + break; case NV3_PRAMDAC_HBLANK_START: ret = nv3->pramdac.hblank_start; + break; case NV3_PRAMDAC_HBLANK_END: ret = nv3->pramdac.hblank_end; + break; case NV3_PRAMDAC_HTOTAL: ret = nv3->pramdac.htotal; + break; case NV3_PRAMDAC_HEQU_WIDTH: ret = nv3->pramdac.hequ_width; + break; case NV3_PRAMDAC_HSERR_WIDTH: ret = nv3->pramdac.hserr_width; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 1d714222a..7e718264a 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -104,32 +104,40 @@ uint32_t nv3_ptimer_read(uint32_t address) { case NV3_PTIMER_INTR: ret = nv3->ptimer.interrupt_status; + break; case NV3_PTIMER_INTR_EN: ret = nv3->ptimer.interrupt_enable; + break; case NV3_PTIMER_NUMERATOR: ret = nv3->ptimer.clock_numerator; // 15:0 + break; case NV3_PTIMER_DENOMINATOR: ret = nv3->ptimer.clock_denominator ; //15:0 + break; // 64-bit value // High part case NV3_PTIMER_TIME_0_NSEC: ret = nv3->ptimer.time & 0xFFFFFFFF; //28:0 + break; // Low part case NV3_PTIMER_TIME_1_NSEC: ret = nv3->ptimer.time >> 32; // 31:5 + break; case NV3_PTIMER_ALARM_NSEC: ret = nv3->ptimer.alarm; // 31:5 + break; } + } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index f5e1ee4e8..dc8651fb8 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -74,19 +74,21 @@ uint32_t nv3_pvideo_read(uint32_t address) { case NV3_PVIDEO_INTR: ret = nv3->pvideo.interrupt_status; + break; case NV3_PVIDEO_INTR_EN: ret = nv3->pvideo.interrupt_enable; + break; } } if (reg->friendly_name) - nv_log(": %s (value = 0x%04x)\n", reg->friendly_name, ret); + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); else nv_log("\n"); } else { - nv_log(": Unknown register read (address=0x%04x), returning 0x00\n", address); + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); } return ret; From ef8e4e95c1b0b055e5c9969840de0c91b4b22027 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 18:43:15 +0000 Subject: [PATCH 025/274] actually fire the rivatimer --- src/include/86box/nv/vid_nv.h | 7 +++-- src/include/86box/nv/vid_nv3.h | 6 ++-- src/include/86box/nv/vid_nv_rivatimer.h | 3 +- src/video/nv/nv3/nv3_core.c | 8 +++++- src/video/nv/nv3/subsystems/nv3_pramdac.c | 34 ++++++++++++++++++----- src/video/nv/nv_rivatimer.c | 29 +++++++++++++++++-- 6 files changed, 70 insertions(+), 17 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 9a4a7c55b..0666d8f35 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -28,6 +28,7 @@ #include <86box/timer.h> #include <86box/vid_svga.h> #include <86box/vid_svga_render.h> +#include <86box/nv/vid_nv_rivatimer.h> void nv_log(const char *fmt, ...); @@ -99,10 +100,12 @@ typedef struct nv_base_s nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping double pixel_clock_period; // Period in seconds for pixel clock - pc_timer_t pixel_clock_timer; // Pixel Clock Timer + //pc_timer_t pixel_clock_timer; // Pixel Clock Timer + rivatimer_t* pixel_clock_timer; bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times double memory_clock_period; // Period in seconds for pixel clock - pc_timer_t memory_clock_timer; // Memory Clock Timer + //pc_timer_t memory_clock_timer; // Memory Clock Timer + rivatimer_t* memory_clock_timer; bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times } nv_base_t; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index db9474602..4a93ebddb 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -28,7 +28,7 @@ extern const device_config_t nv3_config[]; #define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start #define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN -#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1000 // The amount by which we have to ration out the memory clock because it's not fast enough... +#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. // Default value for the boot information register. // Depends on the chip @@ -952,8 +952,8 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val); void nv3_pramdac_init(); void nv3_pramdac_set_vram_clock(); void nv3_pramdac_set_pixel_clock(); -void nv3_pramdac_pixel_clock_poll(void* priv); -void nv3_pramdac_memory_clock_poll(void* priv); +void nv3_pramdac_pixel_clock_poll(/*void* priv*/); +void nv3_pramdac_memory_clock_poll(/*void* priv*/); // NV3 PTIMER void nv3_ptimer_init(); diff --git a/src/include/86box/nv/vid_nv_rivatimer.h b/src/include/86box/nv/vid_nv_rivatimer.h index 00e94cd97..31483992e 100644 --- a/src/include/86box/nv/vid_nv_rivatimer.h +++ b/src/include/86box/nv/vid_nv_rivatimer.h @@ -80,4 +80,5 @@ void rivatimer_update_all(); void rivatimer_start(rivatimer_t* rivatimer_ptr); void rivatimer_stop(rivatimer_t* rivatimer_ptr); double rivatimer_get_time(rivatimer_t* rivatimer_ptr); -void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()); \ No newline at end of file +void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()); +void rivatimer_set_period(rivatimer_t* rivatimer_ptr, double period); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index dde1043c4..c7a4407f2 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -350,6 +350,8 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) void nv3_close(void* priv) { + rivatimer_destroy(nv3->nvbase.pixel_clock_timer); + rivatimer_destroy(nv3->nvbase.memory_clock_timer); svga_close(&nv3->nvbase.svga); free(nv3); nv3 = NULL; @@ -839,12 +841,16 @@ void* nv3_init(const device_t *info) nv_log("NV3: Initialising timers...\n"); + /* // These only get turned on when the requisite registers are twiddled timer_add(&nv3->nvbase.pixel_clock_timer, nv3_pramdac_pixel_clock_poll, nv3, false); nv_log("NV3: Pixel clock OK. Will be started when the VBIOS tells us to start\n"); - + timer_add(&nv3->nvbase.memory_clock_timer, nv3_pramdac_memory_clock_poll, nv3, false); nv_log("NV3: Memory clock OK. Will be started when the VBIOS tells us to start\n"); + */ + + return nv3; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index d30900d43..4dabc0a47 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -42,7 +42,6 @@ void nv3_pramdac_init() nv3->pramdac.memory_clock_n = nv3->pramdac.pixel_clock_n = 0xc8; nv3->pramdac.memory_clock_p = nv3->pramdac.pixel_clock_p = 0x0c; - nv3_pramdac_set_pixel_clock(); nv3_pramdac_set_vram_clock(); @@ -51,22 +50,24 @@ void nv3_pramdac_init() // Polls the pixel clock. // This updates the 2D/3D engine PGRAPH -void nv3_pramdac_pixel_clock_poll(void* priv) +void nv3_pramdac_pixel_clock_poll(/*void* priv*/) { + /* nv3_t* nv3_poll = (nv3_t*)priv; timer_on_auto(&nv3_poll->nvbase.pixel_clock_timer, nv3_poll->nvbase.pixel_clock_period); + */ } // Polls the memory clock. -void nv3_pramdac_memory_clock_poll(void* priv) +void nv3_pramdac_memory_clock_poll(/*void* priv*/) { - nv3_t* nv3_poll = (nv3_t*)priv; + //nv3_t* nv3_poll = (nv3_t*)priv; // Let's hope qeeg was right here. nv3_ptimer_tick(); - timer_on_auto(&nv3_poll->nvbase.memory_clock_timer, nv3_poll->nvbase.memory_clock_period); + //timer_on_auto(&nv3_poll->nvbase.memory_clock_timer, nv3_poll->nvbase.memory_clock_period); } // Gets the vram clock register. @@ -118,6 +119,7 @@ void nv3_pramdac_set_vram_clock() if (nv3->pramdac.memory_clock_n == 0) nv3->pramdac.memory_clock_n = 1; + // Convert to microseconds frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box @@ -126,8 +128,16 @@ void nv3_pramdac_set_vram_clock() nv3->nvbase.memory_clock_period = time; - timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period); + //timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period); + // Create and start if it it's not running. + if (!nv3->nvbase.memory_clock_timer) + { + nv3->nvbase.memory_clock_timer = rivatimer_create(time, nv3_pramdac_pixel_clock_poll); + rivatimer_start(nv3->nvbase.memory_clock_timer); + } + + rivatimer_set_period(nv3->nvbase.memory_clock_timer, time); //Breaks everything? //timer_set_delay_u64(&nv3->nvbase.memory_clock_timer, time * TIMER_USEC); // do we need to decrease } @@ -170,7 +180,17 @@ void nv3_pramdac_set_pixel_clock() nv3->nvbase.pixel_clock_period = time; - timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period); + // Create and start if it it's not running. + if (!nv3->nvbase.pixel_clock_timer) + { + nv3->nvbase.pixel_clock_timer = rivatimer_create(time, nv3_pramdac_pixel_clock_poll); + rivatimer_start(nv3->nvbase.pixel_clock_timer); + } + + rivatimer_set_period(nv3->nvbase.pixel_clock_timer, time); + + + //timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period); //Breaks everything? //timer_set_delay_u64(&nv3->nvbase.pixel_clock_timer, time * TIMER_USEC); // do we need to decrease } diff --git a/src/video/nv/nv_rivatimer.c b/src/video/nv/nv_rivatimer.c index 1ccde5a2f..c31ee11fe 100644 --- a/src/video/nv/nv_rivatimer.c +++ b/src/video/nv/nv_rivatimer.c @@ -42,8 +42,15 @@ void rivatimer_init() if (!rivatimer_ptr) return; - while (rivatimer_ptr->next) + while (rivatimer_ptr) + { + // since we are destroing it + rivatimer_t* old_next = rivatimer_ptr->next; rivatimer_destroy(rivatimer_ptr); + + rivatimer_ptr = old_next; + } + #ifdef _WIN32 // Query the performance frequency. @@ -98,10 +105,12 @@ bool rivatimer_really_exists(rivatimer_t* rivatimer) if (!current) return false; - while (current->next != NULL) + while (current) { if (current == rivatimer) return true; + + current = current->next; } return false; @@ -160,10 +169,14 @@ void rivatimer_update_all() if (!rivatimer_ptr) return; - while (rivatimer_ptr->next) + while (rivatimer_ptr) { + // if it's not running skip it if (!rivatimer_ptr->running) + { + rivatimer_ptr = rivatimer_ptr->next; continue; + } #ifdef _WIN32 LARGE_INTEGER current_time; @@ -199,6 +212,8 @@ void rivatimer_update_all() rivatimer_ptr->callback(); } + + rivatimer_ptr = rivatimer_ptr->next; } } @@ -248,4 +263,12 @@ void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()) fatal("rivatimer_set_callback: No callback!"); rivatimer_ptr->callback = callback; +} + +void rivatimer_set_period(rivatimer_t* rivatimer_ptr, double period) +{ + if (!rivatimer_really_exists(rivatimer_ptr)) + fatal("rivatimer_set_period: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + + rivatimer_ptr->period = period; } \ No newline at end of file From fd99d6e71199e4489f12d6cfa0927c9249922afe Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 18:48:31 +0000 Subject: [PATCH 026/274] cleanup legacy code --- src/include/86box/nv/vid_nv.h | 2 -- src/include/86box/nv/vid_nv3.h | 4 ++-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 17 +++-------------- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 0666d8f35..b7450338b 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -100,11 +100,9 @@ typedef struct nv_base_s nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping double pixel_clock_period; // Period in seconds for pixel clock - //pc_timer_t pixel_clock_timer; // Pixel Clock Timer rivatimer_t* pixel_clock_timer; bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times double memory_clock_period; // Period in seconds for pixel clock - //pc_timer_t memory_clock_timer; // Memory Clock Timer rivatimer_t* memory_clock_timer; bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times } nv_base_t; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 4a93ebddb..328d8335e 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -952,8 +952,8 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val); void nv3_pramdac_init(); void nv3_pramdac_set_vram_clock(); void nv3_pramdac_set_pixel_clock(); -void nv3_pramdac_pixel_clock_poll(/*void* priv*/); -void nv3_pramdac_memory_clock_poll(/*void* priv*/); +void nv3_pramdac_pixel_clock_poll(); +void nv3_pramdac_memory_clock_poll(); // NV3 PTIMER void nv3_ptimer_init(); diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 4dabc0a47..2d4b4fbcb 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -50,17 +50,13 @@ void nv3_pramdac_init() // Polls the pixel clock. // This updates the 2D/3D engine PGRAPH -void nv3_pramdac_pixel_clock_poll(/*void* priv*/) +void nv3_pramdac_pixel_clock_poll() { - /* - nv3_t* nv3_poll = (nv3_t*)priv; - - timer_on_auto(&nv3_poll->nvbase.pixel_clock_timer, nv3_poll->nvbase.pixel_clock_period); - */ + // TODO: UPDATE PGRAPH! } // Polls the memory clock. -void nv3_pramdac_memory_clock_poll(/*void* priv*/) +void nv3_pramdac_memory_clock_poll() { //nv3_t* nv3_poll = (nv3_t*)priv; @@ -138,8 +134,6 @@ void nv3_pramdac_set_vram_clock() } rivatimer_set_period(nv3->nvbase.memory_clock_timer, time); - //Breaks everything? - //timer_set_delay_u64(&nv3->nvbase.memory_clock_timer, time * TIMER_USEC); // do we need to decrease } void nv3_pramdac_set_pixel_clock() @@ -188,11 +182,6 @@ void nv3_pramdac_set_pixel_clock() } rivatimer_set_period(nv3->nvbase.pixel_clock_timer, time); - - - //timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period); - //Breaks everything? - //timer_set_delay_u64(&nv3->nvbase.pixel_clock_timer, time * TIMER_USEC); // do we need to decrease } // From caa33123c698110b7614275d4e91a8c95f5e9f5d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 19:29:27 +0000 Subject: [PATCH 027/274] add prmvio --- src/include/86box/nv/vid_nv3.h | 6 +- src/video/nv/nv3/nv3_core.c | 97 +++++++++++++++++++++++- src/video/nv/nv3/nv3_core_arbiter.c | 5 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 11 ++- 4 files changed, 112 insertions(+), 7 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 328d8335e..d185cd408 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -212,8 +212,8 @@ extern const device_config_t nv3_config[]; #define NV3_VGA_VRAM_END 0xBFFFF #define NV3_VGA_START 0xC0000 // VGA Emulation Registers #define NV3_VGA_END 0xC7FFF -#define NV3_PRMVIO_START NV3_VGA_START -#define NV3_PRMVIO_END NV3_VGA_END +#define NV3_PRMVIO_START NV3_VGA_START // VGA stuff written from main GPU +#define NV3_PRMVIO_END 0xC0400 #define NV3_PFB_START 0x100000 // GPU Interface to VRAM #define NV3_PFB_BOOT 0x100000 // Boot registration #define NV3_PFB_BOOT_RAM_AMOUNT 0 // The amount of ram @@ -342,11 +342,13 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_PLANE_MASK 0x400628 #define NV3_PGRAPH_CHROMA_KEY 0x40062C #define NV3_PGRAPH_BETA 0x400640 // Beta factor (30:23 fractional, 22:0 before fraction) +#define NV3_PGRAPH_DMA 0x400680 #define NV3_PGRAPH_NOTIFY 0x400684 // Notifier for PGRAPH #define NV3_PGRAPH_CLIP0_MIN 0x400690 // Clip for Blitting 0 Min #define NV3_PGRAPH_CLIP0_MAX 0x400694 // Clip for Blitting 0 Max #define NV3_PGRAPH_CLIP1_MIN 0x400698 // Clip for Blitting 1 Min #define NV3_PGRAPH_CLIP1_MAX 0x40069C // Clip for Blitting 1 Max +#define NV3_PGRAPH_CLIP_MISC 0x4006A0 // Regions/Render/Complex mode #define NV3_PGRAPH_FIFO_ACCESS 0x4006A4 // Is PGRAPH enabled? #define NV3_PGRAPH_FIFO_ACCESS_DISABLED 0x0 #define NV3_PGRAPH_FIFO_ACCESS_ENABLED 0x1 diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index c7a4407f2..77abd7a00 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -46,27 +46,92 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); // Read 8-bit MMIO uint8_t nv3_mmio_read8(uint32_t addr, void* priv) { + uint32_t ret = 0x00; + + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + addr &= 0xFFFFFF; + + if (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + ret = nv3_svga_in(real_address, nv3); + + return ret; + } + // see if unaligned reads are a problem - uint32_t ret = nv3_mmio_read32(addr, priv); + ret = nv3_mmio_read32(addr, priv); return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFF); } // Read 16-bit MMIO uint16_t nv3_mmio_read16(uint32_t addr, void* priv) { - uint32_t ret = nv3_mmio_read32(addr, priv); + uint32_t ret = 0x00; + + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + addr &= 0xFFFFFF; + + if (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + ret = nv3_svga_in(real_address, nv3) + | (nv3_svga_in(real_address + 1, nv3) << 8); + + return ret; + } + + ret = nv3_mmio_read32(addr, priv); return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFFFF); } // Read 32-bit MMIO uint32_t nv3_mmio_read32(uint32_t addr, void* priv) { + uint32_t ret = 0x00; + + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + addr &= 0xFFFFFF; + + if (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + ret = nv3_svga_in(real_address, nv3) + | (nv3_svga_in(real_address + 1, nv3) << 8) + | (nv3_svga_in(real_address + 2, nv3) << 16) + | (nv3_svga_in(real_address + 3, nv3) << 24); + + return ret; + } + + return nv3_mmio_arbitrate_read(addr); } // Write 8-bit MMIO void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) { + // This is weitek vga stuff + if (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + nv3_svga_out(real_address, val & 0xFF, nv3); + + return; + } + // overwrite first 8bits of a 32 bit value uint32_t new_val = nv3_mmio_read32(addr, NULL); @@ -79,6 +144,19 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // Write 16-bit MMIO void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) { + // This is weitek vga stuff + if (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + nv3_svga_out(real_address, val & 0xFF, nv3); + nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); + + return; + } + // overwrite first 16bits of a 32 bit value uint32_t new_val = nv3_mmio_read32(addr, NULL); @@ -91,6 +169,21 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // Write 32-bit MMIO void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) { + // This is weitek vga stuff + if (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + nv3_svga_out(real_address, val & 0xFF, nv3); + nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); + nv3_svga_out(real_address + 2, (val >> 16) & 0xFF, nv3); + nv3_svga_out(real_address + 3, (val >> 24) & 0xFF, nv3); + + return; + } + nv3_mmio_arbitrate_write(addr, val); } diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index e74e6a93d..ee8fe048d 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -57,7 +57,7 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) return 0x00; uint32_t ret = 0x00; - + // note: some registers are byte aligned not dword aligned // only very few are though, so they can be handled specially, using the register list most likely address &= 0xFFFFFC; @@ -120,6 +120,9 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) if (!nv3) return; + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + address &= 0xFFFFFF; + // note: some registers are byte aligned not dword aligned // only very few are though, so they can be handled specially, using the register list most likely address &= 0xFFFFFC; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index d7b7bfb01..9dfca4f00 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -43,6 +43,10 @@ void nv3_pgraph_init() // nv_register_t pgraph_registers[] = { + { NV3_PGRAPH_DEBUG_0, "PGRAPH Debug 0", NULL, NULL }, + { NV3_PGRAPH_DEBUG_1, "PGRAPH Debug 1", NULL, NULL }, + { NV3_PGRAPH_DEBUG_2, "PGRAPH Debug 2", NULL, NULL }, + { NV3_PGRAPH_DEBUG_3, "PGRAPH Debug 3", NULL, NULL }, { NV3_PGRAPH_INTR_0, "PGRAPH Interrupt Status 0", NULL, NULL }, { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL }, { NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL }, @@ -69,7 +73,10 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_ROP3, "PGRAPH Render Operation ROP3 (2^3 bits = 256 possible operations)", NULL, NULL}, { NV3_PGRAPH_PLANE_MASK, "PGRAPH Current Plane Mask (7:0)", NULL, NULL}, { NV3_PGRAPH_CHROMA_KEY, "PGRAPH Chroma Key (17:0) (Bit 30 = Alpha, 29:20 = Red, 19:10 = Green, 9:0 = Blue)", NULL, NULL}, - { NV3_PGRAPH_NOTIFY, "PGRAPH Notifier (Wip...)", NULL, NULL}, + { NV3_PGRAPH_BETA, "PGRAPH Beta factor", NULL, NULL }, + { NV3_PGRAPH_DMA, "PGRAPH DMA", NULL, NULL }, + { NV3_PGRAPH_CLIP_MISC, "PGRAPH Clipping Miscellaneous Settings", NULL, NULL }, + { NV3_PGRAPH_NOTIFY, "PGRAPH Notifier (Wip...)", NULL, NULL }, { NV3_PGRAPH_CLIP0_MIN, "PGRAPH Clip0 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, { NV3_PGRAPH_CLIP0_MAX, "PGRAPH Clip0 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, { NV3_PGRAPH_CLIP1_MIN, "PGRAPH Clip1 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, @@ -164,7 +171,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); - nv_log("NV3: pgraph Write 0x%08x -> 0x%08x\n", value, address); + nv_log("NV3: PGRAPH Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) From 56a5522aa61325d2f6b15280302deae34eea5629 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 29 Dec 2024 19:37:19 +0000 Subject: [PATCH 028/274] fix ptimer --- src/video/nv/nv3/nv3_core.c | 11 ----------- src/video/nv/nv3/subsystems/nv3_pramdac.c | 4 +--- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 77abd7a00..0636a3c91 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -934,17 +934,6 @@ void* nv3_init(const device_t *info) nv_log("NV3: Initialising timers...\n"); - /* - // These only get turned on when the requisite registers are twiddled - timer_add(&nv3->nvbase.pixel_clock_timer, nv3_pramdac_pixel_clock_poll, nv3, false); - nv_log("NV3: Pixel clock OK. Will be started when the VBIOS tells us to start\n"); - - timer_add(&nv3->nvbase.memory_clock_timer, nv3_pramdac_memory_clock_poll, nv3, false); - nv_log("NV3: Memory clock OK. Will be started when the VBIOS tells us to start\n"); - */ - - - return nv3; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 2d4b4fbcb..0c57b71cb 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -62,8 +62,6 @@ void nv3_pramdac_memory_clock_poll() // Let's hope qeeg was right here. nv3_ptimer_tick(); - - //timer_on_auto(&nv3_poll->nvbase.memory_clock_timer, nv3_poll->nvbase.memory_clock_period); } // Gets the vram clock register. @@ -129,7 +127,7 @@ void nv3_pramdac_set_vram_clock() // Create and start if it it's not running. if (!nv3->nvbase.memory_clock_timer) { - nv3->nvbase.memory_clock_timer = rivatimer_create(time, nv3_pramdac_pixel_clock_poll); + nv3->nvbase.memory_clock_timer = rivatimer_create(time, nv3_pramdac_memory_clock_poll); rivatimer_start(nv3->nvbase.memory_clock_timer); } From bdc47bf3eef66ede54d7e6b1d33ea2ad914a477d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 00:38:06 +0000 Subject: [PATCH 029/274] start working on the actual graphics objects. Since we figured out the pfifo/ramht/object class crap. --- doc/Memory map (RIVA 128).txt | 81 +++++++++ doc/PFIFO RAMHT RAMRO.txt | 38 +++++ doc/nv3 driver init status.txt | 1 + doc/nv3_object_classes.txt | 37 ++++ doc/nv3_object_classes_driver.txt | 57 +++++++ doc/nv3d3d_t.txt | 161 ++++++++++++++++++ .../86box/nv/classes/vid_nv3_classes.h | 66 +++++++ src/include/86box/nv/vid_nv.h | 21 ++- src/include/86box/nv/vid_nv3.h | 70 +++++++- src/video/CMakeLists.txt | 2 + src/video/nv/nv3/classes/nv3_class_names.c | 63 +++++++ src/video/nv/nv3/nv3_core.c | 1 - src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 1 + src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 10 ++ 15 files changed, 591 insertions(+), 20 deletions(-) create mode 100644 doc/Memory map (RIVA 128).txt create mode 100644 doc/PFIFO RAMHT RAMRO.txt create mode 100644 doc/nv3_object_classes.txt create mode 100644 doc/nv3_object_classes_driver.txt create mode 100644 doc/nv3d3d_t.txt create mode 100644 src/include/86box/nv/classes/vid_nv3_classes.h create mode 100644 src/video/nv/nv3/classes/nv3_class_names.c diff --git a/doc/Memory map (RIVA 128).txt b/doc/Memory map (RIVA 128).txt new file mode 100644 index 000000000..fbfe9074f --- /dev/null +++ b/doc/Memory map (RIVA 128).txt @@ -0,0 +1,81 @@ +Memory map (RIVA 128) + +32 megabytes of MMIO starting at 0x0000000-0x01FFFFFF + +MC (Master Control) 0x00000000-0x00000FFF + Config/Boot 0x00000000-0x000000FF + Master Config 0x00000100-0x00000FFF + Also used to define DMA channel IDs? + +MPU-401 I/O 0x00000330-0x00000331 Probably NV1 leftover, NV1 has mpu401 emulation -- no audio in nv3 +VGA emulated ports 0x000003B0-0x000003DF Emulated I/O ports for VGA + +Bus Control (PBUS) 0x00001000-0x00001FFF +FIFO (PFIFO) 0x00002000-0x00003FFF Submit starting at 0x00800000. Used to configure RAMHT,RAMFC,RAMRO structures & cache + +PRM 0x00004000-0x00005FFF Realmode DOS device support + +PRMIO 0x00007000-0x00007FFF Realmode access to PCI BAR (Base Address Register) + PCI I/O +PTIMER 0x00009000-0x00009FFF Timer + +VGA emulation 0x0000A000-0x0000BFFF + +VGA vram emulation 0x000A0000-0x000BFFFF (PRMVGA) +VGA 0x000C0000-0x000C7FFF VGA sequencer + graph controller registers (PRMVIO) + +(All of this up to 0x0000FFFF can be traced) + +PFB (Framebuffer) 0x00100000-0x00100FFF Interface to vram +PEXTDEV 0x00101000-0x00101FFF External device interface - contains straps + Straps 0x00101000 11 bits of cfg + +ROM (VBIOS?) 0x00110000-0x0011FFFF +PALT (?) 0x00120000-0x00120FFF + +PEXTDEV 0x00101000-0x00101FFF External Devices + +Media Engine (PME) 0x00200000-0x00200FFF Allows for external video capture according to envytools? + +PGRAPH (3D rendering) 0x00400000-0x00401FFF + +PGRAPH objects (using RAMHT???) +*i assume that when you submit an object these are the registers used to actually draw the current object + +Beta blending factor 0x00410000-0x00411FFF +ROP 0x00420000-0x00421FFF Global bitwise operation (Render OPeration) for filtering the final pixel +Color Key 0x00430000-0x00431FFF +Plane Switch 0x00440000-0x00441FFF Something to do with color formats and objects? +Clipping 0x00450000-0x00451FFF +Blend Pattern 0x00460000-0x00461FFF Used for specific blending modes +Quad [OBSOLETE] 0x00470000-0x00471FFF A rectangle. NV1 LEFTOVER, OBSOLETE +Point 0x00480000-0x00481FFF A single point +Line 0x00490000-0x00491FFF A line (with an optional colour). Can also draw a polygon made out of lines - polyline +Lin 0x004A0000-0x004A1FFF A line, without starting or ending pixel (with an optional colour). Can also draw a "polylin" +Triangle [OBSOLETE] 0x004B0000-0x004B1FFF A triangle. NV1 LEFTOVER, OBSOLETE? +Win95 GDI text 0x004C0000-0x004C1FFF Win95 text acceleration +Memory to memory xfer 0x004D0000-0x004D1FFF Represents a memory to memory transfer +Scaled image from vram 0x004E0000-0x004E1FFF Scaled image from GPU VRAM +Image blit from vram 0x00500000-0x00501FFF Image from GPU VRAM +Image blit from cpu 0x00510000-0x00511FFF Image from CPU +Bitmap from cpu 0x00520000-0x00521FFF Bitmap from CPU +Image to memory 0x00540000-0x00541FFF Image to GPU VRAM +Stretch image from cpu 0x00550000-0x00551FFF Stretched image from CPU +Direct3D 5.0 triangle 0x00570000-0x00571FFF A triangle optimised explicitly for directx3/directx5 rendering - supercedes UTRI +PointZ 0x00580000-0x00581FFF A single point with "zeta factor" (not sure what this is yet) +Image in memory 0x005C0000-0x005C0FFF Image in vram(?) + +PVIDEO (Video Control) 0x00680000-0x006802FF +External DAC 0x00680000-0x006800FF + +PRMCIO 0x00601000-0x00601FFF VGA emulation - CRTC + attribute controller + +PRAMDAC 0x00680300-0x00680FFF (used for color lookup tables, hardware cursor, video overlay, PLL for clocking and pixel generation) +"USER" DAC 0x00681200-0x00681FFF + +DMA submission w/FIFO 0x00800000-0x00FFFFFF NV_USER - uses FIFO buffer + +PNVM / PDFB / VRAM 0x01000000-0x017FFFFF (actual VRAM amount depends on card, but max is 8MB) + +RAMIN 0x01C00000-0x01FFFFFF (note that this is actually mapped in the last 1mb of vram) + +contains ramht that has obj parameters for submission, configurable \ No newline at end of file diff --git a/doc/PFIFO RAMHT RAMRO.txt b/doc/PFIFO RAMHT RAMRO.txt new file mode 100644 index 000000000..9b4c94718 --- /dev/null +++ b/doc/PFIFO RAMHT RAMRO.txt @@ -0,0 +1,38 @@ +PIO VS dma + +driver is DIRECTLY modifying pfifo + +8X8 channel setup + +Names are 32-bit integers >4096 + +RAMFC - DMA Context object 0,0 to 8,8 + +context = channel, render object, object type, offset in instance memory + +for a rectangle (type 0x47), object render = 1, channel 0, at 0x0400 in the ramht memory + +=0x00c70400 as the context + +the ramht hash : + +xor every byte of the hash individually and then xor that with the channel number + +so obj id 01020304 in channel 0 is 1 xor 2 xor 3 xor 4 xor 0 + +Store in RAMHT at + 4*16 = name +Store in RAMHT at + 4*16 + 4 = context + +then the ramin stuff starts at *0xc04000 since c00000 is the start of ramin [PCI BAR1] which is where you put the contents of the class struct + +nv_user + +Consider the 8x8 channels as 64 subchannels. +Now you can do: + +They seem to end at 0x880000 + +(0x880000)/64 = 0x2000 for each channel + +FAILURE -> RAMRO! + diff --git a/doc/nv3 driver init status.txt b/doc/nv3 driver init status.txt index 6ac794588..025e781a2 100644 --- a/doc/nv3 driver init status.txt +++ b/doc/nv3 driver init status.txt @@ -105,3 +105,4 @@ NvFindAdapter -> RmInitNvMapping Success 19:18 26/11/2024 NvFindAdapter -> RmPostNvDevice Success 17:32 27/11/2024 NvFindAdapter -> NVGetNVInfo Success 17:32 27/11/2024 NvFindAdapter -> NVMapFrameBuffer Success 17:32 27/11/2024 + diff --git a/doc/nv3_object_classes.txt b/doc/nv3_object_classes.txt new file mode 100644 index 000000000..3cb99882b --- /dev/null +++ b/doc/nv3_object_classes.txt @@ -0,0 +1,37 @@ +Object classes as understood by the GPU. + +(May be represented, in RAMFC, as 0x40+ 22:16) + +0x00 = Invalid +0x01 = beta factor +0x02 = ROP5 operation +0x03 = Chroma key +0x04 = Plane mask +0x05 = Clipping rectangle +0x06 = Pattern +0x07 = Rectangle +0x08 = Point +0x09 = Line +0x0A = Lin (line without starting or ending pixel) +0x0B = Triangle +0x0C = Windows 95 GDI text acceleration +0x0D = Memory to memory format +0x0E = Scaled image from memory +0x0F = INVALID +0x10 = Blit +0x11 = Image +0x12 = Bitmap +0x13 = INVALID +0x14 = Transfer to Memory +0x15 = Stretched image from CPU +0x16 = INVALID +0x17 = Direct3D 5.0 accelerated textured triangle w/zeta buffer +0x18 = INVALID +0x19 = INVALID +0x1A = INVALID +0x1B = INVALID +0x1C = Image in memory +0x1D = INVALID +0x1E = INVALID +0x1F = INVALID + \ No newline at end of file diff --git a/doc/nv3_object_classes_driver.txt b/doc/nv3_object_classes_driver.txt new file mode 100644 index 000000000..83b421335 --- /dev/null +++ b/doc/nv3_object_classes_driver.txt @@ -0,0 +1,57 @@ +Object classes + +NOT represented by the GPU. These are the ones the drivers recognise. Most of them are faked. + +Version 0.77_win95 (!!!) + +object class 1 = "general" methods shared across all objects +object class 2 = DMA from memory +object class 3 = DMA to memory +object class 4 = timer +object class 5 = chip ID +object class 6 = "context ordinal" +object class 10/0Ah = patchcord (links objects together) +object class 11/0Bh = video sink +object class 12/0Ch = video switch +object class 13/0Dh = video colormap +object class 14/0Eh = patchcord...again +object class 15/0Fh = image to video +object class 16/10h = image stencil buffer +object class 17/11h = image blending methods +object class 18/12h = beta solid +object class 19/13h = image -> render operation +object class 20/14h = ROP5 (2^5 = 32bit rop) +object class 21/15h = color key +object class 22/16h = plane switch +object class 23/17h = "solid image" +object class 24/18h = pattern +object class 25/19h = black rectangle +object class 26/1Ah = solid point +object class 27/1Bh = solid line +object class 28/1Ch = solid lin (line without its ending or starting pixel) +object class 29/1Dh = triangle +object class 30/1Eh = solid rectangle +object class 31/1Fh = blit image +object class 33/21h = get image from cpu +object class 34/22h = get image from cpu, monochrome +object class 37/25h = get image from local GPU memory +object class 49/31h and 51/33h = patchcord, again +object class 54/36h = get image from cpu, stretched +object class 55/37h = get image from vram, scaled +object class 56/38h = get image from vram, scaled, YUV 420 color space (probably internal colour space used for rendering) +object class 57/39h = convert image(?) between formats in place in vram, allows you to set an in and out buffer and all that jazz +object class 61/3Dh = In-Memory DMA (vram to vram?) +object class 62/3Eh = get image from vram +object class 63/3Fh = get video from vram +object class 64/40h = video scaler +object class 65/41h = video color key (as opposed to image) +object class 66/42h = capture video to memory +object class 67/43h = Solid ROP5 +object class 68/44h = zeta buffer (something to do with how the gpu internally renders 3d stuff) from CPU(?) +object class 69/45h = zeta buffer in VRAM +object class 70/46h = zeta buffer patchcord +object class 71/47h = render solid point into zeta buffer (Also rectangle0 +object class 72/48h = render Direct3D 5.x ("D3D0") accelerated triangle into zeta buffer +object class 73/49h = render Direct3D 5.x ("D3D0") accelerated triangle +object class 74/4Ah = video source +object class 75/4Bh = render Windows GDI accelerated rectangle and text \ No newline at end of file diff --git a/doc/nv3d3d_t.txt b/doc/nv3d3d_t.txt new file mode 100644 index 000000000..c8579fd6c --- /dev/null +++ b/doc/nv3d3d_t.txt @@ -0,0 +1,161 @@ +12=unk_int12 +16=unk_short16 +22=unk_short22 (seems to determine if nv_sys_ptr is valid) +24=unk_short24 +26=unk_short26 +44=unk_int44 +56=unk_int56 +60=unk_int60 +64=unk_short64 +66=unk_short66 + +82=unk_short82 + +362..822: + big_struct + (weird alignment?) + 477 + 489 + 505 + +1140=nv_sys_ptr + + +1156=unk_int1156 [start of structure] +1160=unk_int1160 + +1168=unk_int1168 [possibly a byte array of up to 16 bytes) + +1184=unk_int1184 + +1208=unk_int1208 +1212=unk_int1212 +1216=unk_int1216 +1220=unk_int1220 +1224=unk_int1224 + +1236=unk_int1236 +1240=unk_int1240 +1244=unk_int1244 +1248=unk_int1248 + +1256=unk_int1256 +1260=fog_table_enable +1264=unk_int1264 +1270=unk_int1270 +1272=unk_byte1272 +1273=unk_byte1273 +1274=unk_byte1274 (?) +1275=unk_byte1275 + +1316=unk_int1316 +1320=unk_int1320 + +1332=unk_int1332 + +1340=unk_int1340 +1344=unk_int1344 + +1356=unk_int1356 +1360=d3d_clear_enabled +1364=texture_enabled +1368=mipmap_size_max +1372=mipmap_levels +1376=user_mipmaps +1380=zoh_mode (bool) +1384=tex_heap +1388=text_size +1392=video_texture +1396=min_video_tex_size +1400=draw_prim +1404=spread_x +1408=spread_y +1412=size_adj +1416=turbo_adj +1420=dma_min_push_count +1424=dma_push_enable + +1436=unk_int1436 +1440=unk_int1440 + +1448=unk_int1448 +1452=unk_int1452 (set to value of unk_int1908) +1456=unk_int1456 (set to value of unk_int1956) +1460=unk_int1460 (set to value of unk_int2020) + +1516=unk_int1516 +1520=unk_int1520 +1524=unk_int1524 +1528=unk_int1528 +1532=unk_int1532 + +1548=unk_int1548 +1552=unk_int1552 +1556=unk_int1556 +1560=unk_int1560 +1564=unk_int1564 + +1600=unk_int1600 + +1612=unk_int1612 +1616=unk_int1616 +1620=unk_int1620 + +1632=unk_int1632 + +1640=unk_int1640 +1644=unk_ptr1644 + +1676=unk_int1676 +1680=unk_int1680 +1684=unk_int1684 +1688=unk_int1688 +1692=unk_int1692 +1696=unk_int1696 +1700=unk_int1700 + +1716=unk_int1716 +1720=unk_int1720 +1724=unk_int1724 +1728=unk_ptr1728 + +1848=unk_int1848 +1852=unk_int1852 +1856=unk_int1856 (unk_int1552 | 0x800) +1864=unk_func_ptr1864 +1868=unk_int1868 + +1884=unk_int1884 +1888=ptr_to_start_of_structure? +1892=hInstDll +1896=unk_int1896 +1900=unk_int1900 + +1908=unk_int1908 +1912=unk_int1912 +1916=unk_func_ptr1916 +1920=unk_func_ptr1920 + +1932=unk_func_ptr1932 +1936=unk_func_ptr1936 +1944=unk_func_ptr1944 + +1956..2020: Set of function pointrs + 1956=unk_int1956 + 1960=unk_int1960 + 1960=unk_func_ptr1960 + 1964=unk_func_ptr1964 + 1968=unk_func_ptr1968 + 1976=unk_func_ptr1976 + 1980=unk_func_ptr1980 + 1988=unk_func_ptr1988 + 1996=unk_func_ptr1996 + 2000=unk_func_ptr2000 + 2004=unk_func_ptr2004 + 2008=unk_func_ptr2008 + + 2020=unk_int2020 + +2024=unk_int2024 +2028=unk_int2028 +2032=unk_int2032 diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h new file mode 100644 index 000000000..e47b5eb71 --- /dev/null +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -0,0 +1,66 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Defines graphics objects for Nvidia NV3 architecture-based GPU (RIVA 128/RIVA 128 ZX), + * as well as for later GPUs if they use the same objects. + * + * + * + * Authors: Connor Hyde + * + * Copyright 2024-2025 Connor Hyde + */ + +#pragma once +#include +#include +#include +#include + +/* + Note: These uint32_ts are basically object methods that are being submitted + They have different names so the user can use them more easily but different versions of the same class can be distinguished + + ALL of these structures HAVE to be a size of exactly 0x2000 bytes because that's what the hashtable expects. + + Also, these class IDs don't relate to the internal architecture of the GPU. + Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of + classes recognised by the driver. + + The 3-bit DMA SUBCHANNEL is combined with a 4-bit CLASS ID to get the REAL CLASS ID. There are 32 CLASSES per subchannel and 8 SUBCHANNELS. + + This is why the Class IDs you see here are not the same as you may see in other places. +*/ + +extern const char* nv3_class_names[]; + +/* +Object Class 0x07 (real hardware) + 0x1E (drivers) +Also 0x47 in context IDs +A rectangle. Wahey! +*/ +typedef struct nv_object_class_007 +{ + uint8_t reserved[0xFF]; // Required for NV_CLASS Core Functionality + uint32_t set_notify_ctx_dma; // Set notifier context for DMA + uint32_t set_notify; // Set notifier + uint32_t set_image_output; // Set the image output type + uint8_t reserved2[0xF5]; // up to 0x200 + uint32_t set_zeta_output; // Zeta buffer input + uint32_t set_zeta_input; // Zeta buffer input + uint32_t set_color_format; // Color format: 0x100000=15bpp. + uint8_t reserved3[0xF5]; // up to 0x300 + + /* THESE ARE ALL THE SAME METHOD */ + uint32_t color_zeta32; // 32-bit zeta buffer color (?) + uint32_t point; // Draw a point i guess + uint8_t reserved4[0x4F3]; // up to 0x7fc + uint32_t control_out; // 7fd-7ff + uint8_t reserved5[0x1800]; // up to 0x2000 +} nv3_rectangle_t; diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index b7450338b..39e9a68d0 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -6,20 +6,23 @@ * * This file is part of the 86Box distribution. * - * JENSEN HUANG APPROVED !!!! + * Shared implementation file for all NVIDIA GPUs (hopefully to be) emulated by 86box. * * Credit to: * - * - fuel (PCBox developer) - * - Marcelina Kościelnicka (envytools) - * - nouveau developers - * - Utah GLX developers - * - XFree86 developers - * - xemu developers - * + * - Marcelina Kościelnicka (envytools) https://envytools.readthedocs.io/en/latest/ + * - fuel (PCBox developer) https://github.com/PCBox/PCBox + * - nouveau developers https://nouveau.freedesktop.org/ + * - Utah GLX developers https://utah-glx.sourceforge.net/ + * - XFree86 developers https://www.xfree86.org/ + * - xemu developers https://github.com/xemu-project/xemu + * - RivaTV developers https://rivatv.sourceforge.net (esp. https://rivatv.sourceforge.net/stuff/riva128.txt) + * - Nvidia for leaking their driver symbols numerous times ;^) https://nvidia.com + * - People who prevented me from giving up (various) + * * Authors: Connor Hyde / starfrost * - * Copyright 2024 Connor Hyde + * Copyright 2024-2025 Connor Hyde */ #ifdef EMU_DEVICE_H // what diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index d185cd408..b17423305 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -12,11 +12,11 @@ * * Authors: Connor Hyde * - * Copyright 2024 Connor Hyde + * Copyright 2024-2025 Connor Hyde */ // vid_nv3.h: NV3 Architecture Hardware Reference (open-source) -// Last updated 2 December 2024 +// Last updated 30 December 2024 // The GPU base structure extern const device_config_t nv3_config[]; @@ -28,13 +28,20 @@ extern const device_config_t nv3_config[]; #define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start #define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN +// DMA channels are basically the number of contexts that the gpu can deal with at once. +// Channel 0 is always taken up by NV drivers. + +// Subchannels deal with specific parts of the GPU and are manipulated by the driver to manipulate the gpu. +#define NV3_DMA_CHANNELS 8 +#define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8 + #define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. // Default value for the boot information register. // Depends on the chip -#define NV3_BOOT_REG_REV_A00 0x00030100 -#define NV3_BOOT_REG_REV_B00 0x00030110 -#define NV3_BOOT_REG_REV_C00 0x00030120 +#define NV3_BOOT_REG_REV_A00 0x00030100 +#define NV3_BOOT_REG_REV_B00 0x00030110 +#define NV3_BOOT_REG_REV_C00 0x00030120 // various vbioses for testing // Coming soon: MIROmagic Premium BIOS (when I get mine dumped) @@ -297,9 +304,9 @@ extern const device_config_t nv3_config[]; #define NV3_PSTRAPS_OVERWRITE_ENABLED 0x1 #define NV3_PEXTDEV_END 0x101FFF #define NV3_PROM_START 0x110000 // VBIOS? -#define NV3_PROM_END 0x110FFF +#define NV3_PROM_END 0x11FFFF #define NV3_PALT_START 0x120000 // ??? but it exists -#define NV3_PALT_END 0x120FFF +#define NV3_PALT_END 0x12FFFF #define NV3_PME_START 0x200000 // Mediaport #define NV3_PME_INTR 0x200100 // Mediaport: Interrupt Pending? #define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable @@ -459,7 +466,7 @@ extern const device_config_t nv3_config[]; #define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC -#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO +#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?) #define NV3_USER_END 0xFFFFFF // easier name @@ -478,6 +485,8 @@ extern const device_config_t nv3_config[]; // these all have configurable sizes, define them here #define NV3_PRAMIN_START 0x1C00000 + + #define NV3_PRAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects #define NV3_PRAMIN_RAMHT_END 0x1C00FFF #define NV3_PRAMIN_RAMHT_SIZE_0 0xFFF @@ -651,8 +660,15 @@ typedef struct nv_pfifo_s { uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable + uint32_t ramht_config; // RAMHT config + uint32_t ramfc_config; // RAMFC config + uint32_t ramro_config; // RAMRO config + uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? + } nv3_pfifo_t; +// create_object(uint32_t type) here + // RAMDAC typedef struct nv3_pramdac_s { @@ -761,12 +777,48 @@ typedef struct nv3_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; +typedef struct nv3_pramin_name_s +{ + union + { + uint32_t name; + uint8_t byte_high; + uint8_t byte_mid2; + uint8_t byte_mid1; + uint8_t byte_low; + }; +} nv3_pramin_name_t; + +typedef struct nv3_pramin_context_s +{ + union + { + uint32_t context; + uint8_t dma_channel; + uint8_t render_object; //0=sw, 1=render + uint8_t class_id; + uint8_t ramin_offset; //find + }; +} nv3_pramin_context_t; + +// Graphics object hashtable for specific DMA [channel, subchannel] pair +typedef struct nv3_pramin_ramht_subchannel_s +{ + nv3_pramin_name_t name; // must be >4096 + + // Contextual information. + // See the above union. + nv3_pramin_context_t context; +} nv3_pramin_ramht_subchannel_t; + // Graphics object hashtable typedef struct nv3_pramin_ramht_s { - + nv3_pramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; } nv3_pramin_ramht_t; +uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel); + // Anti-fuckup device typedef struct nv3_pramin_ramro_s { diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 4b927c9ea..b99f4fc4b 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -41,6 +41,8 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c nv/nv3/subsystems/nv3_ptimer.c nv/nv3/subsystems/nv3_pramin.c nv/nv3/subsystems/nv3_pramin_ramht.c nv/nv3/subsystems/nv3_pramin_ramfc.c nv/nv3/subsystems/nv3_pramin_ramro.c nv/nv3/subsystems/nv3_pvideo.c + + nv/nv3/classes/nv3_class_names.c ) if(G100) diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c new file mode 100644 index 000000000..48b85cab4 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -0,0 +1,63 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Defines core class names for debugging purposes + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ + +/* Taken from Win9x drivers 0.77, these had the best reversing potential */ + +#include <86Box/nv/classes/vid_nv3_classes.h> + + +/* These are the object classes AS RECOGNISED BY THE GRAPHICS HARDWARE. */ +/* The drivers implement a COMPLETELY DIFFERENT SET OF CLASSES. */ + +/* THERE CAN ONLY BE 32 CLASSES IN NV3 BECAUSE THE CLASS ID PART OF THE CONTEXT OF A GRAPHICS OBJECT IN PFIFO RAM HASH TABLE IS ONLY 5 BITS LONG! */ + +const char* nv3_class_names[] = +{ + "NV3 INVALID class 0x00", + "NV3 class 0x01: Beta factor", + "NV3 class 0x02: ROP5 (32-bit) operation", + "NV3 class 0x03: Chroma key", + "NV3 class 0x04: Plane mask", + "NV3 class 0x05: Clipping rectangle", + "NV3 class 0x06: Pattern", + "NV3 class 0x07: Rectangle", + "NV3 class 0x08: Point", + "NV3 class 0x09: Line", + "NV3 class 0x0A: Lin (line without starting or ending pixel)", + "NV3 class 0x0B: Triangle", + "NV3 class 0x0C: Windows 95 GDI text acceleration", + "NV3 class 0x0D: Memory to memory format", + "NV3 class 0x0E: Scaled image from memory", + "NV3 INVALID class 0x0F", + "NV3 class 0x10: Blit", + "NV3 class 0x11: Image", + "NV3 class 0x12: Bitmap", + "NV3 INVALID class 0x13", + "NV3 class 0x14: Transfer to Memory", + "NV3 class 0x15: Stretched image from CPU", + "NV3 INVALID class 0x16", + "NV3 class 0x17: Direct3D 5.0 accelerated textured triangle w/zeta buffer", + "NV3 INVALID class 0x18", + "NV3 INVALID class 0x19", + "NV3 INVALID class 0x1A", + "NV3 INVALID class 0x1B", + "NV3 class 0x1C: Image in Memory", + "NV3 INVALID class 0x1D", + "NV3 INVALID class 0x1E", + "NV3 INVALID class 0x1F", + +}; diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 0636a3c91..e736e0c79 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -614,7 +614,6 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) uint8_t old_value; // todo: - // RMA // Pixel formats (8bit vs 555 vs 565) // VBE 3.0? diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 1ce59171a..57d19fc42 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -28,3 +28,4 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +/* Nvidia DMA Engine */ \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 7448f77c7..08a2b48ff 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -115,7 +115,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) // Write 16-bit ramin void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) { - addr &= (nv3->nvbase.svga.vram_max- 1); + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line svga_t* svga = &nv3->nvbase.svga; diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index 7f80a1035..b77f18729 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -28,3 +28,13 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +/* This implements the hash that all the objects are stored within. +It is used to get the offset within RAMHT of a graphics object. + */ + +uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel) +{ + uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel); + nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)", name, channel); + return hash; +} \ No newline at end of file From 54bafba20cefaaeb878eda5f165dcb4559302a18 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 16:14:52 +0000 Subject: [PATCH 030/274] Suppress logging of ptimer time unless it changes to massively reduce logspam --- src/video/nv/nv3/subsystems/nv3_ptimer.c | 29 +++++++++++++++++++----- 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 7e718264a..c0d68a24c 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -69,12 +69,19 @@ void nv3_ptimer_tick() // to the state. double current_time = ((double)nv3->ptimer.clock_numerator * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)nv3->ptimer.clock_denominator; // *10.0? + // Logging is suppressed when reading this register because it is read many times + // So we only log when we update. + // truncate it nv3->ptimer.time += (uint64_t)current_time; + + nv_log("PTIMER time ticked (The value is now 0x%08x)\n", nv3->ptimer.time); + // Check if the alarm has actually triggered... if (nv3->ptimer.time >= nv3->ptimer.alarm) { + nv_log("PTIMER alarm interrupt fired because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM); } } @@ -85,7 +92,13 @@ uint32_t nv3_ptimer_read(uint32_t address) nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - nv_log("NV3: PTIMER Read from 0x%08x", address); + // Only log these when tehy actually tick + if (address != NV3_PTIMER_TIME_0_NSEC + && address != NV3_PTIMER_TIME_1_NSEC) + { + nv_log("NV3: PTIMER Read from 0x%08x", address); + } + uint32_t ret = 0x00; @@ -129,11 +142,15 @@ uint32_t nv3_ptimer_read(uint32_t address) } } - - if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); - else - nv_log("\n"); + //TIME0 and TIME1 produce too much log spam that slows everything down + if (reg->address != NV3_PTIMER_TIME_0_NSEC + && reg->address != NV3_PTIMER_TIME_1_NSEC) + { + if (reg->friendly_name) + nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + else + nv_log("\n"); + } } else { From 713ef4585b362f90cd41f6b5e81d4722f98d157c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 16:36:24 +0000 Subject: [PATCH 031/274] PRMVIO and interrupt fixes. --- src/video/nv/nv3/nv3_core.c | 6 ++++++ src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 +- src/video/nv/nv3/subsystems/nv3_pmc.c | 7 +++++-- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index e736e0c79..a7caa0b2b 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -120,6 +120,8 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) // Write 8-bit MMIO void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) { + addr &= 0xFFFFFF; + // This is weitek vga stuff if (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) @@ -144,6 +146,8 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // Write 16-bit MMIO void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) { + addr &= 0xFFFFFF; + // This is weitek vga stuff if (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) @@ -169,6 +173,8 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // Write 32-bit MMIO void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) { + addr &= 0xFFFFFF; + // This is weitek vga stuff if (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 9dfca4f00..1d44a3f94 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -231,7 +231,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // Fire a VALID Pgraph interrupt: num is the bit# of the interrupt in the GPU subsystem INTR_EN register. void nv3_pgraph_interrupt_valid(uint32_t num) { - nv3->pgraph.interrupt_enable_0 |= (1 << num); + nv3->pgraph.interrupt_status_0 |= (1 << num); nv3_pmc_handle_interrupts(true); } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 6b2b51b09..1cc28140c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -89,9 +89,12 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO); // PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...clean this up once we verify it - if (nv3->pgraph.interrupt_status_0 & (1 << 8)) + if (nv3->pgraph.interrupt_status_0 & (1 << 8) + && nv3->pgraph.interrupt_enable_0 & (1 << 8)) new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB); - else if (nv3->pgraph.interrupt_status_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt + + if (nv3->pgraph.interrupt_status_0 & ~(1 << 8) + && nv3->pgraph.interrupt_enable_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0); // Check second pgraph interrupt register From 9d97e3c7bae50950056671ff258f5975bd708bd8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 16:50:47 +0000 Subject: [PATCH 032/274] More anti-stupidity measures. CLEAR interrupts...WHEN WE CLEAR THEM...AND DON'T SET SPURIOUS INTERRUPTS! --- src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 1cc28140c..d32738a5e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -61,7 +61,7 @@ nv_register_t pmc_registers[] = { uint32_t nv3_pmc_clear_interrupts() { nv_log("NV3: Clearing IRQs\n"); - pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); + pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } // Handle hardware interrupts From ec0cf28d25dfc7c71228d4fd52bb7885db3a7644 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 19:59:33 +0000 Subject: [PATCH 033/274] Implement some basic i2c shit and more SVGA shit, so that the drivers don't magically explode. LOL --- src/include/86box/nv/vid_nv.h | 17 ++++-- src/include/86box/nv/vid_nv3.h | 5 +- src/video/nv/nv3/nv3_core.c | 84 +++++++++++++++++++++++---- src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- 4 files changed, 90 insertions(+), 18 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 39e9a68d0..06c545fc7 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -28,6 +28,8 @@ //TODO: split this all into nv1, nv3, nv4... +#include <86box/i2c.h> +#include <86box/vid_ddc.h> #include <86box/timer.h> #include <86box/vid_svga.h> #include <86box/vid_svga_render.h> @@ -68,16 +70,19 @@ void nv_log(const char *fmt, ...); typedef enum nv_bus_generation_e { + // NV1 - Prototype version + nv_bus_vlb = 0, + // NV1 // NV3 - nv_bus_pci = 0, + nv_bus_pci = 1, // NV3 - nv_bus_agp_1x = 1, + nv_bus_agp_1x = 2, // NV3T // NV4 - nv_bus_agp_2x = 2, + nv_bus_agp_2x = 3, } nv_bus_generation; @@ -103,11 +108,13 @@ typedef struct nv_base_s nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping double pixel_clock_period; // Period in seconds for pixel clock - rivatimer_t* pixel_clock_timer; + rivatimer_t* pixel_clock_timer; // Timer for measuring pixel clock bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times double memory_clock_period; // Period in seconds for pixel clock - rivatimer_t* memory_clock_timer; + rivatimer_t* memory_clock_timer; // Timer for measuring memory/gpu clock bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times + void* i2c; // I2C for monitor EDID + void* ddc; } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index b17423305..5aa0e6c79 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -568,7 +568,10 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_PIXELMODE_16BPP 0x02 #define NV3_CRTC_REGISTER_PIXELMODE_32BPP 0x03 -#define NV3_CRTC_REGISTER_RMA 0x38 // REAL MODE ACCESS! +#define NV3_CRTC_REGISTER_RL0 0x34 +#define NV3_CRTC_REGISTER_RL1 0x35 +#define NV3_CRTC_REGISTER_RMA 0x38 // REAL MODE ACCESS! +#define NV3_CRTC_REGISTER_I2C 0x3F // where the fuck is GDC? #define NV3_CRTC_BANKED_128K_A0000 0x00 diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index a7caa0b2b..cfbb0c324 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -243,7 +243,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) break; case PCI_REG_COMMAND_H: - ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] | NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back + ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] & NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back break; // pci status register @@ -447,15 +447,6 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) } } -void nv3_close(void* priv) -{ - rivatimer_destroy(nv3->nvbase.pixel_clock_timer); - rivatimer_destroy(nv3->nvbase.memory_clock_timer); - svga_close(&nv3->nvbase.svga); - free(nv3); - nv3 = NULL; -} - // // SVGA functions @@ -575,6 +566,18 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv) // Support the extended NVIDIA CRTC register range switch (nv3->nvbase.svga.crtcreg) { + case NV3_CRTC_REGISTER_RL0: + ret = nv3->nvbase.svga.displine & 0xFF; + break; + /* Is rl1?*/ + case NV3_CRTC_REGISTER_RL1: + ret = (nv3->nvbase.svga.displine >> 8) & 7; + break; + case NV3_CRTC_REGISTER_I2C: + ret = i2c_gpio_get_sda((nv3->nvbase.i2c) << 3) + | i2c_gpio_get_scl((nv3->nvbase.i2c) << 2); + + break; default: ret = nv3->nvbase.svga.crtc[nv3->nvbase.svga.crtcreg]; } @@ -641,6 +644,8 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) val = (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_OVERFLOW] & ~0x10) | (val & 0x10); // set the register value... + uint8_t old_value = nv3->nvbase.svga.crtc[crtcreg]; + nv3->nvbase.svga.crtc[crtcreg] = val; // ...now act on it @@ -664,6 +669,27 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) case NV3_CRTC_REGISTER_RMA: nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX; break; + case NV3_CRTC_REGISTER_I2C: + uint8_t scl = !!(val & 0x20); + uint8_t sda = !!(val & 0x10); + // Set an I2C GPIO register + i2c_gpio_set(nv3->nvbase.i2c, scl, sda); + break; + } + + /* Recalculate the timings if we actually changed them + Additionally only do it if the value actually changed*/ + if (old_value != val) + { + // Thx to Fuel who basically wrote all the SVGA compatibility code already (although I fixed some issues), because VGA is boring + // and in the words of an ex-Rendition/3dfx/NVIDIA engineer, "VGA was basically an undocumented bundle of steaming you-know-what. + // And it was essential that any cores the PC 3D startups acquired had to work with all the undocumented modes and timing tweaks (mode X, etc.)" + if (nv3->nvbase.svga.crtcreg < 0xE + && nv3->nvbase.svga.crtcreg > 0x10) + { + nv3->nvbase.svga.fullchange = changeframecount; + svga_recalctimings(&nv3->nvbase.svga); + } } break; @@ -937,7 +963,9 @@ void* nv3_init(const device_t *info) nv3_ptimer_init(); // Initialise programmable interval timer nv3_pvideo_init(); // Initialise video overlay engine - nv_log("NV3: Initialising timers...\n"); + nv_log("NV3: Initialising I2C..."); + nv3->nvbase.i2c = i2c_gpio_init("nv3_i2c"); + nv3->nvbase.ddc = ddc_init(i2c_gpio_get_bus(nv3->nvbase.i2c)); return nv3; } @@ -958,6 +986,38 @@ void* nv3_init_agp(const device_t* info) nv3_init(info); } +void nv3_close(void* priv) +{ + // Shut down I2C and the DDC + i2c_gpio_close(nv3->nvbase.i2c); + ddc_close(nv3->nvbase.ddc); + + // Destroy the Rivatimers. (It doesn't matter if they are running.) + rivatimer_destroy(nv3->nvbase.pixel_clock_timer); + rivatimer_destroy(nv3->nvbase.memory_clock_timer); + + // Shut down SVGA + svga_close(&nv3->nvbase.svga); + free(nv3); + nv3 = NULL; +} + +// See if the bios rom is available. +void nv3_available() +{ + return rom_present(NV3_VBIOS_ASUS_V3000_V151) + || rom_present(NV3_VBIOS_DIAMOND_V330_V162) + || rom_present(NV3_VBIOS_ERAZOR_V14700) + || rom_present(NV3_VBIOS_ERAZOR_V15403) + || rom_present(NV3_VBIOS_ERAZOR_V15500) + || rom_present(NV3_VBIOS_STB_V128_V182) + || rom_present(NV3_VBIOS_STB_V128_V182) + || rom_present(NV3T_VBIOS_ASUS_V170) + || rom_present(NV3T_VBIOS_DIAMOND_V330_V182B) + || rom_present(NV3T_VBIOS_REFERENCE_CEK_V171) + || rom_present(NV3T_VBIOS_REFERENCE_CEK_V172); +} + // NV3 (RIVA 128) // PCI // 2MB or 4MB VRAM @@ -971,6 +1031,7 @@ const device_t nv3_device_pci = .close = nv3_close, .speed_changed = nv3_speed_changed, .force_redraw = nv3_force_redraw, + .available = nv3_available, .config = nv3_config, }; @@ -987,5 +1048,6 @@ const device_t nv3_device_agp = .close = nv3_close, .speed_changed = nv3_speed_changed, .force_redraw = nv3_force_redraw, + .available = nv3_available, .config = nv3_config, }; \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index d32738a5e..7313a7554 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -72,7 +72,7 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) // PGRAPH DMA INTR_EN (there is no DMA engine yet) // PRM Real-Mode Compatibility Interrupts - uint32_t new_intr_value; + uint32_t new_intr_value = 0x00; // set the new interrupt value // PAUDIO not used From f6e1ce28df9bc4c5a7e55dafbd9a440f08ce5581 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 20:01:07 +0000 Subject: [PATCH 034/274] fix compile --- src/video/nv/nv3/nv3_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index cfbb0c324..ba0cd16ac 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -574,8 +574,8 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv) ret = (nv3->nvbase.svga.displine >> 8) & 7; break; case NV3_CRTC_REGISTER_I2C: - ret = i2c_gpio_get_sda((nv3->nvbase.i2c) << 3) - | i2c_gpio_get_scl((nv3->nvbase.i2c) << 2); + ret = i2c_gpio_get_sda(nv3->nvbase.i2c) << 3 + | i2c_gpio_get_scl(nv3->nvbase.i2c) << 2; break; default: @@ -1003,7 +1003,7 @@ void nv3_close(void* priv) } // See if the bios rom is available. -void nv3_available() +int32_t nv3_available() { return rom_present(NV3_VBIOS_ASUS_V3000_V151) || rom_present(NV3_VBIOS_DIAMOND_V330_V162) From 486087face1c9bc7d2146ff9b680472ffb69de8b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 20:42:34 +0000 Subject: [PATCH 035/274] Actually send the reads and writes to the right place. Fix driver init infinite loop at stateNv -> stateGr(STATE_INIT) -> initGr phase. --- src/include/86box/nv/vid_nv3.h | 6 ++++ src/video/nv/nv3/nv3_core.c | 52 ++++++++++++++++++++++++++++------ 2 files changed, 50 insertions(+), 8 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 5aa0e6c79..80766be94 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -425,6 +425,12 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_REAL_END 0x5C1FFF #define NV3_PRMCIO_START 0x601000 +// Following four are CRTC+I2C access registers +// and get redirected to VGA +#define NV3_PRMCIO_CRX_MONO 0x6013B4 +#define NV3_PRMCIO_CR_MONO 0x6013B5 +#define NV3_PRMCIO_CRX_COLOR 0x6013D4 +#define NV3_PRMCIO_CR_COLOR 0x6013D5 #define NV3_PRMCIO_END 0x601FFF #define NV3_PDAC_START 0x680000 // OPTIONAL external DAC diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index ba0cd16ac..cfbb282d5 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -52,12 +52,18 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) addr &= 0xFFFFFF; if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END) + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; ret = nv3_svga_in(real_address, nv3); + + nv_log("NV3: Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x", addr, ret); return ret; } @@ -76,7 +82,11 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) addr &= 0xFFFFFF; if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END) + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -84,6 +94,8 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); + nv_log("NV3: Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x", addr, ret); + return ret; } @@ -100,7 +112,11 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) addr &= 0xFFFFFF; if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END) + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -109,7 +125,9 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 1, nv3) << 8) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - + + nv_log("NV3: Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x", addr, ret); + return ret; } @@ -123,12 +141,18 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) addr &= 0xFFFFFF; // This is weitek vga stuff + // If we need to add more of these we can convert these to a switch statement if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END) + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; + nv_log("NV3: Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); return; @@ -150,11 +174,16 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // This is weitek vga stuff if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END) + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; + nv_log("NV3: Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -177,11 +206,17 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // This is weitek vga stuff if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END) + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; + nv_log("NV3: Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x", addr, val); + nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); nv3_svga_out(real_address + 2, (val >> 16) & 0xFF, nv3); @@ -989,8 +1024,9 @@ void* nv3_init_agp(const device_t* info) void nv3_close(void* priv) { // Shut down I2C and the DDC - i2c_gpio_close(nv3->nvbase.i2c); ddc_close(nv3->nvbase.ddc); + i2c_gpio_close(nv3->nvbase.i2c); + // Destroy the Rivatimers. (It doesn't matter if they are running.) rivatimer_destroy(nv3->nvbase.pixel_clock_timer); From f7ccbc4e718351d500461483f5ceeca2671a3bda Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 22:03:06 +0000 Subject: [PATCH 036/274] Run PTIMER at a reasonable speed. Fix I2C register.s This means we actually for real get beyond stateGr and now try to accelerate rendering --- src/include/86box/nv/vid_nv.h | 4 ++-- src/include/86box/nv/vid_nv3.h | 23 ++++++++++++----------- src/include/86box/nv/vid_nv_rivatimer.h | 4 ++-- src/video/nv/nv3/nv3_core.c | 16 ++++++++-------- src/video/nv/nv3/subsystems/nv3_pramdac.c | 18 +++++++----------- src/video/nv/nv3/subsystems/nv3_ptimer.c | 11 +++++++++-- src/video/nv/nv_rivatimer.c | 6 +++--- 7 files changed, 43 insertions(+), 39 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 06c545fc7..d067c0148 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -107,10 +107,10 @@ typedef struct nv_base_s uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping - double pixel_clock_period; // Period in seconds for pixel clock + double pixel_clock_frequency; // Frequency used for pixel clock rivatimer_t* pixel_clock_timer; // Timer for measuring pixel clock bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times - double memory_clock_period; // Period in seconds for pixel clock + double memory_clock_frequency; // Source Frequency for PTIMER rivatimer_t* memory_clock_timer; // Timer for measuring memory/gpu clock bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times void* i2c; // I2C for monitor EDID diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 80766be94..a404df979 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -577,7 +577,8 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_RL0 0x34 #define NV3_CRTC_REGISTER_RL1 0x35 #define NV3_CRTC_REGISTER_RMA 0x38 // REAL MODE ACCESS! -#define NV3_CRTC_REGISTER_I2C 0x3F +#define NV3_CRTC_REGISTER_I2C 0x3E +#define NV3_CRTC_REGISTER_I2C_GPIO 0x3F // where the fuck is GDC? #define NV3_CRTC_BANKED_128K_A0000 0x00 @@ -904,7 +905,7 @@ void nv3_speed_changed(void *priv); void nv3_force_redraw(void* priv); // Memory Mapping -void nv3_update_mappings(); +void nv3_update_mappings(); // Update memory mappings uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO @@ -917,12 +918,12 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv); // Read PCI configuration registers void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers -uint8_t nv3_ramin_read8(uint32_t addr, void* priv); // Read 8-bit RAMIN -uint16_t nv3_ramin_read16(uint32_t addr, void* priv); // Read 16-bit RAMIN -uint32_t nv3_ramin_read32(uint32_t addr, void* priv); // Read 32-bit RAMIN -void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit RAMIN -void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN -void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN +uint8_t nv3_ramin_read8(uint32_t addr, void* priv); // Read 8-bit RAMIN +uint16_t nv3_ramin_read16(uint32_t addr, void* priv); // Read 16-bit RAMIN +uint32_t nv3_ramin_read32(uint32_t addr, void* priv); // Read 32-bit RAMIN +void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit RAMIN +void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN +void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN // MMIO Arbitration // Determine where the hell in this mess our reads or writes are going @@ -1015,12 +1016,12 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val); void nv3_pramdac_init(); void nv3_pramdac_set_vram_clock(); void nv3_pramdac_set_pixel_clock(); -void nv3_pramdac_pixel_clock_poll(); -void nv3_pramdac_memory_clock_poll(); +void nv3_pramdac_pixel_clock_poll(double real_time); +void nv3_pramdac_memory_clock_poll(double real_time); // NV3 PTIMER void nv3_ptimer_init(); -void nv3_ptimer_tick(); +void nv3_ptimer_tick(double real_time); // NV3 PVIDEO void nv3_pvideo_init(); diff --git a/src/include/86box/nv/vid_nv_rivatimer.h b/src/include/86box/nv/vid_nv_rivatimer.h index 31483992e..d5bb86b90 100644 --- a/src/include/86box/nv/vid_nv_rivatimer.h +++ b/src/include/86box/nv/vid_nv_rivatimer.h @@ -73,12 +73,12 @@ typedef struct rivatimer_s } rivatimer_t; void rivatimer_init(); // Initialise the Rivatimer. -rivatimer_t* rivatimer_create(double period, void (*callback)()); +rivatimer_t* rivatimer_create(double period, void (*callback)(double real_time)); void rivatimer_destroy(rivatimer_t* rivatimer_ptr); void rivatimer_update_all(); void rivatimer_start(rivatimer_t* rivatimer_ptr); void rivatimer_stop(rivatimer_t* rivatimer_ptr); double rivatimer_get_time(rivatimer_t* rivatimer_ptr); -void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()); +void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)(double real_time)); void rivatimer_set_period(rivatimer_t* rivatimer_ptr, double period); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index cfbb282d5..cd1614e8e 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -63,8 +63,8 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3); - nv_log("NV3: Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x", addr, ret); - + nv_log("NV3: Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x\n", addr, ret); + return ret; } @@ -94,7 +94,7 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); - nv_log("NV3: Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x", addr, ret); + nv_log("NV3: Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); return ret; } @@ -126,7 +126,7 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - nv_log("NV3: Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x", addr, ret); + nv_log("NV3: Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x\n", addr, ret); return ret; } @@ -152,7 +152,7 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("NV3: Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x", addr, val); + nv_log("NV3: Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); return; @@ -183,7 +183,7 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("NV3: Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x", addr, val); + nv_log("NV3: Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -215,7 +215,7 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("NV3: Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x", addr, val); + nv_log("NV3: Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -704,7 +704,7 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) case NV3_CRTC_REGISTER_RMA: nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX; break; - case NV3_CRTC_REGISTER_I2C: + case NV3_CRTC_REGISTER_I2C_GPIO: uint8_t scl = !!(val & 0x20); uint8_t sda = !!(val & 0x10); // Set an I2C GPIO register diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 0c57b71cb..9c44105b9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -50,18 +50,16 @@ void nv3_pramdac_init() // Polls the pixel clock. // This updates the 2D/3D engine PGRAPH -void nv3_pramdac_pixel_clock_poll() +void nv3_pramdac_pixel_clock_poll(double real_time) { - // TODO: UPDATE PGRAPH! + // TODO: ???? } // Polls the memory clock. -void nv3_pramdac_memory_clock_poll() +void nv3_pramdac_memory_clock_poll(double real_time) { - //nv3_t* nv3_poll = (nv3_t*)priv; - - // Let's hope qeeg was right here. - nv3_ptimer_tick(); + nv3_ptimer_tick(real_time); + // TODO: UPDATE PGRAPH! } // Gets the vram clock register. @@ -120,10 +118,8 @@ void nv3_pramdac_set_vram_clock() nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f); - nv3->nvbase.memory_clock_period = time; + nv3->nvbase.memory_clock_frequency = frequency; - //timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period); - // Create and start if it it's not running. if (!nv3->nvbase.memory_clock_timer) { @@ -170,7 +166,7 @@ void nv3_pramdac_set_pixel_clock() nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f); - nv3->nvbase.pixel_clock_period = time; + nv3->nvbase.pixel_clock_frequency = frequency; // Create and start if it it's not running. if (!nv3->nvbase.pixel_clock_timer) diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index c0d68a24c..ab19c1e61 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -57,7 +57,7 @@ void nv3_ptimer_interrupt(uint32_t num) } // Ticks the timer. -void nv3_ptimer_tick() +void nv3_ptimer_tick(double real_time) { // do not divide by zero if (nv3->ptimer.clock_numerator == 0 @@ -67,7 +67,14 @@ void nv3_ptimer_tick() // get the current time // Due to timer system limitations, the timer system is not capable of running at 100 megahertz. Therefore, we have to scale it down and then scale up the level of changes // to the state. - double current_time = ((double)nv3->ptimer.clock_numerator * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)nv3->ptimer.clock_denominator; // *10.0? + + // See Envytools. We need to use the frequency as a source. + // But we need to figure out how many cycles actually occurred because this counts up every cycle... + + // Convert to microseconds + double freq_base = (real_time / 1000000.0f) / ((double)1.0 / nv3->nvbase.memory_clock_frequency); + + double current_time = freq_base * ((double)nv3->ptimer.clock_numerator * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)nv3->ptimer.clock_denominator; // *10.0? // Logging is suppressed when reading this register because it is read many times // So we only log when we update. diff --git a/src/video/nv/nv_rivatimer.c b/src/video/nv/nv_rivatimer.c index c31ee11fe..343ec02ff 100644 --- a/src/video/nv/nv_rivatimer.c +++ b/src/video/nv/nv_rivatimer.c @@ -59,7 +59,7 @@ void rivatimer_init() } // Creates a rivatimer. -rivatimer_t* rivatimer_create(double period, void (*callback)()) +rivatimer_t* rivatimer_create(double period, void (*callback)(double real_time)) { rivatimer_t* new_rivatimer = NULL; @@ -210,7 +210,7 @@ void rivatimer_update_all() continue; } - rivatimer_ptr->callback(); + rivatimer_ptr->callback(microseconds); } rivatimer_ptr = rivatimer_ptr->next; @@ -254,7 +254,7 @@ double rivatimer_get_time(rivatimer_t* rivatimer_ptr) return rivatimer_ptr->time; } -void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)()) +void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)(double real_time)) { if (!rivatimer_really_exists(rivatimer_ptr)) fatal("rivatimer_set_callback: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); From d30307e2a5013f54610e7cc81e37e76882eaf5b0 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 22:10:33 +0000 Subject: [PATCH 037/274] More logging --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index c5868ef10..97d5e6f0e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -119,7 +119,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - nv_log("NV3: pfifo Write 0x%08x -> 0x%08x\n", value, address); + nv_log("NV3: PFIFO Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 08a2b48ff..a6561be9d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -50,7 +50,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) uint8_t val = nv3->nvbase.svga.vram[addr]; - nv_log("NV3: Read byte from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + nv_log("NV3: Read byte from RAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); return val; } @@ -70,7 +70,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) uint16_t val = vram_16bit[addr]; // what - nv_log("NV3: Read word from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + nv_log("NV3: Read word from RAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); return val; } @@ -90,7 +90,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) uint32_t val = vram_32bit[addr]; - nv_log("NV3: Read dword from ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + nv_log("NV3: Read dword from RAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); return val; } @@ -109,7 +109,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) nv3->nvbase.svga.vram[addr] = val; - nv_log("NV3: Write byte to ramin addr=0x%08x val=0x%08x (raw address=0x%08x)", addr, val, raw_addr); + nv_log("NV3: Write byte to RAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); } // Write 16-bit ramin @@ -127,7 +127,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) vram_16bit[addr] = val; - nv_log("NV3: Write word to ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + nv_log("NV3: Write word to RAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr); } // Write 32-bit ramin @@ -145,5 +145,5 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) vram_32bit[addr] = val; - nv_log("NV3: Write dword to ramin addr=0x%08x (raw address=0x%08x)", addr, raw_addr); + nv_log("NV3: Write dword to RAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } From fda2c3a3fe85c8d2c93caa82a3493147457b58f9 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 31 Dec 2024 22:34:55 +0000 Subject: [PATCH 038/274] note current state of drivers --- doc/nv3 driver init status.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/nv3 driver init status.txt b/doc/nv3 driver init status.txt index 025e781a2..d0d13bacd 100644 --- a/doc/nv3 driver init status.txt +++ b/doc/nv3 driver init status.txt @@ -106,3 +106,7 @@ NvFindAdapter -> RmPostNvDevice Success 17:32 27/11/2024 NvFindAdapter -> NVGetNVInfo Success 17:32 27/11/2024 NvFindAdapter -> NVMapFrameBuffer Success 17:32 27/11/2024 +00:00 30/12/2024: stateGr -> i2c_Write +22:31 31/12/2024: fifoService + +fix ptimer issue \ No newline at end of file From dee308f4b5b05294af7ff597986fb7f005237843 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 1 Jan 2025 02:32:34 +0000 Subject: [PATCH 039/274] fix compiler warning --- src/include/86box/nv/classes/vid_nv3_classes.h | 9 +++++++++ src/include/86box/nv/vid_nv3.h | 6 +++--- src/video/nv/nv3/nv3_core.c | 2 +- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index e47b5eb71..b5d4ff44a 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -39,6 +39,15 @@ extern const char* nv3_class_names[]; +/* Object Class 0x01 (real hardware) + Beta factor +*/ +typedef struct nv_object_class_001 +{ + uint8_t reserved[0xFF]; // Required for NV_CLASS Core Functionality + // Put the rest of it here +} nv3_beta_factor_t; + /* Object Class 0x07 (real hardware) 0x1E (drivers) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index a404df979..3e69b57fd 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -6,7 +6,8 @@ * * This file is part of the 86Box distribution. * - * JENSEN HUANG APPROVED !!!! + * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) + * Last updated 1 January 2025 (STILL WORKING ON IT) * * * @@ -15,8 +16,7 @@ * Copyright 2024-2025 Connor Hyde */ -// vid_nv3.h: NV3 Architecture Hardware Reference (open-source) -// Last updated 30 December 2024 + // The GPU base structure extern const device_config_t nv3_config[]; diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index cd1614e8e..e69244209 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -679,7 +679,7 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) val = (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_OVERFLOW] & ~0x10) | (val & 0x10); // set the register value... - uint8_t old_value = nv3->nvbase.svga.crtc[crtcreg]; + old_value = nv3->nvbase.svga.crtc[crtcreg]; nv3->nvbase.svga.crtc[crtcreg] = val; // ...now act on it From 23467b07b8afc98b2b92c028ba4b01dcf425432b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 2 Jan 2025 11:35:41 +0000 Subject: [PATCH 040/274] fix compiler warning --- src/video/nv/nv3/subsystems/nv3_pbus.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index cf5b698a1..61385b8f2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -175,8 +175,6 @@ uint8_t nv3_pbus_rma_read(uint16_t addr) // Implements a 32-bit write using 16 bit port number void nv3_pbus_rma_write(uint16_t addr, uint8_t val) { - uint8_t ret = 0x00; - // addresses are in reality 8bit so just mask it to be safe addr &= 0xFF; From 61042299f306c8d5816ae32251eedece1a9db6a1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 2 Jan 2025 21:55:01 +0000 Subject: [PATCH 041/274] eh 2nd time i need to merge today --- doc/old nouveau wiki.txt | 9 +++++++++ src/video/nv/nv3/subsystems/nv3_pgraph.c | 3 ++- 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 doc/old nouveau wiki.txt diff --git a/doc/old nouveau wiki.txt b/doc/old nouveau wiki.txt new file mode 100644 index 000000000..c875954fd --- /dev/null +++ b/doc/old nouveau wiki.txt @@ -0,0 +1,9 @@ +old nouveau wiki: +real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) + +nv3=16 bytes + +0x400000 - ((0x100000) - (0x100000 % 16)) - 16 + (0x100000 % 16) = 2ffff0 + + + \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 1d44a3f94..32f87ee30 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -86,7 +86,8 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_TRAPPED_ADDRESS, "PGRAPH Trapped Address", NULL, NULL }, { NV3_PGRAPH_TRAPPED_DATA, "PGRAPH Trapped Data", NULL, NULL }, { NV3_PGRAPH_TRAPPED_INSTANCE, "PGRAPH Trapped Object Instance", NULL, NULL }, - + { NV3_PGRAPH_DMA_INTR_0, "PGRAPH DMA Interrupt Status (unimplemented)", NULL, NULL }, + { NV3_PGRAPH_DMA_INTR_EN_0, "PGRAPH DMA Interrupt Enable (unimplemented)", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; From ee0dfda9eef1f323c4eff35247f8bab6fb39a25c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 2 Jan 2025 22:01:23 +0000 Subject: [PATCH 042/274] Some refactoring for the SVGA redirection --- src/video/nv/nv3/nv3_core.c | 51 +++++++++++++------------------------ 1 file changed, 18 insertions(+), 33 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index e69244209..6114749a6 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -34,12 +34,23 @@ nv3_t* nv3; // Prototypes for functions only used in this translation unit void nv3_init_mappings_mmio(); void nv3_init_mappings_svga(); -void nv3_shutdown_mappings_mmio(); -void nv3_shutdown_mappings_svga(); +bool nv3_is_svga_redirect_address(uint32_t addr); uint8_t nv3_svga_in(uint16_t addr, void* priv); void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); +// Determine if this address needs to be redirected to the SVGA subsystem. + +bool nv3_is_svga_redirect_address(uint32_t addr) +{ + return (addr >= NV3_PRMVIO_START + && addr <= NV3_PRMVIO_END + || addr == NV3_PRMCIO_CR_COLOR + || addr == NV3_PRMCIO_CRX_COLOR + || addr == NV3_PRMCIO_CR_MONO + || addr == NV3_PRMCIO_CRX_MONO); +} + // All MMIO regs are 32-bit i believe internally // so we have to do some munging to get this to read @@ -51,12 +62,7 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. addr &= 0xFFFFFF; - if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO) + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -81,12 +87,7 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. addr &= 0xFFFFFF; - if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO) + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -111,12 +112,7 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. addr &= 0xFFFFFF; - if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO) + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -142,12 +138,7 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // This is weitek vga stuff // If we need to add more of these we can convert these to a switch statement - if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO) + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -205,12 +196,7 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) addr &= 0xFFFFFF; // This is weitek vga stuff - if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO) + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; @@ -1027,7 +1013,6 @@ void nv3_close(void* priv) ddc_close(nv3->nvbase.ddc); i2c_gpio_close(nv3->nvbase.i2c); - // Destroy the Rivatimers. (It doesn't matter if they are running.) rivatimer_destroy(nv3->nvbase.pixel_clock_timer); rivatimer_destroy(nv3->nvbase.memory_clock_timer); From f83153a2ee97fe0ff625d3ff0700c3e6f7958f23 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 3 Jan 2025 01:05:49 +0000 Subject: [PATCH 043/274] The first half of the completely insane object class system's structs. --- .../Memory map (RIVA 128).txt | 0 doc/{ => nvidia_notes}/NV_PFB_CONFIG_0.txt | 0 doc/{ => nvidia_notes}/PFIFO RAMHT RAMRO.txt | 0 doc/{ => nvidia_notes}/RIVA fansites.txt | 0 doc/{ => nvidia_notes}/Versions.txt | 0 doc/{ => nvidia_notes}/gpucompanies.txt | 0 .../nv3 driver init status.txt | 0 doc/{ => nvidia_notes}/nv3_object_classes.txt | 0 .../nv3_object_classes_driver.txt | 0 doc/{ => nvidia_notes}/nv3d3d_t.txt | 0 doc/{ => nvidia_notes}/old nouveau wiki.txt | 0 doc/nvidia_notes/rivatv_riva128.txt | 2238 +++++++++++++++++ .../86box/nv/classes/vid_nv3_classes.h | 498 +++- src/include/86box/nv/vid_nv3.h | 4 +- 14 files changed, 2702 insertions(+), 38 deletions(-) rename doc/{ => nvidia_notes}/Memory map (RIVA 128).txt (100%) rename doc/{ => nvidia_notes}/NV_PFB_CONFIG_0.txt (100%) rename doc/{ => nvidia_notes}/PFIFO RAMHT RAMRO.txt (100%) rename doc/{ => nvidia_notes}/RIVA fansites.txt (100%) rename doc/{ => nvidia_notes}/Versions.txt (100%) rename doc/{ => nvidia_notes}/gpucompanies.txt (100%) rename doc/{ => nvidia_notes}/nv3 driver init status.txt (100%) rename doc/{ => nvidia_notes}/nv3_object_classes.txt (100%) rename doc/{ => nvidia_notes}/nv3_object_classes_driver.txt (100%) rename doc/{ => nvidia_notes}/nv3d3d_t.txt (100%) rename doc/{ => nvidia_notes}/old nouveau wiki.txt (100%) create mode 100644 doc/nvidia_notes/rivatv_riva128.txt diff --git a/doc/Memory map (RIVA 128).txt b/doc/nvidia_notes/Memory map (RIVA 128).txt similarity index 100% rename from doc/Memory map (RIVA 128).txt rename to doc/nvidia_notes/Memory map (RIVA 128).txt diff --git a/doc/NV_PFB_CONFIG_0.txt b/doc/nvidia_notes/NV_PFB_CONFIG_0.txt similarity index 100% rename from doc/NV_PFB_CONFIG_0.txt rename to doc/nvidia_notes/NV_PFB_CONFIG_0.txt diff --git a/doc/PFIFO RAMHT RAMRO.txt b/doc/nvidia_notes/PFIFO RAMHT RAMRO.txt similarity index 100% rename from doc/PFIFO RAMHT RAMRO.txt rename to doc/nvidia_notes/PFIFO RAMHT RAMRO.txt diff --git a/doc/RIVA fansites.txt b/doc/nvidia_notes/RIVA fansites.txt similarity index 100% rename from doc/RIVA fansites.txt rename to doc/nvidia_notes/RIVA fansites.txt diff --git a/doc/Versions.txt b/doc/nvidia_notes/Versions.txt similarity index 100% rename from doc/Versions.txt rename to doc/nvidia_notes/Versions.txt diff --git a/doc/gpucompanies.txt b/doc/nvidia_notes/gpucompanies.txt similarity index 100% rename from doc/gpucompanies.txt rename to doc/nvidia_notes/gpucompanies.txt diff --git a/doc/nv3 driver init status.txt b/doc/nvidia_notes/nv3 driver init status.txt similarity index 100% rename from doc/nv3 driver init status.txt rename to doc/nvidia_notes/nv3 driver init status.txt diff --git a/doc/nv3_object_classes.txt b/doc/nvidia_notes/nv3_object_classes.txt similarity index 100% rename from doc/nv3_object_classes.txt rename to doc/nvidia_notes/nv3_object_classes.txt diff --git a/doc/nv3_object_classes_driver.txt b/doc/nvidia_notes/nv3_object_classes_driver.txt similarity index 100% rename from doc/nv3_object_classes_driver.txt rename to doc/nvidia_notes/nv3_object_classes_driver.txt diff --git a/doc/nv3d3d_t.txt b/doc/nvidia_notes/nv3d3d_t.txt similarity index 100% rename from doc/nv3d3d_t.txt rename to doc/nvidia_notes/nv3d3d_t.txt diff --git a/doc/old nouveau wiki.txt b/doc/nvidia_notes/old nouveau wiki.txt similarity index 100% rename from doc/old nouveau wiki.txt rename to doc/nvidia_notes/old nouveau wiki.txt diff --git a/doc/nvidia_notes/rivatv_riva128.txt b/doc/nvidia_notes/rivatv_riva128.txt new file mode 100644 index 000000000..780ad5edd --- /dev/null +++ b/doc/nvidia_notes/rivatv_riva128.txt @@ -0,0 +1,2238 @@ + + +Riva 128 documentation +====================== + +This document is based on kernel sources, XFree86 sources, open sources +released by nVidia and pure deduction. To make nVidia happy: + + /***************************************************************************\ +|* *| +|* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *| +|* *| +|* NOTICE TO USER: The source code is copyrighted under U.S. and *| +|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| +|* the copyright and as design patents pending on the design and *| +|* interface of the NV chips. Users and possessors of this source *| +|* code are hereby granted a nonexclusive, royalty-free copyright *| +|* and design patent license to use this code in individual and *| +|* commercial software. *| +|* *| +|* Any use of this source code must include, in the user documenta- *| +|* tion and internal comments to the code, notices to the end user *| +|* as follows: *| +|* *| +|* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *| +|* pending in the U.S. and foreign countries. *| +|* *| +|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| +|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| +|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| +|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| +|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| +|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| +|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| +|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| +|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| +|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| +|* PERFORMANCE OF THIS SOURCE CODE. *| +|* *| + \***************************************************************************/ + +Feel free to send me corrections, updates, suggestions about this document to: +fero@drama.obuda.kando.hu or rivatv-devel@lists.sourceforge.net +Any kind of info, hint or idea may be helpful. +Please visit the rivatv homepage at: +http://fero.koli.kando.hu/rivatv/ + + + +Rendering +========= + +DMA vs PIO +---------- + +Theese two methods are used to program the hardware. DMA method provides +better performance but it is harder to implement. Almost all of the released +sources uses PIO method. The rest of this document describes the PIO method. + + +Objects +------- + +The Riva rendering engine is an object-oriented hardware. (See the nVidia +docs at https://www.nvidia.com/nv/nvarch.nsf/Home?OpenView -> Documents -> +NV Programmer's Reference Manual) Do not take it serious, it's simplified +for the hardware, it is not like C++. +Each object has a name. The name is 32 bits long and should be unique. + + +FIFO Channels +------------- + +There are 8 channels for submitting graphical objects to the rendering engine. +Each channel contains 8 subchannels. The rules how channels and subchannels +are working is not clear for me yet. Channel 0 is usable without extra coding. +Other channels can not be used until the 'context switching' code is done. +FIFO channels are located in the CTRL memory at 0x00800000-0x0087FFFF. Each +channel is 64 kbytes long, each subchannel is 8 kbytes long. Registers of +subchannels are variable: their function depends on the type of the submitted +object. Registers are write only and 32 bits long except the 'Free' register. + +Offset Name(s) Valid object types +------ ----------------------------- ------------------ +0000 Object all +0010 Free (2 bytes, read only!) all +0100 Synchronize t V s3 +0100 NoOperation BKPCLTRbISMr DG +0104 StopAlarm t +0104 Notify BKPCLTRbISMr DG +0104 StopImage V +0108 StopCursor V +010c StopDac V +0180 DmaNotifies tBKPCLTRbISMrVDGs3 +0184 ClipRectangle LTR +0184 ColorKey bIS +0184 DmaImage M V +0184 DmaTexture D +0184 Pattern G +0184 DmaSource s +0184 DmaSurfaces 3 +0188 Pattern LTR SM +0188 ClipRectangle bI D +0188 Rop G +0188 DmaDestin s +018c Rop LTR SM +018c Pattern bI +018c DmaLut V +018c Surfaces3D D +018c Beta1 G +0190 Beta1 LTR SM +0190 Rop bI +0190 Surfaces G +0194 Surfaces LTR SM +0194 Beta1 bI +0194 DmaCursor V +0198 Surfaces I +019c Surfaces b +02fc Operation LTRbIS G +02fc Get V +0300 Time0 t +0300 Beta1d31 B +0300 ColorFormat KP LTR ISM G +0300 Point C +0300 ControlPointIn b +0300 Rop r +0300 Image V +0300 Format s +0300 Pitch 3 +0304 Time1 t +0304 Color K LTR +0304 MonochromeFormat P G +0304 Size C +0304 ControlPointOut b +0304 Point I +0304 SizeIn S +0304 TextureOffset D +0304 Pitch s +0304 OffsetColor 3 +0300 Operation M +0308 AlarmNotify t +0308 MonochromeShape P +0308 Size b +0308 SizeOut I +0308 DxDu S +0308 ClipPoint M +0308 TextureFormat D +0308 OffsetSource s +0308 OffsetZeta 3 +030c SizeIn I +030c DyDv S +030c ClipSize M +030c TextureFilter D +030c OffsetDestin s +0310 MonochromeColor0 P +0310 TrianglePoint0 T +0310 ClipPoint S +0310 ImageOutPoint M +0310 FogColor D +0314 MonochromeColor1 P +0314 TrianglePoint1 T +0314 ClipSize S +0314 ImageOutSize M +0314 Control0 D +0318 MonochromePattern0 P +0318 TrianglePoint2 T +0318 Point12d4 S +0318 DxDu M +0318 Control1 D +031c MonochromePattern1 P +031c DyDv M +0320 Triangle32Point0X T +0324 Triangle32Point0Y T +0328 Triangle32Point1X T +032c Triangle32Point1Y T +0330 Triangle32Point2X T +0334 Triangle32Point2Y T +0340 Cursor V +0358 CursorPointOutA V +0380 Dac V +03a0 PixelClock V +03fc Color1A G +0400 Lin L +0400 Trimesh T +0400 Rectangle R +0400 Color IS +0400 ImageInSize M +0400 UnclippedRectangle G +0404 ImageInFormat M +0408 ImageInOffset M +040c ImageInPoint M +0480 Lin32 L +0480 Trimesh32 T +0500 PolyLin L +0500 ColorTriangle T +0580 PolyLin32 L +0580 ColorTrimesh T +0600 ColorPolyLin L +07f4 ClipPoint0B G +07f8 ClipPoint0B G +07fc Color1B G +0800 ClippedRectangle G +0bec ClipPoint0C G +0bf0 ClipPoint1C G +0bf4 Color1C G +0bf8 SizeC G +0bfc PointC G +0c00 MonochromeColor1C G +0fe8 ClipPoint0D G +0fec ClipPoint1D G +0ff0 Color1D G +0ff4 SizeInD G +0ff8 SizeOutD G +0ffc PointD G +1000 Tlvertex D +1000 MonochromeColor1D G +13e4 ClipPoint0E G +13e8 ClipPoint1E G +13ec Color0E G +13f0 Color1E G +13f4 SizeInE G +13f8 SizeOutE G +13fc PointE G +1400 MonochromeColor01E G + +t=timer +B=beta1 (0x41) +K=color key (0x43) +P=pattern (0x46) +C=clip rectangle (0x45) +L=solid line (0x4a) +T=solid triangle (0x4b) +R=solid rectangle (0x47) +b=image blit (0x50) +I=image from CPU (0x51) +S=stretched image from CPU (0x55) +M=scaled image from memory (0x4e) +r=raster operation (0x42) +V=video lut cursor dac +D=DX3 textured triangle (0x57) +G=GDI rectangle text (0x4c?) +s=Surfaces 2D +3=Surfaces 3D + +Contexts +-------- + +Context is a 32 bit record of channel id, object type and pointer to the +object. + +Bits 24-30: channel id +Bit 23: rendering + 0x0 other object (DMA?) + 0x1 renderable object +Bits 16-22: object type + 0x41 beta1 + 0x42 raster operation + 0x43 color key + 0x44 plane + 0x45 clipping rectangle + 0x46 pattern + 0x47 solid rectangle + 0x49 unknown line + 0x4A solid line + 0x4B solid triangle + 0x4C GDI rectangle + 0x4E scaled image from memory + 0x50 blit + 0x51 image from CPU + 0x52 bitmap + 0x55 streched image from CPU + 0x57 DX3 textured triangle + 0x?? Surfaces 2D + 0x?? Surfaces 3D + 0x?? Timer + 0x?? Video lut cursor dac + and many more... +Bits 0-15: offset in instance memory (RAMIN) / 16 + +Each graphic object has a context. Context determines the type (triangle, +raster operation, bitmap, etc) of the object. Don't ask me why this thingy +is called context: I really don't know. + + +Hash table +---------- + +The hash table (HT) is located in the instance memory area (RAMIN). +See RAMHT register in section FIFO registers. +The HT contains 8 byte length records of object names and contexts. Each +record is placed in the table by it's hash key. The key is computed as +follows: each byte of the object's name and the channel id are XOR-ed +together, and this value is multiplied by the hash depth. More explanation +on hash tables can be found in database books. +The purpose of HT is to provide connection between object names and contexts +for the graphic hardware. But it may be useful for your software driver too. + + +FIFO context table +------------------ + +The FIFO context table (FC) is located in the instance memory area (RAMIN). +See RAMFC register in section FIFO registers. +FC contains the context values for each subchannel. E.g. if FC begins +at 0x1C00: +0x1C00 Context of object in channel 0, subchannel 0 +0x1C04 Context of object in channel 0, subchannel 1 +0x1C08 Context of object in channel 0, subchannel 2 +... +0x1C1C Context of object in channel 0, subchannel 7 +0x1C20 Context of object in channel 1, subchannel 0 +0x1C24 Context of object in channel 1, subchannel 1 +... +0x1CFC Context of object in channel 7, subchannel 7 + + +Example: How to render a solid rectangle? +----------------------------------------- + +- Choose a name for your rectangle. E.g.: 0x01020304 +- Select an unused area in the instance memory. Let it be 0x00c04000 +- Calculate the context: + Channel = 0x00 + Render object = 1 + Object type = 0x47 (rectangle) + Offset in intance memory = 0x4000 / 16 = 0x0400 + Context = 0x00c70400 +- Place the name - context pair in the hash table (HT begins at 0x00c00000): + Hash key = 01 xor 02 xor 03 xor 04 xor 00 = 0x04 + (each byte of the name) (channel id) + *(0x00c00000 + 0x04 * 16) = 0x00000001; // name + *(0x00c00000 + 0x04 * 16) + 4 = 0x00c70400; // context +- Fill in the instace ram: + *(0x00c04000) = 0x00100000; // 15bpp (TODO: decode this magic) + *(0x00c04004) = 0x00000000; // not used yet + *(0x00c04008) = 0x00000000; // not used yet + *(0x00c0400c) = 0x00000000; // not used yet +- At this point the FIFO channel is ready for submitting rectangles. +- Submit the first rectangle: + write the object's name to channel 0 (subchannel 0): + *(0x00800000) = 0x00000001; +- At this point subchannel 0 becomes a rectangle. +- Submit the attributes of the rectangle: + write x,y coordinates: + (0x00800400) = 0x01000200; // x=0x100 y=0x200 + size: + (0x00800404) = 0x00100020; // width=0x10 height=0x20 +- After size is submitted, our rectangle appears on the screen. +- Subsequent rectangles may be submitted by re-sending new attributes. + + +Speculation: How to make video in working? +------------------------------------------ + +V4L stuff and hardware rendered rectangles have some similarities: +- both have color keys +- both have clipping rectangles +- both are stretchable +I suppose video in feature is implemented by rendered objects. A chroma-keyed +and clipped rectangle with 'live texture' is blitted on the screen. +Thats all. :) + + + +Memory layout +============= + +Three memory regions are accessible via the PCI (or AGP) interface: +- CTRL region (PCI base 0) +- FB region (PCI base 1) +- BIOS ROM (PCI base 2) + + +CTRL region +----------- + +The CTRL region contains memory mapped IO ports. Most of them are 32-bit +registers. The registers are grouped by functionality: + +- MC: master control (0x00000000-0x00000FFF) +- BUS: (0x00001000-0x00001FFF) +- FIFO: for DMA and PIO stuff (0x00002000-0x00003FFF) +- TIMER: built-in timer (0x00009000-0x00009FFF) +- VIO: 8 bit SVGA (MISC, GRAPH, SEQ) registers (0x000C0000-0x00C00FFF) +- FB: framebuffer properties (0x00100000-0x00100FFF) +- EXTDEV: external devices (0x00101000-0x00101FFF) +- GRAPH: (0x00400000-0x00401FFF) +- PCIO: 8 bit SVGA (CRTC, ATTR) registers (0x00601000-0x00601FFF) +- RAMDAC: RAMDAC timings (0x00680000-0x00680FFF) +- PDIO: 8 bit registers (0x00681000-0x00681FFF) +- FIFO channels: (0x00800000-0x0087FFFF) +(List in not complete.) + + +FB region +--------- + +This region contains the video memory and the instance memory. +Video memory begins at offset 0x00000000. Instance memory (RAMIN) +begins at offset 0x00C00000. (Note: Riva TNT (and higher) cards have +their instance memory in the CTRL region.) + + + +Master control +============== + +The MC registers begin at 0x00000000 in the CTRL region. They control the +master IRQ. + +Interrupt 0 register +-------------------- +Name: INTR_0 +Offset: 0x00000100 +4 bytes, read-write + +Bit 0: PAUDIO (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 4: PMEDIA (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 8: PFIFO (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 12: PGRAPH0 (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 13: PGRAPH1 (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 16: PVIDEO (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 20: PTIMER (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 24: PFB (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 28: PBUS (-V, read-only) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + +Bit 31: SOFTWARE (IV, read-write) + NOT_PENDING 0x0 (default, read-write) + PENDING 0x1 (read-write) + +Interrupt 0 enable register +--------------------------- +Name: INTR_EN_0 +Offset: 0x00000140 +4 bytes, read-write + +Bits 0-1: INTA (IV, read-write) + DISABLED 0x0 (default, read-write) + HARDWARE 0x1 (read-write) + SOFTWARE 0x2 (read-write) + +Enable (what?) register +----------------------- +Name: ENABLE +Offset: 0x00000200 +4 bytes, read-write + + + +Bus +=== + +The BUS registers begin at 0x00001000 in the CTRL region. They are +undiscovered. + +Debug 0 register +---------------- +Name: DEBUG_0 +Offset: 0x00001080 +4 bytes, read-write + +Bit 0: MODE (IV, read-write) + MODE_DISABLED 0x0 (default, read-write) + MODE_ENABLED 0x1 (read-write) + +Bit 4: DESKEWER (IV, read-write) + ENABLED 0x0 (default, read-write) + +Bits 8-11: FBIO_SCLK_DELAY (IV, read-write) + 0x0 (default, read-write) + +Bits 12-15: FBIO_FBCLK_DELAY (IV, read-write) + 0x3 (default, read-write) + +Debug 1 register +---------------- +Name: DEBUG_1 +Offset: 0x00001084 +4 bytes, read-write + +Bit 0: PCIM_THROTTLE (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +Bit 1: PCIM_CMD (IV, read-write) + SIZE_BASED 0x0 (default, read-write) + MRL_ONLY 0x1 (read-write) + +Bit 2: PCIM_AGP (IV, read-write) + IS_AGP 0x0 (default, read-write) + IS_PCI 0x1 (read-write) + +Bits 3-4: AGPM_CMD (IV, read-write) + HP_ON_1ST 0x0 (read-write) + LP_ONLY 0x1 (default, read-write) + HP_ONLY 0x2 (read-write) + +Bit 5: PCIS_WRITE (IV, read-write) + 0_CYCLE 0x0 (read-write) + 1_CYCLE 0x1 (default, read-write) + +Bit 6: PCIS_2_1 (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +Bit 7: PCIS_RETRY (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +Bit 8: PCIS_RD_BURST (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 9: PCIS_WR_BURST (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 10: PCIS_EARLY_RTY (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +Bit 11: PCIS_RMAIO (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +Bit 12: PCIS_CPUQ (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +Bit 13: DPSH_PIPE (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 14: SPARE1 (IV, read-write) + ZERO 0x0 (default, read-write) + ONE 0x1 (read-write) + +Bit 15: SPARE2 (IV, read-write) + ZERO 0x0 (default, read-write) + ONE 0x1 (read-write) + +Bit 16: SPARE3 (IV, read-write) + ZERO 0x0 (default, read-write) + ONE 0x1 (read-write) + + + +FIFO +==== + +The BUS registers begin at 0x00002000 in the CTRL region. + +Interrupt 0 register +-------------------- + +Name: INTR_0 +Offset: 0x00002100 +4 bytes, read-write + +Bit 0: CACHE_ERROR (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 4: RUNOUT (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 8: RUNOUT_OVERFLOW (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 12: DMA_PUSHER (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 16: DMA_PTE (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Interrupt 0 enable register +--------------------------- + +Name: INTR_EN_0 +Offset: 0x00002140 +4 bytes, read-write + +Bit 0: CACHE_ERROR (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 4: RUNOUT (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 8: RUNOUT_OVERFLOW (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Config 0 register +----------------- + +Name: CONFIG_0 +Offset: 0x00002200 +4 bytes, read-write + +Hash table register +------------------- + +Hardware hash table offset (in instance memory) and size. + +Name: RAMHT +Offset: 0x00002210 +4 bytes, read-write + +Bits 12-15: BASE_ADDRESS (XV, read-write) + +Bits 16-17: SIZE (XV, read-write) + 4K 0x0 (default, read-write) + 8K 0x1 (read-write) + 16K 0x2 (read-write) + 32K 0x3 (read-write) + +FIFO context table offset +------------------------- + +Name: RAMFC +Offset: 0x00002214 +4 bytes, read-write + +Bits 9-15: BASE_ADDRESS (XV, read-write) + +Runout table register +--------------------- + +FIFO runout table offset and size. + +Name: RAMRO +Offset: 0x00002218 +4 bytes, read-write + +Bits 9-15: BASE_ADDRESS (XV, read-write) + +Bit 16: SIZE (XV, read-write) + 512 0x0 (default, read-write) + 8K 0x1 (read-write) + +Runout status register +---------------------- + +Name: RUNOUT_STATUS +Offset: 0x00002400 +4 bytes, read-only + +Runout put register +------------------- + +Index in runout table. + +Name: RUNOUT_PUT +Offset: 0x00002410 +4 bytes, read-write + +Runout get register +------------------- + +Index in runout table. + +Name: RUNOUT_GET +Offset: 0x00002420 +4 bytes, read-write + +Caches register +--------------- + +Name: CACHES +Offset: 0x00002500 +4 bytes, read-write + +Bit 0: REASSIGN (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Cache 0 push 0 register +----------------------- + +Name: CACHE0_PUSH0 +Offset: 0x00003000 +4 bytes, read-write + +Bit 0: ACCESS (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Cache 0 push 1 register +----------------------- + +Name: CACHE0_PUSH1 +Offset: 0x00003004 +4 bytes, read-write + +Bits 0-6: CHID (XU, read-write) + +Cache 0 pull 0 register +----------------------- + +Name: CACHE0_PULL0 +Offset: 0x00003040 +4 bytes, read-write + +Bit 0: ACCESS (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Cache 1 push 0 register +----------------------- + +Name: CACHE1_PUSH0 +Offset: 0x00003200 +4 bytes, read-write + +Bit 0: ACCESS (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Cache 1 push 1 register +----------------------- + +Name: CACHE1_PUSH1 +Offset: 0x00003204 +4 bytes, read-write + +Bits 0-6: CHID (XU, read-write) + +Cache 1 put register +-------------------- + +Name: CACHE1_PUT +Offset: 0x00003210 +4 bytes, read-write + +Bits 2-6: ADDRESS (XU, read-write) + +Cache 1 DMA 0 register +----------------------- + +Name: CACHE1_DMA0 +Offset: 0x00003220 +4 bytes, read-write + +Cache 1 DMA 1 register +----------------------- + +Name: CACHE1_DMA1 +Offset: 0x00003224 +4 bytes, read-write + +Cache 1 DMA 2 register +----------------------- + +Name: CACHE1_DMA2 +Offset: 0x00003228 +4 bytes, read-write + +Cache 1 pull 0 register +----------------------- + +Name: CACHE1_PULL0 +Offset: 0x00003240 +4 bytes, read-write + +Bit 0: ACCESS (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Cache 1 pull 1 register +----------------------- + +Name: CACHE1_PULL1 +Offset: 0x00003250 +4 bytes, read-write + +Bit 4: CTX (XV, read-write) + CLEAN 0x0 (read-write) + DIRTY 0x1 (read-write) + +Cache 1 get register +-------------------- + +Name: CACHE1_GET +Offset: 0x00003270 +4 bytes, read-write + +Bits 2-6: ADDRESS (XU, read-write) + +Cache 1 context registers +------------------------- + +8 context registers for each channel (I guess). + +Name: CACHE1_CTX +Offset: 0x00003280+i*16 (0 <= i < 8) +8*16(4?) bytes, read-write + + + +Framebuffer properties +====================== + +The FB registers begin at 0x00100000 in the CTRL region. + +Boot 0 register +--------------- + +Name: BOOT_0 +Offset: 0x00100000 +4 bytes, read-write + +Bits 0-1: RAM_AMOUNT (IV, read-write) + 1MB 0x0 (read-write) + 2MB 0x1 (read-write) + 4MB 0x2 (read-write) + 8MB 0x0 (read-write) + UNDEFINED 0x3 (read-write) + DEFAULT 0x2 (default, read-write) + +Bit 2: RAM_WIDTH_128 (-V, read-write) + OFF 0x0 (read-write) + ON 0x1 (read-write) + +Bit 3: RAM_BANKS (IV, read-write) + 2BANK 0x0 (default, read-write) + 4BANK 0x1 (read-write) + +Bit 4: RAMDATA_TWIDDLE (IV, read-write) + OFF 0x0 (default, read-write) + ON 0x1 (read-write) + +Bit 5: RAM_AMOUNT_EXTENSION (IV, read-write) + OFF 0x0 (default, read-write) + 8MB 0x1 (read-write) + +Delay 1 register +---------------- + +Name: DELAY_1 +Offset: 0x00100044 +4 bytes, read-write + +Bits 0-1: WRITE_ENABLE_RISE (IU, read-write) + WRITE_ENABLE_RISE_0 0x0 (default, read-write) + +Bits 4-5: WRITE_ENABLE_FALL (IU, read-write) + WRITE_ENABLE_FALL_0 0x0 (default, read-write) + +Bits 8-9: CAS_ENABLE_RISE (IU, read-write) + CAS_ENABLE_RISE_0 0x0 (default, read-write) + +Bits 12-13: CAS_ENABLE_FALL (IU, read-write) + CAS_ENABLE_FALL_0 0x0 (default, read-write) + +Bits 16-17: OUTPUT_DATA (IU, read-write) + OUTPUT_DATA_0 0x0 (default, read-write) + +Bits 20-21: RAS_ENABLE (IU, read-write) + RAS_ENABLE_0 0x0 (default, read-write) + +Debug 0 register +---------------- + +Name: DEBUG_0 +Offset: 0x00100080 +4 bytes, read-write + +Bit 4: REFRESH (IV, read-write) + ENABLED 0x0 (default, read-write) + DISABLED 0x1 (read-write) + +Green 0 register +---------------- + +Name: GREEN_0 +Offset: 0x001000C0 +4 bytes, read-write + +Bits 0-1: LEVEL (IV, read-write) + VIDEO_ENABLED 0x0 (read-write) + VIDEO_DISABLED 0x1 (read-write) + TIMING_DISABLED 0x2 (read-write) + MEMORY_DISABLED 0x3 (default, read-write) + +Config 0 register +----------------- + +Name: CONFIG_0 +Offset: 0x00100200 +4 bytes, read-write + +Bits 0-5: RESOLUTION (IV, read-write) + 320_PIXELS 0x0a (read-write) + 400_PIXELS 0x0d (read-write) + 480_PIXELS 0x0f (read-write) + 512_PIXELS 0x10 (read-write) + 640_PIXELS 0x14 (read-write) + 800_PIXELS 0x19 (read-write) + 960_PIXELS 0x1e (read-write) + 1024_PIXELS 0x20 (read-write) + 1152_PIXELS 0x24 (read-write) + 1280_PIXELS 0x28 (read-write) + 1600_PIXELS 0x32 (read-write) + DEFAULT 0x14 (default, read-write) + +Bits 8-9: PIXEL_DEPTH (IV, read-write) + 8_BITS 0x1 (read-write) + 16_BITS 0x2 (read-write) + 32_BITS 0x3 (read-write) + DEFAULT 0x1 (default, read-write) + +Bit 12: TILING (IV, read-write) + ENABLED 0x0 (read-write) + DISABLED 0x1 (default, read-write) + + +Bits 13-23: TILING_DEBUG (IV, read-write) + DISABLED 0x0 (read-write) + +RTL(?) register +--------------- + +Name: RTL +Offset: 0x00100??? +4 bytes, read-write + +Bits 0-1: S (IU, read-write) + DEFAULT 0x2 (default, read-write) + +Bits 4-5: V (IU, read-write) + DEFAULT 0x2 (default, read-write) + +Bits 8-9: M (IU, read-write) + DEFAULT 0x2 (default, read-write) + +Bits 12-13: H (IU, read-write) + DEFAULT 0x1 (default, read-write) + +Bits 16-17: A (IU, read-write) + DEFAULT 0x1 (default, read-write) + +Bits 20-21: G (IU, read-write) + DEFAULT 0x1 (default, read-write) + +Bit 24: ARB_GR_HI_PRIOR (IU, read-write) + DEFAULT 0x0 (default, read-write) + +Bit 28: ARB_MEDIA_HI_PRIOR (IU, read-write) + DEFAULT 0x0 (default, read-write) + + + +External devices +================ + +The EXTDEV registers begin at 0x00101000 in the CTRL region. + +Boot 0 register +--------------- + +Name: BOOT_0 +Offset: 0x00101000 +4 bytes, read-write + +Bit 2: STRAP_RAM_TYPE (XV, read-write) + SGRAM_8MBIT 0x1 (read-write) + SGRAM_16MBIT 0x0 (read-write) + +Bit 11: STRAP_OVERWRITE (IV, read-write) + ENABLED 0x1 (read-write) + +Bit 4: STRAP_RAM_WIDTH (XV, read-write) + 64 0x0 (read-write) + 128 0x1 (read-write) + + + +GRAPH +===== + +The GRAPH registers begin at 0x00400000 in the CTRL region. + +Debug 0 register +---------------- + +Name: DEBUG_0 +Offset: 0x00400080 +4 bytes, read-write + +Bit 0: STATE (-V, clear(check?)-write) + NORMAL 0x0 (clear(check?)-write) + RESET 0x1 (write-only) + +Bit 4: BULK_READS (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 20: WRITE_ONLY_ROPS_2D (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 24: DRAWDIR_AUTO (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Debug 1 register +---------------- + +Name: DEBUG_1 +Offset: 0x00400084 +4 bytes, read-write + +Bit 0: VOLATILE_RESET (IV, read-write) + NOT_LAST 0x0 (default, read-write) + LAST 0x1 (read-write) + +Bit 16: INSTANCE (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 20: CTX (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Debug 2 register +---------------- + +Name: DEBUG_2 +Offset: 0x00400088 +4 bytes, read-write + +Bit 0: AVOID_RMW_BLEND (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 8: DPWR_FIFO (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Bit 28: VOLATILE_RESET (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Debug 3 register +---------------- + +Name: DEBUG_3 +Offset: 0x0040008C +4 bytes, read-write + +Bit 24: HONOR_ALPHA (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Interrupt 0 register +-------------------- + +Name: INTR_0 +Offset: 0x00400100 +4 bytes, read-write + +Bit 0: RESERVED (-V, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 4: CONTEXT_SWITCH (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 8: VBLANK (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 12: RANGE (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 16: METHOD_COUNT (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 20: FORMAT (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 24: COMPLEX_CLIP (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 28: NOTIFY (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Interrupt 1 register +-------------------- + +Name: INTR_1 +Offset: 0x00400104 +4 bytes, read-write + +Bit 0: METHOD (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 4: DATA (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 12: DOUBLE_NOTIFY (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 16: CTXSW_NOTIFY (IV, read-write) + NOT_PENDING 0x0 (default, read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Interrupt 0 enable register +--------------------------- + +Name: INTR_EN_0 +Offset: 0x00400140 +4 bytes, read-write + +Interrupt 1 enable register +--------------------------- + +Name: INTR_EN_1 +Offset: 0x00400144 +4 bytes, read-write + +Context switch register +----------------------- + +Name: CTX_SWITCH +Offset: 0x00400180 +4 bytes, read-write + +Context control register +------------------------ + +Name: CTX_CONTROL +Offset: 0x00400190 +4 bytes, read-write + +Bits 0-1: MINIMUM_TIME (IV, read-write) + 33US 0x0 (default, read-write) + 262US 0x1 (read-write) + 2MS 0x2 (read-write) + 17MS 0x3 (read-write) + +Bit 8: TIME (IV, read-write) + EXPIRED 0x0 (default, read-write) + NOT_EXPIRED 0x1 (read-write) + +Bit 16: CHID (IV, read-write) + INVALID 0x0 (default, read-write) + VALID 0x1 (read-write) + +Bit 20: SWITCH (-V, read-only) + UNAVAILABLE 0x0 (read-only) + AVAILABLE 0x1 (read-only) + +Bit 24: SWITCHING (IV, read-write) + IDLE 0x0 (default, read-write) + BUSY 0x1 (read-write) + +Bit 28: DEVICE (IV, read-write) + DISABLED 0x0 (default, read-write) + ENABLED 0x1 (read-write) + +Context user register +--------------------- + +Name: CTX_USER +Offset: 0x00400194 +4 bytes, read-write + +Context cache registers +----------------------- + +8 context registers for each channel (I guess). + +Name: CTX_CACHE +Offset: 0x004001a0+i*4 (0 <= i 8) +8*4 bytes, read-write + +Absolute X RAM registers +------------------------ + +Name: ABS_X_RAM +Offset: 0x00400400+i*4 (0 <= i < 32) +32*4 bytes, read-write + +Absolute Y RAM registers +------------------------ + +Name: ABS_Y_RAM +Offset: 0x00400480+i*4 (0 <= i < 32) +32*4 bytes, read-write + +X misc register +--------------- + +Name: X_MISC +Offset: 0x00400500 +4 bytes, read-write + +Y misc register +--------------- + +Name: Y_MISC +Offset: 0x00400504 +4 bytes, read-write + +Exceptions register +------------------- + +Name: EXCEPTIONS +Offset: 0x00400508 +4 bytes, read-write + +Source color register +--------------------- + +Name: SOURCE_COLOR +Offset: 0x0040050C +4 bytes, read-write + +XY logic misc 0 register +------------------------ + +Name: XY_LOGIC_MISC0 +Offset: 0x00400514 +4 bytes, read-write + +XY logic misc 1 register +------------------------ + +Name: XY_LOGIC_MISC1 +Offset: 0x00400518 +4 bytes, read-write + + DVDY_VALUE 0x0 (default, read-write) (???) + +XY logic misc 2 register +------------------------ + +Name: XY_LOGIC_MISC2 +Offset: 0x0040051C +4 bytes, read-write + +XY logic misc 3 register +------------------------ + +Name: XY_LOGIC_MISC3 +Offset: 0x00400520 +4 bytes, read-write + +Clip X 0 register +----------------- + +Name: CLIPX_0 +Offset: 0x00400524 +4 bytes, read-write + +Clip X 1 register +----------------- + +Name: CLIPX_1 +Offset: 0x00400528 +4 bytes, read-write + +Clip Y 0 register +----------------- + +Name: CLIPY_0 +Offset: 0x0040052c +4 bytes, read-write + +Clip Y 1 register +----------------- + +Name: CLIPY_1 +Offset: 0x00400530 +4 bytes, read-write + +Absolute iclip X max. register +------------------------------ + +Name: ABS_ICLIP_XMAX +Offset: 0x00400534 +4 bytes, read-write + +Absolute iclip Y max. register +------------------------------ + +Name: ABS_ICLIP_YMAX +Offset: 0x00400538 +4 bytes, read-write + +Absolute uclip X min. register +------------------------------ + +Name: ABS_UCLIP_XMIN +Offset: 0x0040053C +4 bytes, read-write + +Absolute uclip Y min. register +------------------------------ + +Name: ABS_UCLIP_YMIN +Offset: 0x00400540 +4 bytes, read-write + +Absolute uclip X max. register +------------------------------ + +Name: ABS_UCLIP_XMAX +Offset: 0x00400544 +4 bytes, read-write + +Absolute uclip Y max. register +------------------------------ + +Name: ABS_UCLIP_YMAX +Offset: 0x00400548 +4 bytes, read-write + +Absolute uclipa X min. register +------------------------------ + +Name: ABS_UCLIPA_XMIN +Offset: 0x00400560 +4 bytes, read-write + +Absolute uclipa Y min. register +------------------------------ + +Name: ABS_UCLIPA_YMIN +Offset: 0x00400564 +4 bytes, read-write + +Absolute uclipa X max. register +------------------------------ + +Name: ABS_UCLIPA_XMAX +Offset: 0x00400568 +4 bytes, read-write + +Absolute uclipa Y max. register +------------------------------ + +Name: ABS_UCLIPA_YMAX +Offset: 0x0040056C +4 bytes, read-write + +Source canvas min. register +--------------------------- + +Name: SRC_CANVAS_MIN +Offset: 0x00400550 +4 bytes, read-write + +Source canvas max. register +--------------------------- + +Name: SRC_CANVAS_MAX +Offset: 0x00400554 +4 bytes, read-write + +Destination canvas min. register +-------------------------------- + +Name: DST_CANVAS_MIN +Offset: 0x00400558 +4 bytes, read-write + +Destination canvas max. register +-------------------------------- + +Name: DST_CANVAS_MAX +Offset: 0x0040055C +4 bytes, read-write + +Pattern color 0 0 register +-------------------------- + +Name: PATT_COLOR0_0 +Offset: 0x00400600 +4 bytes, read-write + +Pattern color 0 1 register +-------------------------- + +Name: PATT_COLOR0_1 +Offset: 0x00400604 +4 bytes, read-write + +Pattern color 1 0 register +-------------------------- + +Name: PATT_COLOR1_0 +Offset: 0x00400608 +4 bytes, read-write + +Pattern color 1 1 register +-------------------------- + +Name: PATT_COLOR1_1 +Offset: 0x0040060C +4 bytes, read-write + +Pattern registers +----------------- + +Name: PATTERN +Offset: 0x00400610+i*4 (0 <=i < 2) +2*4 bytes, read-write + +Pattern shape register +---------------------- + +Name: PATTERN_SHAPE +Offset: 0x00400618 +4 bytes, read-write + +Bits 0-1: VALUE (XV, read-write) + 8X8 0x0 (read-write) + 64X1 0x1 (read-write) + 1X64 0x2 (read-write) + +Monochrome color 0 register +--------------------------- + +Name: MONO_COLOR0 +Offset: 0x0040061C +4 bytes, read-write + +Raster operation register +------------------------- + +Name: ROP3 +Offset: 0x00400624 +4 bytes, read-write + +Plane mask register +------------------- + +Name: PLANE_MASK +Offset: 0x00400628 +4 bytes, read-write + +Chroma register +--------------- + +Name: CHROMA +Offset: 0x0040062C +4 bytes, read-write + +B(?) offset 0 register +---------------------- + +Name: BOFFSET0 +Offset: 0x00400630 +4 bytes, read-write + +B(?) offset 1 register +---------------------- + +Name: BOFFSET1 +Offset: 0x00400634 +4 bytes, read-write + +B(?) offset 2 register +---------------------- + +Name: BOFFSET2 +Offset: 0x00400638 +4 bytes, read-write + +B(?) offset 3 register +---------------------- + +Name: BOFFSET3 +Offset: 0x0040063C +4 bytes, read-write + +Beta register +------------- + +Name: BETA +Offset: 0x00400640 +4 bytes, read-write + +Control out register +-------------------- + +Name: CONTROL_OUT +Offset: 0x00400644 +4 bytes, read-write + +B(?) pitch 0 register +--------------------- + +Name: BPITCH0 +Offset: 0x00400650 +4 bytes, read-write + +B(?) pitch 1 register +--------------------- + +Name: BPITCH1 +Offset: 0x00400654 +4 bytes, read-write + +B(?) pitch 2 register +--------------------- + +Name: BPITCH2 +Offset: 0x00400658 +4 bytes, read-write + +B(?) pitch 3 register +--------------------- + +Name: BPITCH3 +Offset: 0x0040065C +4 bytes, read-write + +DMA register +------------ + +Name: DMA +Offset: 0x00400680 +4 bytes, read-write + +Notify register +--------------- + +Name: NOTIFY +Offset: 0x00400684 +4 bytes, read-write + +Bits 0-15: INST_MEM_LOC ??? + +Instance register +----------------- + +Name: INSTANCE +Offset: 0x00400688 +4 bytes, read-write + +Memory format register +---------------------- + +Name: MEMFMT +Offset: 0x0040068C +4 bytes, read-write + +Clip 0 min. register +-------------------- + +Name: CLIP0_MIN +Offset: 0x00400690 +4 bytes, read-write + +Clip 0 max. register +-------------------- + +Name: CLIP0_MAX +Offset: 0x00400694 +4 bytes, read-write + +Clip 1 min. register +-------------------- + +Name: CLIP1_MIN +Offset: 0x00400698 +4 bytes, read-write + +Clip 1 max. register +-------------------- + +Name: CLIP1_MAX +Offset: 0x0040069C +4 bytes, read-write + +Clip misc register +------------------ + +Name: CLIP_MISC +Offset: 0x004006A0 +4 bytes, read-write + +FIFO register +------------- + +Name: FIFO +Offset: 0x004006A4 +4 bytes, read-write + +Bit 0: ACCESS (IV, read-write) + DISABLED 0x0 (read-write) + ENABLED 0x1 (default, read-write) + +B(?) pixel register +------------------- + +Name: BPIXEL +Offset: 0x004006A8 +4 bytes, read-write + +Bits 0-1: DEPTH0_FMT (XV, read-write) + Y16_BITS 0x0 (read-write) + BITS_8 0x1 (read-write) + BITS_16 0x2 (read-write) + BITS_32 0x3 (read-write) + +Bit 2: DEPTH0 (XV, read-write) + NOT_VALID 0x0 (read-write) + VALID 0x1 (read-write) + +Bits 4-5: DEPTH1_FMT (XV, read-write) + Y16_BITS 0x0 (read-write) + BITS_8 0x1 (read-write) + BITS_16 0x2 (read-write) + BITS_32 0x3 (read-write) + +Bit 6: DEPTH1 (XV, read-write) + NOT_VALID 0x0 (read-write) + VALID 0x1 (read-write) + +Bits 8-9: DEPTH2_FMT (XV, read-write) + Y16_BITS 0x0 (read-write) + BITS_8 0x1 (read-write) + BITS_16 0x2 (read-write) + BITS_32 0x3 (read-write) + +Bit 10: DEPTH2 (XV, read-write) + NOT_VALID 0x0 (read-write) + VALID 0x1 (read-write) + +Bits 12-13: DEPTH3_FMT (XV, read-write) + Y16_BITS 0x0 (read-write) + BITS_8 0x1 (read-write) + BITS_16 0x2 (read-write) + BITS_32 0x3 (read-write) + +Bit 14: DEPTH3 (XV, read-write) + NOT_VALID 0x0 (read-write) + VALID 0x1 (read-write) + +Status register +--------------- + +Name: STATUS +Offset: 0x004006B0 +4 bytes, read-only + +DMA interrupt 0 register +------------------------ + +Name: DMA_INTR_0 +Offset: 0x00401100 +4 bytes, read-write + +Bit 0: INSTANCE (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 4: PRESENT (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 8: PROTECTION (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 12: LINEAR (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +Bit 16: NOTIFY (XV, read-write) + NOT_PENDING 0x0 (read-only) + PENDING 0x1 (read-only) + RESET 0x1 (write-only) + +DMA interrupt 0 enable register +------------------------------- + +Name: DMA_INTR_EN_0 +Offset: 0x00401140 +4 bytes, read-write + +DMA control register +-------------------- + +Name: DMA_CONTROL +Offset: 0x00401210 +4 bytes, read-write + + + +RAMDAC +====== + +The RAMDAC registers begin at 0x00680000 in the CTRL region. + +Graphic cursor starting position register +----------------------------------------- + +Name: GRCURSOR_START_POS +Offset: 0x00680300 +4 bytes, read-write + +Bits 0-11: X (XS, read-write) + +Bits 16-27: Y (XS, read-write) + +MPLL coeff register +------------------- + +Name: MPLL_COEFF +Offset: 0x00680504 +4 bytes, read-write + +Bits 0-7: MDIV (IU, read-write) + +Bits 8-15: NDIV (IU, read-write) + +Bits 16-18: PDIV (IV, read-write) + +VPLL coeff register +------------------- + +Name: VPLL_COEFF +Offset: 0x00680508 +4 bytes, read-write + +Bits 0-7: MDIV (IU, read-write) + +Bits 8-15: NDIV (IU, read-write) + +Bits 16-18: PDIV (IV, read-write) + +PLL coeff select register +------------------------- + +Name: PLL_COEFF_SELECT +Offset: 0x0068050C +4 bytes, read-write + +Bit 4: DLL_BYPASS (IV, read-write) + FALSE 0x0 (default, read-write) + TRUE 0x1 (read-write) + +Bit 8: MPLL_SOURCE (IV, read-write) + DEFAULT 0x0 (default, read-write) + PROG 0x1 (read-write) + +Bit 12: MPLL_BYPASS (IV, read-write) + FALSE 0x0 (default, read-write) + TRUE 0x1 (read-write) + +Bit 16: VPLL_SOURCE (IV, read-write) + DEFAULT 0x0 (default, read-write) + PROG 0x1 (read-write) + +Bit 20: VPLL_BYPASS (IV, read-write) + FALSE 0x0 (default, read-write) + TRUE 0x1 (read-write) + +Bits 24-25: PCLK_SOURCE (IV, read-write) + VPLL 0x0 (default, read-write) + VIP 0x1 (read-write) + XTALOSC 0x2 (read-write) + +Bit 28: VCLK_RATIO (IV, read-write) + DB1 0x0 (default, read-write) + DB2 0x1 (read-write) + +General control register +------------------------ + +Various flags for DAC. BPC controls the width of the palette. + +Name: GENERAL_CONTROL +Offset: 0x00680600 +4 bytes, read-write + +Bits 0-1: FF_COEFF (IV, read-write) + DEF 0x0 (default, read-write) + +Bit 4: IDC_MODE (IV, read-write) + GAMMA 0x0 (default, read-write) + INDEX 0x1 (read-write) + +Bit 8: VGA_STATE (IV, read-write) + NOTSEL 0x0 (default, read-write) + SEL 0x1 (read-write) + +Bit 12: 565_MODE (IV, read-write) + NOTSEL 0x0 (default, read-write) + SEL 0x1 (read-write) + +Bit 16: BLK_PEDSTL (IV, read-write) + OFF 0x0 (default, read-write) + ON 0x1 (read-write) + +Bit 17: TERMINATION (IV, read-write) + 37OHM 0x0 (default, read-write) + 75OHM 0x1 (read-write) + +Bit 20: BPC (IV, read-write) + 6BITS 0x0 (default, read-write) + 8BITS 0x1 (read-write) + +Bit 24: DAC_SLEEP (IV, read-write) + DIS 0x0 (default, read-write) + EN 0x1 (read-write) + +Bit 28: PALETTE_CLK (IV, read-write) + EN 0x0 (default, read-write) + DIS 0x1 (read-write) + +VSERR width register +-------------------- + +Name: VSERR_WIDTH +Offset: 0x00680700 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +VEQU end register +----------------- + +Name: VEQU_END +Offset: 0x00680704 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Vertical B(?) blank end register +-------------------------------- + +Name: VBBLANK_END +Offset: 0x00680708 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Vertical blank end register +--------------------------- + +Name: VBLANK_END +Offset: 0x0068070C +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Vertical blank start register +----------------------------- + +Name: VBLANK_START +Offset: 0x00680710 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Vertical (B?) blank start register +---------------------------------- + +Name: VBBLANK_START +Offset: 0x00680714 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +VEQU start register +------------------- + +Name: VEQU_START +Offset: 0x00680718 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Vertical total register +----------------------- + +Name: VTOTAL +Offset: 0x0068071C +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Horizontal sync width register +------------------------------ + +Name: HSYNC_WIDTH +Offset: 0x00680720 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Horizontal burst start register +------------------------------- + +Name: HBURST_START +Offset: 0x00680724 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Horizontal burst end register +----------------------------- + +Name: HBURST_END +Offset: 0x00680728 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Horizontal blank start register +------------------------------- + +Name: HBLANK_START +Offset: 0x0068072C +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Horizontal blank end register +----------------------------- + +Name: HBLANK_END +Offset: 0x00680730 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +Horizontal total register +------------------------- + +Name: HTOTAL +Offset: 0x00680734 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +HEQU width register +------------------- + +Name: HEQU_WIDTH +Offset: 0x00680738 +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + +HSERR width register +-------------------- + +Name: HSERR_WIDTH +Offset: 0x0068073C +4 bytes, read-write + +Bits 0-10: VAL (IV, read-write) + + + +'Standard' SVGA registers +========================= + +ATTR, CTRC, GRAPH, SEQ and MISC registers are available throught MMIO too. + +Name: ATTR_REG_INDEX +Offset: 0x006013c0 +1 byte, read-write + +Name: ATTR_REG_DATA +Offset: 0x006013c1 +1 byte, read-write + +Name: CRTC_REG_INDEX +Offset: 0x006013d4 +1 byte, read-write + +Name: CRTC_REG_DATA +Offset: 0x006013d5 +1 byte, read-write + +Name: GRA_REG_INDEX +Offset: 0x000C03ce +1 byte, read-write + +Name: GRA_REG_DATA +Offset: 0x000C03cf +1 byte, read-write + +Name: SEQ_REG_INDEX +Offset: 0x000C03c4 +1 byte, read-write + +Name: SEQ_REG_DATA +Offset: 0x000C03c5 +1 byte, read-write + +Name: MISC_REG +Offset: 0x000C03c2 +1 byte, read-write + + + +Extra CRTC registers +==================== + +Repaint 0 register +------------------ + +Extended offset and start address. + +Name: REPAINT0 +Index: 0x19 +1 byte + +Bits 0-4: START_ADDR_20_16 + +Bits 5-7: OFFSET_10_8 + +Repaint 1 register +------------------ + +Various flags. + +Name: REPAINT1 +Index: 0x1a +1 byte + +Bit 1: PALETTE_WIDTH + 8BITS 0x0 + 6BITS 0x1 + +Bit 2: LARGE_SCREEN + DISABLE 0x1 + ENABLE 0x0 ( >= 1280 ) + +Bit 4: COMPATIBLE_TEXT + ENABLE 0x1 + DISABLE 0x0 + +Bit 6: VSYNC + DISABLE 0x1 + ENABLE 0x0 + +Bit 7: HSYNC + DISABLE 0x1 + ENABLE 0x0 + +FIFO control register +--------------------- + +Controls how much data the refresh fifo requests. + +Name: FIFO_CONTROL +Index: 0x1b +1 byte + +Bits 0-2: BURST_LENGTH + BURST_LENGTH_8 0x0 + BURST_LENGTH_32 0x1 + BURST_LENGTH_64 0x2 + BURST_LENGTH_128 0x3 + BURST_LENGTH_256 0x4 + +Bit 7: UNDERFLOW_WARN + +FIFO register +------------- + +When the fifo occupancy falls below *twice* the watermark, +the refresh fifo will start to be refilled. If this value is +too low, you will get junk on the screen. Too high, and performance +will suffer. Watermark in units of 8 bytes. + +Name: FIFO +Index: 0x20 +1 byte + +Bits 0-5: WATERMARK + +Bit 7: RESET + +Extra register +-------------- + +Assorted extra bits. + +Name: EXTRA +Index: 0x25 +1 byte + +Bit 0: VERT_TOTAL_10 + +Bit 1: VERT_DISPLAY_END_10 + +Bit 2: VERT_RETRACE_START_10 + +Bit 3: VERT_BLANK_START_10 + +Bit 4: HORIZ_BLANK_END_6 + +Bit 5: OFFSET_11 + +Pixel register +-------------- + +Controls what the format of the framebuffer is. + +Name: PIXEL +Index: 0x28 +1 byte + +Bits 0-1: FORMAT + VGA 0x0 + 8BPP 0x1 + 16BPP 0x2 + 32BPP 0x3 + +Bits 3-5: TV_HORIZ_ADJUST + +Bit 6: TV_MODE + NTSC 0x0 + PAL 0x1 + +Bit 7: MODE + TV 0x1 + VGA 0x0 + +Horizontal extra register +------------------------- + +Horizonal extended bits. + +Name: HORIZ_EXTRA +Index: 0x2d +1 byte + +Bit 0: DISPLAY_TOTAL_8 + +Bit 1: DISPLAY_END_8 + +Bit 2: HORIZ_BLANK_START_8 + +Bit 3: HORIZ_RETRACE_START_8 + +Bit 4: INTER_HALF_START_8 + +Graphic cursor 0 register +------------------------- + +Name: GRCURSOR0 +Index: 0x30 +1 byte + +Bits 0-5: START_ADDR_21_16 + +Graphic cursor 1 register +------------------------- + +Name: GRCURSOR1 +Index: 0x31 +1 byte + +Bit 0: CURSOR + DISABLE 0x0 + ENABLE 0x1 + +Bit 1: SCAN_DBL + DISABLE 0x0 + ENABLE 0x1 + +Bits 3-7: START_ADDR_15_11 + +EOF diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index b5d4ff44a..89196d5e6 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -7,8 +7,18 @@ * This file is part of the 86Box distribution. * * Defines graphics objects for Nvidia NV3 architecture-based GPU (RIVA 128/RIVA 128 ZX), - * as well as for later GPUs if they use the same objects. + * as well as for later GPUs if they use the same objects. + * Note: These uint32_ts are basically object methods that are being submitted + * They have different names so the user can use them more easily but different versions of the same class can be distinguished + * ALL of these structures HAVE(?) to be a size of exactly 0x2000 bytes because that's what the hashtable expects and they need to actually map + * directly to the PHYSICAL PGRAPH REGISTERS while sitting in RAMHT!!!!. * + * Also, these class IDs don't relate to the internal architecture of the GPU. + * Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of + * classes recognised by the driver. + * This is why the Class IDs you see here are not the same as you may see in other places. + * + * Todo: Is reserved* actually needed? * * * Authors: Connor Hyde @@ -22,54 +32,468 @@ #include #include -/* - Note: These uint32_ts are basically object methods that are being submitted - They have different names so the user can use them more easily but different versions of the same class can be distinguished - - ALL of these structures HAVE to be a size of exactly 0x2000 bytes because that's what the hashtable expects. - - Also, these class IDs don't relate to the internal architecture of the GPU. - Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of - classes recognised by the driver. - - The 3-bit DMA SUBCHANNEL is combined with a 4-bit CLASS ID to get the REAL CLASS ID. There are 32 CLASSES per subchannel and 8 SUBCHANNELS. - - This is why the Class IDs you see here are not the same as you may see in other places. -*/ +// This is slower, but these need to map *****EXACTLY***** to the registers in PGRAPH, +// or everything FUCKS UP +// +// DO NOT REMOVE! DO NOT REMOVE! DO NOT REMOVE! +#pragma pack(push, 1) +// CLass names for debugging extern const char* nv3_class_names[]; -/* Object Class 0x01 (real hardware) +/* Class context switch method */ +typedef struct nv3_class_ctx_switch_method_s +{ + union + { + uint32_t data; + + uint16_t instance; + uint8_t channel_id : 6; + uint16_t reserved : 9; + bool reset_if_volatile; // ???? + } set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; // Required for NV_CLASS Core Functionality + uint32_t set_notify; + +} nv3_class_ctx_switch_method_t; + +/* 32-bit BGRA format colour for 2D acceleration */ +typedef struct nv3_color_32_s +{ + uint8_t b; + uint8_t g; + uint8_t r; + uint8_t a; +} nv3_color_32_t; + +/* A4R4G4B4 */ +typedef struct nv3_color_16_a4r4g4b4_s +{ + uint8_t a : 4; + uint8_t r : 4; + uint8_t g : 4; + uint8_t b : 4; +} nv3_color_16_a4r4g4b4_t; + +/* A1R5G5B5 format */ +typedef struct nv3_color_16_a1r5g5b5_s; +{ + uint8_t a : 1; + uint8_t r : 5; + uint8_t g : 5; + uint8_t b : 5; +} nv3_color_16_a1r5g5b5_t; + +/* 565 format - NV3Tweak */ +typedef struct nv3_color_16_r5g6b5_s +{ + uint8_t r : 5; + uint8_t g : 6; + uint8_t b : 5; +} nv3_color_16_r5g6b5_t; + +/* Generic 16-bit position*/ +typedef struct nv3_position_16_s +{ + union + { + uint32_t pos; + + uint16_t y; + uint16_t x; + } position; +} nv3_position_16_t; + +/* Generic 16-bit size */ +typedef struct nv3_size_16_s +{ + union + { + uint32_t size; + + uint16_t h; + uint16_t w; + } size; +} nv3_size_16_t; + +/* Generic 32-bit colour + 16-bit position */ +typedef struct nv3_color_and_position_16_s +{ + uint32_t color; + nv3_position_16_t points; +} nv3_color_and_position_16_t; + +/* Generic 16-bit clip region */ +typedef struct nv3_clip_16_s +{ + // The bounds of the clipping area. + uint16_t left; + uint16_t top; + uint16_t right; + uint16_t bottom; +} nv3_clip_16_t; + +/* In case your positions weren't HIGH PRECISION enough */ +typedef struct nv3_position_32_s +{ + uint32_t x; + uint32_t y; +} nv3_position_32_t; + +// COLOUR FORMATS + +/* + Object Class 0x01 (real hardware, also 0x41) + 0x12 (drivers) Beta factor */ -typedef struct nv_object_class_001 +typedef struct nv3_object_class_001 { - uint8_t reserved[0xFF]; // Required for NV_CLASS Core Functionality + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; // Required for NV_CLASS Core Functionality + uint32_t set_notify; + uint8_t reserved2[0x1F8]; + uint8_t set_beta_factor_1d31; // 31:31 (?) value, 30:21 fraction + uint8_t reserved3[0x1CFB]; // needs to be 0x2000 bytes // Put the rest of it here } nv3_beta_factor_t; /* -Object Class 0x07 (real hardware) - 0x1E (drivers) -Also 0x47 in context IDs -A rectangle. Wahey! + Object class 0x02 (real hardware) + 0x14/0x43 (drivers) + Also 0x42 in context IDs + Render operation used for things like blending. Appears to be 8-bit i.e. a ROP3 with 256 possible operations. */ -typedef struct nv_object_class_007 +typedef struct nv3_object_class_002 { - uint8_t reserved[0xFF]; // Required for NV_CLASS Core Functionality - uint32_t set_notify_ctx_dma; // Set notifier context for DMA + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0xFF]; uint32_t set_notify; // Set notifier - uint32_t set_image_output; // Set the image output type - uint8_t reserved2[0xF5]; // up to 0x200 - uint32_t set_zeta_output; // Zeta buffer input - uint32_t set_zeta_input; // Zeta buffer input - uint32_t set_color_format; // Color format: 0x100000=15bpp. - uint8_t reserved3[0xF5]; // up to 0x300 + uint8_t reserved2[0x1F8]; + uint8_t rop; // ROP3 (ID = ????????) + uint8_t reserved3[0x1CFB]; // needs to be 0x2000 bytes +} nv3_render_operation_t; - /* THESE ARE ALL THE SAME METHOD */ - uint32_t color_zeta32; // 32-bit zeta buffer color (?) - uint32_t point; // Draw a point i guess - uint8_t reserved4[0x4F3]; // up to 0x7fc - uint32_t control_out; // 7fd-7ff - uint8_t reserved5[0x1800]; // up to 0x2000 +/* + Object class 0x03 (real hardware) + 0x15 (drivers) + Also 0x43 in context IDs + A chroma/color key, like in video editing +*/ +typedef struct nv3_object_class_003 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0xFF]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1F8]; + uint8_t color; // ROP3 (ID = ????????) + uint8_t reserved3[0x1CFB]; // needs to be 0x2000 bytes +} nv3_chroma_key_t; + +/* + Object class 0x04 (real hardware) + 0x15 (drivers) + Also 0x44 in context IDs + Plane mask +*/ +typedef struct nv3_object_class_004 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0xFF]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1F8]; + uint8_t color; // ROP3 (ID = ????????) + uint8_t reserved3[0x1CFB]; // needs to be 0x2000 bytes +} nv3_plane_mask_t; + +/* + Object class 0x05 (real hardware) + 0x19/0x1E/0x47 (drivers) + Also 0x45 in context IDs + Clipping rectangle used for various blitting operations +*/ +typedef struct nv3_object_class_005 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0xFF]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1F4]; + + /* 16-bit precision */ + nv3_position_16_t position; + nv3_size_16_t size; + uint8_t reserved3[0x1CFB]; // needs to be 0x2000 bytes + +} nv3_clipping_rectangle_t; + +/* + Object Class 0x06 (real hardware) + 0x?? (drivers) + Also 0x46 in context IDs + A pattern used for blits. Wahey! +*/ +typedef struct nv3_object_class_006 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0xFF]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x200]; + uint32_t shape; // 0 = 8x8, 1 = 64x1, 2 = 1x64 + uint32_t color0; // Some 32-bit format (BGRA?) + uint32_t color1; // BGRA? + uint32_t pattern[2]; // BGRA? + uint8_t reserved3[0x1CDF]; // needs to be 0x2000 bytes +} nv3_pattern_t; + +/* + Object Class 0x07 (real hardware) + 0x1E (drivers) + Also 0x47 in context IDs + A rectangle. Wahey! +*/ +typedef struct nv3_object_class_007 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1FC]; + uint8_t color; // ROP3 (ID = ????????) + uint8_t reserved3[0xF8]; + nv3_position_16_t position[16]; + nv3_size_16_t size[16]; + uint8_t reserved4[0x1B7F]; } nv3_rectangle_t; + + +/* In case your points weren't colourful enough */ +typedef struct nv3_object_class_008_cpoint_s +{ + uint32_t color; + nv3_position_16_t position; + +} nv3_object_class_008_cpoint_t; + +/* + Object Class 0x08 (real hardware) + 0x1A (drivers) + Also 0x48 in context IDs + A point: the revolutionary 3d graphics technique... +*/ +typedef struct nv3_object_class_008 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1FC]; + uint32_t color; // BGRA? + nv3_position_16_t point[16]; // Boring points + nv3_position_32_t point32[16]; // Allows you to have points with full 32-bit precision + nv3_object_class_008_cpoint_t cpoint[16]; // Allows you to have c o l o r f u l points! + uint8_t reserved3[0x1A7B]; +} nv3_point_t; + +/* Normal line... */ +typedef struct nv3_object_class_009_line_s +{ + nv3_position_16_t start; // presumably unless it's in reverse order...TODO: check the order + nv3_position_16_t end; + +} nv3_object_class_009_line_t; + +/* THIRTY TWO BIT PRECISION line */ +typedef struct nv3_object_class_009_line32_s +{ + uint32_t x0; + uint32_t x1; + uint32_t y0; + uint32_t y1; +} nv3_object_class_009_line32_t; + +/* nv3_object_class_009_polyline_t not implemented because it's just a duplicate of nv3_object_class_009_line */ +/* nv3_object_class_009_polyline32_t not implemented because it's just a duplicate of nv3_object_class_009_line32 */ + + +/* + Object Class 0x09 (real hardware) + 0x1B (drivers) + Also 0x49 in context IDs + It's a line, but also a polygon... +*/ +typedef struct nv3_object_class_009 +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1FC]; + uint32_t color; // BGRA? + nv3_object_class_009_line_t line[16]; // List of line points (...) + nv3_object_class_009_line32_t line32[8]; + nv3_object_class_009_line_t polyline[32]; + nv3_object_class_009_line32_t polyline32[16]; + nv3_color_and_position_16_t cpolyline[16]; // List of line points and colours. + + uint8_t reserved3[0x197b]; +} nv3_line_t; + +/* + Object Class 0x0A (real hardware) + 0x1c (drivers) + Also 0x4a in context IDs + + This one is where nvidia reinvents the line, but without the starting or ending pixel. + Seriously. +*/ +typedef struct nv3_object_class_00A +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1FC]; + uint32_t color; // BGRA? + nv3_object_class_009_line_t line[16]; // List of line points (...) + nv3_object_class_009_line32_t line32[8]; + nv3_object_class_009_line_t polyline[32]; + nv3_object_class_009_line32_t polyline32[16]; + nv3_color_and_position_16_t cpolyline[16]; // List of line points and colours. + + uint8_t reserved3[0x197b]; +} nv3_lin_t; + +/* + Object Class 0x0B (real hardware) + 0x?? (drivers) + Also 0x4b in context IDs. + + This is a triangle but seems to be obsolete. It's replaced with UD3D0Z / D3D5 Accelerated Triangle with Zeta Buffer. Does it even exist? +*/ +typedef struct nv3_object_class_00B +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1FC]; + uint32_t color; // BGRA? + uint8_t reserved3[0x8]; + // The points of the triangle. + nv3_position_16_t points[3]; + + // Another way of filling out the points of the triangle + uint32_t x0; + uint32_t y0; + uint32_t x1; + uint32_t y1; + uint32_t y2; + uint32_t x2; + + nv3_position_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? + nv3_position_32_t mesh32[16]; + nv3_color_and_position_16_t ctriangle[3]; // Triangle with colour + nv3_color_and_position_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours + uint8_t reserved4[0x19FB]; +} nv3_triangle_t; + +typedef struct nv3_object_class_00C_nclip_s +{ + nv3_position_16_t position; + nv3_size_16_t size; +} nv3_object_class_00C_nclip_t; + +/* + Object Class 0x0C (real hardware) + 0x0C (drivers) + Also 0x4C in context IDs. + + GDI text acceleration for Windows 95. + How the fuck does this even work? +*/ +typedef struct nv3_object_class_00C +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x2F4]; + uint32_t color_a; // Color for Clip A + nv3_object_class_00C_nclip_t rect_nclip[64]; + uint8_t reserved3[0x1F0]; + nv3_clip_16_t clip_b; + uint32_t color_b; // Color for Clip B + nv3_clip_16_t rect_clip[64]; + uint8_t reserved4[0x1E8]; + nv3_clip_16_t clip_c; + uint32_t color1_c; + nv3_size_16_t size_c; + nv3_position_16_t point_c; + uint32_t color1_c_bitmap[128]; + uint8_t reserved5[0x368]; + nv3_clip_16_t clip_d; + uint32_t color1_d; + nv3_size_16_t size_in_d; + nv3_size_16_t size_out_d; + nv3_position_16_t point_d; + uint32_t mono_color1_d[128]; + uint8_t reserved6[0x364]; + nv3_clip_16_t clip_e; + uint32_t color0_e; + uint32_t color1_e; + nv3_size_16_t size_in_e; + nv3_size_16_t size_out_e; + nv3_position_16_t point_e; + uint32_t mono_color1_e[128]; + uint8_t reserved7[0xB7F]; +} nv3_win95_text_t; + + +/* + Object Class 0x0D (real hardware) + 0x?? (drivers) + Also 0x4D in context IDs. + + Represents reformatting of an image in memory. +*/ +typedef struct nv3_object_class_00D +{ + uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved2[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved3[0x204]; + uint32_t offset_in; + uint32_t offset_out; + uint32_t pitch_in; + uint32_t pitch_out; + uint32_t line_length_in; // Stride? + uint32_t line_count; + uint8_t format_input_bits; // 1 2 or 4 to increment by bits + uint8_t format_output_bits; // 1 2 to 4 to increment by bits + uint8_t reserved4[2]; + uint32_t buffer_notify; // Notify the Buffedr + uint8_t reserved5[0x1CD3]; +} nv3_memory_to_memory_format; + + + +/* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? + They are making it look like a bitfield but it's hex? + + THEY ARE ALL LITTLE ENDIAN +*/ +typedef enum nv3_object_class_01C_pixel_format_e +{ + // Y8P4 + // 12-bits (Y8 - Planar YUV 8 bits (Y value only), 4 bits of indexed colour too? + nv3_m2mt_pixel_format_le_y8_p4 = 0x1010000, + + // Y16P2 + // 16-bits (Y16) - Planar YUV 16 bits (Y value only), 2 bits of indexed colour too? + nv3_m2mt_pixel_format_le_y16_p2 = 0x1010101, + + /* 1 unused bit, 555 15-bit format, p2(?) + */ + nv3_m2mt_pixel_format_x1r5g5b5_p2 = 0x1000000, + + // X8G8B8R8, 24-bit colour (or 24-bit colour with alpha) + nv3_m2mt_pixel_format_x8g8b8r8 = 0x1, +} nv3_object_class_01C_pixel_format; + +// TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! +#pragma pack(pop) // return packing to whatever it was before this disaster \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 3e69b57fd..0b6e6b0eb 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -7,7 +7,7 @@ * This file is part of the 86Box distribution. * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated 1 January 2025 (STILL WORKING ON IT) + * Last updated 2 January 2025 (STILL WORKING ON IT) * * * @@ -603,8 +603,10 @@ extern const device_config_t nv3_config[]; /* STRUCTURES FOR THE GPU START HERE + OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H */ + //todo: pixel format // Master Control From da14dfb9700ea04de60b651536a69eb9dab6d76b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 3 Jan 2025 01:08:04 +0000 Subject: [PATCH 044/274] actually use the ctx_switch structure --- .../86box/nv/classes/vid_nv3_classes.h | 28 +++++++++---------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 89196d5e6..78d9a46a0 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -53,8 +53,6 @@ typedef struct nv3_class_ctx_switch_method_s uint16_t reserved : 9; bool reset_if_volatile; // ???? } set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved[0x100]; // Required for NV_CLASS Core Functionality - uint32_t set_notify; } nv3_class_ctx_switch_method_t; @@ -150,7 +148,7 @@ typedef struct nv3_position_32_s */ typedef struct nv3_object_class_001 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; // Required for NV_CLASS Core Functionality uint32_t set_notify; uint8_t reserved2[0x1F8]; @@ -167,7 +165,7 @@ typedef struct nv3_object_class_001 */ typedef struct nv3_object_class_002 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0xFF]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F8]; @@ -183,7 +181,7 @@ typedef struct nv3_object_class_002 */ typedef struct nv3_object_class_003 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0xFF]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F8]; @@ -199,7 +197,7 @@ typedef struct nv3_object_class_003 */ typedef struct nv3_object_class_004 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0xFF]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F8]; @@ -215,7 +213,7 @@ typedef struct nv3_object_class_004 */ typedef struct nv3_object_class_005 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0xFF]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F4]; @@ -235,7 +233,7 @@ typedef struct nv3_object_class_005 */ typedef struct nv3_object_class_006 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0xFF]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x200]; @@ -254,7 +252,7 @@ typedef struct nv3_object_class_006 */ typedef struct nv3_object_class_007 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; @@ -282,7 +280,7 @@ typedef struct nv3_object_class_008_cpoint_s */ typedef struct nv3_object_class_008 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; @@ -322,7 +320,7 @@ typedef struct nv3_object_class_009_line32_s */ typedef struct nv3_object_class_009 { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; @@ -346,7 +344,7 @@ typedef struct nv3_object_class_009 */ typedef struct nv3_object_class_00A { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; @@ -369,7 +367,7 @@ typedef struct nv3_object_class_00A */ typedef struct nv3_object_class_00B { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; @@ -409,7 +407,7 @@ typedef struct nv3_object_class_00C_nclip_s */ typedef struct nv3_object_class_00C { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x2F4]; @@ -453,7 +451,7 @@ typedef struct nv3_object_class_00C */ typedef struct nv3_object_class_00D { - uint32_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved2[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved3[0x204]; From 98ec3823c63ff4c6ee1ca84217e9e671fa12ab2a Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 3 Jan 2025 12:39:46 +0000 Subject: [PATCH 045/274] begni working on scaled image from memory def so that we can sync --- src/include/86box/nv/classes/vid_nv3_classes.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 78d9a46a0..d7086afc0 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -466,9 +466,19 @@ typedef struct nv3_object_class_00D uint8_t reserved4[2]; uint32_t buffer_notify; // Notify the Buffedr uint8_t reserved5[0x1CD3]; -} nv3_memory_to_memory_format; - +} nv3_memory_to_memory_format_t; +/* + Object Class 0x0E (real hardware) + 0x?? (drivers) + Also 0x4E in context IDs. + + Represents a scaled image coming from memory. +*/ +typedef struct nv3_object_class_00E +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; +} nv3_scaled_image_from_memory_t; /* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? They are making it look like a bitfield but it's hex? From 324c25978d30556c203a349b3b6c8459050c92d5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 4 Jan 2025 02:01:23 +0000 Subject: [PATCH 046/274] fixes to class headers --- .../86box/nv/classes/vid_nv3_classes.h | 41 ++++++++++++------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index d7086afc0..35b704caf 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -98,8 +98,13 @@ typedef struct nv3_position_16_s { uint32_t pos; - uint16_t y; - uint16_t x; + struct vid_nv3_classes + { + uint16_t y; + uint16_t x; + }; + + } position; } nv3_position_16_t; @@ -110,8 +115,13 @@ typedef struct nv3_size_16_s { uint32_t size; - uint16_t h; - uint16_t w; + struct + { + uint16_t h; + uint16_t w; + }; + + } size; } nv3_size_16_t; @@ -166,7 +176,7 @@ typedef struct nv3_object_class_001 typedef struct nv3_object_class_002 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved[0xFF]; + uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F8]; uint8_t rop; // ROP3 (ID = ????????) @@ -182,7 +192,7 @@ typedef struct nv3_object_class_002 typedef struct nv3_object_class_003 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved[0xFF]; + uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F8]; uint8_t color; // ROP3 (ID = ????????) @@ -198,7 +208,7 @@ typedef struct nv3_object_class_003 typedef struct nv3_object_class_004 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved[0xFF]; + uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F8]; uint8_t color; // ROP3 (ID = ????????) @@ -214,7 +224,7 @@ typedef struct nv3_object_class_004 typedef struct nv3_object_class_005 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved[0xFF]; + uint8_t reserved[0X100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1F4]; @@ -234,7 +244,7 @@ typedef struct nv3_object_class_005 typedef struct nv3_object_class_006 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved[0xFF]; + uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x200]; uint32_t shape; // 0 = 8x8, 1 = 64x1, 2 = 1x64 @@ -256,7 +266,7 @@ typedef struct nv3_object_class_007 uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; - uint8_t color; // ROP3 (ID = ????????) + uint32_t color; // The colour uint8_t reserved3[0xF8]; nv3_position_16_t position[16]; nv3_size_16_t size[16]; @@ -452,9 +462,9 @@ typedef struct nv3_object_class_00C typedef struct nv3_object_class_00D { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint8_t reserved2[0x100]; + uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier - uint8_t reserved3[0x204]; + uint8_t reserved2[0x204]; uint32_t offset_in; uint32_t offset_out; uint32_t pitch_in; @@ -463,9 +473,9 @@ typedef struct nv3_object_class_00D uint32_t line_count; uint8_t format_input_bits; // 1 2 or 4 to increment by bits uint8_t format_output_bits; // 1 2 to 4 to increment by bits - uint8_t reserved4[2]; + uint8_t reserved3[2]; uint32_t buffer_notify; // Notify the Buffedr - uint8_t reserved5[0x1CD3]; + uint8_t reserved4[0x1CD3]; } nv3_memory_to_memory_format_t; /* @@ -478,6 +488,9 @@ typedef struct nv3_object_class_00D typedef struct nv3_object_class_00E { nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x200]; } nv3_scaled_image_from_memory_t; /* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? From 6e18a53d27c6161b5bfadf4ea645cab4b965b11a Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 4 Jan 2025 22:38:52 +0000 Subject: [PATCH 047/274] add uscaled --- .../86box/nv/classes/vid_nv3_classes.h | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 35b704caf..39aa600be 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -75,7 +75,7 @@ typedef struct nv3_color_16_a4r4g4b4_s } nv3_color_16_a4r4g4b4_t; /* A1R5G5B5 format */ -typedef struct nv3_color_16_a1r5g5b5_s; +typedef struct nv3_color_16_a1r5g5b5_s { uint8_t a : 1; uint8_t r : 5; @@ -491,6 +491,25 @@ typedef struct nv3_object_class_00E uint8_t reserved[0x100]; uint32_t set_notify; uint8_t reserved2[0x200]; + nv3_position_16_t clip_0; + nv3_size_16_t clip_1; + nv3_position_16_t rectangle_out_0; + nv3_size_16_t rectangle_out_1; + // Calculus in a graphics card + uint32_t delta_du_dx; + uint32_t delta_dv_dy; + uint8_t reserved3[0xE0]; + nv3_size_16_t size; // can be size_y if YUV420 + uint32_t pitch; + uint32_t offset; + uint32_t point; + // YUV420 stuff + uint32_t pitch_yuv420; + uint32_t offset_y; + uint32_t offset_u; + uint32_t offset_v; + uint32_t point_yuv420; + uint8_t reserved4[0x1BE7]; // pad to 0x2000 } nv3_scaled_image_from_memory_t; /* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? From c6f0866509b3438cd9a1e7a791788f8d81fa3a5d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 5 Jan 2025 00:29:35 +0000 Subject: [PATCH 048/274] Define the rest of the object classes. --- .../86box/nv/classes/vid_nv3_classes.h | 563 +++++++++++++++++- src/include/86box/nv/vid_nv3.h | 3 +- 2 files changed, 548 insertions(+), 18 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 39aa600be..a22871beb 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -10,7 +10,8 @@ * as well as for later GPUs if they use the same objects. * Note: These uint32_ts are basically object methods that are being submitted * They have different names so the user can use them more easily but different versions of the same class can be distinguished - * ALL of these structures HAVE(?) to be a size of exactly 0x2000 bytes because that's what the hashtable expects and they need to actually map + * ALL of these structures HAVE(?) to be a size of exactly 0x2000 bytes because that's what the hashtable expects and they need to actually map into the vram address space + * (they are converted to pointers). * directly to the PHYSICAL PGRAPH REGISTERS while sitting in RAMHT!!!!. * * Also, these class IDs don't relate to the internal architecture of the GPU. @@ -57,13 +58,22 @@ typedef struct nv3_class_ctx_switch_method_s } nv3_class_ctx_switch_method_t; /* 32-bit BGRA format colour for 2D acceleration */ -typedef struct nv3_color_32_s +typedef struct nv3_color_bgra_32_s { uint8_t b; uint8_t g; uint8_t r; uint8_t a; -} nv3_color_32_t; +} nv3_color_bgra_32_t; + +/* 32-bit ARGB format colour for internal D3D5 stuff */ +typedef struct nv3_color_argb_32_s +{ + uint8_t r; + uint8_t g; + uint8_t b; + uint8_t a; +} nv3_color_argb_32_t; /* A4R4G4B4 */ typedef struct nv3_color_16_a4r4g4b4_s @@ -128,7 +138,7 @@ typedef struct nv3_size_16_s /* Generic 32-bit colour + 16-bit position */ typedef struct nv3_color_and_position_16_s { - uint32_t color; + nv3_color_argb_32_t color; nv3_position_16_t points; } nv3_color_and_position_16_t; @@ -248,9 +258,9 @@ typedef struct nv3_object_class_006 uint32_t set_notify; // Set notifier uint8_t reserved2[0x200]; uint32_t shape; // 0 = 8x8, 1 = 64x1, 2 = 1x64 - uint32_t color0; // Some 32-bit format (BGRA?) - uint32_t color1; // BGRA? - uint32_t pattern[2]; // BGRA? + uint32_t color0; // Some 32-bit format (argb?) + uint32_t color1; // argb? + uint32_t pattern[2]; // argb? uint8_t reserved3[0x1CDF]; // needs to be 0x2000 bytes } nv3_pattern_t; @@ -262,11 +272,11 @@ typedef struct nv3_object_class_006 */ typedef struct nv3_object_class_007 { - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint8_t reserved[0x100]; - uint32_t set_notify; // Set notifier + uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; - uint32_t color; // The colour + nv3_color_argb_32_t color; // The colour uint8_t reserved3[0xF8]; nv3_position_16_t position[16]; nv3_size_16_t size[16]; @@ -277,9 +287,8 @@ typedef struct nv3_object_class_007 /* In case your points weren't colourful enough */ typedef struct nv3_object_class_008_cpoint_s { - uint32_t color; - nv3_position_16_t position; - + nv3_color_argb_32_t color; // BGRA-format 32-bit color + nv3_position_16_t position; // } nv3_object_class_008_cpoint_t; /* @@ -294,7 +303,7 @@ typedef struct nv3_object_class_008 uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; - uint32_t color; // BGRA? + nv3_color_argb_32_t color; // argb? nv3_position_16_t point[16]; // Boring points nv3_position_32_t point32[16]; // Allows you to have points with full 32-bit precision nv3_object_class_008_cpoint_t cpoint[16]; // Allows you to have c o l o r f u l points! @@ -334,7 +343,7 @@ typedef struct nv3_object_class_009 uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; - uint32_t color; // BGRA? + nv3_color_argb_32_t color; // argb? nv3_object_class_009_line_t line[16]; // List of line points (...) nv3_object_class_009_line32_t line32[8]; nv3_object_class_009_line_t polyline[32]; @@ -358,7 +367,7 @@ typedef struct nv3_object_class_00A uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; - uint32_t color; // BGRA? + nv3_color_argb_32_t color; // argb? nv3_object_class_009_line_t line[16]; // List of line points (...) nv3_object_class_009_line32_t line32[8]; nv3_object_class_009_line_t polyline[32]; @@ -381,7 +390,7 @@ typedef struct nv3_object_class_00B uint8_t reserved[0x100]; uint32_t set_notify; // Set notifier uint8_t reserved2[0x1FC]; - uint32_t color; // BGRA? + nv3_color_argb_32_t color; // argb? uint8_t reserved3[0x8]; // The points of the triangle. nv3_position_16_t points[3]; @@ -512,6 +521,514 @@ typedef struct nv3_object_class_00E uint8_t reserved4[0x1BE7]; // pad to 0x2000 } nv3_scaled_image_from_memory_t; +// (0x0F does not exist) + +/* + Object Class 0x10 (real hardware) + 0x?? (drivers) + Also 0x50 in context IDs. + + Represents a blit. +*/ + +typedef struct nv3_object_class_010 +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x1F8]; + nv3_position_16_t point_in; + nv3_position_16_t point_out; + nv3_size_16_t size; + uint8_t reserved3[0x1CF3]; +} nv3_blit_t; + +/* + Object Class 0x11 (real hardware) + 0x?? (drivers) + Also 0x51 in context IDs. + + Represents an image from the cpu (i guess from system memory) +*/ +typedef struct nv3_object_class_011 +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x1FC]; + nv3_position_16_t point; + nv3_size_16_t size; + nv3_size_16_t size_in; + uint8_t reserved3[0xF0]; + nv3_color_argb_32_t color[32]; // The colour to use + uint8_t reserved4[0x1B7F]; +} nv3_image_t; + +/* + Object Class 0x12 (real hardware) + 0x?? (drivers) + Also 0x52 in context IDs. + + Bitmap from CPU. + It seems the difference is that an image is colour but a +*/ +typedef struct nv3_object_class_012 +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x200]; + nv3_color_argb_32_t color_0; + nv3_color_argb_32_t color_1; + nv3_position_16_t point; // Top left(?) of the bitmap + nv3_size_16_t size; + nv3_size_16_t size_in; + uint32_t monochrome_bitmap[32]; + uint8_t reserved4[0x1B7F]; +} nv3_bitmap_t; + +// 0x13 doesn't exist + +/* + Object Class 0x14 (real hardware) + 0x?? (drivers) + Also 0x54 in context IDs. + + Image Transfer to Memory + It seems the difference is that an image is colour but a bitmap is b&w +*/ +typedef struct nv3_object_class_014 +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x200]; + nv3_position_16_t point; + nv3_size_16_t size; + uint32_t image_pitch; // bytes per row + uint32_t image_start; + uint8_t reserved3[0x1C37]; +} nv3_image_to_memory_t; + +/* + Object Class 0x15 (real hardware) + 0x?? (drivers) + Also 0x55 in context IDs. + + Stretched Image from CPU + Seems to be, by the very large color array, the main class used in 2d acceleration. +*/ +typedef struct nv3_object_class_015 +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x1FC]; + nv3_size_16_t size_in; + uint32_t delta_dx_du; + uint32_t delta_dy_dv; + nv3_position_16_t clip_0; + nv3_size_16_t clip_1; + uint32_t point12d4; /* todo: fraction struct */ + uint8_t reserved3[0xE4]; + uint32_t color[1792]; + // no reserve needed +} nv3_stretched_image_from_cpu_t; + +// 0x16 invalid + +/* + Object Class 0x17 (real hardware) + 0x?? (drivers) + Also 0x57 in context IDs. + + Direct3D 5.0 accelerated triangle with zeta buffer (Not the same as a Zbuffer...) + This is the final boss of this GPU. True horror stands below. +*/ + +// +// NV3 D3D5: TEXTURING & PIXEL FORMATS +// + +typedef enum nv3_d3d5_texture_pixel_format_e +{ + /* + 16-Bit Pixel Format + 5 bits red, 5 bits green, 5 bits alpha, "boolean" alpha + */ + nv3_d3d5_pixel_format_le_a1r5g5b5 = 0, + + /* + 15-Bit Pixel Format (represented as 16) + 1 bit irrelevant, 5 bits red, 5 bits green, 5 bits alpha + */ + nv3_d3d5_pixel_format_le_x1r5g5b5 = 1, + + /* + 16-Bit Pixel Format + 4 bits alpha, 4 bits red, 4 bits green, 4 bits blue + */ + nv3_d3d5_pixel_format_le_a4r4g4b4 = 2, + + /* + 16-Bit Pixel Format + 5 bits red, 6 bits green, 5 bits blue + (Required nv3tweak...) + */ + nv3_d3d5_pixel_format_le_r5g6b5 = 3, + +} nv3_d3d5_texture_pixel_format; + +/* Output format + + The output pixel format...I +*/ +typedef enum nv3_d3d5_output_pixel_format_e +{ + /* + 32-Bit Pixel Format + 8 bits irrelevant, 8 bits red, 8 bits green, 8 bits blue + */ + nv3_d3d5_output_pixel_format_le_x8r8g8b8 = 0, + + /* + 32-Bit Pixel Format + 8 bits irrelevant, 8 bits red, 8 bits green, 8 bits blue + Is this even used?? The riva can't even do 32 bit colour in 3d... + */ + nv3_d3d5_output_pixel_format_le_a8r8g8b8 = 1, + + +} nv3_d3d5_output_pixel_format; + + +/* Texture size + + NOTE: ONLY 256X256 OR LOWER ARE SUPPORTED! 2048X2048X16 TAKES UP ENTIRE VRAM OF RIVA 128 ZX... + I ASSUME THESE ARE INTERNALLY SCALED DOWN +*/ +typedef enum nv3_d3d5_texture_size_e +{ + nv3_d3d5_texture_size_1x1 = 0, + + nv3_d3d5_texture_size_2x2 = 1, + + nv3_d3d5_texture_size_4x4 = 2, + + nv3_d3d5_texture_size_8x8 = 3, + + nv3_d3d5_texture_size_16x16 = 4, + + nv3_d3d5_texture_size_32x32 = 5, + + nv3_d3d5_texture_size_64x64 = 6, + + nv3_d3d5_texture_size_128x128 = 7, + + // Highest size supported natively by hardware? + nv3_d3d5_texture_size_256x256 = 8, + + nv3_d3d5_texture_size_512x512 = 9, + + nv3_d3d5_texture_size_1024x1024 = 10, + + nv3_d3d5_texture_size_2048x2048 = 11, + + +} nv3_d3d5_texture_size; + +/* Texture Wrapping Mode for U/V Coordinate Overflow + +*/ +typedef enum nv3_d3d5_texture_wrap_mode_e +{ + // Map textures in a cylindrical fashion. + nv3_d3d5_texture_wrap_mode_cylindrical = 0, + + // Simply wrap back to the start. + nv3_d3d5_texture_wrap_mode_wrap = 1, + + // Mirror the texture. + nv3_d3d5_texture_wrap_mode_mirror = 2, + + // Clamp to the last border pixel. + nv3_d3d5_texture_wrap_mode_clamp = 3, +} nv3_d3d5_texture_wrap_mode; + + +/* This is blending but isn't really considered to be it in the GPU for some reason + What do we do with out input texel BEFORE processing it? + */ +typedef enum nv3_d3d5_dest_color_interpretation_e +{ + // Do nothing + nv3_d3d5_source_color_normal = 0, + + // Invert Colour + nv3_d3d5_source_color_inverse = 1, + + // Invert Alpha before Processing + nv3_d3d5_source_color_alpha_inverse = 2, + + // Take Alpha as 1 + nv3_d3d5_source_color_alpha_one = 3, + +} nv3_d3d5_dest_color_interpretation; + +// The full texture format structure +typedef struct nv3_d3d5_texture_format_s +{ + uint16_t color_key_color_mask; + bool color_key_enabled : 1; + nv3_d3d5_texture_pixel_format color_format : 2; + nv3_d3d5_texture_size size_min : 4; + nv3_d3d5_texture_size size_max : 4; +} nv3_d3d5_texture_format_t; + +// +// NV3 D3D5: INTERPOLATION +// + +/* + ?????? + Interpolating between mip levels? (or for texture blending) +*/ +typedef enum nv3_d3d5_interpolator_algorithm_e +{ + // Zero-order hold interpolation? + nv3_d3d5_interpolator_zoh = 0, + + // Zero-order hold (microsoft variant)? + nv3_d3d5_interpolator_zoh_ms = 1, + + // Full-order hold interpolation? + nv3_d3d5_interpolator_foh = 2, + +} nv3_d3d5_interpolator_algorithm; + +// +// NV3 D3D5: Z-BUFFER +// + +/* Probably the sorting algorithm */ +typedef enum nv3_d3d5_zbuffer_type_e +{ + // Sort based on linear distance + nv3_d3d5_zbuffer_linear = 0, + + // Sort based on distance from view frustum + nv3_d3d5_zbuffer_screen = 1, + +} nv3_d3d5_zbuffer_type; + +// NV3 D3D5: WRITE CONTROL (SHARED BETWEEN ZETA BUFFER AND ALPHA) +typedef enum nv3_d3d5_buffer_write_control_e +{ + // Never write. + nv3_d3d5_buffer_write_control_never = 0, + + // Only write the alpha. + nv3_d3d5_buffer_write_control_alpha = 1, + + // Write both alpha and the zeta-buffer. + nv3_d3d5_buffer_write_control_alpha_zeta = 2, + + // Write only the zeta-buffer + nv3_d3d5_buffer_write_control_zeta = 3, + + // Write everything (alpha+z+zeta?) + nv3_d3d5_buffer_write_control_always = 4, + + +} nv3_d3d5_buffer_write_control; + +// +// NV3 D3D5: BUFFER COMPARISON (SHARED BETWEEN ZETA BUFFER AND ALPHA CONTROL) +// + +// Todo: Which direction? (i.e. is less than p1 < p2 or p2 < p1!) +typedef enum nv3_d3d5_buffer_comparison_type_e +{ + // !!!ILLEGAL COMPARISON TYPE!!!! + nv3_d3d5_buffer_comparison_illegal = 0, + + // The (depth?) test always fails. + nv3_d3d5_buffer_comparison_always_false = 1, + + // True if less than fail. + nv3_d3d5_buffer_comparison_less_than = 2, + + // The test succeeds if equal. + nv3_d3d5_buffer_comparison_equal = 3, + + // The test succeeds if less or equal. + nv3_d3d5_buffer_comparison_less_or_equal = 4, + + // The test succeeds if greater. + nv3_d3d5_buffer_comparison_greater = 5, + + // The test succeeds if the two elements are equal. + nv3_d3d5_buffer_comparison_not_equal = 6, + + // The test succeeds if greater or equal + nv3_d3d5_buffer_comparison_greater_or_equal = 7, + + // The test always succeeds. + nv3_d3d5_buffer_comparison_always_true = 8, + +} nv3_d3d5_buffer_comparison_type; + +// +// NV3 D3D5: BLENDING +// + +/* Render Operation for Blending */ +typedef enum nv3_d3d5_blend_render_operation_e +{ + nv3_d3d5_blend_render_operation_and = 0, + + nv3_d3d5_blend_add_with_saturation = 1, + +} nv3_d3d5_blend_render_operation; + +typedef enum nv3_d3d5_blend_beta_factor_e +{ + nv3_d3d5_blend_beta_factor_srcalpha = 0, + + nv3_d3d5_blend_beta_factor_zero = 1, + +} nv3_d3d5_blend_beta_factor; + +typedef enum nv3_d3d5_blend_input0_e +{ + nv3_d3d5_blend_input0_srcalpha = 0, + + nv3_d3d5_blend_input0_zero = 1, + +} nv3_d3d5_blend_input0; + +typedef enum nv3_d3d5_blend_input1_e +{ + nv3_d3d5_blend_input1_destalpha = 0, + + nv3_d3d5_blend_input1_zero = 1, + +} nv3_d3d5_blend_input1; + +// +// NV3 D3D5: CULLING +// + +typedef enum nv3_d3d5_culling_algorithm_e +{ + // Don't cull + nv3_d3d5_culling_algorithm_none = 0, + + // Cull Clockwise around view frustum? + nv3_d3d5_culling_algorithm_clockwise = 1, + + // Cull counterclockwise around view frustum? + nv3_d3d5_culling_algorithm_counterclockwise = 2, + +} nv3_d3d5_culling_algorithm; + +/* Specular reflection parameters */ +typedef struct nv3_d3d5_specular_s +{ + uint8_t i0 : 4; + uint8_t i1 : 4; + uint8_t i2 : 4; + uint8_t i3 : 4; + uint8_t i4 : 4; + uint8_t i5 : 4; + uint8_t fog; //table fog emulation? +} nv3_d3d5_specular_t; + +// +// NV3 D3D5: MISC +// +typedef struct nv3_d3d5_texture_filter_s +{ + uint8_t spread_x; + uint8_t spread_y; + uint8_t mipmap; + uint8_t turbo; +} nv3_d3d5_texture_filter_t; + +// +// NV3 D3D5: OUTPUT CONTROL STRUCTURE +// + +/* Output Control for D3D5 Triangles */ +typedef struct nv3_d3d5_control_out_s +{ + nv3_d3d5_interpolator_algorithm ctrl_out_interpolator : 2; + uint8_t reserved : 2; + nv3_d3d5_texture_wrap_mode wrap_u : 2; // Controls wrapping mode of U texture coordinate + nv3_d3d5_texture_wrap_mode wrap_v : 2; // Controls wrapping move of V texture coordinate + nv3_d3d5_output_pixel_format output_pixel_format : 1; + bool reserved2 : 1; + nv3_d3d5_dest_color_interpretation dest_color_interpretation : 2; + nv3_d3d5_culling_algorithm culling_algorithm : 2; + bool reserved3 : 1; + nv3_d3d5_zbuffer_type zbuffer_type : 1; + nv3_d3d5_buffer_comparison_type zeta_buffer_compare : 4; + nv3_d3d5_buffer_write_control zeta_write : 3; + bool reserved4 : 1; + nv3_d3d5_buffer_write_control color_write : 3; + bool reserved5 : 1; + nv3_d3d5_blend_render_operation blend_rop : 1; + nv3_d3d5_blend_input0 blend_input0 : 1; + nv3_d3d5_blend_input1 blend_input1 : 1; +} nv3_d3d5_control_out_t; + +typedef struct nv3_d3d5_alpha_control_s +{ + uint8_t alpha_key; + nv3_d3d5_buffer_comparison_type zeta_buffer_compare : 4; + uint32_t reserved : 20; +} nv3_d3d5_alpha_control_t; + +// +// NV3 D3D5: Triangle Coordinates +// +typedef struct nv3_d3d5_coordinate_s +{ + nv3_d3d5_specular_t specular_reflection_parameters; + nv3_color_bgra_32_t color; // YOU HAVE TO FLIP THE ENDIANNESS. NVIDIA??? WHAT??? + + // Seems more plausible for these specifically to be floats. + // Also makes my life easier... + float x; // X coordinate in 3d space of the triangle + float y; // Y coordinate in 3d space of the triangle + float z; // Z coordinate in 3d space of the triangle + float m; // "Measurement dimension" apparently, allows for more precise measurements. And curves + float u; // U coordinate within texture for the (top left?) of the triangle where sampling starts. + float v; // V coordinate within texture for the (top left?) of the triangle where sampling starts. +} nv3_d3d5_coordinate_t; + +typedef struct nv3_object_class_017 +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1FC]; + uint32_t texture_offset; + nv3_d3d5_texture_format_t texture_format; + nv3_d3d5_texture_filter_t texture_filter; + nv3_color_argb_32_t fog_color; // Alpha is ignored here! + nv3_d3d5_control_out_t control_out; + nv3_d3d5_alpha_control_t alpha_control; + + uint8_t reserved3[0xCE4]; + nv3_d3d5_coordinate_t coordinate_points[128]; // The points wer are rendering. + /* No placeholder needed, it really is that long. */ +} nv3_d3d5_accelerated_triangle_with_zeta_buffer_t; + +/* 0x18, 0x19, 0x1A, 0x1B don't exist */ + + + /* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? They are making it look like a bitfield but it's hex? @@ -535,5 +1052,17 @@ typedef enum nv3_object_class_01C_pixel_format_e nv3_m2mt_pixel_format_x8g8b8r8 = 0x1, } nv3_object_class_01C_pixel_format; +typedef struct nv3_object_class_01C +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint8_t reserved[0x100]; + uint32_t set_notify; // Set notifier + uint8_t reserved2[0x1F8]; + nv3_object_class_01C_pixel_format format; // Completely different from everything else + uint32_t pitch; // 16-bit + uint32_t linear_address; // 22-bit: Linear address in vram. + uint8_t reserved3[0x1C3F]; +} nv3_image_in_memory_t; + // TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! #pragma pack(pop) // return packing to whatever it was before this disaster \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 0b6e6b0eb..72076b64b 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -183,7 +183,6 @@ extern const device_config_t nv3_config[]; #define NV3_PMC_ENABLE_PVIDEO 28 #define NV3_PMC_ENABLE_PVIDEO_ENABLED 0x1 - #define NV3_PMC_END 0xfff // overlaps with CIO #define NV3_CIO_START 0x3b0 // Legacy SVGA Emulation Subsystem #define NV3_CIO_END 0x3df @@ -194,8 +193,10 @@ extern const device_config_t nv3_config[]; #define NV3_PBUS_PCI_END 0x18FF // PCI mirror end #define NV3_PBUS_END 0x1FFF #define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects) + #define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status #define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable + #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 From cdb8635e725828e91599b7def3e651572d9c7c95 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 6 Jan 2025 01:00:16 +0000 Subject: [PATCH 049/274] more defines... --- src/include/86box/nv/vid_nv3.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 72076b64b..5c7ad1d81 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -197,6 +197,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status #define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable +#define NV3_PFIFO_CONFIG_0 0x2200 +#define NV3_PFIFO_CONFIG_0_DMA_FETCH 8 +#define NV3_PFIFO_CONFIG_RAMHT 0x2210 + #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 @@ -669,7 +673,7 @@ typedef struct nv3_pbus_s } nv3_pbus_t; // Command submission to PGRAPH -typedef struct nv_pfifo_s +typedef struct nv3_pfifo_s { uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable @@ -715,6 +719,16 @@ typedef struct nv3_pramdac_s uint32_t hserr_width; // horizontal sync error width } nv3_pramdac_t; +typedef struct nv3_pgraph_context_switch_s +{ + +} nv3_pgraph_context_switch_t; + +typedef struct nv3_pgraph_context_control_s +{ + +} nv3_pgraph_context_control_t; + // Graphics Subsystem typedef struct nv3_pgraph_s { @@ -723,6 +737,8 @@ typedef struct nv3_pgraph_s uint32_t interrupt_status_1; // Interrupt status 1 uint32_t interrupt_enable_1; // Interrupt enable 1 + nv3_pgraph_context_control_t context_control; + nv3_pgraph_context_switch_t context_user_submit; uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE]; // DMA context cache } nv3_pgraph_t; From 108bba522fc25d47d9dbde3c77a726e9f8af7051 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 7 Jan 2025 23:54:56 +0000 Subject: [PATCH 050/274] some more defines --- src/include/86box/nv/vid_nv3.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 5c7ad1d81..0e80eb23b 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -199,7 +199,9 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CONFIG_0 0x2200 #define NV3_PFIFO_CONFIG_0_DMA_FETCH 8 -#define NV3_PFIFO_CONFIG_RAMHT 0x2210 +#define NV3_PFIFO_CONFIG_RAMHT 0x2210 // Hashtable for graphics objects config +#define NV3_PFIFO_CONFIG_RAMRO 0x2214 +#define NV3_PFIFO_CONFIG_RAMFC 0x2218 #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem From 19aa366806a37faeb6f0384aed59224df956d7c0 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 8 Jan 2025 01:59:50 +0000 Subject: [PATCH 051/274] Rough implementation of cyclical logging detection with minimal order 4 and refactor logging system. --- src/86box.c | 213 ++++++++++++++++++++++++++++++++++++-- src/include/86box/86box.h | 5 +- src/video/nv/nv_base.c | 2 +- 3 files changed, 206 insertions(+), 14 deletions(-) diff --git a/src/86box.c b/src/86box.c index 59143a012..fdfdcf1e8 100644 --- a/src/86box.c +++ b/src/86box.c @@ -253,12 +253,37 @@ static volatile atomic_int do_pause_ack = 0; static volatile atomic_int pause_ack = 0; #ifndef RELEASE_BUILD -static char buff[1024]; -static int seen = 0; + +#define LOG_SIZE_BUFFER 1024 /* Log size buffer */ +#define LOG_SIZE_BUFFER_CYCLIC 32 /* Cyclic log size buffer (number of lines that should be cehcked) */ +#define LOG_MINIMUM_REPEAT_ORDER 4 /* Minimum repeat size */ + +static char buff[LOG_SIZE_BUFFER]; +static char cyclic_buff[LOG_SIZE_BUFFER_CYCLIC][LOG_SIZE_BUFFER]; +static int32_t cyclic_last_line = 0; +static int32_t log_cycles = 0; + +static int seen = 0; static int suppr_seen = 1; #endif +/* + Ensures STDLOG is open for pclog_ex and pclog_ex_cyclic +*/ +void +pclog_ensure_stdlog_open() +{ + if (stdlog == NULL) { + if (log_path[0] != '\0') { + stdlog = plat_fopen(log_path, "w"); + if (stdlog == NULL) + stdlog = stdout; + } else + stdlog = stdout; + } +} + /* * Log something to the logfile or stdout. * @@ -270,19 +295,12 @@ void pclog_ex(const char *fmt, va_list ap) { #ifndef RELEASE_BUILD - char temp[1024]; + char temp[LOG_SIZE_BUFFER]; if (strcmp(fmt, "") == 0) return; - if (stdlog == NULL) { - if (log_path[0] != '\0') { - stdlog = plat_fopen(log_path, "w"); - if (stdlog == NULL) - stdlog = stdout; - } else - stdlog = stdout; - } + pclog_ensure_stdlog_open(); vsprintf(temp, fmt, ap); if (suppr_seen && !strcmp(buff, temp)) @@ -299,6 +317,179 @@ pclog_ex(const char *fmt, va_list ap) #endif } + +/* +Starfrost, 7-8 January 2025: + +For RIVA 128 emulation I needed a way to suppress logging if a repeated pattern of the same set of lines were found. + +It doesn't need to be super fast so I don't bother to use an optimised approach. I use iterate from 1 to n/2 and see if a pattern repeats or not. + +Implements a version of the Rabin-Karp algorithm https://en.wikipedia.org/wiki/Rabin%E2%80%93Karp_algorithm +*/ +void +pclog_ex_cyclic(const char* fmt, va_list ap) +{ +#ifndef RELEASE_BUILD + char temp[LOG_SIZE_BUFFER]; + + cyclic_last_line %= LOG_SIZE_BUFFER_CYCLIC; + + vsprintf(temp, fmt, ap); + + pclog_ensure_stdlog_open(); + + strncpy(cyclic_buff[cyclic_last_line], temp, LOG_SIZE_BUFFER); + + uint32_t hashes[LOG_SIZE_BUFFER_CYCLIC] = {0}; + + // Random numbers + uint32_t base = 257; + uint32_t mod = 1000000007; + + uint32_t repeat_order = 0; + bool is_cycle = false; + + // compute the set of hashes for the current log buffer + for (int32_t log_line = 0; log_line < LOG_SIZE_BUFFER_CYCLIC; log_line++) + { + if (cyclic_buff[log_line][0] == '\0') + continue; // skip + + for (int32_t log_line_char = 0; log_line_char < LOG_SIZE_BUFFER; log_line_char++) + { + hashes[log_line] = hashes[log_line] * base + cyclic_buff[log_line][log_line_char] % mod; + } + } + + + // Now see if there are real cycles... + // We implement a minimum repeat size. + for (int32_t check_size = LOG_MINIMUM_REPEAT_ORDER; check_size < LOG_SIZE_BUFFER_CYCLIC / 2; check_size++) + { + //TODO: Log what we need for cycle 1. + //TODO: Command line option that lets us turn off this behaviour. + for (int32_t log_line_to_check = 0; log_line_to_check < check_size; log_line_to_check++) + { + if (hashes[log_line_to_check] == hashes[(log_line_to_check + check_size) % LOG_SIZE_BUFFER_CYCLIC]) + { + repeat_order = check_size; + break; + } + } + + is_cycle = (repeat_order != 0); + + // if there still is a cycle.. + if (is_cycle) + break; + + } + + if (is_cycle) + { + if (cyclic_last_line % repeat_order == 0) + { + log_cycles++; + + if (log_cycles == 1) + fprintf(stdlog, "%s", temp); // allow normal logging + if (log_cycles > 1 && log_cycles < 100) + fprintf(stdlog, "***** Cyclical Log Repeat of Order %d #%d *****\n", repeat_order, log_cycles); + else if (log_cycles == 100) + fprintf(stdlog, "Logged the same cycle 100 times...shutting up until something interesting happens\n"); + } + } + else + { + log_cycles = 0; + fprintf(stdlog, "%s", temp); + } + + cyclic_last_line++; + + /* + This version sucks + bool is_cycle = false; + + uint32_t repeat_order = 0; + + for (int32_t log_line = 0; log_line < (LOG_SIZE_BUFFER_CYCLIC); log_line++) + { + for (int32_t check_size = 1; check_size < (LOG_SIZE_BUFFER_CYCLIC / 2); check_size++) + { + uint32_t log_to_check = log_line + check_size; + + // Loop around + if (log_to_check >= LOG_SIZE_BUFFER_CYCLIC) + log_to_check %= LOG_SIZE_BUFFER_CYCLIC; + + // find an initial repeat + if (cyclic_buff[log_line][0] != '\0' + || cyclic_buff[log_to_check][0] != '\0') + { + if (!strncmp(cyclic_buff[log_line], cyclic_buff[log_to_check], LOG_SIZE_BUFFER)) + { + // now see if there are actually repeats (loop over to the start of the log...) + + int32_t highest_real_loop = 1; + + for (int32_t loop_chk = 1; loop_chk < check_size; loop_chk++) + { + uint32_t log_to_check_1 = log_line + loop_chk; + uint32_t log_to_check_2 = (log_line + loop_chk) + check_size; + + if (log_to_check_1 >= LOG_SIZE_BUFFER_CYCLIC) + log_to_check_1 %= LOG_SIZE_BUFFER_CYCLIC; + + if (log_to_check_2 >= LOG_SIZE_BUFFER_CYCLIC) + log_to_check_2 %= LOG_SIZE_BUFFER_CYCLIC; + + if (!strncmp(cyclic_buff[log_to_check_1], cyclic_buff[log_to_check_2], LOG_SIZE_BUFFER)) + { + is_cycle = true; + repeat_order = check_size; + break; + } + } + + + } + + } + + if (is_cycle) break; + } + + if (is_cycle) break; + } + + if (is_cycle + && cyclic_last_line % repeat_order == 0) + { + log_cycles++; + } + else if (!is_cycle) + log_cycles = 0; + + + if (log_cycles <= 1) + { + strcpy(buff, temp); + fprintf(stdlog, "%s", temp); + } + else + { + if (cyclic_last_line % repeat_order == 0) + fprintf(stdlog, "***** Cyclical Log Repeat %d *****\n", log_cycles); + } + + fflush(stdlog); +*/ +#endif + +} + void pclog_toggle_suppr(void) { diff --git a/src/include/86box/86box.h b/src/include/86box/86box.h index ffa670b7e..e43310149 100644 --- a/src/include/86box/86box.h +++ b/src/include/86box/86box.h @@ -187,8 +187,9 @@ extern int config_changed; /* config has changed */ /* Function prototypes. */ #ifdef HAVE_STDARG_H -extern void pclog_ex(const char *fmt, va_list); -extern void fatal_ex(const char *fmt, va_list); +extern void pclog_ex(const char *fmt, va_list ap); +extern void pclog_ex_cyclic(const char* fmt, va_list ap); +extern void fatal_ex(const char *fmt, va_list ap); #endif extern void pclog_toggle_suppr(void); extern void pclog(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))); diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index da776a721..88cb5208b 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -34,7 +34,7 @@ void nv_log(const char *fmt, ...) if (nv_do_log) { va_start(ap, fmt); - pclog_ex(fmt, ap); + pclog_ex_cyclic(fmt, ap); va_end(ap); } } From 39419ae95638c449087dfcc9fc0bd038732b86a6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 9 Jan 2025 02:14:48 +0000 Subject: [PATCH 052/274] Initial cfg for ramfc (unused dma context storage), RAMHT --- src/86box.c | 78 ------------------------ src/include/86box/nv/vid_nv3.h | 25 ++++++-- src/video/nv/nv3/nv3_core_arbiter.c | 8 +-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 53 ++++++++++++++++ src/video/nv/nv3/subsystems/nv3_pramin.c | 13 ++++ 5 files changed, 90 insertions(+), 87 deletions(-) diff --git a/src/86box.c b/src/86box.c index fdfdcf1e8..2825535fd 100644 --- a/src/86box.c +++ b/src/86box.c @@ -408,84 +408,6 @@ pclog_ex_cyclic(const char* fmt, va_list ap) cyclic_last_line++; - /* - This version sucks - bool is_cycle = false; - - uint32_t repeat_order = 0; - - for (int32_t log_line = 0; log_line < (LOG_SIZE_BUFFER_CYCLIC); log_line++) - { - for (int32_t check_size = 1; check_size < (LOG_SIZE_BUFFER_CYCLIC / 2); check_size++) - { - uint32_t log_to_check = log_line + check_size; - - // Loop around - if (log_to_check >= LOG_SIZE_BUFFER_CYCLIC) - log_to_check %= LOG_SIZE_BUFFER_CYCLIC; - - // find an initial repeat - if (cyclic_buff[log_line][0] != '\0' - || cyclic_buff[log_to_check][0] != '\0') - { - if (!strncmp(cyclic_buff[log_line], cyclic_buff[log_to_check], LOG_SIZE_BUFFER)) - { - // now see if there are actually repeats (loop over to the start of the log...) - - int32_t highest_real_loop = 1; - - for (int32_t loop_chk = 1; loop_chk < check_size; loop_chk++) - { - uint32_t log_to_check_1 = log_line + loop_chk; - uint32_t log_to_check_2 = (log_line + loop_chk) + check_size; - - if (log_to_check_1 >= LOG_SIZE_BUFFER_CYCLIC) - log_to_check_1 %= LOG_SIZE_BUFFER_CYCLIC; - - if (log_to_check_2 >= LOG_SIZE_BUFFER_CYCLIC) - log_to_check_2 %= LOG_SIZE_BUFFER_CYCLIC; - - if (!strncmp(cyclic_buff[log_to_check_1], cyclic_buff[log_to_check_2], LOG_SIZE_BUFFER)) - { - is_cycle = true; - repeat_order = check_size; - break; - } - } - - - } - - } - - if (is_cycle) break; - } - - if (is_cycle) break; - } - - if (is_cycle - && cyclic_last_line % repeat_order == 0) - { - log_cycles++; - } - else if (!is_cycle) - log_cycles = 0; - - - if (log_cycles <= 1) - { - strcpy(buff, temp); - fprintf(stdlog, "%s", temp); - } - else - { - if (cyclic_last_line % repeat_order == 0) - fprintf(stdlog, "***** Cyclical Log Repeat %d *****\n", log_cycles); - } - - fflush(stdlog); -*/ #endif } diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 0e80eb23b..f2d28eaf9 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -199,9 +199,26 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CONFIG_0 0x2200 #define NV3_PFIFO_CONFIG_0_DMA_FETCH 8 + #define NV3_PFIFO_CONFIG_RAMHT 0x2210 // Hashtable for graphics objects config -#define NV3_PFIFO_CONFIG_RAMRO 0x2214 -#define NV3_PFIFO_CONFIG_RAMFC 0x2218 +#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 +#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS_DEFAULT 0x0 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 +#define NV3_PFIFO_CONFIG_RAMHT_4K 0x0 +#define NV3_PFIFO_CONFIG_RAMHT_8K 0x1 +#define NV3_PFIFO_CONFIG_RAMHT_16K 0x2 +#define NV3_PFIFO_CONFIG_RAMHT_32K 0x3 + +#define NV3_PFIFO_CONFIG_RAMFC 0x2214 +#define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS 9 +#define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS_DEFAULT 0x1C00 // Hardcoded in silicon? + +#define NV3_PFIFO_CONFIG_RAMRO 0x2218 +#define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS 9 +#define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS_DEFAULT 0x1E00 // Hardcoded in silicon? +#define NV3_PFIFO_CONFIG_RAMRO_SIZE 16 +#define NV3_PFIFO_CONFIG_RAMRO_SIZE_512B 0x0 +#define NV3_PFIFO_CONFIG_RAMRO_SIZE_8K 0x1 #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem @@ -1001,8 +1018,8 @@ uint32_t nv3_user_read(uint32_t address); void nv3_user_write(uint32_t address, uint32_t value); #define nv3_object_submit_start nv3_user_read #define nv3_object_submit_end nv3_user_write -uint32_t nv3_pramin_read(uint32_t address); -void nv3_pramin_write(uint32_t address, uint32_t value); +uint32_t nv3_pramin_arbitrate_read(uint32_t address); +void nv3_pramin_arbitrate_write(uint32_t address, uint32_t value); // TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* // GPU subsystems diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index ee8fe048d..22da49b20 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -104,7 +104,7 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - ret = nv3_pramin_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function + ret = nv3_pramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); @@ -167,7 +167,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) else if (address >= NV3_USER_START && address <= NV3_USER_END) nv3_user_write(address, value); else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - nv3_pramin_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions + nv3_pramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions else { nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); @@ -201,6 +201,4 @@ uint32_t nv3_vram_read(uint32_t address) { return 0; }; void nv3_vram_write(uint32_t address, uint32_t value) {}; uint32_t nv3_user_read(uint32_t address) { return 0; }; -void nv3_user_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_pramin_read(uint32_t address) { return 0; }; -void nv3_pramin_write(uint32_t address, uint32_t value) {}; \ No newline at end of file +void nv3_user_write(uint32_t address, uint32_t value) {}; \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 97d5e6f0e..931244b20 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -37,6 +37,9 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL}, { NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,}, + { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, + { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, + { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -90,6 +93,16 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_INTR_EN: ret = nv3->pfifo.interrupt_enable; break; + // These may need to become functions. + case NV3_PFIFO_CONFIG_RAMFC: + ret = nv3->pfifo.ramfc_config; + break; + case NV3_PFIFO_CONFIG_RAMHT: + ret = nv3->pfifo.ramht_config; + break; + case NV3_PFIFO_CONFIG_RAMRO: + ret = nv3->pfifo.ramro_config; + break; } } @@ -149,6 +162,46 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_INTR_EN: nv3->pbus.interrupt_enable = value & 0x00001111; break; + case NV3_PFIFO_CONFIG_RAMHT: + nv3->pfifo.ramht_config = value; +// This code sucks a bit fix it later +#ifdef ENABLE_NV_LOG + uint32_t new_size_ramht = ((value >> 16) & 0x03); + + if (new_size_ramht == 0) + new_size_ramht = 0x1000; + else if (new_size_ramht == 1) + new_size_ramht = 0x2000; + else if (new_size_ramht == 2) + new_size_ramht = 0x4000; + else if (new_size_ramht == 3) + new_size_ramht = 0x8000; + + nv_log("NV3: RAMHT Reconfiguration\n" + "Base Address in RAMIN: %d\n" + "Size: 0x%08x bytes\n", (value >> 12) & 0x1f, new_size_ramht); +#endif + break; + case NV3_PFIFO_CONFIG_RAMFC: + nv3->pfifo.ramfc_config = value; + + nv_log("NV3: RAMFC Reconfiguration\n" + "Base Address in RAMIN: %d\n", (value >> 12) & 0x1f); + break; + case NV3_PFIFO_CONFIG_RAMRO: + nv3->pfifo.ramro_config = value; + + uint32_t new_size_ramro = ((value >> 16) & 0x01); + + if (new_size_ramro == 0) + new_size_ramro = 0x200; + else if (new_size_ramro == 1) + new_size_ramro = 0x2000; + + nv_log("NV3: RAMRO Reconfiguration\n" + "Base Address in RAMIN: %d\n" + "Size: 0x%08x bytes\n", (value >> 12) & 0x1f, new_size_ramro); + break; } } } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index a6561be9d..c5093a175 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -147,3 +147,16 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) nv_log("NV3: Write dword to RAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } + +/* +Arbitrates reads and writes to RAMFC, RAMRO, RAMHT and generic RAMIN +*/ +uint32_t nv3_pramin_arbitrate_read(uint32_t address) +{ + return 0; +} + +void nv3_pramin_arbitrate_write(uint32_t address, uint32_t value) +{ + +} \ No newline at end of file From 4778e86273e29158a8b9ed3002f535b3cfec7fa6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 11 Jan 2025 02:24:12 +0000 Subject: [PATCH 053/274] Initial progress at RAMRO, RAMHT and RAMFC --- src/include/86box/nv/vid_nv3.h | 26 ++- src/video/nv/nv3/nv3_core_arbiter.c | 5 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 6 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 196 ++++++++++++++++-- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 9 + .../nv/nv3/subsystems/nv3_pramin_ramht.c | 15 +- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 9 + 7 files changed, 232 insertions(+), 34 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index f2d28eaf9..e831de61f 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -7,7 +7,7 @@ * This file is part of the 86Box distribution. * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated 2 January 2025 (STILL WORKING ON IT) + * Last updated 9 January 2025 (STILL WORKING ON IT) * * * @@ -204,10 +204,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 #define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS_DEFAULT 0x0 #define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 -#define NV3_PFIFO_CONFIG_RAMHT_4K 0x0 -#define NV3_PFIFO_CONFIG_RAMHT_8K 0x1 -#define NV3_PFIFO_CONFIG_RAMHT_16K 0x2 -#define NV3_PFIFO_CONFIG_RAMHT_32K 0x3 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE_4K 0x0 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE_8K 0x1 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE_16K 0x2 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE_32K 0x3 #define NV3_PFIFO_CONFIG_RAMFC 0x2214 #define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS 9 @@ -578,7 +578,7 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_STANDARDVGA_END 0x18 -// These are nvidia (25-63) +// These are nvidia, licensed from weitek (25-63) #define NV3_CRTC_REGISTER_RPC0 0x19 // What does this mean? #define NV3_CRTC_REGISTER_RPC1 0x1A // What does this mean? #define NV3_CRTC_REGISTER_READ_BANK 0x1D @@ -865,7 +865,7 @@ typedef struct nv3_pramin_ramht_s nv3_pramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; } nv3_pramin_ramht_t; -uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel); +uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel); // Anti-fuckup device typedef struct nv3_pramin_ramro_s @@ -963,6 +963,16 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN +bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin +bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin + +uint32_t nv3_ramfc_read(uint32_t address); +void nv3_ramfc_write(uint32_t address, uint32_t value); +uint32_t nv3_ramro_read(uint32_t address); +void nv3_ramro_write(uint32_t address, uint32_t value); +uint32_t nv3_ramht_read(uint32_t address); +void nv3_ramht_write(uint32_t address, uint32_t value); + // MMIO Arbitration // Determine where the hell in this mess our reads or writes are going uint32_t nv3_mmio_arbitrate_read(uint32_t address); @@ -1018,8 +1028,6 @@ uint32_t nv3_user_read(uint32_t address); void nv3_user_write(uint32_t address, uint32_t value); #define nv3_object_submit_start nv3_user_read #define nv3_object_submit_end nv3_user_write -uint32_t nv3_pramin_arbitrate_read(uint32_t address); -void nv3_pramin_arbitrate_write(uint32_t address, uint32_t value); // TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* // GPU subsystems diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 22da49b20..bab378b9f 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -103,8 +103,9 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) ret = nv3_vram_read(address); else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); - else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - ret = nv3_pramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function + // RAMIN is handled by a separate memory mapping in PCI BAR1 + //else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) + //ret = nv3_pramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 931244b20..1838faef5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -179,14 +179,14 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_log("NV3: RAMHT Reconfiguration\n" "Base Address in RAMIN: %d\n" - "Size: 0x%08x bytes\n", (value >> 12) & 0x1f, new_size_ramht); + "Size: 0x%08x bytes\n", ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12, new_size_ramht); #endif break; case NV3_PFIFO_CONFIG_RAMFC: nv3->pfifo.ramfc_config = value; nv_log("NV3: RAMFC Reconfiguration\n" - "Base Address in RAMIN: %d\n", (value >> 12) & 0x1f); + "Base Address in RAMIN: %d\n", ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9); break; case NV3_PFIFO_CONFIG_RAMRO: nv3->pfifo.ramro_config = value; @@ -200,7 +200,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_log("NV3: RAMRO Reconfiguration\n" "Base Address in RAMIN: %d\n" - "Size: 0x%08x bytes\n", (value >> 12) & 0x1f, new_size_ramro); + "Size: 0x%08x bytes\n", ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9, new_size_ramro); break; } } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index c5093a175..35fa80603 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -48,11 +48,15 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) addr ^= (nv3->nvbase.svga.vram_max- 0x10); - uint8_t val = nv3->nvbase.svga.vram[addr]; + uint32_t val = 0x00; - nv_log("NV3: Read byte from RAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + if (!nv3_pramin_arbitrate_read(addr, &val)) // Oh well + { + val = (uint8_t)nv3->nvbase.svga.vram[addr]; + nv_log("NV3: Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + } - return val; + return (uint8_t)val; } // Read 16-bit ramin @@ -68,9 +72,13 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 1; // what - uint16_t val = vram_16bit[addr]; // what + uint32_t val = 0x00; - nv_log("NV3: Read word from RAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + if (!nv3_pramin_arbitrate_read(addr, &val)) + { + val = (uint16_t)vram_16bit[addr]; + nv_log("NV3: Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + } return val; } @@ -88,9 +96,14 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 2; // what - uint32_t val = vram_32bit[addr]; + uint32_t val = 0x00; - nv_log("NV3: Read dword from RAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + if (!nv3_pramin_arbitrate_read(addr, &val)) + { + val = vram_32bit[addr]; + + nv_log("NV3: Read dword from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + } return val; } @@ -107,9 +120,15 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) addr ^= (nv3->nvbase.svga.vram_max - 0x10); - nv3->nvbase.svga.vram[addr] = val; + uint32_t val32 = 0x00; + + if (!nv3_pramin_arbitrate_write(addr, val32)) + { + nv3->nvbase.svga.vram[addr] = val; + nv_log("NV3: Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); + } + - nv_log("NV3: Write byte to RAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); } // Write 16-bit ramin @@ -125,9 +144,15 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 1; // what - vram_16bit[addr] = val; + uint32_t val32 = 0x00; + + if (!nv3_pramin_arbitrate_write(addr, val32)) + { + vram_16bit[addr] = val; + nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr); + } + - nv_log("NV3: Write word to RAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr); } // Write 32-bit ramin @@ -143,20 +168,155 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 2; // what - vram_32bit[addr] = val; + uint32_t val32 = 0x00; + + if (!nv3_pramin_arbitrate_write(addr, val32)) + { + vram_32bit[addr] = val; + nv_log("NV3: Write dnv3_pramin_arbitrate_readword to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr); + } - nv_log("NV3: Write dword to RAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } /* -Arbitrates reads and writes to RAMFC, RAMRO, RAMHT and generic RAMIN +RAMIN access arbitration functions +Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) (RAMAU?) +and generic RAMIN + +Takes a pointer to a result integer. This is because we need to check its result in our normal write function. +Returns true if a valid "non-generic" address was found (e.g. RAMFC/RAMRO/RAMHT). False if the specified address is a generic RAMIN address */ -uint32_t nv3_pramin_arbitrate_read(uint32_t address) +bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value) { - return 0; + if (!nv3) return 0x00; + + uint32_t ramht_size = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03); + uint32_t ramro_size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + + // Get the addresses of RAMHT, RAMFC, RAMRO + // They must be within first 64KB of PRAMIN! + uint32_t ramht_start = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12; // Must be 0x1000 aligned + uint32_t ramfc_start = ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned + uint32_t ramro_start = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned + + // Calculate the RAMHT and RAMRO end points. + // (RAMFC is always 0x1000 bytes on NV3.) + uint32_t ramht_end = ramht_start; + uint32_t ramfc_end = ramfc_start + 0x1000; + uint32_t ramro_end = ramro_start; + + switch (ramht_size) + { + case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_0; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_1; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_2; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_3; + break; + } + + switch (ramro_size) + { + case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B: + ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_0; + break; + case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K: + ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_1; + break; + } + + if (address >= ramht_start + && address <= ramht_end) + { + *value = nv3_ramht_read(address); + return true; + } + else if (address >= ramfc_start + && address <= ramfc_end) + { + *value = nv3_ramfc_read(address); + return true; + } + else if (address >= ramro_start + && address <= ramro_end) + { + *value = nv3_ramro_read(address); + return true; + } + + /* temp */ + return false; } -void nv3_pramin_arbitrate_write(uint32_t address, uint32_t value) +bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value) { - + if (!nv3) return 0x00; + + uint32_t ramht_size = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03); + uint32_t ramro_size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + + // Get the addresses of RAMHT, RAMFC, RAMRO + // They must be within first 64KB of PRAMIN! + uint32_t ramht_start = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12; // Must be 0x1000 aligned + uint32_t ramfc_start = ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned + uint32_t ramro_start = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned + + // Calculate the RAMHT and RAMRO end points. + // (RAMFC is always 0x1000 bytes on NV3.) + uint32_t ramht_end = ramht_start; + uint32_t ramfc_end = ramfc_start + 0x1000; + uint32_t ramro_end = ramro_start; + + switch (ramht_size) + { + case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_0; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_1; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_2; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: + ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_3; + break; + } + + switch (ramro_size) + { + case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B: + ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_0; + break; + case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K: + ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_1; + break; + } + + if (address >= ramht_start + && address <= ramht_end) + { + nv3_ramht_write(address, value); + return true; + } + else if (address >= ramfc_start + && address <= ramfc_end) + { + nv3_ramfc_write(address, value); + return true; + } + else if (address >= ramro_start + && address <= ramro_end) + { + nv3_ramro_write(address, value); + return true; + } + + return false; } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index 5c6d3a54c..e06445755 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -28,3 +28,12 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +uint32_t nv3_ramfc_read(uint32_t address) +{ + nv_log("NV3: RAMFC (Unused DMA channel context) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00", address); +} + +void nv3_ramfc_write(uint32_t address, uint32_t value) +{ + nv_log("NV3: RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x), UNIMPLEMENTED", value, address); +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index b77f18729..ff72e811c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -32,9 +32,20 @@ It is used to get the offset within RAMHT of a graphics object. */ -uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel) +uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel) { uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel); nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)", name, channel); return hash; -} \ No newline at end of file +} + + +uint32_t nv3_ramht_read(uint32_t address) +{ + nv_log("NV3: RAMHT (Graphics object storage hashtable) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00", address); +} + +void nv3_ramht_write(uint32_t address, uint32_t value) +{ + nv_log("NV3: RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), UNIMPLEMENTED", value, address); +} diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 865bc46ec..6176e191a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -28,3 +28,12 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +uint32_t nv3_ramro_read(uint32_t address) +{ + nv_log("NV3: RAM Runout (invalid dma object submission) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00", address); +} + +void nv3_ramro_write(uint32_t address, uint32_t value) +{ + nv_log("NV3: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)", value, address); +} \ No newline at end of file From 543487be43aa0af9ce5a0f0df5046922ecca59a0 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 12 Jan 2025 00:55:23 +0000 Subject: [PATCH 054/274] Ramout enum. More descriptive names for the crtc registers in mmio --- src/include/86box/nv/vid_nv3.h | 38 ++++++++++++++++++++++++++++------ src/video/nv/nv3/nv3_core.c | 15 +++++--------- 2 files changed, 37 insertions(+), 16 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index e831de61f..a7780b07e 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -451,10 +451,10 @@ extern const device_config_t nv3_config[]; #define NV3_PRMCIO_START 0x601000 // Following four are CRTC+I2C access registers // and get redirected to VGA -#define NV3_PRMCIO_CRX_MONO 0x6013B4 -#define NV3_PRMCIO_CR_MONO 0x6013B5 -#define NV3_PRMCIO_CRX_COLOR 0x6013D4 -#define NV3_PRMCIO_CR_COLOR 0x6013D5 +#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO 0x6013B4 // Current CRTC Register Index - Monochrome +#define NV3_PRMCIO_CRTC_REGISTER_CUR_MONO 0x6013B5 // Currently Selected CRTC Register - Monochrome +#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR 0x6013D4 // Current CRTC Register Index - Colour +#define NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR 0x6013D5 #define NV3_PRMCIO_END 0x601FFF #define NV3_PDAC_START 0x680000 // OPTIONAL external DAC @@ -825,7 +825,7 @@ typedef struct nv3_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; -typedef struct nv3_pramin_name_s +typedef struct nv3_pramin_name_sd { union { @@ -843,7 +843,7 @@ typedef struct nv3_pramin_context_s { uint32_t context; uint8_t dma_channel; - uint8_t render_object; //0=sw, 1=render + uint8_t render_object; //0=sw, 1=hw accelerated render uint8_t class_id; uint8_t ramin_offset; //find }; @@ -867,6 +867,32 @@ typedef struct nv3_pramin_ramht_s uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel); +typedef enum nv3_pramin_ramro_reason_e +{ + nv3_runout_reason_illegal_access = 0, + + // PFIFO CACHE0/CACHE1 were turned off, so the graphics object could not be processed. + nv3_runout_reason_no_cache_available = 1, + + // Ran out of CACHE0 & CACHE1 space. + nv3_runout_reason_cache_ran_out = 2, + + nv3_runout_reason_free_count_overrun = 3, + + nv3_runout_reason_caught_lying = 4, + + // Access reserved by pagetable + nv3_runout_reason_reserved_access = 5, + +} nv3_pramin_ramro_reason; + +/* This is a gigantic error handling system */ +typedef struct nv3_pramin_ramro_entry_s +{ + + //todo +} nv3_pramin_ramro_entry_t; + // Anti-fuckup device typedef struct nv3_pramin_ramro_s { diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 6114749a6..b7b3319aa 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -45,10 +45,10 @@ bool nv3_is_svga_redirect_address(uint32_t addr) { return (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO); + || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR + || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR + || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_MONO + || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO); } // All MMIO regs are 32-bit i believe internally @@ -164,12 +164,7 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) addr &= 0xFFFFFF; // This is weitek vga stuff - if (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CR_COLOR - || addr == NV3_PRMCIO_CRX_COLOR - || addr == NV3_PRMCIO_CR_MONO - || addr == NV3_PRMCIO_CRX_MONO) + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; From 2cd01db878dda5b95cc593cafcc32e9fd26d225b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 12 Jan 2025 00:58:43 +0000 Subject: [PATCH 055/274] initial attempt to "replay" log entries --- src/86box.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/src/86box.c b/src/86box.c index 2825535fd..f15ca4de3 100644 --- a/src/86box.c +++ b/src/86box.c @@ -254,12 +254,12 @@ static volatile atomic_int pause_ack = 0; #ifndef RELEASE_BUILD -#define LOG_SIZE_BUFFER 1024 /* Log size buffer */ -#define LOG_SIZE_BUFFER_CYCLIC 32 /* Cyclic log size buffer (number of lines that should be cehcked) */ -#define LOG_MINIMUM_REPEAT_ORDER 4 /* Minimum repeat size */ +#define LOG_SIZE_BUFFER 1024 /* Log size buffer */ +#define LOG_SIZE_BUFFER_CYCLIC_LINES 32 /* Cyclic log size buffer (number of lines that should be cehcked) */ +#define LOG_MINIMUM_REPEAT_ORDER 4 /* Minimum repeat size */ static char buff[LOG_SIZE_BUFFER]; -static char cyclic_buff[LOG_SIZE_BUFFER_CYCLIC][LOG_SIZE_BUFFER]; +static char cyclic_buff[LOG_SIZE_BUFFER_CYCLIC_LINES][LOG_SIZE_BUFFER]; static int32_t cyclic_last_line = 0; static int32_t log_cycles = 0; @@ -333,7 +333,7 @@ pclog_ex_cyclic(const char* fmt, va_list ap) #ifndef RELEASE_BUILD char temp[LOG_SIZE_BUFFER]; - cyclic_last_line %= LOG_SIZE_BUFFER_CYCLIC; + cyclic_last_line %= LOG_SIZE_BUFFER_CYCLIC_LINES; vsprintf(temp, fmt, ap); @@ -341,7 +341,7 @@ pclog_ex_cyclic(const char* fmt, va_list ap) strncpy(cyclic_buff[cyclic_last_line], temp, LOG_SIZE_BUFFER); - uint32_t hashes[LOG_SIZE_BUFFER_CYCLIC] = {0}; + uint32_t hashes[LOG_SIZE_BUFFER_CYCLIC_LINES] = {0}; // Random numbers uint32_t base = 257; @@ -351,7 +351,7 @@ pclog_ex_cyclic(const char* fmt, va_list ap) bool is_cycle = false; // compute the set of hashes for the current log buffer - for (int32_t log_line = 0; log_line < LOG_SIZE_BUFFER_CYCLIC; log_line++) + for (int32_t log_line = 0; log_line < LOG_SIZE_BUFFER_CYCLIC_LINES; log_line++) { if (cyclic_buff[log_line][0] == '\0') continue; // skip @@ -365,13 +365,13 @@ pclog_ex_cyclic(const char* fmt, va_list ap) // Now see if there are real cycles... // We implement a minimum repeat size. - for (int32_t check_size = LOG_MINIMUM_REPEAT_ORDER; check_size < LOG_SIZE_BUFFER_CYCLIC / 2; check_size++) + for (int32_t check_size = LOG_MINIMUM_REPEAT_ORDER; check_size < LOG_SIZE_BUFFER_CYCLIC_LINES / 2; check_size++) { //TODO: Log what we need for cycle 1. //TODO: Command line option that lets us turn off this behaviour. for (int32_t log_line_to_check = 0; log_line_to_check < check_size; log_line_to_check++) { - if (hashes[log_line_to_check] == hashes[(log_line_to_check + check_size) % LOG_SIZE_BUFFER_CYCLIC]) + if (hashes[log_line_to_check] == hashes[(log_line_to_check + check_size) % LOG_SIZE_BUFFER_CYCLIC_LINES]) { repeat_order = check_size; break; @@ -393,7 +393,22 @@ pclog_ex_cyclic(const char* fmt, va_list ap) log_cycles++; if (log_cycles == 1) + { + // 'Replay' the last few log entries so they actually show up + // Todo: is this right? + + for (uint32_t index = cyclic_last_line - 1; index > (cyclic_last_line - repeat_order); cyclic_last_line--) + { + // *very important* to prevent out of bounds index + uint32_t real_index = index % LOG_SIZE_BUFFER_CYCLIC_LINES; + fprintf(stdlog, "%s", temp); + + } + fprintf(stdlog, "%s", temp); // allow normal logging + } + + if (log_cycles > 1 && log_cycles < 100) fprintf(stdlog, "***** Cyclical Log Repeat of Order %d #%d *****\n", repeat_order, log_cycles); else if (log_cycles == 100) From 1127400b1a97eaf61dfa2375c49c28430395e903 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 12 Jan 2025 02:11:30 +0000 Subject: [PATCH 056/274] many many more pgraph structs --- src/86box.c | 2 - .../86box/nv/classes/vid_nv3_classes.h | 26 +++++-- src/include/86box/nv/vid_nv3.h | 69 ++++++++++++++++--- src/video/nv/nv3/classes/nv3_class_names.c | 5 +- 4 files changed, 83 insertions(+), 19 deletions(-) diff --git a/src/86box.c b/src/86box.c index f15ca4de3..560bd0a3d 100644 --- a/src/86box.c +++ b/src/86box.c @@ -323,8 +323,6 @@ Starfrost, 7-8 January 2025: For RIVA 128 emulation I needed a way to suppress logging if a repeated pattern of the same set of lines were found. -It doesn't need to be super fast so I don't bother to use an optimised approach. I use iterate from 1 to n/2 and see if a pattern repeats or not. - Implements a version of the Rabin-Karp algorithm https://en.wikipedia.org/wiki/Rabin%E2%80%93Karp_algorithm */ void diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index a22871beb..d63394da8 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -75,7 +75,17 @@ typedef struct nv3_color_argb_32_s uint8_t a; } nv3_color_argb_32_t; -/* A4R4G4B4 */ +/* 30-bit colour format for internal PGRAPH use */ +typedef struct nv3_color_x3a10g10b10_s +{ + uint8_t reserved : 2; + bool alpha_if_chroma_key_otherwise_reserved2 : 1; // 1-bit ALPHA if chroma key, OTHERWISE USELESS and IGNORE + uint16_t r : 10; + uint16_t g : 10; + uint16_t b : 10; +} nv3_color_x3a10g10b10_t; + +/* 16-bit A4R4G4B4 colour format */ typedef struct nv3_color_16_a4r4g4b4_s { uint8_t a : 4; @@ -108,16 +118,25 @@ typedef struct nv3_position_16_s { uint32_t pos; - struct vid_nv3_classes + struct { uint16_t y; uint16_t x; }; - } position; } nv3_position_16_t; +/* A big position format with 30:16 = y, 15:11 = nothing, 10:0 = x */ +typedef struct nv3_position_16_bigy_s +{ + // WHOSE IDEA WAS THIS? + uint16_t x : 11; + uint8_t reserved : 5; + uint16_t y : 15; + bool reserved2 : 1; +} nv3_position_16_bigy_t; + /* Generic 16-bit size */ typedef struct nv3_size_16_s { @@ -130,7 +149,6 @@ typedef struct nv3_size_16_s uint16_t h; uint16_t w; }; - } size; } nv3_size_16_t; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index a7780b07e..b1d7556f6 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -5,18 +5,24 @@ * system designs based on the PCI bus. * * This file is part of the 86Box distribution. - * - * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated 9 January 2025 (STILL WORKING ON IT) - * - * + * + * Welcome to what happens when a single person demands that their overly complicated "vision" of a design be implemented + * with absolutely no compromise. This is true lunacy. + * + * Explanation of what is being done here, and how this all works, hopefully posted on the 86Box blog. + * Notes specific to a subsystem in the header or c file for that subsystem + * Also check the doc folder for some more notres + * + * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) + * Last updated: 12 January 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * * Copyright 2024-2025 Connor Hyde */ - +#pragma once +#include <86Box/nv/classes/vid_nv3_classes.h> // The GPU base structure extern const device_config_t nv3_config[]; @@ -738,19 +744,42 @@ typedef struct nv3_pramdac_s uint32_t hserr_width; // horizontal sync error width } nv3_pramdac_t; +/* Holds DMA context channel information */ typedef struct nv3_pgraph_context_switch_s { - + /* TODO */ } nv3_pgraph_context_switch_t; typedef struct nv3_pgraph_context_control_s { - + /* TODO */ } nv3_pgraph_context_control_t; +/* DMA object context info + Context uploaded from CACHE0/CACH1 by DMA Puller +*/ +typedef struct nv3_pgraph_context_user_s +{ + bool reserved3 : 1; + uint8_t channel : 7; + uint8_t reserved2 : 4; + uint8_t class : 5; + uint8_t subchannel : 3; + uint16_t reserved : 12; +} nv3_pgraph_context_user_t; + +typedef struct nv3_pgraph_dma_settings_s +{ + /* TODO */ +} nv3_pgraph_dma_settings_t; + // Graphics Subsystem typedef struct nv3_pgraph_s { + uint32_t debug_0; + uint32_t debug_1; + uint32_t debug_2; + uint32_t debug_3; uint32_t interrupt_status_0; // Interrupt status 0 uint32_t interrupt_enable_0; // Interrupt enable 0 uint32_t interrupt_status_1; // Interrupt status 1 @@ -758,7 +787,29 @@ typedef struct nv3_pgraph_s nv3_pgraph_context_control_t context_control; nv3_pgraph_context_switch_t context_user_submit; - uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE]; // DMA context cache + nv3_pgraph_context_user_t context_user; + uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE]; // DMA context cache (nv3_pgraph_context_user_t array?) + + // UCLIP stuff + uint32_t abs_uclip_xmin; + uint32_t abs_uclip_xmax; + uint32_t abs_uclip_ymin; + uint32_t abs_uclip_ymax; + nv3_position_16_bigy_t src_canvas_min; + nv3_position_16_bigy_t src_canvas_max; + nv3_position_16_bigy_t dst_canvas_min; + nv3_position_16_bigy_t dst_canvas_max; + nv3_color_x3a10g10b10_t pattern_color_0_0; + uint32_t pattern_color_0_1; // only 7:0 relevant + nv3_color_x3a10g10b10_t pattern_color_1_0; + uint32_t pattern_color_1_1; // only 7:0 relevant + uint32_t pattern_bitmap_high; // high part of pattern bitmap for blit + uint32_t pattern_bitmap_low; + uint32_t pattern_shape; // may need to be an enum - 0=8x8, 1=64x1, 2=1x64 + uint32_t plane_mask; // only 7:0 relevant + nv3_color_x3a10g10b10_t chroma_key; // color key + nv3_pgraph_dma_settings_t dma_settings; + } nv3_pgraph_t; // GPU Manufacturing Configuration (again) diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index 48b85cab4..3124f727c 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -15,10 +15,7 @@ * Copyright 2024-2025 starfrost */ -/* Taken from Win9x drivers 0.77, these had the best reversing potential */ - -#include <86Box/nv/classes/vid_nv3_classes.h> - +#include <86Box/nv/vid_nv3.h> /* These are the object classes AS RECOGNISED BY THE GRAPHICS HARDWARE. */ /* The drivers implement a COMPLETELY DIFFERENT SET OF CLASSES. */ From ced6c58616bbb189469d4e8b8b7edce9158c98b7 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 12 Jan 2025 02:15:22 +0000 Subject: [PATCH 057/274] whoops... --- src/86box.c | 2 +- src/include/86box/nv/vid_nv3.h | 2 +- src/video/nv/nv3/classes/nv3_class_names.c | 10 +++++++++- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/86box.c b/src/86box.c index 560bd0a3d..8450c8b6b 100644 --- a/src/86box.c +++ b/src/86box.c @@ -395,7 +395,7 @@ pclog_ex_cyclic(const char* fmt, va_list ap) // 'Replay' the last few log entries so they actually show up // Todo: is this right? - for (uint32_t index = cyclic_last_line - 1; index > (cyclic_last_line - repeat_order); cyclic_last_line--) + for (uint32_t index = cyclic_last_line - 1; index > (cyclic_last_line - repeat_order); index--) { // *very important* to prevent out of bounds index uint32_t real_index = index % LOG_SIZE_BUFFER_CYCLIC_LINES; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index b1d7556f6..15efb9562 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -809,7 +809,7 @@ typedef struct nv3_pgraph_s uint32_t plane_mask; // only 7:0 relevant nv3_color_x3a10g10b10_t chroma_key; // color key nv3_pgraph_dma_settings_t dma_settings; - + uint32_t beta_factor; } nv3_pgraph_t; // GPU Manufacturing Configuration (again) diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index 3124f727c..2b38afbb4 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -14,7 +14,15 @@ * * Copyright 2024-2025 starfrost */ - +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> /* These are the object classes AS RECOGNISED BY THE GRAPHICS HARDWARE. */ From e2d875b75fb926ff35924dc3e25f81bc6b8bf2d4 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 12 Jan 2025 15:01:27 +0000 Subject: [PATCH 058/274] notifier shit --- src/include/86box/nv/vid_nv3.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 15efb9562..8c4daf0e1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -664,6 +664,12 @@ typedef struct nv3_pci_config_s uint8_t int_line; } nv3_pci_config_t; +/* Notifier Engine */ +typedef struct nv3_notifier_s +{ + /* TODO */ +} nv3_notifier_t; + // add enums for eac // Chip configuration typedef struct nv3_straps_s @@ -773,6 +779,11 @@ typedef struct nv3_pgraph_dma_settings_s /* TODO */ } nv3_pgraph_dma_settings_t; +typedef struct nv3_pgraph_clip_misc_settings_s +{ + /* TODO */ +} nv3_pgraph_clip_misc_settings_t; + // Graphics Subsystem typedef struct nv3_pgraph_s { @@ -808,8 +819,10 @@ typedef struct nv3_pgraph_s uint32_t pattern_shape; // may need to be an enum - 0=8x8, 1=64x1, 2=1x64 uint32_t plane_mask; // only 7:0 relevant nv3_color_x3a10g10b10_t chroma_key; // color key - nv3_pgraph_dma_settings_t dma_settings; uint32_t beta_factor; + nv3_pgraph_dma_settings_t dma_settings; + nv3_pgraph_clip_misc_settings_t clip_misc_settings; + nv3_notifier_t notifier; } nv3_pgraph_t; // GPU Manufacturing Configuration (again) From cefc313a3983311647f46a7a8a6062cff324d2dd Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 14 Jan 2025 00:01:04 +0000 Subject: [PATCH 059/274] patches from p0 --- src/86box.c | 10 +++++++--- src/include/86box/nv/vid_nv_rivatimer.h | 8 ++++---- src/timer.c | 2 +- src/video/nv/nv_rivatimer.c | 18 +++++++++--------- 4 files changed, 21 insertions(+), 17 deletions(-) diff --git a/src/86box.c b/src/86box.c index 8450c8b6b..85cbb9957 100644 --- a/src/86box.c +++ b/src/86box.c @@ -266,14 +266,17 @@ static int32_t log_cycles = 0; static int seen = 0; static int suppr_seen = 1; + +// Functions only used in this translation unit +void pclog_ensure_stdlog_open(void); #endif /* Ensures STDLOG is open for pclog_ex and pclog_ex_cyclic */ -void -pclog_ensure_stdlog_open() +void pclog_ensure_stdlog_open(void) { +#ifndef RELEASE_BUILD if (stdlog == NULL) { if (log_path[0] != '\0') { stdlog = plat_fopen(log_path, "w"); @@ -282,6 +285,7 @@ pclog_ensure_stdlog_open() } else stdlog = stdout; } +#endif } /* @@ -399,7 +403,7 @@ pclog_ex_cyclic(const char* fmt, va_list ap) { // *very important* to prevent out of bounds index uint32_t real_index = index % LOG_SIZE_BUFFER_CYCLIC_LINES; - fprintf(stdlog, "%s", temp); + fprintf(stdlog, "%s", cyclic_buff[real_index]); } diff --git a/src/include/86box/nv/vid_nv_rivatimer.h b/src/include/86box/nv/vid_nv_rivatimer.h index d5bb86b90..59f6cfebf 100644 --- a/src/include/86box/nv/vid_nv_rivatimer.h +++ b/src/include/86box/nv/vid_nv_rivatimer.h @@ -47,7 +47,7 @@ So I decided to create this timer that is completely separate from the CPU Core. #include #include #include -#include <86Box\86box.h> +#include <86box/86box.h> #ifdef _WIN32 #include @@ -63,7 +63,7 @@ typedef struct rivatimer_s double value; // The current value of the rivatimer bool running; // Is this RivaTimer running? struct rivatimer_s* next; // Next RivaTimer - void (*callback)(); // Callback to call on fire + void (*callback)(double real_time); // Callback to call on fire #ifdef _WIN32 LARGE_INTEGER starting_time; // Starting time. #else @@ -72,11 +72,11 @@ typedef struct rivatimer_s double time; // Accumulated time in uS. } rivatimer_t; -void rivatimer_init(); // Initialise the Rivatimer. +void rivatimer_init(void); // Initialise the Rivatimer. rivatimer_t* rivatimer_create(double period, void (*callback)(double real_time)); void rivatimer_destroy(rivatimer_t* rivatimer_ptr); -void rivatimer_update_all(); +void rivatimer_update_all(void); void rivatimer_start(rivatimer_t* rivatimer_ptr); void rivatimer_stop(rivatimer_t* rivatimer_ptr); double rivatimer_get_time(rivatimer_t* rivatimer_ptr); diff --git a/src/timer.c b/src/timer.c index 2b92a1958..a3a7c9efb 100644 --- a/src/timer.c +++ b/src/timer.c @@ -4,7 +4,7 @@ #include #include <86box/86box.h> #include <86box/timer.h> -#include <86Box/nv/vid_nv_rivatimer.h> +#include <86box/nv/vid_nv_rivatimer.h> uint64_t TIMER_USEC; uint32_t timer_target; diff --git a/src/video/nv/nv_rivatimer.c b/src/video/nv/nv_rivatimer.c index 343ec02ff..12d40c026 100644 --- a/src/video/nv/nv_rivatimer.c +++ b/src/video/nv/nv_rivatimer.c @@ -22,7 +22,7 @@ Since Windows XP, QueryPerformanceCounter and QueryPerformanceFrequency cannot f */ -#include <86Box/nv/vid_nv_rivatimer.h> +#include <86box/nv/vid_nv_rivatimer.h> #ifdef _WIN32 LARGE_INTEGER performance_frequency; @@ -34,7 +34,7 @@ rivatimer_t* rivatimer_tail; // The tail of the rivatimer list. /* Functions only used in this translation unit */ bool rivatimer_really_exists(rivatimer_t* rivatimer); // Determine if a rivatimer really exists in the linked list. -void rivatimer_init() +void rivatimer_init(void) { // Destroy all the rivatimers. rivatimer_t* rivatimer_ptr = rivatimer_head; @@ -120,7 +120,7 @@ bool rivatimer_really_exists(rivatimer_t* rivatimer) void rivatimer_destroy(rivatimer_t* rivatimer_ptr) { if (!rivatimer_really_exists(rivatimer_ptr)) - fatal("rivatimer_destroy: The timer was already destroyed, or never existed in the first place. Punch starfrost in the face"); + fatal("rivatimer_destroy: The timer was already destroyed, or never existed in the first place."); // Case: We are destroying the head if (rivatimer_ptr == rivatimer_head) @@ -162,7 +162,7 @@ void rivatimer_destroy(rivatimer_t* rivatimer_ptr) rivatimer_ptr = NULL; //explicitly set to null } -void rivatimer_update_all() +void rivatimer_update_all(void) { rivatimer_t* rivatimer_ptr = rivatimer_head; @@ -221,7 +221,7 @@ void rivatimer_update_all() void rivatimer_start(rivatimer_t* rivatimer_ptr) { if (!rivatimer_really_exists(rivatimer_ptr)) - fatal("rivatimer_start: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + fatal("rivatimer_start: The timer has been destroyed, or never existed in the first place."); if (rivatimer_ptr->period <= 0) fatal("rivatimer_start: Zero period!"); @@ -239,7 +239,7 @@ void rivatimer_start(rivatimer_t* rivatimer_ptr) void rivatimer_stop(rivatimer_t* rivatimer_ptr) { if (!rivatimer_really_exists(rivatimer_ptr)) - fatal("rivatimer_stop: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + fatal("rivatimer_stop: The timer has been destroyed, or never existed in the first place."); rivatimer_ptr->running = false; rivatimer_ptr->time = 0; @@ -249,7 +249,7 @@ void rivatimer_stop(rivatimer_t* rivatimer_ptr) double rivatimer_get_time(rivatimer_t* rivatimer_ptr) { if (!rivatimer_really_exists(rivatimer_ptr)) - fatal("rivatimer_get_time: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + fatal("rivatimer_get_time: The timer has been destroyed, or never existed in the first place."); return rivatimer_ptr->time; } @@ -257,7 +257,7 @@ double rivatimer_get_time(rivatimer_t* rivatimer_ptr) void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)(double real_time)) { if (!rivatimer_really_exists(rivatimer_ptr)) - fatal("rivatimer_set_callback: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + fatal("rivatimer_set_callback: The timer has been destroyed, or never existed in the first place."); if (!callback) fatal("rivatimer_set_callback: No callback!"); @@ -268,7 +268,7 @@ void rivatimer_set_callback(rivatimer_t* rivatimer_ptr, void (*callback)(double void rivatimer_set_period(rivatimer_t* rivatimer_ptr, double period) { if (!rivatimer_really_exists(rivatimer_ptr)) - fatal("rivatimer_set_period: The timer has been destroyed, or never existed in the first place. Punch starfrost in the face"); + fatal("rivatimer_set_period: The timer has been destroyed, or never existed in the first place."); rivatimer_ptr->period = period; } \ No newline at end of file From 1c25e61896472e96683b6b8de4dcfa23dfe07467 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 15 Jan 2025 01:52:33 +0000 Subject: [PATCH 060/274] Move to new logging system. --- src/include/86box/nv/vid_nv.h | 6 ++++-- src/video/nv/nv3/nv3_core.c | 16 ++++++++++++++-- src/video/nv/nv_base.c | 18 ++++++++++++++++-- 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index d067c0148..2927b91c6 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -27,7 +27,7 @@ #ifdef EMU_DEVICE_H // what //TODO: split this all into nv1, nv3, nv4... - +#include <86box/log.h> #include <86box/i2c.h> #include <86box/vid_ddc.h> #include <86box/timer.h> @@ -35,6 +35,7 @@ #include <86box/vid_svga_render.h> #include <86box/nv/vid_nv_rivatimer.h> +void nv_log_set_device(void* device); void nv_log(const char *fmt, ...); // Defines common to all NV chip architectural generations @@ -92,6 +93,7 @@ typedef struct nv_base_s rom_t vbios; // NVIDIA/OEm VBIOS // move to nv3_cio_t? svga_t svga; // SVGA core (separate to nv3) - Weitek licensed + void* log; // new logging engine // stuff that doesn't fit in the svga structure uint32_t cio_read_bank; // SVGA read bank uint32_t cio_write_bank; // SVGA write bank @@ -114,7 +116,7 @@ typedef struct nv_base_s rivatimer_t* memory_clock_timer; // Timer for measuring memory/gpu clock bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times void* i2c; // I2C for monitor EDID - void* ddc; + void* ddc; // Display Data Channel for EDID } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index b7b3319aa..9cf8a602a 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -913,6 +913,10 @@ void nv3_update_mappings() // void* nv3_init(const device_t *info) { + nv3->nvbase.log = log_open("NV3"); + + // Allows nv_log to be used for multiple nvidia devices + nv_log_set_device(nv3->nvbase.log); nv_log("NV3: initialising core\n"); // Figure out which vbios the user selected @@ -928,9 +932,13 @@ void* nv3_init(const device_t *info) int32_t err = rom_init(&nv3->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); if (err) - nv_log("NV3: failed to load VBIOS err=%d\n", err); + { + nv_log("NV3 FATAL: failed to load VBIOS err=%d\n", err); + fatal("Nvidia NV3 init failed: Somehow selected a nonexistent VBIOS? err=%d\n", err); + return NULL; + } else - nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); + nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); // set the vram amount and gpu revision uint32_t vram_amount = device_get_config_int("VRAM"); @@ -1004,6 +1012,10 @@ void* nv3_init_agp(const device_t* info) void nv3_close(void* priv) { + // Shut down logging + log_close(nv3->nvbase.log); + nv_log_set_device(NULL); + // Shut down I2C and the DDC ddc_close(nv3->nvbase.ddc); i2c_gpio_close(nv3->nvbase.i2c); diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index 88cb5208b..96e011430 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -17,9 +17,11 @@ // Common NV1/3/4... init #define HAVE_STDARG_H // wtf is this crap +#include #include #include -#include + +#include <86box/log.h> #include <86box/86box.h> #include <86box/nv/vid_nv.h> @@ -28,13 +30,25 @@ #ifdef ENABLE_NV_LOG int nv_do_log = ENABLE_NV_LOG; +// A bit of kludge so that in the future we can abstract this function acorss multiple generations of Nvidia GPUs +void* nv_log_device; + +void nv_log_set_device(void* device) +{ + nv_log_device = device; +} + void nv_log(const char *fmt, ...) { + if (!nv_log_device) + return; + va_list ap; if (nv_do_log) { va_start(ap, fmt); - pclog_ex_cyclic(fmt, ap); + + log_out_cyclic(nv_log_device, fmt, ap); va_end(ap); } } From f20fd42e79ba59b06060b1675d7d6d81fc5cef1a Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 17 Jan 2025 15:30:51 +0000 Subject: [PATCH 061/274] Add pgraph status and even more registers, man that was boring... --- .../86box/nv/classes/vid_nv3_classes.h | 2 +- src/include/86box/nv/vid_nv3.h | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index d63394da8..5ccd067a9 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -78,7 +78,7 @@ typedef struct nv3_color_argb_32_s /* 30-bit colour format for internal PGRAPH use */ typedef struct nv3_color_x3a10g10b10_s { - uint8_t reserved : 2; + uint8_t reserved : 1; bool alpha_if_chroma_key_otherwise_reserved2 : 1; // 1-bit ALPHA if chroma key, OTHERWISE USELESS and IGNORE uint16_t r : 10; uint16_t g : 10; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 8c4daf0e1..7845f132b 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -784,6 +784,29 @@ typedef struct nv3_pgraph_clip_misc_settings_s /* TODO */ } nv3_pgraph_clip_misc_settings_t; +typedef struct nv3_pgraph_status_s +{ + bool overall_busy : 1; // Is anything busy? + uint8_t reserved : 3; + bool xy_logic_busy : 1; // Determines if the line drawing/xy/vector stuff is busy. + uint8_t reserved2 : 3; + bool port_notify_busy : 1; // Mediaport?/PIO? notifier engine busy + uint8_t reserved3 : 3; + bool port_register_busy : 1; + uint8_t reserved4 : 3; + bool port_dma_busy : 1; // Mediaport?/PIO? DMA engine busy + bool dma_engine_busy : 1; // DMA engine busy + uint8_t reserved5 : 2; + bool dma_notify_busy : 1; // Are the notifiers busy? + uint8_t reserved6 : 3; + bool engine_3d_busy : 1; // 3d engine busy? + bool engine_cache_busy : 1; // PFIFO CACHE0/CACHE1 busy? + bool engine_zfifo_busy : 1; // ZFIFO (zeta buffer? z buffer?) busy? + bool port_user_busy : 1; // User context switch? + uint8_t reserved7 : 3; + +} nv3_pgraph_status_t; + // Graphics Subsystem typedef struct nv3_pgraph_s { @@ -823,6 +846,17 @@ typedef struct nv3_pgraph_s nv3_pgraph_dma_settings_t dma_settings; nv3_pgraph_clip_misc_settings_t clip_misc_settings; nv3_notifier_t notifier; + nv3_position_16_bigy_t clip0_min; + nv3_position_16_bigy_t clip0_max; + nv3_position_16_bigy_t clip1_min; + nv3_position_16_bigy_t clip1_max; + uint32_t fifo_access; + nv3_pgraph_status_t status; + uint32_t trapped_address; + uint32_t trapped_data; + uint32_t trapped_instance; + uint32_t interrupt_status_dma; + uint32_t interrupt_enable_dma; } nv3_pgraph_t; // GPU Manufacturing Configuration (again) From 7ba088a5eb0643b5e358997109a96b6cb9b9ecb5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 20 Jan 2025 01:09:32 +0000 Subject: [PATCH 062/274] Actually add basic read and write to those pgraph registers so we can debug them, add PFIFO definitions and add the PFIFO CACHE1 gray code conversion functions as preparation for future work --- .../86box/nv/classes/vid_nv3_classes.h | 5 +- src/include/86box/nv/vid_nv3.h | 104 +++++++-- src/video/nv/nv3/classes/nv3_class_names.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 30 ++- src/video/nv/nv3/subsystems/nv3_pgraph.c | 213 ++++++++++++++++++ .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 6 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 6 +- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 4 +- 8 files changed, 336 insertions(+), 34 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 5ccd067a9..099c0bdc6 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1043,9 +1043,12 @@ typedef struct nv3_object_class_017 /* No placeholder needed, it really is that long. */ } nv3_d3d5_accelerated_triangle_with_zeta_buffer_t; -/* 0x18, 0x19, 0x1A, 0x1B don't exist */ +/* 0x19, 0x1A, 0x1B don't exist */ +typedef struct nv3_object_class_018 +{ +} nv3_point_with_zeta_buffer_t; /* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? They are making it look like a bitfield but it's hex? diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 7845f132b..a2c54748e 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 12 January 2025 (STILL WORKING ON IT!!!) + * Last updated: 20 January 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -218,7 +218,6 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CONFIG_RAMFC 0x2214 #define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS 9 #define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS_DEFAULT 0x1C00 // Hardcoded in silicon? - #define NV3_PFIFO_CONFIG_RAMRO 0x2218 #define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS 9 #define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS_DEFAULT 0x1E00 // Hardcoded in silicon? @@ -226,6 +225,44 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CONFIG_RAMRO_SIZE_512B 0x0 #define NV3_PFIFO_CONFIG_RAMRO_SIZE_8K 0x1 +#define NV3_PFIFO_RUNOUT_STATUS 0x2400 +#define NV3_PFIFO_RUNOUT_STATUS_RANOUT 0 // 1 if we fucked up +#define NV3_PFIFO_RUNOUT_STATUS_LOW_MARK 4 // 1 if ramro is empty +#define NV3_PFIFO_RUNOUT_STATUS_HIGH_MARK 8 +#define NV3_PFIFO_RUNOUT_PUT 0x2410 +#define NV3_PFIFO_RUNOUT_PUT_ADDRESS 3 // 9:3 if small ramfc(?) otherwise 12:3 +#define NV3_PFIFO_RUNOUT_GET 0x2420 +#define NV3_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 + +#define NV3_PFIFO_CACHE0_SIZE 1 // This is for software-injected notified only! +#define NV3_PFIFO_CACHE1_SIZE_REV_AB 32 +#define NV3_PFIFO_CACHE1_SIZE_REV_C 64 +#define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C +#define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 +#define NV3_PFIFO_CACHE0_ACCESS 0x3000 +#define NV3_PFIFO_CACHE0_DMA_CHANNEL_ID 0x3004 +#define NV3_PFIFO_CACHE0_PUT 0x3010 +#define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit +#define NV3_PFIFO_CACHE0_PULLER 0x3040 +#define NV3_PFIFO_CACHE0_GET 0x3070 +#define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit +#define NV3_PFIFO_CACHE1_ACCESS 0x3200 +#define NV3_PFIFO_CACHE1_DMA_CHANNEL_ID 0x3204 +#define NV3_PFIFO_CACHE1_PUT 0x3210 +#define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 +#define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218 +#define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220 +#define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 +#define NV3_PFIFO_CACHE1_DMA_CONFIG_2 0x3228 +#define NV3_PFIFO_CACHE1_DMA_CONFIG_3 0x322C +// Why does a gpu need its own translation lookaside buffer and pagetable format. Are they crazy +#define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 +#define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA +#define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA +#define NV3_PFIFO_CACHE1_PULLER 0x3240 +#define NV3_PFIFO_CACHE1_PULLER_CONTEXT_IS_CLEAN 0x3250 +#define NV3_PFIFO_CACHE1_GET 0x3270 +#define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 @@ -750,7 +787,7 @@ typedef struct nv3_pramdac_s uint32_t hserr_width; // horizontal sync error width } nv3_pramdac_t; -/* Holds DMA context channel information */ +/* Holds DMA channel context information */ typedef struct nv3_pgraph_context_switch_s { /* TODO */ @@ -766,12 +803,20 @@ typedef struct nv3_pgraph_context_control_s */ typedef struct nv3_pgraph_context_user_s { - bool reserved3 : 1; - uint8_t channel : 7; - uint8_t reserved2 : 4; - uint8_t class : 5; - uint8_t subchannel : 3; - uint16_t reserved : 12; + union + { + uint32_t value; + + struct + { + bool reserved3 : 1; + uint8_t channel : 7; + uint8_t reserved2 : 3; + uint8_t class : 5; + uint8_t subchannel : 3; + uint16_t reserved : 13; + }; + }; } nv3_pgraph_context_user_t; typedef struct nv3_pgraph_dma_settings_s @@ -819,6 +864,7 @@ typedef struct nv3_pgraph_s uint32_t interrupt_status_1; // Interrupt status 1 uint32_t interrupt_enable_1; // Interrupt enable 1 + uint32_t context_switch; // TODO: Make this a struct, it's just going to be enormous lol. nv3_pgraph_context_control_t context_control; nv3_pgraph_context_switch_t context_user_submit; nv3_pgraph_context_user_t context_user; @@ -923,16 +969,21 @@ typedef struct nv3_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; -typedef struct nv3_pramin_name_sd +typedef struct nv3_pramin_name_s { union { uint32_t name; - uint8_t byte_high; - uint8_t byte_mid2; - uint8_t byte_mid1; - uint8_t byte_low; + + struct + { + uint8_t byte_high; + uint8_t byte_mid2; + uint8_t byte_mid1; + uint8_t byte_low; + }; }; + } nv3_pramin_name_t; typedef struct nv3_pramin_context_s @@ -940,10 +991,16 @@ typedef struct nv3_pramin_context_s union { uint32_t context; - uint8_t dma_channel; - uint8_t render_object; //0=sw, 1=hw accelerated render - uint8_t class_id; - uint8_t ramin_offset; //find + + struct + { + + uint8_t dma_channel; + uint8_t render_object; //0=sw, 1=hw accelerated render + uint8_t class_id; + uint8_t ramin_offset; //find + }; + }; } nv3_pramin_context_t; @@ -1110,8 +1167,6 @@ uint32_t nv3_cio_read(uint32_t address); void nv3_cio_write(uint32_t address, uint32_t value); uint32_t nv3_pbus_read(uint32_t address); void nv3_pbus_write(uint32_t address, uint32_t value); -uint32_t nv3_pfifo_read(uint32_t address); -void nv3_pfifo_write(uint32_t address, uint32_t value); uint32_t nv3_prm_read(uint32_t address); void nv3_prm_write(uint32_t address, uint32_t value); uint32_t nv3_prmio_read(uint32_t address); @@ -1133,8 +1188,6 @@ uint32_t nv3_palt_read(uint32_t address); void nv3_palt_write(uint32_t address, uint32_t value); uint32_t nv3_pme_read(uint32_t address); void nv3_pme_write(uint32_t address, uint32_t value); -uint32_t nv3_pgraph_read(uint32_t address); -void nv3_pgraph_write(uint32_t address, uint32_t value); // TODO: PGRAPH class registers @@ -1163,11 +1216,18 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now); // NV3 PGRAPH void nv3_pgraph_init(); +uint32_t nv3_pgraph_read(uint32_t address); +void nv3_pgraph_write(uint32_t address, uint32_t value); void nv3_pgraph_vblank_start(svga_t* svga); // NV3 PFIFO void nv3_pfifo_init(); +uint32_t nv3_pfifo_read(uint32_t address); +void nv3_pfifo_write(uint32_t address, uint32_t value); +// NV3 PFIFO - Caches +uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); +uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); // NV3 PFB void nv3_pfb_init(); diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index 2b38afbb4..0ee56443b 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -56,7 +56,7 @@ const char* nv3_class_names[] = "NV3 class 0x15: Stretched image from CPU", "NV3 INVALID class 0x16", "NV3 class 0x17: Direct3D 5.0 accelerated textured triangle w/zeta buffer", - "NV3 INVALID class 0x18", + "NV3 class 0x18: Point with zeta buffer", "NV3 INVALID class 0x19", "NV3 INVALID class 0x1A", "NV3 INVALID class 0x1B", diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 1838faef5..b770116f3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -28,8 +28,6 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> - - // // ****** pfifo register list START ****** // @@ -206,4 +204,32 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) } } +} + +/* +https://en.wikipedia.org/wiki/Gray_code +WHY?????? IT'S NOT A TELEGRAPH IT'S A GPU????? + +Convert from a normal number to a total insanity number which is only used in PFIFO CACHE1 for ungodly and totally unknowable reasons +*/ +uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val) +{ + return (val) ^ (val >> 1); +} + +/* +Back to sanity +*/ +uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) +{ + uint32_t mask = val >> 1; + + // shift right until we have our normla number again + while (mask) + { + val ^= mask; + mask >>= 1; + } + + return val; } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 32f87ee30..fbdf058ec 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -120,6 +120,17 @@ uint32_t nv3_pgraph_read(uint32_t address) { switch (reg->address) { + case NV3_PGRAPH_DEBUG_0: + ret = nv3->pgraph.debug_0; + break; + case NV3_PGRAPH_DEBUG_1: + ret = nv3->pgraph.debug_1; + break; + case NV3_PGRAPH_DEBUG_2: + ret = nv3->pgraph.debug_2; + break; + case NV3_PGRAPH_DEBUG_3: + ret = nv3->pgraph.debug_3; //interrupt status and enable regs case NV3_PGRAPH_INTR_0: ret = nv3->pgraph.interrupt_status_0; @@ -133,6 +144,101 @@ uint32_t nv3_pgraph_read(uint32_t address) case NV3_PGRAPH_INTR_EN_1: ret = nv3->pgraph.interrupt_enable_1; break; + // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like + // during the driver initialisation process + + // In the future, these will most likely have their own functions... + + // Context Swithcing (THIS IS CONTROLLED BY PFIFO!) + case NV3_PGRAPH_CONTEXT_SWITCH: + ret = nv3->pgraph.context_switch; + break; + case NV3_PGRAPH_CONTEXT_CONTROL: + ret = *(uint32_t*)&nv3->pgraph.context_control; + break; + case NV3_PGRAPH_CONTEXT_USER: + ret = *(uint32_t*)&nv3->pgraph.context_user; + break; + // Clip + case NV3_PGRAPH_ABS_UCLIP_XMIN: + ret = nv3->pgraph.abs_uclip_xmin; + break; + case NV3_PGRAPH_ABS_UCLIP_XMAX: + ret = nv3->pgraph.abs_uclip_xmax; + break; + case NV3_PGRAPH_ABS_UCLIP_YMIN: + ret = nv3->pgraph.abs_uclip_ymin; + break; + case NV3_PGRAPH_ABS_UCLIP_YMAX: + ret = nv3->pgraph.abs_uclip_ymax; + break; + // Canvas + case NV3_PGRAPH_SRC_CANVAS_MIN: + ret = *(uint32_t*)&nv3->pgraph.src_canvas_min; + break; + case NV3_PGRAPH_SRC_CANVAS_MAX: + ret = *(uint32_t*)&nv3->pgraph.src_canvas_max; + break; + // Pattern + case NV3_PGRAPH_PATTERN_COLOR_0_0: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_0; + break; + case NV3_PGRAPH_PATTERN_COLOR_0_1: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_1; + break; + case NV3_PGRAPH_PATTERN_COLOR_1_0: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_0; + break; + case NV3_PGRAPH_PATTERN_COLOR_1_1: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_1; + break; + case NV3_PGRAPH_PATTERN_BITMAP_HIGH: + ret = nv3->pgraph.pattern_bitmap_high; + break; + case NV3_PGRAPH_PATTERN_BITMAP_LOW: + ret = nv3->pgraph.pattern_bitmap_low; + break; + // Beta factor + case NV3_PGRAPH_BETA: + ret = nv3->pgraph.beta_factor; + break; + // DMA + case NV3_PGRAPH_DMA: + ret = *(uint32_t*)&nv3->pgraph.dma_settings; + break; + case NV3_PGRAPH_NOTIFY: + ret = *(uint32_t*)&nv3->pgraph.notifier; + break; + // More clip + case NV3_PGRAPH_CLIP0_MIN: + ret = *(uint32_t*)&nv3->pgraph.clip0_min; + break; + case NV3_PGRAPH_CLIP0_MAX: + ret = *(uint32_t*)&nv3->pgraph.clip0_max; + break; + case NV3_PGRAPH_CLIP1_MIN: + ret = *(uint32_t*)&nv3->pgraph.clip1_min; + break; + case NV3_PGRAPH_CLIP1_MAX: + ret = *(uint32_t*)&nv3->pgraph.clip1_max; + break; + case NV3_PGRAPH_CLIP_MISC: + ret = *(uint32_t*)&nv3->pgraph.clip_misc_settings; + break; + // Overall Status + case NV3_PGRAPH_STATUS: + ret = *(uint32_t*)&nv3->pgraph.status; + break; + // Trapped Address + case NV3_PGRAPH_TRAPPED_ADDRESS: + ret = nv3->pgraph.trapped_address; + break; + case NV3_PGRAPH_TRAPPED_DATA: + ret = nv3->pgraph.trapped_data; + break; + case NV3_PGRAPH_TRAPPED_INSTANCE: + ret = nv3->pgraph.trapped_instance; + break; } } @@ -189,6 +295,18 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) { switch (reg->address) { + case NV3_PGRAPH_DEBUG_0: + nv3->pgraph.debug_0 = value; + break; + case NV3_PGRAPH_DEBUG_1: + nv3->pgraph.debug_1 = value; + break; + case NV3_PGRAPH_DEBUG_2: + nv3->pgraph.debug_2 = value; + break; + case NV3_PGRAPH_DEBUG_3: + nv3->pgraph.debug_3 = value; + break; //interrupt status and enable regs case NV3_PGRAPH_INTR_0: nv3->pgraph.interrupt_status_0 &= ~value; @@ -210,6 +328,101 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) nv3->pgraph.interrupt_enable_1 = value & 0x00011111; nv3_pmc_handle_interrupts(true); + break; + // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like + // during the driver initialisation process + + // In the future, these will most likely have their own functions... + + // Context Swithcing (THIS IS CONTROLLED BY PFIFO!) + case NV3_PGRAPH_CONTEXT_SWITCH: + nv3->pgraph.context_switch = value; + break; + case NV3_PGRAPH_CONTEXT_CONTROL: + *(uint32_t*)&nv3->pgraph.context_control = value; + break; + case NV3_PGRAPH_CONTEXT_USER: + *(uint32_t*)&nv3->pgraph.context_user = value; + break; + // Clip + case NV3_PGRAPH_ABS_UCLIP_XMIN: + nv3->pgraph.abs_uclip_xmin = value; + break; + case NV3_PGRAPH_ABS_UCLIP_XMAX: + nv3->pgraph.abs_uclip_xmax = value; + break; + case NV3_PGRAPH_ABS_UCLIP_YMIN: + nv3->pgraph.abs_uclip_ymin = value; + break; + case NV3_PGRAPH_ABS_UCLIP_YMAX: + nv3->pgraph.abs_uclip_ymax = value; + break; + // Canvas + case NV3_PGRAPH_SRC_CANVAS_MIN: + *(uint32_t*)&nv3->pgraph.src_canvas_min = value; + break; + case NV3_PGRAPH_SRC_CANVAS_MAX: + *(uint32_t*)&nv3->pgraph.src_canvas_max = value; + break; + // Pattern + case NV3_PGRAPH_PATTERN_COLOR_0_0: + *(uint32_t*)&nv3->pgraph.pattern_color_0_0 = value; + break; + case NV3_PGRAPH_PATTERN_COLOR_0_1: + *(uint32_t*)&nv3->pgraph.pattern_color_0_1 = value; + break; + case NV3_PGRAPH_PATTERN_COLOR_1_0: + *(uint32_t*)&nv3->pgraph.pattern_color_1_0 = value; + break; + case NV3_PGRAPH_PATTERN_COLOR_1_1: + *(uint32_t*)&nv3->pgraph.pattern_color_1_1 = value; + break; + case NV3_PGRAPH_PATTERN_BITMAP_HIGH: + nv3->pgraph.pattern_bitmap_high = value; + break; + case NV3_PGRAPH_PATTERN_BITMAP_LOW: + nv3->pgraph.pattern_bitmap_low = value; + break; + // Beta factor + case NV3_PGRAPH_BETA: + nv3->pgraph.beta_factor = value; + break; + // DMA + case NV3_PGRAPH_DMA: + *(uint32_t*)&nv3->pgraph.dma_settings = value; + break; + case NV3_PGRAPH_NOTIFY: + *(uint32_t*)&nv3->pgraph.notifier = value; + break; + // More clip + case NV3_PGRAPH_CLIP0_MIN: + *(uint32_t*)&nv3->pgraph.clip0_min = value; + break; + case NV3_PGRAPH_CLIP0_MAX: + *(uint32_t*)&nv3->pgraph.clip0_max = value; + break; + case NV3_PGRAPH_CLIP1_MIN: + *(uint32_t*)&nv3->pgraph.clip1_min = value; + break; + case NV3_PGRAPH_CLIP1_MAX: + *(uint32_t*)&nv3->pgraph.clip1_max = value; + break; + case NV3_PGRAPH_CLIP_MISC: + *(uint32_t*)&nv3->pgraph.clip_misc_settings = value; + break; + // Overall Status + case NV3_PGRAPH_STATUS: + *(uint32_t*)&nv3->pgraph.status = value; + break; + // Trapped Address + case NV3_PGRAPH_TRAPPED_ADDRESS: + nv3->pgraph.trapped_address = value; + break; + case NV3_PGRAPH_TRAPPED_DATA: + nv3->pgraph.trapped_data = value; + break; + case NV3_PGRAPH_TRAPPED_INSTANCE: + nv3->pgraph.trapped_instance = value; break; } } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index e06445755..a3872c40a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -6,7 +6,7 @@ * * This file is part of the 86Box distribution. * - * NV3 PFIFO RAMFC area: Stores context unused DMA channels + * NV3 PFIFO RAMFC area: Stores context for unused DMA channels * * * @@ -30,10 +30,10 @@ uint32_t nv3_ramfc_read(uint32_t address) { - nv_log("NV3: RAMFC (Unused DMA channel context) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00", address); + nv_log("NV3: RAMFC (Unused DMA channel context) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); } void nv3_ramfc_write(uint32_t address, uint32_t value) { - nv_log("NV3: RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x), UNIMPLEMENTED", value, address); + nv_log("NV3: RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index ff72e811c..7df99d697 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -35,17 +35,17 @@ It is used to get the offset within RAMHT of a graphics object. uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel) { uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel); - nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)", name, channel); + nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", name, channel); return hash; } uint32_t nv3_ramht_read(uint32_t address) { - nv_log("NV3: RAMHT (Graphics object storage hashtable) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00", address); + nv_log("NV3: RAMHT (Graphics object storage hashtable) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); } void nv3_ramht_write(uint32_t address, uint32_t value) { - nv_log("NV3: RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), UNIMPLEMENTED", value, address); + nv_log("NV3: RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 6176e191a..b7d8f4f57 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -30,10 +30,10 @@ uint32_t nv3_ramro_read(uint32_t address) { - nv_log("NV3: RAM Runout (invalid dma object submission) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00", address); + nv_log("NV3: RAM Runout (invalid dma object submission) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); } void nv3_ramro_write(uint32_t address, uint32_t value) { - nv_log("NV3: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)", value, address); + nv_log("NV3: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)\n", value, address); } \ No newline at end of file From e4f446c6d019481a7d8510ef63704eda133c92d6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 22 Jan 2025 14:52:46 +0000 Subject: [PATCH 063/274] fix logging for ramin writes. --- doc/nvidia_notes/nv3_object_classes.txt | 2 +- src/include/86box/nv/vid_nv3.h | 27 +++++++++++++++++++++++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 13 ++++++++++-- src/video/nv/nv3/subsystems/nv3_pramin.c | 16 ++++++++++++-- 4 files changed, 52 insertions(+), 6 deletions(-) diff --git a/doc/nvidia_notes/nv3_object_classes.txt b/doc/nvidia_notes/nv3_object_classes.txt index 3cb99882b..05d1d9bf3 100644 --- a/doc/nvidia_notes/nv3_object_classes.txt +++ b/doc/nvidia_notes/nv3_object_classes.txt @@ -26,7 +26,7 @@ Object classes as understood by the GPU. 0x15 = Stretched image from CPU 0x16 = INVALID 0x17 = Direct3D 5.0 accelerated textured triangle w/zeta buffer -0x18 = INVALID +0x18 = Point w/zeta buffer 0x19 = INVALID 0x1A = INVALID 0x1B = INVALID diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index a2c54748e..4033873bb 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -242,6 +242,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_ACCESS 0x3000 #define NV3_PFIFO_CACHE0_DMA_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 +#define NV3_PFIFO_CACHE0_STATUS 0x3014 +#define NV3_PFIFO_CACHE0_STATUS_RANOUT 0 // 1 if we fucked up +#define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty +#define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit #define NV3_PFIFO_CACHE0_PULLER 0x3040 #define NV3_PFIFO_CACHE0_GET 0x3070 @@ -250,6 +254,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 +#define NV3_PFIFO_CACHE1_STATUS 0x3214 +#define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up +#define NV3_PFIFO_CACHE1_STATUS_LOW_MARK 4 // 1 if ramro is empty +#define NV3_PFIFO_CACHE1_STATUS_HIGH_MARK 8 #define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218 #define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220 #define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 @@ -740,6 +748,20 @@ typedef struct nv3_pbus_s nv3_pbus_rma_t rma; } nv3_pbus_t; +typedef struct nv3_pfifo_cache_s +{ + uint8_t put_address; // Trigger a DMA into the value you put here. + uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. + /* TODO */ +} nv3_pfifo_cache_t; + +typedef struct nv3_pfifo_cache_entry_s +{ + uint8_t subchannel_id : 3; + uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin) + uint32_t data; // is this the context +} nv3_pfifo_cache_entry_t; + // Command submission to PGRAPH typedef struct nv3_pfifo_s { @@ -749,7 +771,10 @@ typedef struct nv3_pfifo_s uint32_t ramfc_config; // RAMFC config uint32_t ramro_config; // RAMRO config uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? - + nv3_pfifo_cache_t cache0_settings; + nv3_pfifo_cache_t cache1_settings; + uint32_t cache0_status; // status of cache0 + uint32_t cache1_status; // status of cache1 } nv3_pfifo_t; // create_object(uint32_t type) here diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index b770116f3..990d085f2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> // -// ****** pfifo register list START ****** +// ****** PFIFO register list START ****** // nv_register_t pfifo_registers[] = { @@ -38,6 +38,12 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, + { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, + { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, + { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, + { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, + { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, + { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -101,6 +107,9 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CONFIG_RAMRO: ret = nv3->pfifo.ramro_config; break; + case NV3_PFIFO_CACHE0_GET: + //wa + break; } } @@ -220,7 +229,7 @@ uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val) /* Back to sanity */ -uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) +uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) { uint32_t mask = val >> 1; diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 35fa80603..ee6d0ddf5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -43,6 +43,8 @@ // Read 8-bit ramin uint8_t nv3_ramin_read8(uint32_t addr, void* priv) { + if (!nv3) return; + addr &= (nv3->nvbase.svga.vram_max - 1); uint32_t raw_addr = addr; // saved after and @@ -62,6 +64,8 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) // Read 16-bit ramin uint16_t nv3_ramin_read16(uint32_t addr, void* priv) { + if (!nv3) return; + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line @@ -86,6 +90,8 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) // Read 32-bit ramin uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { + if (!nv3) return; + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line @@ -111,6 +117,8 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) // Write 8-bit ramin void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) { + if (!nv3) return; + addr &= (nv3->nvbase.svga.vram_max - 1); uint32_t raw_addr = addr; // saved after and @@ -134,6 +142,8 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) // Write 16-bit ramin void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) { + if (!nv3) return; + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line @@ -149,7 +159,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) if (!nv3_pramin_arbitrate_write(addr, val32)) { vram_16bit[addr] = val; - nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr); + nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); } @@ -158,6 +168,8 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) // Write 32-bit ramin void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) { + if (!nv3) return; + addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line @@ -173,7 +185,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) if (!nv3_pramin_arbitrate_write(addr, val32)) { vram_32bit[addr] = val; - nv_log("NV3: Write dnv3_pramin_arbitrate_readword to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr); + nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); } } From 81404a35fc480477926721ab3d7f385ba3d1e9e3 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 22 Jan 2025 14:54:19 +0000 Subject: [PATCH 064/274] fix compilation --- src/video/nv/nv3/subsystems/nv3_pramin.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index ee6d0ddf5..a5c75ea21 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -43,7 +43,7 @@ // Read 8-bit ramin uint8_t nv3_ramin_read8(uint32_t addr, void* priv) { - if (!nv3) return; + if (!nv3) return 0x00; addr &= (nv3->nvbase.svga.vram_max - 1); uint32_t raw_addr = addr; // saved after and @@ -64,7 +64,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) // Read 16-bit ramin uint16_t nv3_ramin_read16(uint32_t addr, void* priv) { - if (!nv3) return; + if (!nv3) return 0x00; addr &= (nv3->nvbase.svga.vram_max - 1); @@ -90,7 +90,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) // Read 32-bit ramin uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { - if (!nv3) return; + if (!nv3) return 0x00; addr &= (nv3->nvbase.svga.vram_max - 1); From 07dc73bcf8c52904473406a57628b58984130a19 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 22 Jan 2025 15:28:14 +0000 Subject: [PATCH 065/274] fixes to the logging system and register names --- src/86box.c | 2 +- src/include/86box/nv/vid_nv3.h | 103 ++++++++++++----------- src/log.c | 10 ++- src/video/nv/nv3/nv3_core.c | 8 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- 5 files changed, 70 insertions(+), 55 deletions(-) diff --git a/src/86box.c b/src/86box.c index 97c211bee..a696dfc1e 100644 --- a/src/86box.c +++ b/src/86box.c @@ -267,7 +267,7 @@ void pclog_ensure_stdlog_open(void); #endif /* - Ensures STDLOG is open for pclog_ex and pclog_ex_cyclic + Ensures STDLOG is open for pclog_ex */ void pclog_ensure_stdlog_open(void) { diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 4033873bb..1976bd732 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 20 January 2025 (STILL WORKING ON IT!!!) + * Last updated: 2 January 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -267,7 +267,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULLER 0x3240 +#define NV3_PFIFO_CACHE1_PULLER_STATE0 0x3240 +#define NV3_PFIFO_CACHE1_PULLER_STATE0_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULLER_STATE0_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE1_PULLER_STATE0_DEVICE 8 #define NV3_PFIFO_CACHE1_PULLER_CONTEXT_IS_CLEAN 0x3250 #define NV3_PFIFO_CACHE1_GET 0x3270 #define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 @@ -445,56 +448,56 @@ extern const device_config_t nv3_config[]; // not sure about the class ids // these are NOT what each class is, just uSed to manipulate it (there isn't a one to one class->reg mapping anyway) -#define NV3_PGRAPH_CLASS18_BETA_START 0x410000 // Beta blending factor -#define NV3_PGRAPH_CLASS18_BETA_END 0x411FFF -#define NV3_PGRAPH_CLASS20_ROP_START 0x420000 // Blending render operation used at final pixel/fragment generation stage -#define NV3_PGRAPH_CLASS20_ROP_END 0x421FFF -#define NV3_PGRAPH_CLASS21_COLORKEY_START 0x430000 // Color key for image -#define NV3_PGRAPH_CLASS21_COLORKEY_END 0x431FFF -#define NV3_PGRAPH_CLASS22_PLANEMASK_START 0x440000 // Plane mask (for clipping?) -#define NV3_PGRAPH_CLASS22_PLANEMASK_END 0x441FFF -#define NV3_PGRAPH_CLASSXX_CLIP_START 0x450000 // clipping, probably class 23 -#define NV3_PGRAPH_CLASSXX_CLIP_END 0x451FFF -#define NV3_PGRAPH_CLASS24_PATTERN_START 0x460000 // presumably a blend pattern -#define NV3_PGRAPH_CLASS24_PATTERN_END 0x461FFF -#define NV3_PGRAPH_CLASS30_RECTANGLE_START 0x470000 // also class 25 - that's black [NV1] -#define NV3_PGRAPH_CLASS30_RECTANGLE_END 0x471FFF // also class 25 - that's black [NV1] -#define NV3_PGRAPH_CLASS26_POINT_START 0x480000 // A single point -#define NV3_PGRAPH_CLASS26_POINT_END 0x481FFF -#define NV3_PGRAPH_CLASS27_LINE_START 0x490000 // A line -#define NV3_PGRAPH_CLASS27_LINE_END 0x491FFF -#define NV3_PGRAPH_CLASS28_LIN_START 0x4A0000 // A lin - a line without its starting or ending pixels -#define NV3_PGRAPH_CLASS28_LIN_END 0x4A1FFF -#define NV3_PGRAPH_CLASS29_TRIANGLE_START 0x4B0000 // A triangle [NV1 variant] - in NV1 this was converted to a quad patch -#define NV3_PGRAPH_CLASS29_TRIANGLE_END 0x4B1FFF -#define NV3_PGRAPH_CLASS75_GDITEXT_START 0x4C0000 // Windows 95/NT GDI text acceleration -#define NV3_PGRAPH_CLASS75_GDITEXT_END 0x4C1FFF +#define NV3_PGRAPH_CLASS01_BETA_START 0x410000 // Beta blending factor +#define NV3_PGRAPH_CLASS01_BETA_END 0x411FFF +#define NV3_PGRAPH_CLASS02_ROP_START 0x420000 // Blending render operation used at final pixel/fragment generation stage +#define NV3_PGRAPH_CLASS02_ROP_END 0x421FFF +#define NV3_PGRAPH_CLASS03_COLORKEY_START 0x430000 // Color key for image +#define NV3_PGRAPH_CLASS03_COLORKEY_END 0x431FFF +#define NV3_PGRAPH_CLASS04_PLANEMASK_START 0x440000 // Plane mask (for clipping?) +#define NV3_PGRAPH_CLASS04_PLANEMASK_END 0x441FFF +#define NV3_PGRAPH_CLASS05_CLIP_START 0x450000 // clipping, probably class 23 +#define NV3_PGRAPH_CLASS05_CLIP_END 0x451FFF +#define NV3_PGRAPH_CLASS06_PATTERN_START 0x460000 // presumably a blend pattern +#define NV3_PGRAPH_CLASS06_PATTERN_END 0x461FFF +#define NV3_PGRAPH_CLASS07_RECTANGLE_START 0x470000 // also class 25 - that's black [NV1] +#define NV3_PGRAPH_CLASS07_RECTANGLE_END 0x471FFF // also class 25 - that's black [NV1] +#define NV3_PGRAPH_CLASS08_POINT_START 0x480000 // A single point +#define NV3_PGRAPH_CLASS08_POINT_END 0x481FFF +#define NV3_PGRAPH_CLASS09_LINE_START 0x490000 // A line +#define NV3_PGRAPH_CLASS09_LINE_END 0x491FFF +#define NV3_PGRAPH_CLASS0A_LIN_START 0x4A0000 // A lin - a line without its starting or ending pixels +#define NV3_PGRAPH_CLASS0A_LIN_END 0x4A1FFF +#define NV3_PGRAPH_CLASS0B_TRIANGLE_START 0x4B0000 // A triangle [NV1 variant] - in NV1 this was converted to a quad patch +#define NV3_PGRAPH_CLASS0B_TRIANGLE_END 0x4B1FFF +#define NV3_PGRAPH_CLASS0C_GDITEXT_START 0x4C0000 // Windows 95/NT GDI text acceleration +#define NV3_PGRAPH_CLASS0C_GDITEXT_END 0x4C1FFF -#define NV3_PGRAPH_CLASS61_MEM2MEM_XFER_START 0x4D0000 // memory to memory transfer (not sure about which class this is) -#define NV3_PGRAPH_CLASS61_MEM2MEM_XFER_END 0x4D1FFF -#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_SCALED_START 0x4E0000 // class 55, 56 -#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_SCALED_END 0x4E1FFF +#define NV3_PGRAPH_CLASS0D_MEM2MEM_XFER_START 0x4D0000 // memory to memory transfer (not sure about which class this is) +#define NV3_PGRAPH_CLASS0D_MEM2MEM_XFER_END 0x4D1FFF +#define NV3_PGRAPH_CLASS0E_IMAGE2MEM_XFER_SCALED_START 0x4E0000 // class 55, 56 +#define NV3_PGRAPH_CLASS0F_IMAGE2MEM_XFER_SCALED_END 0x4E1FFF -#define NV3_PGRAPH_CLASS31_BLIT_START 0x500000 // Blit 2d image from memory -#define NV3_PGRAPH_CLASS31_BLIT_END 0x501FFF +#define NV3_PGRAPH_CLASS10_BLIT_START 0x500000 // Blit 2d image from memory +#define NV3_PGRAPH_CLASS10_BLIT_END 0x501FFF -#define NV3_PGRAPH_CLASSXX_CPU2MEM_IMAGE_START 0x510000 // Used for class 33, 34, 54 -#define NV3_PGRAPH_CLASSXX_CPU2MEM_IMAGE_END 0x511FFF -#define NV3_PGRAPH_CLASSXX_CPU2MEM_BITMAP_START 0x520000 // not sure, might depend on format -#define NV3_PGRAPH_CLASSXX_CPU2MEM_BITMAP_END 0x521FFF +#define NV3_PGRAPH_CLASS11_CPU2MEM_IMAGE_START 0x510000 // Used for class 33, 34, 54 +#define NV3_PGRAPH_CLASS11_CPU2MEM_IMAGE_END 0x511FFF +#define NV3_PGRAPH_CLASS12_CPU2MEM_BITMAP_START 0x520000 // not sure, might depend on format +#define NV3_PGRAPH_CLASS12_CPU2MEM_BITMAP_END 0x521FFF -#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_START 0x540000 // send image to vram, not sure what class -#define NV3_PGRAPH_CLASSXX_IMAGE2MEM_XFER_END 0x541FFF -#define NV3_PGRAPH_CLASS54_CPU2MEM_STRETCHED_START 0x550000 // stretched cpu->vram transfer, 54 -#define NV3_PGRAPH_CLASS54_CPU2MEM_STRETCHED_END 0x551FFF +#define NV3_PGRAPH_CLASS14_IMAGE2MEM_XFER_START 0x540000 // send image to vram, not sure what class +#define NV3_PGRAPH_CLASS14_IMAGE2MEM_XFER_END 0x541FFF +#define NV3_PGRAPH_CLASS15_CPU2MEM_STRETCHED_START 0x550000 // stretched cpu->vram transfer, 54 +#define NV3_PGRAPH_CLASS15_CPU2MEM_STRETCHED_END 0x551FFF -#define NV3_PGRAPH_CLASS72_D3D5TRI_ZETA_START 0x570000 // [NV3] Copy a direct3d 5.0 accelerated triangle to the zeta buffer -#define NV3_PGRAPH_CLASS72_D3D5TRI_ZETA_END 0x571FFF -#define NV3_PGRAPH_CLASSXX_POINTZETA_START 0x580000 // possibly class 69 -#define NV3_PGRAPH_CLASSXX_POINTZETA_END 0x581FFF +#define NV3_PGRAPH_CLASS17_D3D5TRI_ZETA_START 0x570000 // [NV3] Copy a direct3d 5.0 accelerated triangle to the zeta buffer +#define NV3_PGRAPH_CLASS17_D3D5TRI_ZETA_END 0x571FFF +#define NV3_PGRAPH_CLASS18_POINTZETA_START 0x580000 // possibly class 69 +#define NV3_PGRAPH_CLASS18_POINTZETA_END 0x581FFF -#define NV3_PGRAPH_CLASS62_MEM2IMAGE_START 0x5C0000 // class 55, 56, 62, 63? -#define NV3_PGRAPH_CLASS62_MEM2IMAGE_END 0x5C1FFF +#define NV3_PGRAPH_CLASS1C_MEM2IMAGE_START 0x5C0000 // class 55, 56, 62, 63? +#define NV3_PGRAPH_CLASS1C_MEM2IMAGE_END 0x5C1FFF #define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers #define NV3_PGRAPH_REAL_END 0x5C1FFF @@ -600,6 +603,12 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_DATA_OUT 0x3C0 #define NV3_CRTC_MISCOUT 0x3C2 +#define NV3_RMA_REGISTER_START 0x3D0 +#define NV3_RMA_REGISTER_END 0x3D3 + +#define NV3_CRTC_REGISTER_INDEX 0x3D4 +#define NV3_CRTC_REGISTER_CURRENT 0x3D5 + // These are standard (0-18h) #define NV3_CRTC_REGISTER_HTOTAL 0x00 #define NV3_CRTC_REGISTER_HDISPEND 0x01 @@ -662,8 +671,6 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_BANKED_32K_B8000 0x0C -#define NV3_RMA_REGISTER_START 0x3D0 -#define NV3_RMA_REGISTER_END 0x3D3 #define NV3_CRTC_REGISTER_NVIDIA_END 0x3F // for 86box 8bit addressing diff --git a/src/log.c b/src/log.c index a4d84e616..7d1a9b8fa 100644 --- a/src/log.c +++ b/src/log.c @@ -46,6 +46,7 @@ typedef struct log_t { char cyclic_buff[LOG_SIZE_BUFFER_CYCLIC_LINES][LOG_SIZE_BUFFER]; // Cyclical log buffer. This is 32kb, might calloc? int32_t cyclic_last_line; int32_t log_cycles; + int32_t last_repeat_order; // used to detect changes between different repeating patterns } log_t; extern FILE *stdlog; /* file to log output to */ @@ -216,6 +217,13 @@ log_out_cyclic(void* priv, const char* fmt, va_list ap) { log->log_cycles++; + // If the order of the log repeat changes + if (log->last_repeat_order != repeat_order + && log->last_repeat_order > 0) + { + log->log_cycles = 1; + } + if (log->log_cycles == 1) { // 'Replay' the last few log entries so they actually show up @@ -251,7 +259,7 @@ log_out_cyclic(void* priv, const char* fmt, va_list ap) } log->cyclic_last_line++; - + log->last_repeat_order = repeat_order; #endif } diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 9cf8a602a..5e7017c65 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -575,10 +575,10 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv) switch (addr) { // Alias for "get current SVGA CRTC register ID" - case 0x3D4: + case NV3_CRTC_REGISTER_INDEX: ret = nv3->nvbase.svga.crtcreg; break; - case 0x3D5: + case NV3_CRTC_REGISTER_CURRENT: // Support the extended NVIDIA CRTC register range switch (nv3->nvbase.svga.crtcreg) { @@ -644,12 +644,12 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) switch (addr) { - case 0x3D4: + case NV3_CRTC_REGISTER_INDEX: // real mode access to GPU MMIO space... nv3->nvbase.svga.crtcreg = val; break; // support the extended crtc regs and debug this out - case 0x3D5: + case NV3_CRTC_REGISTER_CURRENT: // Implements the VGA Protect register if ((nv3->nvbase.svga.crtcreg < NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80)) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index a5c75ea21..8203519c5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -185,7 +185,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) if (!nv3_pramin_arbitrate_write(addr, val32)) { vram_32bit[addr] = val; - nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } } From 94af12da439fed03bd6663e93bd2eb393bc43720 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 23 Jan 2025 23:55:41 +0000 Subject: [PATCH 066/274] prepare for implementation of multithreaded renderer and add some of the simpler pfifo registers. e.g. debug0, which the driver writes to. --- .../nv3_object_classes_driver.txt | 2 +- .../86box/nv/classes/vid_nv3_classes.h | 2 +- src/include/86box/nv/vid_nv3.h | 50 ++++++-- src/video/nv/nv3/nv3_core.c | 6 +- src/video/nv/nv3/nv3_core_config.c | 108 ++++++++++++++++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 39 ++++++- 6 files changed, 183 insertions(+), 24 deletions(-) diff --git a/doc/nvidia_notes/nv3_object_classes_driver.txt b/doc/nvidia_notes/nv3_object_classes_driver.txt index 83b421335..3e4955a80 100644 --- a/doc/nvidia_notes/nv3_object_classes_driver.txt +++ b/doc/nvidia_notes/nv3_object_classes_driver.txt @@ -47,7 +47,7 @@ object class 64/40h = video scaler object class 65/41h = video color key (as opposed to image) object class 66/42h = capture video to memory object class 67/43h = Solid ROP5 -object class 68/44h = zeta buffer (something to do with how the gpu internally renders 3d stuff) from CPU(?) +object class 68/44h = zeta buffer (combined z and stencil buffer) from CPU(?) object class 69/45h = zeta buffer in VRAM object class 70/46h = zeta buffer patchcord object class 71/47h = render solid point into zeta buffer (Also rectangle0 diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 099c0bdc6..afe3fe18d 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -660,7 +660,7 @@ typedef struct nv3_object_class_015 0x?? (drivers) Also 0x57 in context IDs. - Direct3D 5.0 accelerated triangle with zeta buffer (Not the same as a Zbuffer...) + Direct3D 5.0 accelerated triangle with zeta buffer (combined z buffer and stencil buffer) This is the final boss of this GPU. True horror stands below. */ diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 1976bd732..37c4683d5 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -200,6 +200,10 @@ extern const device_config_t nv3_config[]; #define NV3_PBUS_END 0x1FFF #define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects) +#define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register +#define NV3_PFIFO_CACHE0_ERROR_PENDING 0 +#define NV3_PFIFO_CACHE1_ERROR_PENDING 1 + #define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status #define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable @@ -247,7 +251,12 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty #define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE0_PULLER 0x3040 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE0_PULLER_STATE1 0x3050 +#define NV3_PFIFO_CACHE0_PULLER_STATE1_CTX_IS_CLEAN 4 #define NV3_PFIFO_CACHE0_GET 0x3070 #define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit #define NV3_PFIFO_CACHE1_ACCESS 0x3200 @@ -267,11 +276,12 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULLER_STATE0 0x3240 -#define NV3_PFIFO_CACHE1_PULLER_STATE0_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULLER_STATE0_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE1_PULLER_STATE0_DEVICE 8 -#define NV3_PFIFO_CACHE1_PULLER_CONTEXT_IS_CLEAN 0x3250 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250 +#define NV3_PFIFO_CACHE1_PULLER_STATE1_CTX_IS_CLEAN 4 #define NV3_PFIFO_CACHE1_GET 0x3270 #define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 #define NV3_PFIFO_END 0x3FFF @@ -759,6 +769,26 @@ typedef struct nv3_pfifo_cache_s { uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. + uint8_t channel_id; + uint32_t status; + uint32_t status_puller; + uint32_t control; + uint32_t context[8]; + + /* cache1 only + do we even need to emulate this? + */ + bool dma_enabled; // 0x3220 bit0 + bool dma_is_busy; // 0x3220 bit4 + uint32_t dma_length; + uint32_t dma_address; + uint8_t dma_target_node; // depends on card bus + uint8_t dma_tlb_tag; + uint8_t tlb_pte; // DMA Engine - Translation Lookaside Buffer + uint8_t tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres + + bool context_is_dirty; + /* TODO */ } nv3_pfifo_cache_t; @@ -767,6 +797,7 @@ typedef struct nv3_pfifo_cache_entry_s uint8_t subchannel_id : 3; uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin) uint32_t data; // is this the context + } nv3_pfifo_cache_entry_t; // Command submission to PGRAPH @@ -774,14 +805,17 @@ typedef struct nv3_pfifo_s { uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable + uint32_t debug_0; // Cache Debug register uint32_t ramht_config; // RAMHT config uint32_t ramfc_config; // RAMFC config uint32_t ramro_config; // RAMRO config uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? nv3_pfifo_cache_t cache0_settings; nv3_pfifo_cache_t cache1_settings; - uint32_t cache0_status; // status of cache0 - uint32_t cache1_status; // status of cache1 + + nv3_pfifo_cache_entry_t cache0_entries[1]; + nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS + } nv3_pfifo_t; // create_object(uint32_t type) here diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 5e7017c65..499c06a92 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -920,7 +920,7 @@ void* nv3_init(const device_t *info) nv_log("NV3: initialising core\n"); // Figure out which vbios the user selected - const char* vbios_id = device_get_config_bios("VBIOS"); + const char* vbios_id = device_get_config_bios("vbios"); const char* vbios_file = ""; // depends on the bus we are using @@ -941,8 +941,8 @@ void* nv3_init(const device_t *info) nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); // set the vram amount and gpu revision - uint32_t vram_amount = device_get_config_int("VRAM"); - nv3->nvbase.gpu_revision = device_get_config_int("Chip Revision"); + uint32_t vram_amount = device_get_config_int("vram_size"); + nv3->nvbase.gpu_revision = device_get_config_int("chip_revision"); // set up the bus and start setting up SVGA core if (nv3->nvbase.bus_generation == nv_bus_pci) diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index 3bc8692b9..ca4c3bf38 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -31,61 +31,105 @@ const device_config_t nv3_config[] = { // VBIOS type configuration { - .name = "VBIOS", + .name = "vbios", + #ifndef RELEASE_BUILD .description = "VBIOS", + #else + .description = "Model", + #endif .type = CONFIG_BIOS, .default_string = "NV3_VBIOS_ERAZOR_V15403", .default_int = 0, .bios = { { + #ifndef RELEASE_BUILD .name = "[NV3 - 1997-09-30] ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00)", .files_no = 1, + #else + .name = "[RIVA 128] ELSA Victory Erazor v1.47.01", .files_no = 1, + #endif .internal_name = "NV3_VBIOS_ERAZOR_V14700", .files = {NV3_VBIOS_ERAZOR_V14700, ""} }, { + #ifndef RELEASE_BUILD .name = "[NV3 - 1998-02-06] ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, + #else + .name = "[RIVA 128] ELSA Victory Erazor v1.54.03", .files_no = 1, + #endif .internal_name = "NV3_VBIOS_ERAZOR_V15403", .files = {NV3_VBIOS_ERAZOR_V15403, ""} }, { - .name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, + #ifndef RELEASE_BUILD + .name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, + #else + .name = "[RIVA 128] ELSA Victory Erazor v1.55.00", .files_no = 1, + #endif .internal_name = "NV3_VBIOS_ERAZOR_V15500", .files = {NV3_VBIOS_ERAZOR_V15500, ""} }, { + #ifndef RELEASE_BUILD .name = "[NV3 - 1998-01-14] Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO", .files_no = 1, + #else + .name = "[RIVA 128] Diamond Viper V330", .files_no = 1, + #endif .internal_name = "NV3_VBIOS_DIAMOND_V330_V162", .files = {NV3_VBIOS_DIAMOND_V330_V162, ""}, }, { + #ifndef RELEASE_BUILD .name = "[NV3 - 1997-09-06] ASUS AGP/3DP-V3000 BIOS 1.51B", .files_no = 1, + #else + .name = "[RIVA 128] ASUS AGP/3DP-V3000", .files_no = 1, + #endif .internal_name = "NV3_VBIOS_ASUS_V3000_V151", .files = {NV3_VBIOS_ASUS_V3000_V151, ""}, }, { + #ifndef RELEASE_BUILD .name = "[NV3 - 1997-12-17] STB Velocity 128 (RIVA 128) Ver.1.82", .files_no = 1, + #else + .name = "[RIVA 128] STB Velocity 128", .files_no = 1, + #endif .internal_name = "NV3_VBIOS_STB_V128_V182", .files = {NV3_VBIOS_STB_V128_V182, ""}, }, { + #ifndef RELEASE_BUILD .name = "[NV3T - 1998-09-15] Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1, + #else + .name = "[RIVA 128 ZX] Diamond Multimedia Viper V330 8MB", .files_no = 1, + #endif .internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B", .files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""}, }, { + #ifndef RELEASE_BUILD .name = "[NV3T - 1998-08-04] ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1, + #else + .name = "[RIVA 128 ZX] ASUS AGP-V3000 ZXTV", .files_no = 1, + #endif .internal_name = "NV3T_VBIOS_ASUS_V170", .files = {NV3T_VBIOS_ASUS_V170, ""}, }, { + #ifndef RELEASE_BUILD .name = "[NV3T - 1998-07-30] RIVA 128 ZX BIOS - V1.71B-N", .files_no = 1, + #else + .name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.71", .files_no = 1, + #endif .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171", .files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""}, }, - + { + #ifndef RELEASE_BUILD .name = "[NV3T+SGRAM - 1998-08-15] RIVA 128 ZX BIOS - V1.72B", .files_no = 1, + #else + .name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.72", .files_no = 1, + #endif .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172", .files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""}, }, @@ -93,18 +137,19 @@ const device_config_t nv3_config[] = }, // Memory configuration { - .name = "VRAM", + .name = "vram_size", .description = "VRAM Size", .type = CONFIG_SELECTION, .default_int = VRAM_SIZE_4MB, .selection = { - // This never existed officially but was planned. Same for 64-bit bus. Debug only +#ifndef RELEASE_BUILD + // This never existed officially but was planned. Debug only { .description = "2 MB (Never officially sold)", .value = VRAM_SIZE_2MB, }, - +#endif { .description = "4 MB", .value = VRAM_SIZE_4MB, @@ -117,26 +162,69 @@ const device_config_t nv3_config[] = }, { - .name = "Chip Revision", + .name = "chip_revision", .description = "Chip Revision", .type = CONFIG_SELECTION, .default_int = NV3_PCI_CFG_REVISION_B00, .selection = { +#ifndef RELEASE_BUILD { - .description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997)", + .description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997) with integrated PAUDIO sound card", +#else + .description = "RIVA 128 Prototype (Revision A)", +#endif .value = NV3_PCI_CFG_REVISION_A00, }, +#ifndef RELEASE_BUILD { - .description = "RIVA 128 (NV3) / Stepping B0 (August 1997)", + .description = "RIVA 128 / Stepping B0 (October 1997)", +#else + .description = "RIVA 128 (Revision B)", +#endif .value = NV3_PCI_CFG_REVISION_B00, }, +#ifndef RELEASE_BUILD { - .description = "RIVA 128 ZX (NV3T) / Stepping C0 (March 1998)", + .description = "NV3T - RIVA 128 ZX / Stepping C0 (March 1998)", +#else + .description = "RIVA 128 ZX (Revision C)", +#endif .value = NV3_PCI_CFG_REVISION_C00, }, } }, + // Multithreading configuration + { + + .name = "pgraph_threads", +#ifndef RELEASE_BUILD + .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", +#else + .description = "Render threads", +#endif + .type = CONFIG_SELECTION, + .default_int = 1, // todo: change later + .selection = + { + { + .description = "1 thread (Only use if issues appear with more threads)", + .value = 1, + }, + { + .description = "2 threads", + .value = 2, + }, + { + .description = "4 threads", + .value = 4, + }, + { + .description = "8 threads", + .value = 8, + }, + }, + }, { .type = CONFIG_END } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 990d085f2..3de7661e3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -38,6 +38,11 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, + { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller State0", NULL, NULL}, + { NV3_PFIFO_CACHE0_PULLER_STATE1, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller State0", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULLER_STATE1, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, + { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, @@ -97,6 +102,10 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_INTR_EN: ret = nv3->pfifo.interrupt_enable; break; + // Debug + case NV3_PFIFO_DEBUG_0: + ret = nv3->pfifo.debug_0; + break; // These may need to become functions. case NV3_PFIFO_CONFIG_RAMFC: ret = nv3->pfifo.ramfc_config; @@ -110,6 +119,17 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE0_GET: //wa break; + // Reassignment + case NV3_PFIFO_CACHE_REASSIGNMENT: + ret = nv3->pfifo.cache_reassignment & 0x01; //1bit meaningful + break; + // Control + case NV3_PFIFO_CACHE0_PULLER_CONTROL: + ret = nv3->pfifo.cache0_settings.control & 0xFF; // 8bits meaningful + break; + case NV3_PFIFO_CACHE1_PULLER_CONTROL: + ret = nv3->pfifo.cache1_settings.control & 0xFF; // only 8bits are meaningful + break; } } @@ -208,6 +228,21 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_log("NV3: RAMRO Reconfiguration\n" "Base Address in RAMIN: %d\n" "Size: 0x%08x bytes\n", ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9, new_size_ramro); + break; + case NV3_PFIFO_DEBUG_0: + nv3->pfifo.debug_0 = value; + break; + // Reassignment + case NV3_PFIFO_CACHE_REASSIGNMENT: + nv3->pfifo.cache_reassignment = value & 0x01; //1bit meaningful + break; + // Control + case NV3_PFIFO_CACHE0_PULLER_CONTROL: + nv3->pfifo.cache0_settings.control = value; // 8bits meaningful + break; + case NV3_PFIFO_CACHE1_PULLER_CONTROL: + nv3->pfifo.cache1_settings.control = value; // 8bits meaningful + break; } } @@ -236,8 +271,10 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) // shift right until we have our normla number again while (mask) { - val ^= mask; + // NT4 drivers v1.29 mask >>= 1; + val ^= mask; + } return val; From e5a566014e6133a876a53f5e0864ba0c133b9fd2 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 24 Jan 2025 00:33:27 +0000 Subject: [PATCH 067/274] implement prom subsystem, which i forgot existed --- src/include/86box/nv/vid_nv3.h | 3 ++- src/video/nv/nv3/nv3_core.c | 33 +++++++++++++++++++++--- src/video/nv/nv3/nv3_core_arbiter.c | 3 +-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 4 +-- src/video/nv/nv3/subsystems/nv3_ptimer.c | 1 - 5 files changed, 35 insertions(+), 9 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 37c4683d5..f0286e2db 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1248,7 +1248,8 @@ void nv3_pextdev_write(uint32_t address, uint32_t value); #define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS) #define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x) -uint32_t nv3_prom_read(uint32_t address); +// Reads from vbios are 8bit +uint8_t nv3_prom_read(uint32_t address); void nv3_prom_write(uint32_t address, uint32_t value); uint32_t nv3_palt_read(uint32_t address); void nv3_palt_write(uint32_t address, uint32_t value); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 499c06a92..761ca9cf9 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -22,7 +22,7 @@ #include <86Box/86box.h> #include <86Box/device.h> #include <86Box/mem.h> -#include <86box/io.h> +#include <86Box/io.h> #include <86box/pci.h> #include <86Box/rom.h> // DEPENDENT!!! #include <86Box/video.h> @@ -727,6 +727,35 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) nv_log("nv3_draw_cursor drawline=0x%04x", drawline); } +// MMIO 0x6000->0x7FFF is mapped to a mirror of the VBIOS. + +uint8_t nv3_prom_read(uint32_t address) +{ + // prom area is 64k, so... + // first see if we even have a rom of 64kb in size + uint32_t max_rom_size = NV3_PROM_END - NV3_PROM_START; + uint32_t real_rom_size = max_rom_size; + + // set it + if (nv3->nvbase.vbios.sz < max_rom_size) + real_rom_size = nv3->nvbase.vbios.sz; + + //get our real address + uint8_t rom_address = address & max_rom_size; + + // Does this mirror on real hardware? + if (rom_address >= real_rom_size) + return 0xFF; + else + return nv3->nvbase.vbios.rom[rom_address]; +} + +void nv3_prom_write(uint32_t address, uint32_t value) +{ + uint32_t real_addr = address & 0x1FFFF; + nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=)"); +} + // Initialise the MMIO mappings void nv3_init_mappings_mmio() { @@ -906,8 +935,6 @@ void nv3_update_mappings() } } - - // // Init code // diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index bab378b9f..88ab74fe5 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -189,8 +189,7 @@ uint32_t nv3_prm_read(uint32_t address) { return 0; }; void nv3_prm_write(uint32_t address, uint32_t value) {}; uint32_t nv3_prmio_read(uint32_t address) { return 0; }; void nv3_prmio_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_prom_read(uint32_t address) { return 0; }; -void nv3_prom_write(uint32_t address, uint32_t value) {}; + uint32_t nv3_palt_read(uint32_t address) { return 0; }; void nv3_palt_write(uint32_t address, uint32_t value) {}; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 3de7661e3..db657b63e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -125,10 +125,10 @@ uint32_t nv3_pfifo_read(uint32_t address) break; // Control case NV3_PFIFO_CACHE0_PULLER_CONTROL: - ret = nv3->pfifo.cache0_settings.control & 0xFF; // 8bits meaningful + ret = nv3->pfifo.cache0_settings.control; // 8bits meaningful break; case NV3_PFIFO_CACHE1_PULLER_CONTROL: - ret = nv3->pfifo.cache1_settings.control & 0xFF; // only 8bits are meaningful + ret = nv3->pfifo.cache1_settings.control; // only 8bits are meaningful break; } } diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index ab19c1e61..938389054 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -105,7 +105,6 @@ uint32_t nv3_ptimer_read(uint32_t address) { nv_log("NV3: PTIMER Read from 0x%08x", address); } - uint32_t ret = 0x00; From e760c5311364992639505c7df5323d0faf7b13f3 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 24 Jan 2025 00:35:40 +0000 Subject: [PATCH 068/274] whoops, missed comment and actually print address on read/write --- src/video/nv/nv3/nv3_core.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 761ca9cf9..ce67ee46c 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -727,7 +727,8 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) nv_log("nv3_draw_cursor drawline=0x%04x", drawline); } -// MMIO 0x6000->0x7FFF is mapped to a mirror of the VBIOS. +// MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. +// Note this area is 64kb and the vbios is only 32kb. See below.. uint8_t nv3_prom_read(uint32_t address) { @@ -745,15 +746,22 @@ uint8_t nv3_prom_read(uint32_t address) // Does this mirror on real hardware? if (rom_address >= real_rom_size) + { + nv_log("PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); return 0xFF; + } else - return nv3->nvbase.vbios.rom[rom_address]; + { + uint8_t val = nv3->nvbase.vbios.rom[rom_address]; + nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address);# + return val; + } } void nv3_prom_write(uint32_t address, uint32_t value) { uint32_t real_addr = address & 0x1FFFF; - nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=)"); + nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x)", address); } // Initialise the MMIO mappings From 334dbeb88314871f6842989352588fbdc304e49c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 24 Jan 2025 00:36:16 +0000 Subject: [PATCH 069/274] and the value too... --- src/video/nv/nv3/nv3_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index ce67ee46c..4f317a325 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -753,7 +753,7 @@ uint8_t nv3_prom_read(uint32_t address) else { uint8_t val = nv3->nvbase.vbios.rom[rom_address]; - nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address);# + nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); return val; } } @@ -761,7 +761,7 @@ uint8_t nv3_prom_read(uint32_t address) void nv3_prom_write(uint32_t address, uint32_t value) { uint32_t real_addr = address & 0x1FFFF; - nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x)", address); + nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value); } // Initialise the MMIO mappings From 3edc11a68274f0371b09d2795aa7d4c3521c3c84 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 24 Jan 2025 23:05:40 +0000 Subject: [PATCH 070/274] add ability to disable cyclical logging --- doc/nvidia_notes/2025-01-24.txt | 1 + .../How to optimise riva 128 applications.txt | 4 +++ doc/nvidia_notes/multithreading.pdn | Bin 0 -> 106011 bytes doc/nvidia_notes/multithreading.png | Bin 0 -> 117148 bytes src/video/nv/nv3/nv3_core.c | 8 ++--- src/video/nv/nv3/nv3_core_config.c | 8 +++++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 1 + src/video/nv/nv_base.c | 29 +++++++++++++++--- 8 files changed, 41 insertions(+), 10 deletions(-) create mode 100644 doc/nvidia_notes/2025-01-24.txt create mode 100644 doc/nvidia_notes/How to optimise riva 128 applications.txt create mode 100644 doc/nvidia_notes/multithreading.pdn create mode 100644 doc/nvidia_notes/multithreading.png diff --git a/doc/nvidia_notes/2025-01-24.txt b/doc/nvidia_notes/2025-01-24.txt new file mode 100644 index 000000000..e35818dc0 --- /dev/null +++ b/doc/nvidia_notes/2025-01-24.txt @@ -0,0 +1 @@ +THIS IS FIFOSERVICE!!!!!!!!!!!! \ No newline at end of file diff --git a/doc/nvidia_notes/How to optimise riva 128 applications.txt b/doc/nvidia_notes/How to optimise riva 128 applications.txt new file mode 100644 index 000000000..1c20aef2a --- /dev/null +++ b/doc/nvidia_notes/How to optimise riva 128 applications.txt @@ -0,0 +1,4 @@ +How to optimise riva 128 applications: +* Ensure any set of polygons with one texture is close to a multiple of 128 polygons. +* Try to sort areas of a model with one texture to as close to 128 polygons as possible for efficient submission due to the lack of texturing. +* Try to have around (32*128) for nv3 or (64*128) for nv3t polygons \ No newline at end of file diff --git a/doc/nvidia_notes/multithreading.pdn b/doc/nvidia_notes/multithreading.pdn new file mode 100644 index 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-8,8 +8,6 @@ * * NV3 bringup and device emulation. * - * Notes: - * xfree86 ref has INVERTED bit numbering? What? * * Authors: Connor Hyde, I need a better email address ;^) * @@ -747,13 +745,13 @@ uint8_t nv3_prom_read(uint32_t address) // Does this mirror on real hardware? if (rom_address >= real_rom_size) { - nv_log("PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); + nv_log("NV3: PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); return 0xFF; } else { uint8_t val = nv3->nvbase.vbios.rom[rom_address]; - nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); + nv_log("NV3: PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); return val; } } @@ -761,7 +759,7 @@ uint8_t nv3_prom_read(uint32_t address) void nv3_prom_write(uint32_t address, uint32_t value) { uint32_t real_addr = address & 0x1FFFF; - nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value); + nv_log("NV3: What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value); } // Initialise the MMIO mappings diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index ca4c3bf38..d32a7dfd7 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -225,6 +225,14 @@ const device_config_t nv3_config[] = }, }, }, +#ifndef RELEASE_BUILD + { + .name = "nv_debug_fulllog", + .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", + .type = CONFIG_BINARY, + .default_int = 0, + }, +#endif { .type = CONFIG_END } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index db657b63e..aaf27ab25 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -35,6 +35,7 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL}, { NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,}, + { NV3_PFIFO_DEBUG_0, "PFIFO - Debug 0", NULL, NULL, }, { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index 96e011430..af17bd3a7 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -18,12 +18,14 @@ // Common NV1/3/4... init #define HAVE_STDARG_H // wtf is this crap #include +#include #include #include - -#include <86box/log.h> -#include <86box/86box.h> -#include <86box/nv/vid_nv.h> +#include <86Box/86box.h> +#ifndef RELEASE_BUILD +#include <86Box/device.h> +#endif +#include <86Box/log.h> // Common logging @@ -32,9 +34,19 @@ int nv_do_log = ENABLE_NV_LOG; // A bit of kludge so that in the future we can abstract this function acorss multiple generations of Nvidia GPUs void* nv_log_device; +bool nv_log_full = false; void nv_log_set_device(void* device) { + // in case the cyclical logger doesn't show you the full context of what went on, you can enable this debug feature + #ifndef RELEASE_BUILD + if (device + && device_get_config_int("nv_debug_fulllog")) + { + nv_log_full = true; + } + #endif + nv_log_device = device; } @@ -48,7 +60,14 @@ void nv_log(const char *fmt, ...) if (nv_do_log) { va_start(ap, fmt); - log_out_cyclic(nv_log_device, fmt, ap); + // If our debug config option is configured, full log. Otherwise log with cyclical detection. + #ifndef RELEASE_BUILD + if (nv_log_full) + log_out(nv_log_device, fmt, ap); + else + #endif + log_out_cyclic(nv_log_device, fmt, ap); + va_end(ap); } } From 84cb84ed2fa4e6c8f1017f9850981118e86e9150 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 27 Jan 2025 01:35:21 +0000 Subject: [PATCH 071/274] add numerous reigsters for pfifo --- .../How to optimise riva 128 applications.txt | 4 +- src/include/86box/nv/vid_nv3.h | 62 ++++--- src/video/nv/nv3/subsystems/nv3_pfifo.c | 171 +++++++++++++++++- 3 files changed, 204 insertions(+), 33 deletions(-) diff --git a/doc/nvidia_notes/How to optimise riva 128 applications.txt b/doc/nvidia_notes/How to optimise riva 128 applications.txt index 1c20aef2a..004593a21 100644 --- a/doc/nvidia_notes/How to optimise riva 128 applications.txt +++ b/doc/nvidia_notes/How to optimise riva 128 applications.txt @@ -1,4 +1,6 @@ How to optimise riva 128 applications: * Ensure any set of polygons with one texture is close to a multiple of 128 polygons. * Try to sort areas of a model with one texture to as close to 128 polygons as possible for efficient submission due to the lack of texturing. -* Try to have around (32*128) for nv3 or (64*128) for nv3t polygons \ No newline at end of file +* Try to have around (32*128) for nv3 or (64*128) for nv3t polygons +* Get coding +* Alcohol \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index f0286e2db..2842cd5da 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -243,24 +243,27 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_REV_C 64 #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_ACCESS 0x3000 -#define NV3_PFIFO_CACHE0_DMA_CHANNEL_ID 0x3004 +#define NV3_PFIFO_CACHE0_PUSH_ACCESS 0x3000 +#define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 #define NV3_PFIFO_CACHE0_STATUS_RANOUT 0 // 1 if we fucked up #define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty #define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8 -#define NV3_PFIFO_CACHE0_PULLER_STATE1 0x3050 -#define NV3_PFIFO_CACHE0_PULLER_STATE1_CTX_IS_CLEAN 4 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY 0x3050 +#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY_BOOL 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 #define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE1_ACCESS 0x3200 -#define NV3_PFIFO_CACHE1_DMA_CHANNEL_ID 0x3204 +#define NV3_PFIFO_CACHE0_METHOD 0x3100 +#define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 +#define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 +#define NV3_PFIFO_CACHE1_PUSH_ACCESS 0x3200 +#define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 #define NV3_PFIFO_CACHE1_STATUS 0x3214 @@ -276,14 +279,17 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8 #define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250 -#define NV3_PFIFO_CACHE1_PULLER_STATE1_CTX_IS_CLEAN 4 +#define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 #define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 +#define NV3_PFIFO_CACHE1_METHOD 0x3300 +#define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2 +#define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13 #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 @@ -588,7 +594,8 @@ extern const device_config_t nv3_config[]; #define NV3_PRAMIN_RAMHT_SIZE_2 0x3FFF #define NV3_PRAMIN_RAMHT_SIZE_3 0x7FFF -#define NV3_PRAMIN_RAMAU_START 0x1C01000 // Auxillary area +/* OBSOLETE AREA for AUDIO probably. DO NOT USE! */ +#define NV3_PRAMIN_RAMAU_START 0x1C01000 #define NV3_PRAMIN_RAMAU_END 0x1C01BFF #define NV3_PRAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels #define NV3_PRAMIN_RAMFC_END 0x1C01DFF @@ -767,9 +774,10 @@ typedef struct nv3_pbus_s typedef struct nv3_pfifo_cache_s { + bool access_enabled; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. - uint8_t channel_id; + uint8_t channel_id; // The DMA channel ID of this cache. uint32_t status; uint32_t status_puller; uint32_t control; @@ -778,15 +786,19 @@ typedef struct nv3_pfifo_cache_s /* cache1 only do we even need to emulate this? */ + uint32_t dma_status; // 0x3218 bool dma_enabled; // 0x3220 bit0 bool dma_is_busy; // 0x3220 bit4 - uint32_t dma_length; - uint32_t dma_address; - uint8_t dma_target_node; // depends on card bus - uint8_t dma_tlb_tag; - uint8_t tlb_pte; // DMA Engine - Translation Lookaside Buffer - uint8_t tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres + uint32_t dma_state; // Corresponds to PFIFO_CACHE1_DMA0 + uint32_t dma_length; // Corresponds to PFIFO_CACHE1_DMA1 + uint32_t dma_address; // Corresponds to PFIFO_CACHE1_DMA2 + uint8_t dma_target_node; // Corresponds to PFIFO_CACHE1_DMA3 depends on card bus + uint8_t dma_tlb_tag; + uint8_t dma_tlb_pte; // DMA Engine - Translation Lookaside Buffer + uint8_t dma_tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres + uint16_t method_address; // address of the method (i.e. what method it is) + uint16_t method_subchannel; // subchannel bool context_is_dirty; /* TODO */ @@ -1293,6 +1305,10 @@ uint32_t nv3_pfifo_read(uint32_t address); void nv3_pfifo_write(uint32_t address, uint32_t value); // NV3 PFIFO - Caches +void nv3_pfifo_cache0_push(); +void nv3_pfifo_cache0_pull(); +void nv3_pfifo_cache1_push(); +void nv3_pfifo_cache1_pull(); uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index aaf27ab25..7956632f4 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -39,17 +39,33 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, - { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller State0", NULL, NULL}, - { NV3_PFIFO_CACHE0_PULLER_STATE1, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, + { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller Control", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller Control"}, + { NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller State0", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_STATE1, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - + { NV3_PFIFO_CACHE0_PUSH_ACCESS, "PFIFO - Cache0 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH_ACCESS, "PFIFO - Cache1 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 DMA Channel ID", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 DMA Channel ID", NULL, NULL, }, + { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, + //Cache1 exclusive stuff + { NV3_PFIFO_CACHE1_DMA_CONFIG_0, "PFIFO - Cache1 DMA Config0"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_1, "PFIFO - Cache1 DMA Config1"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_2, "PFIFO - Cache1 DMA Config2"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_3, "PFIFO - Cache1 DMA Config3"}, + { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA Translation Lookaside Buffer - Pagetable Base"}, + { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA Status"}, + + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -107,7 +123,7 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_DEBUG_0: ret = nv3->pfifo.debug_0; break; - // These may need to become functions. + // Some of these may need to become functions. case NV3_PFIFO_CONFIG_RAMFC: ret = nv3->pfifo.ramfc_config; break; @@ -117,6 +133,45 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CONFIG_RAMRO: ret = nv3->pfifo.ramro_config; break; + case NV3_PFIFO_CACHE0_PULLER_CONTROL: + ret = nv3->pfifo.cache0_settings.control; + break; + case NV3_PFIFO_CACHE1_PULLER_CONTROL: + ret = nv3->pfifo.cache1_settings.control; + break; + case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: + ret = nv3->pfifo.cache0_settings.context_is_dirty; + break; + case NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY: + ret = nv3->pfifo.cache1_settings.context_is_dirty; + break; + case NV3_PFIFO_CACHE0_PUSH_ACCESS: + ret = nv3->pfifo.cache0_settings.access_enabled; + break; + case NV3_PFIFO_CACHE1_PUSH_ACCESS: + ret = nv3->pfifo.cache1_settings.access_enabled; + break; + case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: + ret = nv3->pfifo.cache0_settings.channel_id; + break; + case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: + ret = nv3->pfifo.cache1_settings.channel_id; + break; + case NV3_PFIFO_CACHE0_STATUS: + /* Todo: Return values based on runout put/get*/ + ret = nv3->pfifo.cache0_settings.status; + break; + case NV3_PFIFO_CACHE1_STATUS: + ret = nv3->pfifo.cache1_settings.status; + break; + case NV3_PFIFO_CACHE0_METHOD: + ret = ((nv3->pfifo.cache0_settings.method_subchannel << 13) & 0x07) + | ((nv3->pfifo.cache0_settings.method_address << 2) & 0x7FF); + break; + case NV3_PFIFO_CACHE1_METHOD: + ret = ((nv3->pfifo.cache1_settings.method_subchannel << 13) & 0x07) + | ((nv3->pfifo.cache1_settings.method_address << 2) & 0x7FF); + break; case NV3_PFIFO_CACHE0_GET: //wa break; @@ -124,13 +179,34 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE_REASSIGNMENT: ret = nv3->pfifo.cache_reassignment & 0x01; //1bit meaningful break; + // Cache1 exclusive stuff // Control - case NV3_PFIFO_CACHE0_PULLER_CONTROL: - ret = nv3->pfifo.cache0_settings.control; // 8bits meaningful + case NV3_PFIFO_CACHE1_DMA_CONFIG_0: + ret = nv3->pfifo.cache1_settings.dma_state; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_1: + ret = nv3->pfifo.cache1_settings.dma_length; break; - case NV3_PFIFO_CACHE1_PULLER_CONTROL: - ret = nv3->pfifo.cache1_settings.control; // only 8bits are meaningful + case NV3_PFIFO_CACHE1_DMA_CONFIG_2: + ret = nv3->pfifo.cache1_settings.dma_address; break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_3: + ret = nv3->pfifo.cache1_settings.dma_target_node; + break; + case NV3_PFIFO_CACHE1_DMA_STATUS: + ret = nv3->pfifo.cache1_settings.dma_status; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: + ret = nv3->pfifo.cache1_settings.dma_tlb_pt_base; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PTE: + ret = nv3->pfifo.cache1_settings.dma_tlb_pte; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_TAG: + ret = nv3->pfifo.cache1_settings.dma_tlb_tag; + break; + + } } @@ -243,7 +319,64 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) break; case NV3_PFIFO_CACHE1_PULLER_CONTROL: nv3->pfifo.cache1_settings.control = value; // 8bits meaningful - + break; + case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: + nv3->pfifo.cache0_settings.context_is_dirty = value; + break; + case NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY: + nv3->pfifo.cache1_settings.context_is_dirty = value; + break; + case NV3_PFIFO_CACHE0_PUSH_ACCESS: + nv3->pfifo.cache0_settings.access_enabled = value; + break; + case NV3_PFIFO_CACHE1_PUSH_ACCESS: + nv3->pfifo.cache1_settings.access_enabled = value; + break; + case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: + nv3->pfifo.cache0_settings.channel_id = value; + break; + case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: + nv3->pfifo.cache1_settings.channel_id = value; + break; + case NV3_PFIFO_CACHE0_STATUS: + /* Todo: Return values based on runout put/get*/ + nv3->pfifo.cache0_settings.status = value; + break; + case NV3_PFIFO_CACHE1_STATUS: + nv3->pfifo.cache1_settings.status = value; + break; + case NV3_PFIFO_CACHE0_METHOD: + nv3->pfifo.cache0_settings.method_subchannel = (value >> 13) & 0x07; + nv3->pfifo.cache0_settings.method_address = (value >> 2) & 0x7FF; + + break; + case NV3_PFIFO_CACHE1_METHOD: + nv3->pfifo.cache1_settings.method_subchannel = (value >> 13) & 0x07; + nv3->pfifo.cache1_settings.method_address = (value >> 2) & 0x7FF; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_0: + nv3->pfifo.cache1_settings.dma_state = value; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_1: + nv3->pfifo.cache1_settings.dma_length = value; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_2: + nv3->pfifo.cache1_settings.dma_address = value; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_3: + nv3->pfifo.cache1_settings.dma_target_node = value; + break; + case NV3_PFIFO_CACHE1_DMA_STATUS: + nv3->pfifo.cache1_settings.dma_status = value; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: + nv3->pfifo.cache1_settings.dma_tlb_pt_base = value; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PTE: + nv3->pfifo.cache1_settings.dma_tlb_pte = value; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_TAG: + nv3->pfifo.cache1_settings.dma_tlb_tag = value; break; } } @@ -279,4 +412,24 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) } return val; +} + +void nv3_pfifo_cache0_push() +{ + +} + +void nv3_pfifo_cache0_pull() +{ + +} + +void nv3_pfifo_cache1_push() +{ + +} + +void nv3_pfifo_cache1_pull() +{ + } \ No newline at end of file From 5b3617efe61d5f8666406017dad2a991a5ff1574 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 28 Jan 2025 23:35:25 +0000 Subject: [PATCH 072/274] standardise on "ramin" over "pramin", add cache status registers --- src/include/86box/nv/vid_nv3.h | 135 +++++++++--------- src/video/nv/nv3/nv3_core_arbiter.c | 8 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 40 ++++-- src/video/nv/nv3/subsystems/nv3_pramin.c | 40 +++--- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 2 +- 5 files changed, 127 insertions(+), 98 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 2842cd5da..2a635e8b4 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 2 January 2025 (STILL WORKING ON IT!!!) + * Last updated: 28 January 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -231,8 +231,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_RUNOUT_STATUS 0x2400 #define NV3_PFIFO_RUNOUT_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_RUNOUT_STATUS_LOW_MARK 4 // 1 if ramro is empty -#define NV3_PFIFO_RUNOUT_STATUS_HIGH_MARK 8 +#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty +#define NV3_PFIFO_RUNOUT_STATUS_FULL 8 #define NV3_PFIFO_RUNOUT_PUT 0x2410 #define NV3_PFIFO_RUNOUT_PUT_ADDRESS 3 // 9:3 if small ramfc(?) otherwise 12:3 #define NV3_PFIFO_RUNOUT_GET 0x2420 @@ -247,9 +247,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 -#define NV3_PFIFO_CACHE0_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty -#define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8 +#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty +#define NV3_PFIFO_CACHE0_STATUS_FULL 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit #define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 #define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 @@ -268,8 +267,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 #define NV3_PFIFO_CACHE1_STATUS 0x3214 #define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_CACHE1_STATUS_LOW_MARK 4 // 1 if ramro is empty -#define NV3_PFIFO_CACHE1_STATUS_HIGH_MARK 8 +#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty +#define NV3_PFIFO_CACHE1_STATUS_FULL 8 #define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218 #define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220 #define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 @@ -583,32 +582,30 @@ extern const device_config_t nv3_config[]; // control structures for dma'd in graphics objects from pfifo // these all have configurable sizes, define them here -#define NV3_PRAMIN_START 0x1C00000 +#define NV3_RAMIN_START 0x1C00000 - - -#define NV3_PRAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects -#define NV3_PRAMIN_RAMHT_END 0x1C00FFF -#define NV3_PRAMIN_RAMHT_SIZE_0 0xFFF -#define NV3_PRAMIN_RAMHT_SIZE_1 0x1FFF -#define NV3_PRAMIN_RAMHT_SIZE_2 0x3FFF -#define NV3_PRAMIN_RAMHT_SIZE_3 0x7FFF +#define NV3_RAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects +#define NV3_RAMIN_RAMHT_END 0x1C00FFF +#define NV3_RAMIN_RAMHT_SIZE_0 0xFFF +#define NV3_RAMIN_RAMHT_SIZE_1 0x1FFF +#define NV3_RAMIN_RAMHT_SIZE_2 0x3FFF +#define NV3_RAMIN_RAMHT_SIZE_3 0x7FFF /* OBSOLETE AREA for AUDIO probably. DO NOT USE! */ -#define NV3_PRAMIN_RAMAU_START 0x1C01000 -#define NV3_PRAMIN_RAMAU_END 0x1C01BFF -#define NV3_PRAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels -#define NV3_PRAMIN_RAMFC_END 0x1C01DFF -#define NV3_PRAMIN_RAMFC_SIZE_0 0x1FF -#define NV3_PRAMIN_RAMFC_SIZE_1 0xFFF -#define NV3_PRAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions -#define NV3_PRAMIN_RAMRO_SIZE_0 0x1FF -#define NV3_PRAMIN_RAMRO_SIZE_1 0x1FFF -#define NV3_PRAMIN_RAMRO_END 0x1C01FFF -#define NV3_PRAMIN_RAMRM_START 0x1C02000 -#define NV3_PRAMIN_RAMRM_END 0x1C02FFF +#define NV3_RAMIN_RAMAU_START 0x1C01000 +#define NV3_RAMIN_RAMAU_END 0x1C01BFF +#define NV3_RAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels +#define NV3_RAMIN_RAMFC_END 0x1C01DFF +#define NV3_RAMIN_RAMFC_SIZE_0 0x1FF +#define NV3_RAMIN_RAMFC_SIZE_1 0xFFF +#define NV3_RAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions +#define NV3_RAMIN_RAMRO_SIZE_0 0x1FF +#define NV3_RAMIN_RAMRO_SIZE_1 0x1FFF +#define NV3_RAMIN_RAMRO_END 0x1C01FFF +#define NV3_RAMIN_RAMRM_START 0x1C02000 +#define NV3_RAMIN_RAMRM_END 0x1C02FFF -#define NV3_PRAMIN_END 0x1FFFFFF +#define NV3_RAMIN_END 0x1FFFFFF // not done @@ -821,13 +818,19 @@ typedef struct nv3_pfifo_s uint32_t ramht_config; // RAMHT config uint32_t ramfc_config; // RAMFC config uint32_t ramro_config; // RAMRO config + // Runout stuff + uint32_t runout_put; + uint32_t runout_get; + + // Cache stuff uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? nv3_pfifo_cache_t cache0_settings; nv3_pfifo_cache_t cache1_settings; nv3_pfifo_cache_entry_t cache0_entries[1]; nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS - + + } nv3_pfifo_t; // create_object(uint32_t type) here @@ -1047,7 +1050,7 @@ typedef struct nv3_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; -typedef struct nv3_pramin_name_s +typedef struct nv3_ramin_name_s { union { @@ -1062,9 +1065,9 @@ typedef struct nv3_pramin_name_s }; }; -} nv3_pramin_name_t; +} nv3_ramin_name_t; -typedef struct nv3_pramin_context_s +typedef struct nv3_ramin_context_s { union { @@ -1080,27 +1083,27 @@ typedef struct nv3_pramin_context_s }; }; -} nv3_pramin_context_t; +} nv3_ramin_context_t; // Graphics object hashtable for specific DMA [channel, subchannel] pair -typedef struct nv3_pramin_ramht_subchannel_s +typedef struct nv3_ramin_ramht_subchannel_s { - nv3_pramin_name_t name; // must be >4096 + nv3_ramin_name_t name; // must be >4096 // Contextual information. // See the above union. - nv3_pramin_context_t context; -} nv3_pramin_ramht_subchannel_t; + nv3_ramin_context_t context; +} nv3_ramin_ramht_subchannel_t; // Graphics object hashtable -typedef struct nv3_pramin_ramht_s +typedef struct nv3_ramin_ramht_s { - nv3_pramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; -} nv3_pramin_ramht_t; + nv3_ramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; +} nv3_ramin_ramht_t; -uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel); +uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel); -typedef enum nv3_pramin_ramro_reason_e +typedef enum nv3_ramin_ramro_reason_e { nv3_runout_reason_illegal_access = 0, @@ -1117,37 +1120,40 @@ typedef enum nv3_pramin_ramro_reason_e // Access reserved by pagetable nv3_runout_reason_reserved_access = 5, -} nv3_pramin_ramro_reason; +} nv3_ramin_ramro_reason; /* This is a gigantic error handling system */ -typedef struct nv3_pramin_ramro_entry_s +typedef struct nv3_ramin_ramro_entry_s { //todo -} nv3_pramin_ramro_entry_t; +} nv3_ramin_ramro_entry_t; // Anti-fuckup device -typedef struct nv3_pramin_ramro_s +typedef struct nv3_ramin_ramro_s { -} nv3_pramin_ramro_t; +} nv3_ramin_ramro_t; // context for unused channels -typedef struct nv3_pramin_ramfc_s +typedef struct nv3_ramin_ramfc_s { -} nv3_pramin_ramfc_t; +} nv3_ramin_ramfc_t; -// ????? ram auxillary -typedef struct nv_pramin_ramau_s +// RAM for AUDIO - RevisionA ONLY +typedef struct nv_ramin_ramau_s { -} nv3_pramin_ramau_t; +} nv3_ramin_ramau_t; -typedef struct nv3_pramin_s +typedef struct nv3_ramin_s { -} nv3_pramin_t; +} nv3_ramin_t; + +// RAMIN functions +void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id); typedef struct nv3_pvideo_s { @@ -1179,11 +1185,11 @@ typedef struct nv3_s nv3_pgraph_t pgraph; // 2D/3D Graphics nv3_pextdev_t pextdev; // Chip configuration nv3_ptimer_t ptimer; // programmable interval timer - nv3_pramin_ramht_t ramht; // hashtable for PGRAPH objects - nv3_pramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission - nv3_pramin_ramfc_t ramfc; // context for unused channels - nv3_pramin_ramau_t ramau; // auxillary weirdnes - nv3_pramin_t pramin; // Ram for INput of DMA objects. Very important! + nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects + nv3_ramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission + nv3_ramin_ramfc_t ramfc; // context for unused channels + nv3_ramin_ramau_t ramau; // auxillary weirdnes + nv3_ramin_t pramin; // Ram for INput of DMA objects. Very important! nv3_pvideo_t pvideo; // Video overlay nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface //more here @@ -1222,8 +1228,8 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN -bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin -bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin +bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin +bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin uint32_t nv3_ramfc_read(uint32_t address); void nv3_ramfc_write(uint32_t address, uint32_t value); @@ -1284,7 +1290,7 @@ uint32_t nv3_user_read(uint32_t address); void nv3_user_write(uint32_t address, uint32_t value); #define nv3_object_submit_start nv3_user_read #define nv3_object_submit_end nv3_user_write -// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_* +// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_ramin_* // GPU subsystems @@ -1311,6 +1317,7 @@ void nv3_pfifo_cache1_push(); void nv3_pfifo_cache1_pull(); uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); +bool nv3_pfifo_cache1_is_free(); // NV3 PFB void nv3_pfb_init(); diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 88ab74fe5..2022625fd 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -104,8 +104,8 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); // RAMIN is handled by a separate memory mapping in PCI BAR1 - //else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - //ret = nv3_pramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function + //else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END) + //ret = nv3_ramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); @@ -167,8 +167,8 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) nv3_vram_write(address, value); else if (address >= NV3_USER_START && address <= NV3_USER_END) nv3_user_write(address, value); - else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END) - nv3_pramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions + else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END) + nv3_ramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions else { nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 7956632f4..4638b066e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -158,10 +158,28 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = nv3->pfifo.cache1_settings.channel_id; break; case NV3_PFIFO_CACHE0_STATUS: - /* Todo: Return values based on runout put/get*/ - ret = nv3->pfifo.cache0_settings.status; + uint32_t ret = 0x00; + + // CACHE0 has only one entry so it can only ever be empty or full + + if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache1_settings.get_address) + ret |= 1 << NV3_PFIFO_CACHE0_STATUS_EMPTY; + else + ret |= 1 << NV3_PFIFO_CACHE0_STATUS_FULL; + break; case NV3_PFIFO_CACHE1_STATUS: + if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) + ret |= 1 << NV3_PFIFO_CACHE1_STATUS_EMPTY; + + // Check if Cache1 (0x7C bytes in size depending on gpu?) is full + // Based on how the drivers do it + if (!nv3_pfifo_cache1_is_free()) + ret |= 1 << NV3_PFIFO_CACHE1_STATUS_FULL; + + if (nv3->pfifo.runout_put == nv3->pfifo.runout_get) + ret |= 1 << NV3_PFIFO_CACHE1_STATUS_RANOUT; + ret = nv3->pfifo.cache1_settings.status; break; case NV3_PFIFO_CACHE0_METHOD: @@ -338,13 +356,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: nv3->pfifo.cache1_settings.channel_id = value; break; - case NV3_PFIFO_CACHE0_STATUS: - /* Todo: Return values based on runout put/get*/ - nv3->pfifo.cache0_settings.status = value; - break; - case NV3_PFIFO_CACHE1_STATUS: - nv3->pfifo.cache1_settings.status = value; - break; + // CACHE0_STATUS and CACHE1_STATUS are not writable case NV3_PFIFO_CACHE0_METHOD: nv3->pfifo.cache0_settings.method_subchannel = (value >> 13) & 0x07; nv3->pfifo.cache0_settings.method_address = (value >> 2) & 0x7FF; @@ -432,4 +444,14 @@ void nv3_pfifo_cache1_push() void nv3_pfifo_cache1_pull() { +} + +bool nv3_pfifo_cache1_is_free() +{ + // convert to gray code + uint32_t real_get_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.get_address); + uint32_t real_put_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.put_address); + + // There is no hope of being able to understand it. Nobody can understand + return (real_get_address - real_put_address - 4) & 0x7C; // there are 64 entries what } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 8203519c5..9e013f4aa 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -52,7 +52,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) uint32_t val = 0x00; - if (!nv3_pramin_arbitrate_read(addr, &val)) // Oh well + if (!nv3_ramin_arbitrate_read(addr, &val)) // Oh well { val = (uint8_t)nv3->nvbase.svga.vram[addr]; nv_log("NV3: Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); @@ -78,7 +78,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) uint32_t val = 0x00; - if (!nv3_pramin_arbitrate_read(addr, &val)) + if (!nv3_ramin_arbitrate_read(addr, &val)) { val = (uint16_t)vram_16bit[addr]; nv_log("NV3: Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); @@ -104,7 +104,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) uint32_t val = 0x00; - if (!nv3_pramin_arbitrate_read(addr, &val)) + if (!nv3_ramin_arbitrate_read(addr, &val)) { val = vram_32bit[addr]; @@ -130,7 +130,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) uint32_t val32 = 0x00; - if (!nv3_pramin_arbitrate_write(addr, val32)) + if (!nv3_ramin_arbitrate_write(addr, val32)) { nv3->nvbase.svga.vram[addr] = val; nv_log("NV3: Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); @@ -156,7 +156,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) uint32_t val32 = 0x00; - if (!nv3_pramin_arbitrate_write(addr, val32)) + if (!nv3_ramin_arbitrate_write(addr, val32)) { vram_16bit[addr] = val; nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); @@ -182,7 +182,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) uint32_t val32 = 0x00; - if (!nv3_pramin_arbitrate_write(addr, val32)) + if (!nv3_ramin_arbitrate_write(addr, val32)) { vram_32bit[addr] = val; nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); @@ -198,7 +198,7 @@ and generic RAMIN Takes a pointer to a result integer. This is because we need to check its result in our normal write function. Returns true if a valid "non-generic" address was found (e.g. RAMFC/RAMRO/RAMHT). False if the specified address is a generic RAMIN address */ -bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value) +bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value) { if (!nv3) return 0x00; @@ -220,26 +220,26 @@ bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value) switch (ramht_size) { case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_0; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_0; break; case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_1; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_1; break; case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_2; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_2; break; case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_3; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_3; break; } switch (ramro_size) { case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B: - ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_0; + ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_0; break; case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K: - ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_1; + ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_1; break; } @@ -266,7 +266,7 @@ bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value) return false; } -bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value) +bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) { if (!nv3) return 0x00; @@ -288,26 +288,26 @@ bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value) switch (ramht_size) { case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_0; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_0; break; case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_1; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_1; break; case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_2; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_2; break; case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: - ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_3; + ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_3; break; } switch (ramro_size) { case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B: - ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_0; + ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_0; break; case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K: - ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_1; + ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_1; break; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index 7df99d697..6568e6db4 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -32,7 +32,7 @@ It is used to get the offset within RAMHT of a graphics object. */ -uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel) +uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel) { uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel); nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", name, channel); From 8c19d2682df259071a069b6104125c192804d6f2 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 29 Jan 2025 20:25:41 +0000 Subject: [PATCH 073/274] Create a bunch of placeholder c files for every single fucking class --- src/include/86box/nv/vid_nv3.h | 7 ++--- src/video/CMakeLists.txt | 26 +++++++++++++++++++ .../nv3/classes/nv3_class_001_beta_factor.c | 16 ++++++++++++ src/video/nv/nv3/classes/nv3_class_002_rop.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_003_chroma_key.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_004_plane_mask.c | 16 ++++++++++++ .../nv3_class_005_clipping_rectangle.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_006_pattern.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_007_rectangle.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_008_point.c | 16 ++++++++++++ src/video/nv/nv3/classes/nv3_class_009_line.c | 16 ++++++++++++ src/video/nv/nv3/classes/nv3_class_00a_lin.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_00b_triangle.c | 16 ++++++++++++ .../classes/nv3_class_00c_win95_gdi_text.c | 16 ++++++++++++ src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 16 ++++++++++++ .../nv3_class_00e_scaled_image_from_mem.c | 16 ++++++++++++ src/video/nv/nv3/classes/nv3_class_010_blit.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_011_image.c | 16 ++++++++++++ .../nv/nv3/classes/nv3_class_012_bitmap.c | 16 ++++++++++++ .../classes/nv3_class_014_transfer2memory.c | 16 ++++++++++++ .../nv3_class_015_stretched_image_from_cpu.c | 16 ++++++++++++ .../nv3_class_017_d3d5_tri_zeta_buffer.c | 16 ++++++++++++ .../classes/nv3_class_018_point_zeta_buffer.c | 16 ++++++++++++ .../classes/nv3_class_01c_image_in_memory.c | 16 ++++++++++++ src/video/nv/nv3/classes/nv3_class_names.c | 4 +-- src/video/nv/nv3/subsystems/nv3_pramin.c | 6 +++++ 26 files changed, 390 insertions(+), 5 deletions(-) create mode 100644 src/video/nv/nv3/classes/nv3_class_001_beta_factor.c create mode 100644 src/video/nv/nv3/classes/nv3_class_002_rop.c create mode 100644 src/video/nv/nv3/classes/nv3_class_003_chroma_key.c create mode 100644 src/video/nv/nv3/classes/nv3_class_004_plane_mask.c create mode 100644 src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c create mode 100644 src/video/nv/nv3/classes/nv3_class_006_pattern.c create mode 100644 src/video/nv/nv3/classes/nv3_class_007_rectangle.c create mode 100644 src/video/nv/nv3/classes/nv3_class_008_point.c create mode 100644 src/video/nv/nv3/classes/nv3_class_009_line.c create mode 100644 src/video/nv/nv3/classes/nv3_class_00a_lin.c create mode 100644 src/video/nv/nv3/classes/nv3_class_00b_triangle.c create mode 100644 src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c create mode 100644 src/video/nv/nv3/classes/nv3_class_00d_m2mf.c create mode 100644 src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c create mode 100644 src/video/nv/nv3/classes/nv3_class_010_blit.c create mode 100644 src/video/nv/nv3/classes/nv3_class_011_image.c create mode 100644 src/video/nv/nv3/classes/nv3_class_012_bitmap.c create mode 100644 src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c create mode 100644 src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c create mode 100644 src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c create mode 100644 src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c create mode 100644 src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 2a635e8b4..aa719a7d2 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1101,7 +1101,6 @@ typedef struct nv3_ramin_ramht_s nv3_ramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; } nv3_ramin_ramht_t; -uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel); typedef enum nv3_ramin_ramro_reason_e { @@ -1152,8 +1151,6 @@ typedef struct nv3_ramin_s } nv3_ramin_t; -// RAMIN functions -void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id); typedef struct nv3_pvideo_s { @@ -1231,6 +1228,10 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin +// RAMIN functions +uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel); +void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id); + uint32_t nv3_ramfc_read(uint32_t address); void nv3_ramfc_write(uint32_t address, uint32_t value); uint32_t nv3_ramro_read(uint32_t address); diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index b99f4fc4b..2135213fb 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -11,8 +11,11 @@ # Authors: David Hrdlička, # # Copyright 2020-2021 David Hrdlička. +# Copyright 2025 Connor Hyde # +# todo: Split nv stuff into its own file... + add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c vid_compaq_cga.c vid_mda.c vid_hercules.c vid_herculesplus.c vid_incolor.c vid_colorplus.c vid_genius.c vid_pgc.c vid_im1024.c @@ -43,6 +46,29 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c nv/nv3/subsystems/nv3_pvideo.c nv/nv3/classes/nv3_class_names.c + nv/nv3/classes/nv3_class_001_beta_factor.c + nv/nv3/classes/nv3_class_002_rop.c + nv/nv3/classes/nv3_class_003_chroma_key.c + nv/nv3/classes/nv3_class_004_plane_mask.c + nv/nv3/classes/nv3_class_005_clipping_rectangle.c + nv/nv3/classes/nv3_class_006_pattern.c + nv/nv3/classes/nv3_class_007_rectangle.c + nv/nv3/classes/nv3_class_008_point.c + nv/nv3/classes/nv3_class_009_line.c + nv/nv3/classes/nv3_class_00a_lin.c + nv/nv3/classes/nv3_class_00b_triangle.c + nv/nv3/classes/nv3_class_00c_win95_gdi_text.c + nv/nv3/classes/nv3_class_00d_m2mf.c + nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c + nv/nv3/classes/nv3_class_010_blit.c + nv/nv3/classes/nv3_class_011_image.c + nv/nv3/classes/nv3_class_012_bitmap.c + nv/nv3/classes/nv3_class_014_transfer2memory.c + nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c + nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c + nv/nv3/classes/nv3_class_018_point_zeta_buffer.c + nv/nv3/classes/nv3_class_01c_image_in_memory.c + ) if(G100) diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c new file mode 100644 index 000000000..2f9cdb066 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x01 (Beta factor) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c new file mode 100644 index 000000000..e3256d699 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x02 (Render operation) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c new file mode 100644 index 000000000..188f5f94e --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x02 (Chroma/color key) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c new file mode 100644 index 000000000..0797819d7 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x02 (Plane mask) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c new file mode 100644 index 000000000..c675be6e8 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x05 (Clipping rectangle) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c new file mode 100644 index 000000000..d75307a24 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x06 (Pattern) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c new file mode 100644 index 000000000..513f19496 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x07 (Rectangle) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c new file mode 100644 index 000000000..92561591a --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x08 (Point) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c new file mode 100644 index 000000000..d10501558 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x09 (Line) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c new file mode 100644 index 000000000..372a56e92 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x0A (Lin - a line without starting or ending pixels) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c new file mode 100644 index 000000000..1b8c23f03 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x0B (Basic triangle) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c new file mode 100644 index 000000000..9c58cf250 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x0C (Windows 95 GDI text acceleration) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c new file mode 100644 index 000000000..0b6c48cc1 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x0D (Reformat image in memory) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c new file mode 100644 index 000000000..6e90a552a --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x0E (Get image from vram and scale it) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c new file mode 100644 index 000000000..5e6f19aff --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x10 (Blit something) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c new file mode 100644 index 000000000..3334b4185 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x11 (Color image) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c new file mode 100644 index 000000000..b5c62f5f4 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x12 (Monochrome bitmap) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c new file mode 100644 index 000000000..c4b97a98a --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x14 (Transfer to Memory) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c new file mode 100644 index 000000000..951d77bce --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x15 (stretched image to memory) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c new file mode 100644 index 000000000..4e0463104 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x17 (Direct3D 5.0 accelerated triangle with zeta buffer) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c new file mode 100644 index 000000000..0440c39fe --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x18 (Point with zeta buffer) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c new file mode 100644 index 000000000..daea3e0bb --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -0,0 +1,16 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods for class 0x1C (Image in memory) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index 0ee56443b..3604d147b 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -12,7 +12,7 @@ * * Authors: Connor Hyde, I need a better email address ;^) * - * Copyright 2024-2025 starfrost + * Copyright 2024-2025 Connor Hyde */ #include #include @@ -34,7 +34,7 @@ const char* nv3_class_names[] = { "NV3 INVALID class 0x00", "NV3 class 0x01: Beta factor", - "NV3 class 0x02: ROP5 (32-bit) operation", + "NV3 class 0x02: Render operation", "NV3 class 0x03: Chroma key", "NV3 class 0x04: Plane mask", "NV3 class 0x05: Clipping rectangle", diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 9e013f4aa..f27ca0415 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -331,4 +331,10 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) } return false; +} + +// THIS IS THE MOST IMPORTANT FUNCTION! +void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id) +{ + // TODO: WRITE IT!!! } \ No newline at end of file From ce27b51ff5bd81cb2b307afbb516c85ab8d364a8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 29 Jan 2025 20:38:52 +0000 Subject: [PATCH 074/274] log.c in accordance with upstream --- src/log.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/src/log.c b/src/log.c index 6839e1243..129f2313f 100644 --- a/src/log.c +++ b/src/log.c @@ -40,7 +40,7 @@ typedef struct log_t { char *dev_name; int seen; int suppr_seen; - char cyclic_buff[LOG_SIZE_BUFFER_CYCLIC_LINES][LOG_SIZE_BUFFER]; // Cyclical log buffer. This is 32kb, might calloc? + char** cyclic_buff; int32_t cyclic_last_line; int32_t log_cycles; int32_t last_repeat_order; @@ -94,14 +94,6 @@ log_set_suppr_seen(void *priv, int suppr_seen) log->suppr_seen = suppr_seen; } -void -log_set_dev_name(void *priv, char *dev_name) -{ - log_t *log = (log_t *) priv; - - log->dev_name = dev_name; -} - /* Log something to the logfile or stdout. @@ -280,11 +272,14 @@ log_out_cyclic(void* priv, const char* fmt, va_list ap) fprintf(stdlog, "%s", temp); } - log->cyclic_last_line++; - - log->last_repeat_order = repeat_order; + log->cyclic_last_line++; + + log->last_repeat_order = repeat_order; + } +} #endif + void log_fatal(void *priv, const char *fmt, ...) { From 1e8c804cfdda0c87ff101198cb77fc98fe69daf3 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 31 Jan 2025 01:21:28 +0000 Subject: [PATCH 075/274] Implement RAMIN lookup and start the pullers. I hate nvidia --- src/include/86box/nv/vid_nv3.h | 116 +++++++------ src/log.c | 17 +- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 14 ++ src/video/nv/nv3/subsystems/nv3_pramin.c | 163 +++++++++++++++++- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 12 +- 6 files changed, 254 insertions(+), 70 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index aa719a7d2..651693257 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,8 +14,8 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 28 January 2025 (STILL WORKING ON IT!!!) - * + * Last updated: 30 January 2025 (STILL WORKING ON IT!!!) + * * Authors: Connor Hyde * * Copyright 2024-2025 Connor Hyde @@ -43,9 +43,16 @@ extern const device_config_t nv3_config[]; #define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. +#define NV3_LAST_VALID_GRAPHICS_OBJECT_ID 0x1F + +// The class ids are represented with 5 bits in PGRAPH, but 7 bits in PFIFO! +// What... +#define NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID 0x40 +#define NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID 0x5F + // Default value for the boot information register. // Depends on the chip -#define NV3_BOOT_REG_REV_A00 0x00030100 +#define NV3_BOOT_REG_REV_A00 0x00030100 // todo: format is wrong(?) for nv3a, fix it later #define NV3_BOOT_REG_REV_B00 0x00030110 #define NV3_BOOT_REG_REV_C00 0x00030120 @@ -72,7 +79,7 @@ extern const device_config_t nv3_config[]; #define VRAM_SIZE_2MB 0x200000 // 2MB #define VRAM_SIZE_4MB 0x400000 // 4MB #define VRAM_SIZE_8MB 0x800000 // NV3T only - +// There is also 1mb supported by the card but it was never used // PCI config #define NV3_PCI_CFG_VENDOR_ID 0x0 @@ -194,6 +201,7 @@ extern const device_config_t nv3_config[]; #define NV3_CIO_END 0x3df #define NV3_PBUS_START 0x1000 // Bus Control Subsystem #define NV3_PBUS_INTR 0x1100 // Bus Control - Interrupt Status + #define NV3_PBUS_INTR_EN 0x1140 // Bus Control - Interrupt Enable #define NV3_PBUS_PCI_START 0x1800 // PCI mirror start #define NV3_PBUS_PCI_END 0x18FF // PCI mirror end @@ -202,18 +210,25 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register #define NV3_PFIFO_CACHE0_ERROR_PENDING 0 -#define NV3_PFIFO_CACHE1_ERROR_PENDING 1 +#define NV3_PFIFO_CACHE1_ERROR_PENDING 4 #define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status #define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable +// PFIFO interrupts +#define NV3_PFIFO_INTR_CACHE_ERROR 0 +#define NV3_PFIFO_INTR_RUNOUT 4 +#define NV3_PFIFO_INTR_RUNOUT_OVERFLOW 8 +#define NV3_PFIFO_INTR_DMA_PUSHER 12 +#define NV3_PFIFO_INTR_DMA_PTE 16 + #define NV3_PFIFO_CONFIG_0 0x2200 #define NV3_PFIFO_CONFIG_0_DMA_FETCH 8 #define NV3_PFIFO_CONFIG_RAMHT 0x2210 // Hashtable for graphics objects config -#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 +#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 // 15:12 #define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS_DEFAULT 0x0 -#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 +#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 // 17:16 #define NV3_PFIFO_CONFIG_RAMHT_SIZE_4K 0x0 #define NV3_PFIFO_CONFIG_RAMHT_SIZE_8K 0x1 #define NV3_PFIFO_CONFIG_RAMHT_SIZE_16K 0x2 @@ -231,8 +246,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_RUNOUT_STATUS 0x2400 #define NV3_PFIFO_RUNOUT_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty -#define NV3_PFIFO_RUNOUT_STATUS_FULL 8 +#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty +#define NV3_PFIFO_RUNOUT_STATUS_FULL 8 #define NV3_PFIFO_RUNOUT_PUT 0x2410 #define NV3_PFIFO_RUNOUT_PUT_ADDRESS 3 // 9:3 if small ramfc(?) otherwise 12:3 #define NV3_PFIFO_RUNOUT_GET 0x2420 @@ -243,17 +258,18 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_REV_C 64 #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 + #define NV3_PFIFO_CACHE0_PUSH_ACCESS 0x3000 #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 -#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty -#define NV3_PFIFO_CACHE0_STATUS_FULL 8 +#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty +#define NV3_PFIFO_CACHE0_STATUS_FULL 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit #define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 #define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD 8 #define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY 0x3050 #define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY_BOOL 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 @@ -267,8 +283,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 #define NV3_PFIFO_CACHE1_STATUS 0x3214 #define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty -#define NV3_PFIFO_CACHE1_STATUS_FULL 8 +#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty +#define NV3_PFIFO_CACHE1_STATUS_FULL 8 #define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218 #define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220 #define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 @@ -279,9 +295,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA #define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 +//todo: merge stuff #define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD 8 // 0=software, 1=hardware #define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250 #define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 @@ -289,6 +306,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_METHOD 0x3300 #define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13 + #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 @@ -684,9 +702,8 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_BANKED_32K_B0000 0x08 #define NV3_CRTC_BANKED_32K_B8000 0x0C - - #define NV3_CRTC_REGISTER_NVIDIA_END 0x3F + // for 86box 8bit addressing // get rid of this asap, replace with 32->8 macros #define NV3_RMA_SIGNATURE_MSB 0x65 @@ -696,13 +713,11 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F - /* STRUCTURES FOR THE GPU START HERE OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H */ - //todo: pixel format // Master Control @@ -712,12 +727,15 @@ typedef struct nv3_pmc_s Holds chip manufacturing information at bootup. Current specification (may change later): pre-packed for convenience - FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?) - 31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001 - little endian 00000000 00000011 00000001 00010001 = 0x00300111 + Revision A: + FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?) + 31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001 + little endian 00000000 00000011 00000001 00010001 = 0x00300111# + Revision B/c: + write this later */ int32_t boot; - int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems. + int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems. int32_t interrupt_enable; // Determines if interrupts are actually enabled. int32_t enable; // Determines which subsystems are enabled. @@ -776,9 +794,9 @@ typedef struct nv3_pfifo_cache_s uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. uint8_t channel_id; // The DMA channel ID of this cache. uint32_t status; - uint32_t status_puller; + uint32_t puller_control; uint32_t control; - uint32_t context[8]; + uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; /* cache1 only do we even need to emulate this? @@ -1050,23 +1068,9 @@ typedef struct nv3_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv3_ptimer_t; -typedef struct nv3_ramin_name_s -{ - union - { - uint32_t name; - - struct - { - uint8_t byte_high; - uint8_t byte_mid2; - uint8_t byte_mid1; - uint8_t byte_low; - }; - }; - -} nv3_ramin_name_t; - +// Object name is just a uint32_t identifier it doesn't need a struct +// This is howt he cotnext is represented in ramin +// IN PGRAPH IT IS DIFFERENT! ONLY 5 BITS FOR THE CLASS ID! WHY? typedef struct nv3_ramin_context_s { union @@ -1075,11 +1079,11 @@ typedef struct nv3_ramin_context_s struct { - - uint8_t dma_channel; - uint8_t render_object; //0=sw, 1=hw accelerated render - uint8_t class_id; - uint8_t ramin_offset; //find + bool reserved : 1; + uint8_t channel_id : 7; + bool is_rendering : 1; + uint8_t class_id : 7; + uint16_t ramin_offset; }; }; @@ -1088,7 +1092,7 @@ typedef struct nv3_ramin_context_s // Graphics object hashtable for specific DMA [channel, subchannel] pair typedef struct nv3_ramin_ramht_subchannel_s { - nv3_ramin_name_t name; // must be >4096 + uint32_t name; // must be >4096 // Contextual information. // See the above union. @@ -1193,10 +1197,13 @@ typedef struct nv3_s } nv3_t; -// device objects +// device object extern nv3_t* nv3; -// NV3 stuff +/* + *FUNCTIONS* for the GPU core start here + Functions for PGRAPH objects are in vid_nv3_classes.h +*/ // Device Core void* nv3_init(const device_t *info); @@ -1229,8 +1236,8 @@ bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value); / bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin // RAMIN functions -uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel); -void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id); +uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel); +bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_id, uint32_t subchannel_id); uint32_t nv3_ramfc_read(uint32_t address); void nv3_ramfc_write(uint32_t address, uint32_t value); @@ -1310,6 +1317,7 @@ void nv3_pgraph_vblank_start(svga_t* svga); void nv3_pfifo_init(); uint32_t nv3_pfifo_read(uint32_t address); void nv3_pfifo_write(uint32_t address, uint32_t value); +void nv3_pfifo_interrupt(uint32_t id, bool fire_now); // NV3 PFIFO - Caches void nv3_pfifo_cache0_push(); diff --git a/src/log.c b/src/log.c index 129f2313f..fa39a6897 100644 --- a/src/log.c +++ b/src/log.c @@ -36,14 +36,15 @@ #include <86box/log.h> typedef struct log_t { - char buff[1024]; - char *dev_name; - int seen; - int suppr_seen; - char** cyclic_buff; - int32_t cyclic_last_line; - int32_t log_cycles; - int32_t last_repeat_order; + char buff[1024]; + char dev_name[1024]; + int seen; + int suppr_seen; + /* Cyclical log buffer. */ + char **cyclic_buff; + int32_t cyclic_last_line; + int32_t log_cycles; + int32_t last_repeat_order; } log_t; /* File to log output to. */ diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 57d19fc42..3aa1d497b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -6,7 +6,7 @@ * * This file is part of the 86Box distribution. * - * NV3 PBUS DMA: DMA Engine + * NV3 PBUS DMA: DMA & Notifier Engine * * * diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 4638b066e..b9e7e4cdd 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -433,7 +433,15 @@ void nv3_pfifo_cache0_push() void nv3_pfifo_cache0_pull() { + // Do nothing if PFIFO CACHE0 is disabled + if (!nv3->pfifo.cache0_settings.puller_control & (1 >> NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED)) + return; + // Do nothing if there is nothing in cache0 to pull + if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache0_settings.get_address) + return; + + // There is only one entry } void nv3_pfifo_cache1_push() @@ -443,7 +451,13 @@ void nv3_pfifo_cache1_push() void nv3_pfifo_cache1_pull() { + // Do nothing if PFIFO CACHE1 is disabled + if (!nv3->pfifo.cache1_settings.puller_control & (1 >> NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED)) + return; + // Do nothing if there is nothing in cache1 to pull + if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) + return; } bool nv3_pfifo_cache1_is_free() diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index f27ca0415..d9ab438d7 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -23,11 +23,17 @@ #include <86Box/86box.h> #include <86Box/device.h> #include <86Box/mem.h> -#include <86box/pci.h> +#include <86Box/pci.h> #include <86Box/rom.h> // DEPENDENT!!! #include <86Box/video.h> #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +// Functions only used in this translation unit +#ifndef RELEASE_BUILD +void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context); +#endif // i believe the main loop is to walk the hashtable in RAMIN (last 0.5 MB of VRAM), // find the objects that were submitted from DMA @@ -190,6 +196,12 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) } +void nv3_pfifo_interrupt(uint32_t id, bool fire_now) +{ + nv3->pfifo.interrupt_status |= (1 << id); + nv3_pmc_handle_interrupts(fire_now); +} + /* RAMIN access arbitration functions Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) (RAMAU?) @@ -311,6 +323,7 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) break; } + // send the addresses to the right part if (address >= ramht_start && address <= ramht_end) { @@ -334,7 +347,151 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) } // THIS IS THE MOST IMPORTANT FUNCTION! -void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id) +bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_id, uint32_t subchannel_id) { // TODO: WRITE IT!!! -} \ No newline at end of file + // Set the number of entries to search based on the ramht size (2*(size+1)) + // Not a switch statement in case newer gpus have larger ramins + uint32_t bucket_entries = 2 * (((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03) + 1); + + // Calculate the address in the hashtable + uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; + uint32_t ramht_cur_address = ramht_base; + + nv_log("NV3: Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel_id, subchannel_id); + + bool found_object = false; + + // set up some variables + uint32_t found_obj_name; + nv3_ramin_context_t obj_context_struct; + + for (uint32_t bucket_entry = 0; bucket_entry < bucket_entries; bucket_entry++) + { + found_obj_name = nv3_ramin_read32(ramht_cur_address, NULL); + ramht_cur_address += 0x04; + uint32_t obj_context = nv3_ramin_read32(ramht_cur_address, NULL); + ramht_cur_address += 0x04; + obj_context_struct = *(nv3_ramin_context_t*)&obj_context; + + // see if the object is in the right channel + if (found_obj_name == name + && obj_context_struct.channel_id == channel_id) + { + found_object = true; + break; + } + } + + if (!found_object) + { + if (!cache_num) + { + nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; + nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; + + //It turns itself off on failure, the drivers turn it back on + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + } + else + { + nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; + nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE; + + //It turns itself off on failure, the drivers turn it back on + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED; + } + + nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); + + return false; + } + + // So we did find an object. + // Now try to read some of this... + + // Class ID is 5 bits in all other parts of the gpu but 7 bits here. A move in a direction that didn't pan out? + // Represented as 0x40-0x5f? Some other meaning + + // Perform more validation + + if (obj_context_struct.class_id > NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID + || obj_context_struct.class_id < NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID) + { + fatal("NV3: Invalid graphics object class ID name=0x%04x type=%04x, interpreted by pgraph as: %04x (Contact starfrost)", + name, obj_context_struct.class_id, obj_context_struct.class_id & 0x1F); + } + else if (obj_context_struct.channel_id > NV3_DMA_CHANNELS) + fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-8", obj_context_struct.channel_id); + + // Illegal accesses sent to RAMRO, so ignore here + // TODO: SEND THESE TO RAMRO!!!!! + + #ifndef RELEASE_BUILD + nv3_debug_ramin_print_context_info(name, obj_context_struct); + #endif + + // By definition we can't have a cache error by here so take it off + if (!cache_num) + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; + else + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE; + + // Caches store all the subchannels for our current dma channel and basically get stale every context switch + // Also we have to check that a osftware object didn't end up in here... + + bool is_software = false; + if (!cache_num) + is_software = (nv3->pfifo.cache0_settings.context[subchannel_id] & 0x800000); + else + is_software = (nv3->pfifo.cache1_settings.context[subchannel_id] & 0x800000); + + // This isn't an error but it's sent as an interrupt so the drivers can sync + if (is_software) + { + // handle it as an error + if (!cache_num) + { + nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + } + else + { + nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED; + } + + // It's an error but it isn't lol + nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); + + } + else + { + // obviously turn off the "is software" if it's not + if (!cache_num) + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; + else + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD; + } + + // Ok we found it. Lol + return true; + +} + +#ifndef RELEASE_BUILD +// Prints out some informaiton about the object +void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context) +{ + nv_log("NV3: Found object:"); + nv_log("Name: 0x%04x", name); + + nv_log("Context:"); + nv_log("DMA Channel %d (0-7 valid)", context.channel_id); + nv_log("Class ID: as repreesnted in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)", context.class_id, + context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); + nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)", context.is_rendering); + nv_log("PRAMIN Offset 0x%08x", context.ramin_offset << 4); +} + +#endif \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index 6568e6db4..fc0190c2e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -22,7 +22,7 @@ #include <86Box/86box.h> #include <86Box/device.h> #include <86Box/mem.h> -#include <86box/pci.h> +#include <86Box/pci.h> #include <86Box/rom.h> // DEPENDENT!!! #include <86Box/video.h> #include <86Box/nv/vid_nv.h> @@ -32,10 +32,14 @@ It is used to get the offset within RAMHT of a graphics object. */ -uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel) +uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) { - uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel); - nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", name, channel); + // convert the name to an array of bytes + uint8_t* hash_bytes = (uint8_t*)name; + + // is this the right endianness? + uint32_t hash = (hash_bytes[0] ^ hash_bytes[1] ^ hash_bytes[2] ^ hash_bytes[3] ^ (uint8_t)channel); + nv_log("NV3: Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, name, channel); return hash; } From 3a77b631b453229f6feeb7e50087b508f2fb2766 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 22:30:46 +0000 Subject: [PATCH 076/274] Write the pullers and some graphics object skeletons. --- .../86box/nv/classes/vid_nv3_classes.h | 62 +++++++++++++- src/include/86box/nv/vid_nv3.h | 15 ++-- .../nv3/classes/nv3_class_001_beta_factor.c | 23 ++++- src/video/nv/nv3/classes/nv3_class_002_rop.c | 23 ++++- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 23 ++++- .../nv/nv3/classes/nv3_class_004_plane_mask.c | 23 ++++- .../nv3_class_005_clipping_rectangle.c | 22 ++++- .../nv/nv3/classes/nv3_class_006_pattern.c | 23 ++++- .../nv/nv3/classes/nv3_class_007_rectangle.c | 23 ++++- .../nv/nv3/classes/nv3_class_008_point.c | 23 ++++- src/video/nv/nv3/classes/nv3_class_009_line.c | 23 ++++- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 24 +++++- .../nv/nv3/classes/nv3_class_00b_triangle.c | 23 ++++- .../classes/nv3_class_00c_win95_gdi_text.c | 23 ++++- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 23 ++++- .../nv3_class_00e_scaled_image_from_mem.c | 23 ++++- src/video/nv/nv3/classes/nv3_class_010_blit.c | 23 ++++- .../nv/nv3/classes/nv3_class_011_image.c | 23 ++++- .../nv/nv3/classes/nv3_class_012_bitmap.c | 24 +++++- .../classes/nv3_class_014_transfer2memory.c | 24 +++++- .../nv3_class_015_stretched_image_from_cpu.c | 25 +++++- .../nv3_class_017_d3d5_tri_zeta_buffer.c | 23 ++++- .../classes/nv3_class_018_point_zeta_buffer.c | 23 ++++- .../classes/nv3_class_01c_image_in_memory.c | 23 ++++- src/video/nv/nv3/classes/nv3_class_names.c | 1 - .../nv/nv3/classes/nv3_class_shared_methods.c | 35 ++++++++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 85 +++++++++++++++++-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 5 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 16 ++-- 29 files changed, 683 insertions(+), 46 deletions(-) create mode 100644 src/video/nv/nv3/classes/nv3_class_shared_methods.c diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index afe3fe18d..b794e43b9 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -50,7 +50,7 @@ typedef struct nv3_class_ctx_switch_method_s uint32_t data; uint16_t instance; - uint8_t channel_id : 6; + uint8_t channel : 6; uint16_t reserved : 9; bool reset_if_volatile; // ???? } set_notify_ctx_dma; // Set notifier context for DMA (context switch) @@ -1085,5 +1085,63 @@ typedef struct nv3_object_class_01C uint8_t reserved3[0x1C3F]; } nv3_image_in_memory_t; +// See envytools. This is where we finally end up after this mess, it allows parameters to be passed to the methods. +typedef struct nv3_grobj_s +{ + uint32_t grobj_0; + uint32_t grobj_1; + uint32_t grobj_2; + uint32_t grobj_3; +} nv3_grobj_t; // TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! -#pragma pack(pop) // return packing to whatever it was before this disaster \ No newline at end of file +#pragma pack(pop) // return packing to whatever it was before this disaster + +// Class methods +void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_001_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_002_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_003_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_004_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_005_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_006_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_007_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_009_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_00c_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_00d_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_00e_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_010_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_011_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_012_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_014_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_015_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_017_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_018_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_class_01c_method(uint32_t method_id, nv3_grobj_t grobj); + +// This area is used for holding universal representations of the U* registers... +extern struct nv3_object_class_001 nv3_beta_factor; +extern struct nv3_object_class_002 nv3_rop; +extern struct nv3_object_class_003 nv3_chroma_key; +extern struct nv3_object_class_004 nv3_plane_mask; +extern struct nv3_object_class_005 nv3_clipping_rectangle; +extern struct nv3_object_class_006 nv3_pattern; +extern struct nv3_object_class_007 nv3_triangle; +extern struct nv3_object_class_008 nv3_point; +extern struct nv3_object_class_009 nv3_line; +extern struct nv3_object_class_00a nv3_lin; +extern struct nv3_object_class_00b nv3_triangle; +extern struct nv3_object_class_00c nv3_win95_gdi_text; +extern struct nv3_object_class_00d nv3_m2mf; +extern struct nv3_object_class_00e nv3_scaled_image_from_memory; +extern struct nv3_object_class_010 nv3_blit; +extern struct nv3_object_class_011 nv3_image; +extern struct nv3_object_class_012 nv3_bitmap; +extern struct nv3_object_class_014 nv3_transfer2memory; +extern struct nv3_object_class_015 nv3_stretched_image_from_cpu; +extern struct nv3_object_class_017 nv3_d3d5_tri; +extern struct nv3_object_class_018 nv3_point_zeta_buffer; +extern struct nv3_object_class_01c nv3_image_in_memory; \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 651693257..275671f4f 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -41,7 +41,7 @@ extern const device_config_t nv3_config[]; #define NV3_DMA_CHANNELS 8 #define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8 -#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough... +#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. #define NV3_LAST_VALID_GRAPHICS_OBJECT_ID 0x1F @@ -298,7 +298,7 @@ extern const device_config_t nv3_config[]; //todo: merge stuff #define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 #define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD 8 // 0=software, 1=hardware +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD 8 // 0=software, 1=hardware #define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250 #define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 @@ -792,7 +792,7 @@ typedef struct nv3_pfifo_cache_s bool access_enabled; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. - uint8_t channel_id; // The DMA channel ID of this cache. + uint8_t channel; // The DMA channel ID of this cache. uint32_t status; uint32_t puller_control; uint32_t control; @@ -821,7 +821,7 @@ typedef struct nv3_pfifo_cache_s typedef struct nv3_pfifo_cache_entry_s { - uint8_t subchannel_id : 3; + uint8_t subchannel : 3; uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin) uint32_t data; // is this the context @@ -845,7 +845,7 @@ typedef struct nv3_pfifo_s nv3_pfifo_cache_t cache0_settings; nv3_pfifo_cache_t cache1_settings; - nv3_pfifo_cache_entry_t cache0_entries[1]; + nv3_pfifo_cache_entry_t cache0_entry; // It only has 1 entry nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS @@ -1080,7 +1080,7 @@ typedef struct nv3_ramin_context_s struct { bool reserved : 1; - uint8_t channel_id : 7; + uint8_t channel : 7; bool is_rendering : 1; uint8_t class_id : 7; uint16_t ramin_offset; @@ -1238,6 +1238,9 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); / // RAMIN functions uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel); bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_id, uint32_t subchannel_id); +#ifndef RELEASE_BUILD +void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context); +#endif uint32_t nv3_ramfc_read(uint32_t address); void nv3_ramfc_write(uint32_t address, uint32_t value); diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 2f9cdb066..b6b97ee3a 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_001 beta_factor; + +void nv3_class_001_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index e3256d699..747d4b017 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_002 nv3_rop; + +void nv3_class_002_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 188f5f94e..08f854529 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_003 nv3_chroma_key; + +void nv3_class_003_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 0797819d7..0388bc35a 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_004 nv3_plane_mask; + +void nv3_class_004_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index c675be6e8..01f395040 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -13,4 +13,24 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_005 nv3_clipping_rectangle; + +void nv3_class_005_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index d75307a24..282557b95 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_006 nv3_pattern; + +void nv3_class_006_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 513f19496..3d378df91 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_007 nv3_rectangle; + +void nv3_class_007_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 92561591a..55fae702c 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_008 nv3_point; + +void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index d10501558..cd0a8b768 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_009 nv3_line; + +void nv3_class_009_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 372a56e92..4f44d4e80 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -13,4 +13,26 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_00a nv3_lin; + +void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index 1b8c23f03..4c668c275 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_00b nv3_triangle; + +void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 9c58cf250..d0116b910 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_00c nv3_win95_gdi_text; + +void nv3_class_00c_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 0b6c48cc1..a121abcde 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_00d nv3_m2mf; + +void nv3_class_00d_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index 6e90a552a..a3daae7fc 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_00e nv3_scaled_image_from_mem; + +void nv3_class_00e_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 5e6f19aff..2bcdc2234 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_010 nv3_blit; + +void nv3_class_010_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 3334b4185..9a2f73486 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_011 nv3_image; + +void nv3_class_011_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index b5c62f5f4..f2d49f6b0 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -13,4 +13,26 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_012 nv3_bitmap; + +void nv3_class_012_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index c4b97a98a..ada899cf6 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -13,4 +13,26 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_014 nv3_transfer2memory; + +void nv3_class_014_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index 951d77bce..c0a4f492f 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -6,11 +6,32 @@ * * This file is part of the 86Box distribution. * - * NV3: Methods for class 0x15 (stretched image to memory) + * NV3: Methods for class 0x15 (stretched image from cpu to memory) * * * * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_014 nv3_stretched_image_from_cpu; + +void nv3_class_015_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 4e0463104..b45ef8968 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_017 nv3_d3d5_tri; + +void nv3_class_017_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 0440c39fe..23e09904f 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; + +void nv3_class_018_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index daea3e0bb..a0e454fd4 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -13,4 +13,25 @@ * Authors: Connor Hyde, I need a better email address ;^) * * Copyright 2024-2025 Connor Hyde - */ \ No newline at end of file + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +struct nv3_object_class_01c nv3_image_in_memory; + +void nv3_class_01c_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index 3604d147b..e05ddc1eb 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -64,5 +64,4 @@ const char* nv3_class_names[] = "NV3 INVALID class 0x1D", "NV3 INVALID class 0x1E", "NV3 INVALID class 0x1F", - }; diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c new file mode 100644 index 000000000..e336168c6 --- /dev/null +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -0,0 +1,35 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3: Methods shared across multiple classes + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> + +void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj) +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index b9e7e4cdd..a83d055cf 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -152,10 +152,10 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = nv3->pfifo.cache1_settings.access_enabled; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: - ret = nv3->pfifo.cache0_settings.channel_id; + ret = nv3->pfifo.cache0_settings.channel; break; case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: - ret = nv3->pfifo.cache1_settings.channel_id; + ret = nv3->pfifo.cache1_settings.channel; break; case NV3_PFIFO_CACHE0_STATUS: uint32_t ret = 0x00; @@ -351,10 +351,10 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv3->pfifo.cache1_settings.access_enabled = value; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: - nv3->pfifo.cache0_settings.channel_id = value; + nv3->pfifo.cache0_settings.channel = value; break; case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: - nv3->pfifo.cache1_settings.channel_id = value; + nv3->pfifo.cache1_settings.channel = value; break; // CACHE0_STATUS and CACHE1_STATUS are not writable case NV3_PFIFO_CACHE0_METHOD: @@ -441,7 +441,38 @@ void nv3_pfifo_cache0_pull() if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache0_settings.get_address) return; - // There is only one entry + // There is only one entry for cache0 + uint16_t current_channel = nv3->pfifo.cache0_settings.channel; + uint32_t current_subchannel = nv3->pfifo.cache0_entry.subchannel; + uint32_t current_name = nv3->pfifo.cache0_entry.data; + uint32_t current_method = nv3->pfifo.cache0_entry.method; + + // i.e. there is no method in cache0, so we have to find the object. + if (!current_method) + { + if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) + return; // interrupt was fired, and we went to ramro + } + + uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries? + + // Tell the CPU if we found a software method + if (current_context & 0x800000) + { + nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); + } + + // Is this needed? + nv3->pfifo.cache0_settings.get_address ^= 0x04; + + #ifndef RELEASE_BUILD + nv_log("NV3: ***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE0 PULLED ****** Contextual information below\n"); + + nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); + #endif + } void nv3_pfifo_cache1_push() @@ -458,6 +489,50 @@ void nv3_pfifo_cache1_pull() // Do nothing if there is nothing in cache1 to pull if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) return; + + // There is only one entry for cache0 + uint32_t get_address = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably + + uint16_t current_channel = nv3->pfifo.cache1_settings.channel; + uint32_t current_subchannel = nv3->pfifo.cache1_entries[get_address].subchannel; + uint32_t current_name = nv3->pfifo.cache1_entries[get_address].data; + uint32_t current_method = nv3->pfifo.cache1_entries[get_address].method; + + // i.e. there is no method in cache0, so we have to find the object. + if (!current_method) + { + if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) + return; // interrupt was fired, and we went to ramro + } + + uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries? + + // Tell the CPU if we found a software method + if (current_context & 0x800000) + { + nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); + } + + // start by incrementing + uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_address) + 1; + + if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# + next_get_address &= NV3_PFIFO_CACHE1_SIZE_REV_C; + else + next_get_address &= NV3_PFIFO_CACHE1_SIZE_REV_AB; + + // Is this needed? + nv3->pfifo.cache0_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; + + #ifndef RELEASE_BUILD + nv_log("NV3: ***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE1 PULLED ****** Contextual information below\n"); + + nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); + #endif + + //Todo: finish it } bool nv3_pfifo_cache1_is_free() diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 9c44105b9..f913e2917 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -49,16 +49,19 @@ void nv3_pramdac_init() } // Polls the pixel clock. -// This updates the 2D/3D engine PGRAPH void nv3_pramdac_pixel_clock_poll(double real_time) { // TODO: ???? } // Polls the memory clock. +// This updates the 2D/3D engine PGRAPH, PTIMER and more void nv3_pramdac_memory_clock_poll(double real_time) { nv3_ptimer_tick(real_time); + + nv3_pfifo_cache0_pull(); + nv3_pfifo_cache1_pull(); // TODO: UPDATE PGRAPH! } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index d9ab438d7..3730765ab 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -347,7 +347,7 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) } // THIS IS THE MOST IMPORTANT FUNCTION! -bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_id, uint32_t subchannel_id) +bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel, uint32_t subchannel) { // TODO: WRITE IT!!! // Set the number of entries to search based on the ramht size (2*(size+1)) @@ -358,7 +358,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_i uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; uint32_t ramht_cur_address = ramht_base; - nv_log("NV3: Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel_id, subchannel_id); + nv_log("NV3: Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel, subchannel); bool found_object = false; @@ -376,7 +376,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_i // see if the object is in the right channel if (found_obj_name == name - && obj_context_struct.channel_id == channel_id) + && obj_context_struct.channel == channel) { found_object = true; break; @@ -421,8 +421,8 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_i fatal("NV3: Invalid graphics object class ID name=0x%04x type=%04x, interpreted by pgraph as: %04x (Contact starfrost)", name, obj_context_struct.class_id, obj_context_struct.class_id & 0x1F); } - else if (obj_context_struct.channel_id > NV3_DMA_CHANNELS) - fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-8", obj_context_struct.channel_id); + else if (obj_context_struct.channel > NV3_DMA_CHANNELS) + fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-8", obj_context_struct.channel); // Illegal accesses sent to RAMRO, so ignore here // TODO: SEND THESE TO RAMRO!!!!! @@ -442,9 +442,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_i bool is_software = false; if (!cache_num) - is_software = (nv3->pfifo.cache0_settings.context[subchannel_id] & 0x800000); + is_software = (nv3->pfifo.cache0_settings.context[subchannel] & 0x800000); else - is_software = (nv3->pfifo.cache1_settings.context[subchannel_id] & 0x800000); + is_software = (nv3->pfifo.cache1_settings.context[subchannel] & 0x800000); // This isn't an error but it's sent as an interrupt so the drivers can sync if (is_software) @@ -487,7 +487,7 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte nv_log("Name: 0x%04x", name); nv_log("Context:"); - nv_log("DMA Channel %d (0-7 valid)", context.channel_id); + nv_log("DMA Channel %d (0-7 valid)", context.channel); nv_log("Class ID: as repreesnted in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)", context.class_id, context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)", context.is_rendering); From 3c92d67b891a369003662fd887192bf6ba145656 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 22:37:51 +0000 Subject: [PATCH 077/274] fix compile --- src/include/86box/nv/classes/vid_nv3_classes.h | 14 +++++++------- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 2 +- src/video/nv/nv3/classes/nv3_class_00b_triangle.c | 2 +- .../nv/nv3/classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 2 +- .../classes/nv3_class_00e_scaled_image_from_mem.c | 2 +- .../nv3_class_015_stretched_image_from_cpu.c | 2 +- .../nv/nv3/classes/nv3_class_01c_image_in_memory.c | 2 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 5 +++++ 9 files changed, 19 insertions(+), 14 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index b794e43b9..04fda9dbe 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1129,14 +1129,14 @@ extern struct nv3_object_class_003 nv3_chroma_key; extern struct nv3_object_class_004 nv3_plane_mask; extern struct nv3_object_class_005 nv3_clipping_rectangle; extern struct nv3_object_class_006 nv3_pattern; -extern struct nv3_object_class_007 nv3_triangle; +extern struct nv3_object_class_007 nv3_rectangle; extern struct nv3_object_class_008 nv3_point; extern struct nv3_object_class_009 nv3_line; -extern struct nv3_object_class_00a nv3_lin; -extern struct nv3_object_class_00b nv3_triangle; -extern struct nv3_object_class_00c nv3_win95_gdi_text; -extern struct nv3_object_class_00d nv3_m2mf; -extern struct nv3_object_class_00e nv3_scaled_image_from_memory; +extern struct nv3_object_class_00A nv3_lin; +extern struct nv3_object_class_00B nv3_triangle; +extern struct nv3_object_class_00C nv3_win95_gdi_text; +extern struct nv3_object_class_00D nv3_m2mf; +extern struct nv3_object_class_00E nv3_scaled_image_from_memory; extern struct nv3_object_class_010 nv3_blit; extern struct nv3_object_class_011 nv3_image; extern struct nv3_object_class_012 nv3_bitmap; @@ -1144,4 +1144,4 @@ extern struct nv3_object_class_014 nv3_transfer2memory; extern struct nv3_object_class_015 nv3_stretched_image_from_cpu; extern struct nv3_object_class_017 nv3_d3d5_tri; extern struct nv3_object_class_018 nv3_point_zeta_buffer; -extern struct nv3_object_class_01c nv3_image_in_memory; \ No newline at end of file +extern struct nv3_object_class_01C nv3_image_in_memory; \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 4f44d4e80..f9c23dc21 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -30,7 +30,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_00a nv3_lin; +struct nv3_object_class_00A nv3_lin; void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index 4c668c275..a65b3d600 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_00b nv3_triangle; +struct nv3_object_class_00B nv3_triangle; void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index d0116b910..54c013783 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_00c nv3_win95_gdi_text; +struct nv3_object_class_00C nv3_win95_gdi_text; void nv3_class_00c_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index a121abcde..10ccb9bc3 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_00d nv3_m2mf; +struct nv3_object_class_00D nv3_m2mf; void nv3_class_00d_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index a3daae7fc..9a4e86dca 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_00e nv3_scaled_image_from_mem; +struct nv3_object_class_00E nv3_scaled_image_from_mem; void nv3_class_00e_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index c0a4f492f..24480624d 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_014 nv3_stretched_image_from_cpu; +struct nv3_object_class_015 nv3_stretched_image_from_cpu; void nv3_class_015_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index a0e454fd4..e6533627d 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -29,7 +29,7 @@ #include <86Box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_01c nv3_image_in_memory; +struct nv3_object_class_01C nv3_image_in_memory; void nv3_class_01c_method(uint32_t method_id, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index fbdf058ec..19e9f33b0 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -453,4 +453,9 @@ void nv3_pgraph_interrupt_valid(uint32_t num) void nv3_pgraph_vblank_start(svga_t* svga) { nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_EN_0_VBLANK); +} + +void nv3_pgraph_submit() +{ + } \ No newline at end of file From 7909c5e1b9d3984cea94e9d86349500ef0b32ecf Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 23:05:00 +0000 Subject: [PATCH 078/274] Add PFIFO CONFIG_0, DELAY_0, RUNOUT_GET, RUNOUT_PUT --- src/include/86box/nv/vid_nv3.h | 7 ++-- src/video/nv/nv3/nv3_core.c | 5 ++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 44 ++++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 275671f4f..2df06a68d 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -208,6 +208,7 @@ extern const device_config_t nv3_config[]; #define NV3_PBUS_END 0x1FFF #define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects) +#define NV3_PFIFO_DELAY_0 0x2040 // PFIFO Config Register #define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register #define NV3_PFIFO_CACHE0_ERROR_PENDING 0 #define NV3_PFIFO_CACHE1_ERROR_PENDING 4 @@ -832,13 +833,15 @@ typedef struct nv3_pfifo_s { uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable + uint32_t dma_delay_retry; // DMA Delay/Retry uint32_t debug_0; // Cache Debug register + uint32_t config_0; uint32_t ramht_config; // RAMHT config uint32_t ramfc_config; // RAMFC config uint32_t ramro_config; // RAMRO config // Runout stuff - uint32_t runout_put; - uint32_t runout_get; + uint32_t runout_put; // 8:3 if RAMRO=512b, otherwise 12:3 + uint32_t runout_get; // 8:3 if RAMRO=512b, otherwise 12:3 // Cache stuff uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 08a51bca7..c6944ad28 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -946,7 +946,10 @@ void nv3_update_mappings() // void* nv3_init(const device_t *info) { - nv3->nvbase.log = log_open("NV3"); + if (device_get_config_int("nv_debug_fulllog")) + nv3->nvbase.log = log_open("NV3"); + else + nv3->nvbase.log = log_open_cyclic("NV3"); // Allows nv_log to be used for multiple nvidia devices nv_log_set_device(nv3->nvbase.log); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index a83d055cf..f399b919d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -35,7 +35,9 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL}, { NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,}, + { NV3_PFIFO_DELAY_0, "PFIFO - DMA Delay/Retry Register", NULL, NULL}, { NV3_PFIFO_DEBUG_0, "PFIFO - Debug 0", NULL, NULL, }, + { NV3_PFIFO_CONFIG_0, "PFIFO - Config 0", NULL, NULL, }, { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, @@ -64,8 +66,9 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA Translation Lookaside Buffer - Pagetable Base"}, { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA Status"}, { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA Status"}, - - + //Runout + { NV3_PFIFO_RUNOUT_GET, "PFIFO Runout Get Address [8:3 if 512b, otherwise 12:3]"}, + { NV3_PFIFO_RUNOUT_PUT, "PFIFO Runout Put Address [8:3 if 512b, otherwise 12:3]"}, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -119,10 +122,15 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_INTR_EN: ret = nv3->pfifo.interrupt_enable; break; + case NV3_PFIFO_DELAY_0: + ret = nv3->pfifo.dma_delay_retry; + break; // Debug case NV3_PFIFO_DEBUG_0: ret = nv3->pfifo.debug_0; break; + case NV3_PFIFO_CONFIG_0: + ret = nv3->pfifo.config_0; // Some of these may need to become functions. case NV3_PFIFO_CONFIG_RAMFC: ret = nv3->pfifo.ramfc_config; @@ -223,7 +231,12 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE1_DMA_TLB_TAG: ret = nv3->pfifo.cache1_settings.dma_tlb_tag; break; - + case NV3_PFIFO_RUNOUT_GET: + ret = nv3->pfifo.runout_get; + break; + case NV3_PFIFO_RUNOUT_PUT: + ret = nv3->pfifo.runout_put; + break; } } @@ -284,6 +297,13 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_INTR_EN: nv3->pbus.interrupt_enable = value & 0x00001111; break; + case NV3_PFIFO_DELAY_0: + nv3->pfifo.dma_delay_retry = value; + break; + case NV3_PFIFO_CONFIG_0: + nv3->pfifo.config_0 = value; + break; + case NV3_PFIFO_CONFIG_RAMHT: nv3->pfifo.ramht_config = value; // This code sucks a bit fix it later @@ -313,7 +333,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CONFIG_RAMRO: nv3->pfifo.ramro_config = value; - uint32_t new_size_ramro = ((value >> 16) & 0x01); + uint32_t new_size_ramro = ((value >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (new_size_ramro == 0) new_size_ramro = 0x200; @@ -390,6 +410,22 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CACHE1_DMA_TLB_TAG: nv3->pfifo.cache1_settings.dma_tlb_tag = value; break; + case NV3_PFIFO_RUNOUT_GET: + uint32_t size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + + if (size == 0) //512b + nv3->pfifo.runout_get = ((value & 0x3F) << 3); + else + nv3->pfifo.runout_get = ((value & 0x3FF) << 3); + break; + case NV3_PFIFO_RUNOUT_PUT: + uint32_t size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + + if (size == 0) //512b + nv3->pfifo.runout_put = ((value & 0x3F) << 3); + else + nv3->pfifo.runout_put = ((value & 0x3FF) << 3); + break; } } } From 5ebc5f550503359e651f749c7a90a6066e73cbe8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 23:43:00 +0000 Subject: [PATCH 079/274] NV_USER and the other half of submitting (to cache1) --- src/include/86box/nv/vid_nv3.h | 10 +- src/video/CMakeLists.txt | 9 +- src/video/nv/nv3/nv3_core_arbiter.c | 2 - src/video/nv/nv3/subsystems/nv3_pfifo.c | 95 ++++++++++++++++++- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 5 + src/video/nv/nv3/subsystems/nv3_user.c | 47 +++++++++ 6 files changed, 157 insertions(+), 11 deletions(-) create mode 100644 src/video/nv/nv3/subsystems/nv3_user.c diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 2df06a68d..0b4813cd1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -254,6 +254,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_RUNOUT_GET 0x2420 #define NV3_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 +#define NV3_PFIFO_RUNOUT_RAMIN_ERR 28 + #define NV3_PFIFO_CACHE0_SIZE 1 // This is for software-injected notified only! #define NV3_PFIFO_CACHE1_SIZE_REV_AB 32 #define NV3_PFIFO_CACHE1_SIZE_REV_C 64 @@ -589,6 +591,8 @@ extern const device_config_t nv3_config[]; // easier name #define NV3_OBJECT_SUBMIT_START NV3_USER_START +#define NV3_OBJECT_SUBMIT_SUBCHANNEL 13 +#define NV3_OBJECT_SUBMIT_CHANNEL 16 #define NV3_OBJECT_SUBMIT_END NV3_USER_END // also PDFB (Debug Framebuffer?) @@ -850,12 +854,8 @@ typedef struct nv3_pfifo_s nv3_pfifo_cache_entry_t cache0_entry; // It only has 1 entry nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS - - } nv3_pfifo_t; -// create_object(uint32_t type) here - // RAMDAC typedef struct nv3_pramdac_s { @@ -1328,7 +1328,7 @@ void nv3_pfifo_interrupt(uint32_t id, bool fire_now); // NV3 PFIFO - Caches void nv3_pfifo_cache0_push(); void nv3_pfifo_cache0_pull(); -void nv3_pfifo_cache1_push(); +void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val); void nv3_pfifo_cache1_pull(); uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 2135213fb..2a90957b2 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -31,8 +31,13 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c vid_ibm_rgb528_ramdac.c vid_sdac_ramdac.c vid_ogc.c vid_mga.c vid_nga.c vid_tvp3026_ramdac.c vid_att2xc498_ramdac.c vid_xga.c vid_bochs_vbe.c + nv/nv_base.c nv/nv_rivatimer.c - nv/nv3/nv3_core.c nv/nv3/nv3_core_config.c nv/nv3/nv3_core_arbiter.c + + nv/nv3/nv3_core.c + nv/nv3/nv3_core_config.c + nv/nv3/nv3_core_arbiter.c + nv/nv3/subsystems/nv3_pramdac.c nv/nv3/subsystems/nv3_pfifo.c nv/nv3/subsystems/nv3_pgraph.c @@ -44,8 +49,10 @@ add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c nv/nv3/subsystems/nv3_ptimer.c nv/nv3/subsystems/nv3_pramin.c nv/nv3/subsystems/nv3_pramin_ramht.c nv/nv3/subsystems/nv3_pramin_ramfc.c nv/nv3/subsystems/nv3_pramin_ramro.c nv/nv3/subsystems/nv3_pvideo.c + nv/nv3/subsystems/nv3_user.c nv/nv3/classes/nv3_class_names.c + nv/nv3/classes/nv3_class_shared_methods.c nv/nv3/classes/nv3_class_001_beta_factor.c nv/nv3/classes/nv3_class_002_rop.c nv/nv3/classes/nv3_class_003_chroma_key.c diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 2022625fd..e10382feb 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -200,5 +200,3 @@ void nv3_prmcio_write(uint32_t address, uint32_t value) {}; uint32_t nv3_vram_read(uint32_t address) { return 0; }; void nv3_vram_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_user_read(uint32_t address) { return 0; }; -void nv3_user_write(uint32_t address, uint32_t value) {}; \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index f399b919d..1d9543fd9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -462,11 +462,13 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) return val; } +// Submits graphics objects INTO cache0 void nv3_pfifo_cache0_push() { - + } +// Pulls graphics objects OUT of cache0 void nv3_pfifo_cache0_pull() { // Do nothing if PFIFO CACHE0 is disabled @@ -511,11 +513,98 @@ void nv3_pfifo_cache0_pull() } -void nv3_pfifo_cache1_push() +void nv3_pfifo_context_switch(uint32_t new_channel) { - + /* Send our contexts to RAMFC. Load the new ones from RAMFC. */ } +// NV_USER writes go here! +// Pushes graphics objects into cache1 +void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) +{ + bool oh_shit = false; // RAMRO needed + nv3_ramin_ramro_reason oh_shit_reason = 0x00; // It's all good for now + + // bit 23 of a ramin dword means it's a write... + uint32_t new_address = 0; + + uint32_t method_offset = (addr & 0x1FFC); // size of dma object is 0x2000 and some universal methods are implemented at this point, like free + + // Up to 128 per envytools? + uint32_t channel = (addr >> NV3_OBJECT_SUBMIT_CHANNEL) & 0x7F; + uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & 0x07; + + // first make sure there is even any cache available + if (!nv3->pfifo.cache1_settings.access_enabled) + { + oh_shit = true; + oh_shit_reason = nv3_runout_reason_no_cache_available; + } + + // Check if runout is full + if (nv3->pfifo.runout_get != nv3->pfifo.runout_put) + { + oh_shit = true; + oh_shit_reason = nv3_runout_reason_cache_ran_out; // ? really ? I guess this means we already ran out.. + new_address |= (nv3_runout_reason_cache_ran_out << NV3_PFIFO_RUNOUT_RAMIN_ERR); + } + + if (!nv3_pfifo_cache1_is_free()) + { + oh_shit = true; + oh_shit_reason = nv3_runout_reason_free_count_overrun; + new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR); + } + + if (method_offset > 0 && method_offset <= 0x100) + { + // Reserved NVIDIA Objects + oh_shit = true; + oh_shit_reason = nv3_runout_reason_reserved_access; + new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR); + + } + + // Now check for context switching + + if (channel != nv3->pfifo.cache1_settings.channel) + { + if (!nv3->pfifo.cache_reassignment + || (nv3->pfifo.cache0_settings.get_address != nv3->pfifo.cache0_settings.get_address)) + { + oh_shit = true; + oh_shit_reason = nv3_runout_reason_no_cache_available; + new_address |= (nv3_runout_reason_no_cache_available << NV3_PFIFO_RUNOUT_RAMIN_ERR); + } + } + + // Did we fuck up? + if (oh_shit) + { + nv_log("NV3: WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset); + return; + } + + // We didn't. Let's put it in CACHE1 + uint32_t current_put_address = nv3->pfifo.cache1_settings.put_address >> 2; + nv3->pfifo.cache1_entries[current_put_address].subchannel = subchannel; + nv3->pfifo.cache1_entries[current_put_address].method = method_offset; + nv3->pfifo.cache1_entries[current_put_address].data = val; + + // now we have to recalculate the cache1 put address + uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address); + + if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# + next_put_address &= NV3_PFIFO_CACHE1_SIZE_REV_C; + else + next_put_address &= NV3_PFIFO_CACHE1_SIZE_REV_AB; + + nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address); + + // Now we're done. Phew! +} + +// Pulls graphics objects OUT of cache1 void nv3_pfifo_cache1_pull() { // Do nothing if PFIFO CACHE1 is disabled diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index b7d8f4f57..a206343c9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -36,4 +36,9 @@ uint32_t nv3_ramro_read(uint32_t address) void nv3_ramro_write(uint32_t address, uint32_t value) { nv_log("NV3: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)\n", value, address); +} + +void nv3_ramro_send() +{ + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c new file mode 100644 index 000000000..eee994208 --- /dev/null +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -0,0 +1,47 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 User Submission Area (NV_USER, conceptually considered "Cache1 Pusher") + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ + +#include +#include +#include +#include +#include <86Box/86box.h> +#include <86Box/device.h> +#include <86Box/mem.h> +#include <86box/pci.h> +#include <86Box/rom.h> // DEPENDENT!!! +#include <86Box/video.h> +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv3.h> + +// 128 channels conceptually supported - a hangover from nv1 where multiple windows all directly programming the gpu were supported? total lunacy. +uint32_t nv3_user_read(uint32_t address) +{ + uint8_t method_offset = (address & 0x1FFC); + + nv_log("NV3: User Submission Area method_offset=0x%04x OH SHIT!! NOT IMPLEMENTED!!!", method_offset); + + // 0x10 is free CACHE1 object, other stuff? + return 0x00; +}; + +// Although NV3 doesn't have DMA mode unlike NV4 and later, it's conceptually similar to a "pusher" that pushes graphics commands that you write into CACHE1 that are then pulled out. +// So we send the writes here. This might do other stuff, so we keep this function +void nv3_user_write(uint32_t address, uint32_t value) +{ + nv3_pfifo_cache1_push(address, value); +} \ No newline at end of file From 1f1b88a119cc3e8352b074c1a5931839badf85ad Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 23:43:52 +0000 Subject: [PATCH 080/274] Whoops, fix the compile --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 1d9543fd9..138f5f4bd 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -411,17 +411,17 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv3->pfifo.cache1_settings.dma_tlb_tag = value; break; case NV3_PFIFO_RUNOUT_GET: - uint32_t size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + uint32_t size_get = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - if (size == 0) //512b + if (size_get == 0) //512b nv3->pfifo.runout_get = ((value & 0x3F) << 3); else nv3->pfifo.runout_get = ((value & 0x3FF) << 3); break; case NV3_PFIFO_RUNOUT_PUT: - uint32_t size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + uint32_t size_put = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - if (size == 0) //512b + if (size_put == 0) //512b nv3->pfifo.runout_put = ((value & 0x3F) << 3); else nv3->pfifo.runout_put = ((value & 0x3FF) << 3); From 782a4a058b5c708add64ef76c1b5a9e83ff5aaa7 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 23:44:21 +0000 Subject: [PATCH 081/274] actually call the context switch function even if it doesn't exist yet --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 138f5f4bd..1508bc092 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -576,6 +576,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) oh_shit_reason = nv3_runout_reason_no_cache_available; new_address |= (nv3_runout_reason_no_cache_available << NV3_PFIFO_RUNOUT_RAMIN_ERR); } + + nv3_pfifo_context_switch(channel); } // Did we fuck up? From 4e001ae17167b671138024bb3ee1407d21850e12 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 1 Feb 2025 23:44:39 +0000 Subject: [PATCH 082/274] indicate the right error --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 1508bc092..6c98cf85f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -561,7 +561,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) // Reserved NVIDIA Objects oh_shit = true; oh_shit_reason = nv3_runout_reason_reserved_access; - new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR); + new_address |= (nv3_runout_reason_reserved_access << NV3_PFIFO_RUNOUT_RAMIN_ERR); } From f5687370831c83ae6bd8aac05c8e79102a2dff35 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 2 Feb 2025 00:43:27 +0000 Subject: [PATCH 083/274] various logging/pfifo fixes, add pfifo ctx --- .../nv3_object_classes_driver.txt | 57 ------------------- src/include/86box/nv/vid_nv3.h | 16 ++++-- src/video/nv/nv3/subsystems/nv3_pbus.c | 2 +- src/video/nv/nv3/subsystems/nv3_pextdev.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfb.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 49 +++++++++++++--- src/video/nv/nv3/subsystems/nv3_pgraph.c | 6 +- src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- src/video/nv/nv3/subsystems/nv3_pme.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 2 +- src/video/nv/nv3/subsystems/nv3_ptimer.c | 9 +-- src/video/nv/nv3/subsystems/nv3_pvideo.c | 2 +- 12 files changed, 66 insertions(+), 85 deletions(-) delete mode 100644 doc/nvidia_notes/nv3_object_classes_driver.txt diff --git a/doc/nvidia_notes/nv3_object_classes_driver.txt b/doc/nvidia_notes/nv3_object_classes_driver.txt deleted file mode 100644 index 3e4955a80..000000000 --- a/doc/nvidia_notes/nv3_object_classes_driver.txt +++ /dev/null @@ -1,57 +0,0 @@ -Object classes - -NOT represented by the GPU. These are the ones the drivers recognise. Most of them are faked. - -Version 0.77_win95 (!!!) - -object class 1 = "general" methods shared across all objects -object class 2 = DMA from memory -object class 3 = DMA to memory -object class 4 = timer -object class 5 = chip ID -object class 6 = "context ordinal" -object class 10/0Ah = patchcord (links objects together) -object class 11/0Bh = video sink -object class 12/0Ch = video switch -object class 13/0Dh = video colormap -object class 14/0Eh = patchcord...again -object class 15/0Fh = image to video -object class 16/10h = image stencil buffer -object class 17/11h = image blending methods -object class 18/12h = beta solid -object class 19/13h = image -> render operation -object class 20/14h = ROP5 (2^5 = 32bit rop) -object class 21/15h = color key -object class 22/16h = plane switch -object class 23/17h = "solid image" -object class 24/18h = pattern -object class 25/19h = black rectangle -object class 26/1Ah = solid point -object class 27/1Bh = solid line -object class 28/1Ch = solid lin (line without its ending or starting pixel) -object class 29/1Dh = triangle -object class 30/1Eh = solid rectangle -object class 31/1Fh = blit image -object class 33/21h = get image from cpu -object class 34/22h = get image from cpu, monochrome -object class 37/25h = get image from local GPU memory -object class 49/31h and 51/33h = patchcord, again -object class 54/36h = get image from cpu, stretched -object class 55/37h = get image from vram, scaled -object class 56/38h = get image from vram, scaled, YUV 420 color space (probably internal colour space used for rendering) -object class 57/39h = convert image(?) between formats in place in vram, allows you to set an in and out buffer and all that jazz -object class 61/3Dh = In-Memory DMA (vram to vram?) -object class 62/3Eh = get image from vram -object class 63/3Fh = get video from vram -object class 64/40h = video scaler -object class 65/41h = video color key (as opposed to image) -object class 66/42h = capture video to memory -object class 67/43h = Solid ROP5 -object class 68/44h = zeta buffer (combined z and stencil buffer) from CPU(?) -object class 69/45h = zeta buffer in VRAM -object class 70/46h = zeta buffer patchcord -object class 71/47h = render solid point into zeta buffer (Also rectangle0 -object class 72/48h = render Direct3D 5.x ("D3D0") accelerated triangle into zeta buffer -object class 73/49h = render Direct3D 5.x ("D3D0") accelerated triangle -object class 74/4Ah = video source -object class 75/4Bh = render Windows GDI accelerated rectangle and text \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 0b4813cd1..a00699a62 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 30 January 2025 (STILL WORKING ON IT!!!) + * Last updated: 2 February 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -272,11 +272,14 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 #define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 #define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD 8 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD 8 #define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY 0x3050 #define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY_BOOL 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 #define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit +// Current channel context - cache1 +#define NV3_PFIFO_CACHE0_CTX 0x3080 + #define NV3_PFIFO_CACHE0_METHOD 0x3100 #define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 @@ -306,6 +309,11 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 #define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 + +// Current channel context - cache1 +#define NV3_PFIFO_CACHE1_CTX_START 0x3280 +#define NV3_PFIFO_CACHE1_CTX_END 0x32F0 + #define NV3_PFIFO_CACHE1_METHOD 0x3300 #define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13 @@ -797,11 +805,11 @@ typedef struct nv3_pfifo_cache_s bool access_enabled; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. - uint8_t channel; // The DMA channel ID of this cache. + uint8_t channel; // The DMA channel ID of this cache. uint32_t status; uint32_t puller_control; uint32_t control; - uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; + uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; // Only one of these exists for cache0 /* cache1 only do we even need to emulate this? diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 61385b8f2..ffe2c57cf 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -75,7 +75,7 @@ uint32_t nv3_pbus_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 2fbbd3489..3e0d63b5e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -113,7 +113,7 @@ uint32_t nv3_pextdev_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 4de4d5069..510c61e6a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -90,7 +90,7 @@ uint32_t nv3_pfb_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 6c98cf85f..1e52175c5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -41,6 +41,7 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, + { NV3_PFIFO_CACHE_REASSIGNMENT, "PFIFO - Allow Cache Channel Reassignment", NULL, NULL }, { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller Control", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller Control"}, { NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, @@ -231,21 +232,34 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE1_DMA_TLB_TAG: ret = nv3->pfifo.cache1_settings.dma_tlb_tag; break; + // Runout case NV3_PFIFO_RUNOUT_GET: ret = nv3->pfifo.runout_get; break; case NV3_PFIFO_RUNOUT_PUT: ret = nv3->pfifo.runout_put; break; + /* Cache1 is handled below */ + case NV3_PFIFO_CACHE0_CTX: + ret = nv3->pfifo.cache0_settings.context[0]; + break; } } if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } + /* Handle some special memory areas */ + else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) + { + uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; + ret = nv3->pfifo.cache1_settings.context[ctx_entry_id]; + + nv_log("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x", ctx_entry_id, ret); + } else { nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); @@ -267,16 +281,11 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - nv_log("NV3: PFIFO Write 0x%08x -> 0x%08x\n", value, address); + nv_log("NV3: PFIFO Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); - // on-read function if (reg->on_write) reg->on_write(value); @@ -293,9 +302,15 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_INTR: nv3->pfifo.interrupt_status &= ~value; nv3_pmc_clear_interrupts(); + + // update the internal cache error state + if (!nv3->pfifo.interrupt_status & NV3_PFIFO_INTR_CACHE_ERROR) + nv3->pfifo.debug_0 &= ~NV3_PFIFO_INTR_CACHE_ERROR; + break; case NV3_PFIFO_INTR_EN: - nv3->pbus.interrupt_enable = value & 0x00001111; + nv3->pfifo.interrupt_enable = value & 0x00001111; + nv3_pmc_handle_interrupts(true); break; case NV3_PFIFO_DELAY_0: nv3->pfifo.dma_delay_retry = value; @@ -426,10 +441,26 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) else nv3->pfifo.runout_put = ((value & 0x3FF) << 3); break; + /* Cache1 is handled below */ + case NV3_PFIFO_CACHE0_CTX: + nv3->pfifo.cache0_settings.context[0] = value; + break; } } - } + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + } + /* Handle some special memory areas */ + else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) + { + uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; + nv3->pfifo.cache1_settings.context[ctx_entry_id] = value; + + nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x", ctx_entry_id, value); + } } /* diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 19e9f33b0..8782abd8a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -140,9 +140,11 @@ uint32_t nv3_pgraph_read(uint32_t address) break; case NV3_PGRAPH_INTR_EN_0: ret = nv3->pgraph.interrupt_enable_0; + nv3_pmc_handle_interrupts(true); break; case NV3_PGRAPH_INTR_EN_1: ret = nv3->pgraph.interrupt_enable_1; + nv3_pmc_handle_interrupts(true); break; // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like // during the driver initialisation process @@ -243,7 +245,7 @@ uint32_t nv3_pgraph_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } @@ -457,5 +459,5 @@ void nv3_pgraph_vblank_start(svga_t* svga) void nv3_pgraph_submit() { - + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 7313a7554..4d8ef7c4f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -211,7 +211,7 @@ uint32_t nv3_pmc_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index 2ba4af426..d059eb05f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -77,7 +77,7 @@ uint32_t nv3_pme_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index f913e2917..c87a7e14e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -285,7 +285,7 @@ uint32_t nv3_pramdac_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 938389054..30dd96f23 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -76,14 +76,11 @@ void nv3_ptimer_tick(double real_time) double current_time = freq_base * ((double)nv3->ptimer.clock_numerator * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)nv3->ptimer.clock_denominator; // *10.0? - // Logging is suppressed when reading this register because it is read many times - // So we only log when we update. - // truncate it nv3->ptimer.time += (uint64_t)current_time; - - nv_log("PTIMER time ticked (The value is now 0x%08x)\n", nv3->ptimer.time); + // Only log on ptimer alarm. Otherwise, it's too much spam. + //nv_log("PTIMER time ticked (The value is now 0x%08x)\n", nv3->ptimer.time); // Check if the alarm has actually triggered... if (nv3->ptimer.time >= nv3->ptimer.alarm) @@ -153,7 +150,7 @@ uint32_t nv3_ptimer_read(uint32_t address) && reg->address != NV3_PTIMER_TIME_1_NSEC) { if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index dc8651fb8..dacf984c9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -82,7 +82,7 @@ uint32_t nv3_pvideo_read(uint32_t address) } if (reg->friendly_name) - nv_log(": %s (value = 0x%08x)\n", reg->friendly_name, ret); + nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); else nv_log("\n"); } From 908ae99cd8551b971641838b4e9abc228231d21e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 2 Feb 2025 01:39:17 +0000 Subject: [PATCH 084/274] fix puller_control --- src/include/86box/nv/vid_nv3.h | 1 - src/video/nv/nv3/subsystems/nv3_pfifo.c | 9 ++++----- src/video/nv/nv3/subsystems/nv3_pgraph.c | 5 ++++- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index a00699a62..3d4bd9b0a 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -808,7 +808,6 @@ typedef struct nv3_pfifo_cache_s uint8_t channel; // The DMA channel ID of this cache. uint32_t status; uint32_t puller_control; - uint32_t control; uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; // Only one of these exists for cache0 /* cache1 only diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 1e52175c5..b788f0e94 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -143,10 +143,10 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = nv3->pfifo.ramro_config; break; case NV3_PFIFO_CACHE0_PULLER_CONTROL: - ret = nv3->pfifo.cache0_settings.control; + ret = nv3->pfifo.cache0_settings.puller_control; break; case NV3_PFIFO_CACHE1_PULLER_CONTROL: - ret = nv3->pfifo.cache1_settings.control; + ret = nv3->pfifo.cache1_settings.puller_control; break; case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: ret = nv3->pfifo.cache0_settings.context_is_dirty; @@ -368,10 +368,10 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) break; // Control case NV3_PFIFO_CACHE0_PULLER_CONTROL: - nv3->pfifo.cache0_settings.control = value; // 8bits meaningful + nv3->pfifo.cache0_settings.puller_control = value; // 8bits meaningful break; case NV3_PFIFO_CACHE1_PULLER_CONTROL: - nv3->pfifo.cache1_settings.control = value; // 8bits meaningful + nv3->pfifo.cache1_settings.puller_control = value; // 8bits meaningful break; case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: nv3->pfifo.cache0_settings.context_is_dirty = value; @@ -648,7 +648,6 @@ void nv3_pfifo_cache1_pull() if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) return; - // There is only one entry for cache0 uint32_t get_address = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably uint16_t current_channel = nv3->pfifo.cache1_settings.channel; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 8782abd8a..7d294d820 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -134,9 +134,11 @@ uint32_t nv3_pgraph_read(uint32_t address) //interrupt status and enable regs case NV3_PGRAPH_INTR_0: ret = nv3->pgraph.interrupt_status_0; + nv3_pmc_clear_interrupts(); break; case NV3_PGRAPH_INTR_1: ret = nv3->pgraph.interrupt_status_1; + nv3_pmc_clear_interrupts(); break; case NV3_PGRAPH_INTR_EN_0: ret = nv3->pgraph.interrupt_enable_0; @@ -323,7 +325,8 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // Only bits divisible by 4 matter // and only bit0-16 is defined in intr_1 case NV3_PGRAPH_INTR_EN_0: - nv3->pgraph.interrupt_enable_0 = value & 0x11111111; + value |= (1 << NV3_PGRAPH_INTR_EN_0_VBLANK); + nv3->pgraph.interrupt_enable_0 = value & 0x11111111; nv3_pmc_handle_interrupts(true); break; case NV3_PGRAPH_INTR_EN_1: From aa8a5a6d0e90d751cd305812cde3d554252b3de0 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 5 Feb 2025 01:28:06 +0000 Subject: [PATCH 085/274] IT ATTEMPTS TO RENDER THE DESKTOP HOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOLY SHIT IT ONLY TOOK ME 6 MONTHS --- .../nv3 driver status_CURRENT.txt | 4 ++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 44 +++++++++++++++---- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 - 3 files changed, 39 insertions(+), 11 deletions(-) create mode 100644 doc/nvidia_notes/nv3 driver status_CURRENT.txt diff --git a/doc/nvidia_notes/nv3 driver status_CURRENT.txt b/doc/nvidia_notes/nv3 driver status_CURRENT.txt new file mode 100644 index 000000000..f284f7457 --- /dev/null +++ b/doc/nvidia_notes/nv3 driver status_CURRENT.txt @@ -0,0 +1,4 @@ +Failure condition: + Failed check, causes fifoService call in fifo service init in RM, FifoState STATE_LOAD + + CHECK NVSTARTIO! DEBUG TOMORROW \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index b788f0e94..17d1f464b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -70,6 +70,7 @@ nv_register_t pfifo_registers[] = { //Runout { NV3_PFIFO_RUNOUT_GET, "PFIFO Runout Get Address [8:3 if 512b, otherwise 12:3]"}, { NV3_PFIFO_RUNOUT_PUT, "PFIFO Runout Put Address [8:3 if 512b, otherwise 12:3]"}, + { NV3_PFIFO_RUNOUT_STATUS, "PFIFO Runout Status"}, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -132,6 +133,7 @@ uint32_t nv3_pfifo_read(uint32_t address) break; case NV3_PFIFO_CONFIG_0: ret = nv3->pfifo.config_0; + break; // Some of these may need to become functions. case NV3_PFIFO_CONFIG_RAMFC: ret = nv3->pfifo.ramfc_config; @@ -166,9 +168,7 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: ret = nv3->pfifo.cache1_settings.channel; break; - case NV3_PFIFO_CACHE0_STATUS: - uint32_t ret = 0x00; - + case NV3_PFIFO_CACHE0_STATUS: // CACHE0 has only one entry so it can only ever be empty or full if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache1_settings.get_address) @@ -178,6 +178,8 @@ uint32_t nv3_pfifo_read(uint32_t address) break; case NV3_PFIFO_CACHE1_STATUS: + // CACHE1 doesn't... + if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) ret |= 1 << NV3_PFIFO_CACHE1_STATUS_EMPTY; @@ -186,10 +188,9 @@ uint32_t nv3_pfifo_read(uint32_t address) if (!nv3_pfifo_cache1_is_free()) ret |= 1 << NV3_PFIFO_CACHE1_STATUS_FULL; - if (nv3->pfifo.runout_put == nv3->pfifo.runout_get) + if (nv3->pfifo.runout_put != nv3->pfifo.runout_get) ret |= 1 << NV3_PFIFO_CACHE1_STATUS_RANOUT; - ret = nv3->pfifo.cache1_settings.status; break; case NV3_PFIFO_CACHE0_METHOD: ret = ((nv3->pfifo.cache0_settings.method_subchannel << 13) & 0x07) @@ -212,7 +213,7 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = nv3->pfifo.cache1_settings.dma_state; break; case NV3_PFIFO_CACHE1_DMA_CONFIG_1: - ret = nv3->pfifo.cache1_settings.dma_length; + ret = nv3->pfifo.cache1_settings.dma_length & (VRAM_SIZE_8MB) - 4; //MAX vram size break; case NV3_PFIFO_CACHE1_DMA_CONFIG_2: ret = nv3->pfifo.cache1_settings.dma_address; @@ -239,6 +240,27 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_RUNOUT_PUT: ret = nv3->pfifo.runout_put; break; + case NV3_PFIFO_RUNOUT_STATUS: + if (nv3->pfifo.runout_put == nv3->pfifo.runout_get) + ret |= 1 << NV3_PFIFO_RUNOUT_STATUS_EMPTY; /* good news */ + else + ret |= 1 << NV3_PFIFO_RUNOUT_STATUS_RANOUT; /* bad news */ + + /* TODO: the following code sucks (move to a functio?) */ + + uint32_t new_size_ramro = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + + if (new_size_ramro == 0) + new_size_ramro = 0x200; + else if (new_size_ramro == 1) + new_size_ramro = 0x2000; + + // WTF? + if (nv3->pfifo.runout_put + 0x08 & (new_size_ramro - 0x08) == nv3->pfifo.runout_get) + ret |= 1 << NV3_PFIFO_RUNOUT_STATUS_FULL; /* VERY BAD news */ + + break; + /* Cache1 is handled below */ case NV3_PFIFO_CACHE0_CTX: ret = nv3->pfifo.cache0_settings.context[0]; @@ -306,10 +328,9 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) // update the internal cache error state if (!nv3->pfifo.interrupt_status & NV3_PFIFO_INTR_CACHE_ERROR) nv3->pfifo.debug_0 &= ~NV3_PFIFO_INTR_CACHE_ERROR; - break; case NV3_PFIFO_INTR_EN: - nv3->pfifo.interrupt_enable = value & 0x00001111; + nv3->pfifo.interrupt_enable = value & 0x00011111; nv3_pmc_handle_interrupts(true); break; case NV3_PFIFO_DELAY_0: @@ -395,7 +416,6 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CACHE0_METHOD: nv3->pfifo.cache0_settings.method_subchannel = (value >> 13) & 0x07; nv3->pfifo.cache0_settings.method_address = (value >> 2) & 0x7FF; - break; case NV3_PFIFO_CACHE1_METHOD: nv3->pfifo.cache1_settings.method_subchannel = (value >> 13) & 0x07; @@ -547,6 +567,11 @@ void nv3_pfifo_cache0_pull() void nv3_pfifo_context_switch(uint32_t new_channel) { /* Send our contexts to RAMFC. Load the new ones from RAMFC. */ + if (new_channel >= NV3_DMA_CHANNELS) + fatal("Tried to switch to invalid dma channel"); + + uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF; + } // NV_USER writes go here! @@ -600,6 +625,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) if (channel != nv3->pfifo.cache1_settings.channel) { + // Cache reassignment required if (!nv3->pfifo.cache_reassignment || (nv3->pfifo.cache0_settings.get_address != nv3->pfifo.cache0_settings.get_address)) { diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 7d294d820..9835a788d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -325,14 +325,12 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // Only bits divisible by 4 matter // and only bit0-16 is defined in intr_1 case NV3_PGRAPH_INTR_EN_0: - value |= (1 << NV3_PGRAPH_INTR_EN_0_VBLANK); nv3->pgraph.interrupt_enable_0 = value & 0x11111111; nv3_pmc_handle_interrupts(true); break; case NV3_PGRAPH_INTR_EN_1: nv3->pgraph.interrupt_enable_1 = value & 0x00011111; nv3_pmc_handle_interrupts(true); - break; // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like // during the driver initialisation process From acd0dc40bb1e6b68fa270dd49bbcdfe93ff2693e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 5 Feb 2025 18:46:38 +0000 Subject: [PATCH 086/274] Implement pixel mask registers. --- src/include/86box/nv/vid_nv3.h | 2 ++ src/video/nv/nv3/nv3_core.c | 3 ++- src/video/nv/nv3/subsystems/nv3_pfb.c | 5 +++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 3d4bd9b0a..5bc967911 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -593,6 +593,8 @@ extern const device_config_t nv3_config[]; #define NV3_PRAMDAC_END 0x680FFF #define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC +#define NV3_VGA_DAC_START 0x6813C6 +#define NV3_VGA_DAC_END 0x6813C9 #define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?) #define NV3_USER_END 0xFFFFFF diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index c6944ad28..c185af738 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -46,7 +46,8 @@ bool nv3_is_svga_redirect_address(uint32_t addr) || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_MONO - || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO); + || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO + || (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END)); } // All MMIO regs are 32-bit i believe internally diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 510c61e6a..ba42c1734 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -144,10 +144,15 @@ void nv3_pfb_config0_write(uint32_t val) // so we don't update things here for now uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; + // i don't think 16:9 is supported + uint32_t new_pfb_vtotal = new_pfb_htotal * (4/3); + uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; nv_log("NV3: Framebuffer Config Change\n"); nv_log("NV3: Horizontal Size=%d pixels\n", new_pfb_htotal); + nv_log("NV3: Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); + if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) nv_log("NV3: Bit Depth=8bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP) From f3c90b3ef2baf12b95cde32771ba99d3b431308b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 5 Feb 2025 20:01:21 +0000 Subject: [PATCH 087/274] Fix PTIMER speed, which fixes 1 minute of being frozen on the win2k bootscreen --- src/video/nv/nv3/subsystems/nv3_ptimer.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 30dd96f23..b182644ec 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -59,22 +59,21 @@ void nv3_ptimer_interrupt(uint32_t num) // Ticks the timer. void nv3_ptimer_tick(double real_time) { - // do not divide by zero + // prevent a divide by zero if (nv3->ptimer.clock_numerator == 0 || nv3->ptimer.clock_denominator == 0) return; // get the current time - // Due to timer system limitations, the timer system is not capable of running at 100 megahertz. Therefore, we have to scale it down and then scale up the level of changes - // to the state. // See Envytools. We need to use the frequency as a source. - // But we need to figure out how many cycles actually occurred because this counts up every cycle... + // We need to figure out how many cycles actually occurred because this counts up every cycle... + // However it seems that their formula is wrong. I can't be bothered to figure out what's going on and, based on documentation from NVIDIA, + // timer_0 is meant to roll over every 4 seconds. Multiplying by 10 basically does the job. // Convert to microseconds - double freq_base = (real_time / 1000000.0f) / ((double)1.0 / nv3->nvbase.memory_clock_frequency); - - double current_time = freq_base * ((double)nv3->ptimer.clock_numerator * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)nv3->ptimer.clock_denominator; // *10.0? + double freq_base = (real_time / 1000000.0f) / ((double)1.0 / nv3->nvbase.memory_clock_frequency) * 10.0f; + double current_time = freq_base * ((double)nv3->ptimer.clock_numerator) / (double)nv3->ptimer.clock_denominator; // *10.0? // truncate it nv3->ptimer.time += (uint64_t)current_time; From d5393a0575a1792410fc15f8828332eec7d3a037 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 5 Feb 2025 21:40:41 +0000 Subject: [PATCH 088/274] Now that the log is device specific, let's not log it twice. --- .../86box/nv/classes/vid_nv3_classes.h | 3 ++ src/include/86box/nv/vid_nv3.h | 2 +- src/video/nv/nv3/nv3_core.c | 54 +++++++++---------- src/video/nv/nv3/nv3_core_arbiter.c | 4 +- src/video/nv/nv3/subsystems/nv3_pbus.c | 10 ++-- src/video/nv/nv3/subsystems/nv3_pextdev.c | 16 +++--- src/video/nv/nv3/subsystems/nv3_pfb.c | 18 +++---- src/video/nv/nv3/subsystems/nv3_pfifo.c | 22 ++++---- src/video/nv/nv3/subsystems/nv3_pgraph.c | 14 ++--- src/video/nv/nv3/subsystems/nv3_pmc.c | 18 +++---- src/video/nv/nv3/subsystems/nv3_pme.c | 6 +-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 12 ++--- src/video/nv/nv3/subsystems/nv3_pramin.c | 16 +++--- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 4 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 6 +-- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 4 +- src/video/nv/nv3/subsystems/nv3_ptimer.c | 6 +-- src/video/nv/nv3/subsystems/nv3_pvideo.c | 4 +- src/video/nv/nv3/subsystems/nv3_user.c | 15 +++++- 19 files changed, 124 insertions(+), 110 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 04fda9dbe..36bac6e66 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1096,6 +1096,9 @@ typedef struct nv3_grobj_s // TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! #pragma pack(pop) // return packing to whatever it was before this disaster +// Method IDs +#define NV3_GENERIC_METHOD_IS_PFIFO_FREE 0x0010 + // Class methods void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_001_method(uint32_t method_id, nv3_grobj_t grobj); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 5bc967911..7602361fc 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 2 February 2025 (STILL WORKING ON IT!!!) + * Last updated: 5 February 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index c185af738..ff844c02d 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -68,7 +68,7 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3); - nv_log("NV3: Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x\n", addr, ret); + nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x\n", addr, ret); return ret; } @@ -94,7 +94,7 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); - nv_log("NV3: Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + nv_log("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); return ret; } @@ -121,7 +121,7 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - nv_log("NV3: Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x\n", addr, ret); + nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x\n", addr, ret); return ret; } @@ -142,7 +142,7 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("NV3: Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + nv_log("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); return; @@ -168,7 +168,7 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("NV3: Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x\n", addr, val); + nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -195,7 +195,7 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("NV3: Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x\n", addr, val); + nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -360,7 +360,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) } - nv_log("NV3: nv3_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret); + nv_log("nv3_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret); return ret; } @@ -377,7 +377,7 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) && addr >= NV3_PCI_CFG_BAR1_L && addr <= NV3_PCI_CFG_BAR1_BYTE2) return; - nv_log("NV3: nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); + nv_log("nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); nv3->pci_config.pci_regs[addr] = val; @@ -746,13 +746,13 @@ uint8_t nv3_prom_read(uint32_t address) // Does this mirror on real hardware? if (rom_address >= real_rom_size) { - nv_log("NV3: PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); + nv_log("PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); return 0xFF; } else { uint8_t val = nv3->nvbase.vbios.rom[rom_address]; - nv_log("NV3: PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); + nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); return val; } } @@ -760,13 +760,13 @@ uint8_t nv3_prom_read(uint32_t address) void nv3_prom_write(uint32_t address, uint32_t value) { uint32_t real_addr = address & 0x1FFFF; - nv_log("NV3: What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value); + nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value); } // Initialise the MMIO mappings void nv3_init_mappings_mmio() { - nv_log("NV3: Initialising 32MB MMIO area\n"); + nv_log("Initialising 32MB MMIO area\n"); // 0x0 - 1000000: regs // 0x1000000-2000000 @@ -806,7 +806,7 @@ void nv3_init_mappings_mmio() void nv3_init_mappings_svga() { - nv_log("NV3: Initialising SVGA core memory mapping\n"); + nv_log("Initialising SVGA core memory mapping\n"); // setup the svga mappings mem_mapping_set(&nv3->nvbase.framebuffer_mapping, 0, 0, @@ -873,7 +873,7 @@ void nv3_update_mappings() if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM) { - nv_log("NV3: The memory was turned off, not much is going to happen.\n"); + nv_log("The memory was turned off, not much is going to happen.\n"); return; } @@ -885,7 +885,7 @@ void nv3_update_mappings() // first map bar0 - nv_log("NV3: BAR0 (MMIO Base) = 0x%08x\n", nv3->nvbase.bar0_mmio_base); + nv_log("BAR0 (MMIO Base) = 0x%08x\n", nv3->nvbase.bar0_mmio_base); //mem_mapping_enable(&nv3->nvbase.mmio_mapping); // should have no effect if already enabled @@ -894,7 +894,7 @@ void nv3_update_mappings() // if this breaks anything, remove it // skeptical that 0 is used to disable... - nv_log("NV3: BAR1 (Linear Framebuffer / NV_USER Base & RAMIN) = 0x%08x\n", nv3->nvbase.bar1_lfb_base); + nv_log("BAR1 (Linear Framebuffer / NV_USER Base & RAMIN) = 0x%08x\n", nv3->nvbase.bar1_lfb_base); // this is likely mirrored // 4x on 2mb cards @@ -920,22 +920,22 @@ void nv3_update_mappings() switch (nv3->nvbase.svga.gdcreg[0x06] & 0x0c) { case NV3_CRTC_BANKED_128K_A0000: - nv_log("NV3: SVGA Banked Mode = 128K @ A0000h\n"); + nv_log("SVGA Banked Mode = 128K @ A0000h\n"); mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000 nv3->nvbase.svga.banked_mask = 0x1FFFF; break; case NV3_CRTC_BANKED_64K_A0000: - nv_log("NV3: SVGA Banked Mode = 64K @ A0000h\n"); + nv_log("SVGA Banked Mode = 64K @ A0000h\n"); mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000 nv3->nvbase.svga.banked_mask = 0xFFFF; break; case NV3_CRTC_BANKED_32K_B0000: - nv_log("NV3: SVGA Banked Mode = 32K @ B0000h\n"); + nv_log("SVGA Banked Mode = 32K @ B0000h\n"); mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000 nv3->nvbase.svga.banked_mask = 0x7FFF; break; case NV3_CRTC_BANKED_32K_B8000: - nv_log("NV3: SVGA Banked Mode = 32K @ B8000h\n"); + nv_log("SVGA Banked Mode = 32K @ B8000h\n"); mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000 nv3->nvbase.svga.banked_mask = 0x7FFF; break; @@ -954,7 +954,7 @@ void* nv3_init(const device_t *info) // Allows nv_log to be used for multiple nvidia devices nv_log_set_device(nv3->nvbase.log); - nv_log("NV3: initialising core\n"); + nv_log("initialising core\n"); // Figure out which vbios the user selected const char* vbios_id = device_get_config_bios("vbios"); @@ -975,7 +975,7 @@ void* nv3_init(const device_t *info) return NULL; } else - nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); + nv_log("Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); // set the vram amount and gpu revision uint32_t vram_amount = device_get_config_int("vram_size"); @@ -984,7 +984,7 @@ void* nv3_init(const device_t *info) // set up the bus and start setting up SVGA core if (nv3->nvbase.bus_generation == nv_bus_pci) { - nv_log("NV3: using PCI bus\n"); + nv_log("using PCI bus\n"); pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); @@ -993,7 +993,7 @@ void* nv3_init(const device_t *info) } else if (nv3->nvbase.bus_generation == nv_bus_agp_1x) { - nv_log("NV3: using AGP 1X bus\n"); + nv_log("using AGP 1X bus\n"); pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); @@ -1002,7 +1002,7 @@ void* nv3_init(const device_t *info) } // set vram - nv_log("NV3: VRAM=%d bytes\n", nv3->nvbase.svga.vram_max); + nv_log("VRAM=%d bytes\n", nv3->nvbase.svga.vram_max); // init memory mappings nv3_init_mappings(); @@ -1012,7 +1012,7 @@ void* nv3_init(const device_t *info) nv3->pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM; // svga is done, so now initialise the real gpu - nv_log("NV3: Initialising GPU core...\n"); + nv_log("Initialising GPU core...\n"); nv3_pextdev_init(); // Initialise Straps nv3_pmc_init(); // Initialise Master Control @@ -1024,7 +1024,7 @@ void* nv3_init(const device_t *info) nv3_ptimer_init(); // Initialise programmable interval timer nv3_pvideo_init(); // Initialise video overlay engine - nv_log("NV3: Initialising I2C..."); + nv_log("Initialising I2C..."); nv3->nvbase.i2c = i2c_gpio_init("nv3_i2c"); nv3->nvbase.ddc = ddc_init(i2c_gpio_get_bus(nv3->nvbase.i2c)); diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index e10382feb..de3bc2eec 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -108,7 +108,7 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) //ret = nv3_ramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { - nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); + nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); return 0x00; } @@ -171,7 +171,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) nv3_ramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions else { - nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); + nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); return; } } diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index ffe2c57cf..e9d8723ad 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -40,7 +40,7 @@ nv_register_t pbus_registers[] = { void nv3_pbus_init() { - nv_log("NV3: Initialising PBUS..."); + nv_log("Initialising PBUS..."); nv_log("Done\n"); } @@ -53,7 +53,7 @@ uint32_t nv3_pbus_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PBUS Read from 0x%08x", address); + nv_log("PBUS Read from 0x%08x", address); // if the register actually exists if (reg) @@ -91,7 +91,7 @@ void nv3_pbus_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); - nv_log("NV3: PBUS Write 0x%08x -> 0x%08x\n", value, address); + nv_log("PBUS Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) @@ -163,7 +163,7 @@ uint8_t nv3_pbus_rma_read(uint16_t addr) } // log current location for vbios RE - nv_log("NV3: MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + nv_log("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", addr, real_final_address, ret); break; @@ -228,7 +228,7 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val) nv3->pbus.rma.data &= ~0xff000000; nv3->pbus.rma.data |= (val << 24); - nv_log("NV3: MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + nv_log("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", addr, nv3->pbus.rma.addr, nv3->pbus.rma.data); if (nv3->pbus.rma.addr < NV3_MMIO_SIZE) diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 3e0d63b5e..c62911fb2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -31,7 +31,7 @@ void nv3_pextdev_init() { - nv_log("NV3: Initialising PEXTDEV....\n"); + nv_log("Initialising PEXTDEV....\n"); // Set the chip straps // Make these configurable in the future... @@ -43,7 +43,7 @@ void nv3_pextdev_init() // Bus width 128-Bit (some gpus were sold as 64bit for cost reduction) // - nv_log("NV3: Initialising straps...\n"); + nv_log("Initialising straps...\n"); nv3->pextdev.straps = (NV3_PSTRAPS_AGP2X_DISABLED << NV3_PSTRAPS_AGP2X) | @@ -62,8 +62,8 @@ void nv3_pextdev_init() (NV3_PSTRAPS_BIOS_PRESENT << NV3_PSTRAPS_BIOS) | (NV3_PSTRAPS_BUS_SPEED_66MHZ << NV3_PSTRAPS_BUS_SPEED); - nv_log("NV3: Straps = 0x%04x\n", nv3->pextdev.straps); - nv_log("NV3: Initialising PEXTDEV: Done\n"); + nv_log("Straps = 0x%04x\n", nv3->pextdev.straps); + nv_log("Initialising PEXTDEV: Done\n"); } // @@ -89,11 +89,11 @@ uint32_t nv3_pextdev_read(uint32_t address) // special consideration for straps if (address == NV3_PSTRAPS) { - nv_log("NV3: Straps Read (current value=0x%08x)\n", nv3->pextdev.straps); + nv_log("Straps Read (current value=0x%08x)\n", nv3->pextdev.straps); } else { - nv_log("NV3: PEXTDEV Read from 0x%08x", address); + nv_log("PEXTDEV Read from 0x%08x", address); } // if the register actually exists @@ -129,12 +129,12 @@ void nv3_pextdev_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); - nv_log("NV3: PEXTDEV Write 0x%08x -> 0x%08x\n", value, address); + nv_log("PEXTDEV Write 0x%08x -> 0x%08x\n", value, address); // special consideration for straps if (address == NV3_PSTRAPS) { - nv_log("NV3: Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps); + nv_log("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps); return; } diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index ba42c1734..2334e6d6c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -41,7 +41,7 @@ nv_register_t pfb_registers[] = { void nv3_pfb_init() { - nv_log("NV3: Initialising PFB..."); + nv_log("Initialising PFB..."); // initial configuration: // ram 4mb @@ -67,7 +67,7 @@ uint32_t nv3_pfb_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PFB Read from 0x%08x", address); + nv_log("PFB Read from 0x%08x", address); // if the register actually exists if (reg) @@ -106,7 +106,7 @@ void nv3_pfb_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); - nv_log("NV3: PFB Write 0x%08x -> 0x%08x", value, address); + nv_log("PFB Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) @@ -148,16 +148,16 @@ void nv3_pfb_config0_write(uint32_t val) uint32_t new_pfb_vtotal = new_pfb_htotal * (4/3); uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; - nv_log("NV3: Framebuffer Config Change\n"); - nv_log("NV3: Horizontal Size=%d pixels\n", new_pfb_htotal); - nv_log("NV3: Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); + nv_log("Framebuffer Config Change\n"); + nv_log("Horizontal Size=%d pixels\n", new_pfb_htotal); + nv_log("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) - nv_log("NV3: Bit Depth=8bpp\n"); + nv_log("Bit Depth=8bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP) - nv_log("NV3: Bit Depth=16bpp\n"); + nv_log("Bit Depth=16bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_32BPP) - nv_log("NV3: Bit Depth=32bpp\n"); + nv_log("Bit Depth=32bpp\n"); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 17d1f464b..d5a18af03 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -77,7 +77,7 @@ nv_register_t pfifo_registers[] = { // PFIFO init code void nv3_pfifo_init() { - nv_log("NV3: Initialising PFIFO..."); + nv_log("Initialising PFIFO..."); nv_log("Done!\n"); } @@ -89,7 +89,7 @@ uint32_t nv3_pfifo_read(uint32_t address) if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO) & NV3_PMC_ENABLE_PFIFO_ENABLED) { - nv_log("NV3: Repressing PFIFO read. The subsystem is disabled according to pmc_enable, returning 0\n"); + nv_log("Repressing PFIFO read. The subsystem is disabled according to pmc_enable, returning 0\n"); return 0x00; } @@ -99,7 +99,7 @@ uint32_t nv3_pfifo_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PFIFO Read from 0x%08x", address); + nv_log("PFIFO Read from 0x%08x", address); // if the register actually exists if (reg) @@ -297,13 +297,13 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO) & NV3_PMC_ENABLE_PFIFO_ENABLED) { - nv_log("NV3: Repressing PFIFO write. The subsystem is disabled according to pmc_enable\n"); + nv_log("Repressing PFIFO write. The subsystem is disabled according to pmc_enable\n"); return; } nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - nv_log("NV3: PFIFO Write 0x%08x -> 0x%08x", value, address); + nv_log("PFIFO Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) @@ -355,7 +355,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) else if (new_size_ramht == 3) new_size_ramht = 0x8000; - nv_log("NV3: RAMHT Reconfiguration\n" + nv_log("RAMHT Reconfiguration\n" "Base Address in RAMIN: %d\n" "Size: 0x%08x bytes\n", ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12, new_size_ramht); #endif @@ -363,7 +363,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CONFIG_RAMFC: nv3->pfifo.ramfc_config = value; - nv_log("NV3: RAMFC Reconfiguration\n" + nv_log("RAMFC Reconfiguration\n" "Base Address in RAMIN: %d\n", ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9); break; case NV3_PFIFO_CONFIG_RAMRO: @@ -376,7 +376,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) else if (new_size_ramro == 1) new_size_ramro = 0x2000; - nv_log("NV3: RAMRO Reconfiguration\n" + nv_log("RAMRO Reconfiguration\n" "Base Address in RAMIN: %d\n" "Size: 0x%08x bytes\n", ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9, new_size_ramro); break; @@ -557,7 +557,7 @@ void nv3_pfifo_cache0_pull() nv3->pfifo.cache0_settings.get_address ^= 0x04; #ifndef RELEASE_BUILD - nv_log("NV3: ***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE0 PULLED ****** Contextual information below\n"); + nv_log("***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE0 PULLED ****** Contextual information below\n"); nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); #endif @@ -640,7 +640,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) // Did we fuck up? if (oh_shit) { - nv_log("NV3: WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset); + nv_log("WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset); return; } @@ -710,7 +710,7 @@ void nv3_pfifo_cache1_pull() nv3->pfifo.cache0_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; #ifndef RELEASE_BUILD - nv_log("NV3: ***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE1 PULLED ****** Contextual information below\n"); + nv_log("***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE1 PULLED ****** Contextual information below\n"); nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); #endif diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 9835a788d..facc75d2f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -32,7 +32,7 @@ // Initialise the PGRAPH subsystem. void nv3_pgraph_init() { - nv_log("NV3: Initialising PGRAPH..."); + nv_log("Initialising PGRAPH..."); // Set up the vblank interrupt nv3->nvbase.svga.vblank_start = nv3_pgraph_vblank_start; nv_log("Done!\n"); @@ -98,7 +98,7 @@ uint32_t nv3_pgraph_read(uint32_t address) if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH) & NV3_PMC_ENABLE_PGRAPH_ENABLED) { - nv_log("NV3: Repressing PGRAPH read. The subsystem is disabled according to pmc_enable, returning 0\n"); + nv_log("Repressing PGRAPH read. The subsystem is disabled according to pmc_enable, returning 0\n"); return 0x00; } @@ -108,7 +108,7 @@ uint32_t nv3_pgraph_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PGRAPH Read from 0x%08x", address); + nv_log("PGRAPH Read from 0x%08x", address); // if the register actually exists if (reg) @@ -260,7 +260,7 @@ uint32_t nv3_pgraph_read(uint32_t address) // Addresses should be aligned to 4 bytes. uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); - nv_log("NV3: PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); + nv_log("PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); } else /* Completely unknown */ { @@ -276,13 +276,13 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH) & NV3_PMC_ENABLE_PGRAPH_ENABLED) { - nv_log("NV3: Repressing PGRAPH write. The subsystem is disabled according to pmc_enable\n"); + nv_log("Repressing PGRAPH write. The subsystem is disabled according to pmc_enable\n"); return; } nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); - nv_log("NV3: PGRAPH Write 0x%08x -> 0x%08x\n", value, address); + nv_log("PGRAPH Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) @@ -439,7 +439,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // Addresses should be aligned to 4 bytes. uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); - nv_log("NV3: PGRAPH Context Cache Write (Entry=%04x Value=%04x)\n", entry, value); + nv_log("PGRAPH Context Cache Write (Entry=%04x Value=%04x)\n", entry, value); nv3->pgraph.context_cache[entry] = value; } } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 4d8ef7c4f..f81dd8876 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -32,7 +32,7 @@ void nv3_pmc_init() { - nv_log("NV3: Initialising PMC....\n"); + nv_log("Initialising PMC....\n"); if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_A00) nv3->pmc.boot = NV3_BOOT_REG_REV_A00; @@ -43,7 +43,7 @@ void nv3_pmc_init() nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_SOFTWARE; - nv_log("NV3: Initialising PMC: Done\n"); + nv_log("Initialising PMC: Done\n"); } // @@ -60,7 +60,7 @@ nv_register_t pmc_registers[] = { uint32_t nv3_pmc_clear_interrupts() { - nv_log("NV3: Clearing IRQs\n"); + nv_log("Clearing IRQs\n"); pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } @@ -144,21 +144,21 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) { if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE) { - nv_log("NV3: Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); + nv_log("Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } else - nv_log("NV3: NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); + nv_log("NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); } else { if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_SOFTWARE) { - nv_log("NV3: Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); + nv_log("Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } else - nv_log("NV3: NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); + nv_log("NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); } } @@ -178,7 +178,7 @@ uint32_t nv3_pmc_read(uint32_t address) uint32_t ret = 0x00; // todo: friendly logging - nv_log("NV3: PMC Read from 0x%08x", address); + nv_log("PMC Read from 0x%08x", address); // if the register actually exists if (reg) @@ -227,7 +227,7 @@ void nv3_pmc_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); - nv_log("NV3: PMC Write 0x%08x -> 0x%08x", value, address); + nv_log("PMC Write 0x%08x -> 0x%08x", value, address); // if the register actually exists... if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index d059eb05f..c16b97641 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -36,7 +36,7 @@ nv_register_t pme_registers[] = { void nv3_pme_init() { - nv_log("NV3: Initialising PME..."); + nv_log("Initialising PME..."); nv_log("Done\n"); } @@ -49,7 +49,7 @@ uint32_t nv3_pme_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PME Read from 0x%08x", address); + nv_log("PME Read from 0x%08x", address); // if the register actually exists if (reg) @@ -93,7 +93,7 @@ void nv3_pme_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); - nv_log("NV3: PME Write 0x%08x -> 0x%08x\n", value, address); + nv_log("PME Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index c87a7e14e..95cc2afe2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -33,7 +33,7 @@ void nv3_pramdac_init() { - nv_log("NV3: Initialising PRAMDAC\n"); + nv_log("Initialising PRAMDAC\n"); // defaults, these come from vbios in reality // driver defaults are nonsensical(?), or the algorithm is wrong @@ -45,7 +45,7 @@ void nv3_pramdac_init() nv3_pramdac_set_pixel_clock(); nv3_pramdac_set_vram_clock(); - nv_log("NV3: Initialising PRAMDAC: Done\n"); + nv_log("Initialising PRAMDAC: Done\n"); } // Polls the pixel clock. @@ -119,7 +119,7 @@ void nv3_pramdac_set_vram_clock() double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box - nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f); + nv_log("Memory clock = %.2f MHz\n", frequency / 1000000.0f); nv3->nvbase.memory_clock_frequency = frequency; @@ -167,7 +167,7 @@ void nv3_pramdac_set_pixel_clock() double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box - nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f); + nv_log("Pixel clock = %.2f MHz\n", frequency / 1000000.0f); nv3->nvbase.pixel_clock_frequency = frequency; @@ -220,7 +220,7 @@ uint32_t nv3_pramdac_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PRAMDAC Read from 0x%08x", address); + nv_log("PRAMDAC Read from 0x%08x", address); // if the register actually exists if (reg) @@ -301,7 +301,7 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); - nv_log("NV3: PRAMDAC Write 0x%08x -> 0x%08x", value, address); + nv_log("PRAMDAC Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 3730765ab..16655779b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -61,7 +61,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) if (!nv3_ramin_arbitrate_read(addr, &val)) // Oh well { val = (uint8_t)nv3->nvbase.svga.vram[addr]; - nv_log("NV3: Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + nv_log("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); } return (uint8_t)val; @@ -87,7 +87,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) if (!nv3_ramin_arbitrate_read(addr, &val)) { val = (uint16_t)vram_16bit[addr]; - nv_log("NV3: Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + nv_log("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); } return val; @@ -114,7 +114,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { val = vram_32bit[addr]; - nv_log("NV3: Read dword from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + nv_log("Read dword from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); } return val; @@ -139,7 +139,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) if (!nv3_ramin_arbitrate_write(addr, val32)) { nv3->nvbase.svga.vram[addr] = val; - nv_log("NV3: Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); } @@ -165,7 +165,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) if (!nv3_ramin_arbitrate_write(addr, val32)) { vram_16bit[addr] = val; - nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); } @@ -191,7 +191,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) if (!nv3_ramin_arbitrate_write(addr, val32)) { vram_32bit[addr] = val; - nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } } @@ -358,7 +358,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel, uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; uint32_t ramht_cur_address = ramht_base; - nv_log("NV3: Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel, subchannel); + nv_log("Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel, subchannel); bool found_object = false; @@ -483,7 +483,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel, // Prints out some informaiton about the object void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context) { - nv_log("NV3: Found object:"); + nv_log("Found object:"); nv_log("Name: 0x%04x", name); nv_log("Context:"); diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index a3872c40a..47db7b3b5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -30,10 +30,10 @@ uint32_t nv3_ramfc_read(uint32_t address) { - nv_log("NV3: RAMFC (Unused DMA channel context) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); + nv_log("RAMFC (Unused DMA channel context) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); } void nv3_ramfc_write(uint32_t address, uint32_t value) { - nv_log("NV3: RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); + nv_log("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index fc0190c2e..b471f3a87 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -39,17 +39,17 @@ uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) // is this the right endianness? uint32_t hash = (hash_bytes[0] ^ hash_bytes[1] ^ hash_bytes[2] ^ hash_bytes[3] ^ (uint8_t)channel); - nv_log("NV3: Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, name, channel); + nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, name, channel); return hash; } uint32_t nv3_ramht_read(uint32_t address) { - nv_log("NV3: RAMHT (Graphics object storage hashtable) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); + nv_log("RAMHT (Graphics object storage hashtable) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); } void nv3_ramht_write(uint32_t address, uint32_t value) { - nv_log("NV3: RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); + nv_log("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index a206343c9..3ba6b9d7a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -30,12 +30,12 @@ uint32_t nv3_ramro_read(uint32_t address) { - nv_log("NV3: RAM Runout (invalid dma object submission) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); + nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); } void nv3_ramro_write(uint32_t address, uint32_t value) { - nv_log("NV3: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)\n", value, address); + nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)\n", value, address); } void nv3_ramro_send() diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index b182644ec..366f2510f 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -43,7 +43,7 @@ nv_register_t ptimer_registers[] = { // ptimer init code void nv3_ptimer_init() { - nv_log("NV3: Initialising PTIMER..."); + nv_log("Initialising PTIMER..."); nv_log("Done!\n"); } @@ -99,7 +99,7 @@ uint32_t nv3_ptimer_read(uint32_t address) if (address != NV3_PTIMER_TIME_0_NSEC && address != NV3_PTIMER_TIME_1_NSEC) { - nv_log("NV3: PTIMER Read from 0x%08x", address); + nv_log("PTIMER Read from 0x%08x", address); } uint32_t ret = 0x00; @@ -167,7 +167,7 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) // before doing anything, check the subsystem enablement nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - nv_log("NV3: PTIMER Write 0x%08x -> 0x%08x", value, address); + nv_log("PTIMER Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index dacf984c9..9d3a9b8b3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -52,7 +52,7 @@ uint32_t nv3_pvideo_read(uint32_t address) // todo: friendly logging - nv_log("NV3: PVIDEO Read from 0x%08x", address); + nv_log("PVIDEO Read from 0x%08x", address); // if the register actually exists if (reg) @@ -99,7 +99,7 @@ void nv3_pvideo_write(uint32_t address, uint32_t value) // before doing anything, check the subsystem enablement nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); - nv_log("NV3: PVIDEO Write 0x%08x -> 0x%08x\n", value, address); + nv_log("PVIDEO Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index eee994208..b07bf63b5 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -33,9 +33,20 @@ uint32_t nv3_user_read(uint32_t address) { uint8_t method_offset = (address & 0x1FFC); - nv_log("NV3: User Submission Area method_offset=0x%04x OH SHIT!! NOT IMPLEMENTED!!!", method_offset); + nv_log("User Submission Area method_offset=0x%04x\n", method_offset); + + // 0x10 is free CACHE1 object + // TODO: THERE ARE OTHER STUFF! + switch (method_offset) + { + case NV3_GENERIC_METHOD_IS_PFIFO_FREE: + return nv3_pfifo_cache1_is_free(); + + } + + nv_log("IT'S NOT IMPLEMENTED!!!!\n", method_offset); + - // 0x10 is free CACHE1 object, other stuff? return 0x00; }; From fea8cd649af3bbf7f2e72c77885dfcca35c2eda8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 6 Feb 2025 00:49:19 +0000 Subject: [PATCH 089/274] add various missing registers --- src/include/86box/nv/vid_nv3.h | 36 +++++++++++++++++++++--- src/video/nv/nv3/subsystems/nv3_pfb.c | 27 ++++++++++++++++-- src/video/nv/nv3/subsystems/nv3_pgraph.c | 9 ++++++ src/video/nv/nv3/subsystems/nv3_pvideo.c | 23 +++++++++++++++ 4 files changed, 89 insertions(+), 6 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 7602361fc..47a1d10a0 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -362,7 +362,15 @@ extern const device_config_t nv3_config[]; #define NV3_PFB_BOOT_RAM_EXTENSION 5 #define NV3_PFB_BOOT_RAM_EXTENSION_NONE 0x0 #define NV3_PFB_BOOT_RAM_EXTENSION_8MB 0x1 + +#define NV3_PFB_DELAY 0x100044 +#define NV3_PFB_GREEN_0 0x1000C0 + #define NV3_PFB_CONFIG_0 0x100200 // Framebuffer interface config register 0 + +// What is this lol +// ??? Part of the memory timings +#define NV3_PFB_RTL 0x100300 #define NV3_PFB_CONFIG_0_RESOLUTION 0 // 1=40 horiz. resolution // i assume it can be divided by some kind of divisor to produce the vertical resolution (e.g. 3/2 or multiply by 2/3) to get the final @@ -487,7 +495,12 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_TRAPPED_DATA 0x4006B8 #define NV3_PGRAPH_TRAPPED_INSTANCE 0x4006BC -#define NV3_PGRAPH_DMA_INTR_0 0x401000 // PGRAPH DMA Interrupt Status +#define NV3_PGRAPH_DMA_INTR_0 0x401100 // PGRAPH DMA Interrupt Status +#define NV3_PGRAPH_DMA_INTR_INSTANCE 0 +#define NV3_PGRAPH_DMA_INTR_PRESENT 4 +#define NV3_PGRAPH_DMA_INTR_PROTECTION 8 +#define NV3_PGRAPH_DMA_INTR_LINEAR 12 +#define NV3_PGRAPH_DMA_INTR_NOTIFY 16 #define NV3_PGRAPH_DMA_INTR_EN_0 0x401140 // PGRAPH DMA Interrupt Enable 0 // not sure about the class ids @@ -559,6 +572,13 @@ extern const device_config_t nv3_config[]; #define NV3_PVIDEO_START 0x680000 // Video Generation / overlay configuration #define NV3_PVIDEO_INTR 0x680100 #define NV3_PVIDEO_INTR_EN 0x680140 +#define NV3_PVIDEO_FIFO_THRESHOLD 0x680238 +#define NV3_PVIDEO_FIFO_BURST_LENGTH 0x68023C +#define NV3_PVIDEO_OVERLAY 0x680244 +#define NV3_PVIDEO_OVERLAY_VIDEO_IS_ON 0 +#define NV3_PVIDEO_OVERLAY_KEY_ENABLED 4 +#define NV3_PVIDEO_OVERLAY_FORMAT 8 // 0 = CCIR, 1 = YUY2 + #define NV3_PVIDEO_END 0x6802FF #define NV3_PRAMDAC_START 0x680300 @@ -780,8 +800,11 @@ typedef struct nv3_straps_s typedef struct nv3_pfb_s { uint32_t boot; - uint32_t config_0; + uint32_t config_0; // Framebuffer width, etc. uint32_t config_1; + uint32_t green; + uint32_t delay; + uint32_t rtl; // Part of the memory timings } nv3_pfb_t; #define NV3_RMA_NUM_REGS 4 @@ -974,6 +997,8 @@ typedef struct nv3_pgraph_s uint32_t interrupt_enable_0; // Interrupt enable 0 uint32_t interrupt_status_1; // Interrupt status 1 uint32_t interrupt_enable_1; // Interrupt enable 1 + uint32_t interrupt_status_dma; // Interrupt status for DMA + uint32_t interrupt_enable_dma; // Interrupt enable for DMA uint32_t context_switch; // TODO: Make this a struct, it's just going to be enormous lol. nv3_pgraph_context_control_t context_control; @@ -986,10 +1011,12 @@ typedef struct nv3_pgraph_s uint32_t abs_uclip_xmax; uint32_t abs_uclip_ymin; uint32_t abs_uclip_ymax; + // Canvas stuff nv3_position_16_bigy_t src_canvas_min; nv3_position_16_bigy_t src_canvas_max; nv3_position_16_bigy_t dst_canvas_min; nv3_position_16_bigy_t dst_canvas_max; + // Pattern stuff nv3_color_x3a10g10b10_t pattern_color_0_0; uint32_t pattern_color_0_1; // only 7:0 relevant nv3_color_x3a10g10b10_t pattern_color_1_0; @@ -1012,8 +1039,6 @@ typedef struct nv3_pgraph_s uint32_t trapped_address; uint32_t trapped_data; uint32_t trapped_instance; - uint32_t interrupt_status_dma; - uint32_t interrupt_enable_dma; } nv3_pgraph_t; // GPU Manufacturing Configuration (again) @@ -1172,6 +1197,9 @@ typedef struct nv3_pvideo_s { uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable + uint32_t fifo_threshold; // FIFO threshold + uint32_t fifo_burst_size; // FIFO burst size + uint32_t overlay_settings; // Overlay settings } nv3_pvideo_t; typedef struct nv3_pme_s // Mediaport diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 2334e6d6c..b2eae7c55 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -34,8 +34,11 @@ void nv3_pfb_config0_write(uint32_t val); nv_register_t pfb_registers[] = { { NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL}, + { NV3_PFB_DELAY, "PFB Delay", NULL, NULL}, + { NV3_PFB_GREEN_0, "PFB Green / Power Saving", NULL, NULL,}, { NV3_PFB_CONFIG_0, "PFB Framebuffer Config 0", nv3_pfb_config0_read, nv3_pfb_config0_write }, { NV3_PFB_CONFIG_1, "PFB Framebuffer Config 1", NULL, NULL }, + { NV3_PFB_RTL, "PFB RTL (Part of memory timings?)", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -86,6 +89,16 @@ uint32_t nv3_pfb_read(uint32_t address) case NV3_PFB_CONFIG_1: ret = nv3->pfb.config_1; break; + case NV3_PFB_GREEN_0: + ret = nv3->pfb.green; + break; + case NV3_PFB_DELAY: + ret = nv3->pfb.delay; + break; + case NV3_PFB_RTL: + ret = nv3->pfb.rtl; + break; + } } @@ -123,9 +136,19 @@ void nv3_pfb_write(uint32_t address, uint32_t value) { switch (reg->address) { - // Config 0 has a read/write function + // Config 0 has a read/write function case NV3_PFB_CONFIG_1: // Config Register 1 nv3->pfb.config_1 = value; + break; + case NV3_PFB_GREEN_0: + nv3->pfb.green = value; + break; + case NV3_PFB_DELAY: + nv3->pfb.delay = value; + break; + case NV3_PFB_RTL: + nv3->pfb.rtl = value; + break; } } } @@ -145,7 +168,7 @@ void nv3_pfb_config0_write(uint32_t val) uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; // i don't think 16:9 is supported - uint32_t new_pfb_vtotal = new_pfb_htotal * (4/3); + uint32_t new_pfb_vtotal = new_pfb_htotal * (4.0/3.0); uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; nv_log("Framebuffer Config Change\n"); diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index facc75d2f..d6ae35465 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -332,6 +332,15 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) nv3->pgraph.interrupt_enable_1 = value & 0x00011111; nv3_pmc_handle_interrupts(true); break; + case NV3_PGRAPH_DMA_INTR_0: + nv3->pgraph.interrupt_status_dma &= ~value; + nv3_pmc_clear_interrupts(); + break; + case NV3_PGRAPH_DMA_INTR_EN_0: + nv3->pgraph.interrupt_enable_dma = value & 0x000111111; + nv_log("Handling PGRAPH_DMA interrupts not implemented"); + nv3_pmc_handle_interrupts(true); + break; // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like // during the driver initialisation process diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index 9d3a9b8b3..6709c92a2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -32,6 +32,9 @@ nv_register_t pvideo_registers[] = { { NV3_PVIDEO_INTR, "PVIDEO - Interrupt Status", NULL, NULL}, { NV3_PVIDEO_INTR_EN, "PVIDEO - Interrupt Enable", NULL, NULL,}, + { NV3_PVIDEO_FIFO_THRESHOLD, "PVIDEO - FIFO Fill Threshold", NULL, NULL}, + { NV3_PVIDEO_FIFO_BURST_LENGTH, "PVIDEO - FIFO Burst Length (1=32, 2=64, 3=128)", NULL, NULL}, + { NV3_PVIDEO_OVERLAY, "PVIDEO - Overlay Info (Bit0 = Video On, Bit4 = Key On, Bit8 = Format, 0=CCIR, 1=YUV2)", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -78,6 +81,16 @@ uint32_t nv3_pvideo_read(uint32_t address) case NV3_PVIDEO_INTR_EN: ret = nv3->pvideo.interrupt_enable; break; + case NV3_PVIDEO_FIFO_THRESHOLD: + ret = nv3->pvideo.fifo_threshold; + break; + case NV3_PVIDEO_FIFO_BURST_LENGTH: + ret = nv3->pvideo.fifo_burst_size & 0x03; + break; + case NV3_PVIDEO_OVERLAY: + ret = nv3->pvideo.overlay_settings & 0xFF; + break; + } } @@ -126,6 +139,16 @@ void nv3_pvideo_write(uint32_t address, uint32_t value) case NV3_PVIDEO_INTR_EN: nv3->pvideo.interrupt_enable = value & 0x00000001; break; + case NV3_PVIDEO_FIFO_THRESHOLD: + // only bits 6:3 matter + nv3->pvideo.fifo_threshold = ((value >> 3) & 0x0F) << 3; + break; + case NV3_PVIDEO_FIFO_BURST_LENGTH: + nv3->pvideo.fifo_burst_size = value & 0x03; + break; + case NV3_PVIDEO_OVERLAY: + nv3->pvideo.overlay_settings = value & 0xFF; + break; } } } From c816f7560dfaeed71ac01fae5380acc2fc9ff93a Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 9 Feb 2025 18:10:17 +0000 Subject: [PATCH 090/274] more defines --- doc/nvidia_notes/NV3 DMA Engine.txt | 29 +++++++++++ src/include/86box/nv/vid_nv3.h | 62 ++++++++++++++++++++++++ src/video/nv/nv3/nv3_core.c | 4 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 1 + src/video/nv/nv3/subsystems/nv3_pmc.c | 10 ++-- src/video/nv/nv3/subsystems/nv3_pme.c | 4 +- 6 files changed, 103 insertions(+), 7 deletions(-) create mode 100644 doc/nvidia_notes/NV3 DMA Engine.txt diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt new file mode 100644 index 000000000..50d34cfa9 --- /dev/null +++ b/doc/nvidia_notes/NV3 DMA Engine.txt @@ -0,0 +1,29 @@ +NV3 DMA Engine +(DirectDraw Driver) + +Initially set CACHES, CACHE1_PULL0, CACHE1_PULL1, CACHE1_DMA0 to 1 + +Same for other areas + +CACHE1_PUSH1 contains CHID + +If it's different: + +If RmFifoFlushContext failed: Do nothing + +Set PULL0, PUSH0, Caches to 1, return false + + +If it's not: +DMA TLB PTE seems to be 1 for direct programming, maybe RM does it differently +Tag=FFFFFFFF +CACHE1_DMA1 - Number of bytes to send +CACHE1_DMA2 - Get offset +CACHE1_DMA3 - Bus address space (Area BAR0 mapped to? Or bar1?) + +TO START: +To set up DMA for for Cache1 Puller: CACHE1_PULL0 -> 1, changes to 0 when done +To set up DMA Cache1 Push: CACHE1_PULL0 -> 1, changes to 0 when done +Set CACHES to 1 + +GO: Set DMA0 to 1 diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 47a1d10a0..6b6e0e5d6 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -443,10 +443,72 @@ extern const device_config_t nv3_config[]; #define NV3_PME_END 0x200FFF #define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part // PGRAPH Core + +// For these debug registers, 0=Disabled, 1=Enabled + +// Debug 0: General #define NV3_PGRAPH_DEBUG_0 0x400080 +#define NV3_PGRAPH_DEBUG_0_STATE_IN_RESET 0 +#define NV3_PGRAPH_DEBUG_0_AP_PIPE_IN_RESET 1 +#define NV3_PGRAPH_DEBUG_0_CACHE_IN_RESET 2 +#define NV3_PGRAPH_DEBUG_0_3D_PIPE_IN_RESET 3 +#define NV3_PGRAPH_DEBUG_0_BULK_READS 4 +#define NV3_PGRAPH_DEBUG_0_TILING 16 +#define NV3_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20 +#define NV3_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D 21 +#define NV3_PGRAPH_DEBUG_0_DRAWDIR_AUT 24 +#define NV3_PGRAPH_DEBUG_0_DRAWDIR_Y 25 +#define NV3_PGRAPH_DEBUG_0_ALPHA_ABORT 28 + +// Debug 1: Registers #define NV3_PGRAPH_DEBUG_1 0x400084 +#define NV3_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0 +#define NV3_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 4 +#define NV3_PGRAPH_DEBUG_1_TURBO3D_2X 8 +#define NV3_PGRAPH_DEBUG_1_TURBO3D_4X 9 +#define NV3_PGRAPH_DEBUG_1_TRIANGLE_OPS 12 +#define NV3_PGRAPH_DEBUG_1_TRIANGLE_CLIP_OPS 13 +#define NV3_PGRAPH_DEBUG_1_INSTANCE 16 +#define NV3_PGRAPH_DEBUG_1_CONTEXT 20 +#define NV3_PGRAPH_DEBUG_1_CACHE_FLUSH 24 +#define NV3_PGRAPH_DEBUG_1_ZCLAMP 28 + +// Debug 2: 3D Pipeline #define NV3_PGRAPH_DEBUG_2 0x400088 +#define NV3_PGRAPH_DEBUG_2_AVOID_READMODIFYWRITE_BLEND 0 +#define NV3_PGRAPH_DEBUG_2_DPWR_FIFO 8 +#define NV3_PGRAPH_DEBUG_2_BILINEAR_FILTERING_3D 12 +#define NV3_PGRAPH_DEBUG_2_ANISOTROPIC_FILTERING_3D 13 +#define NV3_PGRAPH_DEBUG_2_FOG 14 +#define NV3_PGRAPH_DEBUG_2_LIGHTING 15 // Not sure what this does, maybe hardware t&l was planned +#define NV3_PGRAPH_DEBUG_2_BILINEAR_FILTERING_2D 16 +#define NV3_PGRAPH_DEBUG_2_ANISOTROPIC_FILTERING_2D 17 +#define NV3_PGRAPH_DEBUG_2_D3D_COALESCE 20 // coalesce reads/writes for d3d class 0x17 +#define NV3_PGRAPH_DEBUG_2_D3D_COALESCE_POINT_ZETA 22 // class 0x18 coalesce +#define NV3_PGRAPH_DEBUG_2_PREFETCH 24 +#define NV3_PGRAPH_DEBUG_2_VOLATILE_RESET 28 + +// Debug 3: Zeta & Alpha Buffer #define NV3_PGRAPH_DEBUG_3 0x40008C +#define NV3_PGRAPH_DEBUG_3_CULLING 0 +#define NV3_PGRAPH_DEBUG_3_FAST_DATA_D3D 4 +#define NV3_PGRAPH_DEBUG_3_FAST_DATA_STRETCH 5 +#define NV3_PGRAPH_DEBUG_3_ZFLUSH 7 +#define NV3_PGRAPH_DEBUG_3_AUTOZFLUSH_POINT_ZETA 8 +#define NV3_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D 9 +#define NV3_PGRAPH_DEBUG_3_SLOT_CONFLICT_POINT_ZETA 10 // Slot conflict handling for POINT_ZETA (class 0x18) +#define NV3_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D 11 // Slot conflict handling for D3D5_TRI (class 0x17) +#define NV3_PGRAPH_DEBUG_3_EARLY_ZABORT 12 +#define NV3_PGRAPH_DEBUG_3_TRIANGLE_END_FLUSH 13 +#define NV3_PGRAPH_DEBUG_3_ZFIFO_NOOP 14 // ??? +#define NV3_PGRAPH_DEBUG_3_DITHER 15 +#define NV3_PGRAPH_DEBUG_3_FORCE_COLOR_BUFFER_READ 16 +#define NV3_PGRAPH_DEBUG_3_FORCE_ZETA_BUFFER_READ 17 +#define NV3_PGRAPH_DEBUG_3_DATA_CHECK 20 +#define NV3_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21 +#define NV3_PGRAPH_DEBUG_3_FORMAT_CHECK 22 +#define NV3_PGRAPH_DEBUG_3_ALPHA_CHECK 24 + #define NV3_PGRAPH_INTR_0 0x400100 #define NV3_PGRAPH_INTR_1 0x400104 #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index ff844c02d..d190c838e 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -952,8 +952,10 @@ void* nv3_init(const device_t *info) else nv3->nvbase.log = log_open_cyclic("NV3"); +#ifdef ENABLE_NV_LOG // Allows nv_log to be used for multiple nvidia devices - nv_log_set_device(nv3->nvbase.log); + nv_log_set_device(nv3->nvbase.log); +#endif nv_log("initialising core\n"); // Figure out which vbios the user selected diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index d6ae35465..b1743c04d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -131,6 +131,7 @@ uint32_t nv3_pgraph_read(uint32_t address) break; case NV3_PGRAPH_DEBUG_3: ret = nv3->pgraph.debug_3; + break; //interrupt status and enable regs case NV3_PGRAPH_INTR_0: ret = nv3->pgraph.interrupt_status_0; diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index f81dd8876..f7f91e87d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -232,10 +232,6 @@ void nv3_pmc_write(uint32_t address, uint32_t value) // if the register actually exists... if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); // ... call its on-write function if (reg->on_write) @@ -266,5 +262,11 @@ void nv3_pmc_write(uint32_t address, uint32_t value) break; } } + + if (reg->friendly_name) + nv_log(": %s\n", reg->friendly_name); + else + nv_log("\n"); + } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index c16b97641..392bcfd63 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -61,7 +61,7 @@ uint32_t nv3_pme_read(uint32_t address) { // Interrupt state: // Bit 0 - Image Notifier - // Bit 4 - Vertical Blank Interfal Notifier + // Bit 4 - Vertical Blank Interval Notifier // Bit 8 - Video Notifier // Bit 12 - Audio Notifier // Bit 16 - VMI Notifer @@ -128,4 +128,4 @@ void nv3_pme_write(uint32_t address, uint32_t value) } } - } \ No newline at end of file +} \ No newline at end of file From 35cb8a4cf2f6ca1c04df2250e2ce69407ccdd6f8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 10 Feb 2025 02:32:02 +0000 Subject: [PATCH 091/274] Fix subchannel free detection. --- .../nv3 driver init status_2025-02-10.txt | 96 +++++++++++++++++++ .../nv3 driver status_CURRENT.txt | 4 - src/include/86box/nv/vid_nv3.h | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 7 +- src/video/nv/nv3/subsystems/nv3_user.c | 2 +- 5 files changed, 102 insertions(+), 9 deletions(-) create mode 100644 doc/nvidia_notes/nv3 driver init status_2025-02-10.txt delete mode 100644 doc/nvidia_notes/nv3 driver status_CURRENT.txt diff --git a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt new file mode 100644 index 000000000..c76e79743 --- /dev/null +++ b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt @@ -0,0 +1,96 @@ +nv3_disp: + +0x10fe -> DrvBitBlt +0x19be -> DrvCopyBits +0x597c -> DrvCreateDeviceBitmap +0x5a6e -> DrvDeleteDeviceBitmap +0x60b8 -> DrvTextOut +0x6248 -> DrvDestroyFont +0x64b8 -> DrvRealizeBrush +0x6a46 -> DrvDitherColor +0x797a -> DrvGetDirectDrawInfo +0x7b14 -> DrvEnableDirectDraw +0x7b70 -> DrvDisableDirectDraw +0x817c -> DrvPaint +0x81c2 -> DrvResetPDEV +0x82dc -> DrvEnableDriver +0x8312 -> DrvEnablePDEV +0x83ee -> DrvDisablePDEV +0x840a -> DrvCompletePDEV +0x8418 -> DrvSynchronise +0x845a -> DrvEnableSurface +0x851a -> DrvDisableSurface +0x8554 -> DrvAssertMode +0x8690 -> DrvGetModes +0xe59a -> DrvEscape +0xf3ee -> DrvFillPath +0xf3f6 -> DrvStrokePath +0xfa08 -> DrvLineTo +0x12fee -> DrvSetPalette +0x132a4 -> DrvMovePointer +0x13d20 -> DrvSetPointerShape +0x13dea -> DrvStretchBlt +0x147f2 -> DrvSetPixelFormat +0x1483c -> DrvDescribePixelFormat +0x1495a -> DrvClipChanged +0x255b8 -> DrvSwapBuffers + +DrvEnableDriver SUCCESS +DrvEnablePDEV SUCCESS 23:28 09/02/2025 + Check for cjCaps >= 0x130 && cjDevInfo >= 0x12C SUCCESS 23:31 09/02/2025 + EngAllocMem call SUCCESS 23:38 09/02/2025 + CreateOglGlobalMemory call SUCCESS 23:40 09/02/2025 + bInitializeModeFields call SUCCESS 23:41 09/02/2025 + bInitializePalette call SUCCESS 23:42 09/02/2025 + EngDeviceIoControl IOCTL 0x232020 (CHECK mini) SUCCESS + EngDeviceIoControl IOCTL 0x232044 (CHECK mini) SUCCESS (eax=0) +DrvCompletePDEV SUCCESS 23:52 09/02/2025 +DrvEnableSurface + bEnableHardware call + EngCreateSemaphore call #1 csCrtc SUCCESS 00:55 10/02/2025 + EngCreateSemaphore call #2 csFifo SUCCESS 00:57 10/02/2025 + EngDeviceIoControl IOCTL 0x230460 SUCCESS 00:57 10/02/2025 + EngDeviceIoControl IOCTL 0x230458 SUCCESS 00:57 10/02/2025 + NvAllocRoot SUCCESS 01:03 10/02/2025 + NvAllocDevice SUCCESS 01:04 10/02/2025 + NV3/NV4 architecture check SUCCESS 01:14 10/02/2025 + bAssertModeHardware call (bEnable=1) FAILURE - HANG/LOOP + EngDeviceIoControl IOCTL 0x23040C] FAILURE 01:27 10/02/2025 + nv3_mini NVStartIO ioctlcode=0x23040C + NVSetMode + NV3SetMode SUCCESS 01:53 10/02/2025 + RmUnloadState SUCCESS 01:48 10/02/2025 + VBESetModeEx SUCCESS 01:51 10/02/2025 + NV_OEMEnableExtensions SUCCESS 01:52 10/02/2025 + UpdateArbitrationSettings SUCCESS 01:52 10/02/2025 + RmLoadState SUCCESS 01:53 10/02/2025 + NV3EnableCursor SUCCESS 01:54 10/02/2025 + NV3WaitUntilFinished SUCCESS Passing 02:23 10/02/2025 + EngDeviceIoControl IOCTL 0x230408 + EngDeviceIoControl IOCTL 0x232024 + NvAllocHardware + bCreateStdPatches(?) + CHECK - NV4 + vDestroyStdPatches(?) + NV3_WaitForOneVerticalRefresh + EngDeviceIoControl IOCTL 0x230410 + + + SET UP CORRECT FUNCTION POINTERS + + _heap_init call + bEnableOffscreenHeap call + bEnablePointer call + bEnableText call + bEnablePalette call + bEnableDirectDraw call + EngCreateBitmap call + EngAssociateBitmap call + + + + + +DrvDisableSurface: ONLY IN THE CASE OF FAILURE + + diff --git a/doc/nvidia_notes/nv3 driver status_CURRENT.txt b/doc/nvidia_notes/nv3 driver status_CURRENT.txt deleted file mode 100644 index f284f7457..000000000 --- a/doc/nvidia_notes/nv3 driver status_CURRENT.txt +++ /dev/null @@ -1,4 +0,0 @@ -Failure condition: - Failed check, causes fifoService call in fifo service init in RM, FifoState STATE_LOAD - - CHECK NVSTARTIO! DEBUG TOMORROW \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 6b6e0e5d6..aeff3a8ce 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1431,7 +1431,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val); void nv3_pfifo_cache1_pull(); uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); -bool nv3_pfifo_cache1_is_free(); +uint32_t nv3_pfifo_cache1_num_free_spaces(); // NV3 PFB void nv3_pfb_init(); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index d5a18af03..5fe709ec6 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -185,7 +185,7 @@ uint32_t nv3_pfifo_read(uint32_t address) // Check if Cache1 (0x7C bytes in size depending on gpu?) is full // Based on how the drivers do it - if (!nv3_pfifo_cache1_is_free()) + if (!nv3_pfifo_cache1_num_free_spaces()) ret |= 1 << NV3_PFIFO_CACHE1_STATUS_FULL; if (nv3->pfifo.runout_put != nv3->pfifo.runout_get) @@ -605,7 +605,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) new_address |= (nv3_runout_reason_cache_ran_out << NV3_PFIFO_RUNOUT_RAMIN_ERR); } - if (!nv3_pfifo_cache1_is_free()) + if (!nv3_pfifo_cache1_num_free_spaces()) { oh_shit = true; oh_shit_reason = nv3_runout_reason_free_count_overrun; @@ -718,7 +718,8 @@ void nv3_pfifo_cache1_pull() //Todo: finish it } -bool nv3_pfifo_cache1_is_free() +// THIS IS PER SUBCHANNEL! +uint32_t nv3_pfifo_cache1_num_free_spaces() { // convert to gray code uint32_t real_get_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.get_address); diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index b07bf63b5..43fa72a94 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -40,7 +40,7 @@ uint32_t nv3_user_read(uint32_t address) switch (method_offset) { case NV3_GENERIC_METHOD_IS_PFIFO_FREE: - return nv3_pfifo_cache1_is_free(); + return nv3_pfifo_cache1_num_free_spaces(); } From 13597fc39ec8eb44948f5482c90ace6c4b8a2ede Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Feb 2025 23:25:06 +0000 Subject: [PATCH 092/274] fix SetNotifyCtxDma --- src/include/86box/nv/classes/vid_nv3_classes.h | 7 ++++--- src/video/CMakeLists.txt | 2 ++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 5 +++-- src/video/nv/nv3/subsystems/nv3_user.c | 10 ++++++++-- 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 36bac6e66..0e638f17e 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1096,8 +1096,10 @@ typedef struct nv3_grobj_s // TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! #pragma pack(pop) // return packing to whatever it was before this disaster -// Method IDs -#define NV3_GENERIC_METHOD_IS_PFIFO_FREE 0x0010 +// PIO Subchannel info +#define NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE 0x0010 +#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START 0x0012 +#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017 // Class methods void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj); @@ -1109,7 +1111,6 @@ void nv3_class_005_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_006_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_007_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_009_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj); void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj); diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index cf65f2519..388681f88 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -80,6 +80,7 @@ add_library(vid OBJECT vid_att2xc498_ramdac.c vid_xga.c vid_bochs_vbe.c + nv/nv_base.c nv/nv_rivatimer.c nv/nv3/nv3_core.c @@ -123,6 +124,7 @@ add_library(vid OBJECT nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c nv/nv3/classes/nv3_class_018_point_zeta_buffer.c nv/nv3/classes/nv3_class_01c_image_in_memory.c + ) if(G100) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 5fe709ec6..ad4d4469f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -612,7 +612,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR); } - if (method_offset > 0 && method_offset <= 0x100) + // 0x0 is used for the context + if (method_offset > 0 && method_offset < 0x100) { // Reserved NVIDIA Objects oh_shit = true; @@ -651,7 +652,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) nv3->pfifo.cache1_entries[current_put_address].data = val; // now we have to recalculate the cache1 put address - uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address); + uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1; if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# next_put_address &= NV3_PFIFO_CACHE1_SIZE_REV_C; diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index 43fa72a94..c26df9b40 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -28,19 +28,25 @@ #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv3.h> + +// PIO Method Submission // 128 channels conceptually supported - a hangover from nv1 where multiple windows all directly programming the gpu were supported? total lunacy. uint32_t nv3_user_read(uint32_t address) { + // Get the address within the subchannel + //todo: print out the subchannel uint8_t method_offset = (address & 0x1FFC); - nv_log("User Submission Area method_offset=0x%04x\n", method_offset); + nv_log("User Submission Area PIO Subchannel method_offset=0x%04x\n (Trying to read...)", method_offset); // 0x10 is free CACHE1 object // TODO: THERE ARE OTHER STUFF! switch (method_offset) { - case NV3_GENERIC_METHOD_IS_PFIFO_FREE: + case NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE: return nv3_pfifo_cache1_num_free_spaces(); + case NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START ... NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END: + return 0x00; } From 289768a93f76ea94280564b2bad2dffe3a01bf36 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 12 Feb 2025 00:36:56 +0000 Subject: [PATCH 093/274] Fix include header capitalisation --- .../86box/nv/classes/vid_nv3_classes.h | 6 ++---- src/include/86box/nv/vid_nv3.h | 2 +- .../nv3/classes/nv3_class_001_beta_factor.c | 14 ++++++------- src/video/nv/nv3/classes/nv3_class_002_rop.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_004_plane_mask.c | 14 ++++++------- .../nv3_class_005_clipping_rectangle.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_006_pattern.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_007_rectangle.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_008_point.c | 14 ++++++------- src/video/nv/nv3/classes/nv3_class_009_line.c | 14 ++++++------- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_00b_triangle.c | 14 ++++++------- .../classes/nv3_class_00c_win95_gdi_text.c | 14 ++++++------- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 14 ++++++------- .../nv3_class_00e_scaled_image_from_mem.c | 14 ++++++------- src/video/nv/nv3/classes/nv3_class_010_blit.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_011_image.c | 14 ++++++------- .../nv/nv3/classes/nv3_class_012_bitmap.c | 14 ++++++------- .../classes/nv3_class_014_transfer2memory.c | 14 ++++++------- .../nv3_class_015_stretched_image_from_cpu.c | 14 ++++++------- .../nv3_class_017_d3d5_tri_zeta_buffer.c | 14 ++++++------- .../classes/nv3_class_018_point_zeta_buffer.c | 14 ++++++------- .../classes/nv3_class_01c_image_in_memory.c | 14 ++++++------- src/video/nv/nv3/classes/nv3_class_names.c | 12 +++++------ .../nv/nv3/classes/nv3_class_shared_methods.c | 14 ++++++------- src/video/nv/nv3/nv3_core.c | 16 +++++++-------- src/video/nv/nv3/nv3_core_arbiter.c | 14 ++++++------- src/video/nv/nv3/nv3_core_config.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pbus.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pextdev.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pfb.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pfifo.c | 20 +++++++++---------- src/video/nv/nv3/subsystems/nv3_pgraph.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pmc.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pme.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pramdac.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pramin.c | 16 +++++++-------- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 14 ++++++------- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 16 +++++++-------- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_ptimer.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_pvideo.c | 14 ++++++------- src/video/nv/nv3/subsystems/nv3_user.c | 14 ++++++------- src/video/nv/nv_base.c | 6 +++--- 46 files changed, 312 insertions(+), 314 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 0e638f17e..aa23d29dc 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -11,8 +11,7 @@ * Note: These uint32_ts are basically object methods that are being submitted * They have different names so the user can use them more easily but different versions of the same class can be distinguished * ALL of these structures HAVE(?) to be a size of exactly 0x2000 bytes because that's what the hashtable expects and they need to actually map into the vram address space - * (they are converted to pointers). - * directly to the PHYSICAL PGRAPH REGISTERS while sitting in RAMHT!!!!. + * (they are converted to pointers). In the case of NV3, these map directly to the PHYSICAL PGRAPH REGISTERS while sitting in RAMHT!!!!. * * Also, these class IDs don't relate to the internal architecture of the GPU. * Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of @@ -1065,8 +1064,7 @@ typedef enum nv3_object_class_01C_pixel_format_e // 16-bits (Y16) - Planar YUV 16 bits (Y value only), 2 bits of indexed colour too? nv3_m2mt_pixel_format_le_y16_p2 = 0x1010101, - /* 1 unused bit, 555 15-bit format, p2(?) - */ + /* 1 unused bit, 555 15-bit format, p2(?) */ nv3_m2mt_pixel_format_x1r5g5b5_p2 = 0x1000000, // X8G8B8R8, 24-bit colour (or 24-bit colour with alpha) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index aeff3a8ce..72d6d5a3d 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -22,7 +22,7 @@ */ #pragma once -#include <86Box/nv/classes/vid_nv3_classes.h> +#include <86box/nv/classes/vid_nv3_classes.h> // The GPU base structure extern const device_config_t nv3_config[]; diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index b6b97ee3a..7a700bf6e 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_001 beta_factor; diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index 747d4b017..ac06ef010 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_002 nv3_rop; diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 08f854529..887e2a8bd 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_003 nv3_chroma_key; diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 0388bc35a..95e5e70c4 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_004 nv3_plane_mask; diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 01f395040..76ab1cfec 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -18,14 +18,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_005 nv3_clipping_rectangle; diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index 282557b95..32561e977 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_006 nv3_pattern; diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 3d378df91..2b194960b 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_007 nv3_rectangle; diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 55fae702c..eaa12f5c4 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_008 nv3_point; diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index cd0a8b768..a17cf0f90 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_009 nv3_line; diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index f9c23dc21..66d3d949b 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -20,14 +20,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_00A nv3_lin; diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index a65b3d600..f1d41a816 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_00B nv3_triangle; diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 54c013783..d8dbc4513 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_00C nv3_win95_gdi_text; diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 10ccb9bc3..4f51f187a 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_00D nv3_m2mf; diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index 9a4e86dca..165c1e9d3 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_00E nv3_scaled_image_from_mem; diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 2bcdc2234..f32309343 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_010 nv3_blit; diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 9a2f73486..e42ea8071 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_011 nv3_image; diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index f2d49f6b0..a0ff8d537 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -20,14 +20,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_012 nv3_bitmap; diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index ada899cf6..bc4e3f879 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -20,14 +20,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_014 nv3_transfer2memory; diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index 24480624d..1954724d1 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_015 nv3_stretched_image_from_cpu; diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index b45ef8968..7c669a1e5 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_017 nv3_d3d5_tri; diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 23e09904f..bbf29694f 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index e6533627d..f40924deb 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_01C nv3_image_in_memory; diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index e05ddc1eb..ded63ece2 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -16,14 +16,14 @@ */ #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> #include <86box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/nv/vid_nv3.h> /* These are the object classes AS RECOGNISED BY THE GRAPHICS HARDWARE. */ /* The drivers implement a COMPLETELY DIFFERENT SET OF CLASSES. */ diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index e336168c6..dd6c49fed 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index d190c838e..949ce53be 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -17,15 +17,15 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> -#include <86Box/io.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> nv3_t* nv3; diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index de3bc2eec..6e8e2b9a5 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -24,14 +24,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> // Gets a register... // move this somewhere else when we have more models diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index d32a7dfd7..e8beb6df7 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -17,15 +17,15 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/io.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> const device_config_t nv3_config[] = { diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index e9d8723ad..c9fd0f3aa 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> // NV3 PBUS RMA - Real Mode Access for VBIOS // This basically works like a shifter, you write one byte at a time from [0x3d0...0x3d3] and it shifts it in to build a 32-bit MMIO address... diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 3aa1d497b..d5d17fe2d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -19,13 +19,13 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> /* Nvidia DMA Engine */ \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index c62911fb2..6d8cadbf0 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -20,14 +20,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> void nv3_pextdev_init() { diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index b2eae7c55..435225bc2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> // Functions only used in this translation unit uint32_t nv3_pfb_config0_read(); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index ad4d4469f..4a62c8cf5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -6,9 +6,9 @@ * * This file is part of the 86Box distribution. * - * NV3 pfifo (FIFO for graphics object submission) - * - * + * NV3 PFIFO (FIFO for graphics object submission) + * PIO object submission + * Gray code conversion routines * * Authors: Connor Hyde, I need a better email address ;^) * @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> // // ****** PFIFO register list START ****** diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index b1743c04d..85ad21cff 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> // Initialise the PGRAPH subsystem. diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index f7f91e87d..f67eb707b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index 392bcfd63..e555c9752 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> nv_register_t pme_registers[] = { { NV3_PME_INTR, "PME - Interrupt Status", NULL, NULL}, diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 95cc2afe2..6ff090716 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -22,14 +22,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> void nv3_pramdac_init() { diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 16655779b..8dcba1b54 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -20,14 +20,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> -#include <86Box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> // Functions only used in this translation unit diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index 47db7b3b5..9a21c2e4f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> uint32_t nv3_ramfc_read(uint32_t address) { diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index b471f3a87..e56dd5c3a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> -#include <86Box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> /* This implements the hash that all the objects are stored within. It is used to get the offset within RAMHT of a graphics object. diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 3ba6b9d7a..2104868c6 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> uint32_t nv3_ramro_read(uint32_t address) { diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 366f2510f..aa5942ad8 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> nv_register_t ptimer_registers[] = { diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index 6709c92a2..db6e78a59 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> nv_register_t pvideo_registers[] = { diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index c26df9b40..5732ec144 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -19,14 +19,14 @@ #include #include #include -#include <86Box/86box.h> -#include <86Box/device.h> -#include <86Box/mem.h> +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> #include <86box/pci.h> -#include <86Box/rom.h> // DEPENDENT!!! -#include <86Box/video.h> -#include <86Box/nv/vid_nv.h> -#include <86Box/nv/vid_nv3.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> // PIO Method Submission diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index af17bd3a7..420d209b4 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -21,11 +21,11 @@ #include #include #include -#include <86Box/86box.h> +#include <86box/86box.h> #ifndef RELEASE_BUILD -#include <86Box/device.h> +#include <86box/device.h> #endif -#include <86Box/log.h> +#include <86box/log.h> // Common logging From f8c2c604d8f639ef82eb675e634ea23d860c9217 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 14 Feb 2025 00:38:42 +0000 Subject: [PATCH 094/274] Start working on the notifier engine and fix thecontext selection for cache1 object submission. --- .../nv3 driver init status_2025-02-10.txt | 8 +++---- .../86box/nv/classes/vid_nv3_classes.h | 24 +++++++++++++++---- src/include/86box/nv/vid_nv3.h | 21 +++++++++++++++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 14 ++++++----- src/video/nv/nv3/subsystems/nv3_user.c | 7 +++++- 5 files changed, 58 insertions(+), 16 deletions(-) diff --git a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt index c76e79743..24137f334 100644 --- a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt +++ b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt @@ -66,10 +66,10 @@ DrvEnableSurface RmLoadState SUCCESS 01:53 10/02/2025 NV3EnableCursor SUCCESS 01:54 10/02/2025 NV3WaitUntilFinished SUCCESS Passing 02:23 10/02/2025 - EngDeviceIoControl IOCTL 0x230408 - EngDeviceIoControl IOCTL 0x232024 - NvAllocHardware - bCreateStdPatches(?) + EngDeviceIoControl IOCTL 0x230408 SUCCESS 02:26 10/02/2025 + EngDeviceIoControl IOCTL 0x232024 SUCCESS 02:26 10/02/2025 + NvAllocHardware SUCCESS 02:29 10/02/2025 + bCreateStdPatches(?) FAILURE 02:31 10/02/2025 CHECK - NV4 vDestroyStdPatches(?) NV3_WaitForOneVerticalRefresh diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index aa23d29dc..019b04ea4 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1038,17 +1038,33 @@ typedef struct nv3_object_class_017 nv3_d3d5_alpha_control_t alpha_control; uint8_t reserved3[0xCE4]; - nv3_d3d5_coordinate_t coordinate_points[128]; // The points wer are rendering. + nv3_d3d5_coordinate_t coordinate_points[128]; // The points we are rendering. /* No placeholder needed, it really is that long. */ } nv3_d3d5_accelerated_triangle_with_zeta_buffer_t; -/* 0x19, 0x1A, 0x1B don't exist */ + +// Color and Zeta Buffer algorithm +typedef struct nv3_zeta_buffer_s +{ + nv3_color_argb_32_t color; + uint32_t zeta; // 16 bits z, 8 bits stenciul +} nv3_zeta_buffer_t; typedef struct nv3_object_class_018 -{ - +{ + nv3_class_ctx_switch_method_t set_notify_ctx_dma; + uint8_t reserved[0x100]; + uint32_t set_notify; + uint8_t reserved2[0x1FC]; + nv3_d3d5_control_out_t control_out; + nv3_d3d5_alpha_control_t alpha_control; + uint8_t reserved3[0x4F0]; + nv3_position_16_t point; + nv3_zeta_buffer_t zeta[8]; } nv3_point_with_zeta_buffer_t; +/* 0x19, 0x1A, 0x1B don't exist */ + /* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? They are making it look like a bitfield but it's hex? diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 72d6d5a3d..98e60ee72 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 5 February 2025 (STILL WORKING ON IT!!!) + * Last updated: 13 February 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -869,6 +869,25 @@ typedef struct nv3_pfb_s uint32_t rtl; // Part of the memory timings } nv3_pfb_t; +// +// DMA & Notifier Engine +// + +// Not a notification status, because it's a 16-bit enum +// C23 fixes this +#define NV3_NOTIFICATION_STATUS_DONE_OK 0x0 +#define NV3_NOTIFICATION_STATUS_IN_PROGRESS 0xFF +#define NV3_NOTIFICATION_STATUS_ERROR 0x100 + +// Core notification structure +typedef struct nv3_notification_s +{ + uint64_t nanoseconds; + uint32_t info32; + uint16_t info16; + uint16_t status; +} nv3_notification_t; + #define NV3_RMA_NUM_REGS 4 // Access the GPU from real-mode typedef struct nv3_pbus_rma_s diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 4a62c8cf5..6e7a4c453 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -504,10 +504,9 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) // shift right until we have our normla number again while (mask) { - // NT4 drivers v1.29 - mask >>= 1; + // NT4 drivers v1.29 do this the other way around?? val ^= mask; - + mask >>= 1; } return val; @@ -588,7 +587,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) // Up to 128 per envytools? uint32_t channel = (addr >> NV3_OBJECT_SUBMIT_CHANNEL) & 0x7F; - uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & 0x07; + uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & (NV3_DMA_CHANNELS - 1); // first make sure there is even any cache available if (!nv3->pfifo.cache1_settings.access_enabled) @@ -661,6 +660,9 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address); + nv_log("Submitted object [PIO]: Channel %d, Subchannel %d, Method ID 0x%04x (Put Address is now %d)\n", + channel, subchannel, method_offset, nv3->pfifo.cache1_settings.put_address); + // Now we're done. Phew! } @@ -689,7 +691,7 @@ void nv3_pfifo_cache1_pull() return; // interrupt was fired, and we went to ramro } - uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries? + uint32_t current_context = nv3->pfifo.cache0_settings.context[current_subchannel]; // only 1 entry for CACHE0 so basically ignore the other context entries? // Tell the CPU if we found a software method if (current_context & 0x800000) @@ -711,7 +713,7 @@ void nv3_pfifo_cache1_pull() nv3->pfifo.cache0_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; #ifndef RELEASE_BUILD - nv_log("***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE1 PULLED ****** Contextual information below\n"); + nv_log("***** OBJECT PULLED, SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - ****** Contextual information below\n"); nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); #endif diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index 5732ec144..4361abcd0 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -37,7 +37,12 @@ uint32_t nv3_user_read(uint32_t address) //todo: print out the subchannel uint8_t method_offset = (address & 0x1FFC); - nv_log("User Submission Area PIO Subchannel method_offset=0x%04x\n (Trying to read...)", method_offset); +#ifndef RELEASE_BUILD + uint8_t channel = (address - NV3_USER_START) / 0x10000; + uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL; + + nv_log("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset); +#endif // 0x10 is free CACHE1 object // TODO: THERE ARE OTHER STUFF! From 0cf469f75b7ff18dc0bccbf988c4221ac1f009cc Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 14 Feb 2025 01:38:06 +0000 Subject: [PATCH 095/274] Fix put addresses --- src/include/86box/nv/vid_nv3.h | 20 ++++++-- .../nv/nv3/classes/nv3_class_shared_methods.c | 5 ++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 49 ++++++++++--------- src/video/nv/nv3/subsystems/nv3_pgraph.c | 11 ++++- src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- 5 files changed, 58 insertions(+), 29 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 98e60ee72..7b037c41c 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -618,6 +618,17 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_CLASS1C_MEM2IMAGE_START 0x5C0000 // class 55, 56, 62, 63? #define NV3_PGRAPH_CLASS1C_MEM2IMAGE_END 0x5C1FFF +/* + OBJECT METHODS +*/ + +// Global stuff +#define NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE 0x0 // I'm going insane at 00:48 14/02/2025 +#define NV3_SET_NOTIFY_CONTEXT_FOR_DMA 0x100 // Set object ctx for dma...see nv3_dma_context_t structure +#define NV3_SET_NOTIFY 0x104 + +#define NV3_W95TXT_COLORA 0x3FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. + #define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers #define NV3_PGRAPH_REAL_END 0x5C1FFF @@ -724,9 +735,6 @@ extern const device_config_t nv3_config[]; // not done -// Master Control - - // CRTC/CIO (0x3b0-0x3df) #define NV3_CRTC_DATA_OUT 0x3C0 @@ -810,6 +818,8 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F + + /* STRUCTURES FOR THE GPU START HERE OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H @@ -1358,9 +1368,9 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); / // RAMIN functions uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel); -bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_id, uint32_t subchannel_id); +bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel_id, uint8_t subchannel_id); #ifndef RELEASE_BUILD -void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context); +void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context); #endif uint32_t nv3_ramfc_read(uint32_t address); diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index dd6c49fed..39f7e2b81 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -32,4 +32,9 @@ void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj) { +} + +void nv3_notify() +{ + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 6e7a4c453..a6252f3b7 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -500,13 +500,13 @@ Back to sanity uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) { uint32_t mask = val >> 1; - + // shift right until we have our normla number again while (mask) { - // NT4 drivers v1.29 do this the other way around?? - val ^= mask; + // Algorithm from NT4 drivers, version 1.29 mask >>= 1; + val ^= mask; } return val; @@ -530,11 +530,11 @@ void nv3_pfifo_cache0_pull() return; // There is only one entry for cache0 - uint16_t current_channel = nv3->pfifo.cache0_settings.channel; - uint32_t current_subchannel = nv3->pfifo.cache0_entry.subchannel; + uint8_t current_channel = nv3->pfifo.cache0_settings.channel; + uint8_t current_subchannel = nv3->pfifo.cache0_entry.subchannel; uint32_t current_name = nv3->pfifo.cache0_entry.data; - uint32_t current_method = nv3->pfifo.cache0_entry.method; - + uint16_t current_method = nv3->pfifo.cache0_entry.method; + // i.e. there is no method in cache0, so we have to find the object. if (!current_method) { @@ -543,6 +543,7 @@ void nv3_pfifo_cache0_pull() } uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries? + uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; // Tell the CPU if we found a software method if (current_context & 0x800000) @@ -594,6 +595,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) { oh_shit = true; oh_shit_reason = nv3_runout_reason_no_cache_available; + new_address |= (nv3_runout_reason_no_cache_available << NV3_PFIFO_RUNOUT_RAMIN_ERR); + } // Check if runout is full @@ -627,7 +630,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) { // Cache reassignment required if (!nv3->pfifo.cache_reassignment - || (nv3->pfifo.cache0_settings.get_address != nv3->pfifo.cache0_settings.get_address)) + || (nv3->pfifo.cache1_settings.get_address != nv3->pfifo.cache1_settings.get_address)) { oh_shit = true; oh_shit_reason = nv3_runout_reason_no_cache_available; @@ -654,13 +657,13 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1; if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# - next_put_address &= NV3_PFIFO_CACHE1_SIZE_REV_C; + next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); else - next_put_address &= NV3_PFIFO_CACHE1_SIZE_REV_AB; + next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); - nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address); + nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; - nv_log("Submitted object [PIO]: Channel %d, Subchannel %d, Method ID 0x%04x (Put Address is now %d)\n", + nv_log("Submitted object [PIO]: Channel %d.%d, Method ID 0x%04x (Put Address is now %d)\n", channel, subchannel, method_offset, nv3->pfifo.cache1_settings.put_address); // Now we're done. Phew! @@ -679,25 +682,27 @@ void nv3_pfifo_cache1_pull() uint32_t get_address = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably - uint16_t current_channel = nv3->pfifo.cache1_settings.channel; - uint32_t current_subchannel = nv3->pfifo.cache1_entries[get_address].subchannel; + uint8_t current_channel = nv3->pfifo.cache1_settings.channel; + uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_address].subchannel; uint32_t current_name = nv3->pfifo.cache1_entries[get_address].data; - uint32_t current_method = nv3->pfifo.cache1_entries[get_address].method; + uint16_t current_method = nv3->pfifo.cache1_entries[get_address].method; - // i.e. there is no method in cache0, so we have to find the object. + // i.e. there is no method in cache1, so we have to find the object. if (!current_method) { if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) return; // interrupt was fired, and we went to ramro } - uint32_t current_context = nv3->pfifo.cache0_settings.context[current_subchannel]; // only 1 entry for CACHE0 so basically ignore the other context entries? + uint32_t current_context = nv3->pfifo.cache1_settings.context[current_subchannel]; // get the current subchannel + + uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; // Tell the CPU if we found a software method if (current_context & 0x800000) { - nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); } @@ -705,12 +710,12 @@ void nv3_pfifo_cache1_pull() uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_address) + 1; if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# - next_get_address &= NV3_PFIFO_CACHE1_SIZE_REV_C; + next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); else - next_get_address &= NV3_PFIFO_CACHE1_SIZE_REV_AB; + next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); // Is this needed? - nv3->pfifo.cache0_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; + nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; #ifndef RELEASE_BUILD nv_log("***** OBJECT PULLED, SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - ****** Contextual information below\n"); diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 85ad21cff..212980c8a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -468,7 +468,16 @@ void nv3_pgraph_vblank_start(svga_t* svga) nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_EN_0_VBLANK); } -void nv3_pgraph_submit() +/* Arbitrates graphics object submission to the right object types */ +void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context) { + // class id can be derived from the context but we debug log it before we get here + switch (method) + { + // This method is how we figure out which methods exist. + case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: + nv_log("Hi, I'm an NV []"); + break; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 8dcba1b54..18538cd91 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -347,7 +347,7 @@ bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) } // THIS IS THE MOST IMPORTANT FUNCTION! -bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel, uint32_t subchannel) +bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, uint8_t subchannel) { // TODO: WRITE IT!!! // Set the number of entries to search based on the ramht size (2*(size+1)) From 8cf57fdc14a779f0defc3d16faa944463bb9f13d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 21 Feb 2025 22:57:04 +0000 Subject: [PATCH 096/274] hash lookup fixes --- .../nv3 driver init status_2025-02-10.txt | 26 ++++++---------- src/include/86box/nv/vid_nv3.h | 2 ++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 12 +++---- src/video/nv/nv3/subsystems/nv3_pgraph.c | 4 +-- src/video/nv/nv3/subsystems/nv3_pramin.c | 31 ++++++++++++++----- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 4 +-- 6 files changed, 46 insertions(+), 33 deletions(-) diff --git a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt index 24137f334..b5643a2ea 100644 --- a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt +++ b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt @@ -46,7 +46,7 @@ DrvEnablePDEV SUCCESS 23:28 09/02/2025 EngDeviceIoControl IOCTL 0x232044 (CHECK mini) SUCCESS (eax=0) DrvCompletePDEV SUCCESS 23:52 09/02/2025 DrvEnableSurface - bEnableHardware call + bEnableHardware call SUCCESS 22:36 13/02/2025 EngCreateSemaphore call #1 csCrtc SUCCESS 00:55 10/02/2025 EngCreateSemaphore call #2 csFifo SUCCESS 00:57 10/02/2025 EngDeviceIoControl IOCTL 0x230460 SUCCESS 00:57 10/02/2025 @@ -54,8 +54,8 @@ DrvEnableSurface NvAllocRoot SUCCESS 01:03 10/02/2025 NvAllocDevice SUCCESS 01:04 10/02/2025 NV3/NV4 architecture check SUCCESS 01:14 10/02/2025 - bAssertModeHardware call (bEnable=1) FAILURE - HANG/LOOP - EngDeviceIoControl IOCTL 0x23040C] FAILURE 01:27 10/02/2025 + bAssertModeHardware call (bEnable=1) SUCCESS Passing starting with build at 02:23 10/02/2025 + EngDeviceIoControl IOCTL 0x23040C] SUCCESS Passing starting with build at 02:23 10/02/2025 nv3_mini NVStartIO ioctlcode=0x23040C NVSetMode NV3SetMode SUCCESS 01:53 10/02/2025 @@ -65,19 +65,19 @@ DrvEnableSurface UpdateArbitrationSettings SUCCESS 01:52 10/02/2025 RmLoadState SUCCESS 01:53 10/02/2025 NV3EnableCursor SUCCESS 01:54 10/02/2025 - NV3WaitUntilFinished SUCCESS Passing 02:23 10/02/2025 + NV3WaitUntilFinished SUCCESS 02:23 10/02/2025 EngDeviceIoControl IOCTL 0x230408 SUCCESS 02:26 10/02/2025 EngDeviceIoControl IOCTL 0x232024 SUCCESS 02:26 10/02/2025 NvAllocHardware SUCCESS 02:29 10/02/2025 - bCreateStdPatches(?) FAILURE 02:31 10/02/2025 - CHECK - NV4 - vDestroyStdPatches(?) - NV3_WaitForOneVerticalRefresh - EngDeviceIoControl IOCTL 0x230410 + bCreateStdPatches(?) SUCCESS (EAX=1!!!) 22:24 13/02/2025 + CHECK - NV4 N/A + vDestroyStdPatches(?) N/A + NV3_WaitForOneVerticalRefresh SUCCESS + EngDeviceIoControl IOCTL 0x230410 SUCCESS SET UP CORRECT FUNCTION POINTERS - + Indirect call (call dword [edi]) to NV3_WaitWhileGraphicsEngineBusy HANG 22:14 16/02/2025 _heap_init call bEnableOffscreenHeap call bEnablePointer call @@ -87,10 +87,4 @@ DrvEnableSurface EngCreateBitmap call EngAssociateBitmap call - - - - DrvDisableSurface: ONLY IN THE CASE OF FAILURE - - diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 7b037c41c..58ca3b623 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1446,6 +1446,8 @@ void nv3_pgraph_init(); uint32_t nv3_pgraph_read(uint32_t address); void nv3_pgraph_write(uint32_t address, uint32_t value); void nv3_pgraph_vblank_start(svga_t* svga); +void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context); + // NV3 PFIFO void nv3_pfifo_init(); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index a6252f3b7..ca5694af3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -680,14 +680,14 @@ void nv3_pfifo_cache1_pull() if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) return; - uint32_t get_address = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably + uint32_t get_index = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably uint8_t current_channel = nv3->pfifo.cache1_settings.channel; - uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_address].subchannel; - uint32_t current_name = nv3->pfifo.cache1_entries[get_address].data; - uint16_t current_method = nv3->pfifo.cache1_entries[get_address].method; + uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_index].subchannel; + uint32_t current_name = nv3->pfifo.cache1_entries[get_index].data; + uint16_t current_method = nv3->pfifo.cache1_entries[get_index].method; - // i.e. there is no method in cache1, so we have to find the object. + // NV_ROOT if (!current_method) { if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) @@ -707,7 +707,7 @@ void nv3_pfifo_cache1_pull() } // start by incrementing - uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_address) + 1; + uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1; if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 212980c8a..1c5750596 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -449,7 +449,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // Addresses should be aligned to 4 bytes. uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); - nv_log("PGRAPH Context Cache Write (Entry=%04x Value=%04x)\n", entry, value); + nv_log("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value); nv3->pgraph.context_cache[entry] = value; } } @@ -477,7 +477,7 @@ void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t s { // This method is how we figure out which methods exist. case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("Hi, I'm an NV []"); + nv_log("Hi, I'm an NVidia object :)\n"); break; } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 18538cd91..e8452d870 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -352,13 +352,32 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // TODO: WRITE IT!!! // Set the number of entries to search based on the ramht size (2*(size+1)) // Not a switch statement in case newer gpus have larger ramins - uint32_t bucket_entries = 2 * (((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03) + 1); + + uint32_t bucket_entries = 2; + + switch (nv3->pfifo.ramht_config) + { + case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: + // stays as is + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: + bucket_entries = 4; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: + bucket_entries = 8; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: + bucket_entries = 16; + break; + + } // Calculate the address in the hashtable uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; - uint32_t ramht_cur_address = ramht_base; + uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel)) * bucket_entries * 8; - nv_log("Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel, subchannel); + nv_log("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n", + ramht_cur_address, name, cache_num, channel, subchannel); bool found_object = false; @@ -385,19 +404,17 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u if (!found_object) { + nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; + if (!cache_num) { - nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; - //It turns itself off on failure, the drivers turn it back on nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; } else { - nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE; - //It turns itself off on failure, the drivers turn it back on nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index e56dd5c3a..00ef8e046 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -35,11 +35,11 @@ It is used to get the offset within RAMHT of a graphics object. uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) { // convert the name to an array of bytes - uint8_t* hash_bytes = (uint8_t*)name; + uint8_t* hash_bytes = (uint8_t*)&name; // is this the right endianness? uint32_t hash = (hash_bytes[0] ^ hash_bytes[1] ^ hash_bytes[2] ^ hash_bytes[3] ^ (uint8_t)channel); - nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, name, channel); + nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel); return hash; } From 71bdf8d081dd07629d3968b4a9aeaf487deb7385 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 26 Feb 2025 23:55:49 +0000 Subject: [PATCH 097/274] even more fixes to hash lookup --- src/include/86box/nv/vid_nv3.h | 4 +++- src/video/nv/nv3/subsystems/nv3_pbus.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 10 ++++++++- src/video/nv/nv3/subsystems/nv3_pramin.c | 22 ++++++++++--------- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 7 +++--- 5 files changed, 30 insertions(+), 17 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 58ca3b623..334c8f615 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 13 February 2025 (STILL WORKING ON IT!!!) + * Last updated: 26 February 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -41,6 +41,8 @@ extern const device_config_t nv3_config[]; #define NV3_DMA_CHANNELS 8 #define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8 +#define NV3_DMA_CHANNELS_TOTAL 0x7F // This is also used somewhere despite there only being 8*8 = 64 channels + #define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1 // The amount by which we have to ration out the memory clock because it's not fast enough... // Multiply by this value to get the real clock speed. #define NV3_LAST_VALID_GRAPHICS_OBJECT_ID 0x1F diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index c9fd0f3aa..2594e0739 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -127,8 +127,8 @@ void nv3_pbus_write(uint32_t address, uint32_t value) uint8_t nv3_pbus_rma_read(uint16_t addr) { addr &= 0xFF; - uint32_t real_final_address; - uint8_t ret; + uint32_t real_final_address = 0x0; + uint8_t ret = 0x0; switch (addr) { diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index ca5694af3..55b961c96 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -290,6 +290,11 @@ uint32_t nv3_pfifo_read(uint32_t address) return ret; } +void nv3_pfifo_trigger_dma_if_required() +{ + +} + void nv3_pfifo_write(uint32_t address, uint32_t value) { // before doing anything, check the subsystem enablement @@ -481,6 +486,9 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x", ctx_entry_id, value); } + + /* Trigger DMA for notifications if we need to */ + nv3_pfifo_trigger_dma_if_required(); } /* @@ -690,7 +698,7 @@ void nv3_pfifo_cache1_pull() // NV_ROOT if (!current_method) { - if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) + if (!nv3_ramin_find_object(current_name, 1, current_channel, current_subchannel)) return; // interrupt was fired, and we went to ramro } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index e8452d870..25f6b36e1 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -114,7 +114,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { val = vram_32bit[addr]; - nv_log("Read dword from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + nv_log("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr); } return val; @@ -134,7 +134,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) addr ^= (nv3->nvbase.svga.vram_max - 0x10); - uint32_t val32 = 0x00; + uint32_t val32 = (uint32_t)val; if (!nv3_ramin_arbitrate_write(addr, val32)) { @@ -160,7 +160,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 1; // what - uint32_t val32 = 0x00; + uint32_t val32 = (uint32_t)val; if (!nv3_ramin_arbitrate_write(addr, val32)) { @@ -186,9 +186,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 2; // what - uint32_t val32 = 0x00; - - if (!nv3_ramin_arbitrate_write(addr, val32)) + if (!nv3_ramin_arbitrate_write(addr, val)) { vram_32bit[addr] = val; nv_log("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); @@ -354,8 +352,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // Not a switch statement in case newer gpus have larger ramins uint32_t bucket_entries = 2; + uint8_t ramht_size = (nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03; - switch (nv3->pfifo.ramht_config) + switch (ramht_size) { case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: // stays as is @@ -374,7 +373,10 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // Calculate the address in the hashtable uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; - uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel)) * bucket_entries * 8; + + // This is certainly wrong. But the objects seem to be written to 4600? So I just multiply it by 80 to multiply the final address by 10. + // Why does this work? + uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel) * bucket_entries * 8); nv_log("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n", ramht_cur_address, name, cache_num, channel, subchannel); @@ -382,8 +384,8 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u bool found_object = false; // set up some variables - uint32_t found_obj_name; - nv3_ramin_context_t obj_context_struct; + uint32_t found_obj_name = 0x00; + nv3_ramin_context_t obj_context_struct = {0}; for (uint32_t bucket_entry = 0; bucket_entry < bucket_entries; bucket_entry++) { diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index 00ef8e046..e09f80e83 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -32,13 +32,14 @@ It is used to get the offset within RAMHT of a graphics object. */ + uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) { - // convert the name to an array of bytes - uint8_t* hash_bytes = (uint8_t*)&name; + // the official nvidia hash algorithm, tweaked for readability + uint32_t hash = ((name ^ (name >> 8) ^ (name >> 16) ^ (name >> 24)) & 0xFF) ^ (channel & NV3_DMA_CHANNELS_TOTAL); + // is this the right endianness? - uint32_t hash = (hash_bytes[0] ^ hash_bytes[1] ^ hash_bytes[2] ^ hash_bytes[3] ^ (uint8_t)channel); nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel); return hash; } From 15ebc48383aa8160d12c47417d96dc0968c0fd6e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 3 Mar 2025 01:27:50 +0000 Subject: [PATCH 098/274] Raise the correct cache error on DEBUG_0 if lookup fails --- src/video/nv/nv3/subsystems/nv3_pramin.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 25f6b36e1..ece982f0e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -406,16 +406,16 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u if (!found_object) { - nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; - if (!cache_num) { + nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; } else { + nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED; From c51127af08fddda10d44cf6f9fa0d5dd2f432365 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 5 Mar 2025 01:43:18 +0000 Subject: [PATCH 099/274] Fix context dirty state, start working on DMA and notifiers, fix target node. --- src/include/86box/nv/vid_nv3.h | 28 ++++--- src/video/nv/nv3/subsystems/nv3_pfifo.c | 98 +++++++++++++++--------- src/video/nv/nv3/subsystems/nv3_pramin.c | 12 +-- 3 files changed, 84 insertions(+), 54 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 334c8f615..34356c5ee 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -256,7 +256,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_RUNOUT_GET 0x2420 #define NV3_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 -#define NV3_PFIFO_RUNOUT_RAMIN_ERR 28 +#define NV3_PFIFO_RUNOUT_RAMIN_ERR 28 // bit to or with #define NV3_PFIFO_CACHE0_SIZE 1 // This is for software-injected notified only! #define NV3_PFIFO_CACHE1_SIZE_REV_AB 32 @@ -264,7 +264,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_PUSH_ACCESS 0x3000 +#define NV3_PFIFO_CACHE0_DMA_PUSH0 0x3000 #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 @@ -275,8 +275,8 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 #define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE 4 #define NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD 8 -#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY 0x3050 -#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY_BOOL 4 // 1=dirty 0=clean +#define NV3_PFIFO_CACHE0_PULLER_CTX_STATE 0x3050 +#define NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 #define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit // Current channel context - cache1 @@ -285,7 +285,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_METHOD 0x3100 #define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 -#define NV3_PFIFO_CACHE1_PUSH_ACCESS 0x3200 +#define NV3_PFIFO_CACHE1_DMA_PUSH0 0x3200 #define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 @@ -298,17 +298,21 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 #define NV3_PFIFO_CACHE1_DMA_CONFIG_2 0x3228 #define NV3_PFIFO_CACHE1_DMA_CONFIG_3 0x322C +#define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE 0 // The type of bus we are sending over +#define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_PCI 0x02 // The type of bus we are sending over +#define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_AGP 0x03 // The type of bus we are sending over + // Why does a gpu need its own translation lookaside buffer and pagetable format. Are they crazy #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 +#define NV3_PFIFO_CACHE1_PULL0 0x3240 //todo: merge stuff -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD 8 // 0=software, 1=hardware -#define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250 -#define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4 +#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware +#define NV3_PFIFO_CACHE1_PULLER_CTX_STATE 0x3250 +#define NV3_PFIFO_CACHE1_PULLER_CTX_STATE_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 #define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 @@ -920,7 +924,7 @@ typedef struct nv3_pbus_s typedef struct nv3_pfifo_cache_s { - bool access_enabled; // Can we even access this cache? + bool dma_push0; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. uint8_t channel; // The DMA channel ID of this cache. diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 55b961c96..00e11895d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -21,6 +21,7 @@ #include #include <86box/86box.h> #include <86box/device.h> +#include <86box/dma.h> #include <86box/mem.h> #include <86box/pci.h> #include <86box/rom.h> // DEPENDENT!!! @@ -43,27 +44,27 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, { NV3_PFIFO_CACHE_REASSIGNMENT, "PFIFO - Allow Cache Channel Reassignment", NULL, NULL }, { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller Control", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller Control"}, - { NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller State0", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULLER_STATE1, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE0_PUSH_ACCESS, "PFIFO - Cache0 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE1_PUSH_ACCESS, "PFIFO - Cache1 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller Control"}, + { NV3_PFIFO_CACHE0_PULLER_CTX_STATE, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULLER_CTX_STATE, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, + { NV3_PFIFO_CACHE0_DMA_PUSH0, "PFIFO - Cache0 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_DMA_PUSH0, "PFIFO - Cache1 Access", NULL, NULL, }, { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 DMA Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 DMA Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, - { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, - { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, - { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, - { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, + { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get", NULL, NULL }, + { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get", NULL, NULL }, + { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put", NULL, NULL }, + { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put", NULL, NULL }, //Cache1 exclusive stuff { NV3_PFIFO_CACHE1_DMA_CONFIG_0, "PFIFO - Cache1 DMA Config0"}, { NV3_PFIFO_CACHE1_DMA_CONFIG_1, "PFIFO - Cache1 DMA Config1"}, { NV3_PFIFO_CACHE1_DMA_CONFIG_2, "PFIFO - Cache1 DMA Config2"}, { NV3_PFIFO_CACHE1_DMA_CONFIG_3, "PFIFO - Cache1 DMA Config3"}, - { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status - PROBABLY TRIGGERING DMA"}, { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA Translation Lookaside Buffer - Pagetable Base"}, { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA Status"}, { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA Status"}, @@ -147,20 +148,20 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE0_PULLER_CONTROL: ret = nv3->pfifo.cache0_settings.puller_control; break; - case NV3_PFIFO_CACHE1_PULLER_CONTROL: + case NV3_PFIFO_CACHE1_PULL0: ret = nv3->pfifo.cache1_settings.puller_control; break; - case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: - ret = nv3->pfifo.cache0_settings.context_is_dirty; + case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: + ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; break; - case NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY: - ret = nv3->pfifo.cache1_settings.context_is_dirty; + case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: + ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; break; - case NV3_PFIFO_CACHE0_PUSH_ACCESS: - ret = nv3->pfifo.cache0_settings.access_enabled; + case NV3_PFIFO_CACHE0_DMA_PUSH0: + ret = nv3->pfifo.cache0_settings.dma_push0; break; - case NV3_PFIFO_CACHE1_PUSH_ACCESS: - ret = nv3->pfifo.cache1_settings.access_enabled; + case NV3_PFIFO_CACHE1_DMA_PUSH0: + ret = nv3->pfifo.cache1_settings.dma_push0; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: ret = nv3->pfifo.cache0_settings.channel; @@ -219,7 +220,10 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = nv3->pfifo.cache1_settings.dma_address; break; case NV3_PFIFO_CACHE1_DMA_CONFIG_3: - ret = nv3->pfifo.cache1_settings.dma_target_node; + if (nv3->nvbase.bus_generation == nv_bus_pci) + return NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_PCI; + else + return NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_AGP; break; case NV3_PFIFO_CACHE1_DMA_STATUS: ret = nv3->pfifo.cache1_settings.dma_status; @@ -292,7 +296,32 @@ uint32_t nv3_pfifo_read(uint32_t address) void nv3_pfifo_trigger_dma_if_required() { + // Not a thing for cache0 + + bool cache1_dma = false; + /* Check that DMA is enabled */ + if (nv3->pfifo.cache1_settings.dma_state + && nv3->pfifo.cache1_settings.dma_enabled) + { + uint32_t bytes_to_send = nv3->pfifo.cache1_settings.dma_length; + uint32_t where_to_send = nv3->pfifo.cache1_settings.dma_address; + uint32_t target_node = nv3->pfifo.cache1_settings.dma_target_node; //2=pci, 3=agp. What does this even do + + /* Pagetable information */ + uint32_t tlb_pt_base = nv3->pfifo.cache1_settings.dma_tlb_pt_base; + uint32_t tlb_pt_entry = nv3->pfifo.cache1_settings.dma_tlb_pte; + uint32_t tlb_pt_tag = nv3->pfifo.cache1_settings.dma_tlb_tag; // 0xFFFFFFFF usually? + + /* PUSH - System to GPU (?) */ + if (nv3->pfifo.cache1_settings.dma_push0) + { + + } + + /* PULL - GPU to System */ + nv_log("Initiating NV to System DMA - Probably we are trying to notify"); + } } void nv3_pfifo_write(uint32_t address, uint32_t value) @@ -396,20 +425,20 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CACHE0_PULLER_CONTROL: nv3->pfifo.cache0_settings.puller_control = value; // 8bits meaningful break; - case NV3_PFIFO_CACHE1_PULLER_CONTROL: + case NV3_PFIFO_CACHE1_PULL0: nv3->pfifo.cache1_settings.puller_control = value; // 8bits meaningful break; - case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: - nv3->pfifo.cache0_settings.context_is_dirty = value; + case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: + nv3->pfifo.cache0_settings.context_is_dirty = (value >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; - case NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY: - nv3->pfifo.cache1_settings.context_is_dirty = value; + case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: + nv3->pfifo.cache1_settings.context_is_dirty = (value >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; - case NV3_PFIFO_CACHE0_PUSH_ACCESS: - nv3->pfifo.cache0_settings.access_enabled = value; + case NV3_PFIFO_CACHE0_DMA_PUSH0: + nv3->pfifo.cache0_settings.dma_push0 = value; break; - case NV3_PFIFO_CACHE1_PUSH_ACCESS: - nv3->pfifo.cache1_settings.access_enabled = value; + case NV3_PFIFO_CACHE1_DMA_PUSH0: + nv3->pfifo.cache1_settings.dma_push0 = value; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: nv3->pfifo.cache0_settings.channel = value; @@ -435,9 +464,6 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) case NV3_PFIFO_CACHE1_DMA_CONFIG_2: nv3->pfifo.cache1_settings.dma_address = value; break; - case NV3_PFIFO_CACHE1_DMA_CONFIG_3: - nv3->pfifo.cache1_settings.dma_target_node = value; - break; case NV3_PFIFO_CACHE1_DMA_STATUS: nv3->pfifo.cache1_settings.dma_status = value; break; @@ -484,7 +510,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; nv3->pfifo.cache1_settings.context[ctx_entry_id] = value; - nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x", ctx_entry_id, value); + nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, value); } /* Trigger DMA for notifications if we need to */ @@ -599,7 +625,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & (NV3_DMA_CHANNELS - 1); // first make sure there is even any cache available - if (!nv3->pfifo.cache1_settings.access_enabled) + if (!nv3->pfifo.cache1_settings.dma_push0) { oh_shit = true; oh_shit_reason = nv3_runout_reason_no_cache_available; @@ -681,7 +707,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) void nv3_pfifo_cache1_pull() { // Do nothing if PFIFO CACHE1 is disabled - if (!nv3->pfifo.cache1_settings.puller_control & (1 >> NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED)) + if (!nv3->pfifo.cache1_settings.puller_control & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) return; // Do nothing if there is nothing in cache1 to pull diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index ece982f0e..b04d261ee 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -416,9 +416,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u else { nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; - nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE; + nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; } nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); @@ -454,7 +454,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u if (!cache_num) nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; else - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE; + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; // Caches store all the subchannels for our current dma channel and basically get stale every context switch // Also we have to check that a osftware object didn't end up in here... @@ -476,8 +476,8 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u } else { - nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; } // It's an error but it isn't lol @@ -490,7 +490,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u if (!cache_num) nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; else - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; } // Ok we found it. Lol From a3e41c611e5f4194e48856650263351362dc83d1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 10 Mar 2025 17:58:17 +0000 Subject: [PATCH 100/274] fix parameter names --- doc/nvidia_notes/NV3 DMA Engine.txt | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 49 ++++++++++++++++++++++--- 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt index 50d34cfa9..282868503 100644 --- a/doc/nvidia_notes/NV3 DMA Engine.txt +++ b/doc/nvidia_notes/NV3 DMA Engine.txt @@ -23,7 +23,7 @@ CACHE1_DMA3 - Bus address space (Area BAR0 mapped to? Or bar1?) TO START: To set up DMA for for Cache1 Puller: CACHE1_PULL0 -> 1, changes to 0 when done -To set up DMA Cache1 Push: CACHE1_PULL0 -> 1, changes to 0 when done +To set up DMA Cache1 Push: CACHE1_PUsh0 -> 1, changes to 0 when done Set CACHES to 1 GO: Set DMA0 to 1 diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 00e11895d..e78c766b4 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -610,7 +610,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel) // NV_USER writes go here! // Pushes graphics objects into cache1 -void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) +void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) { bool oh_shit = false; // RAMRO needed nv3_ramin_ramro_reason oh_shit_reason = 0x00; // It's all good for now @@ -648,7 +648,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR); } - // 0x0 is used for the context + // 0x0 is used for creating the object. if (method_offset > 0 && method_offset < 0x100) { // Reserved NVIDIA Objects @@ -685,7 +685,46 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) uint32_t current_put_address = nv3->pfifo.cache1_settings.put_address >> 2; nv3->pfifo.cache1_entries[current_put_address].subchannel = subchannel; nv3->pfifo.cache1_entries[current_put_address].method = method_offset; - nv3->pfifo.cache1_entries[current_put_address].data = val; + nv3->pfifo.cache1_entries[current_put_address].data = object_name; + + /* + // I think we have to do this on PIO submission. Maybe not? + uint32_t hash = nv3_ramht_hash(object_name, channel); + uint32_t bucket_entries = 2; + uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; + + uint8_t ramht_size = (nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03; + + switch (ramht_size) + { + case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: + // stays as is + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: + bucket_entries = 4; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: + bucket_entries = 8; + break; + case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: + bucket_entries = 16; + break; + + } + + uint32_t ramin_address = ramht_base + hash * bucket_entries * 8; + + if (method_offset == 0) + { + nv3_ramin_write32(ramin_address, object_name, nv3); + nv3_ramin_write32(ramin_address + 0x04, nv3->pfifo.cache1_settings.context[subchannel], nv3); + } + else + { + // MAYBE + nv3_ramin_write32(ramin_address + method_offset, object_name, nv3); + } +*/ // now we have to recalculate the cache1 put address uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1; @@ -697,8 +736,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val) nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; - nv_log("Submitted object [PIO]: Channel %d.%d, Method ID 0x%04x (Put Address is now %d)\n", - channel, subchannel, method_offset, nv3->pfifo.cache1_settings.put_address); + nv_log("Submitted object [PIO]: Channel %d.%d, Object Name 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", + channel, subchannel, object_name, method_offset, nv3->pfifo.cache1_settings.put_address); // Now we're done. Phew! } From 0568028730d853f761f7b1c7499dbd4908da98ad Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 10 Mar 2025 21:19:26 +0000 Subject: [PATCH 101/274] get rid of stupid bad code that had no understanding of dma --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 39 ------------------------- 1 file changed, 39 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index e78c766b4..1ffb1023c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -687,45 +687,6 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) nv3->pfifo.cache1_entries[current_put_address].method = method_offset; nv3->pfifo.cache1_entries[current_put_address].data = object_name; - /* - // I think we have to do this on PIO submission. Maybe not? - uint32_t hash = nv3_ramht_hash(object_name, channel); - uint32_t bucket_entries = 2; - uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; - - uint8_t ramht_size = (nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03; - - switch (ramht_size) - { - case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: - // stays as is - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: - bucket_entries = 4; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: - bucket_entries = 8; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: - bucket_entries = 16; - break; - - } - - uint32_t ramin_address = ramht_base + hash * bucket_entries * 8; - - if (method_offset == 0) - { - nv3_ramin_write32(ramin_address, object_name, nv3); - nv3_ramin_write32(ramin_address + 0x04, nv3->pfifo.cache1_settings.context[subchannel], nv3); - } - else - { - // MAYBE - nv3_ramin_write32(ramin_address + method_offset, object_name, nv3); - } -*/ - // now we have to recalculate the cache1 put address uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1; From 363b2c2f4d9fa240cb09b49f386e2a2fc8c6ad88 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 01:12:41 +0000 Subject: [PATCH 102/274] I don't even know why using a lookup table fixes the object submission to be honest but the objects its submitting alos look completely screwed up --- doc/nvidia_notes/NV3 DMA Engine.txt | 16 +++++++++++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 38 ++++++++++++++++++------- 2 files changed, 43 insertions(+), 11 deletions(-) diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt index 282868503..6cae9d131 100644 --- a/doc/nvidia_notes/NV3 DMA Engine.txt +++ b/doc/nvidia_notes/NV3 DMA Engine.txt @@ -27,3 +27,19 @@ To set up DMA Cache1 Push: CACHE1_PUsh0 -> 1, changes to 0 when done Set CACHES to 1 GO: Set DMA0 to 1 + +***** Implementation in Driver ****** + +You can dma to "localvidmem:", "sysvidmem:" or "sysmem:", this is represented by a driver + +CAUSE OF FAILURE: +the pfifo is never free because it never processes the submitted objects +which means that the FIFO is never free +which means that the drivers spin forever waiting for the fifo to be free + +DMA_OBJECT STRUCTURE IN RESOURCE MANAGER: +0x328: Valid +0x34c: base address? +0x374: actually do the transfer + + diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 1ffb1023c..0037d3e01 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -517,15 +517,33 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv3_pfifo_trigger_dma_if_required(); } + /* https://en.wikipedia.org/wiki/Gray_code WHY?????? IT'S NOT A TELEGRAPH IT'S A GPU????? Convert from a normal number to a total insanity number which is only used in PFIFO CACHE1 for ungodly and totally unknowable reasons + +I decided to use a lookup table to save everyone's time, also the numbers generated from the function +that existed here before didn't make any sense */ + +#define NV3_GRAY_TABLE_NUM_ENTRIES 64 + +uint8_t nv3_pfifo_cache1_gray_code_table[NV3_GRAY_TABLE_NUM_ENTRIES] = { + 0b000000, 0b000001, 0b000011, 0b000010, 0b000110, 0b000111, 0b000101, 0b000100, + 0b001100, 0b001101, 0b001111, 0b001110, 0b001010, 0b001011, 0b001001, 0b001000, + 0b011000, 0b011001, 0b011011, 0b011010, 0b011110, 0b011111, 0b011101, 0b011100, + 0b010100, 0b010101, 0b010111, 0b010110, 0b010010, 0b010011, 0b010001, 0b010000, + 0b110000, 0b110001, 0b110011, 0b110010, 0b110110, 0b110111, 0b110101, 0b110100, + 0b111100, 0b111101, 0b111111, 0b111110, 0b111010, 0b111011, 0b111001, 0b111000, + 0b101000, 0b101001, 0b101011, 0b101010, 0b101110, 0b101111, 0b101101, 0b101100, + 0b100100, 0b100101, 0b100111, 0b100110, 0b100010, 0b100011, 0b100001, 0b100000 +}; + uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val) { - return (val) ^ (val >> 1); + return nv3_pfifo_cache1_gray_code_table[val]; } /* @@ -533,17 +551,14 @@ Back to sanity */ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) { - uint32_t mask = val >> 1; - - // shift right until we have our normla number again - while (mask) + /* Is this a good idea? */ + for (uint32_t i = 0; i < NV3_GRAY_TABLE_NUM_ENTRIES; i++) { - // Algorithm from NT4 drivers, version 1.29 - mask >>= 1; - val ^= mask; + if (nv3_pfifo_cache1_gray_code_table[i] == val) + return i; } - return val; + return 0x00; } // Submits graphics objects INTO cache0 @@ -688,7 +703,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) nv3->pfifo.cache1_entries[current_put_address].data = object_name; // now we have to recalculate the cache1 put address - uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1; + uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address); + next_put_address++; if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); @@ -754,7 +770,7 @@ void nv3_pfifo_cache1_pull() #ifndef RELEASE_BUILD nv_log("***** OBJECT PULLED, SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - ****** Contextual information below\n"); - nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); + nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)¤t_context); #endif //Todo: finish it From 4fdb522792218009198555f4d6538f6d30d4ff14 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 02:02:33 +0000 Subject: [PATCH 103/274] Implement put/get registers. Also, bit numbering is hard. --- src/include/86box/nv/vid_nv3.h | 13 ++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 104 ++++++++++++++--------- src/video/nv/nv3/subsystems/nv3_pramin.c | 14 +-- 3 files changed, 76 insertions(+), 55 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 34356c5ee..56eae4dfa 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 26 February 2025 (STILL WORKING ON IT!!!) + * Last updated: 11 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -977,7 +977,7 @@ typedef struct nv3_pfifo_s uint32_t runout_get; // 8:3 if RAMRO=512b, otherwise 12:3 // Cache stuff - uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0? + uint32_t cache_reassignment; // Allow context switching nv3_pfifo_cache_t cache0_settings; nv3_pfifo_cache_t cache1_settings; @@ -1213,13 +1213,12 @@ typedef struct nv3_ramin_context_s struct { - bool reserved : 1; - uint8_t channel : 7; - bool is_rendering : 1; - uint8_t class_id : 7; uint16_t ramin_offset; + uint8_t class_id : 7; + bool is_rendering : 1; + uint8_t channel : 7; + bool reserved : 1; }; - }; } nv3_ramin_context_t; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 0037d3e01..273e0a2e3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -201,8 +201,17 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = ((nv3->pfifo.cache1_settings.method_subchannel << 13) & 0x07) | ((nv3->pfifo.cache1_settings.method_address << 2) & 0x7FF); break; + case NV3_PFIFO_CACHE0_PUT: + ret = nv3->pfifo.cache0_settings.put_address; + break; case NV3_PFIFO_CACHE0_GET: - //wa + ret = nv3->pfifo.cache0_settings.get_address; + break; + case NV3_PFIFO_CACHE1_PUT: + ret = nv3->pfifo.cache1_settings.put_address; + break; + case NV3_PFIFO_CACHE1_GET: + ret = nv3->pfifo.cache1_settings.get_address; break; // Reassignment case NV3_PFIFO_CACHE_REASSIGNMENT: @@ -324,7 +333,7 @@ void nv3_pfifo_trigger_dma_if_required() } } -void nv3_pfifo_write(uint32_t address, uint32_t value) +void nv3_pfifo_write(uint32_t address, uint32_t val) { // before doing anything, check the subsystem enablement @@ -337,14 +346,14 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - nv_log("PFIFO Write 0x%08x -> 0x%08x", value, address); + nv_log("PFIFO Write 0x%08x -> 0x%08x", val, address); // if the register actually exists if (reg) { // on-read function if (reg->on_write) - reg->on_write(value); + reg->on_write(val); else { switch (reg->address) @@ -356,7 +365,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) // Bit 12 - DMA Pusher // Bit 16 - DMA Page Table Entry (pagefault?) case NV3_PFIFO_INTR: - nv3->pfifo.interrupt_status &= ~value; + nv3->pfifo.interrupt_status &= ~val; nv3_pmc_clear_interrupts(); // update the internal cache error state @@ -364,21 +373,21 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) nv3->pfifo.debug_0 &= ~NV3_PFIFO_INTR_CACHE_ERROR; break; case NV3_PFIFO_INTR_EN: - nv3->pfifo.interrupt_enable = value & 0x00011111; + nv3->pfifo.interrupt_enable = val & 0x00011111; nv3_pmc_handle_interrupts(true); break; case NV3_PFIFO_DELAY_0: - nv3->pfifo.dma_delay_retry = value; + nv3->pfifo.dma_delay_retry = val; break; case NV3_PFIFO_CONFIG_0: - nv3->pfifo.config_0 = value; + nv3->pfifo.config_0 = val; break; case NV3_PFIFO_CONFIG_RAMHT: - nv3->pfifo.ramht_config = value; + nv3->pfifo.ramht_config = val; // This code sucks a bit fix it later #ifdef ENABLE_NV_LOG - uint32_t new_size_ramht = ((value >> 16) & 0x03); + uint32_t new_size_ramht = ((val >> 16) & 0x03); if (new_size_ramht == 0) new_size_ramht = 0x1000; @@ -395,15 +404,15 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) #endif break; case NV3_PFIFO_CONFIG_RAMFC: - nv3->pfifo.ramfc_config = value; + nv3->pfifo.ramfc_config = val; nv_log("RAMFC Reconfiguration\n" "Base Address in RAMIN: %d\n", ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9); break; case NV3_PFIFO_CONFIG_RAMRO: - nv3->pfifo.ramro_config = value; + nv3->pfifo.ramro_config = val; - uint32_t new_size_ramro = ((value >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); + uint32_t new_size_ramro = ((val >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (new_size_ramro == 0) new_size_ramro = 0x200; @@ -415,86 +424,99 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) "Size: 0x%08x bytes\n", ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9, new_size_ramro); break; case NV3_PFIFO_DEBUG_0: - nv3->pfifo.debug_0 = value; + nv3->pfifo.debug_0 = val; break; // Reassignment case NV3_PFIFO_CACHE_REASSIGNMENT: - nv3->pfifo.cache_reassignment = value & 0x01; //1bit meaningful + nv3->pfifo.cache_reassignment = val & 0x01; //1bit meaningful break; // Control case NV3_PFIFO_CACHE0_PULLER_CONTROL: - nv3->pfifo.cache0_settings.puller_control = value; // 8bits meaningful + nv3->pfifo.cache0_settings.puller_control = val; // 8bits meaningful break; case NV3_PFIFO_CACHE1_PULL0: - nv3->pfifo.cache1_settings.puller_control = value; // 8bits meaningful + nv3->pfifo.cache1_settings.puller_control = val; // 8bits meaningful break; case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: - nv3->pfifo.cache0_settings.context_is_dirty = (value >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; + nv3->pfifo.cache0_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: - nv3->pfifo.cache1_settings.context_is_dirty = (value >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; + nv3->pfifo.cache1_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; case NV3_PFIFO_CACHE0_DMA_PUSH0: - nv3->pfifo.cache0_settings.dma_push0 = value; + nv3->pfifo.cache0_settings.dma_push0 = val; break; case NV3_PFIFO_CACHE1_DMA_PUSH0: - nv3->pfifo.cache1_settings.dma_push0 = value; + nv3->pfifo.cache1_settings.dma_push0 = val; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: - nv3->pfifo.cache0_settings.channel = value; + nv3->pfifo.cache0_settings.channel = val; break; case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: - nv3->pfifo.cache1_settings.channel = value; + nv3->pfifo.cache1_settings.channel = val; break; // CACHE0_STATUS and CACHE1_STATUS are not writable case NV3_PFIFO_CACHE0_METHOD: - nv3->pfifo.cache0_settings.method_subchannel = (value >> 13) & 0x07; - nv3->pfifo.cache0_settings.method_address = (value >> 2) & 0x7FF; + nv3->pfifo.cache0_settings.method_subchannel = (val >> 13) & 0x07; + nv3->pfifo.cache0_settings.method_address = (val >> 2) & 0x7FF; break; case NV3_PFIFO_CACHE1_METHOD: - nv3->pfifo.cache1_settings.method_subchannel = (value >> 13) & 0x07; - nv3->pfifo.cache1_settings.method_address = (value >> 2) & 0x7FF; + nv3->pfifo.cache1_settings.method_subchannel = (val >> 13) & 0x07; + nv3->pfifo.cache1_settings.method_address = (val >> 2) & 0x7FF; break; case NV3_PFIFO_CACHE1_DMA_CONFIG_0: - nv3->pfifo.cache1_settings.dma_state = value; + nv3->pfifo.cache1_settings.dma_state = val; break; case NV3_PFIFO_CACHE1_DMA_CONFIG_1: - nv3->pfifo.cache1_settings.dma_length = value; + nv3->pfifo.cache1_settings.dma_length = val; break; case NV3_PFIFO_CACHE1_DMA_CONFIG_2: - nv3->pfifo.cache1_settings.dma_address = value; + nv3->pfifo.cache1_settings.dma_address = val; break; case NV3_PFIFO_CACHE1_DMA_STATUS: - nv3->pfifo.cache1_settings.dma_status = value; + nv3->pfifo.cache1_settings.dma_status = val; break; case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: - nv3->pfifo.cache1_settings.dma_tlb_pt_base = value; + nv3->pfifo.cache1_settings.dma_tlb_pt_base = val; break; case NV3_PFIFO_CACHE1_DMA_TLB_PTE: - nv3->pfifo.cache1_settings.dma_tlb_pte = value; + nv3->pfifo.cache1_settings.dma_tlb_pte = val; break; case NV3_PFIFO_CACHE1_DMA_TLB_TAG: - nv3->pfifo.cache1_settings.dma_tlb_tag = value; + nv3->pfifo.cache1_settings.dma_tlb_tag = val; + break; + /* Put and Get addresses */ + case NV3_PFIFO_CACHE0_PUT: + nv3->pfifo.cache0_settings.put_address = val; + break; + case NV3_PFIFO_CACHE0_GET: + nv3->pfifo.cache0_settings.get_address = val; + break; + case NV3_PFIFO_CACHE1_PUT: + nv3->pfifo.cache1_settings.put_address = val; + break; + case NV3_PFIFO_CACHE1_GET: + nv3->pfifo.cache1_settings.get_address = val; break; case NV3_PFIFO_RUNOUT_GET: uint32_t size_get = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (size_get == 0) //512b - nv3->pfifo.runout_get = ((value & 0x3F) << 3); + nv3->pfifo.runout_get = ((val & 0x3F) << 3); else - nv3->pfifo.runout_get = ((value & 0x3FF) << 3); + nv3->pfifo.runout_get = ((val & 0x3FF) << 3); break; case NV3_PFIFO_RUNOUT_PUT: uint32_t size_put = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (size_put == 0) //512b - nv3->pfifo.runout_put = ((value & 0x3F) << 3); + nv3->pfifo.runout_put = ((val & 0x3F) << 3); else - nv3->pfifo.runout_put = ((value & 0x3FF) << 3); + nv3->pfifo.runout_put = ((val & 0x3FF) << 3); break; /* Cache1 is handled below */ case NV3_PFIFO_CACHE0_CTX: - nv3->pfifo.cache0_settings.context[0] = value; + nv3->pfifo.cache0_settings.context[0] = val; break; } } @@ -508,9 +530,9 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) { uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; - nv3->pfifo.cache1_settings.context[ctx_entry_id] = value; + nv3->pfifo.cache1_settings.context[ctx_entry_id] = val; - nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, value); + nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val); } /* Trigger DMA for notifications if we need to */ diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index b04d261ee..33799c39b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -502,15 +502,15 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // Prints out some informaiton about the object void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context) { - nv_log("Found object:"); - nv_log("Name: 0x%04x", name); + nv_log("Found object:\n"); + nv_log("Name: 0x%04x\n", name); - nv_log("Context:"); - nv_log("DMA Channel %d (0-7 valid)", context.channel); - nv_log("Class ID: as repreesnted in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)", context.class_id, + nv_log("Context:\n"); + nv_log("DMA Channel %d (0-7 valid)\n", context.channel); + nv_log("Class ID: as repreesnted in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)\n", context.class_id, context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); - nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)", context.is_rendering); - nv_log("PRAMIN Offset 0x%08x", context.ramin_offset << 4); + nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); + nv_log("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); } #endif \ No newline at end of file From 467c7124d369f1d5b4c2daad1ec1020931eba460 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 02:30:18 +0000 Subject: [PATCH 104/274] Direct CACHE0/CACHE1 Injection --- src/include/86box/nv/vid_nv3.h | 7 ++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 69 ++++++++++++++++++------ src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- 3 files changed, 58 insertions(+), 20 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 56eae4dfa..d18aa8754 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -282,7 +282,8 @@ extern const device_config_t nv3_config[]; // Current channel context - cache1 #define NV3_PFIFO_CACHE0_CTX 0x3080 -#define NV3_PFIFO_CACHE0_METHOD 0x3100 +#define NV3_PFIFO_CACHE0_METHOD_START 0x3100 +#define NV3_PFIFO_CACHE0_METHOD_END 0x3200 #define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 #define NV3_PFIFO_CACHE1_DMA_PUSH0 0x3200 @@ -320,10 +321,12 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_CTX_START 0x3280 #define NV3_PFIFO_CACHE1_CTX_END 0x32F0 -#define NV3_PFIFO_CACHE1_METHOD 0x3300 +#define NV3_PFIFO_CACHE1_METHOD_START 0x3300 +#define NV3_PFIFO_CACHE1_METHOD_END 0x3400 #define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13 + #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 273e0a2e3..1743750ba 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -192,14 +192,6 @@ uint32_t nv3_pfifo_read(uint32_t address) if (nv3->pfifo.runout_put != nv3->pfifo.runout_get) ret |= 1 << NV3_PFIFO_CACHE1_STATUS_RANOUT; - break; - case NV3_PFIFO_CACHE0_METHOD: - ret = ((nv3->pfifo.cache0_settings.method_subchannel << 13) & 0x07) - | ((nv3->pfifo.cache0_settings.method_address << 2) & 0x7FF); - break; - case NV3_PFIFO_CACHE1_METHOD: - ret = ((nv3->pfifo.cache1_settings.method_subchannel << 13) & 0x07) - | ((nv3->pfifo.cache1_settings.method_address << 2) & 0x7FF); break; case NV3_PFIFO_CACHE0_PUT: ret = nv3->pfifo.cache0_settings.put_address; @@ -295,6 +287,30 @@ uint32_t nv3_pfifo_read(uint32_t address) nv_log("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x", ctx_entry_id, ret); } + /* Direct cache read stuff */ + else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) + { + if (address & 4) + return nv3->pfifo.cache0_entry.data; + else + return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + } + else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) + { + // Not sure if REV C changes this. It should... + uint32_t slot = 0; + + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + slot = (address >> 3) & 0x3F; + else + slot = (address >> 3) & 0x1F; + + // See if we want the object name or the channel/subchannel information. + if (address & 4) + return nv3->pfifo.cache1_entries[slot].data; + else + return nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + } else { nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); @@ -456,14 +472,6 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.cache1_settings.channel = val; break; // CACHE0_STATUS and CACHE1_STATUS are not writable - case NV3_PFIFO_CACHE0_METHOD: - nv3->pfifo.cache0_settings.method_subchannel = (val >> 13) & 0x07; - nv3->pfifo.cache0_settings.method_address = (val >> 2) & 0x7FF; - break; - case NV3_PFIFO_CACHE1_METHOD: - nv3->pfifo.cache1_settings.method_subchannel = (val >> 13) & 0x07; - nv3->pfifo.cache1_settings.method_address = (val >> 2) & 0x7FF; - break; case NV3_PFIFO_CACHE1_DMA_CONFIG_0: nv3->pfifo.cache1_settings.dma_state = val; break; @@ -526,6 +534,33 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) else nv_log("\n"); } + else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) + { + if (address & 4) + nv3->pfifo.cache0_entry.data = val; + else + nv3->pfifo.cache0_entry.method = (val & 0x1FFC); + nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; + } + else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) + { + // Not sure if REV C changes this. It should... + uint32_t slot = 0; + + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + slot = (address >> 3) & 0x3F; + else + slot = (address >> 3) & 0x1F; + + uint32_t real_entry = nv3_pfifo_cache1_normal2gray(slot); + + // See if we want the object name or the channel/subchannel information. + if (address & 4) + nv3->pfifo.cache1_entries[real_entry].data = val; + else + nv3->pfifo.cache1_entries[real_entry].method = (val & 0x1FFC); + nv3->pfifo.cache1_entries[real_entry].subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; + } /* Handle some special memory areas */ else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) { @@ -630,7 +665,7 @@ void nv3_pfifo_cache0_pull() #ifndef RELEASE_BUILD nv_log("***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE0 PULLED ****** Contextual information below\n"); - nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context); + nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)¤t_context); #endif } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 33799c39b..e1a2a6442 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -54,7 +54,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) addr &= (nv3->nvbase.svga.vram_max - 1); uint32_t raw_addr = addr; // saved after and - addr ^= (nv3->nvbase.svga.vram_max- 0x10); + addr ^= (nv3->nvbase.svga.vram_max - 0x10); uint32_t val = 0x00; From 145831eb35ec847e49cb9f64a09ba0056c041c29 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 17:21:36 +0000 Subject: [PATCH 105/274] Update cache0 put address on object creation, too --- src/include/86box/nv/vid_nv.h | 26 +++++------ src/include/86box/nv/vid_nv3.h | 18 ++++---- src/video/nv/nv3/subsystems/nv3_pfifo.c | 58 ++++++++++++++---------- src/video/nv/nv3/subsystems/nv3_pgraph.c | 18 +++++++- src/video/nv/nv3/subsystems/nv3_pramin.c | 24 +++++----- 5 files changed, 85 insertions(+), 59 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 2927b91c6..c58d3b0ba 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -21,7 +21,7 @@ * - People who prevented me from giving up (various) * * Authors: Connor Hyde / starfrost - * + * * Copyright 2024-2025 Connor Hyde */ #ifdef EMU_DEVICE_H // what @@ -55,19 +55,19 @@ void nv_log(const char *fmt, ...); #define PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) #define PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) -#define CHIP_REVISION_NV1_A0 0x0000 -#define CHIP_REVISION_NV1_B0 0x0010 -#define CHIP_REVISION_NV1_C0 0x0020 +#define CHIP_REVISION_NV1_A0 0x0000 // 1994 +#define CHIP_REVISION_NV1_B0 0x0010 // 1995 +#define CHIP_REVISION_NV1_C0 0x0020 // #define CHIP_REVISION_NV3_A0 0x0000 // January 1997 #define CHIP_REVISION_NV3_B0 0x0010 // October 1997 #define CHIP_REVISION_NV3_C0 0x0020 // 1998 // Architecture IDs -#define NV_ARCHITECTURE_NV1 1 -#define NV_ARCHITECTURE_NV2 2 -#define NV_ARCHITECTURE_NV3 3 - +#define NV_ARCHITECTURE_NV1 1 // NV1/STG2000 +#define NV_ARCHITECTURE_NV2 2 // Nvidia 'Mutara V08' +#define NV_ARCHITECTURE_NV3 3 // Riva 128 +#define NV_ARCHITECTURE_NV4 4 // Riva TNT and later typedef enum nv_bus_generation_e { @@ -119,7 +119,7 @@ typedef struct nv_base_s void* ddc; // Display Data Channel for EDID } nv_base_t; -#define NV_REG_LIST_END 0xD15EA5E +#define NV_REG_LIST_END 0xD15EA5E // The NV architectures are very complex. // There are hundreds of registers at minimum, and implementing these in a standard way would lead to @@ -131,11 +131,11 @@ typedef struct nv_base_s // Typically, unless they are for a special purpose (and handled specially) e.g. vga all register reads and writes are also 32-bit aligned typedef struct nv_register_s { - int32_t address; // MMIO Address - char* friendly_name; // Friendly name + int32_t address; // MMIO Address + char* friendly_name; // Friendly name // reg_ptr not needed as a parameter, because we implicitly know which register si being tiwddled - uint32_t (*on_read)(); // Optional on-read function - void (*on_write)(uint32_t value);// Optional on-write fucntion + uint32_t (*on_read)(); // Optional on-read function + void (*on_write)(uint32_t value); // Optional on-write fucntion } nv_register_t; nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index d18aa8754..d9d0a6ad3 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -271,10 +271,10 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty #define NV3_PFIFO_CACHE0_STATUS_FULL 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD 8 +#define NV3_PFIFO_CACHE0_DMA_PULL0 0x3040 +#define NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE0_DMA_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD 8 #define NV3_PFIFO_CACHE0_PULLER_CTX_STATE 0x3050 #define NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 @@ -307,11 +307,11 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULL0 0x3240 +#define NV3_PFIFO_CACHE1_DMA_PULL0 0x3240 //todo: merge stuff -#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware +#define NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE1_DMA_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE1_DMA_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE 0x3250 #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 @@ -932,7 +932,7 @@ typedef struct nv3_pfifo_cache_s uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. uint8_t channel; // The DMA channel ID of this cache. uint32_t status; - uint32_t puller_control; + uint32_t dma_pull0; uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; // Only one of these exists for cache0 /* cache1 only diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 1743750ba..9857afbd7 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -43,19 +43,20 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, { NV3_PFIFO_CACHE_REASSIGNMENT, "PFIFO - Allow Cache Channel Reassignment", NULL, NULL }, - { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller Control", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller Control"}, + { NV3_PFIFO_CACHE0_DMA_PULL0, "PFIFO - Cache0 Puller Control", NULL, NULL}, + { NV3_PFIFO_CACHE1_DMA_PULL0, "PFIFO - Cache1 Puller Control"}, { NV3_PFIFO_CACHE0_PULLER_CTX_STATE, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, + { NV3_PFIFO_CACHE1_DMA_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CTX_STATE, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, { NV3_PFIFO_CACHE0_DMA_PUSH0, "PFIFO - Cache0 Access", NULL, NULL, }, { NV3_PFIFO_CACHE1_DMA_PUSH0, "PFIFO - Cache1 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 DMA Channel ID", NULL, NULL, }, - { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 DMA Channel ID", NULL, NULL, }, + { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 Push Channel ID", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get", NULL, NULL }, + { NV3_PFIFO_CACHE0_CTX, "PFIFO - Cache0 Context", NULL, NULL }, { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get", NULL, NULL }, { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put", NULL, NULL }, { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put", NULL, NULL }, @@ -145,11 +146,11 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CONFIG_RAMRO: ret = nv3->pfifo.ramro_config; break; - case NV3_PFIFO_CACHE0_PULLER_CONTROL: - ret = nv3->pfifo.cache0_settings.puller_control; + case NV3_PFIFO_CACHE0_DMA_PULL0: + ret = nv3->pfifo.cache0_settings.dma_pull0; break; - case NV3_PFIFO_CACHE1_PULL0: - ret = nv3->pfifo.cache1_settings.puller_control; + case NV3_PFIFO_CACHE1_DMA_PULL0: + ret = nv3->pfifo.cache1_settings.dma_pull0; break; case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; @@ -285,11 +286,13 @@ uint32_t nv3_pfifo_read(uint32_t address) uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; ret = nv3->pfifo.cache1_settings.context[ctx_entry_id]; - nv_log("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x", ctx_entry_id, ret); + nv_log("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x\n", ctx_entry_id, ret); } /* Direct cache read stuff */ else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { + nv_log("PFIFO Cache0 Read\n"); + if (address & 4) return nv3->pfifo.cache0_entry.data; else @@ -305,6 +308,8 @@ uint32_t nv3_pfifo_read(uint32_t address) else slot = (address >> 3) & 0x1F; + nv_log("PFIFO Cache1 Read slot=%d\n", slot); + // See if we want the object name or the channel/subchannel information. if (address & 4) return nv3->pfifo.cache1_entries[slot].data; @@ -341,11 +346,15 @@ void nv3_pfifo_trigger_dma_if_required() /* PUSH - System to GPU (?) */ if (nv3->pfifo.cache1_settings.dma_push0) { - + /* PULL - GPU to System */ + nv_log("Initiating System to NV DMA - Probably we are trying to notify\n"); + } + else if (nv3->pfifo.cache1_settings.dma_pull0) + { + /* PULL - GPU to System */ + nv_log("Initiating NV to System DMA - Probably we are trying to notify\n"); } - /* PULL - GPU to System */ - nv_log("Initiating NV to System DMA - Probably we are trying to notify"); } } @@ -447,11 +456,11 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.cache_reassignment = val & 0x01; //1bit meaningful break; // Control - case NV3_PFIFO_CACHE0_PULLER_CONTROL: - nv3->pfifo.cache0_settings.puller_control = val; // 8bits meaningful + case NV3_PFIFO_CACHE0_DMA_PULL0: + nv3->pfifo.cache0_settings.dma_pull0 = val; // 8bits meaningful break; - case NV3_PFIFO_CACHE1_PULL0: - nv3->pfifo.cache1_settings.puller_control = val; // 8bits meaningful + case NV3_PFIFO_CACHE1_DMA_PULL0: + nv3->pfifo.cache1_settings.dma_pull0 = val; // 8bits meaningful break; case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: nv3->pfifo.cache0_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; @@ -628,7 +637,7 @@ void nv3_pfifo_cache0_push() void nv3_pfifo_cache0_pull() { // Do nothing if PFIFO CACHE0 is disabled - if (!nv3->pfifo.cache0_settings.puller_control & (1 >> NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED)) + if (!nv3->pfifo.cache0_settings.dma_pull0 & (1 >> NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED)) return; // Do nothing if there is nothing in cache0 to pull @@ -644,6 +653,9 @@ void nv3_pfifo_cache0_pull() // i.e. there is no method in cache0, so we have to find the object. if (!current_method) { + // flip the get address over + nv3->pfifo.cache0_settings.get_address ^= 0x04; + if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) return; // interrupt was fired, and we went to ramro } @@ -654,8 +666,8 @@ void nv3_pfifo_cache0_pull() // Tell the CPU if we found a software method if (current_context & 0x800000) { - nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache0_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); } @@ -780,7 +792,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) void nv3_pfifo_cache1_pull() { // Do nothing if PFIFO CACHE1 is disabled - if (!nv3->pfifo.cache1_settings.puller_control & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) + if (!nv3->pfifo.cache1_settings.dma_pull0 & (1 >> NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED)) return; // Do nothing if there is nothing in cache1 to pull @@ -808,8 +820,8 @@ void nv3_pfifo_cache1_pull() // Tell the CPU if we found a software method if (current_context & 0x800000) { - nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache1_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); } diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 1c5750596..50089c410 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -468,16 +468,30 @@ void nv3_pgraph_vblank_start(svga_t* svga) nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_EN_0_VBLANK); } +void nv3_pgraph_arbitrate_method(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context) +{ + switch (class_id) + { + + } +} + /* Arbitrates graphics object submission to the right object types */ void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context) { // class id can be derived from the context but we debug log it before we get here - + // Do we need to read grobj here? + switch (method) { // This method is how we figure out which methods exist. case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("Hi, I'm an NVidia object :)\n"); + nv_log("I'm an Nvidia Object! name=0x%08x channel=%d.%d class=0x%02x (%s) method=0x%04x, context=0x%08x\n", + name, channel, subchannel, class_id, nv3_class_names[class_id], method, context); + break; + default: + // Object Method orchestration + nv3_pgraph_arbitrate_method(name, method, channel, subchannel, class_id, context); break; } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index e1a2a6442..55de2616b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -409,16 +409,16 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u if (!cache_num) { nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; - nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; + nv3->pfifo.cache0_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; } else { nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; - nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; + nv3->pfifo.cache1_settings.dma_pull0 |= NV3_PFIFO_CACHE1_DMA_PULL0_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; + nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED; } nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); @@ -452,9 +452,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // By definition we can't have a cache error by here so take it off if (!cache_num) - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE; + nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_HASH_FAILURE; else - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; + nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_HASH_FAILURE; // Caches store all the subchannels for our current dma channel and basically get stale every context switch // Also we have to check that a osftware object didn't end up in here... @@ -471,13 +471,13 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // handle it as an error if (!cache_num) { - nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED; + nv3->pfifo.cache0_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; } else { - nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; + nv3->pfifo.cache1_settings.dma_pull0 |= NV3_PFIFO_CACHE1_DMA_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED; } // It's an error but it isn't lol @@ -488,9 +488,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u { // obviously turn off the "is software" if it's not if (!cache_num) - nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; else - nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_SOFTWARE_METHOD; } // Ok we found it. Lol From ca6a7c4f37d1a0dce73d80324ea841ff3f26f517 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 17:56:25 +0000 Subject: [PATCH 106/274] Workaround for 86box dynarec design allowing the riva to overwrite old graphics objects. --- src/video/nv/nv3/nv3_core.c | 13 ++++++++++++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 8 ++++++-- src/video/nv/nv3/subsystems/nv3_user.c | 4 ++++ 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 949ce53be..0876f7c89 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -127,7 +127,14 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) } - return nv3_mmio_arbitrate_read(addr); + ret = nv3_mmio_arbitrate_read(addr); + + // This may get around the riva shredding its own cache + //nv3_pfifo_cache0_pull(); + //nv3_pfifo_cache1_pull(); + + return ret; + } // Write 8-bit MMIO @@ -206,6 +213,10 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) } nv3_mmio_arbitrate_write(addr, val); + + // This may get around the riva shredding its own cache + //nv3_pfifo_cache0_pull(); + //nv3_pfifo_cache1_pull(); } // PCI stuff diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 9857afbd7..a9ae7dc61 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -267,7 +267,7 @@ uint32_t nv3_pfifo_read(uint32_t address) break; - /* Cache1 is handled below */ + /* Cache1 is handled below - cache0 only has one entry */ case NV3_PFIFO_CACHE0_CTX: ret = nv3->pfifo.cache0_settings.context[0]; break; @@ -293,7 +293,7 @@ uint32_t nv3_pfifo_read(uint32_t address) { nv_log("PFIFO Cache0 Read\n"); - if (address & 4) + if (address & 4) return nv3->pfifo.cache0_entry.data; else return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); @@ -545,8 +545,12 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) } else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { + // 3104 always written after 3100 if (address & 4) + { nv3->pfifo.cache0_entry.data = val; + nv3_pfifo_cache0_pull(); // immediately pull out + } else nv3->pfifo.cache0_entry.method = (val & 0x1FFC); nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index 4361abcd0..a6c9a588c 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -66,4 +66,8 @@ uint32_t nv3_user_read(uint32_t address) void nv3_user_write(uint32_t address, uint32_t value) { nv3_pfifo_cache1_push(address, value); + + // This isn't ideal, but otherwise, the dynarec causes the GPU to write so many objects into CACHE1, it starts overwriting the old objects + // This basically makes the fifo not a fifo, but oh well + nv3_pfifo_cache1_pull(); } \ No newline at end of file From ce207fef8520f9b490af44584399c1cc831427d2 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 18:06:57 +0000 Subject: [PATCH 107/274] remove some oboslete code --- src/video/nv/nv3/nv3_core.c | 4 ---- src/video/nv/nv3/nv3_core_arbiter.c | 6 +----- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 0876f7c89..c56551b14 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -213,10 +213,6 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) } nv3_mmio_arbitrate_write(addr, val); - - // This may get around the riva shredding its own cache - //nv3_pfifo_cache0_pull(); - //nv3_pfifo_cache1_pull(); } // PCI stuff diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 6e8e2b9a5..17cca15df 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -103,9 +103,6 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) ret = nv3_vram_read(address); else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); - // RAMIN is handled by a separate memory mapping in PCI BAR1 - //else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END) - //ret = nv3_ramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function else { nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); @@ -167,8 +164,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) nv3_vram_write(address, value); else if (address >= NV3_USER_START && address <= NV3_USER_END) nv3_user_write(address, value); - else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END) - nv3_ramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions + //RAMIN is its own thing else { nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); From 1e32c119c56e0310bd358162f6ad0f1bd7138c57 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 19:00:08 +0000 Subject: [PATCH 108/274] Make the pullre registers work. This makes the grobj submitted exist --- src/include/86box/nv/vid_nv3.h | 24 +++--- src/video/nv/nv3/subsystems/nv3_pfifo.c | 98 ++++++++++++++++-------- src/video/nv/nv3/subsystems/nv3_pramin.c | 24 +++--- 3 files changed, 89 insertions(+), 57 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index d9d0a6ad3..852c368b5 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -264,17 +264,17 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_DMA_PUSH0 0x3000 +#define NV3_PFIFO_CACHE0_PUSH0 0x3000 #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 #define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty #define NV3_PFIFO_CACHE0_STATUS_FULL 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE0_DMA_PULL0 0x3040 -#define NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE0_DMA_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD 8 +#define NV3_PFIFO_CACHE0_PULL0 0x3040 +#define NV3_PFIFO_CACHE0_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE0_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD 8 #define NV3_PFIFO_CACHE0_PULLER_CTX_STATE 0x3050 #define NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 @@ -286,7 +286,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_METHOD_END 0x3200 #define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 -#define NV3_PFIFO_CACHE1_DMA_PUSH0 0x3200 +#define NV3_PFIFO_CACHE1_PUSH0 0x3200 #define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 @@ -307,11 +307,11 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_DMA_PULL0 0x3240 +#define NV3_PFIFO_CACHE1_PULL0 0x3240 //todo: merge stuff -#define NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE1_DMA_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_DMA_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware +#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE 0x3250 #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 @@ -927,12 +927,12 @@ typedef struct nv3_pbus_s typedef struct nv3_pfifo_cache_s { - bool dma_push0; // Can we even access this cache? + bool push0; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. uint8_t channel; // The DMA channel ID of this cache. uint32_t status; - uint32_t dma_pull0; + uint32_t pull0; uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; // Only one of these exists for cache0 /* cache1 only diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index a9ae7dc61..c3deac24e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -43,13 +43,13 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, { NV3_PFIFO_CACHE_REASSIGNMENT, "PFIFO - Allow Cache Channel Reassignment", NULL, NULL }, - { NV3_PFIFO_CACHE0_DMA_PULL0, "PFIFO - Cache0 Puller Control", NULL, NULL}, - { NV3_PFIFO_CACHE1_DMA_PULL0, "PFIFO - Cache1 Puller Control"}, + { NV3_PFIFO_CACHE0_PULL0, "PFIFO - Cache0 Puller Control", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller Control"}, { NV3_PFIFO_CACHE0_PULLER_CTX_STATE, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE1_DMA_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CTX_STATE, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE0_DMA_PUSH0, "PFIFO - Cache0 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE1_DMA_PUSH0, "PFIFO - Cache1 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE0_PUSH0, "PFIFO - Cache0 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH0, "PFIFO - Cache1 Access", NULL, NULL, }, { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, @@ -146,11 +146,12 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CONFIG_RAMRO: ret = nv3->pfifo.ramro_config; break; - case NV3_PFIFO_CACHE0_DMA_PULL0: - ret = nv3->pfifo.cache0_settings.dma_pull0; + /* These automatically trigger pulls when 1 is written */ + case NV3_PFIFO_CACHE0_PULL0: + ret = nv3->pfifo.cache0_settings.pull0; break; - case NV3_PFIFO_CACHE1_DMA_PULL0: - ret = nv3->pfifo.cache1_settings.dma_pull0; + case NV3_PFIFO_CACHE1_PULL0: + ret = nv3->pfifo.cache1_settings.pull0; break; case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; @@ -158,11 +159,12 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; break; - case NV3_PFIFO_CACHE0_DMA_PUSH0: - ret = nv3->pfifo.cache0_settings.dma_push0; + /* Does this automatically push? */ + case NV3_PFIFO_CACHE0_PUSH0: + ret = nv3->pfifo.cache0_settings.push0; break; - case NV3_PFIFO_CACHE1_DMA_PUSH0: - ret = nv3->pfifo.cache1_settings.dma_push0; + case NV3_PFIFO_CACHE1_PUSH0: + ret = nv3->pfifo.cache1_settings.push0; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: ret = nv3->pfifo.cache0_settings.channel; @@ -344,12 +346,12 @@ void nv3_pfifo_trigger_dma_if_required() uint32_t tlb_pt_tag = nv3->pfifo.cache1_settings.dma_tlb_tag; // 0xFFFFFFFF usually? /* PUSH - System to GPU (?) */ - if (nv3->pfifo.cache1_settings.dma_push0) + if (nv3->pfifo.cache1_settings.push0) { /* PULL - GPU to System */ nv_log("Initiating System to NV DMA - Probably we are trying to notify\n"); } - else if (nv3->pfifo.cache1_settings.dma_pull0) + else if (nv3->pfifo.cache1_settings.pull0) { /* PULL - GPU to System */ nv_log("Initiating NV to System DMA - Probably we are trying to notify\n"); @@ -455,12 +457,20 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) case NV3_PFIFO_CACHE_REASSIGNMENT: nv3->pfifo.cache_reassignment = val & 0x01; //1bit meaningful break; - // Control - case NV3_PFIFO_CACHE0_DMA_PULL0: - nv3->pfifo.cache0_settings.dma_pull0 = val; // 8bits meaningful + // Control - these can trigger pulls + case NV3_PFIFO_CACHE0_PULL0: + nv3->pfifo.cache0_settings.pull0 = val; // 8bits meaningful + + if (nv3->pfifo.cache0_settings.pull0 & (1 >> NV3_PFIFO_CACHE0_PULL0_ENABLED)) + nv3_pfifo_cache0_pull(); + break; - case NV3_PFIFO_CACHE1_DMA_PULL0: - nv3->pfifo.cache1_settings.dma_pull0 = val; // 8bits meaningful + case NV3_PFIFO_CACHE1_PULL0: + nv3->pfifo.cache1_settings.pull0 = val; // 8bits meaningful + + if (nv3->pfifo.cache1_settings.pull0 & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) + nv3_pfifo_cache1_pull(); + break; case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: nv3->pfifo.cache0_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; @@ -468,11 +478,11 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: nv3->pfifo.cache1_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; - case NV3_PFIFO_CACHE0_DMA_PUSH0: - nv3->pfifo.cache0_settings.dma_push0 = val; + case NV3_PFIFO_CACHE0_PUSH0: + nv3->pfifo.cache0_settings.push0 = val; break; - case NV3_PFIFO_CACHE1_DMA_PUSH0: - nv3->pfifo.cache1_settings.dma_push0 = val; + case NV3_PFIFO_CACHE1_PUSH0: + nv3->pfifo.cache1_settings.push0 = val; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: nv3->pfifo.cache0_settings.channel = val; @@ -545,15 +555,22 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) } else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { + nv_log("PFIFO Cache0 Write"); + // 3104 always written after 3100 if (address & 4) { + nv_log("Name = 0x%08x\n", val); nv3->pfifo.cache0_entry.data = val; nv3_pfifo_cache0_pull(); // immediately pull out } else + { nv3->pfifo.cache0_entry.method = (val & 0x1FFC); nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; + nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache0_entry.subchannel, nv3->pfifo.cache0_entry.method); + } + } else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) { @@ -567,12 +584,21 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) uint32_t real_entry = nv3_pfifo_cache1_normal2gray(slot); + nv_log("Cache1 Write Slot %d (Gray code)", real_entry); + // See if we want the object name or the channel/subchannel information. if (address & 4) + { + nv_log("Name = 0x%08x\n", val); nv3->pfifo.cache1_entries[real_entry].data = val; + } else + { nv3->pfifo.cache1_entries[real_entry].method = (val & 0x1FFC); nv3->pfifo.cache1_entries[real_entry].subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; + nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method); + } + } /* Handle some special memory areas */ else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) @@ -641,7 +667,7 @@ void nv3_pfifo_cache0_push() void nv3_pfifo_cache0_pull() { // Do nothing if PFIFO CACHE0 is disabled - if (!nv3->pfifo.cache0_settings.dma_pull0 & (1 >> NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED)) + if (!nv3->pfifo.cache0_settings.pull0 & (1 >> NV3_PFIFO_CACHE0_PULL0_ENABLED)) return; // Do nothing if there is nothing in cache0 to pull @@ -668,10 +694,12 @@ void nv3_pfifo_cache0_pull() uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; // Tell the CPU if we found a software method - if (current_context & 0x800000) + if (!(current_context & 0x800000)) { - nv3->pfifo.cache0_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; + nv_log("The object in CACHE0 is a software object\n"); + + nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); } @@ -713,7 +741,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & (NV3_DMA_CHANNELS - 1); // first make sure there is even any cache available - if (!nv3->pfifo.cache1_settings.dma_push0) + if (!nv3->pfifo.cache1_settings.push0) { oh_shit = true; oh_shit_reason = nv3_runout_reason_no_cache_available; @@ -796,7 +824,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) void nv3_pfifo_cache1_pull() { // Do nothing if PFIFO CACHE1 is disabled - if (!nv3->pfifo.cache1_settings.dma_pull0 & (1 >> NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED)) + if (!nv3->pfifo.cache1_settings.pull0 & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) return; // Do nothing if there is nothing in cache1 to pull @@ -822,10 +850,14 @@ void nv3_pfifo_cache1_pull() uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; // Tell the CPU if we found a software method - if (current_context & 0x800000) + //bit23 unset=software + //bit23 set=hardware + if (!(current_context & 0x800000)) { - nv3->pfifo.cache1_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; + nv_log("The object in CACHE1 is a software object\n"); + + nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 55de2616b..a591f69b1 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -409,16 +409,16 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u if (!cache_num) { nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; - nv3->pfifo.cache0_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_HASH_FAILURE; + nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; + nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; } else { nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; - nv3->pfifo.cache1_settings.dma_pull0 |= NV3_PFIFO_CACHE1_DMA_PULL0_HASH_FAILURE; + nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED; + nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; } nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); @@ -452,9 +452,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // By definition we can't have a cache error by here so take it off if (!cache_num) - nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_HASH_FAILURE; + nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_HASH_FAILURE; else - nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_HASH_FAILURE; + nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; // Caches store all the subchannels for our current dma channel and basically get stale every context switch // Also we have to check that a osftware object didn't end up in here... @@ -471,13 +471,13 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // handle it as an error if (!cache_num) { - nv3->pfifo.cache0_settings.dma_pull0 |= NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_ENABLED; + nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; } else { - nv3->pfifo.cache1_settings.dma_pull0 |= NV3_PFIFO_CACHE1_DMA_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_ENABLED; + nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; } // It's an error but it isn't lol @@ -488,9 +488,9 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u { // obviously turn off the "is software" if it's not if (!cache_num) - nv3->pfifo.cache0_settings.dma_pull0 &= ~NV3_PFIFO_CACHE0_DMA_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; else - nv3->pfifo.cache1_settings.dma_pull0 &= ~NV3_PFIFO_CACHE1_DMA_PULL0_SOFTWARE_METHOD; + nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; } // Ok we found it. Lol From 66fda3070d4a8c3f8a7cfd5b6e5f8fd0b58bc75d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 11 Mar 2025 22:24:51 +0000 Subject: [PATCH 109/274] Fix cache0 checks. Now it actually does a whole bunch of shit. --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index c3deac24e..b219ae535 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -175,7 +175,7 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE0_STATUS: // CACHE0 has only one entry so it can only ever be empty or full - if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache1_settings.get_address) + if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache0_settings.get_address) ret |= 1 << NV3_PFIFO_CACHE0_STATUS_EMPTY; else ret |= 1 << NV3_PFIFO_CACHE0_STATUS_FULL; @@ -491,6 +491,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.cache1_settings.channel = val; break; // CACHE0_STATUS and CACHE1_STATUS are not writable + // DMA configuration case NV3_PFIFO_CACHE1_DMA_CONFIG_0: nv3->pfifo.cache1_settings.dma_state = val; break; @@ -701,6 +702,7 @@ void nv3_pfifo_cache0_pull() nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); + return; } // Is this needed? @@ -859,6 +861,7 @@ void nv3_pfifo_cache1_pull() nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); + return; } // start by incrementing From 4d8a9d2892546ebfd7f088f3d73750cceff6e823 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 12 Mar 2025 16:35:35 +0000 Subject: [PATCH 110/274] Send pgraph writes to the right classes. Implement grobj reading. Fix class execution functions --- .../86box/nv/classes/vid_nv3_classes.h | 73 ++++++++++----- src/include/86box/nv/vid_nv3.h | 3 +- .../nv3/classes/nv3_class_001_beta_factor.c | 2 +- src/video/nv/nv3/classes/nv3_class_002_rop.c | 2 +- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 2 +- .../nv/nv3/classes/nv3_class_004_plane_mask.c | 2 +- .../nv3_class_005_clipping_rectangle.c | 2 +- .../nv/nv3/classes/nv3_class_006_pattern.c | 2 +- .../nv/nv3/classes/nv3_class_007_rectangle.c | 2 +- .../nv/nv3/classes/nv3_class_008_point.c | 2 +- src/video/nv/nv3/classes/nv3_class_009_line.c | 2 +- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 2 +- .../nv/nv3/classes/nv3_class_00b_triangle.c | 2 +- .../classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 2 +- .../nv3_class_00e_scaled_image_from_mem.c | 2 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- .../nv/nv3/classes/nv3_class_011_image.c | 2 +- .../nv/nv3/classes/nv3_class_012_bitmap.c | 2 +- .../classes/nv3_class_014_transfer2memory.c | 2 +- .../nv3_class_015_stretched_image_from_cpu.c | 2 +- .../nv3_class_017_d3d5_tri_zeta_buffer.c | 2 +- .../classes/nv3_class_018_point_zeta_buffer.c | 2 +- .../classes/nv3_class_01c_image_in_memory.c | 2 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 16 ++-- src/video/nv/nv3/subsystems/nv3_pgraph.c | 88 ++++++++++++++++++- src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 4 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 4 +- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 4 +- 31 files changed, 178 insertions(+), 62 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 019b04ea4..0a5225226 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -41,6 +41,33 @@ // CLass names for debugging extern const char* nv3_class_names[]; +/* Defines valid classes. */ +typedef enum nv3_pgraph_class_e +{ + nv3_pgraph_class01_beta_factor = 0x01, + nv3_pgraph_class02_rop = 0x02, + nv3_pgraph_class03_chroma_key = 0x03, + nv3_pgraph_class04_plane_mask = 0x04, + nv3_pgraph_class05_clipping_rectangle = 0x05, + nv3_pgraph_class06_pattern = 0x06, + nv3_pgraph_class07_rectangle = 0x07, + nv3_pgraph_class08_point = 0x08, + nv3_pgraph_class09_line = 0x09, + nv3_pgraph_class0a_lin = 0x0a, + nv3_pgraph_class0b_triangle = 0x0b, + nv3_pgraph_class0c_w95txt = 0x0c, + nv3_pgraph_class0d_m2mf = 0x0d, + nv3_pgraph_class0e_scaled_image_from_memory = 0x0e, + nv3_pgraph_class10_blit = 0x10, + nv3_pgraph_class11_image = 0x11, + nv3_pgraph_class12_bitmap = 0x12, + nv3_pgraph_class14_transfer2memory = 0x14, + nv3_pgraph_class15_stretched_image_from_cpu = 0x15, + nv3_pgraph_class17_d3d5tri_zeta_buffer = 0x17, + nv3_pgraph_class18_point_zeta_buffer = 0x18, + nv3_pgraph_class1c_image_in_memory = 0x1c, +} nv3_pgraph_class; + /* Class context switch method */ typedef struct nv3_class_ctx_switch_method_s { @@ -1116,29 +1143,29 @@ typedef struct nv3_grobj_s #define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017 // Class methods -void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_001_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_002_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_003_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_004_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_005_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_006_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_007_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_009_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_00c_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_00d_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_00e_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_010_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_011_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_012_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_014_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_015_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_017_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_018_method(uint32_t method_id, nv3_grobj_t grobj); -void nv3_class_01c_method(uint32_t method_id, nv3_grobj_t grobj); +void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); // This area is used for holding universal representations of the U* registers... extern struct nv3_object_class_001 nv3_beta_factor; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 852c368b5..07c30a9ac 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1086,6 +1086,7 @@ typedef struct nv3_pgraph_status_s } nv3_pgraph_status_t; + // Graphics Subsystem typedef struct nv3_pgraph_s { @@ -1454,7 +1455,7 @@ void nv3_pgraph_init(); uint32_t nv3_pgraph_read(uint32_t address); void nv3_pgraph_write(uint32_t address, uint32_t value); void nv3_pgraph_vblank_start(svga_t* svga); -void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context); +void nv3_pgraph_submit(uint32_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context); // NV3 PFIFO diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 7a700bf6e..2dc6a4022 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -31,7 +31,7 @@ struct nv3_object_class_001 beta_factor; -void nv3_class_001_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index ac06ef010..f5a1c343e 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -31,7 +31,7 @@ struct nv3_object_class_002 nv3_rop; -void nv3_class_002_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 887e2a8bd..8b99fa808 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -31,7 +31,7 @@ struct nv3_object_class_003 nv3_chroma_key; -void nv3_class_003_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 95e5e70c4..e32eb6333 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -31,7 +31,7 @@ struct nv3_object_class_004 nv3_plane_mask; -void nv3_class_004_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 76ab1cfec..b5d4a5b80 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -30,7 +30,7 @@ struct nv3_object_class_005 nv3_clipping_rectangle; -void nv3_class_005_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index 32561e977..8442bde0d 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -31,7 +31,7 @@ struct nv3_object_class_006 nv3_pattern; -void nv3_class_006_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 2b194960b..9b0908b8d 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -31,7 +31,7 @@ struct nv3_object_class_007 nv3_rectangle; -void nv3_class_007_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index eaa12f5c4..4ecfa6d87 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -31,7 +31,7 @@ struct nv3_object_class_008 nv3_point; -void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index a17cf0f90..c8104cd9c 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -31,7 +31,7 @@ struct nv3_object_class_009 nv3_line; -void nv3_class_009_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 66d3d949b..8e83c2433 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -32,7 +32,7 @@ struct nv3_object_class_00A nv3_lin; -void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index f1d41a816..766597af1 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -31,7 +31,7 @@ struct nv3_object_class_00B nv3_triangle; -void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index d8dbc4513..cceece8b7 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -31,7 +31,7 @@ struct nv3_object_class_00C nv3_win95_gdi_text; -void nv3_class_00c_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 4f51f187a..6e2569cd9 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -31,7 +31,7 @@ struct nv3_object_class_00D nv3_m2mf; -void nv3_class_00d_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index 165c1e9d3..e5cbb9634 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -31,7 +31,7 @@ struct nv3_object_class_00E nv3_scaled_image_from_mem; -void nv3_class_00e_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index f32309343..7c1e9626f 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -31,7 +31,7 @@ struct nv3_object_class_010 nv3_blit; -void nv3_class_010_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index e42ea8071..d7a2a7987 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -31,7 +31,7 @@ struct nv3_object_class_011 nv3_image; -void nv3_class_011_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index a0ff8d537..63a5f8e1d 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -32,7 +32,7 @@ struct nv3_object_class_012 nv3_bitmap; -void nv3_class_012_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index bc4e3f879..197235c75 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -32,7 +32,7 @@ struct nv3_object_class_014 nv3_transfer2memory; -void nv3_class_014_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index 1954724d1..1ab61faed 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -31,7 +31,7 @@ struct nv3_object_class_015 nv3_stretched_image_from_cpu; -void nv3_class_015_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 7c669a1e5..2bb2bfd77 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -31,7 +31,7 @@ struct nv3_object_class_017 nv3_d3d5_tri; -void nv3_class_017_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index bbf29694f..68747c9ce 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -31,7 +31,7 @@ struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; -void nv3_class_018_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index f40924deb..0efb6c8ce 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -31,7 +31,7 @@ struct nv3_object_class_01C nv3_image_in_memory; -void nv3_class_01c_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 39f7e2b81..eb0469823 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -29,7 +29,7 @@ #include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> -void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj) +void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index b219ae535..31630dae2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -709,9 +709,13 @@ void nv3_pfifo_cache0_pull() nv3->pfifo.cache0_settings.get_address ^= 0x04; #ifndef RELEASE_BUILD - nv_log("***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE0 PULLED ****** Contextual information below\n"); + nv_log("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n"); - nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)¤t_context); + nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; + + nv3_debug_ramin_print_context_info(current_name, context_structure); + + nv3_pgraph_submit(current_name, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); #endif } @@ -876,9 +880,11 @@ void nv3_pfifo_cache1_pull() nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; #ifndef RELEASE_BUILD - nv_log("***** OBJECT PULLED, SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - ****** Contextual information below\n"); - - nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)¤t_context); + nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; + + nv3_debug_ramin_print_context_info(current_name, context_structure); + + nv3_pgraph_submit(current_name, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); #endif //Todo: finish it diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 50089c410..ffbaa7f01 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -468,16 +468,98 @@ void nv3_pgraph_vblank_start(svga_t* svga) nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_EN_0_VBLANK); } -void nv3_pgraph_arbitrate_method(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context) +/* Sends off method execution to the right class */ +void nv3_pgraph_arbitrate_method(uint32_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) { + /* Obtain the grobj information from the context in ramin */ + nv3_grobj_t grobj = {0}; + + grobj.grobj_0 = nv3_ramin_read32(context.ramin_offset, nv3); + grobj.grobj_1 = nv3_ramin_read32(context.ramin_offset + 4, nv3); + grobj.grobj_2 = nv3_ramin_read32(context.ramin_offset + 8, nv3); + grobj.grobj_3 = nv3_ramin_read32(context.ramin_offset + 12, nv3); + + nv_log("**** About to execute method **** obj name=0x%08x, method=0x%04x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x", + name, method, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); + + // By this point, we already ANDed the class ID to 0x1F. + // Send the grobj, the context, the method and the name off to actually be acted upon. switch (class_id) { - + case nv3_pgraph_class01_beta_factor: + nv3_class_001_method(name, method, context, grobj); + break; + case nv3_pgraph_class02_rop: + nv3_class_002_method(name, method, context, grobj); + break; + case nv3_pgraph_class03_chroma_key: + nv3_class_003_method(name, method, context, grobj); + break; + case nv3_pgraph_class04_plane_mask: + nv3_class_004_method(name, method, context, grobj); + break; + case nv3_pgraph_class05_clipping_rectangle: + nv3_class_005_method(name, method, context, grobj); + break; + case nv3_pgraph_class06_pattern: + nv3_class_006_method(name, method, context, grobj); + break; + case nv3_pgraph_class07_rectangle: + nv3_class_007_method(name, method, context, grobj); + break; + case nv3_pgraph_class08_point: + nv3_class_008_method(name, method, context, grobj); + break; + case nv3_pgraph_class09_line: + nv3_class_009_method(name, method, context, grobj); + break; + case nv3_pgraph_class0a_lin: + nv3_class_00a_method(name, method, context, grobj); + break; + case nv3_pgraph_class0b_triangle: + nv3_class_00b_method(name, method, context, grobj); + break; + case nv3_pgraph_class0c_w95txt: + nv3_class_00c_method(name, method, context, grobj); + break; + case nv3_pgraph_class0d_m2mf: + nv3_class_00d_method(name, method, context, grobj); + break; + case nv3_pgraph_class0e_scaled_image_from_memory: + nv3_class_00e_method(name, method, context, grobj); + break; + case nv3_pgraph_class10_blit: + nv3_class_010_method(name, method, context, grobj); + break; + case nv3_pgraph_class11_image: + nv3_class_011_method(name, method, context, grobj); + break; + case nv3_pgraph_class12_bitmap: + nv3_class_012_method(name, method, context, grobj); + break; + case nv3_pgraph_class14_transfer2memory: + nv3_class_014_method(name, method, context, grobj); + break; + case nv3_pgraph_class15_stretched_image_from_cpu: + nv3_class_015_method(name, method, context, grobj); + break; + case nv3_pgraph_class17_d3d5tri_zeta_buffer: + nv3_class_017_method(name, method, context, grobj); + break; + case nv3_pgraph_class18_point_zeta_buffer: + nv3_class_018_method(name, method, context, grobj); + break; + case nv3_pgraph_class1c_image_in_memory: + nv3_class_01c_method(name, method, context, grobj); + break; + default: + fatal("NV3 (nv3_pgraph_arbitrate_method): Attempted to execute method on invalid, or unimplemented, class ID %s", nv3_class_names[class_id]); + return; } } /* Arbitrates graphics object submission to the right object types */ -void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context) +void nv3_pgraph_submit(uint32_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) { // class id can be derived from the context but we debug log it before we get here // Do we need to read grobj here? diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index a591f69b1..226f4d8ee 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -507,7 +507,7 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte nv_log("Context:\n"); nv_log("DMA Channel %d (0-7 valid)\n", context.channel); - nv_log("Class ID: as repreesnted in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)\n", context.class_id, + nv_log("Class ID: as represented in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)\n", context.class_id, context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); nv_log("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index 9a21c2e4f..fa0d5899c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -30,10 +30,10 @@ uint32_t nv3_ramfc_read(uint32_t address) { - nv_log("RAMFC (Unused DMA channel context) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); + nv_log("RAMFC (Unused DMA channel context) Read (0x%04x)), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); } void nv3_ramfc_write(uint32_t address, uint32_t value) { - nv_log("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); + nv_log("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x)), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", value, address); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index e09f80e83..e46b46618 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -47,10 +47,10 @@ uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) uint32_t nv3_ramht_read(uint32_t address) { - nv_log("RAMHT (Graphics object storage hashtable) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); + nv_log("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); } void nv3_ramht_write(uint32_t address, uint32_t value) { - nv_log("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), UNIMPLEMENTED\n", value, address); + nv_log("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - UNIMPLEMENTED\n", value, address); } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 2104868c6..d421b28dd 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -30,12 +30,12 @@ uint32_t nv3_ramro_read(uint32_t address) { - nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), UNIMPLEMENTED - RETURNING 0x00\n", address); + nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", address); } void nv3_ramro_write(uint32_t address, uint32_t value) { - nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), UNIMPLEMENTED\n (Todo: Read the entries...)\n", value, address); + nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", value, address); } void nv3_ramro_send() From 3512b462b36d46004b0fdf009522d52f352c2d16 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 12 Mar 2025 16:53:57 +0000 Subject: [PATCH 111/274] fix grobj, rename name to param, fix compile --- .../86box/nv/classes/vid_nv3_classes.h | 25 +---------------- src/include/86box/nv/vid_nv3.h | 28 ++++++++++++++++++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 16 +++++------ src/video/nv/nv3/subsystems/nv3_pgraph.c | 23 ++++++++------- 4 files changed, 49 insertions(+), 43 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 0a5225226..632f99342 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1142,30 +1142,7 @@ typedef struct nv3_grobj_s #define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START 0x0012 #define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017 -// Class methods -void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); + // This area is used for holding universal representations of the U* registers... extern struct nv3_object_class_001 nv3_beta_factor; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 07c30a9ac..3c696bf92 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1142,6 +1142,7 @@ typedef struct nv3_pgraph_s uint32_t trapped_instance; } nv3_pgraph_t; + // GPU Manufacturing Configuration (again) // In the future this will be configurable typedef struct nv3_pextdev_s @@ -1455,8 +1456,33 @@ void nv3_pgraph_init(); uint32_t nv3_pgraph_read(uint32_t address); void nv3_pgraph_write(uint32_t address, uint32_t value); void nv3_pgraph_vblank_start(svga_t* svga); -void nv3_pgraph_submit(uint32_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context); +void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context); +// PGRAPH class methods +// this should be in "vid_nv3_classes.h", but before that can happen, some things need to be rejigged +void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); // NV3 PFIFO void nv3_pfifo_init(); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 31630dae2..a836fdd21 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -678,7 +678,7 @@ void nv3_pfifo_cache0_pull() // There is only one entry for cache0 uint8_t current_channel = nv3->pfifo.cache0_settings.channel; uint8_t current_subchannel = nv3->pfifo.cache0_entry.subchannel; - uint32_t current_name = nv3->pfifo.cache0_entry.data; + uint32_t current_param = nv3->pfifo.cache0_entry.data; uint16_t current_method = nv3->pfifo.cache0_entry.method; // i.e. there is no method in cache0, so we have to find the object. @@ -687,7 +687,7 @@ void nv3_pfifo_cache0_pull() // flip the get address over nv3->pfifo.cache0_settings.get_address ^= 0x04; - if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel)) + if (!nv3_ramin_find_object(current_param, 0, current_channel, current_subchannel)) return; // interrupt was fired, and we went to ramro } @@ -713,9 +713,9 @@ void nv3_pfifo_cache0_pull() nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; - nv3_debug_ramin_print_context_info(current_name, context_structure); + nv3_debug_ramin_print_context_info(current_param, context_structure); - nv3_pgraph_submit(current_name, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); + nv3_pgraph_submit(current_param, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); #endif } @@ -841,13 +841,13 @@ void nv3_pfifo_cache1_pull() uint8_t current_channel = nv3->pfifo.cache1_settings.channel; uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_index].subchannel; - uint32_t current_name = nv3->pfifo.cache1_entries[get_index].data; + uint32_t current_param = nv3->pfifo.cache1_entries[get_index].data; uint16_t current_method = nv3->pfifo.cache1_entries[get_index].method; // NV_ROOT if (!current_method) { - if (!nv3_ramin_find_object(current_name, 1, current_channel, current_subchannel)) + if (!nv3_ramin_find_object(current_param, 1, current_channel, current_subchannel)) return; // interrupt was fired, and we went to ramro } @@ -882,9 +882,9 @@ void nv3_pfifo_cache1_pull() #ifndef RELEASE_BUILD nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; - nv3_debug_ramin_print_context_info(current_name, context_structure); + nv3_debug_ramin_print_context_info(current_param, context_structure); - nv3_pgraph_submit(current_name, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); + nv3_pgraph_submit(current_param, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); #endif //Todo: finish it diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index ffbaa7f01..3cae7b872 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -27,7 +27,7 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> - +#include <86box/nv/classes/vid_nv3_classes.h> // Initialise the PGRAPH subsystem. void nv3_pgraph_init() @@ -474,12 +474,15 @@ void nv3_pgraph_arbitrate_method(uint32_t name, uint16_t method, uint8_t channel /* Obtain the grobj information from the context in ramin */ nv3_grobj_t grobj = {0}; - grobj.grobj_0 = nv3_ramin_read32(context.ramin_offset, nv3); - grobj.grobj_1 = nv3_ramin_read32(context.ramin_offset + 4, nv3); - grobj.grobj_2 = nv3_ramin_read32(context.ramin_offset + 8, nv3); - grobj.grobj_3 = nv3_ramin_read32(context.ramin_offset + 12, nv3); + // we need to shift left by 4 to get the real address, something to do with the 16 byte unit of reversal + uint32_t real_ramin_base = context.ramin_offset << 4; - nv_log("**** About to execute method **** obj name=0x%08x, method=0x%04x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x", + grobj.grobj_0 = nv3_ramin_read32(real_ramin_base, nv3); + grobj.grobj_1 = nv3_ramin_read32(real_ramin_base + 4, nv3); + grobj.grobj_2 = nv3_ramin_read32(real_ramin_base + 8, nv3); + grobj.grobj_3 = nv3_ramin_read32(real_ramin_base + 12, nv3); + + nv_log("**** About to execute method **** obj name=0x%08x, method=0x%04x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", name, method, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); // By this point, we already ANDed the class ID to 0x1F. @@ -559,7 +562,7 @@ void nv3_pgraph_arbitrate_method(uint32_t name, uint16_t method, uint8_t channel } /* Arbitrates graphics object submission to the right object types */ -void nv3_pgraph_submit(uint32_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) +void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) { // class id can be derived from the context but we debug log it before we get here // Do we need to read grobj here? @@ -568,12 +571,12 @@ void nv3_pgraph_submit(uint32_t name, uint16_t method, uint8_t channel, uint8_t { // This method is how we figure out which methods exist. case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("I'm an Nvidia Object! name=0x%08x channel=%d.%d class=0x%02x (%s) method=0x%04x, context=0x%08x\n", - name, channel, subchannel, class_id, nv3_class_names[class_id], method, context); + nv_log("I'm an Nvidia Object! channel=%d.%d class=0x%02x (%s) method=0x%04x parameter=0x%08x, context=0x%08x\n", + channel, subchannel, class_id, nv3_class_names[class_id], method, param, context); break; default: // Object Method orchestration - nv3_pgraph_arbitrate_method(name, method, channel, subchannel, class_id, context); + nv3_pgraph_arbitrate_method(param, method, channel, subchannel, class_id, context); break; } } \ No newline at end of file From 18277c1bf949d73e1f6468bea855f3e64d6c6df6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 13 Mar 2025 13:01:29 +0000 Subject: [PATCH 112/274] Move some defines around and add the rendering files. Add some basic things as to what we have to do next (These won't bein the final thing) --- doc/nvidia_notes/NV128.xlsx | Bin 0 -> 9325 bytes .../86box/nv/classes/vid_nv3_classes.h | 12 +++++ src/include/86box/nv/vid_nv3.h | 10 ---- src/video/CMakeLists.txt | 2 + src/video/nv/nv3/render/nv3_render.h | 19 +++++++ src/video/nv/nv3/render/nv3_render_core.c | 32 +++++++++++ src/video/nv/nv3/subsystems/nv3_pgraph.c | 50 +++++++++--------- 7 files changed, 90 insertions(+), 35 deletions(-) create mode 100644 doc/nvidia_notes/NV128.xlsx create mode 100644 src/video/nv/nv3/render/nv3_render.h create mode 100644 src/video/nv/nv3/render/nv3_render_core.c diff --git a/doc/nvidia_notes/NV128.xlsx b/doc/nvidia_notes/NV128.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..e293a97ebdeea621058b4c580a4a72be07c06e12 GIT binary patch literal 9325 zcmeHtg;!k3_I2Zs;1WEzySoH;m*DO$!QEXN*C2ra0fIK}?jGDB!QJ&o^4|MqCNtk( z@Lu&=RjYg5eb()&+WXYq=PF1;K%xVn0k8l7fCylClx4091^~oC0sv?LSa2<2J6mTH zTW38LcY6~j9eOt#Yr;H8aLOD2_{;VGYyZVFP?|U-*Tsk|dM)uFyhSIqR3!+@b{Noy zO0CG>-ks1}Vx*OAVey{ydiTS4I*ES^H%oIsnlw4n0TJ>R60gp4HiTzcc8TcAMnUYW{Jslo9sMY`3A zvYur|-w1q#F(j@9ad~tVx~Y}ptt=}}RdK{ciDqw{6-}F$wwFg6WlZFS!d)XfhPfV{ zR<@u&QNZLJK*1`q=1m#1?U;AB07kyd&`BrZ@;%u)8eaD*u5n{_Y@D$i7O@TOT0vj7 zh&&eub%4+3{(*YVcKJgiJTKeA379QN(VJ)VE0o>F^L8QRfp#KN@6f}w{#_o=gYj*x zz@yXTU0>!WXaL~(83Lg27h2Y;GLl@p>@}Ge*1dkArJkdSwG#vV&;EaO{4eIjn+J}K^U8wDP+3Qiz|xNnQk!{FjF zZ}eV2(bWcPX(TE-4++S%EF|U5;R6gcxnr`JL+N@qip$L9%vGAWlslzMODy%5`l4Lv zfmIT*sZ)_k zVO%l?lW7?JPKIXl#;)RWZeTnu;CA|A@9rFMoo#2Ex+y1g&AYa2u_E(d^G2ncb8wotvG1XAsZA;uUA*Eb zlP#n+R#n+`?_i@*Vht#NU(F$4JZp;owS7;_AD7syIpMsx<`pPUr+`7QAAo>vum?L})oGlhXrk1Bth0eb64}l66w#}~Xk90jY_uiC##WK)L z*_IaX?v1a|P#xutiTDV?bLNg$(87G3&#}fF@XXLw$w`jqu39KTM!*L4)4bg<$Q4MK zDT))J5J`IT&qF^Fafi`w<5u~m7#gu@At~?~bies_kHy;Tx%TLLGH0iE9Y$2wdZ2{v zYGzoipc`fpXVkBabS)k=a_F85rR0=j-7^~BAH!_ckuj2Y^bZHh>Zca$#1B_+3@i;J zE^QVcHnAAWHxpJpYP@mBhC8965M%N4%43v3i z2I2$NeI(d{8mdKdA{L*ERb1*uo%i3Q86fOJ+>b~4T&~#=Hz3e1J7|g`P$50gtdDu1 z>_*Ngov7sZ6(@8-y3Hpg#t<6HJ_A!%6ZYxC173rio~7 zIz+Ev&zc`hW!*=uI`Z$}xADG6zb#?o^9pe$4DA;u@TCGeZRe#msUEL83*8S=wJn~} z4qY6ZZVmL!tiG)D-v!nTxX!=zBCr%M>WcMp#lHpC$=t-m*@@xT!1PmTGZUm^GZ@i> zuaoWwXph|!f^y;%$rYz}OZJ=&Q>7~cm};|9N}jG8po6igGR#Q@d$n7g%DtQ28v8>s z1#xp10>peI;A*s!@|H0#X2;4>6b)&uq`wutdF25m{4x2X0Ntn*feeB^9IB@B_`(7` z5_p$Y-0)3F;F~rTDQVMF)nkY$3w@L41nU4!_|N{vc?A$ev$2dSs&I(7J+Y{oJc6vO z!+E~Sk)uoIK!Jb+8G@LszN7=>O0?*T*|$>RTem~4s_BO~2luE2Q3;W~G`&0x0~hD6 zQcCt^Q6;6ZTlyznt53YCFj29e?w<%cMJ#gGNtd8ob2nl&BFIT-d;-Y`f@H;0wdk`5 zL^Z~J$M)wHIY?U&^ zp~dv}^Lfpg;c8?!e+0wYPM0Gg5zL3FQqPL8*11G&OM=t@+^ug}y zMlU5w6wYxUM~ltJUAy!|g-Ro%wlC+H$oC6*_IrI2`^xbtvj|u*Orjs!>PA%qk-bo< zmK?egD~I&e6G8OmnRoNXK)LF)bK|e{9`9=*jOsd1sn*4fk{(#5#YYeOyZCV3rbwk7 z;6lMer=OqU1IXGZ6_nVm|npkgy7-HSI{J>?x#I!haU2XxvQ({ zXz1?fraN$zBnArG6G=^k&#i557p)dmQewYuD8az?oXls#G;)t$?rOqBz19xhz*Vzx zb$jNz5}y6I>(danKdyq0jOviJFe9r_XdI1^tdFqp|^IMhB z8==+jyI&Hsi?In5Mh77Tq(XQT2R-TBQ3vPI8;68B5Gl=+cleQ(xpOjAW9=SHcwmyM zBP>hzR^Dxw<{A1x~jgar7^f}Qv>VhS zhUl*`$#h0o?X-KgKX~*d`x`*I@g~@7GT_MhiL=4clp8>~87EY1XzIE-2UgmdyZOIe zB`w|4!R`y{o?}r zjk89$F=Oms-1(~3-?Qht<~v5~jXwFh0u^_O#f_9B-|mu@vb!4b<%x5{ebzo)I=fxD zd;OEbzt*OTN}nqZoJDomdHnFao?3>}!rt#U8`Kri7>+u)Zn zIGdZ;m@xe6e~H3@#z-VC2YMUkodCR(>jT?nEZNH1n03N3sc}{!UM=WAQH_Ne*o=z? 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This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. + /* Class context switch method */ typedef struct nv3_class_ctx_switch_method_s { diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 3c696bf92..6a316e928 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -627,16 +627,6 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_CLASS1C_MEM2IMAGE_START 0x5C0000 // class 55, 56, 62, 63? #define NV3_PGRAPH_CLASS1C_MEM2IMAGE_END 0x5C1FFF -/* - OBJECT METHODS -*/ - -// Global stuff -#define NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE 0x0 // I'm going insane at 00:48 14/02/2025 -#define NV3_SET_NOTIFY_CONTEXT_FOR_DMA 0x100 // Set object ctx for dma...see nv3_dma_context_t structure -#define NV3_SET_NOTIFY 0x104 - -#define NV3_W95TXT_COLORA 0x3FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. #define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers #define NV3_PGRAPH_REAL_END 0x5C1FFF diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index db6b8de2d..03d2b504a 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -124,6 +124,8 @@ add_library(vid OBJECT nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c nv/nv3/classes/nv3_class_018_point_zeta_buffer.c nv/nv3/classes/nv3_class_01c_image_in_memory.c + + nv/nv3/render/nv3_render_core.c ) diff --git a/src/video/nv/nv3/render/nv3_render.h b/src/video/nv/nv3/render/nv3_render.h new file mode 100644 index 000000000..98131680d --- /dev/null +++ b/src/video/nv/nv3/render/nv3_render.h @@ -0,0 +1,19 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 headers for rendering + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ + + #pragma once + diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c new file mode 100644 index 000000000..a26d7ef15 --- /dev/null +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -0,0 +1,32 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 Core rendering code (Software version) + * + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 Connor Hyde + */ + + #include + #include + #include + #include + #include <86box/86box.h> + #include <86box/device.h> + #include <86box/mem.h> + #include <86box/pci.h> + #include <86box/rom.h> + #include <86box/video.h> + #include <86box/nv/vid_nv.h> + #include <86box/nv/vid_nv3.h> + #include <86box/nv/classes/vid_nv3_classes.h> + + \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 3cae7b872..35e5c8e0d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -469,7 +469,7 @@ void nv3_pgraph_vblank_start(svga_t* svga) } /* Sends off method execution to the right class */ -void nv3_pgraph_arbitrate_method(uint32_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) +void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) { /* Obtain the grobj information from the context in ramin */ nv3_grobj_t grobj = {0}; @@ -482,78 +482,78 @@ void nv3_pgraph_arbitrate_method(uint32_t name, uint16_t method, uint8_t channel grobj.grobj_2 = nv3_ramin_read32(real_ramin_base + 8, nv3); grobj.grobj_3 = nv3_ramin_read32(real_ramin_base + 12, nv3); - nv_log("**** About to execute method **** obj name=0x%08x, method=0x%04x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", - name, method, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); + nv_log("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", + method, param, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); // By this point, we already ANDed the class ID to 0x1F. // Send the grobj, the context, the method and the name off to actually be acted upon. switch (class_id) { case nv3_pgraph_class01_beta_factor: - nv3_class_001_method(name, method, context, grobj); + nv3_class_001_method(param, method, context, grobj); break; case nv3_pgraph_class02_rop: - nv3_class_002_method(name, method, context, grobj); + nv3_class_002_method(param, method, context, grobj); break; case nv3_pgraph_class03_chroma_key: - nv3_class_003_method(name, method, context, grobj); + nv3_class_003_method(param, method, context, grobj); break; case nv3_pgraph_class04_plane_mask: - nv3_class_004_method(name, method, context, grobj); + nv3_class_004_method(param, method, context, grobj); break; case nv3_pgraph_class05_clipping_rectangle: - nv3_class_005_method(name, method, context, grobj); + nv3_class_005_method(param, method, context, grobj); break; case nv3_pgraph_class06_pattern: - nv3_class_006_method(name, method, context, grobj); + nv3_class_006_method(param, method, context, grobj); break; case nv3_pgraph_class07_rectangle: - nv3_class_007_method(name, method, context, grobj); + nv3_class_007_method(param, method, context, grobj); break; case nv3_pgraph_class08_point: - nv3_class_008_method(name, method, context, grobj); + nv3_class_008_method(param, method, context, grobj); break; case nv3_pgraph_class09_line: - nv3_class_009_method(name, method, context, grobj); + nv3_class_009_method(param, method, context, grobj); break; case nv3_pgraph_class0a_lin: - nv3_class_00a_method(name, method, context, grobj); + nv3_class_00a_method(param, method, context, grobj); break; case nv3_pgraph_class0b_triangle: - nv3_class_00b_method(name, method, context, grobj); + nv3_class_00b_method(param, method, context, grobj); break; case nv3_pgraph_class0c_w95txt: - nv3_class_00c_method(name, method, context, grobj); + nv3_class_00c_method(param, method, context, grobj); break; case nv3_pgraph_class0d_m2mf: - nv3_class_00d_method(name, method, context, grobj); + nv3_class_00d_method(param, method, context, grobj); break; case nv3_pgraph_class0e_scaled_image_from_memory: - nv3_class_00e_method(name, method, context, grobj); + nv3_class_00e_method(param, method, context, grobj); break; case nv3_pgraph_class10_blit: - nv3_class_010_method(name, method, context, grobj); + nv3_class_010_method(param, method, context, grobj); break; case nv3_pgraph_class11_image: - nv3_class_011_method(name, method, context, grobj); + nv3_class_011_method(param, method, context, grobj); break; case nv3_pgraph_class12_bitmap: - nv3_class_012_method(name, method, context, grobj); + nv3_class_012_method(param, method, context, grobj); break; case nv3_pgraph_class14_transfer2memory: - nv3_class_014_method(name, method, context, grobj); + nv3_class_014_method(param, method, context, grobj); break; case nv3_pgraph_class15_stretched_image_from_cpu: - nv3_class_015_method(name, method, context, grobj); + nv3_class_015_method(param, method, context, grobj); break; case nv3_pgraph_class17_d3d5tri_zeta_buffer: - nv3_class_017_method(name, method, context, grobj); + nv3_class_017_method(param, method, context, grobj); break; case nv3_pgraph_class18_point_zeta_buffer: - nv3_class_018_method(name, method, context, grobj); + nv3_class_018_method(param, method, context, grobj); break; case nv3_pgraph_class1c_image_in_memory: - nv3_class_01c_method(name, method, context, grobj); + nv3_class_01c_method(param, method, context, grobj); break; default: fatal("NV3 (nv3_pgraph_arbitrate_method): Attempted to execute method on invalid, or unimplemented, class ID %s", nv3_class_names[class_id]); From 0b62b3252704d726ecaa6ba07da19580d85a00db Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 13 Mar 2025 13:04:33 +0000 Subject: [PATCH 113/274] Whoops --- .../nv3_render.h => include/86box/nv/render/vid_nv3_render.h} | 0 src/video/nv/nv3/render/nv3_render_core.c | 1 + 2 files changed, 1 insertion(+) rename src/{video/nv/nv3/render/nv3_render.h => include/86box/nv/render/vid_nv3_render.h} (100%) diff --git a/src/video/nv/nv3/render/nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h similarity index 100% rename from src/video/nv/nv3/render/nv3_render.h rename to src/include/86box/nv/render/vid_nv3_render.h diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index a26d7ef15..5fd450260 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -29,4 +29,5 @@ #include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> + \ No newline at end of file From fae3d1023872fda5b8a6f9ad4a49d59726ff8238 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 13 Mar 2025 13:38:09 +0000 Subject: [PATCH 114/274] Move class globals to pgraph. --- .../86box/nv/classes/vid_nv3_classes.h | 57 ++++++++++--------- src/include/86box/nv/render/vid_nv3_render.h | 2 +- src/include/86box/nv/vid_nv3.h | 26 ++++++++- .../nv3/classes/nv3_class_001_beta_factor.c | 3 - src/video/nv/nv3/classes/nv3_class_002_rop.c | 2 - .../nv/nv3/classes/nv3_class_003_chroma_key.c | 3 - .../nv/nv3/classes/nv3_class_004_plane_mask.c | 3 - .../nv3_class_005_clipping_rectangle.c | 3 - .../nv/nv3/classes/nv3_class_006_pattern.c | 3 - .../nv/nv3/classes/nv3_class_007_rectangle.c | 3 - .../nv/nv3/classes/nv3_class_008_point.c | 3 - src/video/nv/nv3/classes/nv3_class_009_line.c | 3 - src/video/nv/nv3/classes/nv3_class_00a_lin.c | 3 - .../nv/nv3/classes/nv3_class_00b_triangle.c | 3 - .../classes/nv3_class_00c_win95_gdi_text.c | 3 - src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 3 - .../nv3_class_00e_scaled_image_from_mem.c | 3 - src/video/nv/nv3/classes/nv3_class_010_blit.c | 3 - .../nv/nv3/classes/nv3_class_011_image.c | 3 - .../nv/nv3/classes/nv3_class_012_bitmap.c | 3 - .../classes/nv3_class_014_transfer2memory.c | 3 - .../nv3_class_015_stretched_image_from_cpu.c | 3 - .../nv3_class_017_d3d5_tri_zeta_buffer.c | 3 - .../classes/nv3_class_018_point_zeta_buffer.c | 1 - .../classes/nv3_class_01c_image_in_memory.c | 3 - .../nv/nv3/classes/nv3_class_shared_methods.c | 1 - 26 files changed, 55 insertions(+), 94 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index c33927090..0e2a27b74 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -132,7 +132,9 @@ typedef struct nv3_color_16_a4r4g4b4_s uint8_t b : 4; } nv3_color_16_a4r4g4b4_t; -/* A1R5G5B5 format */ +/* A1R5G5B5 format + Can also be used for R5G5B5 +*/ typedef struct nv3_color_16_a1r5g5b5_s { uint8_t a : 1; @@ -233,6 +235,31 @@ typedef struct nv3_object_class_001 // Put the rest of it here } nv3_beta_factor_t; +/* Note: This is not used in the class, there are "special" rops that do certain things. So they need to be defined for code readability. It all gets optimised away +by the compiler anyway */ +typedef enum nv3_render_operation_type_e +{ + // Black + nv3_rop_blackness = 0x00, + // dst = !src + nv3_rop_dstinvert = 0x55, + // pattern invert + nv3_rop_patinvert = 0x5A, + // src ^ dst + nv3_rop_xor = 0x66, + // src & dst + nv3_rop_srcand = 0x88, + // dst = src (?) + nv3_rop_dstcopy = 0xAA, + // src = dst (?) + nv3_rop_srccopy = 0xCC, + // paint source + nv3_rop_srcpaint = 0xEE, + // pattern copy + nv3_rop_patcopy = 0xF0, + // White + nv3_rop_whiteness = 0xFF, +} nv3_render_operation_type; /* Object class 0x02 (real hardware) 0x14/0x43 (drivers) @@ -1152,30 +1179,4 @@ typedef struct nv3_grobj_s // PIO Subchannel info #define NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE 0x0010 #define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START 0x0012 -#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017 - - - -// This area is used for holding universal representations of the U* registers... -extern struct nv3_object_class_001 nv3_beta_factor; -extern struct nv3_object_class_002 nv3_rop; -extern struct nv3_object_class_003 nv3_chroma_key; -extern struct nv3_object_class_004 nv3_plane_mask; -extern struct nv3_object_class_005 nv3_clipping_rectangle; -extern struct nv3_object_class_006 nv3_pattern; -extern struct nv3_object_class_007 nv3_rectangle; -extern struct nv3_object_class_008 nv3_point; -extern struct nv3_object_class_009 nv3_line; -extern struct nv3_object_class_00A nv3_lin; -extern struct nv3_object_class_00B nv3_triangle; -extern struct nv3_object_class_00C nv3_win95_gdi_text; -extern struct nv3_object_class_00D nv3_m2mf; -extern struct nv3_object_class_00E nv3_scaled_image_from_memory; -extern struct nv3_object_class_010 nv3_blit; -extern struct nv3_object_class_011 nv3_image; -extern struct nv3_object_class_012 nv3_bitmap; -extern struct nv3_object_class_014 nv3_transfer2memory; -extern struct nv3_object_class_015 nv3_stretched_image_from_cpu; -extern struct nv3_object_class_017 nv3_d3d5_tri; -extern struct nv3_object_class_018 nv3_point_zeta_buffer; -extern struct nv3_object_class_01C nv3_image_in_memory; \ No newline at end of file +#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017 \ No newline at end of file diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 98131680d..fd6ad8abf 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -15,5 +15,5 @@ * Copyright 2024-2025 Connor Hyde */ - #pragma once +#pragma once diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 6a316e928..e2a74aba1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -23,6 +23,7 @@ #pragma once #include <86box/nv/classes/vid_nv3_classes.h> +#include <86box/nv/render/vid_nv3_render.h> // The GPU base structure extern const device_config_t nv3_config[]; @@ -818,7 +819,6 @@ extern const device_config_t nv3_config[]; #define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F - /* STRUCTURES FOR THE GPU START HERE OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H @@ -1130,6 +1130,30 @@ typedef struct nv3_pgraph_s uint32_t trapped_address; uint32_t trapped_data; uint32_t trapped_instance; + + /* This area is used for holding universal representations of the U* registers, which are actually mapped into MMIO */ + struct nv3_object_class_001 beta_factor; + struct nv3_object_class_002 rop; + struct nv3_object_class_003 chroma_key; + struct nv3_object_class_004 plane_mask; + struct nv3_object_class_005 clipping_rectangle; + struct nv3_object_class_006 pattern; + struct nv3_object_class_007 rectangle; + struct nv3_object_class_008 point; + struct nv3_object_class_009 line; + struct nv3_object_class_00A lin; + struct nv3_object_class_00B triangle; + struct nv3_object_class_00C win95_gdi_text; + struct nv3_object_class_00D m2mf; + struct nv3_object_class_00E scaled_image_from_memory; + struct nv3_object_class_010 blit; + struct nv3_object_class_011 image; + struct nv3_object_class_012 bitmap; + struct nv3_object_class_014 transfer2memory; + struct nv3_object_class_015 stretched_image_from_cpu; + struct nv3_object_class_017 d3d5_tri; + struct nv3_object_class_018 point_zeta_buffer; + struct nv3_object_class_01C image_in_memory; } nv3_pgraph_t; diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 2dc6a4022..b03a6cc21 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_001 beta_factor; void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index f5a1c343e..f4102a605 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -27,9 +27,7 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> -struct nv3_object_class_002 nv3_rop; void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 8b99fa808..e86cea995 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_003 nv3_chroma_key; void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index e32eb6333..f26dba5ef 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_004 nv3_plane_mask; void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index b5d4a5b80..456bf6a20 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -26,9 +26,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_005 nv3_clipping_rectangle; void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index 8442bde0d..2eb9755b6 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_006 nv3_pattern; void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 9b0908b8d..cb4d34eaf 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_007 nv3_rectangle; void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 4ecfa6d87..3e0bba3b1 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_008 nv3_point; void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index c8104cd9c..51a637cc4 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_009 nv3_line; void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 8e83c2433..46d538095 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -28,9 +28,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_00A nv3_lin; void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index 766597af1..219e36b62 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_00B nv3_triangle; void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index cceece8b7..17dcfd1a1 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_00C nv3_win95_gdi_text; void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 6e2569cd9..a0b2773d4 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_00D nv3_m2mf; void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index e5cbb9634..d0e4970c2 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_00E nv3_scaled_image_from_mem; void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 7c1e9626f..50149cd54 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_010 nv3_blit; void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index d7a2a7987..404ee3774 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_011 nv3_image; void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index 63a5f8e1d..8cba8c6c6 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -28,9 +28,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_012 nv3_bitmap; void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index 197235c75..a1112b1c9 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -28,9 +28,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_014 nv3_transfer2memory; void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index 1ab61faed..34997d724 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_015 nv3_stretched_image_from_cpu; void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 2bb2bfd77..2c4b88cfa 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_017 nv3_d3d5_tri; void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 68747c9ce..2ba880306 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -27,7 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 0efb6c8ce..2f7440555 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -27,9 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -struct nv3_object_class_01C nv3_image_in_memory; void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index eb0469823..919fc5eb3 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -27,7 +27,6 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { From 12276374d5ed9c521ffe6b6cee420121fa2c469e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 13 Mar 2025 13:43:17 +0000 Subject: [PATCH 115/274] Fix compile --- src/include/86box/nv/vid_nv3.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index e2a74aba1..a1124bad8 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1132,10 +1132,10 @@ typedef struct nv3_pgraph_s uint32_t trapped_instance; /* This area is used for holding universal representations of the U* registers, which are actually mapped into MMIO */ - struct nv3_object_class_001 beta_factor; - struct nv3_object_class_002 rop; - struct nv3_object_class_003 chroma_key; - struct nv3_object_class_004 plane_mask; + struct nv3_object_class_001 beta_factor_class; + struct nv3_object_class_002 rop_class; + struct nv3_object_class_003 chroma_key_class; + struct nv3_object_class_004 plane_mask_class; struct nv3_object_class_005 clipping_rectangle; struct nv3_object_class_006 pattern; struct nv3_object_class_007 rectangle; From 1af8bf7d78843cad1931f21e8ae0584b0c7a020f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 15 Mar 2025 13:45:13 +0000 Subject: [PATCH 116/274] Implement PGRAPH invalid method functionality --- src/include/86box/nv/classes/vid_nv3_classes.h | 16 ++++++++++------ src/include/86box/nv/vid_nv3.h | 16 ++++++++++++---- .../nv/nv3/classes/nv3_class_001_beta_factor.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_002_rop.c | 9 +++++++-- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 8 +++++++- .../nv/nv3/classes/nv3_class_004_plane_mask.c | 8 +++++++- .../classes/nv3_class_005_clipping_rectangle.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_006_pattern.c | 8 +++++++- .../nv/nv3/classes/nv3_class_007_rectangle.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_008_point.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_009_line.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 8 +++++++- .../nv/nv3/classes/nv3_class_00b_triangle.c | 8 +++++++- .../nv3/classes/nv3_class_00c_win95_gdi_text.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 8 +++++++- .../nv3_class_00e_scaled_image_from_mem.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_010_blit.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_011_image.c | 8 +++++++- src/video/nv/nv3/classes/nv3_class_012_bitmap.c | 8 +++++++- .../nv3/classes/nv3_class_014_transfer2memory.c | 8 +++++++- .../nv3_class_015_stretched_image_from_cpu.c | 8 +++++++- .../classes/nv3_class_017_d3d5_tri_zeta_buffer.c | 8 +++++++- .../classes/nv3_class_018_point_zeta_buffer.c | 8 +++++++- .../nv3/classes/nv3_class_01c_image_in_memory.c | 8 +++++++- .../nv/nv3/classes/nv3_class_shared_methods.c | 8 +++++++- src/video/nv/nv3/subsystems/nv3_pgraph.c | 11 ++++++++++- 26 files changed, 193 insertions(+), 35 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 0e2a27b74..c015d0659 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -73,12 +73,16 @@ typedef enum nv3_pgraph_class_e */ // Global stuff -#define NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE 0x0 // I'm going insane at 00:48 14/02/2025 -#define NV3_SET_NOTIFY_CONTEXT_FOR_DMA 0x100 // Set object ctx for dma...see nv3_dma_context_t structure -#define NV3_SET_NOTIFY 0x104 +#define NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE 0x0 // I'm going insane at 00:48 14/02/2025 +#define NV3_SET_NOTIFY_CONTEXT_FOR_DMA 0x0100 // Set object ctx for dma...see nv3_dma_context_t structure +#define NV3_SET_NOTIFY 0x0104 -#define NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE 0x304 -#define NV3_W95TXT_COLORA 0x3FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. +#define NV3_IMAGE_IN_MEMORY_COLOR_FORMAT 0x0300 +#define NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE 0x0304 +#define NV3_IMAGE_IN_MEMORY_PITCH 0x0308 +#define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET 0x030C + +#define NV3_W95TXT_COLORA 0x03FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. /* Class context switch method */ typedef struct nv3_class_ctx_switch_method_s @@ -1085,7 +1089,7 @@ typedef struct nv3_d3d5_coordinate_s float x; // X coordinate in 3d space of the triangle float y; // Y coordinate in 3d space of the triangle float z; // Z coordinate in 3d space of the triangle - float m; // "Measurement dimension" apparently, allows for more precise measurements. And curves + float m; // 1/W for projection float u; // U coordinate within texture for the (top left?) of the triangle where sampling starts. float v; // V coordinate within texture for the (top left?) of the triangle where sampling starts. } nv3_d3d5_coordinate_t; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index a1124bad8..3c99782e6 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 11 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 13 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -520,10 +520,16 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_DEBUG_3_ALPHA_CHECK 24 #define NV3_PGRAPH_INTR_0 0x400100 +#define NV3_PGRAPH_INTR_0_VBLANK 8 // Fired every frame +#define NV3_PGRAPH_INTR_0_VBLANK_ENABLED 0x1 // Is the vblank interrupt enabled? + #define NV3_PGRAPH_INTR_1 0x400104 +#define NV3_PGRAPH_INTR_1_INVALID_METHOD 0 // Invalid method +#define NV3_PGRAPH_INTR_1_INVALID_DATA 4 // Invalid data. Not sure when this would be triggered. +#define NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY 12 // Tried to notify while a notify was pending. +#define NV3_PGRAPH_INTR_1_CTXSW_NOTIFY 16 // Notify fired for software context + #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 -#define NV3_PGRAPH_INTR_EN_0_VBLANK 8 // Fired every frame -#define NV3_PGRAPH_INTR_EN_0_VBLANK_ENABLED 0x1 // Is the vblank interrupt enabled? //todo: add what this does #define NV3_PGRAPH_INTR_EN_1 0x400144 // Interrupt Control for PGRAPH #2 (it can receive two at onc) #define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // DMA context switcher @@ -1470,6 +1476,8 @@ void nv3_pgraph_init(); uint32_t nv3_pgraph_read(uint32_t address); void nv3_pgraph_write(uint32_t address, uint32_t value); void nv3_pgraph_vblank_start(svga_t* svga); +void nv3_pgraph_interrupt_valid(uint32_t num); +void nv3_pgraph_interrupt_invalid(uint32_t num); void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context); // PGRAPH class methods @@ -1491,7 +1499,7 @@ void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_co void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index b03a6cc21..e21189213 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -30,5 +30,11 @@ void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index f4102a605..b771551d3 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -28,8 +28,13 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> - void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index e86cea995..73901d08d 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -30,5 +30,11 @@ void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index f26dba5ef..48a96ab96 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -30,5 +30,11 @@ void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 456bf6a20..1119147e7 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -29,5 +29,11 @@ void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index 2eb9755b6..c8c81066f 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -30,5 +30,11 @@ void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index cb4d34eaf..69e66ca31 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -30,5 +30,11 @@ void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 3e0bba3b1..0cd44b8cd 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -30,5 +30,11 @@ void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index 51a637cc4..8d71f4d5e 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -30,5 +30,11 @@ void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 46d538095..141a2422c 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -31,5 +31,11 @@ void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index 219e36b62..91cbaa837 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -30,5 +30,11 @@ void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 17dcfd1a1..3ba352b3c 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -30,5 +30,11 @@ void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index a0b2773d4..888ac89cf 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -30,5 +30,11 @@ void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index d0e4970c2..bf0286c20 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -30,5 +30,11 @@ void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 50149cd54..da2f16bda 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -30,5 +30,11 @@ void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 404ee3774..4499693df 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -30,5 +30,11 @@ void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index 8cba8c6c6..ca8540b75 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -31,5 +31,11 @@ void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index a1112b1c9..6a18ff1d7 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -31,5 +31,11 @@ void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index 34997d724..c8560ad0f 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -30,5 +30,11 @@ void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 2c4b88cfa..2acb22a08 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -30,5 +30,11 @@ void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 2ba880306..80f10797f 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -32,5 +32,11 @@ struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 2f7440555..a74313276 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -30,5 +30,11 @@ void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 919fc5eb3..555a180e6 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -30,7 +30,13 @@ void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - + switch (method_id) + { + default: + nv_log("Shared Generic Methods: Invalid or Unimplemented method 0x%04x", method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + return; + } } void nv3_notify() diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 35e5c8e0d..802d98d10 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -462,10 +462,19 @@ void nv3_pgraph_interrupt_valid(uint32_t num) nv3_pmc_handle_interrupts(true); } +// Fire an INVALID pgraph interrupt +void nv3_pgraph_interrupt_invalid(uint32_t num) +{ + nv3->pgraph.interrupt_status_1 |= (1 << num); + + // Some code in pcbox hat enables the "reserved" bit HERE if it's set in intr 0. What??? + nv3_pmc_handle_interrupts(true); +} + // VBlank. Fired every single frame. void nv3_pgraph_vblank_start(svga_t* svga) { - nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_EN_0_VBLANK); + nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_VBLANK); } /* Sends off method execution to the right class */ From 6c05cecbcfcfa92868efd99ed27eb16999596277 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 17 Mar 2025 00:18:13 +0000 Subject: [PATCH 117/274] Institute video stdlib --- doc/nvidia_notes/NV3 DMA Engine.txt | 6 + src/include/86box/utils/video_stdlib.h | 20 + src/utils/CMakeLists.txt | 3 + src/utils/video/video_rop.c | 786 ++++++++++++++++++++++ src/video/nv/nv3/render/nv3_render_core.c | 81 ++- 5 files changed, 866 insertions(+), 30 deletions(-) create mode 100644 src/include/86box/utils/video_stdlib.h create mode 100644 src/utils/video/video_rop.c diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt index 6cae9d131..fe2d61508 100644 --- a/doc/nvidia_notes/NV3 DMA Engine.txt +++ b/doc/nvidia_notes/NV3 DMA Engine.txt @@ -42,4 +42,10 @@ DMA_OBJECT STRUCTURE IN RESOURCE MANAGER: 0x34c: base address? 0x374: actually do the transfer +some objects don't actually need to do dma, for example, video patchcord, it just creates a structure in the driver, and rop just allocate ssome memory to put the data for the patchcord/rop thing + +dma start=nv3_mini dc67 +call of mthdCreate for ***DRIVER*** CLASS ID: a7b44, check ptr + + diff --git a/src/include/86box/utils/video_stdlib.h b/src/include/86box/utils/video_stdlib.h new file mode 100644 index 000000000..f8e2ed5af --- /dev/null +++ b/src/include/86box/utils/video_stdlib.h @@ -0,0 +1,20 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Standard library for implementation of video functionality that is duplicated across multiple cards. + * + * + * + * Authors: Connor Hyde + * + * Copyright 2025 Connor Hyde + */ + + +/* ROP */ +int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src, int32_t out); \ No newline at end of file diff --git a/src/utils/CMakeLists.txt b/src/utils/CMakeLists.txt index 2ffe41f7b..ddc423cab 100644 --- a/src/utils/CMakeLists.txt +++ b/src/utils/CMakeLists.txt @@ -23,4 +23,7 @@ add_library(utils OBJECT ini.c log.c random.c + + # VIDEO + video/video_rop.c ) diff --git a/src/utils/video/video_rop.c b/src/utils/video/video_rop.c new file mode 100644 index 000000000..b6350b2e9 --- /dev/null +++ b/src/utils/video/video_rop.c @@ -0,0 +1,786 @@ +#include +#include <86box/utils/video_stdlib.h> + +/* + Implements a standard GDI ternary rop for e.g. bitblit acceleration. + For further information on this function, refer to the documentation on Win32 GDI: + + https://learn.microsoft.com/en-us/windows/win32/gdi/binary-raster-operations + + This is currently used in the following graphics cards: Tseng Labs ET4000/32p, Cirrus Logic CL-GD54xx, 3dfx Voodoo Banshee/Voodoo 3, Trident TGUI9440, + S3 ViRGE, C&T 69000, ATI Mach64, and NVidia RIVA 128 +*/ +int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src, int32_t out) +{ + switch (rop) + { + case 0x00: + out = 0; + break; + case 0x01: + out = ~(dst | (pattern | src)); + break; + case 0x02: + out = dst & ~(pattern | src); + break; + case 0x03: + out = ~(pattern | src); + break; + case 0x04: + out = src & ~(dst | pattern); + break; + case 0x05: + out = ~(dst | pattern); + break; + case 0x06: + out = ~(pattern | ~(dst ^ src)); + break; + case 0x07: + out = ~(pattern | (dst & src)); + break; + case 0x08: + out = src & (dst & ~pattern); + break; + case 0x09: + out = ~(pattern | (dst ^ src)); + break; + case 0x0a: + out = dst & ~pattern; + break; + case 0x0b: + out = ~(pattern | (src & ~dst)); + break; + case 0x0c: + out = src & ~pattern; + break; + case 0x0d: + out = ~(pattern | (dst & ~src)); + break; + case 0x0e: + out = ~(pattern | ~(dst | src)); + break; + case 0x0f: + out = ~pattern; + break; + case 0x10: + out = pattern & ~(dst | src); + break; + case 0x11: + out = ~(dst | src); + break; + case 0x12: + out = ~(src | ~(dst ^ pattern)); + break; + case 0x13: + out = ~(src | (dst & pattern)); + break; + case 0x14: + out = ~(dst | ~(pattern ^ src)); + break; + case 0x15: + out = ~(dst | (pattern & src)); + break; + case 0x16: + out = pattern ^ (src ^ (dst & ~(pattern & src))); + break; + case 0x17: + out = ~(src ^ ((src ^ pattern) & (dst ^ src))); + break; + case 0x18: + out = (src ^ pattern) & (pattern ^ dst); + break; + case 0x19: + out = ~(src ^ (dst & ~(pattern & src))); + break; + case 0x1a: + out = pattern ^ (dst | (src & pattern)); + break; + case 0x1b: + out = ~(src ^ (dst & (pattern ^ src))); + break; + case 0x1c: + out = pattern ^ (src | (dst & pattern)); + break; + case 0x1d: + out = ~(dst ^ (src & (pattern ^ dst))); + break; + case 0x1e: + out = pattern ^ (dst | src); + break; + case 0x1f: + out = ~(pattern & (dst | src)); + break; + case 0x20: + out = dst & (pattern & ~src); + break; + case 0x21: + out = ~(src | (dst ^ pattern)); + break; + case 0x22: + out = dst & ~src; + break; + case 0x23: + out = ~(src | (pattern & ~dst)); + break; + case 0x24: + out = (src ^ pattern) & (dst ^ src); + break; + case 0x25: + out = ~(pattern ^ (dst & ~(src & pattern))); + break; + case 0x26: + out = src ^ (dst | (pattern & src)); + break; + case 0x27: + out = src ^ (dst | ~(pattern ^ src)); + break; + case 0x28: + out = dst & (pattern ^ src); + break; + case 0x29: + out = ~(pattern ^ (src ^ (dst | (pattern & src)))); + break; + case 0x2a: + out = dst & ~(pattern & src); + break; + case 0x2b: + out = ~(src ^ ((src ^ pattern) & (pattern ^ dst))); + break; + case 0x2c: + out = src ^ (pattern & (dst | src)); + break; + case 0x2d: + out = pattern ^ (src | ~dst); + break; + case 0x2e: + out = pattern ^ (src | (dst ^ pattern)); + break; + case 0x2f: + out = ~(pattern & (src | ~dst)); + break; + case 0x30: + out = pattern & ~src; + break; + case 0x31: + out = ~(src | (dst & ~pattern)); + break; + case 0x32: + out = src ^ (dst | (pattern | src)); + break; + case 0x33: + out = ~src; + break; + case 0x34: + out = src ^ (pattern | (dst & src)); + break; + case 0x35: + out = src ^ (pattern | ~(dst ^ src)); + break; + case 0x36: + out = src ^ (dst | pattern); + break; + case 0x37: + out = ~(src & (dst | pattern)); + break; + case 0x38: + out = pattern ^ (src & (dst | pattern)); + break; + case 0x39: + out = src ^ (pattern | ~dst); + break; + case 0x3a: + out = src ^ (pattern | (dst ^ src)); + break; + case 0x3b: + out = ~(src & (pattern | ~dst)); + break; + case 0x3c: + out = pattern ^ src; + break; + case 0x3d: + out = src ^ (pattern | ~(dst | src)); + break; + case 0x3e: + out = src ^ (pattern | (dst & ~src)); + break; + case 0x3f: + out = ~(pattern & src); + break; + case 0x40: + out = pattern & (src & ~dst); + break; + case 0x41: + out = ~(dst | (pattern ^ src)); + break; + case 0x42: + out = (src ^ dst) & (pattern ^ dst); + break; + case 0x43: + out = ~(src ^ (pattern & ~(dst & src))); + break; + case 0x44: + out = src & ~dst; + break; + case 0x45: + out = ~(dst | (pattern & ~src)); + break; + case 0x46: + out = dst ^ (src | (pattern & dst)); + break; + case 0x47: + out = ~(pattern ^ (src & (dst ^ pattern))); + break; + case 0x48: + out = src & (dst ^ pattern); + break; + case 0x49: + out = ~(pattern ^ (dst ^ (src | (pattern & dst)))); + break; + case 0x4a: + out = dst ^ (pattern & (src | dst)); + break; + case 0x4b: + out = pattern ^ (dst | ~src); + break; + case 0x4c: + out = src & ~(dst & pattern); + break; + case 0x4d: + out = ~(src ^ ((src ^ pattern) | (dst ^ src))); + break; + case 0x4e: + out = pattern ^ (dst | (src ^ pattern)); + break; + case 0x4f: + out = ~(pattern & (dst | ~src)); + break; + case 0x50: + out = pattern & ~dst; + break; + case 0x51: + out = ~(dst | (src & ~pattern)); + break; + case 0x52: + out = dst ^ (pattern | (src & dst)); + break; + case 0x53: + out = ~(src ^ (pattern & (dst ^ src))); + break; + case 0x54: + out = ~(dst | ~(pattern | src)); + break; + case 0x55: + out = ~dst; + break; + case 0x56: + out = dst ^ (pattern | src); + break; + case 0x57: + out = ~(dst & (pattern | src)); + break; + case 0x58: + out = pattern ^ (dst & (src | pattern)); + break; + case 0x59: + out = dst ^ (pattern | ~src); + break; + case 0x5a: + out = dst ^ pattern; + break; + case 0x5b: + out = dst ^ (pattern | ~(src | dst)); + break; + case 0x5c: + out = dst ^ (pattern | (src ^ dst)); + break; + case 0x5d: + out = ~(dst & (pattern | ~src)); + break; + case 0x5e: + out = dst ^ (pattern | (src & ~dst)); + break; + case 0x5f: + out = ~(dst & pattern); + break; + case 0x60: + out = pattern & (dst ^ src); + break; + case 0x61: + out = ~(dst ^ (src ^ (pattern | (dst & src)))); + break; + case 0x62: + out = dst ^ (src & (pattern | dst)); + break; + case 0x63: + out = src ^ (dst | ~pattern); + break; + case 0x64: + out = src ^ (dst & (pattern | src)); + break; + case 0x65: + out = dst ^ (src | ~pattern); + break; + case 0x66: + out = dst ^ src; + break; + case 0x67: + out = src ^ (dst | ~(pattern | src)); + break; + case 0x68: + out = ~(dst ^ (src ^ (pattern | ~(dst | src)))); + break; + case 0x69: + out = ~(pattern ^ (dst ^ src)); + break; + case 0x6a: + out = dst ^ (pattern & src); + break; + case 0x6b: + out = ~(pattern ^ (src ^ (dst & (pattern | src)))); + break; + case 0x6c: + out = src ^ (dst & pattern); + break; + case 0x6d: + out = ~(pattern ^ (dst ^ (src & (pattern | dst)))); + break; + case 0x6e: + out = src ^ (dst & (pattern | ~src)); + break; + case 0x6f: + out = ~(pattern & ~(dst ^ src)); + break; + case 0x70: + out = pattern & ~(dst & src); + break; + case 0x71: + out = ~(src ^ ((src ^ dst) & (pattern ^ dst))); + break; + case 0x72: + out = src ^ (dst | (pattern ^ src)); + break; + case 0x73: + out = ~(src & (dst | ~pattern)); + break; + case 0x74: + out = dst ^ (src | (pattern ^ dst)); + break; + case 0x75: + out = ~(dst & (src | ~pattern)); + break; + case 0x76: + out = src ^ (dst | (pattern & ~src)); + break; + case 0x77: + out = ~(dst & src); + break; + case 0x78: + out = pattern ^ (dst & src); + break; + case 0x79: + out = ~(dst ^ (src ^ (pattern & (dst | src)))); + break; + case 0x7a: + out = dst ^ (pattern & (src | ~dst)); + break; + case 0x7b: + out = ~(src & ~(dst ^ pattern)); + break; + case 0x7c: + out = src ^ (pattern & (dst | ~src)); + break; + case 0x7d: + out = ~(dst & ~(pattern ^ src)); + break; + case 0x7e: + out = (src ^ pattern) | (dst ^ src); + break; + case 0x7f: + out = ~(dst & (pattern & src)); + break; + case 0x80: + out = dst & (pattern & src); + break; + case 0x81: + out = ~((src ^ pattern) | (dst ^ src)); + break; + case 0x82: + out = dst & ~(pattern ^ src); + break; + case 0x83: + out = ~(src ^ (pattern & (dst | ~src))); + break; + case 0x84: + out = src & ~(dst ^ pattern); + break; + case 0x85: + out = ~(pattern ^ (dst & (src | ~pattern))); + break; + case 0x86: + out = dst ^ (src ^ (pattern & (dst | src))); + break; + case 0x87: + out = ~(pattern ^ (dst & src)); + break; + case 0x88: + out = dst & src; + break; + case 0x89: + out = ~(src ^ (dst | (pattern & ~src))); + break; + case 0x8a: + out = dst & (src | ~pattern); + break; + case 0x8b: + out = ~(dst ^ (src | (pattern ^ dst))); + break; + case 0x8c: + out = src & (dst | ~pattern); + break; + case 0x8d: + out = ~(src ^ (dst | (pattern ^ src))); + break; + case 0x8e: + out = src ^ ((src ^ dst) & (pattern ^ dst)); + break; + case 0x8f: + out = ~(pattern & ~(dst & src)); + break; + case 0x90: + out = pattern & ~(dst ^ src); + break; + case 0x91: + out = ~(src ^ (dst & (pattern | ~src))); + break; + case 0x92: + out = dst ^ (pattern ^ (src & (dst | pattern))); + break; + case 0x93: + out = ~(src ^ (pattern & dst)); + break; + case 0x94: + out = pattern ^ (src ^ (dst & (pattern | src))); + break; + case 0x95: + out = ~(dst ^ (pattern & src)); + break; + case 0x96: + out = dst ^ (pattern ^ src); + break; + case 0x97: + out = pattern ^ (src ^ (dst | ~(pattern | src))); + break; + case 0x98: + out = ~(src ^ (dst | ~(pattern | src))); + break; + case 0x99: + out = ~(dst ^ src); + break; + case 0x9a: + out = dst ^ (pattern & ~src); + break; + case 0x9b: + out = ~(src ^ (dst & (pattern | src))); + break; + case 0x9c: + out = src ^ (pattern & ~dst); + break; + case 0x9d: + out = ~(dst ^ (src & (pattern | dst))); + break; + case 0x9e: + out = dst ^ (src ^ (pattern | (dst & src))); + break; + case 0x9f: + out = ~(pattern & (dst ^ src)); + break; + case 0xa0: + out = dst & pattern; + break; + case 0xa1: + out = ~(pattern ^ (dst | (src & ~pattern))); + break; + case 0xa2: + out = dst & (pattern | ~src); + break; + case 0xa3: + out = ~(dst ^ (pattern | (src ^ dst))); + break; + case 0xa4: + out = ~(pattern ^ (dst | ~(src | pattern))); + break; + case 0xa5: + out = ~(pattern ^ dst); + break; + case 0xa6: + out = dst ^ (src & ~pattern); + break; + case 0xa7: + out = ~(pattern ^ (dst & (src | pattern))); + break; + case 0xa8: + out = dst & (pattern | src); + break; + case 0xa9: + out = ~(dst ^ (pattern | src)); + break; + case 0xaa: + out = dst; + break; + case 0xab: + out = dst | ~(pattern | src); + break; + case 0xac: + out = src ^ (pattern & (dst ^ src)); + break; + case 0xad: + out = ~(dst ^ (pattern | (src & dst))); + break; + case 0xae: + out = dst | (src & ~pattern); + break; + case 0xaf: + out = dst | ~pattern; + break; + case 0xb0: + out = pattern & (dst | ~src); + break; + case 0xb1: + out = ~(pattern ^ (dst | (src ^ pattern))); + break; + case 0xb2: + out = src ^ ((src ^ pattern) | (dst ^ src)); + break; + case 0xb3: + out = ~(src & ~(dst & pattern)); + break; + case 0xb4: + out = pattern ^ (src & ~dst); + break; + case 0xb5: + out = ~(dst ^ (pattern & (src | dst))); + break; + case 0xb6: + out = dst ^ (pattern ^ (src | (dst & pattern))); + break; + case 0xb7: + out = ~(src & (dst ^ pattern)); + break; + case 0xb8: + out = pattern ^ (src & (dst ^ pattern)); + break; + case 0xb9: + out = ~(dst ^ (src | (pattern & dst))); + break; + case 0xba: + out = dst | (pattern & ~src); + break; + case 0xbb: + out = dst | ~src; + break; + case 0xbc: + out = src ^ (pattern & ~(dst & src)); + break; + case 0xbd: + out = ~((src ^ dst) & (pattern ^ dst)); + break; + case 0xbe: + out = dst | (pattern ^ src); + break; + case 0xbf: + out = dst | ~(pattern & src); + break; + case 0xc0: + out = pattern & src; + break; + case 0xc1: + out = ~(src ^ (pattern | (dst & ~src))); + break; + case 0xc2: + out = ~(src ^ (pattern | ~(dst | src))); + break; + case 0xc3: + out = ~(pattern ^ src); + break; + case 0xc4: + out = src & (pattern | ~dst); + break; + case 0xc5: + out = ~(src ^ (pattern | (dst ^ src))); + break; + case 0xc6: + out = src ^ (dst & ~pattern); + break; + case 0xc7: + out = ~(pattern ^ (src & (dst | pattern))); + break; + case 0xc8: + out = src & (dst | pattern); + break; + case 0xc9: + out = ~(src ^ (pattern | dst)); + break; + case 0xca: + out = dst ^ (pattern & (src ^ dst)); + break; + case 0xcb: + out = ~(src ^ (pattern | (dst & src))); + break; + case 0xcc: + out = src; + break; + case 0xcd: + out = src | ~(dst | pattern); + break; + case 0xce: + out = src | (dst & ~pattern); + break; + case 0xcf: + out = src | ~pattern; + break; + case 0xd0: + out = pattern & (src | ~dst); + break; + case 0xd1: + out = ~(pattern ^ (src | (dst ^ pattern))); + break; + case 0xd2: + out = pattern ^ (dst & ~src); + break; + case 0xd3: + out = ~(src ^ (pattern & (dst | src))); + break; + case 0xd4: + out = src ^ ((src ^ pattern) & (pattern ^ dst)); + break; + case 0xd5: + out = ~(dst & ~(pattern & src)); + break; + case 0xd6: + out = pattern ^ (src ^ (dst | (pattern & src))); + break; + case 0xd7: + out = ~(dst & (pattern ^ src)); + break; + case 0xd8: + out = pattern ^ (dst & (src ^ pattern)); + break; + case 0xd9: + out = ~(src ^ (dst | (pattern & src))); + break; + case 0xda: + out = dst ^ (pattern & ~(src & dst)); + break; + case 0xdb: + out = ~((src ^ pattern) & (dst ^ src)); + break; + case 0xdc: + out = src | (pattern & ~dst); + break; + case 0xdd: + out = src | ~dst; + break; + case 0xde: + out = src | (dst ^ pattern); + break; + case 0xdf: + out = src | ~(dst & pattern); + break; + case 0xe0: + out = pattern & (dst | src); + break; + case 0xe1: + out = ~(pattern ^ (dst | src)); + break; + case 0xe2: + out = dst ^ (src & (pattern ^ dst)); + break; + case 0xe3: + out = ~(pattern ^ (src | (dst & pattern))); + break; + case 0xe4: + out = src ^ (dst & (pattern ^ src)); + break; + case 0xe5: + out = ~(pattern ^ (dst | (src & pattern))); + break; + case 0xe6: + out = src ^ (dst & ~(pattern & src)); + break; + case 0xe7: + out = ~((src ^ pattern) & (pattern ^ dst)); + break; + case 0xe8: + out = src ^ ((src ^ pattern) & (dst ^ src)); + break; + case 0xe9: + out = ~(dst ^ (src ^ (pattern & ~(dst & src)))); + break; + case 0xea: + out = dst | (pattern & src); + break; + case 0xeb: + out = dst | ~(pattern ^ src); + break; + case 0xec: + out = src | (dst & pattern); + break; + case 0xed: + out = src | ~(dst ^ pattern); + break; + case 0xee: + out = dst | src; + break; + case 0xef: + out = src | (dst | ~pattern); + break; + case 0xf0: + out = pattern; + break; + case 0xf1: + out = pattern | ~(dst | src); + break; + case 0xf2: + out = pattern | (dst & ~src); + break; + case 0xf3: + out = pattern | ~src; + break; + case 0xf4: + out = pattern | (src & ~dst); + break; + case 0xf5: + out = pattern | ~dst; + break; + case 0xf6: + out = pattern | (dst ^ src); + break; + case 0xf7: + out = pattern | ~(dst & src); + break; + case 0xf8: + out = pattern | (dst & src); + break; + case 0xf9: + out = pattern | ~(dst ^ src); + break; + case 0xfa: + out = dst | pattern; + break; + case 0xfb: + out = dst | (pattern | ~src); + break; + case 0xfc: + out = pattern | src; + break; + case 0xfd: + out = pattern | (src | ~dst); + break; + case 0xfe: + out = dst | (pattern | src); + break; + case 0xff: + out = ~0; + break; + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 5fd450260..d0d30c66d 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -1,33 +1,54 @@ /* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 Core rendering code (Software version) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ +* 86Box A hypervisor and IBM PC system emulator that specializes in +* running old operating systems and software designed for IBM +* PC systems and compatibles from 1981 through fairly recent +* system designs based on the PCI bus. +* +* This file is part of the 86Box distribution. +* +* NV3 Core rendering code (Software version) +* +* +* +* Authors: Connor Hyde, I need a better email address ;^) +* +* Copyright 2024-2025 Connor Hyde +*/ - #include - #include - #include - #include - #include <86box/86box.h> - #include <86box/device.h> - #include <86box/mem.h> - #include <86box/pci.h> - #include <86box/rom.h> - #include <86box/video.h> - #include <86box/nv/vid_nv.h> - #include <86box/nv/vid_nv3.h> - #include <86box/nv/classes/vid_nv3_classes.h> +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> +#include <86box/nv/classes/vid_nv3_classes.h> - - \ No newline at end of file + +/* Render Core: Performs a ROP */ +void nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, uint32_t pen, nv3_render_operation_type rop) +{ + switch (rop) + { + case nv3_rop_blackness: + return 0; + case nv3_rop_srcand: + + case nv3_rop_srccopy: + return src; + case nv3_rop_dstcopy: + return dst; // do nothing + case nv3_rop_dstinvert: + return !dst; + case nv3_rop_xor: + return src ^ dst; + case nv3_rop_whiteness: + return 1; + + } +} \ No newline at end of file From 9a863caa23794b081f4e6831ab9f4fbafd366a13 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 17 Mar 2025 00:37:45 +0000 Subject: [PATCH 118/274] Fix rop core. Implement some basic image in memory methods. --- .../86box/nv/classes/vid_nv3_classes.h | 5 +++-- src/include/86box/nv/vid_nv3.h | 7 +++--- src/utils/video/video_rop.c | 10 ++++++--- .../classes/nv3_class_01c_image_in_memory.c | 14 +++++++++++- src/video/nv/nv3/render/nv3_render_core.c | 21 ++---------------- src/video/nv/nv3/subsystems/nv3_pgraph.c | 22 ++++++++++++++++++- 6 files changed, 50 insertions(+), 29 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index c015d0659..39c03b295 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -81,6 +81,7 @@ typedef enum nv3_pgraph_class_e #define NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE 0x0304 #define NV3_IMAGE_IN_MEMORY_PITCH 0x0308 #define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET 0x030C +#define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END 22 #define NV3_W95TXT_COLORA 0x03FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. @@ -118,14 +119,14 @@ typedef struct nv3_color_argb_32_s } nv3_color_argb_32_t; /* 30-bit colour format for internal PGRAPH use */ -typedef struct nv3_color_x3a10g10b10_s +typedef struct nv3_color_x2a10g10b10_s { uint8_t reserved : 1; bool alpha_if_chroma_key_otherwise_reserved2 : 1; // 1-bit ALPHA if chroma key, OTHERWISE USELESS and IGNORE uint16_t r : 10; uint16_t g : 10; uint16_t b : 10; -} nv3_color_x3a10g10b10_t; +} nv3_color_x2a10g10b10_t; /* 16-bit A4R4G4B4 colour format */ typedef struct nv3_color_16_a4r4g4b4_s diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 3c99782e6..fb080f1cd 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1114,17 +1114,18 @@ typedef struct nv3_pgraph_s nv3_position_16_bigy_t dst_canvas_min; nv3_position_16_bigy_t dst_canvas_max; // Pattern stuff - nv3_color_x3a10g10b10_t pattern_color_0_0; + nv3_color_x2a10g10b10_t pattern_color_0_0; uint32_t pattern_color_0_1; // only 7:0 relevant - nv3_color_x3a10g10b10_t pattern_color_1_0; + nv3_color_x2a10g10b10_t pattern_color_1_0; uint32_t pattern_color_1_1; // only 7:0 relevant uint32_t pattern_bitmap_high; // high part of pattern bitmap for blit uint32_t pattern_bitmap_low; uint32_t pattern_shape; // may need to be an enum - 0=8x8, 1=64x1, 2=1x64 uint32_t plane_mask; // only 7:0 relevant - nv3_color_x3a10g10b10_t chroma_key; // color key + nv3_color_x2a10g10b10_t chroma_key; // color key uint32_t beta_factor; nv3_pgraph_dma_settings_t dma_settings; + uint8_t rop; // Current GDI Ternary Render Operation nv3_pgraph_clip_misc_settings_t clip_misc_settings; nv3_notifier_t notifier; nv3_position_16_bigy_t clip0_min; diff --git a/src/utils/video/video_rop.c b/src/utils/video/video_rop.c index b6350b2e9..8bfdc9627 100644 --- a/src/utils/video/video_rop.c +++ b/src/utils/video/video_rop.c @@ -10,8 +10,10 @@ This is currently used in the following graphics cards: Tseng Labs ET4000/32p, Cirrus Logic CL-GD54xx, 3dfx Voodoo Banshee/Voodoo 3, Trident TGUI9440, S3 ViRGE, C&T 69000, ATI Mach64, and NVidia RIVA 128 */ -int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src, int32_t out) -{ +int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src) +{ + uint32_t out = 0x00; + switch (rop) { case 0x00: @@ -782,5 +784,7 @@ int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t case 0xff: out = ~0; break; - } + } + + return out; } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index a74313276..b42583f7a 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -28,10 +28,22 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { + case NV3_IMAGE_IN_MEMORY_COLOR_FORMAT: + break; + /* Pitch - length between scanlines */ + case NV3_IMAGE_IN_MEMORY_PITCH: + nv3->pgraph.image_in_memory.pitch = param & 0x1FF0; + nv_log("Image in Memory PITCH=0x%04x", nv3->pgraph.image_in_memory.pitch); + break; + /* Byte offset in GPU VRAM of top left pixel (22:0) */ + case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: + nv3->pgraph.image_in_memory.linear_address = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); + nv_log("Image in Memory TOP_LEFT_OFFSET=0x%08x", nv3->pgraph.image_in_memory.linear_address); + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index d0d30c66d..426cf2c9d 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -28,27 +28,10 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> #include <86box/nv/classes/vid_nv3_classes.h> - +#include <86box/utils/video_stdlib.h> /* Render Core: Performs a ROP */ void nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, uint32_t pen, nv3_render_operation_type rop) { - switch (rop) - { - case nv3_rop_blackness: - return 0; - case nv3_rop_srcand: - - case nv3_rop_srccopy: - return src; - case nv3_rop_dstcopy: - return dst; // do nothing - case nv3_rop_dstinvert: - return !dst; - case nv3_rop_xor: - return src ^ dst; - case nv3_rop_whiteness: - return 1; - - } + return video_rop_gdi_ternary(rop, dst, pattern, src); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 802d98d10..510d8c1d3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -70,7 +70,7 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_PATTERN_BITMAP_HIGH, "PGRAPH Pattern Bitmap (High 32bits)", NULL, NULL}, { NV3_PGRAPH_PATTERN_BITMAP_LOW, "PGRAPH Pattern Bitmap (Low 32bits)", NULL, NULL}, { NV3_PGRAPH_PATTERN_SHAPE, "PGRAPH Pattern Shape (1:0 - 0=8x8, 1=64x1, 2=1x64)", NULL, NULL}, - { NV3_PGRAPH_ROP3, "PGRAPH Render Operation ROP3 (2^3 bits = 256 possible operations)", NULL, NULL}, + { NV3_PGRAPH_ROP3, "PGRAPH GDI Ternary Render Operation ROP3 (2^3 bits = 256 possible operations)", NULL, NULL}, { NV3_PGRAPH_PLANE_MASK, "PGRAPH Current Plane Mask (7:0)", NULL, NULL}, { NV3_PGRAPH_CHROMA_KEY, "PGRAPH Chroma Key (17:0) (Bit 30 = Alpha, 29:20 = Red, 19:10 = Green, 9:0 = Blue)", NULL, NULL}, { NV3_PGRAPH_BETA, "PGRAPH Beta factor", NULL, NULL }, @@ -207,6 +207,16 @@ uint32_t nv3_pgraph_read(uint32_t address) case NV3_PGRAPH_BETA: ret = nv3->pgraph.beta_factor; break; + // Todo: Massive table of ROP IDs or at least known ones? + case NV3_PGRAPH_ROP3: + ret = nv3->pgraph.rop; + break; + case NV3_PGRAPH_CHROMA_KEY: + ret = *(uint32_t*)&nv3->pgraph.chroma_key; + break; + case NV3_PGRAPH_PLANE_MASK: + ret = nv3->pgraph.plane_mask; + break; // DMA case NV3_PGRAPH_DMA: ret = *(uint32_t*)&nv3->pgraph.dma_settings; @@ -400,6 +410,16 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) case NV3_PGRAPH_BETA: nv3->pgraph.beta_factor = value; break; + // Todo: Massive table of ROP IDs or at least known ones? + case NV3_PGRAPH_ROP3: + nv3->pgraph.rop = value & 0xFF; + break; + case NV3_PGRAPH_CHROMA_KEY: + nv3->pgraph.chroma_key = *(nv3_color_x2a10g10b10_t*)value; + break; + case NV3_PGRAPH_PLANE_MASK: + nv3->pgraph.plane_mask = value; + break; // DMA case NV3_PGRAPH_DMA: *(uint32_t*)&nv3->pgraph.dma_settings = value; From 84f82351618f22bf06b89ddc41e28f7c7e4ab1ef Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 17 Mar 2025 01:15:02 +0000 Subject: [PATCH 119/274] Implement bpixel, bformat, bpitch. Actually apply these to class 0x1C mthd 0300,0308,030c. Temporary ROP code too. --- .../B = BUFFER. REMEMBER THESE!!!.txt | 1 + doc/nvidia_notes/NV128.xlsx | Bin 9325 -> 9550 bytes doc/nvidia_notes/NV3 DMA Engine.txt | 3 ++ .../86box/nv/classes/vid_nv3_classes.h | 8 +-- src/include/86box/nv/vid_nv3.h | 50 ++++++++++++++++-- src/include/86box/utils/video_stdlib.h | 2 +- .../classes/nv3_class_01c_image_in_memory.c | 39 ++++++++++++-- src/video/nv/nv3/render/nv3_render_core.c | 3 +- 8 files changed, 92 insertions(+), 14 deletions(-) create mode 100644 doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt diff --git a/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt b/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt new file mode 100644 index 000000000..e8f183240 --- /dev/null +++ b/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt @@ -0,0 +1 @@ +B = BUFFER. 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z(zc$15`wL4-Qiw@Beb;rklT)&l{eYM;Y6W2g^ zhRg1LWkTF=Qe12%`C81mI#b0@KtsXYJsqm@EKPC;Iuc%)YG&Zi_G?^Q`zFHeoN3s~ zV-Py_RV;nXRV5~&O{17C;L)XQ0TIU-Y4)a^UdQpdSH{XKn8%Pwf%# diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt index fe2d61508..380e0281e 100644 --- a/doc/nvidia_notes/NV3 DMA Engine.txt +++ b/doc/nvidia_notes/NV3 DMA Engine.txt @@ -49,3 +49,6 @@ call of mthdCreate for ***DRIVER*** CLASS ID: a7b44, check ptr + + + diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 39c03b295..e1458671e 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1145,17 +1145,17 @@ typedef enum nv3_object_class_01C_pixel_format_e { // Y8P4 // 12-bits (Y8 - Planar YUV 8 bits (Y value only), 4 bits of indexed colour too? - nv3_m2mt_pixel_format_le_y8_p4 = 0x1010000, + nv3_image_in_memory_pixel_format_le_y8_p4 = 0x1010000, // Y16P2 // 16-bits (Y16) - Planar YUV 16 bits (Y value only), 2 bits of indexed colour too? - nv3_m2mt_pixel_format_le_y16_p2 = 0x1010101, + nv3_image_in_memory_pixel_format_le_y16_p2 = 0x1010101, /* 1 unused bit, 555 15-bit format, p2(?) */ - nv3_m2mt_pixel_format_x1r5g5b5_p2 = 0x1000000, + nv3_image_in_memory_pixel_format_x1r5g5b5_p2 = 0x1000000, // X8G8B8R8, 24-bit colour (or 24-bit colour with alpha) - nv3_m2mt_pixel_format_x8g8b8r8 = 0x1, + nv3_image_in_memory_pixel_format_x8g8b8r8 = 0x1, } nv3_object_class_01C_pixel_format; typedef struct nv3_object_class_01C diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index fb080f1cd..49bc8c64e 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 13 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 17 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -454,6 +454,8 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part // PGRAPH Core +#define NV3_PGRAPH_MAX_BUFFERS 4 + // For these debug registers, 0=Disabled, 1=Enabled // Debug 0: General @@ -532,7 +534,25 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 //todo: add what this does #define NV3_PGRAPH_INTR_EN_1 0x400144 // Interrupt Control for PGRAPH #2 (it can receive two at onc) -#define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // DMA context switcher +#define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // Holds the current PGRAPH context, switched by context switching + +/* Contextual information for pgraph */ +#define NV3_PGRAPH_CONTEXT_SWITCH_COLOR_FORMAT 2 // Holds the current color format used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_ALPHA 3 // Holds a boolean if alpha transparency is currently enabled in drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_MONO_FORMAT 8 // Holds the current color format used for monochome drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_DAC_BYPASS 9 // Holds if PRAMDAC should be bypassed, and an external DAC drawn. +#define NV3_PGRAPH_CONTEXT_SWITCH_Z_WRITE 12 // Holds if we should write back to the zbuffer. +#define NV3_PGRAPH_CONTEXT_SWITCH_CHROMA_KEY 13 // Holds the current chroma mask used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_PLANE_MASK 14 // Holds the current plane mask used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_USER_CLIP 15 // Holds the user-specified clipping information used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER 16 // Holds the buffer ID used for drawing operation (i.e. which bpixel/bpitch/boffset index to use) +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED 20 // Holds a boolean indicating if buffer 0 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED 21 // Holds a boolean indicating if buffer 1 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED 22 // Holds a boolean indicating if buffer 2 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED 23 // Holds a boolean indicating if buffer 3 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_PATCH_CONFIG 24 // Something to do with an operation to do during a patchcord? +#define NV3_PGRAPH_CONTEXT_SWITCH_VOLATILE 31 // HUH + #define NV3_PGRAPH_CONTEXT_CONTROL 0x400190 // DMA context control #define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename #define NV3_PGRAPH_CONTEXT_CACHE(i) 0x4001A0+(i*4) // Context Cache @@ -1082,6 +1102,23 @@ typedef struct nv3_pgraph_status_s } nv3_pgraph_status_t; +/* All of this B* stuff is registers at 400630..40065c and 4006a8 in reality, easier to implement it like this + BPixel = Internal Binary Representation of the pixel within the architecture +*/ +#define NV3_BPIXEL_FORMAT 0 +#define NV3_BPIXEL_FORMAT_IS_VALID 2 + +typedef enum nv3_pgraph_bpixel_format_e +{ + // Y16 + bpixel_fmt_y16 = 0, + // 8-bit colour + bpixel_fmt_8bit = 1, + // 16-bit colour + bpixel_fmt_16bit = 2, + // 32-bit colour (BGRA/ARGB) + bpixel_fmt_32bit = 3, +} nv3_pgraph_bpixel_format; // Graphics Subsystem typedef struct nv3_pgraph_s @@ -1126,14 +1163,19 @@ typedef struct nv3_pgraph_s uint32_t beta_factor; nv3_pgraph_dma_settings_t dma_settings; uint8_t rop; // Current GDI Ternary Render Operation + // SURFACE STUFF - PGRAPH CAN OPERATE ON 4 SURFACES/BUFFERS AT A TIME + uint32_t boffset[NV3_PGRAPH_MAX_BUFFERS]; // 22-bit linear VRAM offset for the start of a surface. + uint16_t bpitch[NV3_PGRAPH_MAX_BUFFERS]; // 12-bit linear VRAM offset for the pitch of a surfac.e + uint32_t bpixel[NV3_PGRAPH_MAX_BUFFERS]; // Pixel format for each possible surfaces. + // CLIP nv3_pgraph_clip_misc_settings_t clip_misc_settings; nv3_notifier_t notifier; nv3_position_16_bigy_t clip0_min; nv3_position_16_bigy_t clip0_max; nv3_position_16_bigy_t clip1_min; nv3_position_16_bigy_t clip1_max; - uint32_t fifo_access; - nv3_pgraph_status_t status; + uint32_t fifo_access; // Determines if PGRAPH can access PFIFO. + nv3_pgraph_status_t status; // Current status of the 3D engine. uint32_t trapped_address; uint32_t trapped_data; uint32_t trapped_instance; diff --git a/src/include/86box/utils/video_stdlib.h b/src/include/86box/utils/video_stdlib.h index f8e2ed5af..3605631f1 100644 --- a/src/include/86box/utils/video_stdlib.h +++ b/src/include/86box/utils/video_stdlib.h @@ -17,4 +17,4 @@ /* ROP */ -int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src, int32_t out); \ No newline at end of file +int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index b42583f7a..547ffc441 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -30,19 +30,52 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { + /* We need this for a lot of methods, so may as well store it here. */ + uint32_t src_buffer_id = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + switch (method_id) { + /* Color format of the image */ case NV3_IMAGE_IN_MEMORY_COLOR_FORMAT: + // convert to how the bpixel registers represent surface + uint32_t real_format = 1; + + /* TODO: THIS CODE MIGHT BE NONSENSE + Convert between different internal representations of the pixel format, because Nvidia says: I WANT TO MAKE YOUR LIFE PAIN. + */ + switch (param) + { + case nv3_image_in_memory_pixel_format_x8g8b8r8: + real_format = 3; //32bit + // no change + break; + case nv3_image_in_memory_pixel_format_x1r5g5b5_p2: + real_format = 2; + break; + case nv3_image_in_memory_pixel_format_le_y16_p2: + real_format = 0; + break; + } + + /* Set the format */ + + nv3->pgraph.bpixel[src_buffer_id] = ((real_format & 0x03) | NV3_BPIXEL_FORMAT_IS_VALID); + nv_log("Image in Memory BUF%d COLOR_FORMAT=0x%04x", src_buffer_id, param); + break; /* Pitch - length between scanlines */ case NV3_IMAGE_IN_MEMORY_PITCH: + nv3->pgraph.image_in_memory.pitch = param & 0x1FF0; - nv_log("Image in Memory PITCH=0x%04x", nv3->pgraph.image_in_memory.pitch); + nv3->pgraph.bpitch[src_buffer_id] = param & 0x1FF0; // 12:0 + + nv_log("Image in Memory BUFL%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); break; /* Byte offset in GPU VRAM of top left pixel (22:0) */ case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: - nv3->pgraph.image_in_memory.linear_address = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); - nv_log("Image in Memory TOP_LEFT_OFFSET=0x%08x", nv3->pgraph.image_in_memory.linear_address); + nv3->pgraph.boffset[src_buffer_id] = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); + + nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.image_in_memory.linear_address); break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 426cf2c9d..8b5771f36 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -27,11 +27,10 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> #include <86box/utils/video_stdlib.h> /* Render Core: Performs a ROP */ -void nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, uint32_t pen, nv3_render_operation_type rop) +uint32_t nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, nv3_render_operation_type rop) { return video_rop_gdi_ternary(rop, dst, pattern, src); } \ No newline at end of file From 08983a9da3722689224a948d9d771e193853a5d9 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 17 Mar 2025 01:18:15 +0000 Subject: [PATCH 120/274] start actual notification code --- src/include/86box/nv/vid_nv3.h | 3 +++ src/video/nv/nv3/classes/nv3_class_shared_methods.c | 2 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 ++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 49bc8c64e..957714799 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1549,6 +1549,9 @@ void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_co void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); void nv3_class_01c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); +// Notification Engine +void nv3_notify_if_needed(nv3_grobj_t grobj); + // NV3 PFIFO void nv3_pfifo_init(); uint32_t nv3_pfifo_read(uint32_t address); diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 555a180e6..663214cec 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -39,7 +39,7 @@ void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t c } } -void nv3_notify() +void nv3_notify_if_needed(nv3_grobj_t grobj) { } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 510d8c1d3..117a88733 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -588,6 +588,8 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe fatal("NV3 (nv3_pgraph_arbitrate_method): Attempted to execute method on invalid, or unimplemented, class ID %s", nv3_class_names[class_id]); return; } + + nv3_notify_if_needed(grobj); } /* Arbitrates graphics object submission to the right object types */ From a5b864c59c9fb2083c60c8757d67d0d47679ef12 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 20 Mar 2025 00:01:59 +0000 Subject: [PATCH 121/274] pull out the notifier object. --- doc/nvidia_notes/NV128.xlsx | Bin 9550 -> 9615 bytes src/include/86box/nv/vid_nv3.h | 23 +++++- .../nv3_class_017_d3d5_tri_zeta_buffer.c | 30 +++---- src/video/nv/nv3/classes/nv3_class_names.c | 2 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 76 +++++++++++++++++- src/video/nv/nv3/nv3_core_arbiter.c | 3 +- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 7 +- src/video/nv/nv3/subsystems/nv3_pfb.c | 5 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 +- 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z_YWEJbVQh+@Fgl&#%nXYr#}d~rlV0AL#f4!L$o55kKFLik-5$Iqp)7oRy^4&n|oM! zRk*~9B>mm}C@p<9Q1GewRQsT-1_9>8{tNb~7LR$?F1H_K)q3yT1^2GKPu3x(0l5=* zM$${jX+z_++odpkwIuWUGOH6xa_*^qOX=j7hNh)tJP7uDT<$#gy5-!56K6M>pbfMT~-7FSkit8)?5dFVrm zIgaduX1izOWR);DI7ZkAuznF!qga#EpF^vbj@lc5H$;fPbYItSjAM+-Uk}L54X4+c zi3RTTYragc(X*$M+>s^sk0(%9$Soez#~Pr;b?^11wV+A1!vmu<}*VD6K z4-cG~T}$~8-P0?5!SQjw_jj7T{55*oU}LtK#}{HgSnUKCX&&jv%ihzUSRoWH!rqe$ zR9sy4z9Sa%(24u~6p-Pcm;rnyWZ$273gQczSAyjH`PiAh(874(|K@AUrOkJqRZN79 z04m06#)Z&IPHj1MJB=m&xaaWLTwdDrA(x#o`1u!^9BXP07&R*`G~&>b`i^M$^#bRl zQ`|etZH)|ymUs2QdVG(UDjhvlZQ?ildviaD)n)o}ieDylIx3*~c&KKiu;qNSoUr$<54ub^udW#n=SL?+SjvT!G?iT^S#w1qo&L|2>r%(vBb| z6ab*WIfW_zkw%FAdsG1cp}$A$Uy I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ +* 86Box A hypervisor and IBM PC system emulator that specializes in +* running old operating systems and software designed for IBM +* PC systems and compatibles from 1981 through fairly recent +* system designs based on the PCI bus. +* +* This file is part of the 86Box distribution. +* +* NV3: Methods for class 0x17 (Direct3D 5.0 accelerated triangle with zeta buffer) +* +* +* +* Authors: Connor Hyde, I need a better email address ;^) +* +* Copyright 2024-2025 Connor Hyde +*/ #include #include diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c index ded63ece2..64e35d9b3 100644 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ b/src/video/nv/nv3/classes/nv3_class_names.c @@ -64,4 +64,4 @@ const char* nv3_class_names[] = "NV3 INVALID class 0x1D", "NV3 INVALID class 0x1E", "NV3 INVALID class 0x1F", -}; +}; \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 663214cec..abeb0571b 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -21,6 +21,7 @@ #include #include <86box/86box.h> #include <86box/device.h> +#include <86box/dma.h> #include <86box/mem.h> #include <86box/pci.h> #include <86box/rom.h> @@ -39,7 +40,78 @@ void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t c } } -void nv3_notify_if_needed(nv3_grobj_t grobj) + +/* Sees if any notification is required after an object method is executed. If so, executes it... */ +void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { + if (nv3->pgraph.notify_pending) + { + nv_log("Called nv3_notify_if_needed with nv3->pgraph.notify_pending already set. name=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); + nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); + nv3_debug_ramin_print_context_info(name, context); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + + // disable + nv3->pgraph.notify_pending = false; + return; + } + + // set up the NvNotification structure + nv3_notification_t notify = {0}; + notify.nanoseconds = nv3->ptimer.time; + notify.status = NV3_NOTIFICATION_STATUS_DONE_OK; // it should be fine to just signal that it's ok -} \ No newline at end of file + // this is completely speculative and i have no idea + notify.info32 = grobj.grobj_0; + + // notify object base=grobj_1 >> 12 + uint32_t notify_obj_base = grobj.grobj_1 >> 12; + + uint32_t notify_obj_info = nv3_ramin_read32(notify_obj_base, nv3); + uint32_t notify_obj_limit = nv3_ramin_read32(notify_obj_base + 0x04, nv3); + uint32_t notify_obj_page = nv3_ramin_read32(notify_obj_base + 0x08, nv3); + + /* extract some important information*/ + uint32_t info_adjust = notify_obj_info & 0xFFF; + bool info_pt_present = (notify_obj_info >> NV3_NOTIFICATION_PT_PRESENT) & 0x01; + uint8_t info_notification_target = (notify_obj_info >> NV3_NOTIFICATION_TARGET) & 0x03; + + /* paging information */ + bool page_is_present = notify_obj_page & 0x01; + bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); + uint32_t frame_value = (notify_obj_page >> NV3_NOTIFICATION_PAGE_FRAME_ADDRESS) & 0xFFFFF; + + // This code is temporary and will probably be moved somewhere else + // Print torns of debug info + #ifdef DEBUG + nv_log("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); + + nv_log("Notification Information:\n"); + nv_log("Adjust Value: 0x%08x\n", info_adjust); + (info_pt_present) ? nv_log("Pagetable Present: True\n") : nv_log("Pagetable Present: False\n"); + + switch (info_notification_target) + { + case NV3_NOTIFICATION_TARGET_NVM: + nv_log("Notification Target: VRAM\n"); + break; + case NV3_NOTIFICATION_TARGET_CART: + nv_log("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); + break; + case NV3_NOTIFICATION_TARGET_PCI: + (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log("Notification Target: PCI Bus\n") : nv_log("Notification Target: PCI Bus (On AGP card???)\n"); + break; + case NV3_NOTIFICATION_TARGET_AGP: + (nv3->nvbase.bus_generation == nv_bus_agp_1x + || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log("Notification Target: AGP Bus\n") : nv_log("Notification Target: AGP Bus (On PCI card???)\n"); + break; + } + + nv_log("Limit: 0x%08x", notify_obj_limit); + (page_is_present) ? nv_log("Page is present\n") : nv_log("Page is not present\n"); + (page_is_readwrite) ? nv_log("Page is read-write\n") : nv_log("Page is read-only\n"); + nv_log("Pageframe Address: 0x%08x", frame_value); + #endif + + // set up the dma transfer. we need to translate to a physical address. +} diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 17cca15df..e5e7ced6b 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -194,5 +194,4 @@ uint32_t nv3_prmcio_read(uint32_t address) { return 0; }; void nv3_prmcio_write(uint32_t address, uint32_t value) {}; uint32_t nv3_vram_read(uint32_t address) { return 0; }; -void nv3_vram_write(uint32_t address, uint32_t value) {}; - +void nv3_vram_write(uint32_t address, uint32_t value) {}; \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index d5d17fe2d..4ce686335 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -28,4 +28,9 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -/* Nvidia DMA Engine */ \ No newline at end of file +/* Nvidia DMA Engine */ + +void nv3_dma_translate_address() +{ + +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 435225bc2..92a643502 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -168,13 +168,12 @@ void nv3_pfb_config0_write(uint32_t val) uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; // i don't think 16:9 is supported - uint32_t new_pfb_vtotal = new_pfb_htotal * (4.0/3.0); - + uint32_t new_pfb_vtotal = new_pfb_htotal * (4.0/3.0); uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; + nv_log("Framebuffer Config Change\n"); nv_log("Horizontal Size=%d pixels\n", new_pfb_htotal); nv_log("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); - if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) nv_log("Bit Depth=8bpp\n"); diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 117a88733..5851d9301 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -589,7 +589,7 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe return; } - nv3_notify_if_needed(grobj); + nv3_notify_if_needed(param, method, context, grobj); } /* Arbitrates graphics object submission to the right object types */ diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 226f4d8ee..f85ae3f8e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -498,10 +498,11 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u } -#ifndef RELEASE_BUILD + // Prints out some informaiton about the object void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context) { + #ifndef RELEASE_BUILD nv_log("Found object:\n"); nv_log("Name: 0x%04x\n", name); @@ -511,6 +512,5 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); nv_log("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); + #endif } - -#endif \ No newline at end of file From ac63ad436fdc3646a7c1328575383fb25fdf5bae Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 20 Mar 2025 00:40:29 +0000 Subject: [PATCH 122/274] Implement generic method execution. Implement unknown register write code --- src/include/86box/nv/vid_nv3.h | 20 ++- src/sound/snd_emu8k.c | 2 +- src/sound/snd_sb.c | 4 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 55 ++++-- src/video/nv/nv3/subsystems/nv3_pbus.c | 4 + src/video/nv/nv3/subsystems/nv3_pextdev.c | 4 + src/video/nv/nv3/subsystems/nv3_pfb.c | 4 + src/video/nv/nv3/subsystems/nv3_pfifo.c | 6 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 159 ++++++++++-------- src/video/nv/nv3/subsystems/nv3_pmc.c | 4 + src/video/nv/nv3/subsystems/nv3_pme.c | 5 + src/video/nv/nv3/subsystems/nv3_pramdac.c | 5 + src/video/nv/nv3/subsystems/nv3_ptimer.c | 4 + src/video/nv/nv3/subsystems/nv3_pvideo.c | 5 +- src/video/vid_voodoo.c | 2 +- 15 files changed, 181 insertions(+), 102 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 9c1a5628e..3756a47ed 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 17 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 20 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -521,9 +521,11 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_DEBUG_3_FORMAT_CHECK 22 #define NV3_PGRAPH_DEBUG_3_ALPHA_CHECK 24 +// Interrupt stuff #define NV3_PGRAPH_INTR_0 0x400100 #define NV3_PGRAPH_INTR_0_VBLANK 8 // Fired every frame #define NV3_PGRAPH_INTR_0_VBLANK_ENABLED 0x1 // Is the vblank interrupt enabled? +#define NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY 28 // Fired on software notification #define NV3_PGRAPH_INTR_1 0x400104 #define NV3_PGRAPH_INTR_1_INVALID_METHOD 0 // Invalid method @@ -578,7 +580,14 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_CHROMA_KEY 0x40062C #define NV3_PGRAPH_BETA 0x400640 // Beta factor (30:23 fractional, 22:0 before fraction) #define NV3_PGRAPH_DMA 0x400680 -#define NV3_PGRAPH_NOTIFY 0x400684 // Notifier for PGRAPH + +// Current notification object for pgraph +#define NV3_PGRAPH_NOTIFY 0x400684 // Notifier for PGRAPH +#define NV3_PGRAPH_NOTIFY_INSTANCE 0 +#define NV3_PGRAPH_NOTIFY_REQUEST_PENDING 16 +#define NV3_PGRAPH_NOTIFY_REQUEST_TYPE 20 +#define NV3_PGRAPH_NOTIFY_REQUEST_TYPE_HARDWARE 0x0 // anything else is software + #define NV3_PGRAPH_CLIP0_MIN 0x400690 // Clip for Blitting 0 Min #define NV3_PGRAPH_CLIP0_MAX 0x400694 // Clip for Blitting 0 Max #define NV3_PGRAPH_CLIP1_MIN 0x400698 // Clip for Blitting 1 Min @@ -882,11 +891,6 @@ typedef struct nv3_pci_config_s uint8_t int_line; } nv3_pci_config_t; -/* Notifier Engine */ -typedef struct nv3_notifier_s -{ - /* TODO */ -} nv3_notifier_t; // add enums for eac // Chip configuration @@ -1187,7 +1191,7 @@ typedef struct nv3_pgraph_s uint32_t bpixel[NV3_PGRAPH_MAX_BUFFERS]; // Pixel format for each possible surfaces. // CLIP nv3_pgraph_clip_misc_settings_t clip_misc_settings; - nv3_notifier_t notifier; + uint32_t notifier; bool notify_pending; // Determines if a notification is pending. nv3_position_16_bigy_t clip0_min; nv3_position_16_bigy_t clip0_max; diff --git a/src/sound/snd_emu8k.c b/src/sound/snd_emu8k.c index 822abeeaa..c32c16be1 100644 --- a/src/sound/snd_emu8k.c +++ b/src/sound/snd_emu8k.c @@ -1525,7 +1525,7 @@ emu8k_outw(uint16_t addr, uint16_t val, void *priv) default: break; } - emu8k_log("EMU8K WRITE: Unknown register write: %04X-%02X(%d/%d): %04X \n", addr, (emu8k->cur_reg) << 5 | emu8k->cur_voice, + emu8k_log("EMU8K WRITE: : Unknown register write: %04X-%02X(%d/%d): %04X \n", addr, (emu8k->cur_reg) << 5 | emu8k->cur_voice, emu8k->cur_reg, emu8k->cur_voice, val); } diff --git a/src/sound/snd_sb.c b/src/sound/snd_sb.c index e89946486..160e79881 100644 --- a/src/sound/snd_sb.c +++ b/src/sound/snd_sb.c @@ -798,7 +798,7 @@ sb_ct1335_mixer_write(uint16_t addr, uint8_t val, void *priv) break; default: - sb_log("sb_ct1335: Unknown register WRITE: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); + sb_log("sb_ct1335: : Unknown register write: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); break; } } @@ -899,7 +899,7 @@ sb_ct1345_mixer_write(uint16_t addr, uint8_t val, void *priv) break; default: - sb_log("sb_ct1345: Unknown register WRITE: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); + sb_log("sb_ct1345: : Unknown register write: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); break; } } diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index abeb0571b..fcfe1e7c4 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -29,10 +29,31 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { + // set up the current notification request/object] + // check for double notifiers. + case NV3_SET_NOTIFY: + if (nv3->pgraph.notify_pending) + { + nv_log("Executed method NV3_SET_NOTIFY with nv3->pgraph.notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); + nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); + nv3_debug_ramin_print_context_info(param, context); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + + // disable + nv3->pgraph.notify_pending = false; + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + /* may need to disable fifo in this state */ + return; + } + + // set a notify as pending. + nv3->pgraph.notifier = param; + nv3->pgraph.notify_pending = true; + break; default: nv_log("Shared Generic Methods: Invalid or Unimplemented method 0x%04x", method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); @@ -44,18 +65,19 @@ void nv3_generic_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t c /* Sees if any notification is required after an object method is executed. If so, executes it... */ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { - if (nv3->pgraph.notify_pending) - { - nv_log("Called nv3_notify_if_needed with nv3->pgraph.notify_pending already set. name=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); - nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); - nv3_debug_ramin_print_context_info(name, context); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - - // disable - nv3->pgraph.notify_pending = false; + if (!nv3->pgraph.notify_pending) return; - } + uint32_t current_notification_object = nv3->pgraph.notifier; + + // check for a software method (0 = hardware, 1 = software) + if (((current_notification_object >> NV3_PGRAPH_NOTIFY_REQUEST_TYPE) & 0x07) != 0) + { + nv_log("Software Notification, firing interrupt"); + nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY); + return; + } + // set up the NvNotification structure nv3_notification_t notify = {0}; notify.nanoseconds = nv3->ptimer.time; @@ -79,7 +101,8 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t /* paging information */ bool page_is_present = notify_obj_page & 0x01; bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); - uint32_t frame_value = (notify_obj_page >> NV3_NOTIFICATION_PAGE_FRAME_ADDRESS) & 0xFFFFF; + //uint32_t frame_value = (notify_obj_page >> NV3_NOTIFICATION_PAGE_FRAME_ADDRESS) & 0xFFFFF; + uint32_t frame_value = (notify_obj_page >> NV3_NOTIFICATION_PAGE_FRAME_ADDRESS) & 0xFFFFF000; // This code is temporary and will probably be moved somewhere else // Print torns of debug info @@ -99,18 +122,18 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t nv_log("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); break; case NV3_NOTIFICATION_TARGET_PCI: - (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log("Notification Target: PCI Bus\n") : nv_log("Notification Target: PCI Bus (On AGP card???)\n"); + (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log("Notification Target: PCI Bus\n") : nv_log("Notification Target: PCI Bus (On AGP card?)\n"); break; case NV3_NOTIFICATION_TARGET_AGP: (nv3->nvbase.bus_generation == nv_bus_agp_1x - || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log("Notification Target: AGP Bus\n") : nv_log("Notification Target: AGP Bus (On PCI card???)\n"); + || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log("Notification Target: AGP Bus\n") : nv_log("Notification Target: AGP Bus (On PCI card?)\n"); break; } - nv_log("Limit: 0x%08x", notify_obj_limit); + nv_log("Limit: 0x%08x\n", notify_obj_limit); (page_is_present) ? nv_log("Page is present\n") : nv_log("Page is not present\n"); (page_is_readwrite) ? nv_log("Page is read-write\n") : nv_log("Page is read-only\n"); - nv_log("Pageframe Address: 0x%08x", frame_value); + nv_log("Pageframe Address: 0x%08x\n", frame_value); #endif // set up the dma transfer. we need to translate to a physical address. diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 2594e0739..ca631edfc 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -122,6 +122,10 @@ void nv3_pbus_write(uint32_t address, uint32_t value) } } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } uint8_t nv3_pbus_rma_read(uint16_t addr) diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 6d8cadbf0..c26266a00 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -150,4 +150,8 @@ void nv3_pextdev_write(uint32_t address, uint32_t value) if (reg->on_write) reg->on_write(value); } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 92a643502..f7d80a41a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -152,6 +152,10 @@ void nv3_pfb_write(uint32_t address, uint32_t value) } } } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } uint32_t nv3_pfb_config0_read() diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index a836fdd21..073599577 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -599,7 +599,6 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.cache1_entries[real_entry].subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method); } - } /* Handle some special memory areas */ else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) @@ -609,6 +608,10 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val); } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } /* Trigger DMA for notifications if we need to */ nv3_pfifo_trigger_dma_if_required(); @@ -620,6 +623,7 @@ https://en.wikipedia.org/wiki/Gray_code WHY?????? IT'S NOT A TELEGRAPH IT'S A GPU????? Convert from a normal number to a total insanity number which is only used in PFIFO CACHE1 for ungodly and totally unknowable reasons +(Possibly it just makes it easier to implement in logic) I decided to use a lookup table to save everyone's time, also the numbers generated from the function that existed here before didn't make any sense diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 5851d9301..93fe8c32f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -472,6 +472,10 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) nv_log("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value); nv3->pgraph.context_cache[entry] = value; } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } } @@ -506,6 +510,7 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe // we need to shift left by 4 to get the real address, something to do with the 16 byte unit of reversal uint32_t real_ramin_base = context.ramin_offset << 4; + // readin our grobj grobj.grobj_0 = nv3_ramin_read32(real_ramin_base, nv3); grobj.grobj_1 = nv3_ramin_read32(real_ramin_base + 4, nv3); grobj.grobj_2 = nv3_ramin_read32(real_ramin_base + 8, nv3); @@ -514,80 +519,90 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe nv_log("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", method, param, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); - // By this point, we already ANDed the class ID to 0x1F. - // Send the grobj, the context, the method and the name off to actually be acted upon. - switch (class_id) + /* Methods below 0x104 are shared across all classids, so call generic_method for that*/ + if (method <= NV3_SET_NOTIFY) { - case nv3_pgraph_class01_beta_factor: - nv3_class_001_method(param, method, context, grobj); - break; - case nv3_pgraph_class02_rop: - nv3_class_002_method(param, method, context, grobj); - break; - case nv3_pgraph_class03_chroma_key: - nv3_class_003_method(param, method, context, grobj); - break; - case nv3_pgraph_class04_plane_mask: - nv3_class_004_method(param, method, context, grobj); - break; - case nv3_pgraph_class05_clipping_rectangle: - nv3_class_005_method(param, method, context, grobj); - break; - case nv3_pgraph_class06_pattern: - nv3_class_006_method(param, method, context, grobj); - break; - case nv3_pgraph_class07_rectangle: - nv3_class_007_method(param, method, context, grobj); - break; - case nv3_pgraph_class08_point: - nv3_class_008_method(param, method, context, grobj); - break; - case nv3_pgraph_class09_line: - nv3_class_009_method(param, method, context, grobj); - break; - case nv3_pgraph_class0a_lin: - nv3_class_00a_method(param, method, context, grobj); - break; - case nv3_pgraph_class0b_triangle: - nv3_class_00b_method(param, method, context, grobj); - break; - case nv3_pgraph_class0c_w95txt: - nv3_class_00c_method(param, method, context, grobj); - break; - case nv3_pgraph_class0d_m2mf: - nv3_class_00d_method(param, method, context, grobj); - break; - case nv3_pgraph_class0e_scaled_image_from_memory: - nv3_class_00e_method(param, method, context, grobj); - break; - case nv3_pgraph_class10_blit: - nv3_class_010_method(param, method, context, grobj); - break; - case nv3_pgraph_class11_image: - nv3_class_011_method(param, method, context, grobj); - break; - case nv3_pgraph_class12_bitmap: - nv3_class_012_method(param, method, context, grobj); - break; - case nv3_pgraph_class14_transfer2memory: - nv3_class_014_method(param, method, context, grobj); - break; - case nv3_pgraph_class15_stretched_image_from_cpu: - nv3_class_015_method(param, method, context, grobj); - break; - case nv3_pgraph_class17_d3d5tri_zeta_buffer: - nv3_class_017_method(param, method, context, grobj); - break; - case nv3_pgraph_class18_point_zeta_buffer: - nv3_class_018_method(param, method, context, grobj); - break; - case nv3_pgraph_class1c_image_in_memory: - nv3_class_01c_method(param, method, context, grobj); - break; - default: - fatal("NV3 (nv3_pgraph_arbitrate_method): Attempted to execute method on invalid, or unimplemented, class ID %s", nv3_class_names[class_id]); - return; + nv3_generic_method(param, method, context, grobj); } + else + { + // By this point, we already ANDed the class ID to 0x1F. + // Send the grobj, the context, the method and the name off to actually be acted upon. + switch (class_id) + { + case nv3_pgraph_class01_beta_factor: + nv3_class_001_method(param, method, context, grobj); + break; + case nv3_pgraph_class02_rop: + nv3_class_002_method(param, method, context, grobj); + break; + case nv3_pgraph_class03_chroma_key: + nv3_class_003_method(param, method, context, grobj); + break; + case nv3_pgraph_class04_plane_mask: + nv3_class_004_method(param, method, context, grobj); + break; + case nv3_pgraph_class05_clipping_rectangle: + nv3_class_005_method(param, method, context, grobj); + break; + case nv3_pgraph_class06_pattern: + nv3_class_006_method(param, method, context, grobj); + break; + case nv3_pgraph_class07_rectangle: + nv3_class_007_method(param, method, context, grobj); + break; + case nv3_pgraph_class08_point: + nv3_class_008_method(param, method, context, grobj); + break; + case nv3_pgraph_class09_line: + nv3_class_009_method(param, method, context, grobj); + break; + case nv3_pgraph_class0a_lin: + nv3_class_00a_method(param, method, context, grobj); + break; + case nv3_pgraph_class0b_triangle: + nv3_class_00b_method(param, method, context, grobj); + break; + case nv3_pgraph_class0c_w95txt: + nv3_class_00c_method(param, method, context, grobj); + break; + case nv3_pgraph_class0d_m2mf: + nv3_class_00d_method(param, method, context, grobj); + break; + case nv3_pgraph_class0e_scaled_image_from_memory: + nv3_class_00e_method(param, method, context, grobj); + break; + case nv3_pgraph_class10_blit: + nv3_class_010_method(param, method, context, grobj); + break; + case nv3_pgraph_class11_image: + nv3_class_011_method(param, method, context, grobj); + break; + case nv3_pgraph_class12_bitmap: + nv3_class_012_method(param, method, context, grobj); + break; + case nv3_pgraph_class14_transfer2memory: + nv3_class_014_method(param, method, context, grobj); + break; + case nv3_pgraph_class15_stretched_image_from_cpu: + nv3_class_015_method(param, method, context, grobj); + break; + case nv3_pgraph_class17_d3d5tri_zeta_buffer: + nv3_class_017_method(param, method, context, grobj); + break; + case nv3_pgraph_class18_point_zeta_buffer: + nv3_class_018_method(param, method, context, grobj); + break; + case nv3_pgraph_class1c_image_in_memory: + nv3_class_01c_method(param, method, context, grobj); + break; + default: + fatal("NV3 (nv3_pgraph_arbitrate_method): Attempted to execute method on invalid, or unimplemented, class ID %s", nv3_class_names[class_id]); + return; + } + } + + nv3_notify_if_needed(param, method, context, grobj); } diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index f67eb707b..24f0ad44a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -269,4 +269,8 @@ void nv3_pmc_write(uint32_t address, uint32_t value) nv_log("\n"); } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index e555c9752..d7f6f0cf9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -128,4 +128,9 @@ void nv3_pme_write(uint32_t address, uint32_t value) } } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 6ff090716..c9430018f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -377,4 +377,9 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) } } } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index aa5942ad8..b5c278387 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -222,4 +222,8 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) } } } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index db6e78a59..6f72da719 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -152,5 +152,8 @@ void nv3_pvideo_write(uint32_t address, uint32_t value) } } } - + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } } \ No newline at end of file diff --git a/src/video/vid_voodoo.c b/src/video/vid_voodoo.c index e45f112ed..8f6e8bf26 100644 --- a/src/video/vid_voodoo.c +++ b/src/video/vid_voodoo.c @@ -676,7 +676,7 @@ voodoo_writel(uint32_t addr, uint32_t val, void *priv) default: if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE) { - voodoo_log("Unknown register write in CMDFIFO mode %08x %08x\n", addr, val); + voodoo_log(": Unknown register write in CMDFIFO mode %08x %08x\n", addr, val); } else { voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val); } From fea521d3ac56be29c0d77a9d234bfd47aa652a69 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 20 Mar 2025 01:39:35 +0000 Subject: [PATCH 123/274] At least partially working notifiers that seem to do something --- .../nv/nv3/classes/nv3_class_shared_methods.c | 46 +++++++++++++++++-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 7 ++- src/video/nv/nv3/subsystems/nv3_pramin.c | 6 +-- 3 files changed, 49 insertions(+), 10 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index fcfe1e7c4..2141f238b 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -69,13 +69,14 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t return; uint32_t current_notification_object = nv3->pgraph.notifier; + uint32_t notification_type = ((current_notification_object >> NV3_PGRAPH_NOTIFY_REQUEST_TYPE) & 0x07); // check for a software method (0 = hardware, 1 = software) - if (((current_notification_object >> NV3_PGRAPH_NOTIFY_REQUEST_TYPE) & 0x07) != 0) + if (notification_type != 0) { nv_log("Software Notification, firing interrupt"); nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY); - return; + //return; } // set up the NvNotification structure @@ -101,8 +102,7 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t /* paging information */ bool page_is_present = notify_obj_page & 0x01; bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); - //uint32_t frame_value = (notify_obj_page >> NV3_NOTIFICATION_PAGE_FRAME_ADDRESS) & 0xFFFFF; - uint32_t frame_value = (notify_obj_page >> NV3_NOTIFICATION_PAGE_FRAME_ADDRESS) & 0xFFFFF000; + uint32_t frame_base = notify_obj_page & 0xFFFFF000; // This code is temporary and will probably be moved somewhere else // Print torns of debug info @@ -133,8 +133,44 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t nv_log("Limit: 0x%08x\n", notify_obj_limit); (page_is_present) ? nv_log("Page is present\n") : nv_log("Page is not present\n"); (page_is_readwrite) ? nv_log("Page is read-write\n") : nv_log("Page is read-only\n"); - nv_log("Pageframe Address: 0x%08x\n", frame_value); + nv_log("Pageframe Address: 0x%08x\n", frame_base); #endif // set up the dma transfer. we need to translate to a physical address. + + uint32_t final_address = 0; + + /* Simple case: hardware notification, we can just take the pte since it's based on the type */ + if (notification_type == 0) + { + final_address = frame_base + info_adjust; + } + else + { + // for software we have to calculate the pte index + uint32_t pte_num = ((notification_type << 4) + info_adjust) >> 12; + + /* ramin entries are sorted - 1 object for each pte entry...*/ + final_address = nv3_ramin_read32(notify_obj_base + (0x10 * pte_num) + 8, nv3); + final_address += (info_adjust & 0xFFF); + } + + /* send the notification off */ + nv_log("About to send the notification to 0x%08x (Check target)", final_address); + switch (info_notification_target) + { + case NV3_NOTIFICATION_TARGET_NVM: + svga_writel_linear(final_address, (notify.nanoseconds & 0xFFFFFFFF), nv3); + svga_writel_linear(final_address + 4, (notify.nanoseconds >> 32), nv3); + svga_writel_linear(final_address + 8, notify.info32, nv3); + svga_writel_linear(final_address + 0x0C, (notify.info16 | notify.status), nv3); + break; + case NV3_NOTIFICATION_TARGET_PCI: + case NV3_NOTIFICATION_TARGET_AGP: + dma_bm_write(final_address, (uint8_t*)¬ify, sizeof(nv3_notification_t), 4); + break; + } + + // we're done + nv3->pgraph.notify_pending = false; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index c9430018f..099248f66 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -194,7 +194,10 @@ nv_register_t pramdac_registers[] = { NV3_PRAMDAC_GENERAL_CONTROL, "PRAMDAC - General Control", NULL, NULL }, { NV3_PRAMDAC_VSERR_WIDTH, "PRAMDAC - Vertical Sync Error Width", NULL, NULL}, { NV3_PRAMDAC_VEQU_END, "PRAMDAC - VEqu End", NULL, NULL}, + { NV3_PRAMDAC_VBBLANK_START, "PRAMDAC - VBBlank Start", NULL, NULL}, { NV3_PRAMDAC_VBBLANK_END, "PRAMDAC - VBBlank End", NULL, NULL}, + { NV3_PRAMDAC_HBLANK_END, "PRAMDAC - Horizontal Blanking Interval End", NULL, NULL}, + { NV3_PRAMDAC_HBLANK_START, "PRAMDAC - Horizontal Blanking Interval Start", NULL, NULL}, { NV3_PRAMDAC_VBLANK_END, "PRAMDAC - Vertical Blanking Interval End", NULL, NULL}, { NV3_PRAMDAC_VBLANK_START, "PRAMDAC - Vertical Blanking Interval Start", NULL, NULL}, { NV3_PRAMDAC_VEQU_START, "PRAMDAC - VEqu Start", NULL, NULL}, @@ -220,7 +223,7 @@ uint32_t nv3_pramdac_read(uint32_t address) // todo: friendly logging - nv_log("PRAMDAC Read from 0x%08x", address); + nv_log("PRAMDAC Read from 0x%08x\n", address); // if the register actually exists if (reg) @@ -301,7 +304,7 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); - nv_log("PRAMDAC Write 0x%08x -> 0x%08x", value, address); + nv_log("PRAMDAC Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index f85ae3f8e..439d44bd5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -434,14 +434,14 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // Perform more validation - if (obj_context_struct.class_id > NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID - || obj_context_struct.class_id < NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID) + if (obj_context_struct.class_id < NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID + || obj_context_struct.class_id > NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID) { fatal("NV3: Invalid graphics object class ID name=0x%04x type=%04x, interpreted by pgraph as: %04x (Contact starfrost)", name, obj_context_struct.class_id, obj_context_struct.class_id & 0x1F); } else if (obj_context_struct.channel > NV3_DMA_CHANNELS) - fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-8", obj_context_struct.channel); + fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-7", obj_context_struct.channel); // Illegal accesses sent to RAMRO, so ignore here // TODO: SEND THESE TO RAMRO!!!!! From 275aef30c23e61e794f017ecbffe3192de48d0cf Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 20 Mar 2025 16:06:03 -0500 Subject: [PATCH 124/274] Fix build on Arch Linux --- src/video/nv/nv3/nv3_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index c56551b14..e7e71961d 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -1060,7 +1060,9 @@ void nv3_close(void* priv) { // Shut down logging log_close(nv3->nvbase.log); +#ifdef ENABLE_NV_LOG nv_log_set_device(NULL); +#endif // Shut down I2C and the DDC ddc_close(nv3->nvbase.ddc); From 57d725742e476d85c3e785ef12810cf5e208eae5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 20 Mar 2025 21:35:56 +0000 Subject: [PATCH 125/274] it's definitely argb + some fixes --- src/include/86box/nv/classes/vid_nv3_classes.h | 15 +++------------ src/include/86box/nv/vid_nv3.h | 3 +-- .../nv3/classes/nv3_class_01c_image_in_memory.c | 4 ++-- .../nv/nv3/classes/nv3_class_shared_methods.c | 6 +++--- src/video/nv/nv3/render/nv3_render_core.c | 3 ++- src/video/nv/nv3/subsystems/nv3_pfb.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- 8 files changed, 14 insertions(+), 23 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index e1458671e..f3788040e 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -100,22 +100,13 @@ typedef struct nv3_class_ctx_switch_method_s } nv3_class_ctx_switch_method_t; -/* 32-bit BGRA format colour for 2D acceleration */ -typedef struct nv3_color_bgra_32_s -{ - uint8_t b; - uint8_t g; - uint8_t r; - uint8_t a; -} nv3_color_bgra_32_t; - /* 32-bit ARGB format colour for internal D3D5 stuff */ typedef struct nv3_color_argb_32_s { + uint8_t a; uint8_t r; uint8_t g; uint8_t b; - uint8_t a; } nv3_color_argb_32_t; /* 30-bit colour format for internal PGRAPH use */ @@ -375,7 +366,7 @@ typedef struct nv3_object_class_007 /* In case your points weren't colourful enough */ typedef struct nv3_object_class_008_cpoint_s { - nv3_color_argb_32_t color; // BGRA-format 32-bit color + nv3_color_argb_32_t color; // argb-format 32-bit color nv3_position_16_t position; // } nv3_object_class_008_cpoint_t; @@ -1083,7 +1074,7 @@ typedef struct nv3_d3d5_alpha_control_s typedef struct nv3_d3d5_coordinate_s { nv3_d3d5_specular_t specular_reflection_parameters; - nv3_color_bgra_32_t color; // YOU HAVE TO FLIP THE ENDIANNESS. NVIDIA??? WHAT??? + nv3_color_argb_32_t color; // YOU HAVE TO FLIP THE ENDIANNESS. NVIDIA??? WHAT??? // Seems more plausible for these specifically to be floats. // Also makes my life easier... diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 3756a47ed..e5117366a 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -35,10 +35,9 @@ extern const device_config_t nv3_config[]; #define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start #define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN -// DMA channels are basically the number of contexts that the gpu can deal with at once. +// THere are 64 DMA channels grouped into 8 "channels" with 8 "subchannels" each. You can only use one channel at a time. An arbitrary number of 8 objects can be submitted. // Channel 0 is always taken up by NV drivers. -// Subchannels deal with specific parts of the GPU and are manipulated by the driver to manipulate the gpu. #define NV3_DMA_CHANNELS 8 #define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8 diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 547ffc441..30d6aee17 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -69,13 +69,13 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.image_in_memory.pitch = param & 0x1FF0; nv3->pgraph.bpitch[src_buffer_id] = param & 0x1FF0; // 12:0 - nv_log("Image in Memory BUFL%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); + nv_log("Image in Memory BUF%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); break; /* Byte offset in GPU VRAM of top left pixel (22:0) */ case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: nv3->pgraph.boffset[src_buffer_id] = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); - nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.image_in_memory.linear_address); + nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 2141f238b..2f24daa41 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -84,8 +84,8 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t notify.nanoseconds = nv3->ptimer.time; notify.status = NV3_NOTIFICATION_STATUS_DONE_OK; // it should be fine to just signal that it's ok - // this is completely speculative and i have no idea - notify.info32 = grobj.grobj_0; + // these are only nonzero when there is an error + notify.info32 = notify.info16 = 0; // notify object base=grobj_1 >> 12 uint32_t notify_obj_base = grobj.grobj_1 >> 12; @@ -156,7 +156,7 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t } /* send the notification off */ - nv_log("About to send the notification to 0x%08x (Check target)", final_address); + nv_log("About to send hardware notification to 0x%08x (Check target)\n", final_address); switch (info_notification_target) { case NV3_NOTIFICATION_TARGET_NVM: diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 8b5771f36..57df42b39 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -33,4 +33,5 @@ uint32_t nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, nv3_render_operation_type rop) { return video_rop_gdi_ternary(rop, dst, pattern, src); -} \ No newline at end of file +} + diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index f7d80a41a..160cbff08 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -172,7 +172,7 @@ void nv3_pfb_config0_write(uint32_t val) uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; // i don't think 16:9 is supported - uint32_t new_pfb_vtotal = new_pfb_htotal * (4.0/3.0); + uint32_t new_pfb_vtotal = new_pfb_htotal * (3.0/4.0); uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; nv_log("Framebuffer Config Change\n"); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 073599577..f9e72c71f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -824,7 +824,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; - nv_log("Submitted object [PIO]: Channel %d.%d, Object Name 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", + nv_log("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", channel, subchannel, object_name, method_offset, nv3->pfifo.cache1_settings.put_address); // Now we're done. Phew! diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 439d44bd5..7a5ff749b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -440,7 +440,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u fatal("NV3: Invalid graphics object class ID name=0x%04x type=%04x, interpreted by pgraph as: %04x (Contact starfrost)", name, obj_context_struct.class_id, obj_context_struct.class_id & 0x1F); } - else if (obj_context_struct.channel > NV3_DMA_CHANNELS) + else if (obj_context_struct.channel > (NV3_DMA_CHANNELS - 1)) fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-7", obj_context_struct.channel); // Illegal accesses sent to RAMRO, so ignore here From 69c4b11f7b46786eff6ec7654d22276ed67c7409 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 21 Mar 2025 00:50:29 +0000 Subject: [PATCH 126/274] Rename name to param to represent that it is the parameter. Add pixel writing code, add rectangle rendering code. Implement ROP, Rectangle and Clip class methods. However, the drivers BSOD. --- doc/nvidia_notes/NV128.xlsx | Bin 9615 -> 9708 bytes .../86box/nv/classes/vid_nv3_classes.h | 112 ++++++++---- src/include/86box/nv/render/vid_nv3_render.h | 5 + src/include/86box/nv/vid_nv3.h | 57 +++--- src/include/86box/utils/video_stdlib.h | 2 +- src/utils/video/video_rop.c | 2 +- src/video/CMakeLists.txt | 1 + .../nv3/classes/nv3_class_001_beta_factor.c | 2 +- src/video/nv/nv3/classes/nv3_class_002_rop.c | 5 +- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 2 +- .../nv/nv3/classes/nv3_class_004_plane_mask.c | 2 +- .../nv3_class_005_clipping_rectangle.c | 12 +- .../nv/nv3/classes/nv3_class_006_pattern.c | 2 +- .../nv/nv3/classes/nv3_class_007_rectangle.c | 33 +++- .../nv/nv3/classes/nv3_class_008_point.c | 2 +- src/video/nv/nv3/classes/nv3_class_009_line.c | 2 +- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 2 +- .../nv/nv3/classes/nv3_class_00b_triangle.c | 2 +- .../classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 2 +- .../nv3_class_00e_scaled_image_from_mem.c | 2 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- .../nv/nv3/classes/nv3_class_011_image.c | 2 +- .../nv/nv3/classes/nv3_class_012_bitmap.c | 2 +- .../classes/nv3_class_014_transfer2memory.c | 2 +- .../nv3_class_015_stretched_image_from_cpu.c | 2 +- .../nv3_class_017_d3d5_tri_zeta_buffer.c | 2 +- .../classes/nv3_class_018_point_zeta_buffer.c | 2 +- .../classes/nv3_class_01c_image_in_memory.c | 1 + .../nv/nv3/classes/nv3_class_shared_methods.c | 1 + src/video/nv/nv3/render/nv3_render_core.c | 171 ++++++++++++++++++ .../nv/nv3/render/nv3_render_primitives.c | 46 +++++ 32 files changed, 395 insertions(+), 89 deletions(-) create mode 100644 src/video/nv/nv3/render/nv3_render_primitives.c diff --git a/doc/nvidia_notes/NV128.xlsx b/doc/nvidia_notes/NV128.xlsx index 919297d56816e5278deb74887f1c321198297f08..fbf57c5eb136926abfc26b411f6aec0ae899a3fc 100644 GIT binary patch delta 2944 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zjta7tev*kd81-N5bJ`#9JHNx^4CKH??ETZTj}N*T#G=sw*2qpz|#xBo5Y-RLu` zvGalrBg4^o0e01T@zy-wvrd?u8{@W`)aILe7wq^T3y~gEbLxD&Khy;ymc5&!1d)Do zD`|#P?qs{C<==1R{-mjIzE8VTZVan+YB610vfByKRquwqME`3L3{hvNZEMd%l|g8y z+)NWze`eE!(_n@RNr9ro=_C`&bl-7w;8Z~UW#N0q14NerqJ$IFllxu_p~RM7td@nb zu#u-^%4>~y^MRU7_2cs$vTsE6{>zo99#XgV2lnzE)n5du>+QAVa~Ck&eXLtR-YuM)__PjfS8 zl*U*EU^M)94sF|Qsy`$AaFoO$d4l_x|500m74$> ziC_>V*tM&OfS=*@)LlegE_nCX;7RsY448L^kD}8_6%&J*`og6;&x)9BPp*>Q)uxG< z)3g40Npb7qrVQJx0DuFZ62RF=a6 #include <86box/nv/vid_nv3.h> -void nv3_class_001_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index b771551d3..9286c180c 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -28,10 +28,13 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_002_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_002_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { + case NV3_ROP_SET_ROP: + nv3->pgraph.rop = param & 0xFF; + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 73901d08d..06750521e 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_003_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 48a96ab96..10788b5ce 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_004_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_004_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 1119147e7..8ba698aa5 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -27,10 +27,20 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_005_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { + case NV3_CLIP_POSITION: + nv3->pgraph.clip_start.x = (param >> 16) & 0xFFFF; + nv3->pgraph.clip_start.y = (param) & 0xFFFF; + nv_log("Clip Position: %d,%d", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + break; + case NV3_CLIP_SIZE: + nv3->pgraph.clip_size.x = (param >> 16) & 0xFFFF; + nv3->pgraph.clip_size.y = (param) & 0xFFFF; + nv_log("Clip Size: %d,%d", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index c8c81066f..ee3348669 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_006_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 69e66ca31..dd82030ca 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -28,12 +28,41 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_007_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { + case NV3_RECTANGLE_COLOR: + nv3->pgraph.rectangle.color = param; + break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + /* Check for any rectangle point or size method. */ + if (method_id >= NV3_RECTANGLE_START && method_id <= NV3_RECTNAGLE_END) + { + uint32_t index = (method_id - NV3_RECTANGLE_START) / 8; + + // If the size is submitted, render it. + if (method_id & 0x04) + { + nv3->pgraph.rectangle.size[index].w = (param >> 16) & 0xFFFF; + nv3->pgraph.rectangle.size[index].h = param & 0xFFFF; + + nv_log("Rect%d Size=%d,%d\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h); + + nv3_render_rect(nv3->pgraph.rectangle.position[index], nv3->pgraph.rectangle.size[index], nv3->pgraph.rectangle.color, grobj); + } + else // position + { + nv3->pgraph.rectangle.position[index].x = (param >> 16) & 0xFFFF; + nv3->pgraph.rectangle.position[index].y = param & 0xFFFF; + + nv_log("Rect%d Position=%d,%d\n", index, nv3->pgraph.rectangle.position[index].x, nv3->pgraph.rectangle.position[index].y); + } + + return; + } + + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 0cd44b8cd..8647b27cb 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_008_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_008_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index 8d71f4d5e..dddbf5719 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_009_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_009_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 141a2422c..45f1c97b9 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -29,7 +29,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_00a_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_00a_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index 91cbaa837..e3bbf9f07 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_00b_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_00b_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 3ba352b3c..66eddee71 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_00c_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 888ac89cf..687e1e763 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_00d_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index bf0286c20..f4bc8d6ee 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_00e_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_00e_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index da2f16bda..c502bdd28 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_010_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 4499693df..36679cb7f 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_011_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index ca8540b75..2ce3fb685 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -29,7 +29,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_012_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_012_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index 6a18ff1d7..86be6a74a 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -29,7 +29,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_014_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_014_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index c8560ad0f..5b499b73d 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_015_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_015_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 951ba862d..4f1e73774 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -28,7 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_class_017_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_017_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 80f10797f..4829fafb9 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -30,7 +30,7 @@ struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; -void nv3_class_018_method(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) +void nv3_class_018_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 30d6aee17..d55ee9511 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -60,6 +60,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* Set the format */ nv3->pgraph.bpixel[src_buffer_id] = ((real_format & 0x03) | NV3_BPIXEL_FORMAT_IS_VALID); + nv_log("Image in Memory BUF%d COLOR_FORMAT=0x%04x", src_buffer_id, param); break; diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 2f24daa41..38d45f70e 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -157,6 +157,7 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t /* send the notification off */ nv_log("About to send hardware notification to 0x%08x (Check target)\n", final_address); + switch (info_notification_target) { case NV3_NOTIFICATION_TARGET_NVM: diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 57df42b39..4dff864e0 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -35,3 +35,174 @@ uint32_t nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, nv3_rende return video_rop_gdi_ternary(rop, dst, pattern, src); } +/* Expand a colour. + NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! +*/ +nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) +{ + // grobj0 = seems to share the format of PGRAPH_CONTEXT_SWITCH register. + + uint8_t format = (grobj.grobj_0 & 0x07); + bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + + nv3_color_expanded_t color_final; + // set the pixel format + color_final.pixel_format = format; + + #ifdef ENABLE_NV_LOG + nv_log("Expanding Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d", color, format, alpha_enabled); + #endif + + // default to fully opaque in case alpha is disabled + color_final.a = 0xFF; + + switch (format) + { + // ALL OF THESE TYPES ARE 32 BITS IN SIZE + + // 555 + case nv3_pgraph_pixel_format_r5g5b5: + nv3_color_16_a1r5g5b5_t new_color = *(nv3_color_16_a1r5g5b5_t*)&color; + // "stretch out" the colour + color_final.r = new_color.r * 0x20; + color_final.g = new_color.g * 0x20; + color_final.b = new_color.b * 0x20; + + if (alpha_enabled) + color_final.a = new_color.a; + + break; + // 888 (standard colour + 8-bit alpha) + case nv3_pgraph_pixel_format_r8g8b8: + if (alpha_enabled) + color_final.a = ((color >> 24) & 0xFF) * 4; + + color_final.r = ((color >> 16) & 0xFF) * 4; + color_final.g = ((color >> 8) & 0xFF) * 4; + color_final.b = (color & 0xFF) * 4; + + if (alpha_enabled) + color_final.a = new_color.a; + break; + case nv3_pgraph_pixel_format_r10g10b10: + nv3_color_x2a10g10b10_t new_color_rgb10 = *(nv3_color_x2a10g10b10_t*)&color; + + color_final.r = new_color_rgb10.r; + color_final.g = new_color_rgb10.g; + color_final.b = new_color_rgb10.b; + + if (alpha_enabled) + color_final.a = new_color.a; + + break; + case nv3_pgraph_pixel_format_y8: + color_final.a = (color >> 8) & 0xFF; + + // yuv + color_final.r = color_final.g = color_final.b = (color & 0xFF) * 4; // convert to rgb10 + break; + case nv3_pgraph_pixel_format_y16: + color_final.a = (color >> 16) & 0xFFFF; + + // yuv + color_final.r = color_final.g = color_final.b = (color & 0xFFFF) * 4; // convert to rgb10 + break; + default: + + } + + // i8 is a union under i16 + color_final.i16 = (color & 0xFFFF); + + return color_final; +} + +/* Convert expanded colour format to chroma key format */ +uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) +{ + // convert the alpha to 1 bit. then return packed rgb10 + return !!expanded.a | (expanded.r << 30) | (expanded.b << 20) | (expanded.a << 10); +} + +/* Plots a pixel. */ +void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj) +{ + uint8_t alpha = 0xFF; + + // PFB_0 is always set to hardcoded "NO_TILING" value of 0x1114. + // It seems, you are meant to + + /* put this here for debugging + it may be needed later. */ + #ifdef DEBUG + uint8_t color_format_object = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_COLOR_FORMAT) & 0x07; + #endif + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too? + uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + + /* doesn't seem*/ + nv3_color_argb_t color_data = *(nv3_color_argb_t*)&color; + + if (framebuffer_bpp == 32) + alpha = color_data.a; + + int32_t clip_end_x = nv3->pgraph.clip_start.x + nv3->pgraph.clip_size.x; + int32_t clip_end_y = nv3->pgraph.clip_start.y + nv3->pgraph.clip_size.y; + + /* First, check our current buffer. */ + /* Then do the clip. */ + if (position.x < nv3->pgraph.clip_start.x + || position.y < nv3->pgraph.clip_start.y + || position.x > clip_end_x + || position.y > clip_end_y) + { + // DO NOT DRAW THE PIXEL + return; + } + + /* TODO: Chroma Key, Pattern, Plane Mask...*/ + + /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from. */ + uint32_t pixel_addr_vram = position.x + (nv3->pgraph.bpitch[current_buffer]) * position.y + nv3->pgraph.boffset[current_buffer]; + + pixel_addr_vram &= nv3->nvbase.svga.vram_mask; + + /* Go to vram and do the final ROP for a basic bitblit. + It seems we can skip the downconversion step *for now*, since (framebuffer bits per pixel) == (object bits per pixel) + I'm not sure how games will react. But it depends on how the D3D drivers operate, we may need ro convert texture formats to the current bpp internally. + + TODO: MOVE TO BPIXEL DEPTH or GROBJ0 to determine this, once we figure out how to get the bpixel depth. + */ + + uint32_t src = 0, dst = 0; + + switch (framebuffer_bpp) + { + case 8: + src = color & 0xFF; + dst = nv3->nvbase.svga.vram[pixel_addr_vram]; + nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + + break; + case 16: + uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); + pixel_addr_vram >>= 1; + + src = color & 0xFFFF; + dst = vram_16[pixel_addr_vram]; + nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + + break; + case 32: + uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); + pixel_addr_vram >>= 2; + + src = color; + dst = vram_32[pixel_addr_vram]; + nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + + break; + } + + nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; + +} \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c new file mode 100644 index 000000000..e44636acb --- /dev/null +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -0,0 +1,46 @@ +/* +* 86Box A hypervisor and IBM PC system emulator that specializes in +* running old operating systems and software designed for IBM +* PC systems and compatibles from 1981 through fairly recent +* system designs based on the PCI bus. +* +* This file is part of the 86Box distribution. +* +* NV3 code to render basic objects. +* +* +* +* Authors: Connor Hyde, I need a better email address ;^) +* +* Copyright 2024-2025 Connor Hyde +*/ + +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> +#include <86box/utils/video_stdlib.h> + +void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj) +{ + nv3_position_16_t current_pos = {0}; + + for (int32_t y = position.y; y < (position.y + size.h); y++) + { + current_pos.y = y; + for (int32_t x = position.x; x < (position.x + size.w); x++) + { + current_pos.x = x; + + nv3_render_pixel(current_pos, color, grobj); + } + } +} \ No newline at end of file From b5321903de5b734de7bc44cc6ccae59c27d1847b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 00:57:31 +0000 Subject: [PATCH 127/274] rename intr_1_invalid_method to indicate that it seems to also be used for software ethods --- src/include/86box/nv/classes/vid_nv3_classes.h | 2 ++ src/include/86box/nv/vid_nv3.h | 6 ++++-- src/video/nv/nv3/classes/nv3_class_001_beta_factor.c | 2 +- src/video/nv/nv3/classes/nv3_class_002_rop.c | 2 +- src/video/nv/nv3/classes/nv3_class_003_chroma_key.c | 2 +- src/video/nv/nv3/classes/nv3_class_004_plane_mask.c | 2 +- src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c | 2 +- src/video/nv/nv3/classes/nv3_class_006_pattern.c | 2 +- src/video/nv/nv3/classes/nv3_class_007_rectangle.c | 2 +- src/video/nv/nv3/classes/nv3_class_008_point.c | 2 +- src/video/nv/nv3/classes/nv3_class_009_line.c | 2 +- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 2 +- src/video/nv/nv3/classes/nv3_class_00b_triangle.c | 2 +- src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 2 +- .../nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c | 2 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- src/video/nv/nv3/classes/nv3_class_011_image.c | 2 +- src/video/nv/nv3/classes/nv3_class_012_bitmap.c | 2 +- src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c | 2 +- .../nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c | 2 +- .../nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c | 2 +- src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c | 2 +- src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c | 6 +++++- src/video/nv/nv3/classes/nv3_class_shared_methods.c | 2 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 -- 26 files changed, 33 insertions(+), 27 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index b4f41fc30..c5c014245 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -79,6 +79,8 @@ typedef enum nv3_pgraph_class_e #define NV3_ROP_SET_ROP 0x0300 // Set GDI standard rop +#define NV3_BETA_FACTOR 0x0300 + #define NV3_CLIP_POSITION 0x0300 // S16:S16, 0=topleft #define NV3_CLIP_SIZE 0x0304 // U16:U16 diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index c1d0e3bdd..d7d7dc144 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -210,6 +210,8 @@ extern const device_config_t nv3_config[]; #define NV3_PBUS_END 0x1FFF #define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects) +#define NV3_PFIFO_MINIMUM_GUARANTEED_DEPTH 0x7C + #define NV3_PFIFO_DELAY_0 0x2040 // PFIFO Config Register #define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register #define NV3_PFIFO_CACHE0_ERROR_PENDING 0 @@ -286,7 +288,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE0_METHOD_END 0x3200 #define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 -#define NV3_PFIFO_CACHE1_PUSH0 0x3200 +#define NV3_PFIFO_CACHE1_PUSH0 0x3200 #define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 @@ -527,7 +529,7 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY 28 // Fired on software notification #define NV3_PGRAPH_INTR_1 0x400104 -#define NV3_PGRAPH_INTR_1_INVALID_METHOD 0 // Invalid method +#define NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING 0 // Software or invalid method #define NV3_PGRAPH_INTR_1_INVALID_DATA 4 // Invalid data. Not sure when this would be triggered. #define NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY 12 // Tried to notify while a notify was pending. #define NV3_PGRAPH_INTR_1_CTXSW_NOTIFY 16 // Notify fired for software context diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 2acf3a8f4..784da2eb0 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -34,7 +34,7 @@ void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index 9286c180c..38fe29d78 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -37,7 +37,7 @@ void nv3_class_002_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 06750521e..92a3cb225 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -34,7 +34,7 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 10788b5ce..9c9bced95 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -34,7 +34,7 @@ void nv3_class_004_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 8ba698aa5..10136feac 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -43,7 +43,7 @@ void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index ee3348669..2c2174447 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -34,7 +34,7 @@ void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index dd82030ca..f0e85f4db 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -63,7 +63,7 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 8647b27cb..4ffffba92 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -34,7 +34,7 @@ void nv3_class_008_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index dddbf5719..edb432884 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -34,7 +34,7 @@ void nv3_class_009_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 45f1c97b9..fc7dcc879 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -35,7 +35,7 @@ void nv3_class_00a_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index e3bbf9f07..08a205ac2 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -34,7 +34,7 @@ void nv3_class_00b_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 66eddee71..2b14ec2ff 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -34,7 +34,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 687e1e763..fa1f08811 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -34,7 +34,7 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index f4bc8d6ee..c4b68c34f 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -34,7 +34,7 @@ void nv3_class_00e_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index c502bdd28..3ff52f68a 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -34,7 +34,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 36679cb7f..b40b9025c 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -34,7 +34,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index 2ce3fb685..bbbb6997d 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -35,7 +35,7 @@ void nv3_class_012_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index 86be6a74a..47e4b0c32 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -35,7 +35,7 @@ void nv3_class_014_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index 5b499b73d..f1c571943 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -34,7 +34,7 @@ void nv3_class_015_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 4f1e73774..838c64aa7 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -34,7 +34,7 @@ void nv3_class_017_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 4829fafb9..904cac757 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -36,7 +36,7 @@ void nv3_class_018_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index d55ee9511..9ba86c0eb 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -64,6 +64,10 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Image in Memory BUF%d COLOR_FORMAT=0x%04x", src_buffer_id, param); break; + /* DOn't log invalid */ + case NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE: + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + break; /* Pitch - length between scanlines */ case NV3_IMAGE_IN_MEMORY_PITCH: @@ -80,7 +84,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 38d45f70e..7338c45ad 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -56,7 +56,7 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t break; default: nv_log("Shared Generic Methods: Invalid or Unimplemented method 0x%04x", method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_METHOD); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } } diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 93fe8c32f..eddf61dea 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -602,8 +602,6 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe } } - - nv3_notify_if_needed(param, method, context, grobj); } From b170c51307f29d4074a884c73c344d94ac7ffd7f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 02:05:36 +0000 Subject: [PATCH 128/274] fix the bsod (I hate bitfields). --- src/include/86box/nv/vid_nv3.h | 14 +++---- .../nv/nv3/classes/nv3_class_shared_methods.c | 9 +++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 41 ++++++++++++++++--- src/video/nv/nv3/subsystems/nv3_pgraph.c | 5 --- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 1 - 5 files changed, 49 insertions(+), 21 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index d7d7dc144..16fcee485 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -266,7 +266,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_PUSH0 0x3000 +#define NV3_PFIFO_CACHE0_PUSH0 0x3000 #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 @@ -309,11 +309,11 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULL0 0x3240 +#define NV3_PFIFO_CACHE1_PULL0 0x3240 //todo: merge stuff -#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware +#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 +#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE 0x3250 #define NV3_PFIFO_CACHE1_PULLER_CTX_STATE_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 @@ -997,8 +997,8 @@ typedef struct nv3_pfifo_cache_s typedef struct nv3_pfifo_cache_entry_s { - uint8_t subchannel : 3; - uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin) + uint16_t method; // method id depending on class (offset from entry channel start in ramin) + uint8_t subchannel; uint32_t data; // is this the context } nv3_pfifo_cache_entry_t; diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 7338c45ad..0bb12a2eb 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -33,8 +33,13 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t { switch (method_id) { - // set up the current notification request/object] - // check for double notifiers. + /* mthdCreate in software(?)*/ + case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: + nv_log("mthdCreate\n"); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + break; + // set up the current notification request/object + // and check for double notifiers. case NV3_SET_NOTIFY: if (nv3->pgraph.notify_pending) { diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index f9e72c71f..81b13e5bf 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -295,28 +295,57 @@ uint32_t nv3_pfifo_read(uint32_t address) { nv_log("PFIFO Cache0 Read\n"); - if (address & 4) + // See if we want the object name or the channel/subchannel information. + if (address & 4) + { + nv_log("Data=0x%08x\n", nv3->pfifo.cache0_entry.data); return nv3->pfifo.cache0_entry.data; + } else + { + uint32_t method = nv3->pfifo.cache0_entry.method; + uint32_t subchannel = nv3->pfifo.cache0_entry.subchannel; + uint32_t final = nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + + nv_log("Method=0x%08x, ", nv3->pfifo.cache0_entry.method); + nv_log("Subchannel=0x%08x\n", nv3->pfifo.cache0_entry.subchannel); + nv_log("Final=0x%08x\n", final); + return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + } } else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) { // Not sure if REV C changes this. It should... uint32_t slot = 0; + // shift right by 3, convert from address, to slot. if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) slot = (address >> 3) & 0x3F; else slot = (address >> 3) & 0x1F; - nv_log("PFIFO Cache1 Read slot=%d\n", slot); + nv_log("PFIFO Cache1 Read slot=%d", slot); // See if we want the object name or the channel/subchannel information. if (address & 4) + { + nv_log("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data); return nv3->pfifo.cache1_entries[slot].data; + } else + { + uint32_t method = nv3->pfifo.cache1_entries[slot].method; + uint32_t subchannel = nv3->pfifo.cache1_entries[slot].subchannel; + uint32_t final = nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + + nv_log("Method=0x%08x, ", nv3->pfifo.cache1_entries[slot].method); + nv_log("Subchannel=0x%08x\n", nv3->pfifo.cache1_entries[slot].subchannel); + nv_log("Final=0x%08x\n", final); + return nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + } + } else { @@ -556,7 +585,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) } else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { - nv_log("PFIFO Cache0 Write"); + nv_log("PFIFO Cache0 Write\n"); // 3104 always written after 3100 if (address & 4) @@ -736,7 +765,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel) // NV_USER writes go here! // Pushes graphics objects into cache1 -void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) +void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) { bool oh_shit = false; // RAMRO needed nv3_ramin_ramro_reason oh_shit_reason = 0x00; // It's all good for now @@ -811,7 +840,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) uint32_t current_put_address = nv3->pfifo.cache1_settings.put_address >> 2; nv3->pfifo.cache1_entries[current_put_address].subchannel = subchannel; nv3->pfifo.cache1_entries[current_put_address].method = method_offset; - nv3->pfifo.cache1_entries[current_put_address].data = object_name; + nv3->pfifo.cache1_entries[current_put_address].data = param; // now we have to recalculate the cache1 put address uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address); @@ -825,7 +854,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name) nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; nv_log("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", - channel, subchannel, object_name, method_offset, nv3->pfifo.cache1_settings.put_address); + channel, subchannel, param, method_offset, nv3->pfifo.cache1_settings.put_address); // Now we're done. Phew! } diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index eddf61dea..993232c9d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -613,11 +613,6 @@ void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t switch (method) { - // This method is how we figure out which methods exist. - case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("I'm an Nvidia Object! channel=%d.%d class=0x%02x (%s) method=0x%04x parameter=0x%08x, context=0x%08x\n", - channel, subchannel, class_id, nv3_class_names[class_id], method, param, context); - break; default: // Object Method orchestration nv3_pgraph_arbitrate_method(param, method, channel, subchannel, class_id, context); diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index e46b46618..cce1d74a9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -32,7 +32,6 @@ It is used to get the offset within RAMHT of a graphics object. */ - uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) { // the official nvidia hash algorithm, tweaked for readability From fea06b6d9ae9605c38e15fd9d42bb54a16d496be Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 03:05:09 +0000 Subject: [PATCH 129/274] Don't flip x/y coordinates and w/h of rectangles. --- src/include/86box/nv/vid_nv3.h | 1 + src/video/nv/nv3/classes/nv3_class_007_rectangle.c | 10 ++++++---- src/video/nv/nv3/nv3_core.c | 8 +++++--- src/video/nv/nv3/render/nv3_render_core.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 1 - 5 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 16fcee485..e966f79b6 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1442,6 +1442,7 @@ extern nv3_t* nv3; void* nv3_init(const device_t *info); void nv3_close(void* priv); void nv3_speed_changed(void *priv); +void nv3_recalc_timings(svga_t* svga); void nv3_force_redraw(void* priv); // Memory Mapping diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index f0e85f4db..856c1c6cd 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -44,8 +44,9 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // If the size is submitted, render it. if (method_id & 0x04) { - nv3->pgraph.rectangle.size[index].w = (param >> 16) & 0xFFFF; - nv3->pgraph.rectangle.size[index].h = param & 0xFFFF; + nv3->pgraph.rectangle.size[index].w = param & 0xFFFF; + nv3->pgraph.rectangle.size[index].h = (param >> 16) & 0xFFFF; + nv_log("Rect%d Size=%d,%d\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h); @@ -53,8 +54,9 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } else // position { - nv3->pgraph.rectangle.position[index].x = (param >> 16) & 0xFFFF; - nv3->pgraph.rectangle.position[index].y = param & 0xFFFF; + nv3->pgraph.rectangle.position[index].x = param & 0xFFFF; + nv3->pgraph.rectangle.position[index].y = (param >> 16) & 0xFFFF; + nv_log("Rect%d Position=%d,%d\n", index, nv3->pgraph.rectangle.position[index].x, nv3->pgraph.rectangle.position[index].y); } diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index e7e71961d..3f9fb0274 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -488,22 +488,24 @@ void nv3_recalc_timings(svga_t* svga) // i don't we should force the top 2 bits to 1... // required for VESA resolutions, force parameters higher + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) svga->hdisp += 0x100; // large screen bit // Set the pixel mode switch (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03) { - ///0x0 is VGA textmode case NV3_CRTC_REGISTER_PIXELMODE_8BPP: svga->bpp = 8; svga->lowres = 0; + svga->map8 = svga->pallook; svga->render = svga_render_8bpp_highres; break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: @@ -703,14 +705,14 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) Additionally only do it if the value actually changed*/ if (old_value != val) { - // Thx to Fuel who basically wrote all the SVGA compatibility code already (although I fixed some issues), because VGA is boring + // Thx to Fuel who basically wrote most of the SVGA compatibility code already (although I fixed some issues), because VGA is boring // and in the words of an ex-Rendition/3dfx/NVIDIA engineer, "VGA was basically an undocumented bundle of steaming you-know-what. // And it was essential that any cores the PC 3D startups acquired had to work with all the undocumented modes and timing tweaks (mode X, etc.)" if (nv3->nvbase.svga.crtcreg < 0xE && nv3->nvbase.svga.crtcreg > 0x10) { nv3->nvbase.svga.fullchange = changeframecount; - svga_recalctimings(&nv3->nvbase.svga); + nv3_recalc_timings(&nv3->nvbase.svga); } } diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 4dff864e0..aebfb6466 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -172,7 +172,7 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr TODO: MOVE TO BPIXEL DEPTH or GROBJ0 to determine this, once we figure out how to get the bpixel depth. */ - + uint32_t src = 0, dst = 0; switch (framebuffer_bpp) diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 099248f66..b887b83f9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -384,5 +384,4 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) { nv_log(": Unknown register write (address=0x%08x)\n", address); } - } \ No newline at end of file From ceb4ff7a7301bfe67daf86e69901da64c5f218b9 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 12:02:49 +0000 Subject: [PATCH 130/274] Produce recognisable graphical output and, evne if they don't do anything yet, implement the beta factor/chroma key methods. --- .../86box/nv/classes/vid_nv3_classes.h | 2 + src/include/86box/nv/render/vid_nv3_render.h | 5 +- .../nv3/classes/nv3_class_001_beta_factor.c | 8 ++ .../nv/nv3/classes/nv3_class_003_chroma_key.c | 6 ++ src/video/nv/nv3/render/nv3_render_core.c | 75 ++++++++++++++++--- 5 files changed, 83 insertions(+), 13 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index c5c014245..96df80eb1 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -81,6 +81,8 @@ typedef enum nv3_pgraph_class_e #define NV3_BETA_FACTOR 0x0300 +#define NV3_CHROMA_KEY 0x0304 + #define NV3_CLIP_POSITION 0x0300 // S16:S16, 0=topleft #define NV3_CLIP_SIZE 0x0304 // U16:U16 diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 58ecf9df5..50e41c17e 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -19,6 +19,9 @@ /* Core */ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); +uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); +nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color); /* Primitives */ -void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); \ No newline at end of file +void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); +void nv3_render_chroma_test(nv3_grobj_t grobj); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 784da2eb0..f56a328dd 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -32,6 +32,14 @@ void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { switch (method_id) { + /* even if we don't do anything with this yet... */ + case NV3_BETA_FACTOR: + if (param & 0x80000000) /* bit0 */ + nv3->pgraph.beta_factor = 0; + else + nv3->pgraph.beta_factor = param & 0x7F800000; + + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 92a3cb225..a1364bd98 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -32,6 +32,12 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { switch (method_id) { + case NV3_CHROMA_KEY: + nv3_color_expanded_t expanded_color = nv3_render_expand_color(grobj, param); + + uint32_t color = nv3_render_to_chroma(expanded_color); + nv3->pgraph.chroma_key = *(nv3_color_x2a10g10b10_t*)&color; + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index aebfb6466..8d7bdd189 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -29,12 +29,6 @@ #include <86box/nv/vid_nv3.h> #include <86box/utils/video_stdlib.h> -/* Render Core: Performs a ROP */ -uint32_t nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, nv3_render_operation_type rop) -{ - return video_rop_gdi_ternary(rop, dst, pattern, src); -} - /* Expand a colour. NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! */ @@ -108,6 +102,8 @@ nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) color_final.r = color_final.g = color_final.b = (color & 0xFFFF) * 4; // convert to rgb10 break; default: + warning("nv3_render_expand_color unknown format %d", format); + break; } @@ -117,6 +113,39 @@ nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) return color_final; } +/* Used for chroma test */ +uint32_t nv3_render_downconvert(nv3_grobj_t grobj, nv3_color_expanded_t color) +{ + uint8_t format = (grobj.grobj_0 & 0x07); + bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + + #ifdef ENABLE_NV_LOG + nv_log("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d", color, format, alpha_enabled); + #endif + + uint32_t packed_color = 0x00; + + switch (format) + { + case nv3_pgraph_pixel_format_r5g5b5: + break; + case nv3_pgraph_pixel_format_r8g8b8: + break; + case nv3_pgraph_pixel_format_r10g10b10: + break; + case nv3_pgraph_pixel_format_y8: + break; + case nv3_pgraph_pixel_format_y16: + break; + default: + warning("nv3_render_downconvert_color unknown format %d", format); + break; + + } + + return packed_color; +} + /* Convert expanded colour format to chroma key format */ uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) { @@ -162,7 +191,23 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr /* TODO: Chroma Key, Pattern, Plane Mask...*/ /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from. */ - uint32_t pixel_addr_vram = position.x + (nv3->pgraph.bpitch[current_buffer]) * position.y + nv3->pgraph.boffset[current_buffer]; + + uint32_t vram_x = position.x; + + // we have to multiply the x position by the number of bytes per pixel + switch (framebuffer_bpp) + { + case 8: + break; + case 16: + vram_x = position.x * 2; + break; + case 32: + vram_x = position.x * 4; + break; + } + + uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * position.y) + nv3->pgraph.boffset[current_buffer]; pixel_addr_vram &= nv3->nvbase.svga.vram_mask; @@ -180,7 +225,9 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr case 8: src = color & 0xFF; dst = nv3->nvbase.svga.vram[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + nv3->nvbase.svga.vram[pixel_addr_vram] = (int8_t)video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + + nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; break; case 16: @@ -189,7 +236,9 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr src = color & 0xFFFF; dst = vram_16[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + vram_16[pixel_addr_vram] = (int16_t)video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + + nv3->nvbase.svga.changedvram[pixel_addr_vram >> 11] = changeframecount; break; case 32: @@ -198,11 +247,13 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr src = color; dst = vram_32[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + vram_32[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + + nv3->nvbase.svga.changedvram[pixel_addr_vram >> 10] = changeframecount; break; } - nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; -} \ No newline at end of file +} + From 97a06fa007608aa55881f26d5eb623ba34a9c1a3 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 13:25:33 +0000 Subject: [PATCH 131/274] Implement RAMRO, and also fix runout_put and runout_get so that it can actually runout without freezing (I don't think it should be even if it's only running out on a few objects, but it should be able to runout anyway.) --- .../nv/nv3/classes/nv3_class_007_rectangle.c | 2 +- src/video/nv/nv3/render/nv3_render_core.c | 14 ++++++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 35 ++++++++++++++++--- 3 files changed, 44 insertions(+), 7 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 856c1c6cd..a92a1f761 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -48,7 +48,7 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.rectangle.size[index].h = (param >> 16) & 0xFFFF; - nv_log("Rect%d Size=%d,%d\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h); + nv_log("Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h, nv3->pgraph.rectangle.color); nv3_render_rect(nv3->pgraph.rectangle.position[index], nv3->pgraph.rectangle.size[index], nv3->pgraph.rectangle.color, grobj); } diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 8d7bdd189..7b9b3e303 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -128,6 +128,10 @@ uint32_t nv3_render_downconvert(nv3_grobj_t grobj, nv3_color_expanded_t color) switch (format) { case nv3_pgraph_pixel_format_r5g5b5: + packed_color = (color.r / 0x20) << 10 | + (color.g / 0x20) << 5 | + (color.b / 0x20); + break; case nv3_pgraph_pixel_format_r8g8b8: break; @@ -146,6 +150,12 @@ uint32_t nv3_render_downconvert(nv3_grobj_t grobj, nv3_color_expanded_t color) return packed_color; } +/* Runs the chroma key test */ +void nv3_render_chroma_test(nv3_grobj_t grobj) +{ + +} + /* Convert expanded colour format to chroma key format */ uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) { @@ -200,10 +210,10 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr case 8: break; case 16: - vram_x = position.x * 2; + vram_x = position.x << 1; break; case 32: - vram_x = position.x * 4; + vram_x = position.x << 2; break; } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 81b13e5bf..bac84ede9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -556,20 +556,22 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.cache1_settings.get_address = val; break; case NV3_PFIFO_RUNOUT_GET: + uint32_t size_get = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (size_get == 0) //512b - nv3->pfifo.runout_get = ((val & 0x3F) << 3); + nv3->pfifo.runout_get = val & (NV3_RAMIN_RAMRO_SIZE_0 - 0x07); else - nv3->pfifo.runout_get = ((val & 0x3FF) << 3); + nv3->pfifo.runout_get = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); break; case NV3_PFIFO_RUNOUT_PUT: uint32_t size_put = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (size_put == 0) //512b - nv3->pfifo.runout_put = ((val & 0x3F) << 3); + nv3->pfifo.runout_put = val & (NV3_RAMIN_RAMRO_SIZE_0 - 0x07); else - nv3->pfifo.runout_put = ((val & 0x3FF) << 3); + nv3->pfifo.runout_put = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); + break; /* Cache1 is handled below */ case NV3_PFIFO_CACHE0_CTX: @@ -833,6 +835,31 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) if (oh_shit) { nv_log("WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset); + + nv3_ramro_write(nv3->pfifo.runout_put, new_address); + nv3_ramro_write(nv3->pfifo.runout_put + 4, param); + + nv3->pfifo.runout_put += 0x08; + + uint32_t ramro_size = (nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01; + + /* Make sure it's valid */ + switch (ramro_size) + { + case 0: + nv3->pfifo.runout_put &= (NV3_RAMIN_RAMRO_SIZE_0 - 0x07); + break; + case 1: + nv3->pfifo.runout_put &= (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); + break; + } + + /* Fire the interrupt. Also the very bad interrupt...*/ + if (nv3->pfifo.runout_get == nv3->pfifo.runout_put) + nv3_pfifo_interrupt(NV3_PFIFO_INTR_RUNOUT_OVERFLOW, true); + else + nv3_pfifo_interrupt(NV3_PFIFO_INTR_RUNOUT, true); + return; } From 4e4ed738b202a194d6e92c4fe420357b00ba2a07 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 13:50:56 +0000 Subject: [PATCH 132/274] Fix fifo free spaces check, which was so assbackwards I have no idea how anything worked up to now. It was causing spurious runouts --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 32 ++++++++++--------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index bac84ede9..d8b7cef96 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -303,15 +303,11 @@ uint32_t nv3_pfifo_read(uint32_t address) } else { - uint32_t method = nv3->pfifo.cache0_entry.method; - uint32_t subchannel = nv3->pfifo.cache0_entry.subchannel; uint32_t final = nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); - nv_log("Method=0x%08x, ", nv3->pfifo.cache0_entry.method); - nv_log("Subchannel=0x%08x\n", nv3->pfifo.cache0_entry.subchannel); - nv_log("Final=0x%08x\n", final); + nv_log("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); - return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + return final; } } else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) @@ -335,15 +331,9 @@ uint32_t nv3_pfifo_read(uint32_t address) } else { - uint32_t method = nv3->pfifo.cache1_entries[slot].method; - uint32_t subchannel = nv3->pfifo.cache1_entries[slot].subchannel; uint32_t final = nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); - - nv_log("Method=0x%08x, ", nv3->pfifo.cache1_entries[slot].method); - nv_log("Subchannel=0x%08x\n", nv3->pfifo.cache1_entries[slot].subchannel); - nv_log("Final=0x%08x\n", final); - - return nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); + nv_log("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); + return final; } } @@ -835,7 +825,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) if (oh_shit) { nv_log("WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset); - + nv3_ramro_write(nv3->pfifo.runout_put, new_address); nv3_ramro_write(nv3->pfifo.runout_put + 4, param); @@ -854,7 +844,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) break; } - /* Fire the interrupt. Also the very bad interrupt...*/ + //Fire the interrupt. Also the very bad interrupt... if (nv3->pfifo.runout_get == nv3->pfifo.runout_put) nv3_pfifo_interrupt(NV3_PFIFO_INTR_RUNOUT_OVERFLOW, true); else @@ -953,9 +943,13 @@ void nv3_pfifo_cache1_pull() // THIS IS PER SUBCHANNEL! uint32_t nv3_pfifo_cache1_num_free_spaces() { - // convert to gray code - uint32_t real_get_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.get_address); - uint32_t real_put_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.put_address); + // get the index + + uint32_t get_index = nv3->pfifo.cache1_settings.get_address >> 2; + uint32_t put_index = nv3->pfifo.cache1_settings.put_address >> 2; + + uint32_t real_get_address = nv3_pfifo_cache1_gray2normal(get_index) << 2; + uint32_t real_put_address = nv3_pfifo_cache1_gray2normal(put_index) << 2; // There is no hope of being able to understand it. Nobody can understand return (real_get_address - real_put_address - 4) & 0x7C; // there are 64 entries what From 8d4096fffc34e971f249b38011cd4ef6b14ce6c5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 22 Mar 2025 15:37:14 +0000 Subject: [PATCH 133/274] Fix the colours. Wtf is wrong with NVidia? --- src/include/86box/nv/render/vid_nv3_render.h | 1 + src/include/86box/nv/vid_nv3.h | 1 + src/video/nv/nv3/nv3_core.c | 22 ++++++++++++++----- src/video/nv/nv3/render/nv3_render_core.c | 21 +++++++++++++----- src/video/nv/nv3/subsystems/nv3_pramdac.c | 1 + .../nv/nv3/subsystems/nv3_pramin_ramro.c | 4 ++-- 6 files changed, 37 insertions(+), 13 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 50e41c17e..8481213ac 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -24,4 +24,5 @@ nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color); /* Primitives */ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); + void nv3_render_chroma_test(nv3_grobj_t grobj); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index e966f79b6..640a0c951 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -699,6 +699,7 @@ extern const device_config_t nv3_config[]; #define NV3_PRAMDAC_COEFF_SELECT 0x68050C #define NV3_PRAMDAC_GENERAL_CONTROL 0x680600 +#define NV3_PRAMDAC_GENERAL_CONTROL_565_MODE 12 // These are all 10-bit values, but aligned to 32bits // so treating them as 32bit should be fine diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 3f9fb0274..b1d96f8d9 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -481,8 +481,10 @@ void nv3_recalc_timings(svga_t* svga) nv3_t* nv3 = (nv3_t*)svga->priv; + svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; + + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; // should these actually use separate values? // i don't we should force the top 2 bits to 1... @@ -495,7 +497,6 @@ void nv3_recalc_timings(svga_t* svga) if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) svga->hdisp += 0x100; // large screen bit @@ -509,9 +510,20 @@ void nv3_recalc_timings(svga_t* svga) svga->render = svga_render_8bpp_highres; break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: - svga->bpp = 16; - svga->lowres = 0; - svga->render = svga_render_16bpp_highres; + /* sometimes it really renders in 15bpp, so you need to do this */ + if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) + { + svga->bpp = 16; + svga->lowres = 0; + svga->render = svga_render_16bpp_highres; + } + else + { + svga->bpp = 16; // HACK: DO NOT change this + svga->lowres = 0; + svga->render = svga_render_15bpp_highres; + } + break; case NV3_CRTC_REGISTER_PIXELMODE_32BPP: svga->bpp = 32; diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 7b9b3e303..8ccca2e6f 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -23,6 +23,7 @@ #include <86box/device.h> #include <86box/mem.h> #include <86box/pci.h> +#include <86box/plat.h> #include <86box/rom.h> #include <86box/video.h> #include <86box/nv/vid_nv.h> @@ -175,6 +176,8 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr #ifdef DEBUG uint8_t color_format_object = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_COLOR_FORMAT) & 0x07; #endif + bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too? uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; @@ -235,7 +238,7 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr case 8: src = color & 0xFF; dst = nv3->nvbase.svga.vram[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = (int8_t)video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00) & 0xFF; nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; @@ -244,9 +247,18 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 1; - src = color & 0xFFFF; + // mask off the alpha bit. Even though the drivers should send this. What! + if (!alpha_enabled) + src = ((color & (~0x8000)) & 0xFFFF); + else + src = color & 0xFFFF; + + // convert to 16bpp + // forcing it to render in 15bpp fixes it, + + dst = vram_16[pixel_addr_vram]; - vram_16[pixel_addr_vram] = (int16_t)video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + vram_16[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00) & 0xFFFF; nv3->nvbase.svga.changedvram[pixel_addr_vram >> 11] = changeframecount; @@ -263,7 +275,4 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr break; } - - } - diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index b887b83f9..c640d5f10 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -328,6 +328,7 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) break; case NV3_PRAMDAC_GENERAL_CONTROL: nv3->pramdac.general_control = value; + nv3_recalc_timings(&nv3->nvbase.svga); break; case NV3_PRAMDAC_VSERR_WIDTH: //vslines? diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index d421b28dd..1209faa2f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -30,12 +30,12 @@ uint32_t nv3_ramro_read(uint32_t address) { - nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", address); + nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), Probably shouldn't happenn\n", address); } void nv3_ramro_write(uint32_t address, uint32_t value) { - nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", value, address); + nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), Probably shouldn't happenn", value, address); } void nv3_ramro_send() From 493020ca51a3012bd5d183febb279384a797c011 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 23 Mar 2025 01:24:42 +0000 Subject: [PATCH 134/274] NV_IMAGE_FROM_CPU implemented, leading to the mouse cursor being drawn, and the windows start menu --- doc/nvidia_notes/status.xlsx | Bin 0 -> 15227 bytes .../86box/nv/classes/vid_nv3_classes.h | 10 +- src/include/86box/nv/vid_nv3.h | 3 +- .../nv/nv3/classes/nv3_class_007_rectangle.c | 2 +- .../nv/nv3/classes/nv3_class_011_image.c | 99 +++++++++++++++++- 5 files changed, 109 insertions(+), 5 deletions(-) create mode 100644 doc/nvidia_notes/status.xlsx diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..a301eba64e4f3c03a76698c87a828d2365c86b89 GIT binary patch literal 15227 zcmeHuRa6~Y*7d=HyIXJzc97r_+}+*X9fG^N6Fj)POK=Mw+(`)T5FGxK-0pF2r*A+0 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zf%>;7zbtmYqx^0l`V(aql;i)+z5KEh{f_dxt>8}-2;9F#`DHTr9p(2C)IU*l3H}!4 z*LdphD8CQ){E2b{8j|~)fAnkc=XaFf>;8YDu#)~l`F#}NcYxn37k>iO)BFPXvySn5 z=ot|C-SJ84m#9G6Mkrmfrjx{;zWM*YFJ1zl8rooaCjTK-~E` Q{|Fhd4x(Qu`_H}q2j$D`YybcN literal 0 HcmV?d00001 diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 96df80eb1..80e2c1437 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -92,7 +92,15 @@ typedef enum nv3_pgraph_class_e #define NV3_RECTANGLE_START 0x0400 #define NV3_RECTANGLE_MAX 16 -#define NV3_RECTNAGLE_END 0x0480 +#define NV3_RECTANGLE_END 0x0480 + +// image_from_cpu +#define NV3_IMAGE_START_POSITION 0x0304 // starting position of image from cpu +#define NV3_IMAGE_SIZE 0x0308 +#define NV3_IMAGE_SIZE_IN 0x030C +#define NV3_IMAGE_COLOR_START 0x0400 +#define NV3_IMAGE_COLOR_MAX 32 +#define NV3_IMAGE_COLOR_END 0x0480 #define NV3_IMAGE_IN_MEMORY_COLOR_FORMAT 0x0300 #define NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE 0x0304 diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 640a0c951..29b2f70b9 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 20 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 22 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -1227,6 +1227,7 @@ typedef struct nv3_pgraph_s struct nv3_object_class_00E scaled_image_from_memory; struct nv3_object_class_010 blit; struct nv3_object_class_011 image; + nv3_position_16_t image_current_position; /* This is here so we can hold the current state of the image */ struct nv3_object_class_012 bitmap; struct nv3_object_class_014 transfer2memory; struct nv3_object_class_015 stretched_image_from_cpu; diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index a92a1f761..8f304fdac 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -37,7 +37,7 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: /* Check for any rectangle point or size method. */ - if (method_id >= NV3_RECTANGLE_START && method_id <= NV3_RECTNAGLE_END) + if (method_id >= NV3_RECTANGLE_START && method_id <= NV3_RECTANGLE_END) { uint32_t index = (method_id - NV3_RECTANGLE_START) / 8; diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index b40b9025c..9b4446cff 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -28,13 +28,108 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> +/* Check the line bounds */ +void nv3_class_011_check_line_bounds() +{ + uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x; + //uint32_t relative_y = nv3->pgraph.image_current_position.y - nv3->pgraph.image.point.y; + + /* In theory, relative_y should never be exceeded...because it only submits enough pixels to render the image*/ + if (relative_x >= nv3->pgraph.image.size_in.w) + { + nv3->pgraph.image_current_position.y++; + nv3->pgraph.image_current_position.x = nv3->pgraph.image.point.x; + } +} + void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) { + case NV3_IMAGE_START_POSITION: + nv3->pgraph.image.point.x = (param & 0xFFFF); + nv3->pgraph.image.point.y = (param >> 16); + nv_log("Image Point=%d,%d", nv3->pgraph.image.point.x, nv3->pgraph.image.point.y); + break; + /* Seems to allow scaling of the bitblt. */ + case NV3_IMAGE_SIZE: + nv3->pgraph.image.size.w = (param & 0xFFFF); + nv3->pgraph.image.size.h = (param >> 16); + break; + case NV3_IMAGE_SIZE_IN: + nv3->pgraph.image.size_in.w = (param & 0xFFFF); + nv3->pgraph.image.size_in.h = (param >> 16); + nv3->pgraph.image_current_position = nv3->pgraph.image.point; + break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + if (method_id >= NV3_IMAGE_COLOR_START && method_id <= NV3_IMAGE_COLOR_END) + { + // shift left by 2 because it's 4 bits per si\e.. + uint32_t pixel_slot = (method_id - NV3_IMAGE_COLOR_START) >> 2; + uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + + /* todo: a lot of stuff */ + + uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; + + /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ + /* the reverse order is due to the endianness */ + switch (nv3->nvbase.svga.bpp) + { + // 4pixels packed into one + case 8: + + //pixel3 + pixel3 = param & 0xFF; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel3, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel2 = (param >> 8) & 0xFF; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel2, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel1 = (param >> 16) & 0xFF; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel0 = (param >> 24) & 0xFF; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + break; + //2pixels packed into 1 + case 16: + pixel1 = (param) & 0xFFFF; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel0 = (param >> 16) & 0xFFFF; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + break; + // just one + case 32: + pixel0 = param; + nv3_render_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + break; + } + } + else + { + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + + } return; } } \ No newline at end of file From 160e8a8071c7ba3de0843d887378080aed28fba0 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 23 Mar 2025 17:06:53 +0000 Subject: [PATCH 135/274] Clean up stupid colour structs and implement patterns (class 0x06). Now, you can select taskbar items and some lines draw. Replace some multiplications with shifts. --- doc/nvidia_notes/status.xlsx | Bin 15227 -> 15356 bytes .../86box/nv/classes/vid_nv3_classes.h | 61 +++---- src/include/86box/nv/render/vid_nv3_render.h | 6 +- src/include/86box/nv/vid_nv3.h | 21 ++- src/video/CMakeLists.txt | 3 +- .../nv3/classes/nv3_class_001_beta_factor.c | 2 +- src/video/nv/nv3/classes/nv3_class_002_rop.c | 2 +- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 7 +- .../nv/nv3/classes/nv3_class_006_pattern.c | 41 ++++- .../classes/nv3_class_01c_image_in_memory.c | 2 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 2 +- src/video/nv/nv3/render/nv3_render_core.c | 154 ++++++++++++++---- src/video/nv/nv3/subsystems/nv3_pgraph.c | 50 +++--- 13 files changed, 227 insertions(+), 124 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index a301eba64e4f3c03a76698c87a828d2365c86b89..4118b2c5609b86ddcf989d9b715effdc97ee38e4 100644 GIT binary patch delta 6313 zcmZ8_1ymecuk%kU@ew$q;04cMB3EXn-L&gn{7h&OmT? zx5v$Y|KGoEuU_4IRqb=SS9hJN+ULgo)}vw>19&@OCutPFjzIY#MSYFDy4DTyASEGz|03rGk5O=XWrc^ws&gaj!p*|I zNK@(X_xWIqz1r7s|088H=&!zvP4Yc2C=eCxUHE5O4c$(%wY!VenyunonkL^iLK>Z zy9UrfWO#>l7;QD9wKu50l!W@)ku#IHp@G=6x$nlm%xY(LC6jY7=xHsTFFq}84s^g0 ze~v)AU`CAgsPXmXzcVWv0?dlVygouom2Wg-Bkp-IsHLFCM)I}&tB2hRuwOl_qGmxq zOsTHTd7tM^Kp0_5cTD<@tFXQB6TXtoJBbEjNE(}Zx{_9n7G6FHaI9Kxm%Ay9@)Hm3 z9Fx5su*4I8Y1o}J%DE*;TVg7&?35C#J~+4+s~roo6F-o%)Q0-$%a20_FD32mw9Qc)i^OTT=atcy8^w3r1by-;VRu!at2hTe zL^m2qTJhSOg4JrK&l2Am1Qr{Y?!Ww5ez0<%3Oe<}@-x$E zP6k08PFr2TKF^0{L~*K8NrX_+%)5qiTjk+6A}^r71v}u}UthLmEk)q07{+KPbEXOm zhwe$GsV23=e){z%r_Q2-Ez;`r*s1?=f8@s<@3V9&kD*PKW}Dwl`Zv@OBxcFeQNf6! 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What + if (param > NV3_PATTERN_SHAPE_LAST_VALID) + { + warning("NV3 class 0x06 (Pattern) invalid shape %d (This is a bug)", param); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_DATA); + return; + } + + */ + nv3->pgraph.pattern_shape = param & 0x03; + + break; + case NV3_PATTERN_COLOR0: + nv3_color_expanded_t expanded_colour0 = nv3_render_expand_color(grobj, param); + nv3_render_set_pattern_color(expanded_colour0, false); + break; + case NV3_PATTERN_COLOR1: + nv3_color_expanded_t expanded_colour1 = nv3_render_expand_color(grobj, param); + nv3_render_set_pattern_color(expanded_colour1, true); + break; + case NV3_PATTERN_BITMAP_HIGH: + nv3->pgraph.pattern_bitmap = 0; //reset + nv3->pgraph.pattern_bitmap |= ((uint64_t)param << 32); + break; + case NV3_PATTERN_BITMAP_LOW: + nv3->pgraph.pattern_bitmap |= param; + + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; + break; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 9ba86c0eb..a6cb52fbf 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -85,6 +85,6 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; + break; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 0bb12a2eb..9985845cf 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -35,7 +35,7 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t { /* mthdCreate in software(?)*/ case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("mthdCreate\n"); + nv_log("mthdCreate obj_name=0x%08x\n", param); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; // set up the current notification request/object diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 8ccca2e6f..741f8e422 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -57,14 +57,12 @@ nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) // 555 case nv3_pgraph_pixel_format_r5g5b5: - nv3_color_16_a1r5g5b5_t new_color = *(nv3_color_16_a1r5g5b5_t*)&color; // "stretch out" the colour - color_final.r = new_color.r * 0x20; - color_final.g = new_color.g * 0x20; - color_final.b = new_color.b * 0x20; - if (alpha_enabled) - color_final.a = new_color.a; + color_final.a = (color >> 15) & 0x01; // will be ignored if alpha_enabled isn't used + color_final.r = ((color >> 10) & 0x1F) << 5; + color_final.g = ((color >> 5) & 0x1F) << 5; + color_final.b = (color & 0x1F) << 5; break; // 888 (standard colour + 8-bit alpha) @@ -76,18 +74,12 @@ nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) color_final.g = ((color >> 8) & 0xFF) * 4; color_final.b = (color & 0xFF) * 4; - if (alpha_enabled) - color_final.a = new_color.a; break; case nv3_pgraph_pixel_format_r10g10b10: - nv3_color_x2a10g10b10_t new_color_rgb10 = *(nv3_color_x2a10g10b10_t*)&color; - - color_final.r = new_color_rgb10.r; - color_final.g = new_color_rgb10.g; - color_final.b = new_color_rgb10.b; - - if (alpha_enabled) - color_final.a = new_color.a; + color_final.a = (color << 31) & 0x01; + color_final.r = (color << 30) & 0x3FF; + color_final.g = (color << 20) & 0x1FF; + color_final.b = (color << 10); break; case nv3_pgraph_pixel_format_y8: @@ -115,7 +107,7 @@ nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) } /* Used for chroma test */ -uint32_t nv3_render_downconvert(nv3_grobj_t grobj, nv3_color_expanded_t color) +uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color) { uint8_t format = (grobj.grobj_0 & 0x07); bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; @@ -129,18 +121,30 @@ uint32_t nv3_render_downconvert(nv3_grobj_t grobj, nv3_color_expanded_t color) switch (format) { case nv3_pgraph_pixel_format_r5g5b5: - packed_color = (color.r / 0x20) << 10 | - (color.g / 0x20) << 5 | - (color.b / 0x20); + packed_color = (color.r >> 5) << 10 | + (color.g >> 5) << 5 | + (color.b >> 5); break; case nv3_pgraph_pixel_format_r8g8b8: + packed_color = (color.a) << 24 | // is this a thing? + (color.r >> 2) << 16 | + (color.g >> 2) << 8 | + color.b; break; case nv3_pgraph_pixel_format_r10g10b10: + /* sometimes alpha isn't used but we should incorporate it anyway */ + if (color.a > 0x00) packed_color | (1 << 31); + + packed_color |= (color.r << 30); + packed_color |= (color.g << 20); + packed_color |= (color.b << 10); break; case nv3_pgraph_pixel_format_y8: + nv_log("nv3_render_downconvert: Y8 not implemented"); break; case nv3_pgraph_pixel_format_y16: + nv_log("nv3_render_downconvert: Y16 not implemented"); break; default: warning("nv3_render_downconvert_color unknown format %d", format); @@ -164,6 +168,37 @@ uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) return !!expanded.a | (expanded.r << 30) | (expanded.b << 20) | (expanded.a << 10); } +/* Convert a rgb10 colour to a pattern colour */ +uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1) +{ + /* reset the colour */ + if (!use_color1) + nv3->pgraph.pattern_color_0_rgb.r = nv3->pgraph.pattern_color_0_rgb.g = nv3->pgraph.pattern_color_0_rgb.b = 0x00; + else + nv3->pgraph.pattern_color_1_rgb.r = nv3->pgraph.pattern_color_1_rgb.g = nv3->pgraph.pattern_color_1_rgb.b = 0x00; + + /* select the right pattern colour, _rgb is already in RGB10 format, so we don't need to do any conversion */ + + if (!use_color1) + { + nv3->pgraph.pattern_color_0_alpha = (pattern_colour.a) & 0xFF; + nv3->pgraph.pattern_color_0_rgb.r = pattern_colour.r; + nv3->pgraph.pattern_color_0_rgb.g = pattern_colour.g; + nv3->pgraph.pattern_color_0_rgb.b = pattern_colour.b; + + } + else + { + nv3->pgraph.pattern_color_1_alpha = (pattern_colour.a) & 0xFF; + nv3->pgraph.pattern_color_1_rgb.r = pattern_colour.r; + nv3->pgraph.pattern_color_1_rgb.g = pattern_colour.g; + nv3->pgraph.pattern_color_1_rgb.b = pattern_colour.b; + } + + + +} + /* Plots a pixel. */ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj) { @@ -224,6 +259,46 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr pixel_addr_vram &= nv3->nvbase.svga.vram_mask; + uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0; + uint8_t bit = 0x00; + + /* Get our pattern data, may move to another function */ + switch (nv3->pgraph.pattern.shape) + { + + /* This logic is from NV1 envytoos docs, but seems to be same on NV3*/ + case NV3_PATTERN_SHAPE_8X8: + bit = (position.x & 7) | (position.y & 7) << 3; + break; + case NV3_PATTERN_SHAPE_1X64: + bit = (position.x & 0x3f); + break; + case NV3_PATTERN_SHAPE_64X1: + bit = (position.y & 0x3f); + break; + } + + // pull out the actual bit and see which colour we need to use + + bool use_color1 = (nv3->pgraph.pattern_bitmap >> bit) & 0x01; + + if (!use_color1) + { + if (!nv3->pgraph.pattern_color_0_alpha) + return; + + /* This is stupid */ + rop_pattern = nv3_render_downconvert_color(grobj, nv3->pgraph.pattern_color_0_rgb); + } + else + { + if (!nv3->pgraph.pattern_color_1_alpha) + return; + + rop_pattern = nv3_render_downconvert_color(grobj, nv3->pgraph.pattern_color_1_rgb); + } + + /* Go to vram and do the final ROP for a basic bitblit. It seems we can skip the downconversion step *for now*, since (framebuffer bits per pixel) == (object bits per pixel) I'm not sure how games will react. But it depends on how the D3D drivers operate, we may need ro convert texture formats to the current bpp internally. @@ -231,14 +306,12 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr TODO: MOVE TO BPIXEL DEPTH or GROBJ0 to determine this, once we figure out how to get the bpixel depth. */ - uint32_t src = 0, dst = 0; - switch (framebuffer_bpp) { case 8: - src = color & 0xFF; - dst = nv3->nvbase.svga.vram[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00) & 0xFF; + rop_src = color & 0xFF; + rop_dst = nv3->nvbase.svga.vram[pixel_addr_vram]; + nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern) & 0xFF; nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; @@ -246,19 +319,28 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr case 16: uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 1; + + // mask to 16bit - // mask off the alpha bit. Even though the drivers should send this. What! - if (!alpha_enabled) - src = ((color & (~0x8000)) & 0xFFFF); - else - src = color & 0xFFFF; + rop_src = color & 0xFFFF; + + /* if alpha is turned on and we aren't in 565 mode, reject transparent pixels */ + bool is_16bpp = (nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01; + + // a1r5g5b5 + if (!is_16bpp) + { + if (alpha_enabled && + !(color & 0x8000)) + return; + } // convert to 16bpp // forcing it to render in 15bpp fixes it, - - dst = vram_16[pixel_addr_vram]; - vram_16[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00) & 0xFFFF; + rop_dst = vram_16[pixel_addr_vram]; + + vram_16[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern) & 0xFFFF; nv3->nvbase.svga.changedvram[pixel_addr_vram >> 11] = changeframecount; @@ -267,9 +349,9 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 2; - src = color; - dst = vram_32[pixel_addr_vram]; - vram_32[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, src, dst, 0x00); + rop_src = color; + rop_dst = vram_32[pixel_addr_vram]; + vram_32[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern); nv3->nvbase.svga.changedvram[pixel_addr_vram >> 10] = changeframecount; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 993232c9d..70aef4270 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -63,10 +63,10 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_SRC_CANVAS_MAX, "PGRAPH Source Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, { NV3_PGRAPH_DST_CANVAS_MIN, "PGRAPH Destination Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, { NV3_PGRAPH_DST_CANVAS_MAX, "PGRAPH Destination Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_PATTERN_COLOR_0_0, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_COLOR_0_1, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_COLOR_1_0, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_COLOR_1_1, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, }, + { NV3_PGRAPH_pattern_color_0_rgb, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, + { NV3_PGRAPH_pattern_color_0_alpha, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, }, + { NV3_PGRAPH_pattern_color_1_rgb, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, + { NV3_PGRAPH_pattern_color_1_alpha, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, }, { NV3_PGRAPH_PATTERN_BITMAP_HIGH, "PGRAPH Pattern Bitmap (High 32bits)", NULL, NULL}, { NV3_PGRAPH_PATTERN_BITMAP_LOW, "PGRAPH Pattern Bitmap (Low 32bits)", NULL, NULL}, { NV3_PGRAPH_PATTERN_SHAPE, "PGRAPH Pattern Shape (1:0 - 0=8x8, 1=64x1, 2=1x64)", NULL, NULL}, @@ -185,23 +185,23 @@ uint32_t nv3_pgraph_read(uint32_t address) ret = *(uint32_t*)&nv3->pgraph.src_canvas_max; break; // Pattern - case NV3_PGRAPH_PATTERN_COLOR_0_0: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_0; + case NV3_PGRAPH_pattern_color_0_rgb: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_rgb; break; - case NV3_PGRAPH_PATTERN_COLOR_0_1: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_1; + case NV3_PGRAPH_pattern_color_0_alpha: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_alpha; break; - case NV3_PGRAPH_PATTERN_COLOR_1_0: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_0; + case NV3_PGRAPH_pattern_color_1_rgb: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_rgb; break; - case NV3_PGRAPH_PATTERN_COLOR_1_1: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_1; + case NV3_PGRAPH_pattern_color_1_alpha: + ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_alpha; break; case NV3_PGRAPH_PATTERN_BITMAP_HIGH: - ret = nv3->pgraph.pattern_bitmap_high; + ret = (nv3->pgraph.pattern_bitmap >> 32) & 0xFFFFFFFF; break; case NV3_PGRAPH_PATTERN_BITMAP_LOW: - ret = nv3->pgraph.pattern_bitmap_low; + ret = (nv3->pgraph.pattern_bitmap & 0xFFFFFFFF); break; // Beta factor case NV3_PGRAPH_BETA: @@ -388,23 +388,23 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) *(uint32_t*)&nv3->pgraph.src_canvas_max = value; break; // Pattern - case NV3_PGRAPH_PATTERN_COLOR_0_0: - *(uint32_t*)&nv3->pgraph.pattern_color_0_0 = value; + case NV3_PGRAPH_pattern_color_0_rgb: + *(uint32_t*)&nv3->pgraph.pattern_color_0_rgb = value; break; - case NV3_PGRAPH_PATTERN_COLOR_0_1: - *(uint32_t*)&nv3->pgraph.pattern_color_0_1 = value; + case NV3_PGRAPH_pattern_color_0_alpha: + *(uint32_t*)&nv3->pgraph.pattern_color_0_alpha = value; break; - case NV3_PGRAPH_PATTERN_COLOR_1_0: - *(uint32_t*)&nv3->pgraph.pattern_color_1_0 = value; + case NV3_PGRAPH_pattern_color_1_rgb: + *(uint32_t*)&nv3->pgraph.pattern_color_1_rgb = value; break; - case NV3_PGRAPH_PATTERN_COLOR_1_1: - *(uint32_t*)&nv3->pgraph.pattern_color_1_1 = value; + case NV3_PGRAPH_pattern_color_1_alpha: + *(uint32_t*)&nv3->pgraph.pattern_color_1_alpha = value; break; case NV3_PGRAPH_PATTERN_BITMAP_HIGH: - nv3->pgraph.pattern_bitmap_high = value; + nv3->pgraph.pattern_bitmap |= ((uint64_t)value << 32); break; case NV3_PGRAPH_PATTERN_BITMAP_LOW: - nv3->pgraph.pattern_bitmap_low = value; + nv3->pgraph.pattern_bitmap |= value; break; // Beta factor case NV3_PGRAPH_BETA: @@ -415,7 +415,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) nv3->pgraph.rop = value & 0xFF; break; case NV3_PGRAPH_CHROMA_KEY: - nv3->pgraph.chroma_key = *(nv3_color_x2a10g10b10_t*)value; + nv3->pgraph.chroma_key = value; break; case NV3_PGRAPH_PLANE_MASK: nv3->pgraph.plane_mask = value; From 0b0e6c5256504e72378b319b42e2ca45b5b5107e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 23 Mar 2025 19:12:02 +0000 Subject: [PATCH 136/274] More refactoring + implement screen2screen blits --- .../86box/nv/classes/vid_nv3_classes.h | 5 + src/include/86box/nv/render/vid_nv3_render.h | 14 ++- src/include/86box/nv/vid_nv3.h | 10 +- src/video/CMakeLists.txt | 4 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 16 ++++ .../nv/nv3/classes/nv3_class_011_image.c | 14 +-- src/video/nv/nv3/render/nv3_render_blit.c | 92 +++++++++++++++++++ src/video/nv/nv3/render/nv3_render_core.c | 87 +++++++++++++----- .../nv/nv3/render/nv3_render_primitives.c | 2 +- src/video/nv/nv3/subsystems/nv3_pgraph.c | 24 ++--- 10 files changed, 216 insertions(+), 52 deletions(-) create mode 100644 src/video/nv/nv3/render/nv3_render_blit.c diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 83d378031..5e564fe29 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -113,6 +113,11 @@ typedef enum nv3_pgraph_class_e #define NV3_RECTANGLE_MAX 16 #define NV3_RECTANGLE_END 0x0480 +// blit +#define NV3_BLIT_POSITION_IN 0x0300 +#define NV3_BLIT_POSITION_OUT 0x0304 +#define NV3_BLIT_SIZE 0x0308 + // image_from_cpu #define NV3_IMAGE_START_POSITION 0x0304 // starting position of image from cpu #define NV3_IMAGE_SIZE 0x0308 diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index c5741f30c..e1cb0f65f 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,15 +18,25 @@ #pragma once /* Core */ -void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); +void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); +uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj); +uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj); +uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj); + uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color); // Convert a colour to full RGB10 format from the current working format. uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color); // Convert a colour from the current working format to RGB10 format. + + /* Pattern */ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1); /* Primitives */ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); -void nv3_render_chroma_test(nv3_grobj_t grobj); \ No newline at end of file +/* Chroma */ +void nv3_render_chroma_test(nv3_grobj_t grobj); + +/* Blit */ +void nv3_render_blit_screen2screen(nv3_grobj_t grobj); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index ed8d9c4fc..aa59f7e69 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -569,10 +569,10 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_SRC_CANVAS_MAX 0x400554 // Maximum Source Canvas for Blit, Y=30:16, X=10:0 #define NV3_PGRAPH_DST_CANVAS_MIN 0x400558 // Minimum Destination Canvas for Blit, Y=30:16, X=10:0 #define NV3_PGRAPH_DST_CANVAS_MAX 0x40055C // Maximum Destination Canvas for Blit, Y=30:16, X=10:0 -#define NV3_PGRAPH_pattern_color_0_rgb 0x400600 -#define NV3_PGRAPH_pattern_color_0_alpha 0x400604 -#define NV3_PGRAPH_pattern_color_1_rgb 0x400608 -#define NV3_PGRAPH_pattern_color_1_alpha 0x40060C // pattern color +#define NV3_PGRAPH_PATTERN_COLOR_0_RGB 0x400600 +#define NV3_PGRAPH_PATTERN_COLOR_0_ALPHA 0x400604 +#define NV3_PGRAPH_PATTERN_COLOR_1_RGB 0x400608 +#define NV3_PGRAPH_PATTERN_COLOR_1_ALPHA 0x40060C // pattern color #define NV3_PGRAPH_PATTERN_BITMAP_HIGH 0x400610 // pattern bitmap [31:0] #define NV3_PGRAPH_PATTERN_BITMAP_LOW 0x400614 // pattern bitmap [63:32] #define NV3_PGRAPH_PATTERN_SHAPE 0x400618 @@ -1183,7 +1183,7 @@ typedef struct nv3_pgraph_s uint64_t pattern_bitmap; // pattern bitmap for blit. it's alwaus 64 bits to simplify pixel rendering code uint32_t pattern_shape; // may need to be an enum - 0=8x8, 1=64x1, 2=1x64 uint32_t plane_mask; // only 7:0 relevant - uint32_t chroma_key; // color key + uint32_t chroma_key; // color key uint32_t beta_factor; nv3_pgraph_dma_settings_t dma_settings; uint8_t rop; // Current GDI Ternary Render Operation diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 43e7cf2a0..2e6d3af08 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -128,7 +128,9 @@ add_library(vid OBJECT nv/nv3/classes/nv3_class_01c_image_in_memory.c nv/nv3/render/nv3_render_core.c - nv/nv3/render/nv3_render_primitives.c + nv/nv3/render/nv3_render_primitives.c + nv/nv3/render/nv3_render_blit.c + ) if(G100) diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 3ff52f68a..0f15e82d6 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -32,6 +32,22 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { switch (method_id) { + case NV3_BLIT_POSITION_IN: + nv3->pgraph.blit.point_in.x = (param & 0xFFFF); + nv3->pgraph.blit.point_in.y = ((param >> 16) & 0xFFFF); + break; + case NV3_BLIT_POSITION_OUT: + nv3->pgraph.blit.point_out.x = (param & 0xFFFF); + nv3->pgraph.blit.point_out.y = ((param >> 16) & 0xFFFF); + break; + case NV3_BLIT_SIZE: + /* This is the last one*/ + nv3->pgraph.blit.size.w = (param & 0xFFFF); + nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); + + nv3_render_blit_screen2screen(grobj); + + break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 9b4446cff..dc865243e 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -81,22 +81,22 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ //pixel3 pixel3 = param & 0xFF; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel3, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel2 = (param >> 8) & 0xFF; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel2, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel1 = (param >> 16) & 0xFF; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (param >> 24) & 0xFF; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -104,12 +104,12 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ //2pixels packed into 1 case 16: pixel1 = (param) & 0xFFFF; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (param >> 16) & 0xFFFF; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -117,7 +117,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // just one case 32: pixel0 = param; - nv3_render_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c new file mode 100644 index 000000000..ce836520b --- /dev/null +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -0,0 +1,92 @@ +/* +* 86Box A hypervisor and IBM PC system emulator that specializes in +* running old operating systems and software designed for IBM +* PC systems and compatibles from 1981 through fairly recent +* system designs based on the PCI bus. +* +* This file is part of the 86Box distribution. +* +* NV3 Core rendering code (Software version) +* +* +* +* Authors: Connor Hyde, I need a better email address ;^) +* +* Copyright 2024-2025 Connor Hyde +*/ + +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/plat.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv3.h> + +void nv3_render_blit_screen2screen(nv3_grobj_t grobj) +{ + nv3_position_16_t old_position = nv3->pgraph.blit.point_in; + nv3_position_16_t new_position = nv3->pgraph.blit.point_out; + + uint16_t end_x = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); + uint16_t end_y = (nv3->pgraph.blit.point_out.y + nv3->pgraph.blit.size.h); + + /* Read the old pixel */ + switch (nv3->nvbase.svga.bpp) + { + case 8: //8bpp + for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) + { + old_position.y++; + new_position.y++; + + for (int32_t x = nv3->pgraph.blit.point_out.x; x < end_x; x++) + { + old_position.x++; + new_position.x++; + + uint32_t pixel_to_copy = nv3_render_read_pixel_8(old_position, grobj) & 0xFF; + nv3_render_write_pixel(new_position, pixel_to_copy, grobj); + } + } + break; + case 16: //16bpp + for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) + { + old_position.y++; + new_position.y++; + + for (int32_t x = nv3->pgraph.blit.point_out.x; x < end_x; x++) + { + old_position.x++; + new_position.x++; + + uint32_t pixel_to_copy = nv3_render_read_pixel_16(old_position, grobj) & 0xFFFF; + nv3_render_write_pixel(new_position, pixel_to_copy, grobj); + } + } + break; + case 32: //32bpp + for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) + { + old_position.y++; + new_position.y++; + + for (int32_t x = nv3->pgraph.blit.point_out.x; x < end_x; x++) + { + old_position.x++; + new_position.x++; + + uint32_t pixel_to_copy = nv3_render_read_pixel_32(old_position, grobj); + nv3_render_write_pixel(new_position, pixel_to_copy, grobj); + } + } + break; + } +} \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 741f8e422..c7ffd5f44 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -194,13 +194,71 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool nv3->pgraph.pattern_color_1_rgb.g = pattern_colour.g; nv3->pgraph.pattern_color_1_rgb.b = pattern_colour.b; } - - } +/* /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ +uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj) +{ + uint32_t vram_x = position.x; + uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; + + // we have to multiply the x position by the number of bytes per pixel + switch (framebuffer_bpp) + { + case 8: + break; + case 16: + vram_x = position.x << 1; + break; + case 32: + vram_x = position.x << 2; + break; + } + + uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * position.y) + nv3->pgraph.boffset[current_buffer]; + + pixel_addr_vram &= nv3->nvbase.svga.vram_mask; + + return pixel_addr_vram; +} + +/* Read an 8bpp pixel from the framebuffer. */ +uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj) +{ + // hope you call it with the right bit + uint32_t vram_address = nv3_render_get_vram_address(position, grobj); + + return nv3->nvbase.svga.vram[vram_address]; +} + +/* Read an 16bpp pixel from the framebuffer. */ +uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) +{ + // hope you call it with the right bit + uint32_t vram_address = nv3_render_get_vram_address(position, grobj); + + uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); + vram_address >>= 1; //convert to 16bit pointer + + return vram_16[vram_address]; +} + +/* Read an 16bpp pixel from the framebuffer. */ +uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) +{ + // hope you call it with the right bit + uint32_t vram_address = nv3_render_get_vram_address(position, grobj); + + uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); + vram_address >>= 1; //convert to 16bit pointer + + return vram_32[vram_address]; +} + /* Plots a pixel. */ -void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj) +void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj) { uint8_t alpha = 0xFF; @@ -213,7 +271,7 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr #endif bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; - uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too? + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too?z uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; /* doesn't seem*/ @@ -238,26 +296,7 @@ void nv3_render_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t gr /* TODO: Chroma Key, Pattern, Plane Mask...*/ - /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from. */ - - uint32_t vram_x = position.x; - - // we have to multiply the x position by the number of bytes per pixel - switch (framebuffer_bpp) - { - case 8: - break; - case 16: - vram_x = position.x << 1; - break; - case 32: - vram_x = position.x << 2; - break; - } - - uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * position.y) + nv3->pgraph.boffset[current_buffer]; - - pixel_addr_vram &= nv3->nvbase.svga.vram_mask; + uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj); uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0; uint8_t bit = 0x00; diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index e44636acb..f4bfdebf4 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -40,7 +40,7 @@ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t co { current_pos.x = x; - nv3_render_pixel(current_pos, color, grobj); + nv3_render_write_pixel(current_pos, color, grobj); } } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 70aef4270..251ec7a5f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -63,10 +63,10 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_SRC_CANVAS_MAX, "PGRAPH Source Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, { NV3_PGRAPH_DST_CANVAS_MIN, "PGRAPH Destination Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, { NV3_PGRAPH_DST_CANVAS_MAX, "PGRAPH Destination Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_pattern_color_0_rgb, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, - { NV3_PGRAPH_pattern_color_0_alpha, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, }, - { NV3_PGRAPH_pattern_color_1_rgb, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, - { NV3_PGRAPH_pattern_color_1_alpha, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_0_RGB, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_0_ALPHA, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_1_RGB, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, + { NV3_PGRAPH_PATTERN_COLOR_1_ALPHA, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, }, { NV3_PGRAPH_PATTERN_BITMAP_HIGH, "PGRAPH Pattern Bitmap (High 32bits)", NULL, NULL}, { NV3_PGRAPH_PATTERN_BITMAP_LOW, "PGRAPH Pattern Bitmap (Low 32bits)", NULL, NULL}, { NV3_PGRAPH_PATTERN_SHAPE, "PGRAPH Pattern Shape (1:0 - 0=8x8, 1=64x1, 2=1x64)", NULL, NULL}, @@ -185,16 +185,16 @@ uint32_t nv3_pgraph_read(uint32_t address) ret = *(uint32_t*)&nv3->pgraph.src_canvas_max; break; // Pattern - case NV3_PGRAPH_pattern_color_0_rgb: + case NV3_PGRAPH_PATTERN_COLOR_0_RGB: ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_rgb; break; - case NV3_PGRAPH_pattern_color_0_alpha: + case NV3_PGRAPH_PATTERN_COLOR_0_ALPHA: ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_alpha; break; - case NV3_PGRAPH_pattern_color_1_rgb: + case NV3_PGRAPH_PATTERN_COLOR_1_RGB: ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_rgb; break; - case NV3_PGRAPH_pattern_color_1_alpha: + case NV3_PGRAPH_PATTERN_COLOR_1_ALPHA: ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_alpha; break; case NV3_PGRAPH_PATTERN_BITMAP_HIGH: @@ -388,16 +388,16 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) *(uint32_t*)&nv3->pgraph.src_canvas_max = value; break; // Pattern - case NV3_PGRAPH_pattern_color_0_rgb: + case NV3_PGRAPH_PATTERN_COLOR_0_RGB: *(uint32_t*)&nv3->pgraph.pattern_color_0_rgb = value; break; - case NV3_PGRAPH_pattern_color_0_alpha: + case NV3_PGRAPH_PATTERN_COLOR_0_ALPHA: *(uint32_t*)&nv3->pgraph.pattern_color_0_alpha = value; break; - case NV3_PGRAPH_pattern_color_1_rgb: + case NV3_PGRAPH_PATTERN_COLOR_1_RGB: *(uint32_t*)&nv3->pgraph.pattern_color_1_rgb = value; break; - case NV3_PGRAPH_pattern_color_1_alpha: + case NV3_PGRAPH_PATTERN_COLOR_1_ALPHA: *(uint32_t*)&nv3->pgraph.pattern_color_1_alpha = value; break; case NV3_PGRAPH_PATTERN_BITMAP_HIGH: From be83a7c69db50c298b8446b1dae91bbd1cd5dfbc Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 23 Mar 2025 23:42:44 +0000 Subject: [PATCH 137/274] FIFO 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22 #define NV3_W95TXT_COLORA 0x03FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. +#define NV3_W95TXT_COLORA_RECT_START 0x0400 +#define NV3_W95TXT_COLORA_RECT_END 0x05FF /* Class context switch method */ typedef struct nv3_class_ctx_switch_method_s diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index d8b7cef96..088ddf1ba 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -653,14 +653,27 @@ that existed here before didn't make any sense #define NV3_GRAY_TABLE_NUM_ENTRIES 64 uint8_t nv3_pfifo_cache1_gray_code_table[NV3_GRAY_TABLE_NUM_ENTRIES] = { - 0b000000, 0b000001, 0b000011, 0b000010, 0b000110, 0b000111, 0b000101, 0b000100, - 0b001100, 0b001101, 0b001111, 0b001110, 0b001010, 0b001011, 0b001001, 0b001000, - 0b011000, 0b011001, 0b011011, 0b011010, 0b011110, 0b011111, 0b011101, 0b011100, - 0b010100, 0b010101, 0b010111, 0b010110, 0b010010, 0b010011, 0b010001, 0b010000, - 0b110000, 0b110001, 0b110011, 0b110010, 0b110110, 0b110111, 0b110101, 0b110100, - 0b111100, 0b111101, 0b111111, 0b111110, 0b111010, 0b111011, 0b111001, 0b111000, - 0b101000, 0b101001, 0b101011, 0b101010, 0b101110, 0b101111, 0b101101, 0b101100, - 0b100100, 0b100101, 0b100111, 0b100110, 0b100010, 0b100011, 0b100001, 0b100000 + 0b000000, 0b000001, 0b000011, 0b000010, 0b000110, 0b000111, 0b000101, 0b000100, //0x07 + 0b001100, 0b001101, 0b001111, 0b001110, 0b001010, 0b001011, 0b001001, 0b001000, //0x0F + 0b011000, 0b011001, 0b011011, 0b011010, 0b011110, 0b011111, 0b011101, 0b011100, //0x17 + 0b010100, 0b010101, 0b010111, 0b010110, 0b010010, 0b010011, 0b010001, 0b010000, //0x1F + 0b110000, 0b110001, 0b110011, 0b110010, 0b110110, 0b110111, 0b110101, 0b110100, //0x27 + 0b111100, 0b111101, 0b111111, 0b111110, 0b111010, 0b111011, 0b111001, 0b111000, //0x2F + 0b101000, 0b101001, 0b101011, 0b101010, 0b101110, 0b101111, 0b101101, 0b101100, //0x37 + 0b100100, 0b100101, 0b100111, 0b100110, 0b100010, 0b100011, 0b100001, 0b100000 //0x3F +}; + +/* The function is called up to hundreds of thousands of times per second, it's too slow to do anything else */ +uint8_t nv3_pfifo_cache1_binary_code_table[NV3_GRAY_TABLE_NUM_ENTRIES] = +{ + 0x00, 0x01, 0x03, 0x02, 0x07, 0x06, 0x04, 0x05, // 0x07 (0) + 0x0F, 0x0E, 0x0C, 0x0D, 0x08, 0x09, 0x0B, 0x0A, // 0x0F (1000) + 0x1F, 0x1E, 0x1C, 0x1D, 0x18, 0x19, 0x1B, 0x1A, // 0x17 (10000) + 0x10, 0x11, 0x13, 0x12, 0x17, 0x16, 0x14, 0x15, // 0x1F (11000) + 0x3F, 0x3E, 0x3C, 0x3D, 0x38, 0x39, 0x3B, 0x3A, // 0x27 (100000) + 0x30, 0x31, 0x33, 0x32, 0x37, 0x36, 0x34, 0x35, // 0x2F (101000) + 0x20, 0x21, 0x23, 0x22, 0x27, 0x26, 0x24, 0x25, // 0x37 (110000) + 0x2F, 0x2E, 0x2C, 0x2D, 0x28, 0x29, 0x2B, 0x2A, // 0X3f (111000) }; uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val) @@ -673,14 +686,7 @@ Back to sanity */ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) { - /* Is this a good idea? */ - for (uint32_t i = 0; i < NV3_GRAY_TABLE_NUM_ENTRIES; i++) - { - if (nv3_pfifo_cache1_gray_code_table[i] == val) - return i; - } - - return 0x00; + return nv3_pfifo_cache1_binary_code_table[val]; } // Submits graphics objects INTO cache0 @@ -854,13 +860,13 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) } // We didn't. Let's put it in CACHE1 - uint32_t current_put_address = nv3->pfifo.cache1_settings.put_address >> 2; - nv3->pfifo.cache1_entries[current_put_address].subchannel = subchannel; - nv3->pfifo.cache1_entries[current_put_address].method = method_offset; - nv3->pfifo.cache1_entries[current_put_address].data = param; + uint32_t current_put_index = nv3->pfifo.cache1_settings.put_address >> 2; + nv3->pfifo.cache1_entries[current_put_index].subchannel = subchannel; + nv3->pfifo.cache1_entries[current_put_index].method = method_offset; + nv3->pfifo.cache1_entries[current_put_index].data = param; // now we have to recalculate the cache1 put address - uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address); + uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_index); next_put_address++; if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# From 57edb25a2720046aca75f14bb1d6c537011bceaa Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 24 Mar 2025 01:13:04 +0000 Subject: [PATCH 138/274] GDI acceleration type A + chroma test --- .../86box/nv/classes/vid_nv3_classes.h | 60 +++++++++++++++---- src/include/86box/nv/render/vid_nv3_render.h | 4 +- src/include/86box/nv/vid_nv3.h | 14 +++-- .../nv/nv3/classes/nv3_class_007_rectangle.c | 6 +- .../classes/nv3_class_00c_win95_gdi_text.c | 36 ++++++++++- .../nv/nv3/classes/nv3_class_011_image.c | 6 +- src/video/nv/nv3/render/nv3_render_core.c | 24 +++++++- src/video/nv/nv3/subsystems/nv3_pbus.c | 7 +++ src/video/nv/nv3/subsystems/nv3_pfb.c | 8 +++ src/video/nv/nv3/subsystems/nv3_pgraph.c | 8 +++ 10 files changed, 146 insertions(+), 27 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 076502f63..309a1c5aa 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -132,9 +132,54 @@ typedef enum nv3_pgraph_class_e #define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET 0x030C #define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END 22 -#define NV3_W95TXT_COLORA 0x03FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. -#define NV3_W95TXT_COLORA_RECT_START 0x0400 -#define NV3_W95TXT_COLORA_RECT_END 0x05FF +/* GDI */ + +/* Type A: Unclipped Rectangle */ +#define NV3_W95TXT_A_COLOR 0x03FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. +#define NV3_W95TXT_A_RECT_START 0x0400 +#define NV3_W95TXT_A_RECT_SIZE 64 // Number of rects +#define NV3_W95TXT_A_RECT_END 0x05FF + +/* Type B: Clipped Rectangle */ +#define NV3_W95TXT_B_CLIP_TOPLEFT 0x07F4 +#define NV3_W95TXT_B_CLIP_BOTTOMRIGHT 0x07F8 +#define NV3_W95TXT_B_CLIP_CLIPRECT_START 0x0800 +#define NV3_W95TXT_B_CLIP_CLIPRECT_SIZE 128 // Number of rects +#define NV3_W95TXT_B_CLIP_CLIPRECT_END 0x09FF + +/* Type C: Unscaled Single-Colour Text (filled in from mono bitmap) */ +#define NV3_W95TXT_C_CLIP_TOPLEFT 0x0BEC +#define NV3_W95TXT_C_CLIP_BOTTOMRIGHT 0x0BF0 +#define NV3_W95TXT_C_CLIP_COLOR 0x0BF4 +#define NV3_W95TXT_C_CLIP_SIZE 0x0BF8 +#define NV3_W95TXT_C_CLIP_POSITION 0x0BFC /* TOP LEFT */ +#define NV3_W95TXT_C_CLIP_CLIPRECT_START 0x0C00 +#define NV3_W95TXT_C_CLIP_CLIPRECT_SIZE 64 // Number of rects +#define NV3_W95TXT_C_CLIP_CLIPRECT_END 0x0DFF + +/* Type D: Scaled Single-Colour Text (filled in from mono bitmap) */ +#define NV3_W95TXT_D_CLIP_TOPLEFT 0x0FE8 +#define NV3_W95TXT_D_CLIP_BOTTOMRIGHT 0x0FEC +#define NV3_W95TXT_D_CLIP_COLOR 0x0FF0 +#define NV3_W95TXT_D_CLIP_SIZE_IN 0x0FF4 +#define NV3_W95TXT_D_CLIP_SIZE_OUT 0x0FF8 +#define NV3_W95TXT_D_CLIP_POSITION 0x0FFC /* TOP LEFT */ +#define NV3_W95TXT_D_CLIP_CLIPRECT_START 0x1000 +#define NV3_W95TXT_D_CLIP_CLIPRECT_SIZE 128 // Number of rects +#define NV3_W95TXT_D_CLIP_CLIPRECT_END 0x11FF + +/* Type E: Scaled Pattern-type Bitmap Text (filled) */ +#define NV3_W95TXT_E_CLIP_TOPLEFT 0x13E4 +#define NV3_W95TXT_E_CLIP_BOTTOMRIGHT 0x13E8 +#define NV3_W95TXT_E_CLIP_COLOR_0 0x13EC +#define NV3_W95TXT_E_CLIP_COLOR_1 0x13F0 +#define NV3_W95TXT_E_CLIP_SIZE_IN 0x13F4 +#define NV3_W95TXT_E_CLIP_SIZE_OUT 0x13F8 +#define NV3_W95TXT_E_CLIP_POSITION 0x13FC /* TOP LEFT */ +#define NV3_W95TXT_E_CLIP_CLIPRECT_START 0x1400 +#define NV3_W95TXT_E_CLIP_CLIPRECT_SIZE 128 // Number of rects +#define NV3_W95TXT_E_CLIP_CLIPRECT_END 0x15FF + /* Class context switch method */ typedef struct nv3_class_ctx_switch_method_s @@ -523,12 +568,6 @@ typedef struct nv3_object_class_00B uint8_t reserved4[0x19FB]; } nv3_triangle_t; -typedef struct nv3_object_class_00C_nclip_s -{ - nv3_position_16_t position; - nv3_size_16_t size; -} nv3_object_class_00C_nclip_t; - /* Object Class 0x0C (real hardware) 0x0C (drivers) @@ -544,7 +583,8 @@ typedef struct nv3_object_class_00C uint32_t set_notify; // Set notifier uint8_t reserved2[0x2F4]; uint32_t color_a; // Color for Clip A - nv3_object_class_00C_nclip_t rect_nclip[64]; + nv3_position_16_t rect_a_position[64]; + nv3_size_16_t rect_a_size[64]; uint8_t reserved3[0x1F0]; nv3_clip_16_t clip_b; uint32_t color_b; // Color for Clip B diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index e1cb0f65f..5f6d39ae2 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -27,8 +27,6 @@ uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color); // Convert a colour to full RGB10 format from the current working format. uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color); // Convert a colour from the current working format to RGB10 format. - - /* Pattern */ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1); @@ -36,7 +34,7 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); /* Chroma */ -void nv3_render_chroma_test(nv3_grobj_t grobj); +bool nv3_render_chroma_test(nv3_grobj_t grobj, uint32_t color); /* Blit */ void nv3_render_blit_screen2screen(nv3_grobj_t grobj); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index aa59f7e69..d4ceb5cf4 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -202,6 +202,7 @@ extern const device_config_t nv3_config[]; #define NV3_CIO_START 0x3b0 // Legacy SVGA Emulation Subsystem #define NV3_CIO_END 0x3df #define NV3_PBUS_START 0x1000 // Bus Control Subsystem +#define NV3_PBUS_DEBUG_0 0x1084 // Bus Control Debug #define NV3_PBUS_INTR 0x1100 // Bus Control - Interrupt Status #define NV3_PBUS_INTR_EN 0x1140 // Bus Control - Interrupt Enable @@ -375,6 +376,7 @@ extern const device_config_t nv3_config[]; #define NV3_PFB_BOOT_RAM_EXTENSION_8MB 0x1 #define NV3_PFB_DELAY 0x100044 +#define NV3_PFB_DEBUG_0 0x100080 // Debug register for pfb #define NV3_PFB_GREEN_0 0x1000C0 #define NV3_PFB_CONFIG_0 0x100200 // Framebuffer interface config register 0 @@ -569,10 +571,10 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_SRC_CANVAS_MAX 0x400554 // Maximum Source Canvas for Blit, Y=30:16, X=10:0 #define NV3_PGRAPH_DST_CANVAS_MIN 0x400558 // Minimum Destination Canvas for Blit, Y=30:16, X=10:0 #define NV3_PGRAPH_DST_CANVAS_MAX 0x40055C // Maximum Destination Canvas for Blit, Y=30:16, X=10:0 -#define NV3_PGRAPH_PATTERN_COLOR_0_RGB 0x400600 -#define NV3_PGRAPH_PATTERN_COLOR_0_ALPHA 0x400604 -#define NV3_PGRAPH_PATTERN_COLOR_1_RGB 0x400608 -#define NV3_PGRAPH_PATTERN_COLOR_1_ALPHA 0x40060C // pattern color +#define NV3_PGRAPH_PATTERN_COLOR_0_RGB 0x400600 +#define NV3_PGRAPH_PATTERN_COLOR_0_ALPHA 0x400604 +#define NV3_PGRAPH_PATTERN_COLOR_1_RGB 0x400608 +#define NV3_PGRAPH_PATTERN_COLOR_1_ALPHA 0x40060C // pattern color #define NV3_PGRAPH_PATTERN_BITMAP_HIGH 0x400610 // pattern bitmap [31:0] #define NV3_PGRAPH_PATTERN_BITMAP_LOW 0x400614 // pattern bitmap [63:32] #define NV3_PGRAPH_PATTERN_SHAPE 0x400618 @@ -581,6 +583,7 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_CHROMA_KEY 0x40062C #define NV3_PGRAPH_BETA 0x400640 // Beta factor (30:23 fractional, 22:0 before fraction) #define NV3_PGRAPH_DMA 0x400680 +#define NV3_PGRAPH_INSTANCE 0x400688 // Current instance (?) // Current notification object for pgraph #define NV3_PGRAPH_NOTIFY 0x400684 // Notifier for PGRAPH @@ -905,6 +908,7 @@ typedef struct nv3_straps_s typedef struct nv3_pfb_s { uint32_t boot; + uint32_t debug_0; // debug stuff uint32_t config_0; // Framebuffer width, etc. uint32_t config_1; uint32_t green; @@ -960,6 +964,7 @@ typedef struct nv3_pbus_rma_s // Bus Configuration typedef struct nv3_pbus_s { + uint32_t debug_0; uint32_t interrupt_status; // Interrupt status uint32_t interrupt_enable; // Interrupt enable nv3_pbus_rma_t rma; @@ -1207,6 +1212,7 @@ typedef struct nv3_pgraph_s nv3_pgraph_status_t status; // Current status of the 3D engine. uint32_t trapped_address; uint32_t trapped_data; + uint32_t instance; // no idea what this is but possibly an object context uint32_t trapped_instance; /* This area is used for holding universal representations of the U* registers, which are actually mapped into MMIO */ diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 8f304fdac..fcf31132f 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -39,14 +39,13 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* Check for any rectangle point or size method. */ if (method_id >= NV3_RECTANGLE_START && method_id <= NV3_RECTANGLE_END) { - uint32_t index = (method_id - NV3_RECTANGLE_START) / 8; + uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; // If the size is submitted, render it. if (method_id & 0x04) { nv3->pgraph.rectangle.size[index].w = param & 0xFFFF; - nv3->pgraph.rectangle.size[index].h = (param >> 16) & 0xFFFF; - + nv3->pgraph.rectangle.size[index].h = (param >> 16) & 0xFFFF; nv_log("Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h, nv3->pgraph.rectangle.color); @@ -57,7 +56,6 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.rectangle.position[index].x = param & 0xFFFF; nv3->pgraph.rectangle.position[index].y = (param >> 16) & 0xFFFF; - nv_log("Rect%d Position=%d,%d\n", index, nv3->pgraph.rectangle.position[index].x, nv3->pgraph.rectangle.position[index].y); } diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 2b14ec2ff..9fbc92006 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -32,9 +32,43 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { switch (method_id) { + /* Type A: Unclipped Rectangle */ + + /* NOTE: This method is used by the GDI driver as part of the notification engine. */ + case NV3_W95TXT_A_COLOR: + nv3->pgraph.win95_gdi_text.color_a = param; + break; default: + /* These are the same things as rectangles */ + if (method_id >= NV3_W95TXT_A_RECT_START && method_id <= NV3_W95TXT_A_RECT_END) + { + uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; + + // If the size is submitted, render it. + if (method_id & 0x04) + { + nv3->pgraph.win95_gdi_text.rect_a_size[index].w = param & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].h = (param >> 16) & 0xFFFF; + + nv_log("Rect GDI-A%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, + nv3->pgraph.win95_gdi_text.rect_a_size[index].h, nv3->pgraph.win95_gdi_text.color_a); + + nv3_render_rect(nv3->pgraph.win95_gdi_text.rect_a_position[index], + nv3->pgraph.win95_gdi_text.rect_a_size[index], nv3->pgraph.win95_gdi_text.color_a, grobj); + } + else // position + { + nv3->pgraph.win95_gdi_text.rect_a_position[index].x = param & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_position[index].y = (param >> 16) & 0xFFFF; + + nv_log("Rect GDI-A%d Position=%d,%d\n", index, + nv3->pgraph.win95_gdi_text.rect_a_position[index].x, nv3->pgraph.win95_gdi_text.rect_a_position[index].y); + } + return; + } + nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; + break; } } \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index dc865243e..8dee40a21 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -76,7 +76,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) { - // 4pixels packed into one + // 4pixels packed into one param case 8: //pixel3 @@ -101,7 +101,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3_class_011_check_line_bounds(); break; - //2pixels packed into 1 + //2pixels packed into one param case 16: pixel1 = (param) & 0xFFFF; nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); @@ -114,7 +114,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3_class_011_check_line_bounds(); break; - // just one + // just one pixel in 32bpp case 32: pixel0 = param; nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index c7ffd5f44..7ef08e665 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -155,10 +155,28 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co return packed_color; } -/* Runs the chroma key test */ -void nv3_render_chroma_test(nv3_grobj_t grobj) +/* Runs the chroma key/color key test */ +bool nv3_render_chroma_test(nv3_grobj_t grobj, uint32_t color) { + bool chroma_enabled = ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_CHROMA_KEY) & 0x01); + if (!chroma_enabled) + return true; + + bool alpha = ((nv3->pgraph.chroma_key >> 31) & 0x01); + + if (!alpha) + return true; + + /* this is dumb but i'm lazy, if it kills perf, fix it later - we need to do some format shuffling */ + nv3_grobj_t grobj_fake = {0}; + grobj_fake.grobj_0 = 0x02; /* we don't care about any other bits */ + + nv3_color_expanded_t chroma_expanded = nv3_render_expand_color(grobj_fake, nv3->pgraph.chroma_key); + + uint32_t chroma_downconverted = nv3_render_downconvert_color(grobj, chroma_expanded); + + return !(chroma_downconverted == color); } /* Convert expanded colour format to chroma key format */ @@ -295,6 +313,8 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob } /* TODO: Chroma Key, Pattern, Plane Mask...*/ + if (!nv3_render_chroma_test(grobj, color)) + return; uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj); diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index ca631edfc..46d829fb2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -33,6 +33,7 @@ // Putting this in pbus because imo it makes the most sense (related to memory access/memory interface) nv_register_t pbus_registers[] = { + { NV3_PBUS_DEBUG_0, "PBUS - Debug Register", NULL, NULL}, { NV3_PBUS_INTR, "PBUS - Interrupt Status", NULL, NULL}, { NV3_PBUS_INTR_EN, "PBUS - Interrupt Enable", NULL, NULL,}, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value @@ -65,6 +66,9 @@ uint32_t nv3_pbus_read(uint32_t address) { switch (reg->address) { + case NV3_PBUS_DEBUG_0: + ret = nv3->pbus.debug_0; + break; case NV3_PBUS_INTR: ret = nv3->pbus.interrupt_status; break; @@ -108,6 +112,9 @@ void nv3_pbus_write(uint32_t address, uint32_t value) { switch (reg->address) { + case NV3_PBUS_DEBUG_0: + nv3->pbus.debug_0 = value; + break; // Interrupt registers // Interrupt state: // Bit 0 - PCI Bus Error diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 160cbff08..644d4090d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -35,6 +35,7 @@ void nv3_pfb_config0_write(uint32_t val); nv_register_t pfb_registers[] = { { NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL}, { NV3_PFB_DELAY, "PFB Delay", NULL, NULL}, + { NV3_PFB_DEBUG_0, "PFB Debug", NULL, NULL }, { NV3_PFB_GREEN_0, "PFB Green / Power Saving", NULL, NULL,}, { NV3_PFB_CONFIG_0, "PFB Framebuffer Config 0", nv3_pfb_config0_read, nv3_pfb_config0_write }, { NV3_PFB_CONFIG_1, "PFB Framebuffer Config 1", NULL, NULL }, @@ -85,6 +86,9 @@ uint32_t nv3_pfb_read(uint32_t address) case NV3_PFB_BOOT: ret = nv3->pfb.boot; break; + case NV3_PFB_DEBUG_0: + ret = nv3->pfb.debug_0; + break; // Config 0 has a read/write function case NV3_PFB_CONFIG_1: ret = nv3->pfb.config_1; @@ -136,6 +140,10 @@ void nv3_pfb_write(uint32_t address, uint32_t value) { switch (reg->address) { + // Boot is read only + case NV3_PFB_DEBUG_0: + nv3->pfb.debug_0 = value; + break; // Config 0 has a read/write function case NV3_PFB_CONFIG_1: // Config Register 1 nv3->pfb.config_1 = value; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 251ec7a5f..ece125b0f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -240,6 +240,7 @@ uint32_t nv3_pgraph_read(uint32_t address) case NV3_PGRAPH_CLIP_MISC: ret = *(uint32_t*)&nv3->pgraph.clip_misc_settings; break; + // Overall Status case NV3_PGRAPH_STATUS: ret = *(uint32_t*)&nv3->pgraph.status; @@ -251,6 +252,9 @@ uint32_t nv3_pgraph_read(uint32_t address) case NV3_PGRAPH_TRAPPED_DATA: ret = nv3->pgraph.trapped_data; break; + case NV3_PGRAPH_INSTANCE: + ret = nv3->pgraph.instance; + break; case NV3_PGRAPH_TRAPPED_INSTANCE: ret = nv3->pgraph.trapped_instance; break; @@ -454,9 +458,13 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) case NV3_PGRAPH_TRAPPED_DATA: nv3->pgraph.trapped_data = value; break; + case NV3_PGRAPH_INSTANCE: + nv3->pgraph.instance = value; + break; case NV3_PGRAPH_TRAPPED_INSTANCE: nv3->pgraph.trapped_instance = value; break; + } } } From c3ebf327d90d1cf3d86ec8d35f9816b3f2113c76 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 24 Mar 2025 13:17:22 +0000 Subject: [PATCH 139/274] partially working text acceleration, looks inverted(??) --- doc/nvidia_notes/status.xlsx | Bin 15398 -> 15459 bytes src/include/86box/nv/render/vid_nv3_render.h | 5 +- src/include/86box/nv/vid_nv3.h | 1 + .../classes/nv3_class_00c_win95_gdi_text.c | 47 ++++++++++++- .../nv/nv3/render/nv3_render_primitives.c | 63 ++++++++++++++++++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 3 +- src/video/nv/nv3/subsystems/nv3_pramin.c | 4 +- 7 files changed, 118 insertions(+), 5 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index 7d58d5250c8be03718dd86b5bfe94561227001a6..f36ba573a387bc65b2c1cd642c0d77d58c5ef604 100644 GIT binary patch delta 4045 zcmZ8kWmFUj)82)pk&?~@M1-YTln#+@q(i!60YO;6U8F&JX_oGiR&)gfE+O3^(y1to zz!Ll3_x||qd%pQGXU@#?W8$2dXDWg=gBsTfN#H9?w$}Inz&YwCAs6y58G`%ZFiq1G zDzEb88h6ZcmU@N*+Llga{;@`lJMNkdl{U2_@2^k-A_@r&b>11dygBWBmmo-&cKlFu zGRJ|rmGiUh=tI%2Rl&LmXjzZW8_3GUU!f&aH=)Plm8WbB$&fLQdjMBQ`%KNYCNC|+ zDdu7El_^4#Ijb47?pox+LNgsLLvxwYY{qYCUEBF=i5(y(JxBN2z67`bn1<=JDw`sx zz7Y@G>{!n_;eJBh&ir=ZT^n(OWtdr0e03%J4Ah;*#+zB_s0Q!D#o&`ac%8tT6nx4+ zNs>(6q#7n_tCKcqeAjD5>|e;O1>z2p?mH+Uhw_Q1(g*F`qd}x5sOu}gq&-1{?ckLI z6g2g-jYjzhaeq|7@8#&*Q;FKWTcuBg-b)axeQo0k1H0;za6XF%JG3vZk~(v!tn&iu z!i}GtEq`ehPV(!dS5=yCubp8dhKI!r5r+?+xA72j*VEG7Gx6_dA&?F|-q(|ucNo{C zAbsM!*Tr_9mXr*6M$p-FAH~?PC1FxN8OJZ`a(sdTU1Sy6_h;Fq9N#vtIWBsdcONPD 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+ nv3->pgraph.win95_gdi_text.clip_d.bottom = ((param >> 16) & 0xFFFF); + /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ + break; + case NV3_W95TXT_D_CLIP_COLOR: + nv3->pgraph.win95_gdi_text.color1_d = param; + break; + case NV3_W95TXT_D_CLIP_SIZE_IN: + nv3->pgraph.win95_gdi_text.size_in_d.w = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_in_d.h = ((param >> 16) & 0xFFFF); + break; + case NV3_W95TXT_D_CLIP_SIZE_OUT: + nv3->pgraph.win95_gdi_text.size_out_d.w = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_out_d.h = ((param >> 16) & 0xFFFF); + break; + case NV3_W95TXT_D_CLIP_POSITION: + nv3->pgraph.win95_gdi_text.point_d.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.point_d.y = ((param >> 16) & 0xFFFF); + + nv3->pgraph.win95_gdi_text_current_position = nv3->pgraph.win95_gdi_text.point_d; + break; default: - /* These are the same things as rectangles */ + /* Type A submission: these are the same things as rectangles */ if (method_id >= NV3_W95TXT_A_RECT_START && method_id <= NV3_W95TXT_A_RECT_END) { uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; @@ -66,6 +93,24 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } return; } + else if (method_id >= NV3_W95TXT_D_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_D_CLIP_CLIPRECT_END) + { + /* lol */ + uint32_t index = (method_id - NV3_W95TXT_D_CLIP_CLIPRECT_START) >> 3; + + nv3->pgraph.win95_gdi_text.mono_color1_d[index] = param; + + /* Mammoth logger! */ + nv_log("Rect GDI-D%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", + index, param, nv3->pgraph.win95_gdi_text.size_in_d.w, nv3->pgraph.win95_gdi_text.size_in_d.h, + nv3->pgraph.win95_gdi_text.size_out_d.w, nv3->pgraph.win95_gdi_text.size_out_d.h, + nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y, + nv3->pgraph.win95_gdi_text.color1_d, + nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.right, nv3->pgraph.win95_gdi_text.clip_d.top, nv3->pgraph.win95_gdi_text.clip_d.bottom); + + nv3_render_gdi_type_d(grobj, nv3->pgraph.win95_gdi_text.mono_color1_d[index]); + + } nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index f4bfdebf4..d8dfe7ba9 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -36,6 +36,7 @@ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t co for (int32_t y = position.y; y < (position.y + size.h); y++) { current_pos.y = y; + for (int32_t x = position.x; x < (position.x + size.w); x++) { current_pos.x = x; @@ -43,4 +44,66 @@ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t co nv3_render_write_pixel(current_pos, color, grobj); } } +} + +void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) +{ + // reset when a position is submitted + nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; + + // is this clip or point? + + uint16_t end_x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; + uint16_t end_y = nv3->pgraph.win95_gdi_text.point_d.y + nv3->pgraph.win95_gdi_text.size_in_d.h; + + /* set up our packed pixels */ + uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; + + /* Go through the bitmap that was sent, bit by bit. */ + for (int32_t bit_num = 0; bit_num <= 31; bit_num++) + { + bool bit = (param >> bit_num) & 0x01; + //bool bit = true; // debug test + + nv3->pgraph.win95_gdi_text_current_position.x++; + + /* let's hope NV never overflow the y */ + if (nv3->pgraph.win95_gdi_text_current_position.x >= end_x) + { + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; + nv3->pgraph.win95_gdi_text_current_position.y++; + } + + /* check if we are in the clipping rectangle */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left + || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right + || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top + || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) + { + return; + } + + // if it's 0 we don't need to do anything + if (!bit) + continue; + else + { + switch (nv3->nvbase.svga.bpp) + { + case 8: + uint32_t final_color8 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color8, grobj); + break; + case 16: + uint32_t final_color16 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color16, grobj); + break; + case 32: + uint32_t final_color32 = (nv3->pgraph.win95_gdi_text.color1_d); /* do we need to add anything? mul blend perhaps? */ + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color32, grobj); + break; + } + } + + } } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 088ddf1ba..b782f2b56 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -939,9 +939,10 @@ void nv3_pfifo_cache1_pull() nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; nv3_debug_ramin_print_context_info(current_param, context_structure); + #endif nv3_pgraph_submit(current_param, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); - #endif + //Todo: finish it } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 7a5ff749b..b4858acca 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -477,7 +477,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u else { nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; + nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; } // It's an error but it isn't lol @@ -504,7 +504,7 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte { #ifndef RELEASE_BUILD nv_log("Found object:\n"); - nv_log("Name: 0x%04x\n", name); + nv_log("Param: 0x%04x\n", name); nv_log("Context:\n"); nv_log("DMA Channel %d (0-7 valid)\n", context.channel); From 94cd84363cb505fe10cf532eeb34f93011fb1640 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 24 Mar 2025 13:34:22 +0000 Subject: [PATCH 140/274] Much improved text rendering. It was being read horizontally backwards and the position was being incremented too early. --- .../classes/nv3_class_00c_win95_gdi_text.c | 3 +- .../nv/nv3/render/nv3_render_primitives.c | 42 +++++++++---------- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index a834da989..9c1546cf1 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -63,7 +63,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.point_d.x = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.point_d.y = ((param >> 16) & 0xFFFF); - nv3->pgraph.win95_gdi_text_current_position = nv3->pgraph.win95_gdi_text.point_d; + nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w); + nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); break; default: /* Type A submission: these are the same things as rectangles */ diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index d8dfe7ba9..8a9ca8598 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -65,28 +65,9 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) bool bit = (param >> bit_num) & 0x01; //bool bit = true; // debug test - nv3->pgraph.win95_gdi_text_current_position.x++; - /* let's hope NV never overflow the y */ - if (nv3->pgraph.win95_gdi_text_current_position.x >= end_x) - { - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; - nv3->pgraph.win95_gdi_text_current_position.y++; - } - - /* check if we are in the clipping rectangle */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left - || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right - || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top - || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) - { - return; - } - - // if it's 0 we don't need to do anything - if (!bit) - continue; - else + // if it's a 0 bit we don't need to do anything + if (bit) { switch (nv3->nvbase.svga.bpp) { @@ -105,5 +86,24 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) } } + /* increment the position - the bitmap is stored horizontally backward */ + nv3->pgraph.win95_gdi_text_current_position.x--; + + /* let's hope NV never overflow the y */ + if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) + { + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; + nv3->pgraph.win95_gdi_text_current_position.y++; + } + + /* check if we are in the clipping rectangle */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left + || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right + || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top + || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) + { + return; + } + } } \ No newline at end of file From 997acb990e9393a137e6d85737b0470ef9c0b54e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 24 Mar 2025 19:56:54 +0000 Subject: [PATCH 141/274] Most text seems to be fine now. --- .../classes/nv3_class_00c_win95_gdi_text.c | 18 ++- .../nv/nv3/render/nv3_render_primitives.c | 142 ++++++++++++------ 2 files changed, 112 insertions(+), 48 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 9c1546cf1..dcad8b088 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -63,8 +63,20 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.point_d.x = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.point_d.y = ((param >> 16) & 0xFFFF); - nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w); - nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); + /* small case*/ + if (nv3->pgraph.win95_gdi_text.size_in_d.w < 0x0010) + { + nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w); + nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); + } + /* large case: draw (7-0) (15-8)*/ + else + { + uint16_t large_start = (nv3->pgraph.win95_gdi_text.size_in_d.w >> 1) ; + nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + large_start); + nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); + } + break; default: /* Type A submission: these are the same things as rectangles */ @@ -110,7 +122,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.right, nv3->pgraph.win95_gdi_text.clip_d.top, nv3->pgraph.win95_gdi_text.clip_d.bottom); nv3_render_gdi_type_d(grobj, nv3->pgraph.win95_gdi_text.mono_color1_d[index]); - + return; } nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 8a9ca8598..91c0728c7 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -46,48 +46,50 @@ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t co } } -void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) +void nv3_render_text_1bpp(bool bit, nv3_grobj_t grobj) { - // reset when a position is submitted - nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; + uint16_t clip_x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_out_d.w; + uint16_t clip_y = nv3->pgraph.win95_gdi_text.point_d.y + nv3->pgraph.win95_gdi_text.size_out_d.h; - // is this clip or point? + /* they send more data than they need */ + if (nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) + bit = false; - uint16_t end_x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; - uint16_t end_y = nv3->pgraph.win95_gdi_text.point_d.y + nv3->pgraph.win95_gdi_text.size_in_d.h; - - /* set up our packed pixels */ - uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; - - /* Go through the bitmap that was sent, bit by bit. */ - for (int32_t bit_num = 0; bit_num <= 31; bit_num++) + // if it's a 0 bit we don't need to do anything + if (bit) { - bool bit = (param >> bit_num) & 0x01; - //bool bit = true; // debug test - - - // if it's a 0 bit we don't need to do anything - if (bit) + switch (nv3->nvbase.svga.bpp) { - switch (nv3->nvbase.svga.bpp) - { - case 8: - uint32_t final_color8 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color8, grobj); - break; - case 16: - uint32_t final_color16 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color16, grobj); - break; - case 32: - uint32_t final_color32 = (nv3->pgraph.win95_gdi_text.color1_d); /* do we need to add anything? mul blend perhaps? */ - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color32, grobj); - break; - } + case 8: + uint32_t final_color8 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color8, grobj); + break; + case 16: + uint32_t final_color16 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color16, grobj); + break; + case 32: + uint32_t final_color32 = (nv3->pgraph.win95_gdi_text.color1_d); /* do we need to add anything? mul blend perhaps? */ + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color32, grobj); + break; } + } - /* increment the position - the bitmap is stored horizontally backward */ - nv3->pgraph.win95_gdi_text_current_position.x--; + /* increment the position - the bitmap is stored horizontally backward */ + nv3->pgraph.win95_gdi_text_current_position.x--; + + if (nv3->pgraph.win95_gdi_text.size_in_d.w < 0x0010) + { + if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) + { + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; + nv3->pgraph.win95_gdi_text_current_position.y++; + } + } + /* dumb hack but it never seems to be any other sizes. draw lines (7-0) and then (15-8) */ + else + { + uint16_t midpoint_x = nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_in_d.w << 1); /* let's hope NV never overflow the y */ if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) @@ -95,15 +97,65 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; nv3->pgraph.win95_gdi_text_current_position.y++; } - - /* check if we are in the clipping rectangle */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left - || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right - || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top - || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) - { - return; - } - } + + /* check if we are in the clipping rectangle */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left + || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right + || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top + || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) + { + return; + } + +} + +void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) +{ + // reset when a position is submitted + nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; + + // is this clip or point? + + + /* set up our packed pixels */ + uint32_t pixel0 = param & 0xFF; + uint32_t pixel1 = (param >> 8) & 0xFF; + uint32_t pixel2 = (param >> 16) & 0xFF; + uint32_t pixel3 = (param >> 24) & 0xFF; + + /* small stuff */ + + /* Go through the bitmap that was sent, bit by bit. */ + for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + { + bool bit = (pixel0 >> bit_num) & 0x01; + + nv3_render_text_1bpp(bit, grobj); + } + + /* Go through the bitmap that was sent, bit by bit. */ + for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + { + bool bit = (pixel1 >> bit_num) & 0x01; + + nv3_render_text_1bpp(bit, grobj); + } + + /* Go through the bitmap that was sent, bit by bit. */ + for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + { + bool bit = (pixel2 >> bit_num) & 0x01; + + nv3_render_text_1bpp(bit, grobj); + } + + /* Go through the bitmap that was sent, bit by bit. */ + for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + { + bool bit = (pixel3 >> bit_num) & 0x01; + + nv3_render_text_1bpp(bit, grobj); + } + } \ No newline at end of file From 0b458b8ee4c1ac4b9820384d67de24c69bd91188 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 24 Mar 2025 20:02:36 +0000 Subject: [PATCH 142/274] Simplify the code. --- .../nv/nv3/render/nv3_render_primitives.c | 38 +------------------ 1 file changed, 2 insertions(+), 36 deletions(-) diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 91c0728c7..52473f2d4 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -117,45 +117,11 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) // is this clip or point? - - /* set up our packed pixels */ - uint32_t pixel0 = param & 0xFF; - uint32_t pixel1 = (param >> 8) & 0xFF; - uint32_t pixel2 = (param >> 16) & 0xFF; - uint32_t pixel3 = (param >> 24) & 0xFF; - - /* small stuff */ - /* Go through the bitmap that was sent, bit by bit. */ - for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + for (int32_t bit_num = 0; bit_num <= 31; bit_num++) { - bool bit = (pixel0 >> bit_num) & 0x01; + bool bit = (param >> bit_num) & 0x01; nv3_render_text_1bpp(bit, grobj); } - - /* Go through the bitmap that was sent, bit by bit. */ - for (int32_t bit_num = 0; bit_num <= 7; bit_num++) - { - bool bit = (pixel1 >> bit_num) & 0x01; - - nv3_render_text_1bpp(bit, grobj); - } - - /* Go through the bitmap that was sent, bit by bit. */ - for (int32_t bit_num = 0; bit_num <= 7; bit_num++) - { - bool bit = (pixel2 >> bit_num) & 0x01; - - nv3_render_text_1bpp(bit, grobj); - } - - /* Go through the bitmap that was sent, bit by bit. */ - for (int32_t bit_num = 0; bit_num <= 7; bit_num++) - { - bool bit = (pixel3 >> bit_num) & 0x01; - - nv3_render_text_1bpp(bit, grobj); - } - } \ No newline at end of file From fcf01cb487b976a8abc681c5a07559711ff67cd7 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 24 Mar 2025 20:07:34 +0000 Subject: [PATCH 143/274] Remove even more redundant GDI-D code --- doc/nvidia_notes/status.xlsx | Bin 15459 -> 15504 bytes .../nv/nv3/render/nv3_render_primitives.c | 21 +++--------------- 2 files changed, 3 insertions(+), 18 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index f36ba573a387bc65b2c1cd642c0d77d58c5ef604..0b76f7036b788e2a4943c59f11902094edbef605 100644 GIT binary patch delta 4997 zcmZ8lcTm$^vktw3R0&0T?@f_jl`bHW7Yto`krogTeh|8Z8hS^iL#Tq3(1LX79i@l} z2nYx&#e@&NckVm)JAdpv=REt&oY~pgvwJq5r3BS)5ECWEZxlk2Ux)>Pck*iZ!dB`k z%^3mJRR;k!+z@K{Ug1UP3U6f<_At;uPcQFs5*tUywtsw_lOwZvGI817*kUHk|I9wb zd8kEjLc8~jzoC0gEI-~;$ncrEaIdSqs)-}eb+$coZZtHQaU+=tGM7Mg=?*+*%#@*`GAqW%dZ)T~($Etg4cmD{=ial2~E zPMY(%nSdO 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    &uPDyu1cHL2VW=2q`rZs$+jNS`(R1`=TE z{+Z0+SJ=0T_1qZX&I>oZh{7zsI#=iBa4BhhD^`vW=Lx!;6*sA*m{*LnJe2mDb4q0n z!3a!AYi5?re9epvp)fHNT(((0NZt9*dHz@xCixi%Mtg=$r2*%A< z&zGB0o@8-U&{4tQB2Ra&m5yvxWUfbN|z(VHt;IhpHfCgxJwwI$ELp6yeJnH^fDwvIH(8;0`i- zswZX;X2o^W$t72L2NhG>n*airs1cke3*HB_-fo%P#QHzqhCB;T;>5=Y5l=9CCwriK znq7NKw?Q*lWLcb)P(Vd!Vwd(9ua?u0ma(ZqW&u5RTX{m;qSV3NRYTxeATg!TKicmk7K@wC$qKBQ z*R1D-Pl+Gq_ksdSF@xAScicEtGa z=Mw0JE}A(!=mihvpH3KF`+^D`K?rA}q=f%?K}r8_vjPB6KU4<)ju6tnAZAfY`hUx} z{|~yQcmUDDT}8RjIcfglYaZ}_D~gA5F97fVc0j_&D)c^nh diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 52473f2d4..49684edc3 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -78,25 +78,10 @@ void nv3_render_text_1bpp(bool bit, nv3_grobj_t grobj) /* increment the position - the bitmap is stored horizontally backward */ nv3->pgraph.win95_gdi_text_current_position.x--; - if (nv3->pgraph.win95_gdi_text.size_in_d.w < 0x0010) + if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) { - if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) - { - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; - nv3->pgraph.win95_gdi_text_current_position.y++; - } - } - /* dumb hack but it never seems to be any other sizes. draw lines (7-0) and then (15-8) */ - else - { - uint16_t midpoint_x = nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_in_d.w << 1); - - /* let's hope NV never overflow the y */ - if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) - { - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; - nv3->pgraph.win95_gdi_text_current_position.y++; - } + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; + nv3->pgraph.win95_gdi_text_current_position.y++; } /* check if we are in the clipping rectangle */ From a9250c5d1965e6f9aa262f739f243234099ba8be Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 25 Mar 2025 02:19:21 +0000 Subject: [PATCH 144/274] Legitimately I don't even know how i mostly fixed it. What's going on? --- doc/nvidia_notes/status.xlsx | Bin 15504 -> 15607 bytes src/include/86box/nv/render/vid_nv3_render.h | 3 +- src/include/86box/nv/vid_nv3.h | 2 +- .../classes/nv3_class_00c_win95_gdi_text.c | 57 +++++++++- .../nv/nv3/render/nv3_render_primitives.c | 97 ++++++++++++++++-- 5 files changed, 144 insertions(+), 15 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index 0b76f7036b788e2a4943c59f11902094edbef605..e23fe6c7248b0bed60a1a932a22f5bf1d20bfb23 100644 GIT binary patch delta 3349 zcmV+w4eIicdG~p+;RXZ=y$D2;XT#Vlw!T$6NK8ECfyOM3WiQ$oz41bYTc*F`{!7%!5Gz`+}wGzYO{UTa$ zNk3BC1DBQY#VgGhqGDs}Y z7x)TqLSwR0*F=|AC#%Gs$IEXD++Tu zN}UL&zT=1C%*n#V)bSC2noJOi@B-l<;EW7oDoCfxm&hCF#P%V~CsSX@ewe{1?s)M^ z;~BmD9Misg4Rb$?!=}dFbGB2j8ZljK|D895*d?}uJ#gyjZFkpCe&>ZQL1Yo~!Q?RZ z596B>7~^1S))A`tmfevRj2IU@!!xm;qbx-z^A=7%2~x*jOpz0R<&ozsW`Q4sY347` zwCCrJ2==uVi1w}3^!aeBiSD2*_G9MAA**F<_K;TvHXe?xvu-oCos4X~_qI1oiK;V| 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uint32_t param); /* GDI Type-E: Clipped 1bpp two-colour text */ \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 78cc3953a..e70a0bec6 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1233,7 +1233,7 @@ typedef struct nv3_pgraph_s struct nv3_object_class_00E scaled_image_from_memory; struct nv3_object_class_010 blit; struct nv3_object_class_011 image; - nv3_position_16_t image_current_position; /* This is here so we can hold the current state of the image */ + nv3_position_16_t image_current_position; /* This is here so we can hold the current state of the image */ struct nv3_object_class_012 bitmap; struct nv3_object_class_014 transfer2memory; struct nv3_object_class_015 stretched_image_from_cpu; diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index dcad8b088..8d126e6cc 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -66,17 +66,52 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* small case*/ if (nv3->pgraph.win95_gdi_text.size_in_d.w < 0x0010) { - nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w); + nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_in_d.w - 1)); nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); } /* large case: draw (7-0) (15-8)*/ else { - uint16_t large_start = (nv3->pgraph.win95_gdi_text.size_in_d.w >> 1) ; + uint16_t large_start = (nv3->pgraph.win95_gdi_text.size_in_d.w >> 1) - 1; nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + large_start); nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); } + break; + /* Type E: Two-colour 1bpp */ + case NV3_W95TXT_E_CLIP_TOPLEFT: + nv3->pgraph.win95_gdi_text.clip_e.left = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clip_e.top = ((param >> 16) & 0xFFFF); + break; + case NV3_W95TXT_E_CLIP_BOTTOMRIGHT: + nv3->pgraph.win95_gdi_text.clip_e.right = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clip_e.bottom = ((param >> 16) & 0xFFFF); + /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ + break; + case NV3_W95TXT_E_CLIP_COLOR_0: + nv3->pgraph.win95_gdi_text.color0_e = param; + break; + case NV3_W95TXT_E_CLIP_COLOR_1: + nv3->pgraph.win95_gdi_text.color1_e = param; + break; + case NV3_W95TXT_E_CLIP_SIZE_IN: + nv3->pgraph.win95_gdi_text.size_in_e.w = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_in_e.h = ((param >> 16) & 0xFFFF); + break; + case NV3_W95TXT_E_CLIP_SIZE_OUT: + nv3->pgraph.win95_gdi_text.size_out_e.w = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_out_e.h = ((param >> 16) & 0xFFFF); + break; + case NV3_W95TXT_E_CLIP_POSITION: + nv3->pgraph.win95_gdi_text.point_e.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.point_e.y = ((param >> 16) & 0xFFFF); + + uint16_t large_start = (nv3->pgraph.win95_gdi_text.size_in_e.w >> 1) - 1; + + //nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_e.x + large_start); + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x; + nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_e.y); + break; default: /* Type A submission: these are the same things as rectangles */ @@ -124,6 +159,24 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3_render_gdi_type_d(grobj, nv3->pgraph.win95_gdi_text.mono_color1_d[index]); return; } + else if (method_id >= NV3_W95TXT_E_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_E_CLIP_CLIPRECT_END) + { + /* lol */ + uint32_t index = (method_id - NV3_W95TXT_E_CLIP_CLIPRECT_START) >> 3; + + nv3->pgraph.win95_gdi_text.mono_color1_d[index] = param; + + /* Mammoth logger! */ + nv_log("Rect GDI-E%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", + index, param, nv3->pgraph.win95_gdi_text.size_in_e.w, nv3->pgraph.win95_gdi_text.size_in_e.h, + nv3->pgraph.win95_gdi_text.size_out_e.w, nv3->pgraph.win95_gdi_text.size_out_e.h, + nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y, + nv3->pgraph.win95_gdi_text.color1_e, + nv3->pgraph.win95_gdi_text.clip_e.left, nv3->pgraph.win95_gdi_text.clip_e.right, nv3->pgraph.win95_gdi_text.clip_e.top, nv3->pgraph.win95_gdi_text.clip_e.bottom); + + nv3_render_gdi_type_e(grobj, nv3->pgraph.win95_gdi_text.mono_color1_d[index]); + return; + } nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 49684edc3..6190040a5 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -55,32 +55,37 @@ void nv3_render_text_1bpp(bool bit, nv3_grobj_t grobj) if (nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) bit = false; + uint32_t final_color; + // if it's a 0 bit we don't need to do anything if (bit) { switch (nv3->nvbase.svga.bpp) { case 8: - uint32_t final_color8 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color8, grobj); + final_color = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ break; case 16: - uint32_t final_color16 = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color16, grobj); + final_color = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ break; case 32: - uint32_t final_color32 = (nv3->pgraph.win95_gdi_text.color1_d); /* do we need to add anything? mul blend perhaps? */ - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color32, grobj); + final_color = (nv3->pgraph.win95_gdi_text.color1_d); /* do we need to add anything? mul blend perhaps? */ break; } } + /* in type d colour0 is always transparent */ + if (bit) + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color, grobj); + /* increment the position - the bitmap is stored horizontally backward */ nv3->pgraph.win95_gdi_text_current_position.x--; - if (nv3->pgraph.win95_gdi_text_current_position.x <= nv3->pgraph.win95_gdi_text.point_d.x) + /* check if we need to go down a line */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.point_d.x) { - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w; + nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w - 1); + nv3->pgraph.win95_gdi_text_current_position.y++; } @@ -92,7 +97,6 @@ void nv3_render_text_1bpp(bool bit, nv3_grobj_t grobj) { return; } - } void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) @@ -100,8 +104,6 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) // reset when a position is submitted nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; - // is this clip or point? - /* Go through the bitmap that was sent, bit by bit. */ for (int32_t bit_num = 0; bit_num <= 31; bit_num++) { @@ -109,4 +111,77 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) nv3_render_text_1bpp(bit, grobj); } +} + +/* 2-colour 1bpp color-expanded text from [7-0] */ +void nv3_render_text_1bpp_2color(uint8_t byte, nv3_grobj_t grobj) +{ + for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + { + bool bit = (byte >> bit_num) & 0x01; + + uint16_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_out_e.w; + uint16_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + nv3->pgraph.win95_gdi_text.size_out_e.h; + + /* they send more data than they need */ + if (nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) + bit = false; + + // if it's a 0 bit we don't need to do anything + + uint32_t final_color; + + switch (nv3->nvbase.svga.bpp) + { + case 8: + final_color = (bit) ? (nv3->pgraph.win95_gdi_text.color1_e & 0xFF) : (nv3->pgraph.win95_gdi_text.color0_e & 0xFF); /* do we need to add anything? mul blend perhaps? */ + break; + case 16: + final_color = (bit) ? (nv3->pgraph.win95_gdi_text.color1_e & 0xFFFF) : (nv3->pgraph.win95_gdi_text.color0_e & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ + break; + case 32: + final_color = (bit) ? nv3->pgraph.win95_gdi_text.color1_e : nv3->pgraph.win95_gdi_text.color0_e; /* do we need to add anything? mul blend perhaps? */ + break; + } + + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color, grobj); + + /* increment the position - the bitmap is stored horizontally backward */ + nv3->pgraph.win95_gdi_text_current_position.x--; + + /* see if we need to go to the next line */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.point_e.x) + { + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_in_e.w - 1); + nv3->pgraph.win95_gdi_text_current_position.y++; + } + + /* check if we are in the clipping rectangle */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_e.left + || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_e.right + || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_e.top + || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_e.bottom) + { + return; + } + } + + +} + +void nv3_render_gdi_type_e(nv3_grobj_t grobj, uint32_t param) +{ + // reset when a position is submitted + nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; + + /* we have to interpret every bit in reverse order but in the right bit order */ + uint8_t byte0 = ((param & 0xFF000000) >> 24); + uint8_t byte1 = ((param & 0xFF0000) >> 16); + uint8_t byte2 = ((param & 0xFF00) >> 8); + uint8_t byte3 = (param & 0xFF); + + nv3_render_text_1bpp_2color(byte0, grobj); + nv3_render_text_1bpp_2color(byte1, grobj); + nv3_render_text_1bpp_2color(byte2, grobj); + nv3_render_text_1bpp_2color(byte3, grobj); } \ No newline at end of file From 8b6185eeb19021b37c70f8d6c9c4560d0c10d8f6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 25 Mar 2025 20:38:57 +0000 Subject: [PATCH 145/274] make 15bpp actualyl 15bpp --- src/video/nv/nv3/classes/nv3_class_011_image.c | 1 + src/video/nv/nv3/nv3_core.c | 2 +- src/video/nv/nv3/render/nv3_render_blit.c | 1 + src/video/nv/nv3/render/nv3_render_core.c | 2 ++ src/video/nv/nv3/render/nv3_render_primitives.c | 12 +++++------- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 8dee40a21..b05013f5a 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -102,6 +102,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; //2pixels packed into one param + case 15: case 16: pixel1 = (param) & 0xFFFF; nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index b1d96f8d9..5016329a9 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -519,7 +519,7 @@ void nv3_recalc_timings(svga_t* svga) } else { - svga->bpp = 16; // HACK: DO NOT change this + svga->bpp = 15; // HACK: DO NOT change this svga->lowres = 0; svga->render = svga_render_15bpp_highres; } diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index ce836520b..539871884 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -56,6 +56,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) } } break; + case 15: case 16: //16bpp for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) { diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 7ef08e665..d1563cd76 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -227,6 +227,7 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro { case 8: break; + case 15: case 16: vram_x = position.x << 1; break; @@ -375,6 +376,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; break; + case 15: case 16: uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 1; diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 6190040a5..4695d05b7 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -65,6 +65,7 @@ void nv3_render_text_1bpp(bool bit, nv3_grobj_t grobj) case 8: final_color = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ break; + case 15: case 16: final_color = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ break; @@ -114,7 +115,7 @@ void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) } /* 2-colour 1bpp color-expanded text from [7-0] */ -void nv3_render_text_1bpp_2color(uint8_t byte, nv3_grobj_t grobj) +void nv3_render_text_1bpp_2color(uint32_t byte, nv3_grobj_t grobj) { for (int32_t bit_num = 0; bit_num <= 7; bit_num++) { @@ -123,10 +124,6 @@ void nv3_render_text_1bpp_2color(uint8_t byte, nv3_grobj_t grobj) uint16_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_out_e.w; uint16_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + nv3->pgraph.win95_gdi_text.size_out_e.h; - /* they send more data than they need */ - if (nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) - bit = false; - // if it's a 0 bit we don't need to do anything uint32_t final_color; @@ -136,6 +133,7 @@ void nv3_render_text_1bpp_2color(uint8_t byte, nv3_grobj_t grobj) case 8: final_color = (bit) ? (nv3->pgraph.win95_gdi_text.color1_e & 0xFF) : (nv3->pgraph.win95_gdi_text.color0_e & 0xFF); /* do we need to add anything? mul blend perhaps? */ break; + case 15: case 16: final_color = (bit) ? (nv3->pgraph.win95_gdi_text.color1_e & 0xFFFF) : (nv3->pgraph.win95_gdi_text.color0_e & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ break; @@ -143,7 +141,7 @@ void nv3_render_text_1bpp_2color(uint8_t byte, nv3_grobj_t grobj) final_color = (bit) ? nv3->pgraph.win95_gdi_text.color1_e : nv3->pgraph.win95_gdi_text.color0_e; /* do we need to add anything? mul blend perhaps? */ break; } - + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color, grobj); /* increment the position - the bitmap is stored horizontally backward */ @@ -152,7 +150,7 @@ void nv3_render_text_1bpp_2color(uint8_t byte, nv3_grobj_t grobj) /* see if we need to go to the next line */ if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.point_e.x) { - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_in_e.w - 1); + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_out_e.w - 1); nv3->pgraph.win95_gdi_text_current_position.y++; } From 64b16a43a1f9b4faf87c72387e69b9b854a098e8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 26 Mar 2025 01:43:46 +0000 Subject: [PATCH 146/274] Fix 32bpp bsod by actually creating framebuffer mappings. Don't remap memory if it's 0 (prevents trashing the low/real-mode memory map), general code simplification (some things were enabled 3 times what --- doc/nvidia_notes/status.xlsx | Bin 15607 -> 15648 bytes src/include/86box/nv/vid_nv.h | 1 + src/include/86box/nv/vid_nv3.h | 18 +- .../classes/nv3_class_01c_image_in_memory.c | 2 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 8 +- src/video/nv/nv3/nv3_core.c | 163 ++++++++++++------ src/video/nv/nv3/nv3_core_config.c | 8 +- src/video/nv/nv3/subsystems/nv3_pfb.c | 6 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- 9 files changed, 140 insertions(+), 68 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index e23fe6c7248b0bed60a1a932a22f5bf1d20bfb23..c050432b51bc3ae5023ac7204abcea8ad1e97540 100644 GIT binary patch delta 3970 zcmZ9PXE5At+s1cStX>wYg@_i>79p(O>mq9OE;_-g5&ohRC2WWq5-p;)a1%93^xmQ^ zB5Jgi=)B20@67!^&-vk+^P1zBIX@h8&h@)a0`s0#tw8Y|^u@m0Vtzn5f$(+zxHHW# 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method_id, nv3_ramin_context_t switch (info_notification_target) { case NV3_NOTIFICATION_TARGET_NVM: - svga_writel_linear(final_address, (notify.nanoseconds & 0xFFFFFFFF), nv3); - svga_writel_linear(final_address + 4, (notify.nanoseconds >> 32), nv3); - svga_writel_linear(final_address + 8, notify.info32, nv3); - svga_writel_linear(final_address + 0x0C, (notify.info16 | notify.status), nv3); + svga_writel_linear(final_address, (notify.nanoseconds & 0xFFFFFFFF), &nv3->nvbase.svga); + svga_writel_linear(final_address + 4, (notify.nanoseconds >> 32), &nv3->nvbase.svga); + svga_writel_linear(final_address + 8, notify.info32, &nv3->nvbase.svga); + svga_writel_linear(final_address + 0x0C, (notify.info16 | notify.status), &nv3->nvbase.svga); break; case NV3_NOTIFICATION_TARGET_PCI: case NV3_NOTIFICATION_TARGET_AGP: diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 5016329a9..09d8e093a 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -129,9 +129,6 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) ret = nv3_mmio_arbitrate_read(addr); - // This may get around the riva shredding its own cache - //nv3_pfifo_cache0_pull(); - //nv3_pfifo_cache1_pull(); return ret; @@ -261,7 +258,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) // 66Mhz FSB capable case PCI_REG_COMMAND_L: - ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L]; // we actually respond to the fucking + ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L] ; // we actually respond to the fucking break; case PCI_REG_COMMAND_H: @@ -396,6 +393,11 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) // actually update the mappings nv3_update_mappings(); break; + case PCI_REG_COMMAND_H: + nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] = val; + // actually update the mappings + nv3_update_mappings(); + break; // pci status register case PCI_REG_STATUS_L: nv3->pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE); @@ -736,13 +738,57 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) } +/* DFB, sets up a dumb framebuffer */ +uint8_t nv3_dfb_read8(uint32_t addr, void* priv) +{ + addr &= (nv3->nvbase.svga.vram_mask); + return nv3->nvbase.svga.vram[addr]; +} + +uint16_t nv3_dfb_read16(uint32_t addr, void* priv) +{ + addr &= (nv3->nvbase.svga.vram_mask); + return (nv3->nvbase.svga.vram[addr + 1] << 8) | nv3->nvbase.svga.vram[addr]; +} + +uint32_t nv3_dfb_read32(uint32_t addr, void* priv) +{ + addr &= (nv3->nvbase.svga.vram_mask); + return (nv3->nvbase.svga.vram[addr + 3] << 24) | (nv3->nvbase.svga.vram[addr + 2] << 16) + + (nv3->nvbase.svga.vram[addr + 1] << 8) | nv3->nvbase.svga.vram[addr]; +} + +void nv3_dfb_write8(uint32_t addr, uint8_t val, void* priv) +{ + addr &= (nv3->nvbase.svga.vram_mask); + nv3->nvbase.svga.vram[addr] = val; +} + +void nv3_dfb_write16(uint32_t addr, uint16_t val, void* priv) +{ + addr &= (nv3->nvbase.svga.vram_mask); + nv3->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; + nv3->nvbase.svga.vram[addr] = (val) & 0xFF; +} + +void nv3_dfb_write32(uint32_t addr, uint32_t val, void* priv) +{ + addr &= (nv3->nvbase.svga.vram_mask); + nv3->nvbase.svga.vram[addr + 3] = (val >> 24) & 0xFF; + nv3->nvbase.svga.vram[addr + 2] = (val >> 16) & 0xFF; + nv3->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; + nv3->nvbase.svga.vram[addr] = (val) & 0xFF; +} + +/* Cursor shit */ void nv3_draw_cursor(svga_t* svga, int32_t drawline) { // sanity check if (!nv3) return; - // this is a 2kb bitmap in vram...somewhere... + // On windows, this shows up using NV_IMAGE_IN_MEMORY. + // Do we need to emulate it? nv_log("nv3_draw_cursor drawline=0x%04x", drawline); } @@ -829,25 +875,26 @@ void nv3_init_mappings_svga() { nv_log("Initialising SVGA core memory mapping\n"); + // setup the svga mappings - mem_mapping_set(&nv3->nvbase.framebuffer_mapping, 0, 0, - svga_read_linear, - svga_readw_linear, - svga_readl_linear, - svga_write_linear, - svga_writew_linear, - svga_writel_linear, - NULL, 0, &nv3->nvbase.svga); + mem_mapping_add(&nv3->nvbase.framebuffer_mapping, 0, 0, + nv3_dfb_read8, + nv3_dfb_read16, + nv3_dfb_read32, + nv3_dfb_write8, + nv3_dfb_write16, + nv3_dfb_write32, + nv3->nvbase.svga.vram, 0, &nv3->nvbase.svga); // the SVGA/LFB mapping is also mirrored - mem_mapping_set(&nv3->nvbase.framebuffer_mapping_mirror, 0, 0, - svga_read_linear, - svga_readw_linear, - svga_readl_linear, - svga_write_linear, - svga_writew_linear, - svga_writel_linear, - NULL, 0, &nv3->nvbase.svga); + mem_mapping_add(&nv3->nvbase.framebuffer_mapping_mirror, 0, 0, + nv3_dfb_read8, + nv3_dfb_read16, + nv3_dfb_read32, + nv3_dfb_write8, + nv3_dfb_write16, + nv3_dfb_write32, + nv3->nvbase.svga.vram, 0, &nv3->nvbase.svga); io_sethandler(0x03c0, 0x0020, nv3_svga_in, NULL, NULL, @@ -885,6 +932,12 @@ void nv3_update_mappings() nv3_svga_out, NULL, NULL, nv3); + if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM) + { + nv_log("The memory was turned off, not much is going to happen.\n"); + return; + } + // turn off bar0 and bar1 by defualt mem_mapping_disable(&nv3->nvbase.mmio_mapping); mem_mapping_disable(&nv3->nvbase.framebuffer_mapping); @@ -892,50 +945,56 @@ void nv3_update_mappings() mem_mapping_disable(&nv3->nvbase.ramin_mapping); mem_mapping_disable(&nv3->nvbase.ramin_mapping_mirror); - if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM) - { - nv_log("The memory was turned off, not much is going to happen.\n"); - return; - } - - mem_mapping_enable(&nv3->nvbase.mmio_mapping); - mem_mapping_enable(&nv3->nvbase.framebuffer_mapping); - mem_mapping_enable(&nv3->nvbase.framebuffer_mapping_mirror); - mem_mapping_enable(&nv3->nvbase.ramin_mapping); - mem_mapping_enable(&nv3->nvbase.ramin_mapping_mirror); - - // first map bar0 + // Setup BAR0 (MMIO) nv_log("BAR0 (MMIO Base) = 0x%08x\n", nv3->nvbase.bar0_mmio_base); - //mem_mapping_enable(&nv3->nvbase.mmio_mapping); // should have no effect if already enabled - - mem_mapping_set_addr(&nv3->nvbase.mmio_mapping, nv3->nvbase.bar0_mmio_base, NV3_MMIO_SIZE); - + + if (nv3->nvbase.bar0_mmio_base) + mem_mapping_set_addr(&nv3->nvbase.mmio_mapping, nv3->nvbase.bar0_mmio_base, NV3_MMIO_SIZE); // if this breaks anything, remove it - // skeptical that 0 is used to disable... nv_log("BAR1 (Linear Framebuffer / NV_USER Base & RAMIN) = 0x%08x\n", nv3->nvbase.bar1_lfb_base); // this is likely mirrored // 4x on 2mb cards // 2x on 4mb cards // and not at all on 8mb - mem_mapping_enable(&nv3->nvbase.framebuffer_mapping); - mem_mapping_enable(&nv3->nvbase.framebuffer_mapping_mirror); - mem_mapping_enable(&nv3->nvbase.ramin_mapping); - mem_mapping_enable(&nv3->nvbase.ramin_mapping_mirror); - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_MMIO_SIZE); + /* TODO: 2MB */ + // 4MB VRAM memory map: // LFB_BASE+VRAM_SIZE=RAMIN Mirror(?) 0x1400000 (VERIFY PCBOX) // LFB_BASE+VRAM_SIZE*2=LFB Mirror(?) 0x1800000 // LFB_BASE+VRAM_SIZE*3=Definitely RAMIN (then it ends, the total ram space is 16mb) 0x1C00000 - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_MIRROR_START, NV3_LFB_MAPPING_SIZE); - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_2NDHALF_START, NV3_LFB_MAPPING_SIZE); - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_START, NV3_LFB_MAPPING_SIZE); - // TODO: RAMIN and its mirror + // 8MB VRAM memory map: + // LFB_BASE->LFB_BASE+VRAM_SIZE=LFB + // What is in 800000-c00000? + // LFB_BASE+0xC00000 = RAMIN + + if (nv3->nvbase.bar1_lfb_base) + { + if (nv3->nvbase.vram_amount == NV3_VRAM_SIZE_4MB) + { + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_VRAM_SIZE_4MB); + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_MIRROR_START, NV3_LFB_MAPPING_SIZE); + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_MIRROR_START, NV3_VRAM_SIZE_4MB); + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_START, NV3_LFB_MAPPING_SIZE); + } + else if (nv3->nvbase.vram_amount == NV3_VRAM_SIZE_8MB) + { + // we don't need this one in the case of 8mb, because regular mapping is 8mb + mem_mapping_disable(&nv3->nvbase.ramin_mapping_mirror); + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_VRAM_SIZE_8MB); + mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_MIRROR_START, NV3_LFB_MAPPING_SIZE); + mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_START, NV3_LFB_MAPPING_SIZE); + } + else + { + fatal("NV3-2MB not implemented yet (It never existed anyway)"); + } + } // Did we change the banked SVGA mode? switch (nv3->nvbase.svga.gdcreg[0x06] & 0x0c) @@ -977,7 +1036,7 @@ void* nv3_init(const device_t *info) // Allows nv_log to be used for multiple nvidia devices nv_log_set_device(nv3->nvbase.log); #endif - nv_log("initialising core\n"); + nv_log("Initialising core\n"); // Figure out which vbios the user selected const char* vbios_id = device_get_config_bios("vbios"); @@ -1001,7 +1060,7 @@ void* nv3_init(const device_t *info) nv_log("Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); // set the vram amount and gpu revision - uint32_t vram_amount = device_get_config_int("vram_size"); + nv3->nvbase.vram_amount = device_get_config_int("vram_size"); nv3->nvbase.gpu_revision = device_get_config_int("chip_revision"); // set up the bus and start setting up SVGA core @@ -1011,7 +1070,7 @@ void* nv3_init(const device_t *info) pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, vram_amount, + svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); } else if (nv3->nvbase.bus_generation == nv_bus_agp_1x) @@ -1020,7 +1079,7 @@ void* nv3_init(const device_t *info) pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, vram_amount, + svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); } diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index e8beb6df7..256ae9dd9 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -140,23 +140,23 @@ const device_config_t nv3_config[] = .name = "vram_size", .description = "VRAM Size", .type = CONFIG_SELECTION, - .default_int = VRAM_SIZE_4MB, + .default_int = NV3_VRAM_SIZE_4MB, .selection = { #ifndef RELEASE_BUILD // This never existed officially but was planned. Debug only { .description = "2 MB (Never officially sold)", - .value = VRAM_SIZE_2MB, + .value = NV3_VRAM_SIZE_2MB, }, #endif { .description = "4 MB", - .value = VRAM_SIZE_4MB, + .value = NV3_VRAM_SIZE_4MB, }, { .description = "8 MB", - .value = VRAM_SIZE_8MB, + .value = NV3_VRAM_SIZE_8MB, }, } diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 644d4090d..0dae5ab39 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -57,9 +57,13 @@ void nv3_pfb_init() | (NV3_PFB_BOOT_RAM_DATA_TWIDDLE_OFF << NV3_PFB_BOOT_RAM_DATA_TWIDDLE) | (NV3_PFB_BOOT_RAM_BANKS_4 << NV3_PFB_BOOT_RAM_BANKS) | (NV3_PFB_BOOT_RAM_WIDTH_128 << NV3_PFB_BOOT_RAM_WIDTH) - | (NV3_PFB_BOOT_RAM_AMOUNT_4MB << NV3_PFB_BOOT_RAM_AMOUNT) ); + if (nv3->nvbase.vram_amount == NV3_VRAM_SIZE_4MB) + nv3->pfb.boot |= (NV3_PFB_BOOT_RAM_AMOUNT_4MB << NV3_PFB_BOOT_RAM_AMOUNT); + else + nv3->pfb.boot |= (NV3_PFB_BOOT_RAM_AMOUNT_8MB << NV3_PFB_BOOT_RAM_AMOUNT); + nv_log("Done\n"); } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index b782f2b56..ef6af049e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -218,7 +218,7 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = nv3->pfifo.cache1_settings.dma_state; break; case NV3_PFIFO_CACHE1_DMA_CONFIG_1: - ret = nv3->pfifo.cache1_settings.dma_length & (VRAM_SIZE_8MB) - 4; //MAX vram size + ret = nv3->pfifo.cache1_settings.dma_length & (NV3_VRAM_SIZE_8MB) - 4; //MAX vram size break; case NV3_PFIFO_CACHE1_DMA_CONFIG_2: ret = nv3->pfifo.cache1_settings.dma_address; From ce852caee13e778c34681b314757df3fcfde3353 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 26 Mar 2025 16:22:06 +0000 Subject: [PATCH 147/274] Clip images. Gate some ridiculous logging beyond ENABLE_NV_LOG_ULTRA. 2MB was real for at least one card, as well. --- .../nv3_class_005_clipping_rectangle.c | 4 +-- .../nv/nv3/classes/nv3_class_011_image.c | 17 ++++++----- src/video/nv/nv3/nv3_core.c | 29 +++++++++++++++---- src/video/nv/nv3/nv3_core_config.c | 5 ++-- src/video/nv/nv3/render/nv3_render_core.c | 5 ++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 7 +++++ 6 files changed, 48 insertions(+), 19 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 10136feac..5ad674b44 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -34,12 +34,12 @@ void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_CLIP_POSITION: nv3->pgraph.clip_start.x = (param >> 16) & 0xFFFF; nv3->pgraph.clip_start.y = (param) & 0xFFFF; - nv_log("Clip Position: %d,%d", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + nv_log("Clip Position: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; case NV3_CLIP_SIZE: nv3->pgraph.clip_size.x = (param >> 16) & 0xFFFF; nv3->pgraph.clip_size.y = (param) & 0xFFFF; - nv_log("Clip Size: %d,%d", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + nv_log("Clip Size: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index b05013f5a..c6aa1aceb 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -72,6 +72,9 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; + /* Some extra data is sent as padding, we need to clip it off using size_out */ + + uint16_t clip_x = nv3->pgraph.image_current_position.x + nv3->pgraph.image.size.w; /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) @@ -81,22 +84,22 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ //pixel3 pixel3 = param & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel2 = (param >> 8) & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel1 = (param >> 16) & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (param >> 24) & 0xFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -105,12 +108,12 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case 15: case 16: pixel1 = (param) & 0xFFFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (param >> 16) & 0xFFFF; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -118,7 +121,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // just one pixel in 32bpp case 32: pixel0 = param; - nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 09d8e093a..d9ca57ff0 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -68,7 +68,9 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3); - nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%02x\n", addr, ret); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + #endif return ret; } @@ -94,8 +96,9 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); + #ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - + #endif return ret; } @@ -121,7 +124,9 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%08x\n", addr, ret); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + #endif return ret; } @@ -146,7 +151,10 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; + #ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + #endif + nv3_svga_out(real_address, val & 0xFF, nv3); return; @@ -172,7 +180,10 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%04x\n", addr, val); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + #endif + nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -199,7 +210,9 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%08x\n", addr, val); + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + #endif nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -992,7 +1005,7 @@ void nv3_update_mappings() } else { - fatal("NV3-2MB not implemented yet (It never existed anyway)"); + fatal("NV3 2MB not implemented yet"); } } @@ -1038,6 +1051,10 @@ void* nv3_init(const device_t *info) #endif nv_log("Initialising core\n"); +#ifdef ENABLE_NV_LOG_ULTRA + nv_log("ULTRA LOGGING enabled"); +#endif + // Figure out which vbios the user selected const char* vbios_id = device_get_config_bios("vbios"); const char* vbios_file = ""; diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index 256ae9dd9..a229ca3c7 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -144,9 +144,10 @@ const device_config_t nv3_config[] = .selection = { #ifndef RELEASE_BUILD - // This never existed officially but was planned. Debug only + // I thought this was never released, but it seems that at least one was released: + // The card was called the "NEC G7AGK" { - .description = "2 MB (Never officially sold)", + .description = "2 MB", .value = NV3_VRAM_SIZE_2MB, }, #endif diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index d1563cd76..7ae00efd6 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -219,6 +219,7 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj) { uint32_t vram_x = position.x; + uint32_t vram_y = position.y; uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; @@ -236,7 +237,7 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro break; } - uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * position.y) + nv3->pgraph.boffset[current_buffer]; + uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * vram_y) + nv3->pgraph.boffset[current_buffer]; pixel_addr_vram &= nv3->nvbase.svga.vram_mask; @@ -313,7 +314,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob return; } - /* TODO: Chroma Key, Pattern, Plane Mask...*/ + /* TODO: Plane Mask...*/ if (!nv3_render_chroma_test(grobj, color)) return; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index ef6af049e..55ec21e19 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -740,7 +740,9 @@ void nv3_pfifo_cache0_pull() nv3->pfifo.cache0_settings.get_address ^= 0x04; #ifndef RELEASE_BUILD + #ifdef ENABLE_NV_LOG_ULTRA nv_log("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n"); + #endif nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; @@ -936,6 +938,11 @@ void nv3_pfifo_cache1_pull() nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; #ifndef RELEASE_BUILD + + #ifdef ENABLE_NV_LOG_ULTRA + nv_log("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n"); + #endif + nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; nv3_debug_ramin_print_context_info(current_param, context_structure); From 2829669740d7e61689317de86fb9735d8f123be1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 16:23:18 +0000 Subject: [PATCH 148/274] Redirect all PRMCIO/PRMVIO writes to SVGA subsystem, not just a few random ones. --- doc/nvidia_notes/status.xlsx | Bin 15648 -> 15813 bytes src/include/86box/nv/vid_nv3.h | 7 ++++--- src/video/nv/nv3/nv3_core.c | 10 +++------- src/video/nv/nv3/subsystems/nv3_pmc.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_ptimer.c | 2 +- src/video/nv/nv3/subsystems/nv3_user.c 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zRC#_TKx>@>3yd@Fqaqldge-haC8K$qLP z)z{Ho=?+P4zYsiIzGecxCYy zPI@p$1IWn~lI?6{3Q}r8wbh&yp80v?A|^{Ei`>i1-K4oU+H#s4XN09%Q z70fre%WFOPncx5urEYHg-ZjK_>A_m3+kR)fMXYoTDsmKU{52`J27)De`iY9Q)w(5n z&sW#U>F$8=Zk%Jai~Y%qy5hV64gBB%_)hxD9s#+r?V)zb%xW!HeI+>IgO2Riu(z>1 zual=wi}JxvY}}c2sM5(p6QlaCxdj}NF<*XgM`3c#b1nirYVS!UZSlHW z)#`9*FUhQps z6%M_|=Hb|i$-_mpd9jJAZh3v=j&B00T@~&g|BQ|CFi`?9C&52K8KPWZBa(m2 zaT3J%Jy9I;eSW~MvSi)!--#{#d#ir{&z*kXNfVA z{inqLUlatwieDF_Ci_oS@h@H%PbSVp{x`oA;XoieFbIVEFZgV=@x>d9i^D-`TLu6C diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 40aa94ce2..2efca64b3 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 22 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 26 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -671,9 +671,10 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers #define NV3_PGRAPH_REAL_END 0x5C1FFF +// PRMCIO is redirected to SVGA subsystem #define NV3_PRMCIO_START 0x601000 -// Following four are CRTC+I2C access registers -// and get redirected to VGA + + #define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO 0x6013B4 // Current CRTC Register Index - Monochrome #define NV3_PRMCIO_CRTC_REGISTER_CUR_MONO 0x6013B5 // Currently Selected CRTC Register - Monochrome #define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR 0x6013D4 // Current CRTC Register Index - Colour diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index d9ca57ff0..f8e98689d 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -41,13 +41,9 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); bool nv3_is_svga_redirect_address(uint32_t addr) { - return (addr >= NV3_PRMVIO_START - && addr <= NV3_PRMVIO_END - || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR - || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR - || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_MONO - || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO - || (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END)); + return (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) // VGA + || (addr >= NV3_PRMCIO_START && addr <= NV3_PRMCIO_END) // CRTC + || (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END); // Legacy RAMDAC support(?) } // All MMIO regs are 32-bit i believe internally diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 24f0ad44a..de1c21f24 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -88,11 +88,11 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) if (nv3->pfifo.interrupt_status & nv3->pfifo.interrupt_enable) new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO); - // PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...clean this up once we verify it + // PFB interrupt is VBLANK PGRAPH interrupt...what nvidia... if (nv3->pgraph.interrupt_status_0 & (1 << 8) && nv3->pgraph.interrupt_enable_0 & (1 << 8)) new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB); - + if (nv3->pgraph.interrupt_status_0 & ~(1 << 8) && nv3->pgraph.interrupt_enable_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0); diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index b5c278387..1e3347beb 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -84,7 +84,7 @@ void nv3_ptimer_tick(double real_time) // Check if the alarm has actually triggered... if (nv3->ptimer.time >= nv3->ptimer.alarm) { - nv_log("PTIMER alarm interrupt fired because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); + nv_log("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM); } } diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index a6c9a588c..cb2c96fb4 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -37,7 +37,7 @@ uint32_t nv3_user_read(uint32_t address) //todo: print out the subchannel uint8_t method_offset = (address & 0x1FFC); -#ifndef RELEASE_BUILD +#ifdef ENABLE_NV_LOG_ULTRA uint8_t channel = (address - NV3_USER_START) / 0x10000; uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL; From cc68dcecc481632739451fb8cde2de43692a87db Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 16:52:21 +0000 Subject: [PATCH 149/274] general minor code cleanups. fix logs, send vram writes (0x1000000-0x17fffff), if these ever happen, to DFB, and more --- CMakeLists.txt | 7 +++++ src/include/86box/nv/vid_nv3.h | 9 +++---- .../nv3/classes/nv3_class_001_beta_factor.c | 4 ++- src/video/nv/nv3/classes/nv3_class_002_rop.c | 3 ++- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 2 +- .../nv/nv3/classes/nv3_class_004_plane_mask.c | 2 +- .../nv3_class_005_clipping_rectangle.c | 6 ++--- .../nv/nv3/classes/nv3_class_006_pattern.c | 2 +- .../nv/nv3/classes/nv3_class_007_rectangle.c | 4 +-- .../nv/nv3/classes/nv3_class_008_point.c | 2 +- src/video/nv/nv3/classes/nv3_class_009_line.c | 2 +- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 2 +- .../nv/nv3/classes/nv3_class_00b_triangle.c | 2 +- .../classes/nv3_class_00c_win95_gdi_text.c | 26 ++++++++++++++----- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 2 +- .../nv3_class_00e_scaled_image_from_mem.c | 2 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- .../nv/nv3/classes/nv3_class_011_image.c | 9 ++++--- .../nv/nv3/classes/nv3_class_012_bitmap.c | 2 +- .../classes/nv3_class_014_transfer2memory.c | 2 +- .../nv3_class_015_stretched_image_from_cpu.c | 2 +- .../nv3_class_017_d3d5_tri_zeta_buffer.c | 2 +- .../classes/nv3_class_018_point_zeta_buffer.c | 2 +- .../classes/nv3_class_01c_image_in_memory.c | 9 +++---- src/video/nv/nv3/nv3_core.c | 23 ++++++++-------- src/video/nv/nv3/nv3_core_arbiter.c | 11 +++----- src/video/nv/nv3/subsystems/nv3_pfb.c | 4 +++ src/video/nv/nv3/subsystems/nv3_pramin.c | 3 +-- src/video/nv/nv3/subsystems/nv3_user.c | 5 ++-- src/video/nv/nv_base.c | 8 ++++-- 30 files changed, 93 insertions(+), 68 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index ac7591dd8..1adcf4740 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -137,12 +137,18 @@ option(GDBSTUB "Enable GDB stub server for debugging" option(DEV_BRANCH "Development branch" OFF) option(DISCORD "Discord Rich Presence support" ON) option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) +# Remove when merged, should just be -D option(NV_LOG "NVidia RIVA 128 debug logging" OFF) +option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" OFF) if (NV_LOG) add_compile_definitions(ENABLE_NV_LOG) endif() +if (NV_LOG_ULTRA) + add_compile_definitions(ENABLE_NV_LOG_ULTRA) +endif() + if((ARCH STREQUAL "arm64") OR (ARCH STREQUAL "arm")) set(NEW_DYNAREC ON) else() @@ -193,6 +199,7 @@ cmake_dependent_option(PCL "Generic PCL5e Printer" cmake_dependent_option(SIO_DETECT "Super I/O Detection Helper" ON "DEV_BRANCH" OFF) cmake_dependent_option(WACOM "Wacom Input Devices" ON "DEV_BRANCH" OFF) cmake_dependent_option(XL24 "ATI VGA Wonder XL24 (ATI-28800-6)" ON "DEV_BRANCH" OFF) +cmake_dependent_option(NV3 "NVidia RIVA 128/128ZX (NV3/NV3T)" ON "DEV_BRANCH" OFF) # Ditto but for Qt if(QT) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 2efca64b3..ed55e050d 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1454,7 +1454,7 @@ void nv3_speed_changed(void *priv); void nv3_recalc_timings(svga_t* svga); void nv3_force_redraw(void* priv); -// Memory Mapping +/* BAR0 GPU MMIO read */ void nv3_update_mappings(); // Update memory mappings uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO @@ -1544,10 +1544,7 @@ uint32_t nv3_pvideo_read(uint32_t address); void nv3_pvideo_write(uint32_t address, uint32_t value); uint32_t nv3_pramdac_read(uint32_t address); void nv3_pramdac_write(uint32_t address, uint32_t value); -uint32_t nv3_vram_read(uint32_t address); -void nv3_vram_write(uint32_t address, uint32_t value); -#define nv3_nvm_read nv3_vram_read -#define nv3_nvm_write nv3_vram_write + uint32_t nv3_user_read(uint32_t address); void nv3_user_write(uint32_t address, uint32_t value); #define nv3_object_submit_start nv3_user_read @@ -1641,5 +1638,5 @@ void nv3_ptimer_tick(double real_time); // NV3 PVIDEO void nv3_pvideo_init(); -// NV3 PMEDIA (Mediaport) +// NV3 PME (Mediaport) void nv3_pmedia_init(); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 1450acbeb..694e49085 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -39,9 +39,11 @@ void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ else nv3->pgraph.beta_factor = param & 0x7F800000; + nv_log("Method Execution: Beta Factor = %02x", nv3->pgraph.beta_factor); + break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index 1052da80d..8c3580f4f 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -34,9 +34,10 @@ void nv3_class_002_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { case NV3_ROP_SET_ROP: nv3->pgraph.rop = param & 0xFF; + nv_log("Method Execution: ROP = %02x\n", nv3->pgraph.rop); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index bf24f420f..54d52e197 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -38,7 +38,7 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.chroma_key = nv3_render_to_chroma(expanded_color); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 9c9bced95..5789b8e11 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -33,7 +33,7 @@ void nv3_class_004_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 5ad674b44..7bfbd4dd6 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -34,15 +34,15 @@ void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_CLIP_POSITION: nv3->pgraph.clip_start.x = (param >> 16) & 0xFFFF; nv3->pgraph.clip_start.y = (param) & 0xFFFF; - nv_log("Clip Position: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + nv_log("Method Execution: Clip Position: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; case NV3_CLIP_SIZE: nv3->pgraph.clip_size.x = (param >> 16) & 0xFFFF; nv3->pgraph.clip_size.y = (param) & 0xFFFF; - nv_log("Clip Size: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); + nv_log("Method Execution: Clip Size: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index 36ce70e19..c1fba2309 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -72,7 +72,7 @@ void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index fcf31132f..24193f8d5 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -47,7 +47,7 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.rectangle.size[index].w = param & 0xFFFF; nv3->pgraph.rectangle.size[index].h = (param >> 16) & 0xFFFF; - nv_log("Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h, nv3->pgraph.rectangle.color); + nv_log("Method Execution: Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h, nv3->pgraph.rectangle.color); nv3_render_rect(nv3->pgraph.rectangle.position[index], nv3->pgraph.rectangle.size[index], nv3->pgraph.rectangle.color, grobj); } @@ -56,7 +56,7 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.rectangle.position[index].x = param & 0xFFFF; nv3->pgraph.rectangle.position[index].y = (param >> 16) & 0xFFFF; - nv_log("Rect%d Position=%d,%d\n", index, nv3->pgraph.rectangle.position[index].x, nv3->pgraph.rectangle.position[index].y); + nv_log("Method Execution: Rect%d Position=%d,%d\n", index, nv3->pgraph.rectangle.position[index].x, nv3->pgraph.rectangle.position[index].y); } return; diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index 4ffffba92..ec40419df 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -33,7 +33,7 @@ void nv3_class_008_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index edb432884..c0667af47 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -33,7 +33,7 @@ void nv3_class_009_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index fc7dcc879..839b4768c 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -34,7 +34,7 @@ void nv3_class_00a_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index 08a205ac2..a790eabc3 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -33,7 +33,7 @@ void nv3_class_00b_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 8d126e6cc..38969a5a0 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -37,32 +37,39 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* NOTE: This method is used by the GDI driver as part of the notification engine. */ case NV3_W95TXT_A_COLOR: nv3->pgraph.win95_gdi_text.color_a = param; + nv_log("Method Execution: GDI-A Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; /* Type B and C not implemented YET, as they are not used by NT GDI driver */ case NV3_W95TXT_D_CLIP_TOPLEFT: nv3->pgraph.win95_gdi_text.clip_d.left = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_d.top = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-A Clip Left,Top %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); break; case NV3_W95TXT_D_CLIP_BOTTOMRIGHT: nv3->pgraph.win95_gdi_text.clip_d.right = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_d.bottom = ((param >> 16) & 0xFFFF); /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ + nv_log("Method Execution: GDI-A Clip Right,Bottom %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); break; case NV3_W95TXT_D_CLIP_COLOR: nv3->pgraph.win95_gdi_text.color1_d = param; + nv_log("Method Execution: GDI-D Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; case NV3_W95TXT_D_CLIP_SIZE_IN: nv3->pgraph.win95_gdi_text.size_in_d.w = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.size_in_d.h = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-D Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_d.w, nv3->pgraph.win95_gdi_text.size_in_d.h); break; case NV3_W95TXT_D_CLIP_SIZE_OUT: nv3->pgraph.win95_gdi_text.size_out_d.w = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.size_out_d.h = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-D Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_d.w, nv3->pgraph.win95_gdi_text.size_out_d.h); break; case NV3_W95TXT_D_CLIP_POSITION: nv3->pgraph.win95_gdi_text.point_d.x = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.point_d.y = ((param >> 16) & 0xFFFF); - + nv_log("Method Execution: GDI-D Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y); + /* small case*/ if (nv3->pgraph.win95_gdi_text.size_in_d.w < 0x0010) { @@ -90,17 +97,21 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; case NV3_W95TXT_E_CLIP_COLOR_0: nv3->pgraph.win95_gdi_text.color0_e = param; + nv_log("Method Execution: GDI-E Color0 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; case NV3_W95TXT_E_CLIP_COLOR_1: nv3->pgraph.win95_gdi_text.color1_e = param; + nv_log("Method Execution: GDI-E Color1 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; case NV3_W95TXT_E_CLIP_SIZE_IN: nv3->pgraph.win95_gdi_text.size_in_e.w = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.size_in_e.h = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-E Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_e.w, nv3->pgraph.win95_gdi_text.size_in_e.h); break; case NV3_W95TXT_E_CLIP_SIZE_OUT: nv3->pgraph.win95_gdi_text.size_out_e.w = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.size_out_e.h = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-E Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_e.w, nv3->pgraph.win95_gdi_text.size_out_e.h); break; case NV3_W95TXT_E_CLIP_POSITION: nv3->pgraph.win95_gdi_text.point_e.x = (param & 0xFFFF); @@ -110,8 +121,9 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ //nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_e.x + large_start); nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x; - nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_e.y); + nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_e.y; + nv_log("Method Execution: GDI-E Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y); break; default: /* Type A submission: these are the same things as rectangles */ @@ -125,7 +137,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.rect_a_size[index].w = param & 0xFFFF; nv3->pgraph.win95_gdi_text.rect_a_size[index].h = (param >> 16) & 0xFFFF; - nv_log("Rect GDI-A%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, + nv_log("Method Execution: Rect GDI-A%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, nv3->pgraph.win95_gdi_text.rect_a_size[index].h, nv3->pgraph.win95_gdi_text.color_a); nv3_render_rect(nv3->pgraph.win95_gdi_text.rect_a_position[index], @@ -136,7 +148,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.rect_a_position[index].x = param & 0xFFFF; nv3->pgraph.win95_gdi_text.rect_a_position[index].y = (param >> 16) & 0xFFFF; - nv_log("Rect GDI-A%d Position=%d,%d\n", index, + nv_log("Method Execution: Rect GDI-A%d Position=%d,%d\n", index, nv3->pgraph.win95_gdi_text.rect_a_position[index].x, nv3->pgraph.win95_gdi_text.rect_a_position[index].y); } return; @@ -149,7 +161,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.mono_color1_d[index] = param; /* Mammoth logger! */ - nv_log("Rect GDI-D%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", + nv_log("Method Execution: Rect GDI-D%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", index, param, nv3->pgraph.win95_gdi_text.size_in_d.w, nv3->pgraph.win95_gdi_text.size_in_d.h, nv3->pgraph.win95_gdi_text.size_out_d.w, nv3->pgraph.win95_gdi_text.size_out_d.h, nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y, @@ -167,7 +179,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.mono_color1_d[index] = param; /* Mammoth logger! */ - nv_log("Rect GDI-E%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", + nv_log("Method Execution: Rect GDI-E%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", index, param, nv3->pgraph.win95_gdi_text.size_in_e.w, nv3->pgraph.win95_gdi_text.size_in_e.h, nv3->pgraph.win95_gdi_text.size_out_e.w, nv3->pgraph.win95_gdi_text.size_out_e.h, nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y, @@ -178,7 +190,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ return; } - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index fa1f08811..06c5d93b6 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -33,7 +33,7 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index c4b68c34f..ea5db21ff 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -33,7 +33,7 @@ void nv3_class_00e_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 0f15e82d6..c07c600ee 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -49,7 +49,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index c6aa1aceb..42574bc30 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -49,17 +49,19 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_IMAGE_START_POSITION: nv3->pgraph.image.point.x = (param & 0xFFFF); nv3->pgraph.image.point.y = (param >> 16); - nv_log("Image Point=%d,%d", nv3->pgraph.image.point.x, nv3->pgraph.image.point.y); + nv_log("Method Execution: Image Point=%d,%d\n", nv3->pgraph.image.point.x, nv3->pgraph.image.point.y); break; /* Seems to allow scaling of the bitblt. */ case NV3_IMAGE_SIZE: nv3->pgraph.image.size.w = (param & 0xFFFF); nv3->pgraph.image.size.h = (param >> 16); + nv_log("Method Execution: Image Size (Clip)=%d,%d\n", nv3->pgraph.image.size.w, nv3->pgraph.image.size.h); break; case NV3_IMAGE_SIZE_IN: nv3->pgraph.image.size_in.w = (param & 0xFFFF); nv3->pgraph.image.size_in.h = (param >> 16); nv3->pgraph.image_current_position = nv3->pgraph.image.point; + nv_log("Method Execution: Image SizeIn=%d,%d\n", nv3->pgraph.image.size_in.w, nv3->pgraph.image.size_in.h); break; default: if (method_id >= NV3_IMAGE_COLOR_START && method_id <= NV3_IMAGE_COLOR_END) @@ -67,7 +69,8 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // shift left by 2 because it's 4 bits per si\e.. uint32_t pixel_slot = (method_id - NV3_IMAGE_COLOR_START) >> 2; uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - + nv_log("Method Execution: Pixel%d Colour%08x Format%x\n", pixel_slot, param, (grobj.grobj_0) & 0x07); + /* todo: a lot of stuff */ uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; @@ -130,7 +133,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } else { - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); } diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index bbbb6997d..799673391 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -34,7 +34,7 @@ void nv3_class_012_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index 47e4b0c32..a27538dcb 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -34,7 +34,7 @@ void nv3_class_014_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index f1c571943..d029dc080 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -33,7 +33,7 @@ void nv3_class_015_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index 838c64aa7..c4c7aa0cd 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -33,7 +33,7 @@ void nv3_class_017_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 904cac757..6a0632377 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -35,7 +35,7 @@ void nv3_class_018_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 5eee663f3..5d06ed678 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -61,7 +61,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.bpixel[src_buffer_id] = (real_format | NV3_BPIXEL_FORMAT_IS_VALID); - nv_log("Image in Memory BUF%d COLOR_FORMAT=0x%04x", src_buffer_id, param); + nv_log("Method Execution: Image in Memory BUF%d COLOR_FORMAT=0x%04x\n", src_buffer_id, param); break; /* DOn't log invalid */ @@ -70,20 +70,19 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; /* Pitch - length between scanlines */ case NV3_IMAGE_IN_MEMORY_PITCH: - nv3->pgraph.image_in_memory.pitch = param & 0x1FF0; nv3->pgraph.bpitch[src_buffer_id] = param & 0x1FF0; // 12:0 - nv_log("Image in Memory BUF%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); + nv_log("Method Execution: Image in Memory BUF%d PITCH=0x%04x\n", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); break; /* Byte offset in GPU VRAM of top left pixel (22:0) */ case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: nv3->pgraph.boffset[src_buffer_id] = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); - nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); + nv_log("Method Execution: Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x\n", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index f8e98689d..28c6edab5 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -92,9 +92,9 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); - #ifdef ENABLE_NV_LOG_ULTRA + //#ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - #endif + //#endif return ret; } @@ -120,9 +120,9 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - #ifdef ENABLE_NV_LOG_ULTRA + //#ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - #endif + //#endif return ret; } @@ -147,9 +147,9 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - #ifdef ENABLE_NV_LOG_ULTRA + //#ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - #endif + //#endif nv3_svga_out(real_address, val & 0xFF, nv3); @@ -176,9 +176,9 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - #ifdef ENABLE_NV_LOG_ULTRA + //#ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - #endif + //#endif nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -206,9 +206,9 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - #ifdef ENABLE_NV_LOG_ULTRA + //#ifdef ENABLE_NV_LOG_ULTRA nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - #endif + //#endif nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -842,7 +842,7 @@ void nv3_prom_write(uint32_t address, uint32_t value) // Initialise the MMIO mappings void nv3_init_mappings_mmio() { - nv_log("Initialising 32MB MMIO area\n"); + nv_log("Initialising MMIO mapping\n"); // 0x0 - 1000000: regs // 0x1000000-2000000 @@ -1107,6 +1107,7 @@ void* nv3_init(const device_t *info) nv3->pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM; // svga is done, so now initialise the real gpu + nv_log("Initialising GPU core...\n"); nv3_pextdev_init(); // Initialise Straps diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index e5e7ced6b..2bb3ef8b4 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -100,12 +100,12 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) ret = nv3_pramdac_read(address); else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) - ret = nv3_vram_read(address); + ret = nv3_dfb_read32(address & nv3->nvbase.svga.vram_mask, &nv3->nvbase.svga); else if (address >= NV3_USER_START && address <= NV3_USER_END) ret = nv3_user_read(address); else { - nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); + warning("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); return 0x00; } @@ -161,13 +161,13 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) nv3_pramdac_write(address, value); else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) - nv3_vram_write(address, value); + nv3_dfb_write32(address, value, &nv3->nvbase.svga); else if (address >= NV3_USER_START && address <= NV3_USER_END) nv3_user_write(address, value); //RAMIN is its own thing else { - nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); + warning("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); return; } } @@ -192,6 +192,3 @@ void nv3_palt_write(uint32_t address, uint32_t value) {}; // TODO: PGRAPH class registers uint32_t nv3_prmcio_read(uint32_t address) { return 0; }; void nv3_prmcio_write(uint32_t address, uint32_t value) {}; - -uint32_t nv3_vram_read(uint32_t address) { return 0; }; -void nv3_vram_write(uint32_t address, uint32_t value) {}; \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 0dae5ab39..0be3d14c8 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -187,6 +187,9 @@ void nv3_pfb_config0_write(uint32_t val) uint32_t new_pfb_vtotal = new_pfb_htotal * (3.0/4.0); uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; + + // This doesn't actually seem very useful + #ifdef ENABLE_NV_LOG_ULTRA nv_log("Framebuffer Config Change\n"); nv_log("Horizontal Size=%d pixels\n", new_pfb_htotal); nv_log("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); @@ -197,5 +200,6 @@ void nv3_pfb_config0_write(uint32_t val) nv_log("Bit Depth=16bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_32BPP) nv_log("Bit Depth=32bpp\n"); + #endif } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index b4858acca..2771d5d16 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -508,8 +508,7 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte nv_log("Context:\n"); nv_log("DMA Channel %d (0-7 valid)\n", context.channel); - nv_log("Class ID: as represented in ramin=%04x, Stupid 5 bit version (the actual id)=0x%04x (%s)\n", context.class_id, - context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); + nv_log("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); nv_log("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); #endif diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index cb2c96fb4..99091b5b7 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -37,12 +37,11 @@ uint32_t nv3_user_read(uint32_t address) //todo: print out the subchannel uint8_t method_offset = (address & 0x1FFC); -#ifdef ENABLE_NV_LOG_ULTRA uint8_t channel = (address - NV3_USER_START) / 0x10000; uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL; nv_log("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset); -#endif + // 0x10 is free CACHE1 object // TODO: THERE ARE OTHER STUFF! @@ -55,7 +54,7 @@ uint32_t nv3_user_read(uint32_t address) } - nv_log("IT'S NOT IMPLEMENTED!!!!\n", method_offset); + nv_log("IT'S NOT IMPLEMENTED!!!! offset=0x%04x\n", method_offset); return 0x00; diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index 420d209b4..185c46183 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -72,8 +72,12 @@ void nv_log(const char *fmt, ...) } } #else -void -nv_log(const char *fmt, ...) +void nv_log(const char *fmt, ...) +{ + +} + +void nv_log_set_device(void* device) { } From c28a596a342b629b080a6b4d1ab32154732ddb41 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 17:04:41 +0000 Subject: [PATCH 150/274] Make unimplemented methods a warning rather than log them, and add logging for each method executed. --- src/include/86box/nv/classes/vid_nv3_classes.h | 1 + src/video/nv/nv3/classes/nv3_class_001_beta_factor.c | 2 +- src/video/nv/nv3/classes/nv3_class_002_rop.c | 2 +- src/video/nv/nv3/classes/nv3_class_003_chroma_key.c | 2 +- src/video/nv/nv3/classes/nv3_class_004_plane_mask.c | 2 +- .../nv/nv3/classes/nv3_class_005_clipping_rectangle.c | 2 +- src/video/nv/nv3/classes/nv3_class_006_pattern.c | 7 +++++-- src/video/nv/nv3/classes/nv3_class_007_rectangle.c | 2 +- src/video/nv/nv3/classes/nv3_class_008_point.c | 2 +- src/video/nv/nv3/classes/nv3_class_009_line.c | 2 +- src/video/nv/nv3/classes/nv3_class_00a_lin.c | 2 +- src/video/nv/nv3/classes/nv3_class_00b_triangle.c | 2 +- src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 2 +- .../nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c | 2 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 8 ++++++-- src/video/nv/nv3/classes/nv3_class_011_image.c | 2 +- src/video/nv/nv3/classes/nv3_class_012_bitmap.c | 2 +- src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c | 2 +- .../nv3/classes/nv3_class_015_stretched_image_from_cpu.c | 2 +- .../nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c | 2 +- .../nv/nv3/classes/nv3_class_018_point_zeta_buffer.c | 2 +- src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c | 2 +- src/video/nv/nv3/subsystems/nv3_ptimer.c | 4 +--- 24 files changed, 33 insertions(+), 27 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 309a1c5aa..0503c0c66 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -98,6 +98,7 @@ typedef enum nv3_pgraph_class_e #define NV3_PATTERN_SHAPE_1X64 2 #define NV3_PATTERN_SHAPE_LAST_VALID NV3_PATTERN_SHAPE_1X64 +#define NV3_PATTERN_UNUSED_DRIVER_BUG 0x030C #define NV3_PATTERN_COLOR0 0x0310 #define NV3_PATTERN_COLOR1 0x0314 #define NV3_PATTERN_BITMAP_HIGH 0x0318 diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c index 694e49085..4520a941f 100644 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c @@ -43,7 +43,7 @@ void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c index 8c3580f4f..56b135888 100644 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ b/src/video/nv/nv3/classes/nv3_class_002_rop.c @@ -37,7 +37,7 @@ void nv3_class_002_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: ROP = %02x\n", nv3->pgraph.rop); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 54d52e197..fae6771e2 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -38,7 +38,7 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.chroma_key = nv3_render_to_chroma(expanded_color); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c index 5789b8e11..d93de9bc1 100644 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c @@ -33,7 +33,7 @@ void nv3_class_004_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c index 7bfbd4dd6..c7ec3ae98 100644 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c @@ -42,7 +42,7 @@ void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: Clip Size: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index c1fba2309..f007d5fb8 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -54,6 +54,10 @@ void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ */ nv3->pgraph.pattern_shape = param & 0x03; + break; + /* Seems to be "SetPatternSelect" on Riva TNT and later, but possibly called by accident on Riva 128. There is no hardware equivalent for this. So let's just suppress + the warnings. */ + case NV3_PATTERN_UNUSED_DRIVER_BUG: break; case NV3_PATTERN_COLOR0: nv3_color_expanded_t expanded_colour0 = nv3_render_expand_color(grobj, param); @@ -69,10 +73,9 @@ void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; case NV3_PATTERN_BITMAP_LOW: nv3->pgraph.pattern_bitmap |= param; - break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 24193f8d5..6dfdf281e 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -62,7 +62,7 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ return; } - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c index ec40419df..41002f745 100644 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ b/src/video/nv/nv3/classes/nv3_class_008_point.c @@ -33,7 +33,7 @@ void nv3_class_008_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c index c0667af47..f149bb8b3 100644 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ b/src/video/nv/nv3/classes/nv3_class_009_line.c @@ -33,7 +33,7 @@ void nv3_class_009_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c index 839b4768c..473aaa214 100644 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ b/src/video/nv/nv3/classes/nv3_class_00a_lin.c @@ -34,7 +34,7 @@ void nv3_class_00a_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c index a790eabc3..d08b7a72e 100644 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c @@ -33,7 +33,7 @@ void nv3_class_00b_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 38969a5a0..ea886476d 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -190,7 +190,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ return; } - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 06c5d93b6..fd8f0d5f2 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -33,7 +33,7 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c index ea5db21ff..457c8ade1 100644 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c @@ -33,7 +33,7 @@ void nv3_class_00e_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index c07c600ee..5eea98f85 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -35,21 +35,25 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_BLIT_POSITION_IN: nv3->pgraph.blit.point_in.x = (param & 0xFFFF); nv3->pgraph.blit.point_in.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: S2SB POINT_IN %04x,%04x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); break; case NV3_BLIT_POSITION_OUT: nv3->pgraph.blit.point_out.x = (param & 0xFFFF); nv3->pgraph.blit.point_out.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: S2SB POINT_OUT %04x,%04x\n", nv3->pgraph.blit.point_out.x, nv3->pgraph.blit.point_out.y); + break; case NV3_BLIT_SIZE: /* This is the last one*/ nv3->pgraph.blit.size.w = (param & 0xFFFF); nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); - + nv_log("Method Execution: S2SB Size %04x,%04x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); + nv3_render_blit_screen2screen(grobj); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 42574bc30..523aadff7 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -133,7 +133,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } else { - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); } diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c index 799673391..2ac47f0de 100644 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c @@ -34,7 +34,7 @@ void nv3_class_012_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c index a27538dcb..b49b1fc89 100644 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c @@ -34,7 +34,7 @@ void nv3_class_014_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c index d029dc080..3fa88ba39 100644 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c @@ -33,7 +33,7 @@ void nv3_class_015_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c index c4c7aa0cd..3bb8f66d7 100644 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c @@ -33,7 +33,7 @@ void nv3_class_017_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c index 6a0632377..87111b70c 100644 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c @@ -35,7 +35,7 @@ void nv3_class_018_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); return; } diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 5d06ed678..dd5768103 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -82,7 +82,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x\n", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); break; default: - nv_log("%s: Invalid or Unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 1e3347beb..c1b8a2576 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -78,10 +78,8 @@ void nv3_ptimer_tick(double real_time) // truncate it nv3->ptimer.time += (uint64_t)current_time; + // Check if the alarm has actually triggered.. // Only log on ptimer alarm. Otherwise, it's too much spam. - //nv_log("PTIMER time ticked (The value is now 0x%08x)\n", nv3->ptimer.time); - - // Check if the alarm has actually triggered... if (nv3->ptimer.time >= nv3->ptimer.alarm) { nv_log("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); From 7234b432ac2301aa7fb234c69974e2f40c8f0ae3 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 19:06:46 +0000 Subject: [PATCH 151/274] inform the emulator of the video timings --- src/include/86box/nv/render/vid_nv3_render.h | 5 +- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 2 +- .../nv/nv3/classes/nv3_class_006_pattern.c | 4 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 5 + .../nv/nv3/classes/nv3_class_011_image.c | 77 +--------------- src/video/nv/nv3/nv3_core.c | 22 ++++- src/video/nv/nv3/render/nv3_render_blit.c | 91 ++++++++++++++++++- src/video/nv/nv3/render/nv3_render_core.c | 10 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 11 ++- 9 files changed, 131 insertions(+), 96 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 65541fa0d..fe429da74 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -24,7 +24,7 @@ uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj); uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); -nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color); // Convert a colour to full RGB10 format from the current working format. +nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color); // Convert a colour from the current working format to RGB10 format. /* Pattern */ @@ -34,9 +34,10 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); /* Chroma */ -bool nv3_render_chroma_test(nv3_grobj_t grobj, uint32_t color); +bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj); /* Blit */ +void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj); void nv3_render_blit_screen2screen(nv3_grobj_t grobj); /* GDI */ diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index fae6771e2..f2e575933 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -33,7 +33,7 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ switch (method_id) { case NV3_CHROMA_KEY: - nv3_color_expanded_t expanded_color = nv3_render_expand_color(grobj, param); + nv3_color_expanded_t expanded_color = nv3_render_expand_color(param, grobj); nv3->pgraph.chroma_key = nv3_render_to_chroma(expanded_color); break; diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index f007d5fb8..b66db499e 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -60,11 +60,11 @@ void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_PATTERN_UNUSED_DRIVER_BUG: break; case NV3_PATTERN_COLOR0: - nv3_color_expanded_t expanded_colour0 = nv3_render_expand_color(grobj, param); + nv3_color_expanded_t expanded_colour0 = nv3_render_expand_color(param, grobj); nv3_render_set_pattern_color(expanded_colour0, false); break; case NV3_PATTERN_COLOR1: - nv3_color_expanded_t expanded_colour1 = nv3_render_expand_color(grobj, param); + nv3_color_expanded_t expanded_colour1 = nv3_render_expand_color(param, grobj); nv3_render_set_pattern_color(expanded_colour1, true); break; case NV3_PATTERN_BITMAP_HIGH: diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 5eea98f85..57184054d 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -49,6 +49,11 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); nv_log("Method Execution: S2SB Size %04x,%04x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); + /* Some blits have (point_in == point_out) ???? */ + if (nv3->pgraph.blit.point_in.x == nv3->pgraph.blit.point_out.x + && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y) + return; + nv3_render_blit_screen2screen(grobj); break; diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index 523aadff7..c1d1200b9 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -28,19 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -/* Check the line bounds */ -void nv3_class_011_check_line_bounds() -{ - uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x; - //uint32_t relative_y = nv3->pgraph.image_current_position.y - nv3->pgraph.image.point.y; - /* In theory, relative_y should never be exceeded...because it only submits enough pixels to render the image*/ - if (relative_x >= nv3->pgraph.image.size_in.w) - { - nv3->pgraph.image_current_position.y++; - nv3->pgraph.image_current_position.x = nv3->pgraph.image.point.x; - } -} void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { @@ -65,71 +53,10 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; default: if (method_id >= NV3_IMAGE_COLOR_START && method_id <= NV3_IMAGE_COLOR_END) - { - // shift left by 2 because it's 4 bits per si\e.. + { uint32_t pixel_slot = (method_id - NV3_IMAGE_COLOR_START) >> 2; - uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; nv_log("Method Execution: Pixel%d Colour%08x Format%x\n", pixel_slot, param, (grobj.grobj_0) & 0x07); - - /* todo: a lot of stuff */ - - uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; - - /* Some extra data is sent as padding, we need to clip it off using size_out */ - - uint16_t clip_x = nv3->pgraph.image_current_position.x + nv3->pgraph.image.size.w; - /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ - /* the reverse order is due to the endianness */ - switch (nv3->nvbase.svga.bpp) - { - // 4pixels packed into one param - case 8: - - //pixel3 - pixel3 = param & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel2 = (param >> 8) & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel1 = (param >> 16) & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel0 = (param >> 24) & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - break; - //2pixels packed into one param - case 15: - case 16: - pixel1 = (param) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel0 = (param >> 16) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - break; - // just one pixel in 32bpp - case 32: - pixel0 = param; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - break; - } + nv3_render_blit_image(param, grobj); } else { diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 28c6edab5..1718b4e7f 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -29,6 +29,13 @@ nv3_t* nv3; +/* These are a ****PLACEHOLDER**** and are copied from 3dfx VoodooBanshee/Voodoo3*/ +static video_timings_t timing_nv3_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; +static video_timings_t timing_nv3_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; +// Revision C +static video_timings_t timing_nv3t_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; +static video_timings_t timing_nv3t_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; + // Prototypes for functions only used in this translation unit void nv3_init_mappings_mmio(); void nv3_init_mappings_svga(); @@ -492,9 +499,7 @@ void nv3_recalc_timings(svga_t* svga) nv3_t* nv3 = (nv3_t*)svga->priv; - svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; // should these actually use separate values? @@ -530,7 +535,7 @@ void nv3_recalc_timings(svga_t* svga) } else { - svga->bpp = 15; // HACK: DO NOT change this + svga->bpp = 15; svga->lowres = 0; svga->render = svga_render_15bpp_highres; } @@ -1085,6 +1090,12 @@ void* nv3_init(const device_t *info) svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); + + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_pci); + else + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_pci); + } else if (nv3->nvbase.bus_generation == nv_bus_agp_1x) { @@ -1094,6 +1105,11 @@ void* nv3_init(const device_t *info) svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); + + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_agp); + else + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_agp); } // set vram diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 539871884..9da3f05b1 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -29,9 +29,94 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> +/* Check the line bounds */ +void nv3_class_011_check_line_bounds() +{ + uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x; + //uint32_t relative_y = nv3->pgraph.image_current_position.y - nv3->pgraph.image.point.y; + + /* In theory, relative_y should never be exceeded...because it only submits enough pixels to render the image*/ + if (relative_x >= nv3->pgraph.image.size_in.w) + { + nv3->pgraph.image_current_position.y++; + nv3->pgraph.image_current_position.x = nv3->pgraph.image.point.x; + } +} + +/* Renders an image from cpu */ +void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) +{ + // shift left by 2 because it's 4 bits per size.. + uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + + /* todo: a lot of stuff */ + + uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; + + /* Some extra data is sent as padding, we need to clip it off using size_out */ + + uint16_t clip_x = nv3->pgraph.image_current_position.x + nv3->pgraph.image.size.w; + /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ + /* the reverse order is due to the endianness */ + switch (nv3->nvbase.svga.bpp) + { + // 4pixels packed into one color + case 8: + + //pixel3 + pixel3 = color & 0xFF; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel2 = (color >> 8) & 0xFF; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel1 = (color >> 16) & 0xFF; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel0 = (color >> 24) & 0xFF; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + break; + //2pixels packed into one color + case 15: + case 16: + pixel1 = (color) & 0xFFFF; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + pixel0 = (color >> 16) & 0xFFFF; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + break; + // just one pixel in 32bpp + case 32: + pixel0 = color; + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + nv3->pgraph.image_current_position.x++; + nv3_class_011_check_line_bounds(); + + break; + } + +} + void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { - nv3_position_16_t old_position = nv3->pgraph.blit.point_in; + //nv3_position_16_t old_position = nv3->pgraph.blit.point_in + nv3->pgraph.blit.size.w; + nv3_position_16_t old_position = {0}; + old_position.x = nv3->pgraph.blit.point_in.x + nv3->pgraph.blit.size.w; + old_position.y = nv3->pgraph.blit.point_in.y + nv3->pgraph.blit.size.h; nv3_position_16_t new_position = nv3->pgraph.blit.point_out; uint16_t end_x = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); @@ -63,7 +148,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) old_position.y++; new_position.y++; - for (int32_t x = nv3->pgraph.blit.point_out.x; x < end_x; x++) + for (int32_t x = nv3->pgraph.blit.point_out.x; x >= end_x; x++) { old_position.x++; new_position.x++; @@ -79,7 +164,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) old_position.y++; new_position.y++; - for (int32_t x = nv3->pgraph.blit.point_out.x; x < end_x; x++) + for (int32_t x = nv3->pgraph.blit.point_out.x; x >= end_x; x++) { old_position.x++; new_position.x++; diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 7ae00efd6..15c652e5b 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -33,7 +33,7 @@ /* Expand a colour. NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! */ -nv3_color_expanded_t nv3_render_expand_color(nv3_grobj_t grobj, uint32_t color) +nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) { // grobj0 = seems to share the format of PGRAPH_CONTEXT_SWITCH register. @@ -113,7 +113,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; #ifdef ENABLE_NV_LOG - nv_log("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d", color, format, alpha_enabled); + nv_log("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); #endif uint32_t packed_color = 0x00; @@ -156,7 +156,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co } /* Runs the chroma key/color key test */ -bool nv3_render_chroma_test(nv3_grobj_t grobj, uint32_t color) +bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj) { bool chroma_enabled = ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_CHROMA_KEY) & 0x01); @@ -172,7 +172,7 @@ bool nv3_render_chroma_test(nv3_grobj_t grobj, uint32_t color) nv3_grobj_t grobj_fake = {0}; grobj_fake.grobj_0 = 0x02; /* we don't care about any other bits */ - nv3_color_expanded_t chroma_expanded = nv3_render_expand_color(grobj_fake, nv3->pgraph.chroma_key); + nv3_color_expanded_t chroma_expanded = nv3_render_expand_color(nv3->pgraph.chroma_key, grobj_fake); uint32_t chroma_downconverted = nv3_render_downconvert_color(grobj, chroma_expanded); @@ -315,7 +315,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob } /* TODO: Plane Mask...*/ - if (!nv3_render_chroma_test(grobj, color)) + if (!nv3_render_chroma_test(color, grobj)) return; uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj); diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index c640d5f10..fb83ffaf1 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -341,14 +341,14 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) nv3->pramdac.vblank_end = value; break; case NV3_PRAMDAC_VBLANK_START: - nv3->nvbase.svga.vblankstart = value; + //nv3->nvbase.svga.vblankstart = value; nv3->pramdac.vblank_start = value; break; case NV3_PRAMDAC_VEQU_START: nv3->pramdac.vequ_start = value; break; case NV3_PRAMDAC_VTOTAL: - nv3->pramdac.vtotal = value; + //nv3->pramdac.vtotal = value; nv3->nvbase.svga.vtotal = value; break; case NV3_PRAMDAC_HSYNC_WIDTH: @@ -361,21 +361,22 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) nv3->pramdac.hburst_end = value; break; case NV3_PRAMDAC_HBLANK_START: - nv3->nvbase.svga.hblankstart = value; + //nv3->nvbase.svga.hblankstart = value; nv3->pramdac.hblank_start = value; break; case NV3_PRAMDAC_HBLANK_END: - nv3->nvbase.svga.hblank_end_val = value; + //nv3->nvbase.svga.hblank_end_val = value; nv3->pramdac.hblank_end = value; break; case NV3_PRAMDAC_HTOTAL: nv3->pramdac.htotal = value; - nv3->nvbase.svga.htotal = value; + //nv3->nvbase.svga.htotal = value; break; case NV3_PRAMDAC_HEQU_WIDTH: nv3->pramdac.hequ_width = value; break; case NV3_PRAMDAC_HSERR_WIDTH: + nv3->pramdac.hserr_width = value; break; } From d8fae9abc57a54371f51527679514e61c5ffe40d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 20:39:02 +0000 Subject: [PATCH 152/274] fix clipping of images, black line is gone... --- src/include/86box/nv/vid_nv.h | 24 ++++++++-------- .../classes/nv3_class_00c_win95_gdi_text.c | 10 ++++--- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- src/video/nv/nv3/nv3_core.c | 28 +++++++++++-------- src/video/nv/nv3/render/nv3_render_blit.c | 6 ++-- 5 files changed, 39 insertions(+), 31 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 71c636c78..79a420243 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -48,20 +48,20 @@ void nv_log(const char *fmt, ...); #define NV_PCI_NUM_CFG_REGS 256 // number of pci config registers // 0x0000 was probably the NV0 'Nvidia Hardware Simulator' -#define PCI_DEVICE_NV1 0x0008 // Nvidia NV1 -#define PCI_DEVICE_NV1_VGA 0x0009 // Nvidia NV1 VGA core -#define PCI_DEVICE_NV2 0x0010 // Nvidia NV2 / Mutara V08 (cancelled) -#define PCI_DEVICE_NV3 0x0018 // Nvidia NV3 (Riva 128) -#define PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) -#define PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) +#define NV_PCI_DEVICE_NV1 0x0008 // Nvidia NV1 +#define NV_PCI_DEVICE_NV1_VGA 0x0009 // Nvidia NV1 VGA core +#define NV_PCI_DEVICE_NV2 0x0010 // Nvidia NV2 / Mutara V08 (cancelled) +#define NV_PCI_DEVICE_NV3 0x0018 // Nvidia NV3 (Riva 128) +#define NV_PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) +#define NV_PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) -#define CHIP_REVISION_NV1_A0 0x0000 // 1994 -#define CHIP_REVISION_NV1_B0 0x0010 // 1995 -#define CHIP_REVISION_NV1_C0 0x0020 // +#define NV_CHIP_REVISION_NV1_A0 0x0000 // 1994 +#define NV_CHIP_REVISION_NV1_B0 0x0010 // 1995 +#define NV_CHIP_REVISION_NV1_C0 0x0020 // 1995-96? -#define CHIP_REVISION_NV3_A0 0x0000 // January 1997 -#define CHIP_REVISION_NV3_B0 0x0010 // October 1997 -#define CHIP_REVISION_NV3_C0 0x0020 // 1998 +#define NV_CHIP_REVISION_NV3_A0 0x0000 // January 1997 +#define NV_CHIP_REVISION_NV3_B0 0x0010 // October 1997 +#define NV_CHIP_REVISION_NV3_C0 0x0020 // 1998 // Architecture IDs #define NV_ARCHITECTURE_NV1 1 // NV1/STG2000 diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index ea886476d..30926020a 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -131,11 +131,13 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; + + // IN THIS ONE SPECIFIC PLACE, ****AND ONLY THIS ONE SPECIFIC PLACE****, X AND Y ARE SWAPPED???? */ // If the size is submitted, render it. if (method_id & 0x04) { - nv3->pgraph.win95_gdi_text.rect_a_size[index].w = param & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_size[index].h = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].w = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].h = param & 0xFFFF; nv_log("Method Execution: Rect GDI-A%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, nv3->pgraph.win95_gdi_text.rect_a_size[index].h, nv3->pgraph.win95_gdi_text.color_a); @@ -145,8 +147,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ } else // position { - nv3->pgraph.win95_gdi_text.rect_a_position[index].x = param & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_position[index].y = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_position[index].x = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_position[index].y = param & 0xFFFF; nv_log("Method Execution: Rect GDI-A%d Position=%d,%d\n", index, nv3->pgraph.win95_gdi_text.rect_a_position[index].x, nv3->pgraph.win95_gdi_text.rect_a_position[index].y); diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 57184054d..7bae42184 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -54,7 +54,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y) return; - nv3_render_blit_screen2screen(grobj); + //nv3_render_blit_screen2screen(grobj); break; default: diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 1718b4e7f..5bab81bc4 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -27,6 +27,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> +/* Main device object pointer */ nv3_t* nv3; /* These are a ****PLACEHOLDER**** and are copied from 3dfx VoodooBanshee/Voodoo3*/ @@ -257,11 +258,11 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) // device id case NV3_PCI_CFG_DEVICE_ID: - ret = (PCI_DEVICE_NV3 & 0xFF); + ret = (NV_PCI_DEVICE_NV3 & 0xFF); break; case NV3_PCI_CFG_DEVICE_ID+1: - ret = (PCI_DEVICE_NV3 >> 8); + ret = (NV_PCI_DEVICE_NV3 >> 8); break; // various capabilities @@ -498,6 +499,7 @@ void nv3_recalc_timings(svga_t* svga) return; nv3_t* nv3 = (nv3_t*)svga->priv; + uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03; svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; @@ -506,18 +508,22 @@ void nv3_recalc_timings(svga_t* svga) // i don't we should force the top 2 bits to 1... // required for VESA resolutions, force parameters higher + // only fuck around with any of this in VGAmode? - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; - - if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) - svga->hdisp += 0x100; // large screen bit + if (pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA) + { + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) + svga->hdisp += 0x100; // large screen bit + } + // Set the pixel mode - switch (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03) + switch (pixel_mode) { case NV3_CRTC_REGISTER_PIXELMODE_8BPP: svga->bpp = 8; diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 9da3f05b1..032b23b47 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -55,7 +55,7 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) /* Some extra data is sent as padding, we need to clip it off using size_out */ - uint16_t clip_x = nv3->pgraph.image_current_position.x + nv3->pgraph.image.size.w; + uint16_t clip_x = nv3->pgraph.image.point.x + nv3->pgraph.image.size.w; /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) @@ -89,12 +89,12 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) case 15: case 16: pixel1 = (color) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); + if (nv3->pgraph.image_current_position.x < (clip_x)) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); pixel0 = (color >> 16) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < (clip_x)) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); From 4e01ee82c7ffd853d6ae4174dffcd087ad3aac3c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 21:26:37 +0000 Subject: [PATCH 153/274] Mostly fix 32bpp (8bpp blackscreens instead of drawing garbage all over the screen) by shifting row offset appropriately for the pixel mode. --- src/video/nv/nv3/nv3_core.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 5bab81bc4..204efaaa2 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -502,8 +502,7 @@ void nv3_recalc_timings(svga_t* svga) uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03; svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; - + // should these actually use separate values? // i don't we should force the top 2 bits to 1... @@ -526,13 +525,15 @@ void nv3_recalc_timings(svga_t* svga) switch (pixel_mode) { case NV3_CRTC_REGISTER_PIXELMODE_8BPP: + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 1; // ????? svga->bpp = 8; svga->lowres = 0; svga->map8 = svga->pallook; svga->render = svga_render_8bpp_highres; break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: - /* sometimes it really renders in 15bpp, so you need to do this */ + /* sometimes it really renders in 15bpp, so you need to do this */ + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) { svga->bpp = 16; @@ -548,6 +549,7 @@ void nv3_recalc_timings(svga_t* svga) break; case NV3_CRTC_REGISTER_PIXELMODE_32BPP: + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; svga->bpp = 32; svga->lowres = 0; svga->render = svga_render_32bpp_highres; From 0e16ef5498562655c150825be4e543f69bf93ce6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 29 Mar 2025 23:25:15 +0000 Subject: [PATCH 154/274] Implemented a dummy M2MF class implementation until I fully understand it. This is enough to get Windows 9x to display something. --- .../86box/nv/classes/vid_nv3_classes.h | 24 ++++++++- .../nv/nv3/classes/nv3_class_003_chroma_key.c | 7 +++ .../classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 51 ++++++++++++++++++- 4 files changed, 80 insertions(+), 4 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 0503c0c66..4f52bf789 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -84,6 +84,8 @@ typedef enum nv3_pgraph_class_e #define NV3_BETA_FACTOR 0x0300 // Chroma Key +// Can't figure out what this is, used in 9x but certainly software, can't find anywhere... +#define NV3_CHROMA_UNKNOWN_0200 0x0200 #define NV3_CHROMA_KEY 0x0304 // Clip @@ -114,6 +116,25 @@ typedef enum nv3_pgraph_class_e #define NV3_RECTANGLE_MAX 16 #define NV3_RECTANGLE_END 0x0480 +// M2MF +#define NV3_M2MF_IN_CTXDMA_OFFSET 0x030C +#define NV3_M2MF_OUT_CTXDMA_OFFSET 0x0310 +#define NV3_M2MF_IN_PITCH 0x0314 +#define NV3_M2MF_OUT_PITCH 0x0318 +#define NV3_M2MF_SCANLINE_LENGTH_IN_BYTES 0x031C +#define NV3_M2MF_NUM_SCANLINES 0x0320 +#define NV3_M2MF_FORMAT 0x0324 + +// M2MF formats (IN and OUT ORed together) +#define NV3_M2MF_FORMAT_INPUT_INC_1 0x1 +#define NV3_M2MF_FORMAT_INPUT_INC_2 0x2 +#define NV3_M2MF_FORMAT_INPUT_INC_4 0x4 +#define NV3_M2MF_FORMAT_OUTPUT_INC_1 0x100 +#define NV3_M2MF_FORMAT_OUTPUT_INC_2 0x200 +#define NV3_M2MF_FORMAT_OUTPUT_INC_4 0x400 + +#define NV3_M2MF_NOTIFY 0x0328 + // blit #define NV3_BLIT_POSITION_IN 0x0300 #define NV3_BLIT_POSITION_OUT 0x0304 @@ -634,8 +655,7 @@ typedef struct nv3_object_class_00D uint32_t pitch_out; uint32_t line_length_in; // Stride? uint32_t line_count; - uint8_t format_input_bits; // 1 2 or 4 to increment by bits - uint8_t format_output_bits; // 1 2 to 4 to increment by bits + uint8_t format; // input increment 1 2 or 4, output increment 1 2 or 4 (represented by << 8) uint8_t reserved3[2]; uint32_t buffer_notify; // Notify the Buffedr uint8_t reserved4[0x1CD3]; diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index f2e575933..139099e78 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -32,10 +32,17 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { switch (method_id) { + case NV3_CHROMA_UNKNOWN_0200: + nv_log("Method Execution: Chroma Unknown 0x0200 0x%08x", param); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + + break; case NV3_CHROMA_KEY: nv3_color_expanded_t expanded_color = nv3_render_expand_color(param, grobj); nv3->pgraph.chroma_key = nv3_render_to_chroma(expanded_color); + + nv_log("Method Execution: Chroma = 0x%08x", nv3->pgraph.chroma_key); break; default: warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index 30926020a..e006c41f3 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -192,7 +192,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ return; } - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + nv_log("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index fd8f0d5f2..b75a8e546 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -32,9 +32,58 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { switch (method_id) { + case NV3_M2MF_IN_CTXDMA_OFFSET: + nv3->pgraph.m2mf.offset_in = param; + nv_log("Method Execution: M2MF Offset In = 0x%08x", param); + break; + case NV3_M2MF_OUT_CTXDMA_OFFSET: + nv3->pgraph.m2mf.offset_out = param; + nv_log("Method Execution: M2MF Offset Out = 0x%08x", param); + break; + case NV3_M2MF_IN_PITCH: + nv3->pgraph.m2mf.pitch_in = param; + nv_log("Method Execution: M2MF Pitch In = 0x%08x", param); + break; + case NV3_M2MF_OUT_PITCH: + nv3->pgraph.m2mf.pitch_out = param; + nv_log("Method Execution: M2MF Pitch Out = 0x%08x", param); + break; + case NV3_M2MF_SCANLINE_LENGTH_IN_BYTES: + nv3->pgraph.m2mf.line_length_in = param; + nv_log("Method Execution: M2MF Scanline Length in Bytes = 0x%08x", param); + break; + case NV3_M2MF_NUM_SCANLINES: + nv3->pgraph.m2mf.line_count = param; + nv_log("Method Execution: M2MF Num Scanlines = 0x%08x", param); + break; + case NV3_M2MF_FORMAT: + nv3->pgraph.m2mf.format = param; + nv_log("Method Execution: M2MF Format = 0x%08x", param); + break; + case NV3_M2MF_NOTIFY: + /* This is technically its own thing, but I don't know if it's ever a problem with how we've designed it */ + if (nv3->pgraph.notify_pending) + { + nv_log("M2MF notification with notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); + nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); + nv3_debug_ramin_print_context_info(param, context); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + + // disable + nv3->pgraph.notify_pending = false; + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + /* may need to disable fifo in this state */ + return; + } + + nv_log("Method Execution: TODO: ACTUALLY IMPLEMENT M2MF!!!!"); + // set a notify as pending. + nv3->pgraph.notifier = param; + nv3->pgraph.notify_pending = true; + break; default: warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; + break;; } } \ No newline at end of file From c8e7bfac9e05aff3a6f57722390cfde11f1e23e7 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 30 Mar 2025 02:38:59 +0100 Subject: [PATCH 155/274] make 2k and 9x live happily together, seems vtrace register bit 1 controls rowoffset shifting --- doc/nvidia_notes/status.xlsx | Bin 15813 -> 15983 bytes .../classes/nv3_class_00c_win95_gdi_text.c | 10 ++++++++++ src/video/nv/nv3/nv3_core.c | 17 +++++++++++++++-- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index d43765e803cd7105a9c392f5c3b8fe7889659bd2..6fc2aaa7411f99190fe376bd6114dfa499f86c48 100644 GIT binary patch delta 8245 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z74~`@zVypD#iMQ_#rOWf&#ddCcFhC6@0DlVBL6}aSO43gJN!wGDXF4*U#J2Ei<=3|p?p*ue7BqaTq`t7FgQY?}IL-yM%}M5uDBil{ zs3=zpF&o3+@(&Q_o#05JM3tT%{L3jPA%8mUjn?F@RaeSI9{BUlDA(f5CoB!6UVotp z`=X`-)Nqf~nIE7wy_LC8jFKFK1;Hy4;cb&R9B*ht_jKuIwK=CAn>#>(tBK77uvfe%EnikjiB1-1*Hiyi zmW}t*z}Df(&OF^GWwy6`T7sl(VG>v6vULvd5W03R`Tq?o!Tsxx%C$6t%!pu9l^!0_ z@FUbG*};0}+iGqZ_(#ZUIC59anyJ!~bKfgWP~BdK&_RO{l*EjAt4(9%1E@u8D&-1u zAz9n{B|v85qeW7hRod4rs{`&tI}TvBp0-qk5zo5}bMrz~d}cv0hY~3`LEM&7H(n86 zU85d;95!55O>Kp;JKDI!(E!>PkA9{!|U@6=qXz;V7unGCrfi{mYsTQ$B!fP5? zxJOeOyPKR6760+lXsrImGgn_>q@}Lh1FG&m;53r3wjz=4!ShOuPyj^J^XJp?-sWma zQb|t6nv)JB`kF)66 z^`pAq@B>KCr;q%PJE_J4&&hgI)TT8b%j8D6|KmUa$+@pqj?8_eFnbF;8f8RGONEbd3(kcq1{MSzY zUr;{&Gl(35CWc4xuS52~pyv`$jGgjd8UDZfIb?rNiWdV?{#VtSKUV_&nEwm9rThz; zdpgraph.win95_gdi_text.color_a = param; nv_log("Method Execution: GDI-A Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; + case NV3_W95TXT_B_CLIP_TOPLEFT: + nv3->pgraph.win95_gdi_text.clip_b.left = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clip_b.top = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-B Clip Left,Top %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.left, nv3->pgraph.win95_gdi_text.clip_b.top); + break; + case NV3_W95TXT_B_CLIP_BOTTOMRIGHT: + nv3->pgraph.win95_gdi_text.clip_b.bottom = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clip_b.right = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-B Clip Bottom,Right %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.left, nv3->pgraph.win95_gdi_text.clip_b.top); + break; /* Type B and C not implemented YET, as they are not used by NT GDI driver */ case NV3_W95TXT_D_CLIP_TOPLEFT: nv3->pgraph.win95_gdi_text.clip_d.left = (param & 0xFFFF); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 204efaaa2..a365cab62 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -502,7 +502,7 @@ void nv3_recalc_timings(svga_t* svga) uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03; svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; - + // should these actually use separate values? // i don't we should force the top 2 bits to 1... @@ -532,8 +532,18 @@ void nv3_recalc_timings(svga_t* svga) svga->render = svga_render_8bpp_highres; break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: + /* This is some sketchy shit that is an attempt at an educated guess + at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, this is what's causing it */ + if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01) + { + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; + } + else + { + svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; + } + /* sometimes it really renders in 15bpp, so you need to do this */ - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) { svga->bpp = 16; @@ -545,11 +555,14 @@ void nv3_recalc_timings(svga_t* svga) svga->bpp = 15; svga->lowres = 0; svga->render = svga_render_15bpp_highres; + + // fixes win2000, but breaks 9x?! } break; case NV3_CRTC_REGISTER_PIXELMODE_32BPP: svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; + svga->bpp = 32; svga->lowres = 0; svga->render = svga_render_32bpp_highres; From f1a231b6cced1b0d4586c0c8e6d68cfe4c68487c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 30 Mar 2025 23:56:42 +0100 Subject: [PATCH 156/274] Implement GDI-B. Rewrite text rendering code for perfect implementation of GDI-C, GDI-D and GDI-E text classes. Fucking hell that took forever.... --- .../86box/nv/classes/vid_nv3_classes.h | 9 +- src/include/86box/nv/render/vid_nv3_render.h | 7 +- src/include/86box/nv/vid_nv3.h | 4 +- .../classes/nv3_class_00c_win95_gdi_text.c | 132 ++++-- .../nv/nv3/render/nv3_render_primitives.c | 385 +++++++++++++----- 5 files changed, 392 insertions(+), 145 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 4f52bf789..e3a1bf7aa 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -165,6 +165,7 @@ typedef enum nv3_pgraph_class_e /* Type B: Clipped Rectangle */ #define NV3_W95TXT_B_CLIP_TOPLEFT 0x07F4 #define NV3_W95TXT_B_CLIP_BOTTOMRIGHT 0x07F8 +#define NV3_W95TXT_B_COLOR 0x07FC #define NV3_W95TXT_B_CLIP_CLIPRECT_START 0x0800 #define NV3_W95TXT_B_CLIP_CLIPRECT_SIZE 128 // Number of rects #define NV3_W95TXT_B_CLIP_CLIPRECT_END 0x09FF @@ -610,20 +611,20 @@ typedef struct nv3_object_class_00C uint8_t reserved3[0x1F0]; nv3_clip_16_t clip_b; uint32_t color_b; // Color for Clip B - nv3_clip_16_t rect_clip[64]; + nv3_clip_16_t clipped_rect[64]; uint8_t reserved4[0x1E8]; nv3_clip_16_t clip_c; uint32_t color1_c; nv3_size_16_t size_c; nv3_position_16_t point_c; - uint32_t color1_c_bitmap[128]; + uint32_t bitmap_c[128]; uint8_t reserved5[0x368]; nv3_clip_16_t clip_d; uint32_t color1_d; nv3_size_16_t size_in_d; nv3_size_16_t size_out_d; nv3_position_16_t point_d; - uint32_t mono_color1_d[128]; + uint32_t bitmap_d[128]; uint8_t reserved6[0x364]; nv3_clip_16_t clip_e; uint32_t color0_e; @@ -631,7 +632,7 @@ typedef struct nv3_object_class_00C nv3_size_16_t size_in_e; nv3_size_16_t size_out_e; nv3_position_16_t point_e; - uint32_t mono_color1_e[128]; + uint32_t bitmap_e[128]; uint8_t reserved7[0xB7F]; } nv3_win95_text_t; diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index fe429da74..9b5acd06d 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -31,7 +31,8 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1); /* Primitives */ -void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); +void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); // Render an A (unclipped) GDI rect +void nv3_render_rect_clipped(nv3_clip_16_t clip, uint32_t color, nv3_grobj_t grobj); // Render a B (clipped) GDI rect. /* Chroma */ bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj); @@ -41,5 +42,5 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj); void nv3_render_blit_screen2screen(nv3_grobj_t grobj); /* GDI */ -void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param); /* GDI Type-D: Clipped 1bpp text */ -void nv3_render_gdi_type_e(nv3_grobj_t grobj, uint32_t param); /* GDI Type-E: Clipped 1bpp two-colour text */ \ No newline at end of file +void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitmap_data, nv3_grobj_t grobj); +void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj); /* GDI Type-E: Clipped 1bpp colour-expanded bitmap */ \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index ed55e050d..1957984d2 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1229,7 +1229,9 @@ typedef struct nv3_pgraph_s struct nv3_object_class_00A lin; struct nv3_object_class_00B triangle; struct nv3_object_class_00C win95_gdi_text; - nv3_position_16_t win95_gdi_text_current_position; /* This is here so we can hold the current state of the image draw */ + /* These are here so we can hold the current state of the image draw */ + uint32_t win95_gdi_text_bit_count; + nv3_position_16_t win95_gdi_text_current_position; struct nv3_object_class_00D m2mf; struct nv3_object_class_00E scaled_image_from_memory; struct nv3_object_class_010 blit; diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index a32358912..e2f640fac 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -39,6 +39,11 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.color_a = param; nv_log("Method Execution: GDI-A Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; + /* Type B: Clipped Rectangle */ + case NV3_W95TXT_B_COLOR: + nv3->pgraph.win95_gdi_text.color_b = param; + nv_log("Method Execution: GDI-B Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_b); + break; case NV3_W95TXT_B_CLIP_TOPLEFT: nv3->pgraph.win95_gdi_text.clip_b.left = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_b.top = ((param >> 16) & 0xFFFF); @@ -47,20 +52,53 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_W95TXT_B_CLIP_BOTTOMRIGHT: nv3->pgraph.win95_gdi_text.clip_b.bottom = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_b.right = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-B Clip Bottom,Right %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.left, nv3->pgraph.win95_gdi_text.clip_b.top); + nv_log("Method Execution: GDI-B Clip Bottom,Right %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.right, nv3->pgraph.win95_gdi_text.clip_b.bottom); + break; + /* Type C: Unclipped Bitmap */ + case NV3_W95TXT_C_CLIP_COLOR: + nv3->pgraph.win95_gdi_text.color1_c = param; + nv_log("Method Execution: GDI-C Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color1_c); + break; + case NV3_W95TXT_C_CLIP_SIZE: + nv3->pgraph.win95_gdi_text.size_c.w = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_c.h = ((param >> 16) & 0xFFFF); + + nv3->pgraph.win95_gdi_text_bit_count = 0; + nv_log("Method Execution: GDI-C Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_c.w, nv3->pgraph.win95_gdi_text.size_c.h); + break; + case NV3_W95TXT_C_CLIP_POSITION: + nv3->pgraph.win95_gdi_text.point_c.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.point_c.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-C Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_c.x, nv3->pgraph.win95_gdi_text.point_c.y); + + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_c.x ; + nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_c.y; + + break; + case NV3_W95TXT_C_CLIP_TOPLEFT: + nv3->pgraph.win95_gdi_text.clip_c.left = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clip_c.top = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-C Clip Left,Top %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.top); + break; + case NV3_W95TXT_C_CLIP_BOTTOMRIGHT: + nv3->pgraph.win95_gdi_text.clip_c.right = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clip_c.bottom = ((param >> 16) & 0xFFFF); + /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ + nv_log("Method Execution: GDI-C Clip Right,Bottom %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.top); break; /* Type B and C not implemented YET, as they are not used by NT GDI driver */ case NV3_W95TXT_D_CLIP_TOPLEFT: nv3->pgraph.win95_gdi_text.clip_d.left = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_d.top = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-A Clip Left,Top %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); + nv_log("Method Execution: GDI-D Clip Left,Top %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); break; case NV3_W95TXT_D_CLIP_BOTTOMRIGHT: nv3->pgraph.win95_gdi_text.clip_d.right = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_d.bottom = ((param >> 16) & 0xFFFF); /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ - nv_log("Method Execution: GDI-A Clip Right,Bottom %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); + nv_log("Method Execution: GDI-D Clip Right,Bottom %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); break; + case NV3_W95TXT_D_CLIP_COLOR: nv3->pgraph.win95_gdi_text.color1_d = param; nv_log("Method Execution: GDI-D Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); @@ -80,29 +118,21 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.point_d.y = ((param >> 16) & 0xFFFF); nv_log("Method Execution: GDI-D Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y); - /* small case*/ - if (nv3->pgraph.win95_gdi_text.size_in_d.w < 0x0010) - { - nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_in_d.w - 1)); - nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); - } - /* large case: draw (7-0) (15-8)*/ - else - { - uint16_t large_start = (nv3->pgraph.win95_gdi_text.size_in_d.w >> 1) - 1; - nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + large_start); - nv3->pgraph.win95_gdi_text_current_position.y = (nv3->pgraph.win95_gdi_text.point_d.y); - } + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; + nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_d.y; + nv3->pgraph.win95_gdi_text_bit_count = 0; break; /* Type E: Two-colour 1bpp */ case NV3_W95TXT_E_CLIP_TOPLEFT: nv3->pgraph.win95_gdi_text.clip_e.left = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_e.top = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-E Clip Left,Top 0x%08x\n", nv3->pgraph.win95_gdi_text.clip_e.left, nv3->pgraph.win95_gdi_text.clip_e.top); break; case NV3_W95TXT_E_CLIP_BOTTOMRIGHT: nv3->pgraph.win95_gdi_text.clip_e.right = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.clip_e.bottom = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-E Clip Bottom,Right 0x%08x\n", nv3->pgraph.win95_gdi_text.clip_e.right, nv3->pgraph.win95_gdi_text.clip_e.bottom); /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ break; case NV3_W95TXT_E_CLIP_COLOR_0: @@ -127,11 +157,9 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.point_e.x = (param & 0xFFFF); nv3->pgraph.win95_gdi_text.point_e.y = ((param >> 16) & 0xFFFF); - uint16_t large_start = (nv3->pgraph.win95_gdi_text.size_in_e.w >> 1) - 1; - - //nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_e.x + large_start); nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x; nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_e.y; + nv3->pgraph.win95_gdi_text_bit_count = 0; nv_log("Method Execution: GDI-E Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y); break; @@ -139,9 +167,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* Type A submission: these are the same things as rectangles */ if (method_id >= NV3_W95TXT_A_RECT_START && method_id <= NV3_W95TXT_A_RECT_END) { - uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; + uint32_t index = (method_id - NV3_W95TXT_A_RECT_START) >> 3; - // IN THIS ONE SPECIFIC PLACE, ****AND ONLY THIS ONE SPECIFIC PLACE****, X AND Y ARE SWAPPED???? */ // If the size is submitted, render it. if (method_id & 0x04) @@ -149,8 +176,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.rect_a_size[index].w = (param >> 16) & 0xFFFF; nv3->pgraph.win95_gdi_text.rect_a_size[index].h = param & 0xFFFF; - nv_log("Method Execution: Rect GDI-A%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, - nv3->pgraph.win95_gdi_text.rect_a_size[index].h, nv3->pgraph.win95_gdi_text.color_a); + nv_log("Method Execution: Rect GDI-A%d Size=%d,%d", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, + nv3->pgraph.win95_gdi_text.rect_a_size[index].h); nv3_render_rect(nv3->pgraph.win95_gdi_text.rect_a_position[index], nv3->pgraph.win95_gdi_text.rect_a_size[index], nv3->pgraph.win95_gdi_text.color_a, grobj); @@ -163,14 +190,62 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: Rect GDI-A%d Position=%d,%d\n", index, nv3->pgraph.win95_gdi_text.rect_a_position[index].x, nv3->pgraph.win95_gdi_text.rect_a_position[index].y); } + return; } + /* Type B: Clipped Rectangle */ + else if (method_id >= NV3_W95TXT_B_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_B_CLIP_CLIPRECT_END) + { + uint32_t index = (method_id - NV3_W95TXT_B_CLIP_CLIPRECT_START) >> 3; + + /* Works slightly differently, we define the bounds of the rectangle instead. */ + if (method_id & 0x04) + { + nv3->pgraph.win95_gdi_text.clipped_rect[index].right = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clipped_rect[index].bottom = ((param >> 16) & 0xFFFF); + + nv_log("Method Execution: Rect GDI-B%d Right,Bottom=%d,%d\n", index, nv3->pgraph.win95_gdi_text.clipped_rect[index].right, + nv3->pgraph.win95_gdi_text.clipped_rect[index].bottom); + + nv3_render_rect_clipped(nv3->pgraph.win95_gdi_text.clipped_rect[index], + nv3->pgraph.win95_gdi_text.color_b, grobj); + } + else // left,top + { + nv3->pgraph.win95_gdi_text.clipped_rect[index].left = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.clipped_rect[index].top = ((param >> 16) & 0xFFFF); + + nv_log("Method Execution: Rect GDI-B%d Left,Top=%d,%d\n", index, + nv3->pgraph.win95_gdi_text.clipped_rect[index].left, nv3->pgraph.win95_gdi_text.clipped_rect[index].top); + } + + return; + } + /* Type C */ + else if (method_id >= NV3_W95TXT_C_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_C_CLIP_CLIPRECT_END) + { + /* lol */ + uint32_t index = (method_id - NV3_W95TXT_C_CLIP_CLIPRECT_START) >> 3; + + nv3->pgraph.win95_gdi_text.bitmap_c[index] = param; + + /* Mammoth logger! */ + nv_log("Method Execution: Rect GDI-C%d Data=%08x Size%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", + index, param, nv3->pgraph.win95_gdi_text.size_c.w, nv3->pgraph.win95_gdi_text.size_c.h, + nv3->pgraph.win95_gdi_text.point_c.x, nv3->pgraph.win95_gdi_text.point_c.y, + nv3->pgraph.win95_gdi_text.color1_c, + nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.right, + nv3->pgraph.win95_gdi_text.clip_c.top, nv3->pgraph.win95_gdi_text.clip_c.bottom); + + nv3_render_gdi_transparent_bitmap(false, nv3->pgraph.win95_gdi_text.color1_c, nv3->pgraph.win95_gdi_text.bitmap_c[index], grobj); + return; + } else if (method_id >= NV3_W95TXT_D_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_D_CLIP_CLIPRECT_END) { /* lol */ uint32_t index = (method_id - NV3_W95TXT_D_CLIP_CLIPRECT_START) >> 3; - nv3->pgraph.win95_gdi_text.mono_color1_d[index] = param; + nv3->pgraph.win95_gdi_text.bitmap_d[index] = param; /* Mammoth logger! */ nv_log("Method Execution: Rect GDI-D%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", @@ -178,9 +253,10 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.size_out_d.w, nv3->pgraph.win95_gdi_text.size_out_d.h, nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y, nv3->pgraph.win95_gdi_text.color1_d, - nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.right, nv3->pgraph.win95_gdi_text.clip_d.top, nv3->pgraph.win95_gdi_text.clip_d.bottom); + nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.right, + nv3->pgraph.win95_gdi_text.clip_d.top, nv3->pgraph.win95_gdi_text.clip_d.bottom); - nv3_render_gdi_type_d(grobj, nv3->pgraph.win95_gdi_text.mono_color1_d[index]); + nv3_render_gdi_transparent_bitmap(true, nv3->pgraph.win95_gdi_text.color1_d, nv3->pgraph.win95_gdi_text.bitmap_d[index], grobj); return; } else if (method_id >= NV3_W95TXT_E_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_E_CLIP_CLIPRECT_END) @@ -188,7 +264,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* lol */ uint32_t index = (method_id - NV3_W95TXT_E_CLIP_CLIPRECT_START) >> 3; - nv3->pgraph.win95_gdi_text.mono_color1_d[index] = param; + nv3->pgraph.win95_gdi_text.bitmap_e[index] = param; /* Mammoth logger! */ nv_log("Method Execution: Rect GDI-E%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", @@ -198,7 +274,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.win95_gdi_text.color1_e, nv3->pgraph.win95_gdi_text.clip_e.left, nv3->pgraph.win95_gdi_text.clip_e.right, nv3->pgraph.win95_gdi_text.clip_e.top, nv3->pgraph.win95_gdi_text.clip_e.bottom); - nv3_render_gdi_type_e(grobj, nv3->pgraph.win95_gdi_text.mono_color1_d[index]); + nv3_render_gdi_1bpp_bitmap(nv3->pgraph.win95_gdi_text.color0_e, nv3->pgraph.win95_gdi_text.color1_e, nv3->pgraph.win95_gdi_text.bitmap_e[index], grobj); return; } diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 4695d05b7..487f41731 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -46,140 +46,307 @@ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t co } } -void nv3_render_text_1bpp(bool bit, nv3_grobj_t grobj) +/* Render GDI-B clipped rectangle */ +void nv3_render_rect_clipped(nv3_clip_16_t clip, uint32_t color, nv3_grobj_t grobj) { - uint16_t clip_x = nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_out_d.w; - uint16_t clip_y = nv3->pgraph.win95_gdi_text.point_d.y + nv3->pgraph.win95_gdi_text.size_out_d.h; + nv3_position_16_t current_pos = {0}; - /* they send more data than they need */ - if (nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) - bit = false; - - uint32_t final_color; - - // if it's a 0 bit we don't need to do anything - if (bit) + for (int32_t y = clip.top; y < clip.bottom; y++) { - switch (nv3->nvbase.svga.bpp) + current_pos.y = y; + + for (int32_t x = clip.left; x < clip.right; x++) { - case 8: - final_color = (nv3->pgraph.win95_gdi_text.color1_d & 0xFF); /* do we need to add anything? mul blend perhaps? */ - break; - case 15: - case 16: - final_color = (nv3->pgraph.win95_gdi_text.color1_d & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ - break; - case 32: - final_color = (nv3->pgraph.win95_gdi_text.color1_d); /* do we need to add anything? mul blend perhaps? */ - break; + current_pos.x = x; + + /* compare against the global clip too */ + if (current_pos.x >= nv3->pgraph.win95_gdi_text.clip_b.left + && current_pos.x <= nv3->pgraph.win95_gdi_text.clip_b.right + && current_pos.y >= nv3->pgraph.win95_gdi_text.clip_b.top + && current_pos.y <= nv3->pgraph.win95_gdi_text.clip_b.bottom) + { + nv3_render_write_pixel(current_pos, color, grobj); + } } } +} - /* in type d colour0 is always transparent */ - if (bit) - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color, grobj); - - /* increment the position - the bitmap is stored horizontally backward */ - nv3->pgraph.win95_gdi_text_current_position.x--; - - /* check if we need to go down a line */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.point_d.x) +void nv3_render_gdi_transparent_bitmap_blit(bool bit, bool clip, uint32_t color, nv3_grobj_t grobj) +{ + /* If the bit is set, and cliping is enabled (Type D) tru and lcip */ + if (bit && clip) { - nv3->pgraph.win95_gdi_text_current_position.x = (nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w - 1); - - nv3->pgraph.win95_gdi_text_current_position.y++; + /* Turn the bit off if we need to clip (Type D ) */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left + || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right + || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top + || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) + { + bit = false; + } + + /* + Also clip if we are outside of the SIZE_OUT range + We only need to do this in one direction just to get rid of the crud sent by NV + */ + uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_out_d.w); + uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_d.y + (nv3->pgraph.win95_gdi_text.size_out_d.h); + + if (nv3->pgraph.win95_gdi_text_current_position.x >= clip_x + || nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) + bit = false; } - /* check if we are in the clipping rectangle */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left - || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right - || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top - || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) + /* We don't need to and it, because it seems the Riva only uses non-packed bpp formats for this class */ + if (bit) + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, color, grobj); + + /* + Check if we've reached the bottom + Because we check the bits in reverse, we go forward (bits 7,6,5 were set for a 1x3 bitmap) + */ + + uint32_t end_x = (clip) ? nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w : nv3->pgraph.win95_gdi_text.point_c.x + nv3->pgraph.win95_gdi_text.size_c.w; + + nv3->pgraph.win95_gdi_text_current_position.x++; + + if (nv3->pgraph.win95_gdi_text_current_position.x >= end_x) { + nv3->pgraph.win95_gdi_text_current_position.y++; + + if (!clip) + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_c.x; + else + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; + } +} + +/* Originally written 23 March 2025, but then, redone, properly, on 30 March 2025 */ +void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitmap_data, nv3_grobj_t grobj) +{ + /* + First, we need to figure out how many bits we have left. + If we have less than 32, don't process all of the bits. + + Bits are processed in the following order: [7-0] [15-8] [23-16] [31-24] + TODO: Store this somewhere, so it doesn't need to be recalculated. + + We store a global bit count for this purpose. + */ + + uint32_t bitmap_size = (clip) ? nv3->pgraph.win95_gdi_text.size_in_d.w * nv3->pgraph.win95_gdi_text.size_in_d.h : nv3->pgraph.win95_gdi_text.size_c.w * nv3->pgraph.win95_gdi_text.size_c.h; + uint32_t bits_remaining_in_bitmap = bitmap_size - nv3->pgraph.win95_gdi_text_bit_count; + + /* we have to interpret every bit in reverse bit order but in the right byte order */ + + bool current_bit = false; + + /* Start by rendering bits 7 through 0 */ + for (int32_t bit = 7; bit >= 0; bit--) + { + current_bit = (bitmap_data >> bit) & 0x01; + + nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; + } + + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) return; - } -} -void nv3_render_gdi_type_d(nv3_grobj_t grobj, uint32_t param) -{ - // reset when a position is submitted - nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; - - /* Go through the bitmap that was sent, bit by bit. */ - for (int32_t bit_num = 0; bit_num <= 31; bit_num++) + /* Now for 15 through 8 */ + for (int32_t bit = 15; bit >= 8; bit--) { - bool bit = (param >> bit_num) & 0x01; + current_bit = (bitmap_data >> bit) & 0x01; - nv3_render_text_1bpp(bit, grobj); + nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; } -} -/* 2-colour 1bpp color-expanded text from [7-0] */ -void nv3_render_text_1bpp_2color(uint32_t byte, nv3_grobj_t grobj) -{ - for (int32_t bit_num = 0; bit_num <= 7; bit_num++) + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; + + /* Now for 23 through 16 */ + for (int32_t bit = 23; bit >= 16; bit--) { - bool bit = (byte >> bit_num) & 0x01; + current_bit = (bitmap_data >> bit) & 0x01; - uint16_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_out_e.w; - uint16_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + nv3->pgraph.win95_gdi_text.size_out_e.h; - - // if it's a 0 bit we don't need to do anything - - uint32_t final_color; - - switch (nv3->nvbase.svga.bpp) - { - case 8: - final_color = (bit) ? (nv3->pgraph.win95_gdi_text.color1_e & 0xFF) : (nv3->pgraph.win95_gdi_text.color0_e & 0xFF); /* do we need to add anything? mul blend perhaps? */ - break; - case 15: - case 16: - final_color = (bit) ? (nv3->pgraph.win95_gdi_text.color1_e & 0xFFFF) : (nv3->pgraph.win95_gdi_text.color0_e & 0xFFFF); /* do we need to add anything? mul blend perhaps? */ - break; - case 32: - final_color = (bit) ? nv3->pgraph.win95_gdi_text.color1_e : nv3->pgraph.win95_gdi_text.color0_e; /* do we need to add anything? mul blend perhaps? */ - break; - } + nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, final_color, grobj); - - /* increment the position - the bitmap is stored horizontally backward */ - nv3->pgraph.win95_gdi_text_current_position.x--; - - /* see if we need to go to the next line */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.point_e.x) - { - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_out_e.w - 1); - nv3->pgraph.win95_gdi_text_current_position.y++; - } - - /* check if we are in the clipping rectangle */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_e.left - || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_e.right - || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_e.top - || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_e.bottom) - { - return; - } + if (!bits_remaining_in_bitmap) + break; } - + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; + + /* Now for 31 through 24 */ + for (int32_t bit = 31; bit >= 24; bit--) + { + current_bit = (bitmap_data >> bit) & 0x01; + + nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; + } + + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; } -void nv3_render_gdi_type_e(nv3_grobj_t grobj, uint32_t param) +void nv3_render_gdi_1bpp_bitmap_blit(bool bit, uint32_t color0, uint32_t color1, nv3_grobj_t grobj) { - // reset when a position is submitted - nv3_position_16_t start_position = nv3->pgraph.win95_gdi_text_current_position; + /* We can't force the bit off because this is a 1bpp bitmap */ + bool skip = false; - /* we have to interpret every bit in reverse order but in the right bit order */ - uint8_t byte0 = ((param & 0xFF000000) >> 24); - uint8_t byte1 = ((param & 0xFF0000) >> 16); - uint8_t byte2 = ((param & 0xFF00) >> 8); - uint8_t byte3 = (param & 0xFF); + /* For Type E, always clip */ + /* Turn the bit off if we need to clip (Type D ) */ + if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_e.left + || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_e.right + || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_e.top + || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_e.bottom) + { + skip = true; + } - nv3_render_text_1bpp_2color(byte0, grobj); - nv3_render_text_1bpp_2color(byte1, grobj); - nv3_render_text_1bpp_2color(byte2, grobj); - nv3_render_text_1bpp_2color(byte3, grobj); + /* + Also clip if we are outside of the SIZE_OUT range + We only need to do this in one direction just to get rid of the crud sent by NV + */ + uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_out_e.w); + uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + (nv3->pgraph.win95_gdi_text.size_out_e.h); + + if (nv3->pgraph.win95_gdi_text_current_position.x >= clip_x + || nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) + skip = true; + + /* We don't need to and it, because it seems the Riva only uses non-packed bpp formats for this class */ + if (!skip) + { + if (bit) + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, nv3->pgraph.win95_gdi_text.color1_e, grobj); + else + nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, nv3->pgraph.win95_gdi_text.color0_e, grobj); + } + + + /* + Check if we've reached the bottom, if so, advance to the next horizontal lin + Because we check the bits in reverse, we go forward (bits 7,6,5 were set for a 1x3 bitmap) + */ + + uint32_t end_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_in_e.w; + + nv3->pgraph.win95_gdi_text_current_position.x++; + + if (nv3->pgraph.win95_gdi_text_current_position.x >= end_x) + { + nv3->pgraph.win95_gdi_text_current_position.y++; + nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x; + } +} + +/* Originally written 23 March 2025, but then, redone, properly, on 30 March 2025 */ +void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj) +{ + /* + First, we need to figure out how many bits we have left. + If we have less than 32, don't process all of the bits. + + Bits are processed in the following order: [7-0] [15-8] [23-16] [31-24] + TODO: Store this somewhere, so it doesn't need to be recalculated. + + We store a global bit count for this purpose. + */ + + uint32_t bitmap_size = nv3->pgraph.win95_gdi_text.size_in_e.w * nv3->pgraph.win95_gdi_text.size_in_e.h; + uint32_t bits_remaining_in_bitmap = bitmap_size - nv3->pgraph.win95_gdi_text_bit_count; + + /* we have to interpret every bit in reverse bit order but in the right byte order */ + + bool current_bit = false; + + /* Start by rendering bits 7 through 0 */ + for (int32_t bit = 7; bit >= 0; bit--) + { + current_bit = (bitmap_data >> bit) & 0x01; + + nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; + } + + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; + + /* Now for 15 through 8 */ + for (int32_t bit = 15; bit >= 8; bit--) + { + current_bit = (bitmap_data >> bit) & 0x01; + + nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; + } + + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; + + /* Now for 23 through 16 */ + for (int32_t bit = 23; bit >= 16; bit--) + { + current_bit = (bitmap_data >> bit) & 0x01; + + nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; + } + + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; + + /* Now for 31 through 24 */ + for (int32_t bit = 31; bit >= 24; bit--) + { + current_bit = (bitmap_data >> bit) & 0x01; + + nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); + nv3->pgraph.win95_gdi_text_bit_count++; + bits_remaining_in_bitmap--; + + if (!bits_remaining_in_bitmap) + break; + } + + /* IF we're done, let's return */ + if (!bits_remaining_in_bitmap) + return; } \ No newline at end of file From 7c4e2c82d41a3e5b198ac178b9a07c1fbf2bb505 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 3 Apr 2025 01:40:59 +0100 Subject: [PATCH 157/274] Split up logs into two verbosity levels (one is just init/invalid regs/object submission/pci, everything else is verbose_only) --- doc/nvidia_notes/status.xlsx | Bin 15983 -> 16043 bytes src/include/86box/nv/vid_nv.h | 3 + src/include/86box/nv/vid_nv3.h | 6 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 4 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 24 +++--- src/video/nv/nv3/nv3_core.c | 32 +++----- src/video/nv/nv3/render/nv3_render_core.c | 13 ++-- src/video/nv/nv3/subsystems/nv3_pbus.c | 16 ++-- src/video/nv/nv3/subsystems/nv3_pextdev.c | 16 ++-- src/video/nv/nv3/subsystems/nv3_pfb.c | 29 ++++--- src/video/nv/nv3/subsystems/nv3_pfifo.c | 73 +++++++++--------- src/video/nv/nv3/subsystems/nv3_pgraph.c | 24 +++--- src/video/nv/nv3/subsystems/nv3_pmc.c | 26 +++---- src/video/nv/nv3/subsystems/nv3_pme.c | 12 +-- src/video/nv/nv3/subsystems/nv3_pramdac.c | 18 +++-- src/video/nv/nv3/subsystems/nv3_pramin.c | 28 +++---- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 4 +- .../nv/nv3/subsystems/nv3_pramin_ramht.c | 6 +- .../nv/nv3/subsystems/nv3_pramin_ramro.c | 9 +-- src/video/nv/nv3/subsystems/nv3_ptimer.c | 14 ++-- src/video/nv/nv3/subsystems/nv3_pvideo.c | 16 ++-- src/video/nv/nv3/subsystems/nv3_user.c | 6 +- src/video/nv/nv_base.c | 51 ++++++++---- 23 files changed, 219 insertions(+), 211 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index 6fc2aaa7411f99190fe376bd6114dfa499f86c48..1ddb8b34dbfc1e4e750f4992b5d7e696dbe20b39 100644 GIT binary patch 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void nv_log(const char *fmt, ...); +// Verbose logging level. +void nv_log_verbose_only(const char *fmt, ...); + // Defines common to all NV chip architectural generations // PCI IDs diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 1957984d2..411ccdecf 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 26 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 2 April 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -1605,7 +1605,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value); void nv3_pfifo_interrupt(uint32_t id, bool fire_now); // NV3 PFIFO - Caches -void nv3_pfifo_cache0_push(); +//cache0_push not a thing void nv3_pfifo_cache0_pull(); void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val); void nv3_pfifo_cache1_pull(); @@ -1641,4 +1641,4 @@ void nv3_ptimer_tick(double real_time); void nv3_pvideo_init(); // NV3 PME (Mediaport) -void nv3_pmedia_init(); \ No newline at end of file +void nv3_pme_init(); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index b75a8e546..4a6d2e39c 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -64,8 +64,8 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* This is technically its own thing, but I don't know if it's ever a problem with how we've designed it */ if (nv3->pgraph.notify_pending) { - nv_log("M2MF notification with notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); - nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); + nv_log("WARNING: M2MF notification with notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); + nv_log("IF THIS BUILD WAS COMPILED WITH NV_LOG_ENABLE_ULTRA, YOU SHOULD SEE A CONTEXT BELOW"); nv3_debug_ramin_print_context_info(param, context); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 01f0e90c7..0ec7cdd2d 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -112,33 +112,33 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t // This code is temporary and will probably be moved somewhere else // Print torns of debug info #ifdef DEBUG - nv_log("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); + nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); - nv_log("Notification Information:\n"); - nv_log("Adjust Value: 0x%08x\n", info_adjust); - (info_pt_present) ? nv_log("Pagetable Present: True\n") : nv_log("Pagetable Present: False\n"); + nv_log_verbose_only("Notification Information:\n"); + nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust); + (info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n"); switch (info_notification_target) { case NV3_NOTIFICATION_TARGET_NVM: - nv_log("Notification Target: VRAM\n"); + nv_log_verbose_only("Notification Target: VRAM\n"); break; case NV3_NOTIFICATION_TARGET_CART: - nv_log("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); + nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); break; case NV3_NOTIFICATION_TARGET_PCI: - (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log("Notification Target: PCI Bus\n") : nv_log("Notification Target: PCI Bus (On AGP card?)\n"); + (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); break; case NV3_NOTIFICATION_TARGET_AGP: (nv3->nvbase.bus_generation == nv_bus_agp_1x - || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log("Notification Target: AGP Bus\n") : nv_log("Notification Target: AGP Bus (On PCI card?)\n"); + || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); break; } - nv_log("Limit: 0x%08x\n", notify_obj_limit); - (page_is_present) ? nv_log("Page is present\n") : nv_log("Page is not present\n"); - (page_is_readwrite) ? nv_log("Page is read-write\n") : nv_log("Page is read-only\n"); - nv_log("Pageframe Address: 0x%08x\n", frame_base); + nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit); + (page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n"); + (page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n"); + nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base); #endif // set up the dma transfer. we need to translate to a physical address. diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index a365cab62..610f8c500 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -72,9 +72,7 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3); - #ifdef ENABLE_NV_LOG_ULTRA - nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - #endif + nv_log_verbose_only("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); return ret; } @@ -100,9 +98,8 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) ret = nv3_svga_in(real_address, nv3) | (nv3_svga_in(real_address + 1, nv3) << 8); - //#ifdef ENABLE_NV_LOG_ULTRA - nv_log("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - //#endif + nv_log_verbose_only("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + return ret; } @@ -128,9 +125,7 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) | (nv3_svga_in(real_address + 2, nv3) << 16) | (nv3_svga_in(real_address + 3, nv3) << 24); - //#ifdef ENABLE_NV_LOG_ULTRA - nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - //#endif + nv_log_verbose_only("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); return ret; } @@ -155,9 +150,7 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - //#ifdef ENABLE_NV_LOG_ULTRA - nv_log("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - //#endif + nv_log_verbose_only("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); @@ -184,9 +177,8 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - //#ifdef ENABLE_NV_LOG_ULTRA - nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - //#endif + nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -214,9 +206,7 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - //#ifdef ENABLE_NV_LOG_ULTRA - nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - //#endif + nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_out(real_address, val & 0xFF, nv3); nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -1073,9 +1063,9 @@ void* nv3_init(const device_t *info) #endif nv_log("Initialising core\n"); -#ifdef ENABLE_NV_LOG_ULTRA - nv_log("ULTRA LOGGING enabled"); -#endif + // this will only be logged if ENABLE_NV_LOG_ULTRA is defined + nv_log_verbose_only("ULTRA LOGGING enabled"); + // Figure out which vbios the user selected const char* vbios_id = device_get_config_bios("vbios"); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 15c652e5b..66ee170bc 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -44,9 +44,8 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) // set the pixel format color_final.pixel_format = format; - #ifdef ENABLE_NV_LOG - nv_log("Expanding Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d", color, format, alpha_enabled); - #endif + nv_log_verbose_only("Expanding Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); + // default to fully opaque in case alpha is disabled color_final.a = 0xFF; @@ -112,9 +111,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co uint8_t format = (grobj.grobj_0 & 0x07); bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; - #ifdef ENABLE_NV_LOG - nv_log("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); - #endif + nv_log_verbose_only("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); uint32_t packed_color = 0x00; @@ -141,10 +138,10 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co packed_color |= (color.b << 10); break; case nv3_pgraph_pixel_format_y8: - nv_log("nv3_render_downconvert: Y8 not implemented"); + warning("nv3_render_downconvert: Y8 not implemented"); break; case nv3_pgraph_pixel_format_y16: - nv_log("nv3_render_downconvert: Y16 not implemented"); + warning("nv3_render_downconvert: Y16 not implemented"); break; default: warning("nv3_render_downconvert_color unknown format %d", format); diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 46d829fb2..67a052d50 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -54,7 +54,7 @@ uint32_t nv3_pbus_read(uint32_t address) // todo: friendly logging - nv_log("PBUS Read from 0x%08x", address); + nv_log_verbose_only("PBUS Read from 0x%08x", address); // if the register actually exists if (reg) @@ -79,9 +79,9 @@ uint32_t nv3_pbus_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -95,15 +95,15 @@ void nv3_pbus_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); - nv_log("PBUS Write 0x%08x -> 0x%08x\n", value, address); + nv_log_verbose_only("PBUS Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_write) @@ -174,7 +174,7 @@ uint8_t nv3_pbus_rma_read(uint16_t addr) } // log current location for vbios RE - nv_log("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", addr, real_final_address, ret); break; @@ -239,7 +239,7 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val) nv3->pbus.rma.data &= ~0xff000000; nv3->pbus.rma.data |= (val << 24); - nv_log("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + nv_log_verbose_only("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", addr, nv3->pbus.rma.addr, nv3->pbus.rma.data); if (nv3->pbus.rma.addr < NV3_MMIO_SIZE) diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index c26266a00..30ba68c03 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -89,11 +89,11 @@ uint32_t nv3_pextdev_read(uint32_t address) // special consideration for straps if (address == NV3_PSTRAPS) { - nv_log("Straps Read (current value=0x%08x)\n", nv3->pextdev.straps); + nv_log_verbose_only("Straps Read (current value=0x%08x)\n", nv3->pextdev.straps); } else { - nv_log("PEXTDEV Read from 0x%08x", address); + nv_log_verbose_only("PEXTDEV Read from 0x%08x", address); } // if the register actually exists @@ -113,9 +113,9 @@ uint32_t nv3_pextdev_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -129,12 +129,12 @@ void nv3_pextdev_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); - nv_log("PEXTDEV Write 0x%08x -> 0x%08x\n", value, address); + nv_log_verbose_only("PEXTDEV Write 0x%08x -> 0x%08x\n", value, address); // special consideration for straps if (address == NV3_PSTRAPS) { - nv_log("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps); + warning("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps); return; } @@ -142,9 +142,9 @@ void nv3_pextdev_write(uint32_t address, uint32_t value) if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_write) diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 0be3d14c8..0b36a3993 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -75,7 +75,7 @@ uint32_t nv3_pfb_read(uint32_t address) // todo: friendly logging - nv_log("PFB Read from 0x%08x", address); + nv_log_verbose_only("PFB Read from 0x%08x", address); // if the register actually exists if (reg) @@ -111,9 +111,9 @@ uint32_t nv3_pfb_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -127,15 +127,15 @@ void nv3_pfb_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); - nv_log("PFB Write 0x%08x -> 0x%08x", value, address); + nv_log_verbose_only("PFB Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_write) @@ -189,17 +189,16 @@ void nv3_pfb_config0_write(uint32_t val) // This doesn't actually seem very useful - #ifdef ENABLE_NV_LOG_ULTRA - nv_log("Framebuffer Config Change\n"); - nv_log("Horizontal Size=%d pixels\n", new_pfb_htotal); - nv_log("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); + + nv_log_verbose_only("Framebuffer Config Change\n"); + nv_log_verbose_only("Horizontal Size=%d pixels\n", new_pfb_htotal); + nv_log_verbose_only("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) - nv_log("Bit Depth=8bpp\n"); + nv_log_verbose_only("Bit Depth=8bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP) - nv_log("Bit Depth=16bpp\n"); + nv_log_verbose_only("Bit Depth=16bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_32BPP) - nv_log("Bit Depth=32bpp\n"); - #endif - + nv_log_verbose_only("Bit Depth=32bpp\n"); + } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 55ec21e19..6195c0639 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -101,7 +101,7 @@ uint32_t nv3_pfifo_read(uint32_t address) // todo: friendly logging - nv_log("PFIFO Read from 0x%08x", address); + nv_log_verbose_only("PFIFO Read from 0x%08x", address); // if the register actually exists if (reg) @@ -278,9 +278,9 @@ uint32_t nv3_pfifo_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } /* Handle some special memory areas */ else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) @@ -288,24 +288,26 @@ uint32_t nv3_pfifo_read(uint32_t address) uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; ret = nv3->pfifo.cache1_settings.context[ctx_entry_id]; - nv_log("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x\n", ctx_entry_id, ret); + nv_log_verbose_only("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x\n", ctx_entry_id, ret); } /* Direct cache read stuff */ else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { - nv_log("PFIFO Cache0 Read\n"); + nv_log_verbose_only("PFIFO Cache0 Read\n"); // See if we want the object name or the channel/subchannel information. if (address & 4) { - nv_log("Data=0x%08x\n", nv3->pfifo.cache0_entry.data); + nv_log_verbose_only("Data=0x%08x\n", nv3->pfifo.cache0_entry.data); + return nv3->pfifo.cache0_entry.data; } else { uint32_t final = nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); - nv_log("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); + nv_log_verbose_only("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); + return final; } @@ -320,19 +322,19 @@ uint32_t nv3_pfifo_read(uint32_t address) slot = (address >> 3) & 0x3F; else slot = (address >> 3) & 0x1F; - - nv_log("PFIFO Cache1 Read slot=%d", slot); + + nv_log_verbose_only("PFIFO Cache1 Read slot=%d", slot); // See if we want the object name or the channel/subchannel information. if (address & 4) { - nv_log("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data); + nv_log_verbose_only("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data); return nv3->pfifo.cache1_entries[slot].data; } else { uint32_t final = nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); - nv_log("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); + nv_log_verbose_only("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); return final; } @@ -392,7 +394,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - nv_log("PFIFO Write 0x%08x -> 0x%08x", val, address); + nv_log_verbose_only("PFIFO Write 0x%08x -> 0x%08x", val, address); // if the register actually exists if (reg) @@ -571,18 +573,18 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) } if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) { - nv_log("PFIFO Cache0 Write\n"); + nv_log_verbose_only("PFIFO Cache0 Write\n"); // 3104 always written after 3100 if (address & 4) { - nv_log("Name = 0x%08x\n", val); + nv_log_verbose_only("Name = 0x%08x\n", val); nv3->pfifo.cache0_entry.data = val; nv3_pfifo_cache0_pull(); // immediately pull out } @@ -590,7 +592,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) { nv3->pfifo.cache0_entry.method = (val & 0x1FFC); nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; - nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache0_entry.subchannel, nv3->pfifo.cache0_entry.method); + nv_log_verbose_only("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache0_entry.subchannel, nv3->pfifo.cache0_entry.method); } } @@ -606,19 +608,19 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) uint32_t real_entry = nv3_pfifo_cache1_normal2gray(slot); - nv_log("Cache1 Write Slot %d (Gray code)", real_entry); + nv_log_verbose_only("Cache1 Write Slot %d (Gray code)", real_entry); // See if we want the object name or the channel/subchannel information. if (address & 4) { - nv_log("Name = 0x%08x\n", val); + nv_log_verbose_only("Name = 0x%08x\n", val); nv3->pfifo.cache1_entries[real_entry].data = val; } else { nv3->pfifo.cache1_entries[real_entry].method = (val & 0x1FFC); nv3->pfifo.cache1_entries[real_entry].subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; - nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method); + nv_log_verbose_only("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method); } } /* Handle some special memory areas */ @@ -627,7 +629,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; nv3->pfifo.cache1_settings.context[ctx_entry_id] = val; - nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val); + nv_log_verbose_only("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val); } else /* Completely unknown */ { @@ -689,11 +691,10 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) return nv3_pfifo_cache1_binary_code_table[val]; } -// Submits graphics objects INTO cache0 -void nv3_pfifo_cache0_push() -{ - -} +/* +You can't push into cache0 on the real hardware, but it's not practically done because Cache0 is meant to be reserved for software objects, +NV_USER writes always go to CACHE1 +*/ // Pulls graphics objects OUT of cache0 void nv3_pfifo_cache0_pull() @@ -740,9 +741,9 @@ void nv3_pfifo_cache0_pull() nv3->pfifo.cache0_settings.get_address ^= 0x04; #ifndef RELEASE_BUILD - #ifdef ENABLE_NV_LOG_ULTRA - nv_log("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n"); - #endif + + nv_log_verbose_only("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n"); + nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; @@ -757,7 +758,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel) { /* Send our contexts to RAMFC. Load the new ones from RAMFC. */ if (new_channel >= NV3_DMA_CHANNELS) - fatal("Tried to switch to invalid dma channel"); + fatal("nv3_pfifo_context_switch: Tried to switch to invalid dma channel"); uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF; @@ -832,7 +833,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) // Did we fuck up? if (oh_shit) { - nv_log("WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset); + nv_log("OH CRAP: Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x", + oh_shit_reason, channel, subchannel, method_offset); nv3_ramro_write(nv3->pfifo.runout_put, new_address); nv3_ramro_write(nv3->pfifo.runout_put + 4, param); @@ -878,7 +880,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; - nv_log("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", + nv_log_verbose_only("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", channel, subchannel, param, method_offset, nv3->pfifo.cache1_settings.put_address); // Now we're done. Phew! @@ -918,7 +920,7 @@ void nv3_pfifo_cache1_pull() //bit23 set=hardware if (!(current_context & 0x800000)) { - nv_log("The object in CACHE1 is a software object\n"); + nv_log_verbose_only("The object in CACHE1 is a software object\n"); nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; @@ -939,9 +941,8 @@ void nv3_pfifo_cache1_pull() #ifndef RELEASE_BUILD - #ifdef ENABLE_NV_LOG_ULTRA - nv_log("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n"); - #endif + nv_log_verbose_only("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n"); + nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index ece125b0f..82ad95706 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -108,7 +108,7 @@ uint32_t nv3_pgraph_read(uint32_t address) // todo: friendly logging - nv_log("PGRAPH Read from 0x%08x", address); + nv_log_verbose_only("PGRAPH Read from 0x%08x", address); // if the register actually exists if (reg) @@ -262,9 +262,9 @@ uint32_t nv3_pgraph_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -275,7 +275,7 @@ uint32_t nv3_pgraph_read(uint32_t address) // Addresses should be aligned to 4 bytes. uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); - nv_log("PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); + nv_log_verbose_only("PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); } else /* Completely unknown */ { @@ -297,15 +297,11 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); - nv_log("PGRAPH Write 0x%08x -> 0x%08x\n", value, address); + nv_log_verbose_only("PGRAPH Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); // on-read function if (reg->on_write) @@ -467,6 +463,12 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) } } + + if (reg->friendly_name) + nv_log_verbose_only(": %s\n", reg->friendly_name); + else + nv_log_verbose_only("\n"); + } else { @@ -477,7 +479,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // Addresses should be aligned to 4 bytes. uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); - nv_log("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value); + nv_log_verbose_only("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value); nv3->pgraph.context_cache[entry] = value; } else /* Completely unknown */ @@ -524,7 +526,7 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe grobj.grobj_2 = nv3_ramin_read32(real_ramin_base + 8, nv3); grobj.grobj_3 = nv3_ramin_read32(real_ramin_base + 12, nv3); - nv_log("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", + nv_log_verbose_only("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", method, param, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); /* Methods below 0x104 are shared across all classids, so call generic_method for that*/ diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index de1c21f24..050af07fa 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -60,7 +60,7 @@ nv_register_t pmc_registers[] = { uint32_t nv3_pmc_clear_interrupts() { - nv_log("Clearing IRQs\n"); + nv_log_verbose_only("Clearing IRQs\n"); pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } @@ -144,21 +144,21 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now) { if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE) { - nv_log("Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); + nv_log_verbose_only("Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } else - nv_log("NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); + nv_log_verbose_only("NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); } else { if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_SOFTWARE) { - nv_log("Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); + nv_log_verbose_only("Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); } else - nv_log("NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); + nv_log_verbose_only("NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); } } @@ -178,7 +178,7 @@ uint32_t nv3_pmc_read(uint32_t address) uint32_t ret = 0x00; // todo: friendly logging - nv_log("PMC Read from 0x%08x", address); + nv_log_verbose_only("PMC Read from 0x%08x", address); // if the register actually exists if (reg) @@ -194,7 +194,7 @@ uint32_t nv3_pmc_read(uint32_t address) ret = nv3->pmc.boot; break; case NV3_PMC_INTERRUPT_STATUS: - nv_log("\n"); // clear_interrupts logs + nv_log_verbose_only("\n"); // clear_interrupts logs nv3_pmc_clear_interrupts(); ret = nv3_pmc_handle_interrupts(false); @@ -211,9 +211,9 @@ uint32_t nv3_pmc_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -227,7 +227,7 @@ void nv3_pmc_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); - nv_log("PMC Write 0x%08x -> 0x%08x", value, address); + nv_log_verbose_only("PMC Write 0x%08x -> 0x%08x", value, address); // if the register actually exists... if (reg) @@ -245,7 +245,7 @@ void nv3_pmc_write(uint32_t address, uint32_t value) // This can only be done by software interrupts... if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF)) { - nv_log("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger " + warning("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger " " an interrupt on, rather than writing to NV3_PMC_INTERRUPT_STATUS (Or this is a bug)...NV3_PMC_INTERRUPT_STATUS=0x%08x)\n", nv3->pmc.interrupt_enable); return; } @@ -264,9 +264,9 @@ void nv3_pmc_write(uint32_t address, uint32_t value) } if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else /* Completely unknown */ diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index d7f6f0cf9..b18797a65 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -49,7 +49,7 @@ uint32_t nv3_pme_read(uint32_t address) // todo: friendly logging - nv_log("PME Read from 0x%08x", address); + nv_log_verbose_only("PME Read from 0x%08x", address); // if the register actually exists if (reg) @@ -77,9 +77,9 @@ uint32_t nv3_pme_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -93,15 +93,15 @@ void nv3_pme_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); - nv_log("PME Write 0x%08x -> 0x%08x\n", value, address); + nv_log_verbose_only("PME Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_write) diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index fb83ffaf1..0e41807a0 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -223,7 +223,7 @@ uint32_t nv3_pramdac_read(uint32_t address) // todo: friendly logging - nv_log("PRAMDAC Read from 0x%08x\n", address); + nv_log_verbose_only("PRAMDAC Read from 0x%08x\n", address); // if the register actually exists if (reg) @@ -288,9 +288,9 @@ uint32_t nv3_pramdac_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -304,15 +304,12 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) { nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); - nv_log("PRAMDAC Write 0x%08x -> 0x%08x\n", value, address); + nv_log_verbose_only("PRAMDAC Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) { - if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); - else - nv_log("\n"); + // on-read function if (reg->on_write) @@ -381,6 +378,11 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) break; } } + + if (reg->friendly_name) + nv_log_verbose_only(": %s\n", reg->friendly_name); + else + nv_log_verbose_only("\n"); } else /* Completely unknown */ { diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 2771d5d16..8556822f5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -61,7 +61,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv) if (!nv3_ramin_arbitrate_read(addr, &val)) // Oh well { val = (uint8_t)nv3->nvbase.svga.vram[addr]; - nv_log("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + nv_log_verbose_only("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); } return (uint8_t)val; @@ -87,7 +87,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) if (!nv3_ramin_arbitrate_read(addr, &val)) { val = (uint16_t)vram_16bit[addr]; - nv_log("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + nv_log_verbose_only("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); } return val; @@ -114,7 +114,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { val = vram_32bit[addr]; - nv_log("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr); + nv_log_verbose_only("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr); } return val; @@ -139,7 +139,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) if (!nv3_ramin_arbitrate_write(addr, val32)) { nv3->nvbase.svga.vram[addr] = val; - nv_log("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log_verbose_only("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); } @@ -165,7 +165,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) if (!nv3_ramin_arbitrate_write(addr, val32)) { vram_16bit[addr] = val; - nv_log("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log_verbose_only("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); } @@ -189,7 +189,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) if (!nv3_ramin_arbitrate_write(addr, val)) { vram_32bit[addr] = val; - nv_log("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); + nv_log_verbose_only("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); } } @@ -378,7 +378,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u // Why does this work? uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel) * bucket_entries * 8); - nv_log("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n", + nv_log_verbose_only("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n", ramht_cur_address, name, cache_num, channel, subchannel); bool found_object = false; @@ -503,13 +503,13 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context) { #ifndef RELEASE_BUILD - nv_log("Found object:\n"); - nv_log("Param: 0x%04x\n", name); + nv_log_verbose_only("Found object:\n"); + nv_log_verbose_only("Param: 0x%04x\n", name); - nv_log("Context:\n"); - nv_log("DMA Channel %d (0-7 valid)\n", context.channel); - nv_log("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); - nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); - nv_log("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); + nv_log_verbose_only("Context:\n"); + nv_log_verbose_only("DMA Channel %d (0-7 valid)\n", context.channel); + nv_log_verbose_only("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); + nv_log_verbose_only("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); + nv_log_verbose_only("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); #endif } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index fa0d5899c..51d33c9a6 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -30,10 +30,10 @@ uint32_t nv3_ramfc_read(uint32_t address) { - nv_log("RAMFC (Unused DMA channel context) Read (0x%04x)), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); + nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x)\n", address); } void nv3_ramfc_write(uint32_t address, uint32_t value) { - nv_log("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x)), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", value, address); + nv_log_verbose_only("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x)\n", value, address); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index cce1d74a9..d2d17d321 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -39,17 +39,17 @@ uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) // is this the right endianness? - nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel); + nv_log_verbose_only("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel); return hash; } uint32_t nv3_ramht_read(uint32_t address) { - nv_log("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); + nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); } void nv3_ramht_write(uint32_t address, uint32_t value) { - nv_log("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - UNIMPLEMENTED\n", value, address); + nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - UNIMPLEMENTED\n", value, address); } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 1209faa2f..692a10e91 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -30,15 +30,10 @@ uint32_t nv3_ramro_read(uint32_t address) { - nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), Probably shouldn't happenn\n", address); + nv_log("BIG Problem: RAM Runout (invalid dma object submission) Read (0x%04x)\n", address); } void nv3_ramro_write(uint32_t address, uint32_t value) { - nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), Probably shouldn't happenn", value, address); -} - -void nv3_ramro_send() -{ - + nv_log("BIG Problem: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x)", value, address); } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index c1b8a2576..3a882b5b8 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -82,7 +82,7 @@ void nv3_ptimer_tick(double real_time) // Only log on ptimer alarm. Otherwise, it's too much spam. if (nv3->ptimer.time >= nv3->ptimer.alarm) { - nv_log("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); + nv_log_verbose_only("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM); } } @@ -97,7 +97,7 @@ uint32_t nv3_ptimer_read(uint32_t address) if (address != NV3_PTIMER_TIME_0_NSEC && address != NV3_PTIMER_TIME_1_NSEC) { - nv_log("PTIMER Read from 0x%08x", address); + nv_log_verbose_only("PTIMER Read from 0x%08x", address); } uint32_t ret = 0x00; @@ -147,9 +147,9 @@ uint32_t nv3_ptimer_read(uint32_t address) && reg->address != NV3_PTIMER_TIME_1_NSEC) { if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } } else @@ -165,15 +165,15 @@ void nv3_ptimer_write(uint32_t address, uint32_t value) // before doing anything, check the subsystem enablement nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - nv_log("PTIMER Write 0x%08x -> 0x%08x", value, address); + nv_log_verbose_only("PTIMER Write 0x%08x -> 0x%08x", value, address); // if the register actually exists if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_write) diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index 6f72da719..c883ee7e5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -55,15 +55,15 @@ uint32_t nv3_pvideo_read(uint32_t address) // todo: friendly logging - nv_log("PVIDEO Read from 0x%08x", address); + nv_log_verbose_only("PVIDEO Read from 0x%08x", address); // if the register actually exists if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_read) @@ -95,9 +95,9 @@ uint32_t nv3_pvideo_read(uint32_t address) } if (reg->friendly_name) - nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name); + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); } else { @@ -112,15 +112,15 @@ void nv3_pvideo_write(uint32_t address, uint32_t value) // before doing anything, check the subsystem enablement nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); - nv_log("PVIDEO Write 0x%08x -> 0x%08x\n", value, address); + nv_log_verbose_only("PVIDEO Write 0x%08x -> 0x%08x\n", value, address); // if the register actually exists if (reg) { if (reg->friendly_name) - nv_log(": %s\n", reg->friendly_name); + nv_log_verbose_only(": %s\n", reg->friendly_name); else - nv_log("\n"); + nv_log_verbose_only("\n"); // on-read function if (reg->on_write) diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c index 99091b5b7..f10e28793 100644 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ b/src/video/nv/nv3/subsystems/nv3_user.c @@ -40,8 +40,7 @@ uint32_t nv3_user_read(uint32_t address) uint8_t channel = (address - NV3_USER_START) / 0x10000; uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL; - nv_log("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset); - + nv_log_verbose_only("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset); // 0x10 is free CACHE1 object // TODO: THERE ARE OTHER STUFF! @@ -54,8 +53,7 @@ uint32_t nv3_user_read(uint32_t address) } - nv_log("IT'S NOT IMPLEMENTED!!!! offset=0x%04x\n", method_offset); - + nv_log("NV_USER READ: Channel FIELD NOT IMPLEMENTED!!!! offset=0x%04x\n", method_offset); return 0x00; }; diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index 185c46183..bce7425c2 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -50,31 +50,52 @@ void nv_log_set_device(void* device) nv_log_device = device; } -void nv_log(const char *fmt, ...) +void nv_log_internal(const char* fmt, va_list arg) { if (!nv_log_device) return; - va_list ap; - - if (nv_do_log) { - va_start(ap, fmt); - // If our debug config option is configured, full log. Otherwise log with cyclical detection. - #ifndef RELEASE_BUILD - if (nv_log_full) - log_out(nv_log_device, fmt, ap); - else - #endif - log_out_cyclic(nv_log_device, fmt, ap); - - va_end(ap); - } + if (nv_log_full) + log_out(nv_log_device, fmt, arg); + else + log_out_cyclic(nv_log_device, fmt, arg); + } + +void nv_log(const char *fmt, ...) +{ + va_list arg; + + if (!nv_do_log) + return; + + va_start(arg, fmt); + nv_log_internal(fmt, arg); + va_end(arg); +} + +void nv_log_verbose_only(const char *fmt, ...) +{ + #ifdef ENABLE_NV_LOG_ULTRA + if (!nv_do_log) + return; + + va_start(arg, fmt); + nv_log_internal(fmt, arg); + va_end(arg); + #endif +} + #else void nv_log(const char *fmt, ...) { + +} +void nv_log_verbose_only(const char *fmt, ...) +{ + } void nv_log_set_device(void* device) From 041dc284929b1bf5431011920493f1d723dec68e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 5 Apr 2025 14:44:01 +0100 Subject: [PATCH 158/274] Split src/destination buffers, use grobj --- CMakeLists.txt | 2 +- src/include/86box/nv/render/vid_nv3_render.h | 6 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- .../classes/nv3_class_01c_image_in_memory.c | 2 +- src/video/nv/nv3/render/nv3_render_blit.c | 77 ++++++------------- src/video/nv/nv3/render/nv3_render_core.c | 36 +++++++-- 6 files changed, 58 insertions(+), 67 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 1adcf4740..52f24f4b9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -138,7 +138,7 @@ option(DEV_BRANCH "Development branch" option(DISCORD "Discord Rich Presence support" ON) option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) # Remove when merged, should just be -D -option(NV_LOG "NVidia RIVA 128 debug logging" OFF) +option(NV_LOG "NVidia RIVA 128 debug logging" ON) option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" OFF) if (NV_LOG) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 9b5acd06d..00591e342 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -19,9 +19,9 @@ /* Core */ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); -uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj); -uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj); +uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); +uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); +uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 7bae42184..57184054d 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -54,7 +54,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y) return; - //nv3_render_blit_screen2screen(grobj); + nv3_render_blit_screen2screen(grobj); break; default: diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index dd5768103..af488dc09 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -31,7 +31,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { /* We need this for a lot of methods, so may as well store it here. */ - uint32_t src_buffer_id = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + uint32_t src_buffer_id = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; switch (method_id) { diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 032b23b47..3059aeccd 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -113,66 +113,37 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { - //nv3_position_16_t old_position = nv3->pgraph.blit.point_in + nv3->pgraph.blit.size.w; - nv3_position_16_t old_position = {0}; - old_position.x = nv3->pgraph.blit.point_in.x + nv3->pgraph.blit.size.w; - old_position.y = nv3->pgraph.blit.point_in.y + nv3->pgraph.blit.size.h; + nv3_position_16_t old_position = nv3->pgraph.blit.point_in; nv3_position_16_t new_position = nv3->pgraph.blit.point_out; uint16_t end_x = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); uint16_t end_y = (nv3->pgraph.blit.point_out.y + nv3->pgraph.blit.size.h); - /* Read the old pixel */ - switch (nv3->nvbase.svga.bpp) + uint32_t pixel_to_copy = 0x00; + + /* Read the old pixel and rewrite it to the new position */ + for (int32_t y = nv3->pgraph.blit.point_out.y; y <= end_y; y++) { - case 8: //8bpp - for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) + old_position.y = new_position.y = y; + + for (int32_t x = nv3->pgraph.blit.point_out.x; x <= end_x; x++) + { + old_position.x = new_position.x = x; + + switch (nv3->nvbase.svga.bpp) { - old_position.y++; - new_position.y++; - - for (int32_t x = nv3->pgraph.blit.point_out.x; x < end_x; x++) - { - old_position.x++; - new_position.x++; - - uint32_t pixel_to_copy = nv3_render_read_pixel_8(old_position, grobj) & 0xFF; - nv3_render_write_pixel(new_position, pixel_to_copy, grobj); - } + case 8: + pixel_to_copy = nv3_render_read_pixel_8(old_position, grobj, false) & 0xFF; + break; + case 15 ... 16: //15bpp and 16bpp modes are considered as identical + pixel_to_copy = nv3_render_read_pixel_16(old_position, grobj, false) & 0xFFFF; + break; + case 32: + pixel_to_copy = nv3_render_read_pixel_32(old_position, grobj, false); + break; } - break; - case 15: - case 16: //16bpp - for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) - { - old_position.y++; - new_position.y++; - for (int32_t x = nv3->pgraph.blit.point_out.x; x >= end_x; x++) - { - old_position.x++; - new_position.x++; - - uint32_t pixel_to_copy = nv3_render_read_pixel_16(old_position, grobj) & 0xFFFF; - nv3_render_write_pixel(new_position, pixel_to_copy, grobj); - } - } - break; - case 32: //32bpp - for (int32_t y = nv3->pgraph.blit.point_out.y; y < end_y; y++) - { - old_position.y++; - new_position.y++; - - for (int32_t x = nv3->pgraph.blit.point_out.x; x >= end_x; x++) - { - old_position.x++; - new_position.x++; - - uint32_t pixel_to_copy = nv3_render_read_pixel_32(old_position, grobj); - nv3_render_write_pixel(new_position, pixel_to_copy, grobj); - } - } - break; - } + nv3_render_write_pixel(new_position, pixel_to_copy, grobj); + } + } } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 66ee170bc..9781259ad 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -213,11 +213,31 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool } /* /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ -uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj) +uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) { uint32_t vram_x = position.x; uint32_t vram_y = position.y; uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + + /* test DST_BUFFER code + I assume for 2d at least only one is allowed at a time + */ + + if (use_destination) + { + uint32_t destination_buffer = 5; // 5 = just use the source buffer + + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) destination_buffer = 0; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) destination_buffer = 1; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) destination_buffer = 2; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) destination_buffer = 3; + + if (destination_buffer != current_buffer + && destination_buffer != 5) + current_buffer = destination_buffer; + + } + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // we have to multiply the x position by the number of bytes per pixel @@ -242,19 +262,19 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro } /* Read an 8bpp pixel from the framebuffer. */ -uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj) +uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) { // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj); + uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); return nv3->nvbase.svga.vram[vram_address]; } /* Read an 16bpp pixel from the framebuffer. */ -uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) +uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) { // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj); + uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); vram_address >>= 1; //convert to 16bit pointer @@ -263,10 +283,10 @@ uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) } /* Read an 16bpp pixel from the framebuffer. */ -uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) +uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) { // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj); + uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); vram_address >>= 1; //convert to 16bit pointer @@ -315,7 +335,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob if (!nv3_render_chroma_test(color, grobj)) return; - uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj); + uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj, true); uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0; uint8_t bit = 0x00; From c05098e9ea44fbef0603fa3ba9e97bfb83b386d6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 6 Apr 2025 02:53:02 +0100 Subject: [PATCH 159/274] The worst ever s2sb implementation in human history but at least it works. Why are the buffers set to the same place --- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- .../nv/nv3/classes/nv3_class_011_image.c | 4 +- src/video/nv/nv3/render/nv3_render_blit.c | 59 +++++++++++++++---- src/video/nv/nv3/render/nv3_render_core.c | 2 +- 4 files changed, 52 insertions(+), 15 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 57184054d..7b752243f 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -47,7 +47,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* This is the last one*/ nv3->pgraph.blit.size.w = (param & 0xFFFF); nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB Size %04x,%04x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); + nv_log("Method Execution: S2SB Size %04x,%04x grobj_0=0x%08x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y, grobj.grobj_0); /* Some blits have (point_in == point_out) ???? */ if (nv3->pgraph.blit.point_in.x == nv3->pgraph.blit.point_out.x diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index c1d1200b9..bd5dfa6d3 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -28,8 +28,6 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> - - void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { switch (method_id) @@ -55,7 +53,7 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ if (method_id >= NV3_IMAGE_COLOR_START && method_id <= NV3_IMAGE_COLOR_END) { uint32_t pixel_slot = (method_id - NV3_IMAGE_COLOR_START) >> 2; - nv_log("Method Execution: Pixel%d Colour%08x Format%x\n", pixel_slot, param, (grobj.grobj_0) & 0x07); + nv_log("Method Execution: Image Pixel%d Colour%08x Format%x\n", pixel_slot, param, (grobj.grobj_0) & 0x07); nv3_render_blit_image(param, grobj); } else diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 3059aeccd..46556f928 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -108,27 +108,47 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) break; } - } + +#define NV3_MAX_HORIZONTAL_SIZE 1920 +#define NV3_MAX_VERTICAL_SIZE 1200 + +/* 1920 for margin. Holds a buffer of the old screen we want to hold so we don't overwrite things we already overwtote +We only need to clear it once per blit, because the blits are always the same size, and then only for the size of our new blit + +Extremely not crazy about this...Surely a better way to do it without buffering the ENTIRE SCREEN. I only update the parts that are needed, but still... + +This is LUDICROUSLY INEFFICIENT (2*O(n^2)) and COMPLETELY TERRIBLE code, but it's currently 2:48am so I can't think of a better approach... +*/ +uint32_t nv3_s2sb_line_buffer[NV3_MAX_HORIZONTAL_SIZE*NV3_MAX_VERTICAL_SIZE] = {0}; + void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { + if (nv3->pgraph.blit.size.w < NV3_MAX_HORIZONTAL_SIZE + && nv3->pgraph.blit.size.h < NV3_MAX_VERTICAL_SIZE) + memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.h) * (sizeof(uint32_t) * nv3->pgraph.blit.size.w)); + nv3_position_16_t old_position = nv3->pgraph.blit.point_in; nv3_position_16_t new_position = nv3->pgraph.blit.point_out; - uint16_t end_x = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); + uint16_t end_x_in = (nv3->pgraph.blit.point_in.x + nv3->pgraph.blit.size.w); /* needed for bounds checking */ + uint16_t end_x_out = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); uint16_t end_y = (nv3->pgraph.blit.point_out.y + nv3->pgraph.blit.size.h); uint32_t pixel_to_copy = 0x00; - /* Read the old pixel and rewrite it to the new position */ - for (int32_t y = nv3->pgraph.blit.point_out.y; y <= end_y; y++) - { - old_position.y = new_position.y = y; + /* Prevents overwriting pixels we've already modified*/ + uint32_t xdiff = 0, ydiff = 0; - for (int32_t x = nv3->pgraph.blit.point_out.x; x <= end_x; x++) + /* Read the old pixel into the line buffer */ + for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) + { + old_position.y = nv3->pgraph.blit.point_in.y + y; + + for (int32_t x = 0; x < nv3->pgraph.blit.size.w; x++) { - old_position.x = new_position.x = x; + old_position.x = nv3->pgraph.blit.point_in.x + x; switch (nv3->nvbase.svga.bpp) { @@ -143,7 +163,26 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) break; } - nv3_render_write_pixel(new_position, pixel_to_copy, grobj); + uint32_t buf_position = (y * nv3->pgraph.blit.size.w) + x; + nv3_s2sb_line_buffer[buf_position] = pixel_to_copy; } - } + + + } + /* simply write it all back to vram */ + for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) + { + new_position.y = nv3->pgraph.blit.point_out.y + y; + + for (int32_t x = 0; x < nv3->pgraph.blit.size.w; x++) + { + new_position.x = nv3->pgraph.blit.point_out.x + x; + + uint32_t buf_position = (y * nv3->pgraph.blit.size.w) + x; + + nv3_render_write_pixel(new_position, nv3_s2sb_line_buffer[buf_position], grobj); + } + } + + } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 9781259ad..e9ebeb013 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -289,7 +289,7 @@ uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); - vram_address >>= 1; //convert to 16bit pointer + vram_address >>= 2; //convert to 32bit pointer return vram_32[vram_address]; } From c9f6f87fccfad5fa95230576cf393c3854926fc1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 6 Apr 2025 14:03:09 +0100 Subject: [PATCH 160/274] much less idiotic... --- src/include/86box/nv/render/vid_nv3_render.h | 1 + src/include/86box/nv/vid_nv3.h | 2 +- .../classes/nv3_class_00c_win95_gdi_text.c | 2 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 5 ++ src/video/nv/nv3/render/nv3_render_blit.c | 61 ++++++++----------- src/video/nv/nv3/render/nv3_render_core.c | 3 +- 6 files changed, 33 insertions(+), 41 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 00591e342..048f3089a 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -22,6 +22,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); +uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 411ccdecf..dc6249346 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 2 April 2025 (STILL WORKING ON IT!!!) + * Last updated: 6 April 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index e2f640fac..c1085fe89 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -278,7 +278,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ return; } - nv_log("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); + warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; } diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 7b752243f..6582ada13 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -54,6 +54,11 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y) return; + /* Some of these seem to have sizes of 0, so skip */ + if (nv3->pgraph.blit.size.h == 0 + && nv3->pgraph.blit.size.w == 0) + return; + nv3_render_blit_screen2screen(grobj); break; diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 46556f928..ad8c0e3f9 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -138,51 +138,38 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) uint32_t pixel_to_copy = 0x00; - /* Prevents overwriting pixels we've already modified*/ - uint32_t xdiff = 0, ydiff = 0; + /* Coordinates for copying an entire line at a time */ + uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.w; + + /* Read the old pixel into the line buffer + Assumption: All data is sent in an unpacked format. In the case of an NVIDIA GPU this means that all data is sent 32 bits at a time regardless of if + the actual source data is 32 bits in size or not. For pixel data, the upper bits are left as 0 in 8bpp/16bpp mode. For 86box purposes, the data is written + 8/16 bits at a time. + + TODO: CHECK FOR PACKED FORMAT!!!!! + */ + + if (nv3->nvbase.svga.bpp == 15 + || nv3->nvbase.svga.bpp == 16) + size_x <<= 1; + else if (nv3->nvbase.svga.bpp == 32) + size_x <<= 2; - /* Read the old pixel into the line buffer */ for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) { old_position.y = nv3->pgraph.blit.point_in.y + y; + /* 32bit buffer */ + buf_position = (nv3->pgraph.blit.size.w * y); + vram_position = nv3_render_get_vram_address(old_position, grobj, false); - for (int32_t x = 0; x < nv3->pgraph.blit.size.w; x++) - { - old_position.x = nv3->pgraph.blit.point_in.x + x; - - switch (nv3->nvbase.svga.bpp) - { - case 8: - pixel_to_copy = nv3_render_read_pixel_8(old_position, grobj, false) & 0xFF; - break; - case 15 ... 16: //15bpp and 16bpp modes are considered as identical - pixel_to_copy = nv3_render_read_pixel_16(old_position, grobj, false) & 0xFFFF; - break; - case 32: - pixel_to_copy = nv3_render_read_pixel_32(old_position, grobj, false); - break; - } - - uint32_t buf_position = (y * nv3->pgraph.blit.size.w) + x; - nv3_s2sb_line_buffer[buf_position] = pixel_to_copy; - } - - + memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); } /* simply write it all back to vram */ for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) - { + { + buf_position = (nv3->pgraph.blit.size.w * y); new_position.y = nv3->pgraph.blit.point_out.y + y; - - for (int32_t x = 0; x < nv3->pgraph.blit.size.w; x++) - { - new_position.x = nv3->pgraph.blit.point_out.x + x; - - uint32_t buf_position = (y * nv3->pgraph.blit.size.w) + x; - - nv3_render_write_pixel(new_position, nv3_s2sb_line_buffer[buf_position], grobj); - } + vram_position = nv3_render_get_vram_address(new_position, grobj, false); + memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); } - - } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index e9ebeb013..dca2a6a6c 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -212,7 +212,7 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool } -/* /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ +/* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) { uint32_t vram_x = position.x; @@ -309,7 +309,6 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too?z - uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; /* doesn't seem*/ nv3_color_argb_t color_data = *(nv3_color_argb_t*)&color; From c1506772dec8299b5d4a3f64f32f3415b5bb2f83 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 6 Apr 2025 18:08:42 +0100 Subject: [PATCH 161/274] fix crossbuffer blit, use custom render functions --- .../86box/nv/classes/vid_nv3_classes.h | 4 +- src/include/86box/nv/render/vid_nv3_render.h | 3 + src/include/86box/nv/vid_nv.h | 1 + src/include/86box/nv/vid_nv3.h | 4 +- .../classes/nv3_class_01c_image_in_memory.c | 9 +- src/video/nv/nv3/nv3_core.c | 15 +- src/video/nv/nv3/render/nv3_render_blit.c | 3 +- src/video/nv/nv3/render/nv3_render_core.c | 161 ++++++++++++++++++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 4 +- 9 files changed, 186 insertions(+), 18 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index e3a1bf7aa..3b6eb1411 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -270,8 +270,8 @@ typedef struct nv3_color_argb_s /* Generic 16-bit position*/ typedef struct nv3_position_16_s { - uint16_t y; uint16_t x; + uint16_t y; } nv3_position_16_t; /* A big position format with 30:16 = y, 15:11 = nothing, 10:0 = x */ @@ -287,8 +287,8 @@ typedef struct nv3_position_16_bigy_s /* Generic 16-bit size */ typedef struct nv3_size_16_s { - uint16_t h; uint16_t w; + uint16_t h; } nv3_size_16_t; /* Generic 32-bit colour + 16-bit position */ diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 048f3089a..567cf3cd4 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,6 +18,9 @@ #pragma once /* Core */ +void nv3_render_15bpp(svga_t *svga); +void nv3_render_16bpp(svga_t *svga); +void nv3_render_32bpp(svga_t *svga); void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index c26c51868..0b314d5f3 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -121,6 +121,7 @@ typedef struct nv_base_s bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times void* i2c; // I2C for monitor EDID void* ddc; // Display Data Channel for EDID + uint32_t last_buffer_address; // Last buffer address. } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index dc6249346..482315e32 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1194,8 +1194,8 @@ typedef struct nv3_pgraph_s nv3_pgraph_dma_settings_t dma_settings; uint8_t rop; // Current GDI Ternary Render Operation // SURFACE STUFF - PGRAPH CAN OPERATE ON 4 SURFACES/BUFFERS AT A TIME - uint32_t boffset[NV3_PGRAPH_MAX_BUFFERS]; // 22-bit linear VRAM offset for the start of a surface. - uint16_t bpitch[NV3_PGRAPH_MAX_BUFFERS]; // 12-bit linear VRAM offset for the pitch of a surfac.e + uint32_t boffset[NV3_PGRAPH_MAX_BUFFERS]; // 22-bit linear VRAM offset for the start of a buffer. + uint16_t bpitch[NV3_PGRAPH_MAX_BUFFERS]; // 12-bit linear VRAM offset for the pitch of a buffer uint32_t bpixel[NV3_PGRAPH_MAX_BUFFERS]; // Pixel format for each possible surfaces. // CLIP nv3_pgraph_clip_misc_settings_t clip_misc_settings; diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index af488dc09..9e6a55310 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -77,8 +77,13 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; /* Byte offset in GPU VRAM of top left pixel (22:0) */ case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: - nv3->pgraph.boffset[src_buffer_id] = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); - + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX + nv3->pgraph.boffset[src_buffer_id] = param & 0x7FFFFF; + else + nv3->pgraph.boffset[src_buffer_id] = param & 0x3FFFFF; + + nv3->nvbase.last_buffer_address = nv3->pgraph.boffset[src_buffer_id]; + nv_log("Method Execution: Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x\n", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); break; default: diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 610f8c500..78592160a 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -523,30 +523,27 @@ void nv3_recalc_timings(svga_t* svga) break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: /* This is some sketchy shit that is an attempt at an educated guess - at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, this is what's causing it */ + at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, + this is what's causing it. Possibly fucking *ReactOS* of all things */ if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01) - { svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; - } else - { svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; - } + /* sometimes it really renders in 15bpp, so you need to do this */ if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) { svga->bpp = 16; svga->lowres = 0; - svga->render = svga_render_16bpp_highres; + svga->render = nv3_render_16bpp; } else { svga->bpp = 15; svga->lowres = 0; - svga->render = svga_render_15bpp_highres; + svga->render = nv3_render_15bpp; - // fixes win2000, but breaks 9x?! } break; @@ -555,7 +552,7 @@ void nv3_recalc_timings(svga_t* svga) svga->bpp = 32; svga->lowres = 0; - svga->render = svga_render_32bpp_highres; + svga->render = nv3_render_32bpp; break; } diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index ad8c0e3f9..666a93482 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -164,12 +164,13 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); } + /* simply write it all back to vram */ for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) { buf_position = (nv3->pgraph.blit.size.w * y); new_position.y = nv3->pgraph.blit.point_out.y + y; - vram_position = nv3_render_get_vram_address(new_position, grobj, false); + vram_position = nv3_render_get_vram_address(new_position, grobj, true); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); } } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index dca2a6a6c..147ac8f6e 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -436,3 +436,164 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob break; } } + + +/* + Modified SVGA Core functions + Done, to facilitate the buffer changing around stuff. + + TODO: Do we need a custom 8bpp function? +*/ + +void nv3_render_15bpp(svga_t *svga) +{ + int x; + uint32_t *p; + uint32_t dat; + uint32_t changed_addr; + uint32_t addr; + + /* "force_old_addr" code path removed, since we don't need it */ + + if ((svga->displine + svga->y_add) < 0) + return; + + changed_addr = svga->remap_func(svga, svga->ma); + + if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) { + p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add]; + + if (svga->firstline_draw == 2000) + svga->firstline_draw = svga->displine; + svga->lastline_draw = svga->displine; + + if (!svga->remap_required) { + for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) { + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); + *p++ = svga->conv_16to32(svga, dat >> 16, 15); + + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); + *p++ = svga->conv_16to32(svga, dat >> 16, 15); + + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); + *p++ = svga->conv_16to32(svga, dat >> 16, 15); + + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); + *p++ = svga->conv_16to32(svga, dat >> 16, 15); + } + svga->ma += x << 1; + } else { + for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) { + addr = svga->remap_func(svga, svga->ma); + dat = *(uint32_t *) (&svga->vram[(addr) & svga->vram_display_mask]); + + *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); + *p++ = svga->conv_16to32(svga, dat >> 16, 15); + svga->ma += 4; + } + } + svga->ma &= svga->vram_display_mask; + } +} + + +void nv3_render_16bpp(svga_t *svga) +{ + int x; + uint32_t *p; + uint32_t dat; + uint32_t changed_addr; + uint32_t addr; + + if ((svga->displine + svga->y_add) < 0) + return; + + changed_addr = svga->remap_func(svga, svga->ma); + + /* "force_old_addr" code path removed, since we don't need it */ + if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) { + p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add]; + + if (svga->firstline_draw == 2000) + svga->firstline_draw = svga->displine; + svga->lastline_draw = svga->displine; + + if (!svga->remap_required) { + for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) { + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); + *p++ = svga->conv_16to32(svga, dat >> 16, 16); + + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); + *p++ = svga->conv_16to32(svga, dat >> 16, 16); + + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); + *p++ = svga->conv_16to32(svga, dat >> 16, 16); + + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]); + *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); + *p++ = svga->conv_16to32(svga, dat >> 16, 16); + } + svga->ma += x << 1; + } else { + for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) { + addr = svga->remap_func(svga, svga->ma); + dat = *(uint32_t *) (&svga->vram[(addr) & svga->vram_display_mask]); + + *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); + *p++ = svga->conv_16to32(svga, dat >> 16, 16); + + svga->ma += 4; + } + } + svga->ma &= svga->vram_display_mask; + } +} + + +void nv3_render_32bpp(svga_t *svga) +{ + int x; + uint32_t *p; + uint32_t dat; + uint32_t changed_addr; + uint32_t addr; + + if ((svga->displine + svga->y_add) < 0) + return; + + /* "force_old_addr" code path removed, since we don't need it */ + + changed_addr = svga->remap_func(svga, svga->ma); + + if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) { + p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add]; + + if (svga->firstline_draw == 2000) + svga->firstline_draw = svga->displine; + svga->lastline_draw = svga->displine; + + if (!svga->remap_required) { + for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) { + dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]); + *p++ = svga_lookup_lut_ram(svga, dat & 0xffffff); + } + svga->ma += (x * 4); + } else { + for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) { + addr = svga->remap_func(svga, svga->ma); + dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]); + *p++ = svga_lookup_lut_ram(svga, dat & 0xffffff); + + svga->ma += 4; + } + } + svga->ma &= svga->vram_display_mask; + } +} diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 6195c0639..ea39b9135 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -873,7 +873,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_index); next_put_address++; - if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# + if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX# next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); else next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); @@ -931,7 +931,7 @@ void nv3_pfifo_cache1_pull() // start by incrementing uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1; - if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX# + if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); else next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); From 911a71c67fbe2b6209bae7d957563f7a51c8aeaf Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 9 Apr 2025 21:29:46 +0100 Subject: [PATCH 162/274] very large rewrite. use custom rendering code (for both DFB and GPU) to allow sub-scanline switches; implement a real pixel clock; only blit stuff that actually changed; add void to functions for actions (this may break some things) --- src/include/86box/nv/render/vid_nv3_render.h | 10 +- src/include/86box/nv/vid_nv.h | 9 +- src/include/86box/nv/vid_nv3.h | 34 +- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- src/video/nv/nv3/nv3_core.c | 32 +- src/video/nv/nv3/render/nv3_render_blit.c | 50 +++ src/video/nv/nv3/render/nv3_render_core.c | 373 ++++++++++++------ .../nv/nv3/render/nv3_render_primitives.c | 3 + src/video/nv/nv3/subsystems/nv3_pramdac.c | 17 + 9 files changed, 378 insertions(+), 152 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 567cf3cd4..11f4d2368 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,13 +18,17 @@ #pragma once /* Core */ -void nv3_render_15bpp(svga_t *svga); -void nv3_render_16bpp(svga_t *svga); -void nv3_render_32bpp(svga_t *svga); +void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); +void nv3_render_current_bpp_dfb_8(uint32_t address); +void nv3_render_current_bpp_dfb_16(uint32_t address); +void nv3_render_current_bpp_dfb_32(uint32_t address); + void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); + + uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 0b314d5f3..ef5e80d71 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -72,6 +72,9 @@ void nv_log_verbose_only(const char *fmt, ...); #define NV_ARCHITECTURE_NV3 3 // Riva 128 #define NV_ARCHITECTURE_NV4 4 // Riva TNT and later +#define NV_MAX_BUF_SIZE_X 1920 // Maximum buffer size, X +#define NV_MAX_BUF_SIZE_Y 1200 // Maximum buffer size, Y + typedef enum nv_bus_generation_e { // NV1 - Prototype version @@ -113,7 +116,9 @@ typedef struct nv_base_s uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) uint32_t gpu_revision; // GPU Stepping - double pixel_clock_frequency; // Frequency used for pixel clock + double pixel_clock_frequency; // Frequency used for pixel clock# + double refresh_time; // Rough estimation of refresh rate, for when we can present the screen + double refresh_clock; // Time since the last refresh rivatimer_t* pixel_clock_timer; // Timer for measuring pixel clock bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times double memory_clock_frequency; // Source Frequency for PTIMER @@ -139,7 +144,7 @@ typedef struct nv_register_s int32_t address; // MMIO Address char* friendly_name; // Friendly name // reg_ptr not needed as a parameter, because we implicitly know which register si being tiwddled - uint32_t (*on_read)(); // Optional on-read function + uint32_t (*on_read)(void); // Optional on-read function void (*on_write)(uint32_t value); // Optional on-write fucntion } nv_register_t; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 482315e32..f11a4cdfc 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1457,7 +1457,7 @@ void nv3_recalc_timings(svga_t* svga); void nv3_force_redraw(void* priv); /* BAR0 GPU MMIO read */ -void nv3_update_mappings(); // Update memory mappings +void nv3_update_mappings(void); // Update memory mappings uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO @@ -1556,12 +1556,12 @@ void nv3_user_write(uint32_t address, uint32_t value); // GPU subsystems // NV3 PMC -void nv3_pmc_init(); -uint32_t nv3_pmc_clear_interrupts(); +void nv3_pmc_init(void); +uint32_t nv3_pmc_clear_interrupts(void); uint32_t nv3_pmc_handle_interrupts(bool send_now); // NV3 PGRAPH -void nv3_pgraph_init(); +void nv3_pgraph_init(void); uint32_t nv3_pgraph_read(uint32_t address); void nv3_pgraph_write(uint32_t address, uint32_t value); void nv3_pgraph_vblank_start(svga_t* svga); @@ -1599,46 +1599,46 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_c void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context,nv3_grobj_t grobj); // NV3 PFIFO -void nv3_pfifo_init(); +void nv3_pfifo_init(void); uint32_t nv3_pfifo_read(uint32_t address); void nv3_pfifo_write(uint32_t address, uint32_t value); void nv3_pfifo_interrupt(uint32_t id, bool fire_now); // NV3 PFIFO - Caches //cache0_push not a thing -void nv3_pfifo_cache0_pull(); +void nv3_pfifo_cache0_pull(void); void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val); -void nv3_pfifo_cache1_pull(); +void nv3_pfifo_cache1_pull(void); uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); -uint32_t nv3_pfifo_cache1_num_free_spaces(); +uint32_t nv3_pfifo_cache1_num_free_spaces(void); // NV3 PFB -void nv3_pfb_init(); +void nv3_pfb_init(void); // NV3 PEXTDEV/PSTRAPS -void nv3_pextdev_init(); +void nv3_pextdev_init(void); // NV3 PBUS -void nv3_pbus_init(); +void nv3_pbus_init(void); // NV3 PBUS RMA - Real Mode Access for VBIOS uint8_t nv3_pbus_rma_read(uint16_t addr); void nv3_pbus_rma_write(uint16_t addr, uint8_t val); // NV3 PRAMDAC (Final presentation) -void nv3_pramdac_init(); -void nv3_pramdac_set_vram_clock(); -void nv3_pramdac_set_pixel_clock(); +void nv3_pramdac_init(void); +void nv3_pramdac_set_vram_clock(void); +void nv3_pramdac_set_pixel_clock(void); void nv3_pramdac_pixel_clock_poll(double real_time); void nv3_pramdac_memory_clock_poll(double real_time); // NV3 PTIMER -void nv3_ptimer_init(); +void nv3_ptimer_init(void); void nv3_ptimer_tick(double real_time); // NV3 PVIDEO -void nv3_pvideo_init(); +void nv3_pvideo_init(void); // NV3 PME (Mediaport) -void nv3_pme_init(); \ No newline at end of file +void nv3_pme_init(void); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 6582ada13..45e5155a7 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -59,7 +59,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ && nv3->pgraph.blit.size.w == 0) return; - nv3_render_blit_screen2screen(grobj); + //nv3_render_blit_screen2screen(grobj); break; default: diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 78592160a..aa8865fdd 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -511,6 +511,21 @@ void nv3_recalc_timings(svga_t* svga) svga->hdisp += 0x100; // large screen bit } + /* Turn off override if we are in VGA mode */ + svga->override = !(pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA); + + /* NOTE: The RIVA 128 draws in a way almost completely separate to any other 86Box GPU. + + Basically, we only blit to buffer32 when something changes and we don't even bother using a timer. We only render when there is something to actually render. + + This is because there is no linear relationship between the contents of VRAM and the contents of the display which 86box's SVGA subsystem cannot tolerate. + In fact, the position in VRAM and pitch can be changed at any time via an NV_IMAGE_IN_MEMORY object. + + Therefore, we need to completely bypass it using svga->override and draw our own rendering functions. This allows us to use a neat optimisation trick + to only ever actually draw when we need to do something. This shouldn't be a problem in games, because the drivers will read the current refresh rate from + the Windows settings, and then, just submit objects at that pace for anything that changes on the screen. + */ + // Set the pixel mode switch (pixel_mode) { @@ -519,7 +534,7 @@ void nv3_recalc_timings(svga_t* svga) svga->bpp = 8; svga->lowres = 0; svga->map8 = svga->pallook; - svga->render = svga_render_8bpp_highres; + //svga->render = nv3_render_8bpp; break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: /* This is some sketchy shit that is an attempt at an educated guess @@ -536,13 +551,13 @@ void nv3_recalc_timings(svga_t* svga) { svga->bpp = 16; svga->lowres = 0; - svga->render = nv3_render_16bpp; + //svga->render = nv3_render_16bpp; } else { svga->bpp = 15; svga->lowres = 0; - svga->render = nv3_render_15bpp; + //svga->render = nv3_render_15bpp; } @@ -552,7 +567,7 @@ void nv3_recalc_timings(svga_t* svga) svga->bpp = 32; svga->lowres = 0; - svga->render = nv3_render_32bpp; + //svga->render = nv3_render_32bpp; break; } @@ -784,6 +799,8 @@ void nv3_dfb_write8(uint32_t addr, uint8_t val, void* priv) { addr &= (nv3->nvbase.svga.vram_mask); nv3->nvbase.svga.vram[addr] = val; + nv3->nvbase.svga.changedvram[addr >> 12] = val; + nv3_render_current_bpp_dfb_8(addr); } void nv3_dfb_write16(uint32_t addr, uint16_t val, void* priv) @@ -791,6 +808,9 @@ void nv3_dfb_write16(uint32_t addr, uint16_t val, void* priv) addr &= (nv3->nvbase.svga.vram_mask); nv3->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; nv3->nvbase.svga.vram[addr] = (val) & 0xFF; + nv3->nvbase.svga.changedvram[addr >> 12] = val; + nv3_render_current_bpp_dfb_16(addr); + } void nv3_dfb_write32(uint32_t addr, uint32_t val, void* priv) @@ -800,6 +820,10 @@ void nv3_dfb_write32(uint32_t addr, uint32_t val, void* priv) nv3->nvbase.svga.vram[addr + 2] = (val >> 16) & 0xFF; nv3->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; nv3->nvbase.svga.vram[addr] = (val) & 0xFF; + nv3->nvbase.svga.changedvram[addr >> 12] = val; + + nv3_render_current_bpp_dfb_32(addr); + } /* Cursor shit */ diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 666a93482..09a099977 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -132,6 +132,20 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) nv3_position_16_t old_position = nv3->pgraph.blit.point_in; nv3_position_16_t new_position = nv3->pgraph.blit.point_out; + uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + + /* test DST_BUFFER code + I assume for 2d at least only one is allowed at a time + */ + + uint32_t dst_buffer = 0; // 5 = just use the source buffer + + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; + + uint16_t end_x_in = (nv3->pgraph.blit.point_in.x + nv3->pgraph.blit.size.w); /* needed for bounds checking */ uint16_t end_x_out = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); uint16_t end_y = (nv3->pgraph.blit.point_out.y + nv3->pgraph.blit.size.h); @@ -173,4 +187,40 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) vram_position = nv3_render_get_vram_address(new_position, grobj, true); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); } + + /* + We need to blit manually here because we don't go through nv3_render_write_pixel + We also need to update all of the areas of the screen that moved. + */ + + nv3_position_16_t blit_position = {0}; + nv3_size_16_t blit_size = {0}; + + /* Change the smallest area of the screen that moved */ + if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) + blit_size.w = (nv3->pgraph.blit.point_out.x - nv3->pgraph.blit.point_in.x) + nv3->pgraph.blit.size.w; + else if (nv3->pgraph.blit.point_out.x < nv3->pgraph.blit.point_in.x) + blit_size.w = (nv3->pgraph.blit.point_in.x - nv3->pgraph.blit.point_out.x) + nv3->pgraph.blit.size.w; + else + blit_size.w = nv3->pgraph.blit.size.w; + + if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) + blit_size.h = (nv3->pgraph.blit.point_out.y - nv3->pgraph.blit.point_in.y) + nv3->pgraph.blit.size.h; + else if (nv3->pgraph.blit.point_out.y < nv3->pgraph.blit.point_in.y) + blit_size.h = (nv3->pgraph.blit.point_in.y - nv3->pgraph.blit.point_out.y) + nv3->pgraph.blit.size.h; + else + blit_size.h = nv3->pgraph.blit.size.h; + + if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) + blit_position.x = nv3->pgraph.blit.point_in.x; + else if (nv3->pgraph.blit.point_out.x <= nv3->pgraph.blit.point_in.x) // equals case, just use out + blit_position.x = nv3->pgraph.blit.point_out.x; + + if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) + blit_position.y = nv3->pgraph.blit.point_in.y; + else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out + blit_position.y = nv3->pgraph.blit.point_out.y; + + + nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj); } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 147ac8f6e..4313ac2a6 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -30,6 +30,12 @@ #include <86box/nv/vid_nv3.h> #include <86box/utils/video_stdlib.h> +/* Functions only used in this translation unit */ +void nv3_render_8bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); +void nv3_render_15bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); +void nv3_render_16bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); +void nv3_render_32bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); + /* Expand a colour. NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! */ @@ -261,6 +267,38 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro return pixel_addr_vram; } +/* Convert a dumb framebuffer address to a position. No buffer setup or anything, but just start at 0,0 for address 0. */ +nv3_position_16_t nv3_render_get_dfb_position(uint32_t vram_address) +{ + nv3_position_16_t pos = {0}; + + uint32_t pitch = nv3->nvbase.svga.hdisp; + + if (nv3->nvbase.svga.bpp == 15 + || nv3->nvbase.svga.bpp == 16) + pitch <<= 1; + else if (nv3->nvbase.svga.bpp == 32) + pitch <<= 2; + + //vram_address -= nv3->pgraph.boffset[0]; + + pos.y = (vram_address / pitch); + pos.x = (vram_address % pitch); + + /* Fixup our x position */ + if (nv3->nvbase.svga.bpp == 15 + || nv3->nvbase.svga.bpp == 16) + pos.x >>= 1; + else if (nv3->nvbase.svga.bpp == 32) + pos.x >>= 2; + + + /* there is some strange behaviour where it writes long past the end of the fb */ + if (pos.y >= nv3->nvbase.svga.monitor->target_buffer->h) pos.y = nv3->nvbase.svga.monitor->target_buffer->h - 1; + + return pos; +} + /* Read an 8bpp pixel from the framebuffer. */ uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) { @@ -435,165 +473,250 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob break; } + + /* Go write the pixel */ + nv3_size_16_t size = {0}; + size.w = size.h = 1; + nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj); } +/* Ensure the correct monitor size */ +void nv3_render_ensure_mode() +{ + bool changed = false; //doesn't check if the res is the same? + + if (nv3->nvbase.svga.hdisp != nv3->nvbase.svga.monitor->mon_xsize) + { + changed = true; + nv3->nvbase.svga.monitor->mon_xsize = nv3->nvbase.svga.hdisp; + } + + if (nv3->nvbase.svga.dispend != nv3->nvbase.svga.monitor->mon_ysize) + { + changed = true; + nv3->nvbase.svga.monitor->mon_ysize = nv3->nvbase.svga.dispend; + } + + if (changed) + { + /* set refresh rate - this is just a rough estimation right now. we need it as we only blit what changes */ + nv3->nvbase.refresh_time = 1 / (nv3->nvbase.pixel_clock_frequency / (double)ysize / (double)xsize); // rivatimers count in microseconds + set_screen_size(xsize, ysize); + } + +} + + +/* Blit to the monitor from DFB, 8bpp */ +void nv3_render_current_bpp_dfb_8(uint32_t address) +{ + +} + +/* Blit to the monitor from DFB, 15/16bpp */ +void nv3_render_current_bpp_dfb_16(uint32_t address) +{ + nv3_size_16_t size = {0}; + size.w = size.h = 1; + + nv3_position_16_t pos = nv3_render_get_dfb_position(address); + + //pos.x >>= 1; + + uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); + + if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) + /* should just "tip over" to the next line */ + *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 16); + else + /* should just "tip over" to the next line */ + *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); + + /*does 8bpp packed into 16 occur/ i would be surprised*/ +} + +/* Blit to the monitor from DFB, 32bpp */ +void nv3_render_current_bpp_dfb_32(uint32_t address) +{ + nv3_size_16_t size = {0}; + size.w = size.h = 1; + + nv3_position_16_t pos = nv3_render_get_dfb_position(address); + + uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); + + if (nv3->nvbase.svga.bpp == 32) + { + uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + *p = data; + } + /* Packed format */ + else if (nv3->nvbase.svga.bpp == 15 + || nv3->nvbase.svga.bpp == 16) + { + //pos.x >>= 1; + + uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + + *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, nv3->nvbase.svga.bpp); + *p++; + *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, (data >> 16) & 0xFFFF, nv3->nvbase.svga.bpp); + } +} + + +/* Blit to the monitor from GPU, current bpp */ +void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +{ + /* Ensure that we are in the correct mode. Modified SVGA core code */ + nv3_render_ensure_mode(); + + switch (nv3->nvbase.svga.bpp) + { + case 4: + /* Uh we should never be here because we're in the SVGA mode */ + fatal("NV3 - Tried to render 4bpp in NV mode"); + break; + case 8: + nv3_render_8bpp(pos, size, grobj); + break; + case 15: + nv3_render_15bpp(pos, size, grobj); + break; + case 16: + nv3_render_16bpp(pos, size, grobj); + break; + case 32: + nv3_render_32bpp(pos, size, grobj); + break; + } + +} /* - Modified SVGA Core functions - Done, to facilitate the buffer changing around stuff. - - TODO: Do we need a custom 8bpp function? + Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, indexed 8 bits per pixel format */ -void nv3_render_15bpp(svga_t *svga) +void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) { - int x; - uint32_t *p; - uint32_t dat; - uint32_t changed_addr; - uint32_t addr; + +} - /* "force_old_addr" code path removed, since we don't need it */ +/* + Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 15 bits per pixel format +*/ - if ((svga->displine + svga->y_add) < 0) - return; +void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +{ + if (!nv3) + return; - changed_addr = svga->remap_func(svga, svga->ma); + uint32_t vram_base; //acquired for the start of each line + uint32_t* p; + uint32_t data; + uint32_t start_x = pos.x; - if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) { - p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - if (svga->firstline_draw == 2000) - svga->firstline_draw = svga->displine; - svga->lastline_draw = svga->displine; + for (uint32_t y = 0; y < size.h; y++) + { + /* re-set the vram address because we are basically "jumping" halfway across a line here */ + vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask; - if (!svga->remap_required) { - for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) { - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); - *p++ = svga->conv_16to32(svga, dat >> 16, 15); + for (uint32_t x = 0; x < size.w; x++) + { + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); - *p++ = svga->conv_16to32(svga, dat >> 16, 15); - - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); - *p++ = svga->conv_16to32(svga, dat >> 16, 15); - - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); - *p++ = svga->conv_16to32(svga, dat >> 16, 15); - } - svga->ma += x << 1; - } else { - for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) { - addr = svga->remap_func(svga, svga->ma); - dat = *(uint32_t *) (&svga->vram[(addr) & svga->vram_display_mask]); - - *p++ = svga->conv_16to32(svga, dat & 0xffff, 15); - *p++ = svga->conv_16to32(svga, dat >> 16, 15); - svga->ma += 4; - } + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + + /* should just "tip over" to the next line */ + *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); + + vram_base += 2; + pos.x++; } - svga->ma &= svga->vram_display_mask; + + pos.x = start_x; + pos.y++; } } +/* + Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 16 bits per pixel format +*/ -void nv3_render_16bpp(svga_t *svga) -{ - int x; - uint32_t *p; - uint32_t dat; - uint32_t changed_addr; - uint32_t addr; +void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +{ + if (!nv3) + return; - if ((svga->displine + svga->y_add) < 0) - return; + uint32_t vram_base; //acquired for the start of each line + uint32_t* p; + uint32_t data; + uint32_t start_x = pos.x; - changed_addr = svga->remap_func(svga, svga->ma); + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - /* "force_old_addr" code path removed, since we don't need it */ - if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) { - p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add]; + for (uint32_t y = 0; y < size.h; y++) + { + /* re-get the vram address because we are basically "jumping" halfway across a line here */ + vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask; - if (svga->firstline_draw == 2000) - svga->firstline_draw = svga->displine; - svga->lastline_draw = svga->displine; + for (uint32_t x = 0; x < size.w; x++) + { + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - if (!svga->remap_required) { - for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) { - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); - *p++ = svga->conv_16to32(svga, dat >> 16, 16); - - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); - *p++ = svga->conv_16to32(svga, dat >> 16, 16); - - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); - *p++ = svga->conv_16to32(svga, dat >> 16, 16); - - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]); - *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); - *p++ = svga->conv_16to32(svga, dat >> 16, 16); - } - svga->ma += x << 1; - } else { - for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) { - addr = svga->remap_func(svga, svga->ma); - dat = *(uint32_t *) (&svga->vram[(addr) & svga->vram_display_mask]); - - *p++ = svga->conv_16to32(svga, dat & 0xffff, 16); - *p++ = svga->conv_16to32(svga, dat >> 16, 16); - - svga->ma += 4; - } + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + + /* should just "tip over" to the next line */ + *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); + + vram_base += 2; + pos.x++; } - svga->ma &= svga->vram_display_mask; - } + + pos.x = start_x; + pos.y++; + } } +/* + Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 32 bits per pixel format +*/ -void nv3_render_32bpp(svga_t *svga) +void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) { - int x; - uint32_t *p; - uint32_t dat; - uint32_t changed_addr; - uint32_t addr; + if (!nv3) + return; - if ((svga->displine + svga->y_add) < 0) - return; + uint32_t vram_base; + uint32_t* p; + uint32_t data; + uint32_t start_x = pos.x; - /* "force_old_addr" code path removed, since we don't need it */ + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - changed_addr = svga->remap_func(svga, svga->ma); + for (uint32_t y = 0; y < size.h; y++) + { + /* re-get the vram address because we are basically "jumping" halfway across a line here */ + vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask; + - if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) { - p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add]; + for (uint32_t x = 0; x < size.w; x++) + { + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - if (svga->firstline_draw == 2000) - svga->firstline_draw = svga->displine; - svga->lastline_draw = svga->displine; - - if (!svga->remap_required) { - for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) { - dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]); - *p++ = svga_lookup_lut_ram(svga, dat & 0xffffff); - } - svga->ma += (x * 4); - } else { - for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) { - addr = svga->remap_func(svga, svga->ma); - dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]); - *p++ = svga_lookup_lut_ram(svga, dat & 0xffffff); - - svga->ma += 4; - } + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + + /* should just "tip over" to the next line */ + *p = data; + + vram_base += 4; + pos.x++; } - svga->ma &= svga->vram_display_mask; + + pos.y++; + pos.x = start_x; } } diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index 487f41731..c89fd2d6e 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -119,6 +119,7 @@ void nv3_render_gdi_transparent_bitmap_blit(bool bit, bool clip, uint32_t color, else nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; } + } /* Originally written 23 March 2025, but then, redone, properly, on 30 March 2025 */ @@ -208,6 +209,7 @@ void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitma /* IF we're done, let's return */ if (!bits_remaining_in_bitmap) return; + } void nv3_render_gdi_1bpp_bitmap_blit(bool bit, uint32_t color0, uint32_t color1, nv3_grobj_t grobj) @@ -262,6 +264,7 @@ void nv3_render_gdi_1bpp_bitmap_blit(bool bit, uint32_t color0, uint32_t color1, } } + /* Originally written 23 March 2025, but then, redone, properly, on 30 March 2025 */ void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj) { diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 0e41807a0..d1fb9f1c5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -51,6 +51,23 @@ void nv3_pramdac_init() // Polls the pixel clock. void nv3_pramdac_pixel_clock_poll(double real_time) { + /* Ignore in VGA mode */ + if (!nv3->nvbase.svga.override) + return; + + /* Figure out our refresh time. */ + if (!nv3->nvbase.refresh_time) + nv3->nvbase.refresh_time = (1/60.0); // rivatimers count in microseconds but present the info as seconds + + nv3->nvbase.refresh_clock += real_time; + + if (nv3->nvbase.refresh_clock > nv3->nvbase.refresh_time) + { + /* Update the screen because something changed */ + video_blit_memtoscreen(0, 0, xsize, ysize); + nv3->nvbase.refresh_clock = 0; + } + // TODO: ???? } From c8f3a8ad6910b6287cb6ff2fe4014de176665334 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 9 Apr 2025 21:31:15 +0100 Subject: [PATCH 163/274] uncomment s2sb --- src/video/nv/nv3/classes/nv3_class_010_blit.c | 2 +- src/video/nv/nv3/nv3_core.c | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 45e5155a7..6582ada13 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -59,7 +59,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ && nv3->pgraph.blit.size.w == 0) return; - //nv3_render_blit_screen2screen(grobj); + nv3_render_blit_screen2screen(grobj); break; default: diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index aa8865fdd..babe7a056 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -534,7 +534,6 @@ void nv3_recalc_timings(svga_t* svga) svga->bpp = 8; svga->lowres = 0; svga->map8 = svga->pallook; - //svga->render = nv3_render_8bpp; break; case NV3_CRTC_REGISTER_PIXELMODE_16BPP: /* This is some sketchy shit that is an attempt at an educated guess @@ -545,19 +544,16 @@ void nv3_recalc_timings(svga_t* svga) else svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; - /* sometimes it really renders in 15bpp, so you need to do this */ if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) { svga->bpp = 16; svga->lowres = 0; - //svga->render = nv3_render_16bpp; } else { svga->bpp = 15; svga->lowres = 0; - //svga->render = nv3_render_15bpp; } From 22981f2d4b7d5ca28343ea48cc6d41d80a26d0e7 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 10 Apr 2025 10:56:07 +0100 Subject: [PATCH 164/274] remove some code that was stupid, add void to fucntions --- CMakeLists.txt | 2 +- src/include/86box/nv/render/vid_nv3_render.h | 8 +-- src/video/nv/nv3/classes/nv3_class_010_blit.c | 7 +-- .../nv/nv3/classes/nv3_class_shared_methods.c | 2 +- src/video/nv/nv3/nv3_core.c | 16 +++--- src/video/nv/nv3/render/nv3_render_blit.c | 10 ++-- src/video/nv/nv3/render/nv3_render_core.c | 55 +++++++++---------- src/video/nv/nv3/subsystems/nv3_pbus.c | 2 +- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 2 +- src/video/nv/nv3/subsystems/nv3_pextdev.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfb.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 10 ++-- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 +- src/video/nv/nv3/subsystems/nv3_pmc.c | 6 +- src/video/nv/nv3/subsystems/nv3_pme.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 10 ++-- src/video/nv/nv3/subsystems/nv3_ptimer.c | 2 +- src/video/nv/nv3/subsystems/nv3_pvideo.c | 2 +- 18 files changed, 68 insertions(+), 74 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 52f24f4b9..c9825b9ef 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -139,7 +139,7 @@ option(DISCORD "Discord Rich Presence support" option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) # Remove when merged, should just be -D option(NV_LOG "NVidia RIVA 128 debug logging" ON) -option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" OFF) +option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" ON) if (NV_LOG) add_compile_definitions(ENABLE_NV_LOG) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 11f4d2368..346396c54 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -24,12 +24,12 @@ void nv3_render_current_bpp_dfb_16(uint32_t address); void nv3_render_current_bpp_dfb_32(uint32_t address); void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); -uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); -uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); -uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); +uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj); +uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj); +uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination); +uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj); uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 6582ada13..b1dc30ea0 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -47,12 +47,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* This is the last one*/ nv3->pgraph.blit.size.w = (param & 0xFFFF); nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB Size %04x,%04x grobj_0=0x%08x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y, grobj.grobj_0); - - /* Some blits have (point_in == point_out) ???? */ - if (nv3->pgraph.blit.point_in.x == nv3->pgraph.blit.point_out.x - && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y) - return; + nv_log("Method Execution: S2SB Size %04x,%04x grobj_0=0x%08x\n", nv3->pgraph.blit.size.w, nv3->pgraph.blit.size.h, grobj.grobj_0); /* Some of these seem to have sizes of 0, so skip */ if (nv3->pgraph.blit.size.h == 0 diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 0ec7cdd2d..80c635a21 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -35,7 +35,7 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t { /* mthdCreate in software(?)*/ case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - nv_log("mthdCreate obj_name=0x%08x\n", param); + //nv_log("mthdCreate obj_name=0x%08x\n", param); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); break; // set up the current notification request/object diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index babe7a056..785016a72 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -38,8 +38,8 @@ static video_timings_t timing_nv3t_pci = { .type = VIDEO_PCI, .write_b = 2, .wri static video_timings_t timing_nv3t_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; // Prototypes for functions only used in this translation unit -void nv3_init_mappings_mmio(); -void nv3_init_mappings_svga(); +void nv3_init_mappings_mmio(void); +void nv3_init_mappings_svga(void); bool nv3_is_svga_redirect_address(uint32_t addr); uint8_t nv3_svga_in(uint16_t addr, void* priv); @@ -873,7 +873,7 @@ void nv3_prom_write(uint32_t address, uint32_t value) } // Initialise the MMIO mappings -void nv3_init_mappings_mmio() +void nv3_init_mappings_mmio(void) { nv_log("Initialising MMIO mapping\n"); @@ -913,7 +913,7 @@ void nv3_init_mappings_mmio() } -void nv3_init_mappings_svga() +void nv3_init_mappings_svga(void) { nv_log("Initialising SVGA core memory mapping\n"); @@ -944,14 +944,14 @@ void nv3_init_mappings_svga() nv3); } -void nv3_init_mappings() +void nv3_init_mappings(void) { nv3_init_mappings_mmio(); nv3_init_mappings_svga(); } // Updates the mappings after initialisation. -void nv3_update_mappings() +void nv3_update_mappings(void) { // sanity check if (!nv3) @@ -1177,6 +1177,7 @@ void* nv3_init_pci(const device_t* info) nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); nv3->nvbase.bus_generation = nv_bus_pci; nv3_init(info); + return nv3; } // This function simply allocates ram and sets the bus to agp before initialising. @@ -1185,6 +1186,7 @@ void* nv3_init_agp(const device_t* info) nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); nv3->nvbase.bus_generation = nv_bus_agp_1x; nv3_init(info); + return nv3; } void nv3_close(void* priv) @@ -1210,7 +1212,7 @@ void nv3_close(void* priv) } // See if the bios rom is available. -int32_t nv3_available() +int32_t nv3_available(void) { return rom_present(NV3_VBIOS_ASUS_V3000_V151) || rom_present(NV3_VBIOS_DIAMOND_V330_V162) diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 09a099977..fd32e4e61 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -30,7 +30,7 @@ #include <86box/nv/vid_nv3.h> /* Check the line bounds */ -void nv3_class_011_check_line_bounds() +void nv3_class_011_check_line_bounds(void) { uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x; //uint32_t relative_y = nv3->pgraph.image_current_position.y - nv3->pgraph.image.point.y; @@ -174,7 +174,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) old_position.y = nv3->pgraph.blit.point_in.y + y; /* 32bit buffer */ buf_position = (nv3->pgraph.blit.size.w * y); - vram_position = nv3_render_get_vram_address(old_position, grobj, false); + vram_position = nv3_render_get_vram_address(old_position, grobj); memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); } @@ -184,7 +184,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { buf_position = (nv3->pgraph.blit.size.w * y); new_position.y = nv3->pgraph.blit.point_out.y + y; - vram_position = nv3_render_get_vram_address(new_position, grobj, true); + vram_position = nv3_render_get_vram_address(new_position, grobj); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); } @@ -221,6 +221,8 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out blit_position.y = nv3->pgraph.blit.point_out.y; + uint32_t buf_end = ((nv3->nvbase.svga.bpp + 1) >> 3) * xsize * ysize; - nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj); + //if (nv3->pgraph.boffset[dst_buffer] <= buf_end) + //nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj); } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 4313ac2a6..7d27a2623 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -219,30 +219,23 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool } /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ -uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) +uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj) { uint32_t vram_x = position.x; uint32_t vram_y = position.y; uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - /* test DST_BUFFER code - I assume for 2d at least only one is allowed at a time - */ + uint32_t destination_buffer = 5; // 5 = just use the source buffer - if (use_destination) - { - uint32_t destination_buffer = 5; // 5 = just use the source buffer + // src is hardcoded to 1, dst to 0. Hmm... + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) destination_buffer = 0; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) destination_buffer = 1; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) destination_buffer = 2; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) destination_buffer = 3; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) destination_buffer = 0; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) destination_buffer = 1; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) destination_buffer = 2; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) destination_buffer = 3; - - if (destination_buffer != current_buffer - && destination_buffer != 5) - current_buffer = destination_buffer; - - } + if (destination_buffer != current_buffer + && destination_buffer != 5) + current_buffer = destination_buffer; uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; @@ -300,19 +293,19 @@ nv3_position_16_t nv3_render_get_dfb_position(uint32_t vram_address) } /* Read an 8bpp pixel from the framebuffer. */ -uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) +uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj) { // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); + uint32_t vram_address = nv3_render_get_vram_address(position, grobj); return nv3->nvbase.svga.vram[vram_address]; } /* Read an 16bpp pixel from the framebuffer. */ -uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) +uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) { // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); + uint32_t vram_address = nv3_render_get_vram_address(position, grobj); uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); vram_address >>= 1; //convert to 16bit pointer @@ -321,10 +314,10 @@ uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, } /* Read an 16bpp pixel from the framebuffer. */ -uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination) +uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) { // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination); + uint32_t vram_address = nv3_render_get_vram_address(position, grobj); uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); vram_address >>= 2; //convert to 32bit pointer @@ -372,7 +365,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob if (!nv3_render_chroma_test(color, grobj)) return; - uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj, true); + uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj); uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0; uint8_t bit = 0x00; @@ -481,7 +474,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob } /* Ensure the correct monitor size */ -void nv3_render_ensure_mode() +void nv3_render_ensure_screen_size(void) { bool changed = false; //doesn't check if the res is the same? @@ -570,7 +563,11 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) { /* Ensure that we are in the correct mode. Modified SVGA core code */ - nv3_render_ensure_mode(); + nv3_render_ensure_screen_size(); + + /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM */ + //if (nv3->nvbase.last_buffer_address > (((nv3->nvbase.svga.bpp + 1) >> 3) * xsize * ysize)) + //return; switch (nv3->nvbase.svga.bpp) { @@ -622,7 +619,7 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t y = 0; y < size.h; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask; + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; for (uint32_t x = 0; x < size.w; x++) { @@ -661,7 +658,7 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t y = 0; y < size.h; y++) { /* re-get the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask; + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; for (uint32_t x = 0; x < size.w; x++) { @@ -700,7 +697,7 @@ void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t y = 0; y < size.h; y++) { /* re-get the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask; + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; for (uint32_t x = 0; x < size.w; x++) diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 67a052d50..16934998c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -39,7 +39,7 @@ nv_register_t pbus_registers[] = { { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; -void nv3_pbus_init() +void nv3_pbus_init(void) { nv_log("Initialising PBUS..."); diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 4ce686335..da068e07f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -30,7 +30,7 @@ /* Nvidia DMA Engine */ -void nv3_dma_translate_address() +void nv3_dma_translate_address(void) { } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 30ba68c03..5d7448241 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -29,7 +29,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_pextdev_init() +void nv3_pextdev_init(void) { nv_log("Initialising PEXTDEV....\n"); diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 0b36a3993..bf61f32af 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -43,7 +43,7 @@ nv_register_t pfb_registers[] = { { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; -void nv3_pfb_init() +void nv3_pfb_init(void) { nv_log("Initialising PFB..."); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index ea39b9135..0a6a843a5 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -77,7 +77,7 @@ nv_register_t pfifo_registers[] = { }; // PFIFO init code -void nv3_pfifo_init() +void nv3_pfifo_init(void) { nv_log("Initialising PFIFO..."); @@ -347,7 +347,7 @@ uint32_t nv3_pfifo_read(uint32_t address) return ret; } -void nv3_pfifo_trigger_dma_if_required() +void nv3_pfifo_trigger_dma_if_required(void) { // Not a thing for cache0 @@ -697,7 +697,7 @@ NV_USER writes always go to CACHE1 */ // Pulls graphics objects OUT of cache0 -void nv3_pfifo_cache0_pull() +void nv3_pfifo_cache0_pull(void) { // Do nothing if PFIFO CACHE0 is disabled if (!nv3->pfifo.cache0_settings.pull0 & (1 >> NV3_PFIFO_CACHE0_PULL0_ENABLED)) @@ -887,7 +887,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) } // Pulls graphics objects OUT of cache1 -void nv3_pfifo_cache1_pull() +void nv3_pfifo_cache1_pull(void) { // Do nothing if PFIFO CACHE1 is disabled if (!nv3->pfifo.cache1_settings.pull0 & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) @@ -956,7 +956,7 @@ void nv3_pfifo_cache1_pull() } // THIS IS PER SUBCHANNEL! -uint32_t nv3_pfifo_cache1_num_free_spaces() +uint32_t nv3_pfifo_cache1_num_free_spaces(void) { // get the index diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 82ad95706..43befe49c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -30,7 +30,7 @@ #include <86box/nv/classes/vid_nv3_classes.h> // Initialise the PGRAPH subsystem. -void nv3_pgraph_init() +void nv3_pgraph_init(void) { nv_log("Initialising PGRAPH..."); // Set up the vblank interrupt diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 050af07fa..3ede8b691 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -28,9 +28,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> - - -void nv3_pmc_init() +void nv3_pmc_init(void) { nv_log("Initialising PMC....\n"); @@ -58,7 +56,7 @@ nv_register_t pmc_registers[] = { { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; -uint32_t nv3_pmc_clear_interrupts() +uint32_t nv3_pmc_clear_interrupts(void) { nv_log_verbose_only("Clearing IRQs\n"); pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c index b18797a65..1f0da2aac 100644 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ b/src/video/nv/nv3/subsystems/nv3_pme.c @@ -34,7 +34,7 @@ nv_register_t pme_registers[] = { { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; -void nv3_pme_init() +void nv3_pme_init(void) { nv_log("Initialising PME..."); diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index d1fb9f1c5..8f16cb015 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -31,7 +31,7 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -void nv3_pramdac_init() +void nv3_pramdac_init(void) { nv_log("Initialising PRAMDAC\n"); @@ -83,7 +83,7 @@ void nv3_pramdac_memory_clock_poll(double real_time) } // Gets the vram clock register. -uint32_t nv3_pramdac_get_vram_clock_register() +uint32_t nv3_pramdac_get_vram_clock_register(void) { // the clock format is packed into 19 bits // M divisor [7-0] @@ -94,7 +94,7 @@ uint32_t nv3_pramdac_get_vram_clock_register() + (nv3->pramdac.memory_clock_p << 16); // 0-3 } -uint32_t nv3_pramdac_get_pixel_clock_register() +uint32_t nv3_pramdac_get_pixel_clock_register(void) { return (nv3->pramdac.pixel_clock_m) + (nv3->pramdac.pixel_clock_n << 8) @@ -119,7 +119,7 @@ void nv3_pramdac_set_pixel_clock_register(uint32_t value) nv3_pramdac_set_pixel_clock(); } -void nv3_pramdac_set_vram_clock() +void nv3_pramdac_set_vram_clock(void) { // from driver and vbios source float frequency = 13500000.0f; @@ -150,7 +150,7 @@ void nv3_pramdac_set_vram_clock() rivatimer_set_period(nv3->nvbase.memory_clock_timer, time); } -void nv3_pramdac_set_pixel_clock() +void nv3_pramdac_set_pixel_clock(void) { // frequency divider algorithm from old varcem/86box/pcbox riva driver, // verified by reversing NT drivers v1.50e CalcMNP [symbols] function diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c index 3a882b5b8..ab14be4f9 100644 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c @@ -41,7 +41,7 @@ nv_register_t ptimer_registers[] = { }; // ptimer init code -void nv3_ptimer_init() +void nv3_ptimer_init(void) { nv_log("Initialising PTIMER..."); diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c index c883ee7e5..60019b9c6 100644 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c @@ -39,7 +39,7 @@ nv_register_t pvideo_registers[] = { }; // ptimer init code -void nv3_pvideo_init() +void nv3_pvideo_init(void) { nv_log("Initialising PVIDEO..."); From d93b3de9aae7344d095dbd2d83078be35c43b9fe Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 10 Apr 2025 19:30:50 +0100 Subject: [PATCH 165/274] Fix compilation of nv_log_verbose_only --- src/video/nv/nv_base.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c index bce7425c2..c7a83d5ad 100644 --- a/src/video/nv/nv_base.c +++ b/src/video/nv/nv_base.c @@ -78,6 +78,8 @@ void nv_log(const char *fmt, ...) void nv_log_verbose_only(const char *fmt, ...) { #ifdef ENABLE_NV_LOG_ULTRA + va_list arg; + if (!nv_do_log) return; From e1ad1d39eb707ab102f71a107c50d4387eda1a52 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 12 Apr 2025 00:12:57 +0100 Subject: [PATCH 166/274] hopefully fix build with GHA cfg --- src/include/86box/nv/vid_nv3.h | 2 +- src/video/nv/nv3/nv3_core.c | 6 +++--- src/video/nv/nv3/subsystems/nv3_pextdev.c | 2 +- src/video/nv/nv3/subsystems/nv3_pfb.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 5 ++--- src/video/nv/nv3/subsystems/nv3_pmc.c | 2 +- src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c | 3 ++- src/video/nv/nv3/subsystems/nv3_pramin_ramht.c | 1 + src/video/nv/nv3/subsystems/nv3_pramin_ramro.c | 1 + 9 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index f11a4cdfc..43abf63df 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1557,7 +1557,7 @@ void nv3_user_write(uint32_t address, uint32_t value); // NV3 PMC void nv3_pmc_init(void); -uint32_t nv3_pmc_clear_interrupts(void); +void nv3_pmc_clear_interrupts(void); uint32_t nv3_pmc_handle_interrupts(bool send_now); // NV3 PGRAPH diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 785016a72..ff684ba47 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -616,7 +616,7 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv) return ret; // must be dword aligned - uint32_t real_rma_read_addr = ((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX - 1) << 1) + (addr & 0x03); + uint32_t real_rma_read_addr = (((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX) - 1) << 1) + (addr & 0x03); ret = nv3_pbus_rma_read(real_rma_read_addr); return ret; } @@ -869,7 +869,7 @@ uint8_t nv3_prom_read(uint32_t address) void nv3_prom_write(uint32_t address, uint32_t value) { uint32_t real_addr = address & 0x1FFFF; - nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value); + nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", real_addr, value); } // Initialise the MMIO mappings @@ -974,7 +974,7 @@ void nv3_update_mappings(void) nv3_svga_out, NULL, NULL, nv3); - if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM) + if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) { nv_log("The memory was turned off, not much is going to happen.\n"); return; diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 5d7448241..9aa17698f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -134,7 +134,7 @@ void nv3_pextdev_write(uint32_t address, uint32_t value) // special consideration for straps if (address == NV3_PSTRAPS) { - warning("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps); + warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps); return; } diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index bf61f32af..3e6cd4271 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -29,7 +29,7 @@ #include <86box/nv/vid_nv3.h> // Functions only used in this translation unit -uint32_t nv3_pfb_config0_read(); +uint32_t nv3_pfb_config0_read(void); void nv3_pfb_config0_write(uint32_t val); nv_register_t pfb_registers[] = { @@ -170,7 +170,7 @@ void nv3_pfb_write(uint32_t address, uint32_t value) } } -uint32_t nv3_pfb_config0_read() +uint32_t nv3_pfb_config0_read(void) { return nv3->pfb.config_0; } diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 0a6a843a5..69b834df9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -760,8 +760,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel) if (new_channel >= NV3_DMA_CHANNELS) fatal("nv3_pfifo_context_switch: Tried to switch to invalid dma channel"); - uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF; - + //uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF; } // NV_USER writes go here! @@ -820,7 +819,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) { // Cache reassignment required if (!nv3->pfifo.cache_reassignment - || (nv3->pfifo.cache1_settings.get_address != nv3->pfifo.cache1_settings.get_address)) + || (nv3->pfifo.cache1_settings.get_address != nv3->pfifo.cache1_settings.put_address)) { oh_shit = true; oh_shit_reason = nv3_runout_reason_no_cache_available; diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c index 3ede8b691..b6528fe0a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ b/src/video/nv/nv3/subsystems/nv3_pmc.c @@ -56,7 +56,7 @@ nv_register_t pmc_registers[] = { { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; -uint32_t nv3_pmc_clear_interrupts(void) +void nv3_pmc_clear_interrupts(void) { nv_log_verbose_only("Clearing IRQs\n"); pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c index 51d33c9a6..59fa41e8d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c @@ -30,7 +30,8 @@ uint32_t nv3_ramfc_read(uint32_t address) { - nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x)\n", address); + nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x) (UNIMPLEMENTED returning 0x00)\n", address); + return 0x00; //temp } void nv3_ramfc_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c index d2d17d321..9f90b3434 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c @@ -47,6 +47,7 @@ uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) uint32_t nv3_ramht_read(uint32_t address) { nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); + return 0x00; } void nv3_ramht_write(uint32_t address, uint32_t value) diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c index 692a10e91..142d746d2 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c @@ -31,6 +31,7 @@ uint32_t nv3_ramro_read(uint32_t address) { nv_log("BIG Problem: RAM Runout (invalid dma object submission) Read (0x%04x)\n", address); + return 0x00; } void nv3_ramro_write(uint32_t address, uint32_t value) From b606129b780f9b36358f0400c87cf331ee727ae5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 12 Apr 2025 00:23:17 +0100 Subject: [PATCH 167/274] Add string.h to nv3_render_blit --- src/video/nv/nv3/render/nv3_render_blit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index fd32e4e61..dc6c74aa3 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -19,6 +19,7 @@ #include #include #include +#include #include <86box/86box.h> #include <86box/device.h> #include <86box/mem.h> From 15f49638e03d61ceeb2bfd0af2a12dfb4bc3f8b8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 12 Apr 2025 03:02:55 +0100 Subject: [PATCH 168/274] Big improvement to S2SB, but it doesn't fully work yet. Sometimes it copies in the other direction, what ? --- .../86box/nv/classes/vid_nv3_classes.h | 4 + src/include/86box/nv/render/vid_nv3_render.h | 3 +- src/include/86box/nv/vid_nv3.h | 4 +- .../classes/nv3_class_01c_image_in_memory.c | 4 + src/video/nv/nv3/nv3_core.c | 52 ++++++------- src/video/nv/nv3/render/nv3_render_blit.c | 76 ++++++++++++++----- src/video/nv/nv3/render/nv3_render_core.c | 63 +++++++++++++-- 7 files changed, 151 insertions(+), 55 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 3b6eb1411..5647a3c81 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -77,6 +77,10 @@ typedef enum nv3_pgraph_class_e #define NV3_SET_NOTIFY_CONTEXT_FOR_DMA 0x0100 // Set object ctx for dma...see nv3_dma_context_t structure #define NV3_SET_NOTIFY 0x0104 +// Crap e.g. "OS name", that sometimes gets submitted, for some reason. So we just suppress the warning messages for them +#define NV3_NVCLASS_CRAP_START 0x0310 +#define NV3_NVCLASS_CRAP_END 0x0324 + // Render OPeration #define NV3_ROP_SET_ROP 0x0300 // Set GDI standard rop diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 346396c54..68bc7d557 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,7 +18,7 @@ #pragma once /* Core */ -void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); +void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check); void nv3_render_current_bpp_dfb_8(uint32_t address); void nv3_render_current_bpp_dfb_16(uint32_t address); void nv3_render_current_bpp_dfb_32(uint32_t address); @@ -30,6 +30,7 @@ uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj); +uint32_t nv3_render_get_vram_address_for_buffer(nv3_position_16_t position, nv3_grobj_t grobj, uint32_t buffer); uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 43abf63df..6d5c8cfca 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1473,8 +1473,8 @@ void nv3_dfb_write8(uint32_t addr, uint8_t val, void* priv); void nv3_dfb_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit DFB void nv3_dfb_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit DFB -uint8_t nv3_svga_in(uint16_t addr, void* priv); // Read SVGA compatibility registers -void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); // Write SVGA registers +uint8_t nv3_svga_read(uint16_t addr, void* priv); // Read SVGA compatibility registers +void nv3_svga_write(uint16_t addr, uint8_t val, void* priv); // Write SVGA registers uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv); // Read PCI configuration registers void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 9e6a55310..87cf01812 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -86,6 +86,10 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x\n", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); break; + case NV3_NVCLASS_CRAP_START ... NV3_NVCLASS_CRAP_END: + /* Suppress but don't do anything */ + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + break; default: warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index ff684ba47..1f786fc47 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -42,8 +42,8 @@ void nv3_init_mappings_mmio(void); void nv3_init_mappings_svga(void); bool nv3_is_svga_redirect_address(uint32_t addr); -uint8_t nv3_svga_in(uint16_t addr, void* priv); -void nv3_svga_out(uint16_t addr, uint8_t val, void* priv); +uint8_t nv3_svga_read(uint16_t addr, void* priv); +void nv3_svga_write(uint16_t addr, uint8_t val, void* priv); // Determine if this address needs to be redirected to the SVGA subsystem. @@ -70,7 +70,7 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - ret = nv3_svga_in(real_address, nv3); + ret = nv3_svga_read(real_address, nv3); nv_log_verbose_only("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); @@ -95,8 +95,8 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - ret = nv3_svga_in(real_address, nv3) - | (nv3_svga_in(real_address + 1, nv3) << 8); + ret = nv3_svga_read(real_address, nv3) + | (nv3_svga_read(real_address + 1, nv3) << 8); nv_log_verbose_only("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); @@ -120,10 +120,10 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) // svga writes are not logged anyway rn uint32_t real_address = addr & 0x3FF; - ret = nv3_svga_in(real_address, nv3) - | (nv3_svga_in(real_address + 1, nv3) << 8) - | (nv3_svga_in(real_address + 2, nv3) << 16) - | (nv3_svga_in(real_address + 3, nv3) << 24); + ret = nv3_svga_read(real_address, nv3) + | (nv3_svga_read(real_address + 1, nv3) << 8) + | (nv3_svga_read(real_address + 2, nv3) << 16) + | (nv3_svga_read(real_address + 3, nv3) << 24); nv_log_verbose_only("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); @@ -152,7 +152,7 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) nv_log_verbose_only("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - nv3_svga_out(real_address, val & 0xFF, nv3); + nv3_svga_write(real_address, val & 0xFF, nv3); return; } @@ -180,8 +180,8 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - nv3_svga_out(real_address, val & 0xFF, nv3); - nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); + nv3_svga_write(real_address, val & 0xFF, nv3); + nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); return; } @@ -208,10 +208,10 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - nv3_svga_out(real_address, val & 0xFF, nv3); - nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3); - nv3_svga_out(real_address + 2, (val >> 16) & 0xFF, nv3); - nv3_svga_out(real_address + 3, (val >> 24) & 0xFF, nv3); + nv3_svga_write(real_address, val & 0xFF, nv3); + nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); + nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3); + nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3); return; } @@ -597,7 +597,7 @@ void nv3_force_redraw(void* priv) } // Read from SVGA core memory -uint8_t nv3_svga_in(uint16_t addr, void* priv) +uint8_t nv3_svga_read(uint16_t addr, void* priv) { nv3_t* nv3 = (nv3_t*)priv; @@ -662,7 +662,7 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv) } // Write to SVGA core memory -void nv3_svga_out(uint16_t addr, uint8_t val, void* priv) +void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) { // sanity check if (!nv3) @@ -939,8 +939,8 @@ void nv3_init_mappings_svga(void) nv3->nvbase.svga.vram, 0, &nv3->nvbase.svga); io_sethandler(0x03c0, 0x0020, - nv3_svga_in, NULL, NULL, - nv3_svga_out, NULL, NULL, + nv3_svga_read, NULL, NULL, + nv3_svga_write, NULL, NULL, nv3); } @@ -964,14 +964,14 @@ void nv3_update_mappings(void) (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); io_removehandler(0x03c0, 0x0020, - nv3_svga_in, NULL, NULL, - nv3_svga_out, NULL, NULL, + nv3_svga_read, NULL, NULL, + nv3_svga_write, NULL, NULL, nv3); if (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) io_sethandler(0x03c0, 0x0020, - nv3_svga_in, NULL, NULL, - nv3_svga_out, NULL, NULL, + nv3_svga_read, NULL, NULL, + nv3_svga_write, NULL, NULL, nv3); if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) @@ -1117,7 +1117,7 @@ void* nv3_init(const device_t *info) pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); + nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_pci); @@ -1132,7 +1132,7 @@ void* nv3_init(const device_t *info) pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_in, nv3_svga_out, nv3_draw_cursor, NULL); + nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_agp); diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index dc6c74aa3..788cb4ca2 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -130,14 +130,10 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) && nv3->pgraph.blit.size.h < NV3_MAX_VERTICAL_SIZE) memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.h) * (sizeof(uint32_t) * nv3->pgraph.blit.size.w)); - nv3_position_16_t old_position = nv3->pgraph.blit.point_in; - nv3_position_16_t new_position = nv3->pgraph.blit.point_out; - + /* First calculate our source and destination buffer */ uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - /* test DST_BUFFER code - I assume for 2d at least only one is allowed at a time - */ + bool wtf_nvidia = false; uint32_t dst_buffer = 0; // 5 = just use the source buffer @@ -145,13 +141,23 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; + + nv3_position_16_t old_position; + nv3_position_16_t new_position; - - uint16_t end_x_in = (nv3->pgraph.blit.point_in.x + nv3->pgraph.blit.size.w); /* needed for bounds checking */ - uint16_t end_x_out = (nv3->pgraph.blit.point_out.x + nv3->pgraph.blit.size.w); - uint16_t end_y = (nv3->pgraph.blit.point_out.y + nv3->pgraph.blit.size.h); - - uint32_t pixel_to_copy = 0x00; + /* If src_buffer != dst_buffer, the positions and src/dst buffer seem to be swapped. + Some kind of hardware errata (?), otherwise, I have no explanation for this behaviour. */ + if (nv3->pgraph.boffset[src_buffer] == nv3->pgraph.boffset[dst_buffer]) + { + old_position = nv3->pgraph.blit.point_in; + new_position = nv3->pgraph.blit.point_out; + } + else + { + old_position = nv3->pgraph.blit.point_out; + new_position = nv3->pgraph.blit.point_in; + wtf_nvidia = true; + } /* Coordinates for copying an entire line at a time */ uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.w; @@ -170,23 +176,35 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) else if (nv3->nvbase.svga.bpp == 32) size_x <<= 2; + for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) { - old_position.y = nv3->pgraph.blit.point_in.y + y; - /* 32bit buffer */ buf_position = (nv3->pgraph.blit.size.w * y); - vram_position = nv3_render_get_vram_address(old_position, grobj); + /* shouldn't matter in non-wtf mode */ + vram_position = nv3_render_get_vram_address_for_buffer(old_position, grobj, dst_buffer); memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); + old_position.y++; + /* 32bit buffer */ } /* simply write it all back to vram */ for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) { buf_position = (nv3->pgraph.blit.size.w * y); - new_position.y = nv3->pgraph.blit.point_out.y + y; - vram_position = nv3_render_get_vram_address(new_position, grobj); + + /* Trying to avoid making the above function more complex. It seems, src is used most of th etime...But this is bad... */ + if (wtf_nvidia) + { + /* Use the parameters of our dst buffer with the position of our source buffer, seriously, who was thinking of this */ + vram_position = nv3_render_get_vram_address_for_buffer(new_position, grobj, src_buffer); + //vram_position = vram_position - nv3->pgraph.boffset[dst_buffer] + nv3->pgraph.boffset[src_buffer]; + } + else + vram_position = nv3_render_get_vram_address(new_position, grobj); + memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); + new_position.y++; } /* @@ -222,8 +240,26 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out blit_position.y = nv3->pgraph.blit.point_out.y; - uint32_t buf_end = ((nv3->nvbase.svga.bpp + 1) >> 3) * xsize * ysize; - //if (nv3->pgraph.boffset[dst_buffer] <= buf_end) - //nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj); + /* Figure out the Display Buffer Address from the CRTCs */ + uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) + + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) + + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; + + /* If the BUFFER_ADDRESS of the last buffer is not the DBA, we don't *actually* want to draw this, so let's not + Apply stupid hack */ + + if (wtf_nvidia) + { + if (nv3->pgraph.boffset[src_buffer] != dba) + return; + } + else + { + if (nv3->pgraph.boffset[dst_buffer] != dba) + return; + } + + + nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj, false); } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 7d27a2623..6a6a8e587 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -225,6 +225,7 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro uint32_t vram_y = position.y; uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + /* uint32_t destination_buffer = 5; // 5 = just use the source buffer // src is hardcoded to 1, dst to 0. Hmm... @@ -236,7 +237,7 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro if (destination_buffer != current_buffer && destination_buffer != 5) current_buffer = destination_buffer; - +*/ uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // we have to multiply the x position by the number of bytes per pixel @@ -260,6 +261,36 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro return pixel_addr_vram; } + +/* Combine the current buffer with the pitch to get the address in the video ram for a specific position relative to a specific framebuffer */ +uint32_t nv3_render_get_vram_address_for_buffer(nv3_position_16_t position, nv3_grobj_t grobj, uint32_t buffer) +{ + uint32_t vram_x = position.x; + uint32_t vram_y = position.y; + + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; + + // we have to multiply the x position by the number of bytes per pixel + switch (framebuffer_bpp) + { + case 8: + break; + case 15: + case 16: + vram_x = position.x << 1; + break; + case 32: + vram_x = position.x << 2; + break; + } + + uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[buffer] * vram_y) + nv3->pgraph.boffset[buffer]; + + pixel_addr_vram &= nv3->nvbase.svga.vram_mask; + + return pixel_addr_vram; +} + /* Convert a dumb framebuffer address to a position. No buffer setup or anything, but just start at 0,0 for address 0. */ nv3_position_16_t nv3_render_get_dfb_position(uint32_t vram_address) { @@ -470,7 +501,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob /* Go write the pixel */ nv3_size_16_t size = {0}; size.w = size.h = 1; - nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj); + nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, true); } /* Ensure the correct monitor size */ @@ -560,14 +591,34 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) /* Blit to the monitor from GPU, current bpp */ -void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check) { /* Ensure that we are in the correct mode. Modified SVGA core code */ nv3_render_ensure_screen_size(); - /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM */ - //if (nv3->nvbase.last_buffer_address > (((nv3->nvbase.svga.bpp + 1) >> 3) * xsize * ysize)) - //return; + /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM, so it can be used for s2sb's etc */ + + /* Not needed for s2sb*/ + if (run_render_check) + { + /* Figure out the Display Buffer Address from the CRTCs */ + uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) + + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) + + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; + + /* Check our destination(?) buffer */ + uint32_t dst_buffer = 0; // 5 = just use the source buffer + + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; + + /* If the BUFFER_ADDRESS of the last buffer is not the DBA, we don't *actually* want to draw this, so let's not */ + if (nv3->pgraph.boffset[dst_buffer] != dba) + return; + } + switch (nv3->nvbase.svga.bpp) { From 371a2d269b15710d884ba74410a50f5ce2286a56 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 12 Apr 2025 14:53:42 +0100 Subject: [PATCH 169/274] Turn off ultra logging --- CMakeLists.txt | 2 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c9825b9ef..52f24f4b9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -139,7 +139,7 @@ option(DISCORD "Discord Rich Presence support" option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) # Remove when merged, should just be -D option(NV_LOG "NVidia RIVA 128 debug logging" ON) -option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" ON) +option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" OFF) if (NV_LOG) add_compile_definitions(ENABLE_NV_LOG) diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 8f16cb015..5597e2f73 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -405,4 +405,9 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) { nv_log(": Unknown register write (address=0x%08x)\n", address); } +} + +uint32_t nv3_pramdac_read_clut(void) //4bpp/8bpp +{ + } \ No newline at end of file From 801aa4a97dd85c602be7d85bf4fa02f407d9efe1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 12 Apr 2025 17:28:04 +0100 Subject: [PATCH 170/274] Fix framebuffer size with vertical resolution > 1024 by applying large screen bit even in NV mode --- doc/nvidia_notes/status.xlsx | Bin 16043 -> 15992 bytes src/video/nv/nv3/nv3_core.c | 15 +++++++++++---- src/video/nv/nv3/render/nv3_render_core.c | 2 +- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index 1ddb8b34dbfc1e4e750f4992b5d7e696dbe20b39..4e02b672cb00475d41b8a9e3411d5ca4a9365291 100644 GIT binary patch delta 6573 zcmZ8m1yCJJv&P-s-CctmEVu^^t|7R4utfqv4tnrFaJS&@C%6+JxLXJgL4y3;RK0iK z`=_R+dUt!eW~=+_`KG5L@HXJsaSxrN|q};AM=iSbo$cCI{PUu+el%zBFbOZ8MR{s2F z>akP{gX+)i*jUE--F~39kr5rkuA`;D%}^5xyRXuswI$GPBwXvH6mAgZFaZofgXm_S z0?sE(E-8uQ*(azuVa(kv^^_aSjz;q7FjH+h7%?~;xX3Cuv>lBX(Lz-WaPu>lu5qJR zkhHC-akS2HF}h4=L&tol1wWR-N74wsl`?zVkRooV9e_~XyH)Fu9V)~rRcWg>2Z3#@ zDpuqc0;6}7_a1i=8~Vd`qX19h2-w|{sH)5gf(v^U0uzKk`s<(2B+@%=No zx>Z~ORJP&(QU#H9ZWU9G#ne;+NuKIRV=SxaHx66GAEVKaJJC<5S*X_5Kf$F(HxO?( z;t_S2O>{|1JD(HHzyowJ(Zzn;v`=dXA%t|-R9`fSkPRr1)sx2fnWYMT440gbWyFRe z?AF^Q#MkF+fFox@x7BsIGZv=sLBRq!>0O(FF6SCc(-$cN{C;;HSGOnA%R%;^yyDwS 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if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; + if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; + + if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) + svga->hdisp += 0x100; // large screen bit + + /* if (pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA) { if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) - svga->hdisp += 0x100; // large screen bit } - + */ /* Turn off override if we are in VGA mode */ svga->override = !(pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 6a6a8e587..fc4bce4d9 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -147,7 +147,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co warning("nv3_render_downconvert: Y8 not implemented"); break; case nv3_pgraph_pixel_format_y16: - warning("nv3_render_downconvert: Y16 not implemented"); + //warning("nv3_render_downconvert: Y16 not implemented"); break; default: warning("nv3_render_downconvert_color unknown format %d", format); From afcb3392240f6502cd75ee9cdfbc09bafedf113c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 13 Apr 2025 18:36:48 +0100 Subject: [PATCH 171/274] Get rid of useless "reserved" stuff and also implement 8bpp indexed mode using CLUT. --- doc/nvidia_notes/status.xlsx | Bin 15992 -> 15953 bytes .../86box/nv/classes/vid_nv3_classes.h | 92 ++--------------- src/include/86box/nv/render/vid_nv3_render.h | 9 +- src/include/86box/nv/vid_nv3.h | 21 +++- src/video/nv/nv3/nv3_core.c | 75 ++++++++------ src/video/nv/nv3/nv3_core_arbiter.c | 22 ++-- src/video/nv/nv3/render/nv3_render_core.c | 97 ++++++++++++------ src/video/nv/nv3/subsystems/nv3_pramdac.c | 48 ++++++++- 8 files changed, 203 insertions(+), 161 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index 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NV3_PDAC_END 0x680FFF // OPTIONAL external DAC -#define NV3_VGA_DAC_START 0x6813C6 -#define NV3_VGA_DAC_END 0x6813C9 + +#define NV3_USER_DAC_START 0x681200 +#define NV3_USER_DAC_PALETTE_START 0x6813C6 +#define NV3_USER_DAC_PIXEL_MASK 0x6813C6 +#define NV3_USER_DAC_READ_MODE_ADDRESS 0x6813C7 //bit0=read/write mode? +#define NV3_USER_DAC_WRITE_MODE_ADDRESS 0x6813C8 +#define NV3_USER_DAC_PALETTE_DATA 0x6813C9 +#define NV3_USER_DAC_PALETTE_SIZE 768 +#define NV3_USER_DAC_PALETTE_END 0x6813C9 +#define NV3_USER_DAC_END 0x681FFF #define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?) #define NV3_USER_END 0xFFFFFF @@ -1065,6 +1073,11 @@ typedef struct nv3_pramdac_s uint32_t htotal; // horizontal total lines uint32_t hequ_width; // horizontal equ width (not sure what this is) uint32_t hserr_width; // horizontal sync error width + + uint8_t user_pixel_mask; // pixel mask for DAC lookup + uint32_t user_read_mode_address; // user read mode address + uint32_t user_write_mode_address; // user write mode address + uint8_t palette[NV3_USER_DAC_PALETTE_SIZE]; // Palette Info/CLUT - 256 entriesxr,g,b = 768 bytes } nv3_pramdac_t; /* Holds DMA channel context information */ @@ -1133,7 +1146,7 @@ typedef struct nv3_pgraph_status_s } nv3_pgraph_status_t; /* All of this B* stuff is registers at 400630..40065c and 4006a8 in reality, easier to implement it like this - BPixel = Internal Binary Representation of the pixel within the architecture + BPixel = Buffer Pixel Format */ #define NV3_BPIXEL_FORMAT 0 #define NV3_BPIXEL_FORMAT_IS_VALID 2 diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 14788dcb3..e8456814f 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -49,9 +49,9 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv); bool nv3_is_svga_redirect_address(uint32_t addr) { - return (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) // VGA - || (addr >= NV3_PRMCIO_START && addr <= NV3_PRMCIO_END) // CRTC - || (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END); // Legacy RAMDAC support(?) + return (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) // VGA + || (addr >= NV3_PRMCIO_START && addr <= NV3_PRMCIO_END) // CRTC + || (addr >= NV3_USER_DAC_START && addr <= NV3_USER_DAC_END); // Note: 6813c6-6813c9 are ignored somewhere else } // All MMIO regs are 32-bit i believe internally @@ -65,6 +65,14 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv) // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. addr &= 0xFFFFFF; + // We need to specifically exclude this particular set of registers + // so we can write the 4/8bpp CLUT + if (addr >= NV3_USER_DAC_PALETTE_START && addr <= NV3_USER_DAC_PALETTE_END) + { + // Throw directly into PRAMDAC + return nv3_mmio_arbitrate_read(addr); + } + if (nv3_is_svga_redirect_address(addr)) { // svga writes are not logged anyway rn @@ -143,6 +151,15 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) { addr &= 0xFFFFFF; + // We need to specifically exclude this particular set of registers + // so we can write the 4/8bpp CLUT + if (addr >= NV3_USER_DAC_PALETTE_START && addr <= NV3_USER_DAC_PALETTE_END) + { + // Throw directly into PRAMDAC + nv3_mmio_arbitrate_write(addr, val); + return; + } + // This is weitek vga stuff // If we need to add more of these we can convert these to a switch statement if (nv3_is_svga_redirect_address(addr)) @@ -474,7 +491,7 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) break; default: - + break; } } @@ -493,31 +510,6 @@ void nv3_recalc_timings(svga_t* svga) svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; - // should these actually use separate values? - // i don't we should force the top 2 bits to 1... - - // required for VESA resolutions, force parameters higher - // only fuck around with any of this in VGAmode? - - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) svga->dispend += 0x400; - - if (svga->crtc[NV3_CRTC_REGISTER_HEB] & 0x01) - svga->hdisp += 0x100; // large screen bit - - /* - if (pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA) - { - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) svga->vtotal += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) svga->vblankstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) svga->vsyncstart += 0x400; - if (svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) svga->hdisp += 0x400; - - } - */ /* Turn off override if we are in VGA mode */ svga->override = !(pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA); @@ -698,7 +690,7 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) addr ^= 0x60; uint8_t crtcreg = nv3->nvbase.svga.crtcreg; - uint8_t old_value; + uint8_t old_value = 0x00; // todo: // Pixel formats (8bit vs 555 vs 565) @@ -747,12 +739,33 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) case NV3_CRTC_REGISTER_RMA: nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX; break; + /* Handle some large screen stuff */ + case NV3_CRTC_REGISTER_PIXELMODE: + if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) + nv3->nvbase.svga.vtotal += 0x400; + if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) + nv3->nvbase.svga.vblankstart += 0x400; + if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) + nv3->nvbase.svga.vsyncstart += 0x400; + if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) + nv3->nvbase.svga.hdisp += 0x400; + + /* Make sure dispend and vblankstart are right if we are displaying above 1024 vert */ + if (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) + nv3->nvbase.svga.dispend += 0x400; + + break; + case NV3_CRTC_REGISTER_HEB: + if (val & 0x01) + nv3->nvbase.svga.hdisp += 0x100; + break; case NV3_CRTC_REGISTER_I2C_GPIO: uint8_t scl = !!(val & 0x20); uint8_t sda = !!(val & 0x10); // Set an I2C GPIO register i2c_gpio_set(nv3->nvbase.i2c, scl, sda); break; + } /* Recalculate the timings if we actually changed them @@ -763,7 +776,7 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) // and in the words of an ex-Rendition/3dfx/NVIDIA engineer, "VGA was basically an undocumented bundle of steaming you-know-what. // And it was essential that any cores the PC 3D startups acquired had to work with all the undocumented modes and timing tweaks (mode X, etc.)" if (nv3->nvbase.svga.crtcreg < 0xE - && nv3->nvbase.svga.crtcreg > 0x10) + || nv3->nvbase.svga.crtcreg > 0x10) { nv3->nvbase.svga.fullchange = changeframecount; nv3_recalc_timings(&nv3->nvbase.svga); diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 2bb3ef8b4..99aebb5e7 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -58,9 +58,10 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) uint32_t ret = 0x00; - // note: some registers are byte aligned not dword aligned - // only very few are though, so they can be handled specially, using the register list most likely - address &= 0xFFFFFC; + // Ensure the addresses are dword aligned. + // I don't know why this is needed because writepriv32 is always to dword align, but it crashes if you don't do this. + if (!(address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) + address &= 0xFFFFFC; // gigantic set of if statements to send the write to the right subsystem if (address >= NV3_PMC_START && address <= NV3_PMC_END) @@ -97,7 +98,8 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) ret = nv3_prmcio_read(address); else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END) ret = nv3_pvideo_read(address); - else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) + else if ((address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) + || (address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) //clut ret = nv3_pramdac_read(address); else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) ret = nv3_dfb_read32(address & nv3->nvbase.svga.vram_mask, &nv3->nvbase.svga); @@ -121,9 +123,12 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. address &= 0xFFFFFF; - // note: some registers are byte aligned not dword aligned - // only very few are though, so they can be handled specially, using the register list most likely - address &= 0xFFFFFC; + + // Ensure the addresses are dword aligned. + // I don't know why this is needed because writepriv32 is always to dword align, but it crashes if you don't do this. + // Exclude the 4bpp/8bpp CLUT for this purpose + if (!(address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) + address &= 0xFFFFFC; // gigantic set of if statements to send the write to the right subsystem if (address >= NV3_PMC_START && address <= NV3_PMC_END) @@ -158,7 +163,8 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) nv3_prmcio_write(address, value); else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END) nv3_pvideo_write(address, value); - else if (address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) + else if ((address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) + || (address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) //clut nv3_pramdac_write(address, value); else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) nv3_dfb_write32(address, value, &nv3->nvbase.svga); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index fc4bce4d9..6eb1f50c1 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -88,6 +88,7 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) break; case nv3_pgraph_pixel_format_y8: + /* Indexed mode */ color_final.a = (color >> 8) & 0xFF; // yuv @@ -143,11 +144,11 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co packed_color |= (color.g << 20); packed_color |= (color.b << 10); break; - case nv3_pgraph_pixel_format_y8: - warning("nv3_render_downconvert: Y8 not implemented"); + case nv3_pgraph_pixel_format_y8: /* i think this is just indexed mode. since r=g=b we can just take the indexed from the r */ + packed_color = nv3_render_get_palette_index((color.r >> 2) & 0xFF); break; case nv3_pgraph_pixel_format_y16: - //warning("nv3_render_downconvert: Y16 not implemented"); + warning("nv3_render_downconvert: Y16 not implemented"); break; default: warning("nv3_render_downconvert_color unknown format %d", format); @@ -189,15 +190,24 @@ uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) return !!expanded.a | (expanded.r << 30) | (expanded.b << 20) | (expanded.a << 10); } -/* Convert a rgb10 colour to a pattern colour */ -uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1) +/* Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) */ +uint32_t nv3_render_get_palette_index(uint8_t index) +{ + uint32_t red_index = index * 3; + uint32_t green_index = red_index + 1; + uint32_t blue_index = red_index + 2; + + uint8_t red_colour = nv3->pramdac.palette[red_index]; + uint8_t green_colour = nv3->pramdac.palette[green_index]; + uint8_t blue_colour = nv3->pramdac.palette[blue_index]; + + /* Alpha is always 0xFF */ + return (0xFF << 24) | ((red_colour) << 16) | ((green_colour) << 8) | blue_colour; +} + +/* Convert a rgb10 colour to a pattern colour */ +void nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1) { - /* reset the colour */ - if (!use_color1) - nv3->pgraph.pattern_color_0_rgb.r = nv3->pgraph.pattern_color_0_rgb.g = nv3->pgraph.pattern_color_0_rgb.b = 0x00; - else - nv3->pgraph.pattern_color_1_rgb.r = nv3->pgraph.pattern_color_1_rgb.g = nv3->pgraph.pattern_color_1_rgb.b = 0x00; - /* select the right pattern colour, _rgb is already in RGB10 format, so we don't need to do any conversion */ if (!use_color1) @@ -359,7 +369,6 @@ uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) /* Plots a pixel. */ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj) { - uint8_t alpha = 0xFF; // PFB_0 is always set to hardcoded "NO_TILING" value of 0x1114. // It seems, you are meant to @@ -372,12 +381,6 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too?z - /* doesn't seem*/ - nv3_color_argb_t color_data = *(nv3_color_argb_t*)&color; - - if (framebuffer_bpp == 32) - alpha = color_data.a; - int32_t clip_end_x = nv3->pgraph.clip_start.x + nv3->pgraph.clip_size.x; int32_t clip_end_y = nv3->pgraph.clip_start.y + nv3->pgraph.clip_size.y; @@ -507,7 +510,8 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob /* Ensure the correct monitor size */ void nv3_render_ensure_screen_size(void) { - bool changed = false; //doesn't check if the res is the same? + /* First check if hdisp == xsize and dispend == ysize. */ + bool changed = false; if (nv3->nvbase.svga.hdisp != nv3->nvbase.svga.monitor->mon_xsize) { @@ -521,9 +525,13 @@ void nv3_render_ensure_screen_size(void) nv3->nvbase.svga.monitor->mon_ysize = nv3->nvbase.svga.dispend; } + /* + if either changed: + -> set resolution + -> set refresh rate - this is just a rough estimation right now. we need it as we only blit what changes + */ if (changed) { - /* set refresh rate - this is just a rough estimation right now. we need it as we only blit what changes */ nv3->nvbase.refresh_time = 1 / (nv3->nvbase.pixel_clock_frequency / (double)ysize / (double)xsize); // rivatimers count in microseconds set_screen_size(xsize, ysize); } @@ -534,7 +542,15 @@ void nv3_render_ensure_screen_size(void) /* Blit to the monitor from DFB, 8bpp */ void nv3_render_current_bpp_dfb_8(uint32_t address) { + nv3_size_16_t size = {0}; + size.w = size.h = 1; + nv3_position_16_t pos = nv3_render_get_dfb_position(address); + + uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); + + *p = nv3_render_get_palette_index(data & 0xFF); } /* Blit to the monitor from DFB, 15/16bpp */ @@ -545,8 +561,6 @@ void nv3_render_current_bpp_dfb_16(uint32_t address) nv3_position_16_t pos = nv3_render_get_dfb_position(address); - //pos.x >>= 1; - uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); @@ -623,8 +637,8 @@ void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t s switch (nv3->nvbase.svga.bpp) { case 4: - /* Uh we should never be here because we're in the SVGA mode */ - fatal("NV3 - Tried to render 4bpp in NV mode"); + /* Uh we should never be here because we're in the SVGA mode(?) */ + fatal("NV3 - 4bpp not implemented (not even sure if it's SVGA only)"); break; case 8: nv3_render_8bpp(pos, size, grobj); @@ -648,7 +662,36 @@ void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t s void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) { - + if (!nv3) + return; + + uint32_t vram_base; //acquired for the start of each line + uint32_t* p; + uint32_t data; + uint32_t start_x = pos.x; + + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + + for (uint32_t y = 0; y < size.h; y++) + { + /* re-set the vram address because we are basically "jumping" halfway across a line here */ + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; + + for (uint32_t x = 0; x < size.w; x++) + { + p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + + /* should just "tip over" to the next line */ + *p = nv3_render_get_palette_index(data & 0xFF); + + vram_base++; + pos.x++; + } + + pos.x = start_x; + pos.y++; + } } /* @@ -675,7 +718,6 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t x = 0; x < size.w; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; /* should just "tip over" to the next line */ @@ -714,7 +756,6 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t x = 0; x < size.w; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; /* should just "tip over" to the next line */ @@ -750,11 +791,9 @@ void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro /* re-get the vram address because we are basically "jumping" halfway across a line here */ vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - for (uint32_t x = 0; x < size.w; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; /* should just "tip over" to the next line */ diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 5597e2f73..f9f8b670c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -225,6 +225,10 @@ nv_register_t pramdac_registers[] = { NV3_PRAMDAC_HTOTAL, "PRAMDAC - Total Horizontal Lines", NULL, NULL}, { NV3_PRAMDAC_HEQU_WIDTH, "PRAMDAC - HEqu End", NULL, NULL}, { NV3_PRAMDAC_HSERR_WIDTH, "PRAMDAC - Horizontal Sync Error", NULL, NULL}, + { NV3_USER_DAC_PIXEL_MASK, "PRAMDAC - User DAC Pixel Mask", NULL, NULL}, + { NV3_USER_DAC_READ_MODE_ADDRESS, "PRAMDAC - User DAC Read Mode Address", NULL, NULL}, + { NV3_USER_DAC_WRITE_MODE_ADDRESS, "PRAMDAC - User DAC Write Mode Address", NULL, NULL}, + { NV3_USER_DAC_PALETTE_DATA, "PRAMDAC - User DAC Palette Data", NULL, NULL}, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -301,6 +305,21 @@ uint32_t nv3_pramdac_read(uint32_t address) case NV3_PRAMDAC_HSERR_WIDTH: ret = nv3->pramdac.hserr_width; break; + case NV3_USER_DAC_PIXEL_MASK: + ret = nv3->pramdac.user_pixel_mask; + break; + case NV3_USER_DAC_READ_MODE_ADDRESS: + ret = nv3->pramdac.user_read_mode_address; + break; + case NV3_USER_DAC_WRITE_MODE_ADDRESS: + ret = nv3->pramdac.user_write_mode_address; + break; + case NV3_USER_DAC_PALETTE_DATA: + /* I doubt NV actually read this in their drivers, but it's worth doing anyway */ + /* Bit 1 is listed as "read or write mode" and 7:0 as "Write-only address", but NV only ever set this to 0 too, so i think this should be fine for now */ + ret = nv3->pramdac.palette[nv3->pramdac.user_read_mode_address]; + nv3->pramdac.user_read_mode_address++; + break; } } @@ -390,8 +409,31 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) nv3->pramdac.hequ_width = value; break; case NV3_PRAMDAC_HSERR_WIDTH: - nv3->pramdac.hserr_width = value; + break; + case NV3_USER_DAC_PIXEL_MASK: + nv3->pramdac.user_pixel_mask = value; + break; + case NV3_USER_DAC_READ_MODE_ADDRESS: + nv3->pramdac.user_read_mode_address = value; + break; + case NV3_USER_DAC_WRITE_MODE_ADDRESS: + + /* + This seems to get reset to 0 after 256 writes, but, the palette is 768 bytes in size. + Clearly there's some mechanism here, but I'm not sure what it is. So let's just reset if we reach 768. + */ + if (nv3->pramdac.user_write_mode_address >= NV3_USER_DAC_PALETTE_SIZE) + nv3->pramdac.user_write_mode_address = value; + + break; + case NV3_USER_DAC_PALETTE_DATA: + /* I doubt NV actually read this in their drivers, but it's worth doing anyway */ + /* Bit 1 is listed as "read or write mode" and 7:0 as "Write-only address", but NV only ever set this to 0 too, so i think this should be fine for now */ + nv3->pramdac.palette[nv3->pramdac.user_write_mode_address] = value; + + nv3->pramdac.user_write_mode_address++; + break; } } @@ -407,7 +449,3 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) } } -uint32_t nv3_pramdac_read_clut(void) //4bpp/8bpp -{ - -} \ No newline at end of file From f170901c5563d093b14180dd6c06ba1d063c1fdd Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 15 Apr 2025 01:07:41 +0100 Subject: [PATCH 172/274] some logging fixes --- src/video/nv/nv3/classes/nv3_class_010_blit.c | 6 +++--- src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c | 1 + src/video/nv/nv3/render/nv3_render_blit.c | 4 ++-- src/video/nv/nv3/subsystems/nv3_pgraph.c | 1 + src/video/nv/nv3/subsystems/nv3_pramdac.c | 3 +-- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index b1dc30ea0..5f58ce6f9 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -35,19 +35,19 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_BLIT_POSITION_IN: nv3->pgraph.blit.point_in.x = (param & 0xFFFF); nv3->pgraph.blit.point_in.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB POINT_IN %04x,%04x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); + nv_log("Method Execution: S2SB POINT_IN %d,%d\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); break; case NV3_BLIT_POSITION_OUT: nv3->pgraph.blit.point_out.x = (param & 0xFFFF); nv3->pgraph.blit.point_out.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB POINT_OUT %04x,%04x\n", nv3->pgraph.blit.point_out.x, nv3->pgraph.blit.point_out.y); + nv_log("Method Execution: S2SB POINT_OUT %d,%d\n", nv3->pgraph.blit.point_out.x, nv3->pgraph.blit.point_out.y); break; case NV3_BLIT_SIZE: /* This is the last one*/ nv3->pgraph.blit.size.w = (param & 0xFFFF); nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB Size %04x,%04x grobj_0=0x%08x\n", nv3->pgraph.blit.size.w, nv3->pgraph.blit.size.h, grobj.grobj_0); + nv_log("Method Execution: S2SB Size %d,%d grobj_0=0x%08x\n", nv3->pgraph.blit.size.w, nv3->pgraph.blit.size.h, grobj.grobj_0); /* Some of these seem to have sizes of 0, so skip */ if (nv3->pgraph.blit.size.h == 0 diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 87cf01812..5a1d08733 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -32,6 +32,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { /* We need this for a lot of methods, so may as well store it here. */ uint32_t src_buffer_id = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + switch (method_id) { diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 788cb4ca2..ed8858ee3 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -142,8 +142,8 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; - nv3_position_16_t old_position; - nv3_position_16_t new_position; + nv3_position_16_t old_position = {0}; + nv3_position_16_t new_position = {0}; /* If src_buffer != dst_buffer, the positions and src/dst buffer seem to be swapped. Some kind of hardware errata (?), otherwise, I have no explanation for this behaviour. */ diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 43befe49c..20cb97076 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -85,6 +85,7 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_STATUS, "PGRAPH Status", NULL, NULL }, { NV3_PGRAPH_TRAPPED_ADDRESS, "PGRAPH Trapped Address", NULL, NULL }, { NV3_PGRAPH_TRAPPED_DATA, "PGRAPH Trapped Data", NULL, NULL }, + { NV3_PGRAPH_INSTANCE, "PGRAPH Object Instance", NULL, NULL}, { NV3_PGRAPH_TRAPPED_INSTANCE, "PGRAPH Trapped Object Instance", NULL, NULL }, { NV3_PGRAPH_DMA_INTR_0, "PGRAPH DMA Interrupt Status (unimplemented)", NULL, NULL }, { NV3_PGRAPH_DMA_INTR_EN_0, "PGRAPH DMA Interrupt Enable (unimplemented)", NULL, NULL }, diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index f9f8b670c..b24d3d201 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -418,14 +418,13 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) nv3->pramdac.user_read_mode_address = value; break; case NV3_USER_DAC_WRITE_MODE_ADDRESS: - /* This seems to get reset to 0 after 256 writes, but, the palette is 768 bytes in size. Clearly there's some mechanism here, but I'm not sure what it is. So let's just reset if we reach 768. */ if (nv3->pramdac.user_write_mode_address >= NV3_USER_DAC_PALETTE_SIZE) nv3->pramdac.user_write_mode_address = value; - + break; case NV3_USER_DAC_PALETTE_DATA: /* I doubt NV actually read this in their drivers, but it's worth doing anyway */ From 0a579c0775ef94d966f3aba4d96905cf310ec3c6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 17 Apr 2025 21:40:41 +0100 Subject: [PATCH 173/274] Split RIVA 128 aand RIVA 128 ZX --- src/include/86box/nv/vid_nv3.h | 3 +- src/include/86box/video.h | 2 + src/video/nv/nv3/nv3_core.c | 151 ++++++++++++++---- src/video/nv/nv3/nv3_core_config.c | 182 +++++++++++----------- src/video/nv/nv3/subsystems/nv3_pextdev.c | 8 +- src/video/vid_table.c | 2 + 6 files changed, 223 insertions(+), 125 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 5c21e1918..e7bab44ac 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -26,7 +26,8 @@ #include <86box/nv/render/vid_nv3_render.h> // The GPU base structure -extern const device_config_t nv3_config[]; +extern const device_config_t nv3_config[]; // Config for RIVA 128 (revision A/B) +extern const device_config_t nv3t_config[]; // Config for RIVA 128 ZX (revision C) #define NV3_MMIO_SIZE 0x1000000 // Max MMIO size diff --git a/src/include/86box/video.h b/src/include/86box/video.h index cd48134c2..1b6821557 100644 --- a/src/include/86box/video.h +++ b/src/include/86box/video.h @@ -599,6 +599,8 @@ extern const device_t velocity_100_agp_device; extern const device_t velocity_200_agp_device; extern const device_t nv3_device_pci; extern const device_t nv3_device_agp; +extern const device_t nv3t_device_pci; +extern const device_t nv3t_device_agp; /* Wyse 700 */ extern const device_t wy700_device; diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index e8456814f..deef4f093 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -1089,10 +1089,22 @@ void nv3_update_mappings(void) // void* nv3_init(const device_t *info) { + // set the vram amount and gpu revision + + /* We don't bother looking these up if they are nonzero. On Riva 128 ZX, they are already set by the init function (always 8 MB VRAM + Revision C0) */ + if (!nv3->nvbase.vram_amount) + nv3->nvbase.vram_amount = device_get_config_int("vram_size"); + + if (!nv3->nvbase.gpu_revision) + nv3->nvbase.gpu_revision = device_get_config_int("chip_revision"); + + /* Set log device name based on card model */ + const char* log_device_name = (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) ? "NV3T" : "NV3"; + if (device_get_config_int("nv_debug_fulllog")) - nv3->nvbase.log = log_open("NV3"); + nv3->nvbase.log = log_open(log_device_name); else - nv3->nvbase.log = log_open_cyclic("NV3"); + nv3->nvbase.log = log_open_cyclic(log_device_name); #ifdef ENABLE_NV_LOG // Allows nv_log to be used for multiple nvidia devices @@ -1103,16 +1115,26 @@ void* nv3_init(const device_t *info) // this will only be logged if ENABLE_NV_LOG_ULTRA is defined nv_log_verbose_only("ULTRA LOGGING enabled"); - // Figure out which vbios the user selected + // This depends on the bus we are using and if the gpu is rev a/b or rev c const char* vbios_id = device_get_config_bios("vbios"); const char* vbios_file = ""; - // depends on the bus we are using - if (nv3->nvbase.bus_generation == nv_bus_pci) - vbios_file = device_get_bios_file(&nv3_device_pci, vbios_id, 0); - else - vbios_file = device_get_bios_file(&nv3_device_agp, vbios_id, 0); + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + { + if (nv3->nvbase.bus_generation == nv_bus_pci) + vbios_file = device_get_bios_file(&nv3t_device_pci, vbios_id, 0); + else + vbios_file = device_get_bios_file(&nv3t_device_agp, vbios_id, 0); + } + else + { + if (nv3->nvbase.bus_generation == nv_bus_pci) + vbios_file = device_get_bios_file(&nv3_device_pci, vbios_id, 0); + else + vbios_file = device_get_bios_file(&nv3_device_agp, vbios_id, 0); + } + int32_t err = rom_init(&nv3->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); @@ -1125,39 +1147,52 @@ void* nv3_init(const device_t *info) else nv_log("Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); - // set the vram amount and gpu revision - nv3->nvbase.vram_amount = device_get_config_int("vram_size"); - nv3->nvbase.gpu_revision = device_get_config_int("chip_revision"); - // set up the bus and start setting up SVGA core if (nv3->nvbase.bus_generation == nv_bus_pci) { - nv_log("using PCI bus\n"); + nv_log("Using PCI bus\n"); pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); - + /* Initialise the right revision of the card */ if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + { + svga_init(&nv3t_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, + nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_pci); - else + } + else + { + svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, + nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_pci); + } } - else if (nv3->nvbase.bus_generation == nv_bus_agp_1x) + else if (nv3->nvbase.bus_generation == nv_bus_agp_1x + || nv3->nvbase.bus_generation == nv_bus_agp_2x) { - nv_log("using AGP 1X bus\n"); + nv_log("Using AGP 1X/2X bus\n"); pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); - + /* Initialise the right revision of the card */ if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + { + svga_init(&nv3t_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, + nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_agp); - else + } + else + { + svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, + nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_agp); + } } // set vram @@ -1191,7 +1226,7 @@ void* nv3_init(const device_t *info) return nv3; } -// This function simply allocates ram and sets the bus to pci before initialising. +// RIVA 128 PCI initialisation function: This function simply allocates the device struct, and sets the bus to PCI before initialising. void* nv3_init_pci(const device_t* info) { nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); @@ -1200,7 +1235,7 @@ void* nv3_init_pci(const device_t* info) return nv3; } -// This function simply allocates ram and sets the bus to agp before initialising. +// RIVA 128 AGP initialisation function: This function simply allocates the device struct, and sets the bus to AGP before initialising. void* nv3_init_agp(const device_t* info) { nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); @@ -1209,6 +1244,32 @@ void* nv3_init_agp(const device_t* info) return nv3; } +// RIVA 128 ZX PCI initialisation function: This function simply allocates the device struct, and sets the bus to PCI before initialising. +// It also sets the GPU revision to C0 because NV3T config doesn't let you configure the rev (there were multiple steppings, but it's basically irrelevant), +// and sets RAM to 8 MB (the only supported config on ZX cards) +void* nv3t_init_pci(const device_t* info) +{ + nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); + nv3->nvbase.bus_generation = nv_bus_pci; + nv3->nvbase.gpu_revision = NV3_PCI_CFG_REVISION_C00; + nv3->nvbase.vram_amount = NV3_VRAM_SIZE_8MB; + nv3_init(info); + return nv3; +} + +// RIVA 128 ZX AGP initialisation function: This function simply allocates the device struct, and sets the bus to AGP before initialising. +// It also sets the GPU revision to C0 because NV3T config doesn't let you configure the rev (there were multiple steppings, but it's basically irrelevant) +// and sets RAM to 8 MB (the only supported config on ZX cards) +void* nv3t_init_agp(const device_t* info) +{ + nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); + nv3->nvbase.bus_generation = nv_bus_agp_2x; // Riva 128 ZX is AGP2X + nv3->nvbase.gpu_revision = NV3_PCI_CFG_REVISION_C00; + nv3->nvbase.vram_amount = NV3_VRAM_SIZE_8MB; + nv3_init(info); + return nv3; +} + void nv3_close(void* priv) { // Shut down logging @@ -1252,8 +1313,8 @@ int32_t nv3_available(void) // 2MB or 4MB VRAM const device_t nv3_device_pci = { - .name = "NVidia RIVA 128 (NV3) PCI", - .internal_name = "nv3", + .name = "nVIDIA RIVA 128 (NV3) PCI", + .internal_name = "nv3_pci", .flags = DEVICE_PCI, .local = 0, .init = nv3_init_pci, @@ -1269,7 +1330,7 @@ const device_t nv3_device_pci = // 2MB or 4MB VRAM const device_t nv3_device_agp = { - .name = "NVidia RIVA 128 (NV3) AGP", + .name = "nVIDIA RIVA 128 (NV3) AGP", .internal_name = "nv3_agp", .flags = DEVICE_AGP, .local = 0, @@ -1279,4 +1340,38 @@ const device_t nv3_device_agp = .force_redraw = nv3_force_redraw, .available = nv3_available, .config = nv3_config, +}; + +// NV3T (RIVA 128 ZX) +// PCI +// 8MB VRAM +const device_t nv3t_device_pci = +{ + .name = "nVIDIA RIVA 128 ZX (NV3T) PCI", + .internal_name = "nv3t_pci", + .flags = DEVICE_PCI, + .local = 0, + .init = nv3t_init_pci, + .close = nv3_close, + .speed_changed = nv3_speed_changed, + .force_redraw = nv3_force_redraw, + .available = nv3_available, + .config = nv3t_config, +}; + +// NV3T (RIVA 128) +// AGP +// 2MB or 4MB VRAM +const device_t nv3t_device_agp = +{ + .name = "nVIDIA RIVA 128 ZX (NV3T) AGP", + .internal_name = "nv3t_agp", + .flags = DEVICE_AGP, + .local = 0, + .init = nv3t_init_agp, + .close = nv3_close, + .speed_changed = nv3_speed_changed, + .force_redraw = nv3_force_redraw, + .available = nv3_available, + .config = nv3t_config, }; \ No newline at end of file diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index a229ca3c7..ec7d46e30 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -32,107 +32,42 @@ const device_config_t nv3_config[] = // VBIOS type configuration { .name = "vbios", - #ifndef RELEASE_BUILD - .description = "VBIOS", - #else .description = "Model", - #endif .type = CONFIG_BIOS, .default_string = "NV3_VBIOS_ERAZOR_V15403", .default_int = 0, .bios = { { - #ifndef RELEASE_BUILD - .name = "[NV3 - 1997-09-30] ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00)", .files_no = 1, - #else - .name = "[RIVA 128] ELSA Victory Erazor v1.47.01", .files_no = 1, - #endif + .name = "ELSA VICTORY Erazor - Version 1.47.00", .files_no = 1, .internal_name = "NV3_VBIOS_ERAZOR_V14700", .files = {NV3_VBIOS_ERAZOR_V14700, ""} }, { - #ifndef RELEASE_BUILD - .name = "[NV3 - 1998-02-06] ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, - #else - .name = "[RIVA 128] ELSA Victory Erazor v1.54.03", .files_no = 1, - #endif + .name = "ELSA VICTORY Erazor - Version 1.54.03", .files_no = 1, .internal_name = "NV3_VBIOS_ERAZOR_V15403", .files = {NV3_VBIOS_ERAZOR_V15403, ""} }, { - #ifndef RELEASE_BUILD - .name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1, - #else - .name = "[RIVA 128] ELSA Victory Erazor v1.55.00", .files_no = 1, - #endif + .name = "ELSA VICTORY Erazor - Version 1.55.00", .files_no = 1, .internal_name = "NV3_VBIOS_ERAZOR_V15500", .files = {NV3_VBIOS_ERAZOR_V15500, ""} }, { - #ifndef RELEASE_BUILD - .name = "[NV3 - 1998-01-14] Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO", .files_no = 1, - #else - .name = "[RIVA 128] Diamond Viper V330", .files_no = 1, - #endif + .name = "Diamond Viper V330 - Version 1.62-CO", .files_no = 1, .internal_name = "NV3_VBIOS_DIAMOND_V330_V162", .files = {NV3_VBIOS_DIAMOND_V330_V162, ""}, }, { - #ifndef RELEASE_BUILD - .name = "[NV3 - 1997-09-06] ASUS AGP/3DP-V3000 BIOS 1.51B", .files_no = 1, - #else - .name = "[RIVA 128] ASUS AGP/3DP-V3000", .files_no = 1, - #endif + .name = "ASUS AGP/3DP-V3000 - Version 1.51B", .files_no = 1, .internal_name = "NV3_VBIOS_ASUS_V3000_V151", .files = {NV3_VBIOS_ASUS_V3000_V151, ""}, }, { - #ifndef RELEASE_BUILD - .name = "[NV3 - 1997-12-17] STB Velocity 128 (RIVA 128) Ver.1.82", .files_no = 1, - #else - .name = "[RIVA 128] STB Velocity 128", .files_no = 1, - #endif + .name = "STB Velocity 128 - Version 1.82", .files_no = 1, .internal_name = "NV3_VBIOS_STB_V128_V182", .files = {NV3_VBIOS_STB_V128_V182, ""}, }, - { - #ifndef RELEASE_BUILD - .name = "[NV3T - 1998-09-15] Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1, - #else - .name = "[RIVA 128 ZX] Diamond Multimedia Viper V330 8MB", .files_no = 1, - #endif - .internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B", - .files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""}, - }, - { - #ifndef RELEASE_BUILD - .name = "[NV3T - 1998-08-04] ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1, - #else - .name = "[RIVA 128 ZX] ASUS AGP-V3000 ZXTV", .files_no = 1, - #endif - .internal_name = "NV3T_VBIOS_ASUS_V170", - .files = {NV3T_VBIOS_ASUS_V170, ""}, - }, - { - #ifndef RELEASE_BUILD - .name = "[NV3T - 1998-07-30] RIVA 128 ZX BIOS - V1.71B-N", .files_no = 1, - #else - .name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.71", .files_no = 1, - #endif - .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171", - .files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""}, - }, - - { - #ifndef RELEASE_BUILD - .name = "[NV3T+SGRAM - 1998-08-15] RIVA 128 ZX BIOS - V1.72B", .files_no = 1, - #else - .name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.72", .files_no = 1, - #endif - .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172", - .files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""}, - }, } }, // Memory configuration @@ -143,22 +78,17 @@ const device_config_t nv3_config[] = .default_int = NV3_VRAM_SIZE_4MB, .selection = { -#ifndef RELEASE_BUILD // I thought this was never released, but it seems that at least one was released: // The card was called the "NEC G7AGK" { .description = "2 MB", .value = NV3_VRAM_SIZE_2MB, }, -#endif + { .description = "4 MB", .value = NV3_VRAM_SIZE_4MB, }, - { - .description = "8 MB", - .value = NV3_VRAM_SIZE_8MB, - }, } }, @@ -169,30 +99,94 @@ const device_config_t nv3_config[] = .default_int = NV3_PCI_CFG_REVISION_B00, .selection = { -#ifndef RELEASE_BUILD { - .description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997) with integrated PAUDIO sound card", -#else - .description = "RIVA 128 Prototype (Revision A)", -#endif + .description = "RIVA 128 Prototype (Revision A; January 1997)", .value = NV3_PCI_CFG_REVISION_A00, }, -#ifndef RELEASE_BUILD { - .description = "RIVA 128 / Stepping B0 (October 1997)", -#else .description = "RIVA 128 (Revision B)", -#endif .value = NV3_PCI_CFG_REVISION_B00, }, -#ifndef RELEASE_BUILD - { - .description = "NV3T - RIVA 128 ZX / Stepping C0 (March 1998)", -#else - .description = "RIVA 128 ZX (Revision C)", -#endif - .value = NV3_PCI_CFG_REVISION_C00, - }, + } + }, + // Multithreading configuration + { + + .name = "pgraph_threads", +#ifndef RELEASE_BUILD + .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", +#else + .description = "Render threads", +#endif + .type = CONFIG_SELECTION, + .default_int = 1, // todo: change later + .selection = + { + { + .description = "1 thread (Only use if issues appear with more threads)", + .value = 1, + }, + { + .description = "2 threads", + .value = 2, + }, + { + .description = "4 threads", + .value = 4, + }, + { + .description = "8 threads", + .value = 8, + }, + }, + }, +#ifndef RELEASE_BUILD + { + .name = "nv_debug_fulllog", + .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", + .type = CONFIG_BINARY, + .default_int = 0, + }, +#endif + { + .type = CONFIG_END + } +}; + +const device_config_t nv3t_config[] = +{ + // VBIOS type configuration + { + .name = "vbios", + .description = "Model", + .type = CONFIG_BIOS, + .default_string = "NV3T_VBIOS_DIAMOND_V330_V182B", + .default_int = 0, + .bios = + { + { + + .name = "Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1, + .internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B", + .files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""}, + }, + { + .name = "ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1, + .internal_name = "NV3T_VBIOS_ASUS_V170", + .files = {NV3T_VBIOS_ASUS_V170, ""}, + }, + { + .name = "NVidia Reference BIOS - V1.71B-N", .files_no = 1, + + .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171", + .files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""}, + }, + + { + .name = "NVidia Reference BIOS - V1.72B", .files_no = 1, + .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172", + .files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""}, + }, } }, // Multithreading configuration diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c index 9aa17698f..c89d540c3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c @@ -134,8 +134,12 @@ void nv3_pextdev_write(uint32_t address, uint32_t value) // special consideration for straps if (address == NV3_PSTRAPS) { - warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps); - return; + /* For some reason, all RIVA 128 ZX VBIOSes try to write to the straps. So only indicate this as a problem and return on Rev A/B */ + if (nv3->nvbase.gpu_revision != NV3_PCI_CFG_REVISION_C00) + { + warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps); + return; + } } // if the register actually exists diff --git a/src/video/vid_table.c b/src/video/vid_table.c index 997c79304..202c2dd22 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -253,6 +253,8 @@ video_cards[] = { { .device = &voodoo_3_3500_si_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &nv3_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &nv3_device_pci, .flags = VIDEO_FLAG_TYPE_NONE }, + { .device = &nv3t_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, + { .device = &nv3t_device_pci, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = NULL, .flags = VIDEO_FLAG_TYPE_NONE } // clang-format on }; From 52c36d5644fe41cea0ee247c4be2ec8029025d71 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 18 Apr 2025 19:05:28 +0100 Subject: [PATCH 174/274] Implement a bizarre register that nvidia did not even internally document. WTF? --- src/include/86box/nv/render/vid_nv3_render.h | 2 +- src/include/86box/nv/vid_nv3.h | 20 ++-- src/video/nv/nv3/nv3_core.c | 4 +- src/video/nv/nv3/render/nv3_render_blit.c | 104 +++++++------------ src/video/nv/nv3/render/nv3_render_core.c | 67 ++++++------ 5 files changed, 84 insertions(+), 113 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 369230347..4b4f966ea 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,7 +18,7 @@ #pragma once /* Core */ -void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check); +void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer); void nv3_render_current_bpp_dfb_8(uint32_t address); void nv3_render_current_bpp_dfb_16(uint32_t address); void nv3_render_current_bpp_dfb_32(uint32_t address); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index e7bab44ac..fcfd2de72 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -79,9 +79,9 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_VBIOS_DEFAULT NV3_VBIOS_ERAZOR_V15403 // Temporary, will be loaded from settings -#define NV3_VRAM_SIZE_2MB 0x200000 // 2MB -#define NV3_VRAM_SIZE_4MB 0x400000 // 4MB -#define NV3_VRAM_SIZE_8MB 0x800000 // NV3T only +#define NV3_VRAM_SIZE_2MB 0x200000 // 2MB +#define NV3_VRAM_SIZE_4MB 0x400000 // 4MB +#define NV3_VRAM_SIZE_8MB 0x800000 // NV3T only // There is also 1mb supported by the card but it was never used // PCI config @@ -676,10 +676,7 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PRMCIO_START 0x601000 -#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO 0x6013B4 // Current CRTC Register Index - Monochrome -#define NV3_PRMCIO_CRTC_REGISTER_CUR_MONO 0x6013B5 // Currently Selected CRTC Register - Monochrome -#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR 0x6013D4 // Current CRTC Register Index - Colour -#define NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR 0x6013D5 + #define NV3_PRMCIO_END 0x601FFF #define NV3_PDAC_START 0x680000 // OPTIONAL external DAC @@ -787,6 +784,9 @@ extern const device_config_t nv3t_config[]; // Confi // CRTC/CIO (0x3b0-0x3df) +#define NV3_CRTC_REGISTER_INDEX_MONO 0x3B4 +#define NV3_CRTC_REGISTER_MONO 0x3B5 // Currently Selected CRTC Register - Monochrome + #define NV3_CRTC_DATA_OUT 0x3C0 #define NV3_CRTC_MISCOUT 0x3C2 @@ -796,6 +796,8 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_CRTC_REGISTER_INDEX 0x3D4 #define NV3_CRTC_REGISTER_CURRENT 0x3D5 +#define NV3_CRTC_REGISTER_WTF 0x3D8 + // These are standard (0-18h) #define NV3_CRTC_REGISTER_HTOTAL 0x00 #define NV3_CRTC_REGISTER_HDISPEND 0x01 @@ -1076,8 +1078,8 @@ typedef struct nv3_pramdac_s uint32_t hserr_width; // horizontal sync error width uint8_t user_pixel_mask; // pixel mask for DAC lookup - uint32_t user_read_mode_address; // user read mode address - uint32_t user_write_mode_address; // user write mode address + uint32_t user_read_mode_address; // user read mode address + uint32_t user_write_mode_address; // user write mode address uint8_t palette[NV3_USER_DAC_PALETTE_SIZE]; // Palette Info/CLUT - 256 entriesxr,g,b = 768 bytes } nv3_pramdac_t; diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index deef4f093..2875f3cbc 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -196,7 +196,6 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - nv3_svga_write(real_address, val & 0xFF, nv3); nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); @@ -632,6 +631,9 @@ uint8_t nv3_svga_read(uint16_t addr, void* priv) case NV3_CRTC_REGISTER_INDEX: ret = nv3->nvbase.svga.crtcreg; break; + case NV3_CRTC_REGISTER_WTF: + ret = 0x08; // Required to not freeze in certain situations on v3.xx drivers + break; case NV3_CRTC_REGISTER_CURRENT: // Support the extended NVIDIA CRTC register range switch (nv3->nvbase.svga.crtcreg) diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index ed8858ee3..8b7d9cbf8 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -131,10 +131,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.h) * (sizeof(uint32_t) * nv3->pgraph.blit.size.w)); /* First calculate our source and destination buffer */ - uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - - bool wtf_nvidia = false; - + uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; uint32_t dst_buffer = 0; // 5 = just use the source buffer if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; @@ -142,22 +139,10 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; - nv3_position_16_t old_position = {0}; - nv3_position_16_t new_position = {0}; + bool cross_buffer_blit = (nv3->pgraph.boffset[src_buffer] != nv3->pgraph.boffset[dst_buffer]); - /* If src_buffer != dst_buffer, the positions and src/dst buffer seem to be swapped. - Some kind of hardware errata (?), otherwise, I have no explanation for this behaviour. */ - if (nv3->pgraph.boffset[src_buffer] == nv3->pgraph.boffset[dst_buffer]) - { - old_position = nv3->pgraph.blit.point_in; - new_position = nv3->pgraph.blit.point_out; - } - else - { - old_position = nv3->pgraph.blit.point_out; - new_position = nv3->pgraph.blit.point_in; - wtf_nvidia = true; - } + nv3_position_16_t old_position = nv3->pgraph.blit.point_in; + nv3_position_16_t new_position = nv3->pgraph.blit.point_out; /* Coordinates for copying an entire line at a time */ uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.w; @@ -175,13 +160,12 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) size_x <<= 1; else if (nv3->nvbase.svga.bpp == 32) size_x <<= 2; - for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) { buf_position = (nv3->pgraph.blit.size.w * y); /* shouldn't matter in non-wtf mode */ - vram_position = nv3_render_get_vram_address_for_buffer(old_position, grobj, dst_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(old_position, grobj, src_buffer); memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); old_position.y++; @@ -192,16 +176,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) { buf_position = (nv3->pgraph.blit.size.w * y); - - /* Trying to avoid making the above function more complex. It seems, src is used most of th etime...But this is bad... */ - if (wtf_nvidia) - { - /* Use the parameters of our dst buffer with the position of our source buffer, seriously, who was thinking of this */ - vram_position = nv3_render_get_vram_address_for_buffer(new_position, grobj, src_buffer); - //vram_position = vram_position - nv3->pgraph.boffset[dst_buffer] + nv3->pgraph.boffset[src_buffer]; - } - else - vram_position = nv3_render_get_vram_address(new_position, grobj); + vram_position = nv3_render_get_vram_address_for_buffer(new_position, grobj, dst_buffer); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); new_position.y++; @@ -216,50 +191,43 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) nv3_size_16_t blit_size = {0}; /* Change the smallest area of the screen that moved */ - if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) - blit_size.w = (nv3->pgraph.blit.point_out.x - nv3->pgraph.blit.point_in.x) + nv3->pgraph.blit.size.w; - else if (nv3->pgraph.blit.point_out.x < nv3->pgraph.blit.point_in.x) - blit_size.w = (nv3->pgraph.blit.point_in.x - nv3->pgraph.blit.point_out.x) + nv3->pgraph.blit.size.w; + + if (cross_buffer_blit) + { + blit_position = nv3->pgraph.blit.point_out; + blit_size = nv3->pgraph.blit.size; + } else - blit_size.w = nv3->pgraph.blit.size.w; + { + if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) + blit_size.w = (nv3->pgraph.blit.point_out.x - nv3->pgraph.blit.point_in.x) + nv3->pgraph.blit.size.w; + else if (nv3->pgraph.blit.point_out.x < nv3->pgraph.blit.point_in.x) + blit_size.w = (nv3->pgraph.blit.point_in.x - nv3->pgraph.blit.point_out.x) + nv3->pgraph.blit.size.w; + else + blit_size.w = nv3->pgraph.blit.size.w; - if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) - blit_size.h = (nv3->pgraph.blit.point_out.y - nv3->pgraph.blit.point_in.y) + nv3->pgraph.blit.size.h; - else if (nv3->pgraph.blit.point_out.y < nv3->pgraph.blit.point_in.y) - blit_size.h = (nv3->pgraph.blit.point_in.y - nv3->pgraph.blit.point_out.y) + nv3->pgraph.blit.size.h; - else - blit_size.h = nv3->pgraph.blit.size.h; + if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) + blit_size.h = (nv3->pgraph.blit.point_out.y - nv3->pgraph.blit.point_in.y) + nv3->pgraph.blit.size.h; + else if (nv3->pgraph.blit.point_out.y < nv3->pgraph.blit.point_in.y) + blit_size.h = (nv3->pgraph.blit.point_in.y - nv3->pgraph.blit.point_out.y) + nv3->pgraph.blit.size.h; + else + blit_size.h = nv3->pgraph.blit.size.h; - if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) - blit_position.x = nv3->pgraph.blit.point_in.x; - else if (nv3->pgraph.blit.point_out.x <= nv3->pgraph.blit.point_in.x) // equals case, just use out - blit_position.x = nv3->pgraph.blit.point_out.x; + if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) + blit_position.x = nv3->pgraph.blit.point_in.x; + else if (nv3->pgraph.blit.point_out.x <= nv3->pgraph.blit.point_in.x) // equals case, just use out + blit_position.x = nv3->pgraph.blit.point_out.x; - if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) - blit_position.y = nv3->pgraph.blit.point_in.y; - else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out - blit_position.y = nv3->pgraph.blit.point_out.y; + if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) + blit_position.y = nv3->pgraph.blit.point_in.y; + else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out + blit_position.y = nv3->pgraph.blit.point_out.y; - - /* Figure out the Display Buffer Address from the CRTCs */ - uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) - + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) - + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; + } /* If the BUFFER_ADDRESS of the last buffer is not the DBA, we don't *actually* want to draw this, so let's not Apply stupid hack */ + - if (wtf_nvidia) - { - if (nv3->pgraph.boffset[src_buffer] != dba) - return; - } - else - { - if (nv3->pgraph.boffset[dst_buffer] != dba) - return; - } - - - nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj, false); + nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj, false, true); } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 6eb1f50c1..916717984 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -31,10 +31,10 @@ #include <86box/utils/video_stdlib.h> /* Functions only used in this translation unit */ -void nv3_render_8bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); -void nv3_render_15bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); -void nv3_render_16bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); -void nv3_render_32bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj); +void nv3_render_8bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_15bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_16bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_32bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); /* Expand a colour. NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! @@ -235,19 +235,6 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro uint32_t vram_y = position.y; uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - /* - uint32_t destination_buffer = 5; // 5 = just use the source buffer - - // src is hardcoded to 1, dst to 0. Hmm... - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) destination_buffer = 0; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) destination_buffer = 1; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) destination_buffer = 2; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) destination_buffer = 3; - - if (destination_buffer != current_buffer - && destination_buffer != 5) - current_buffer = destination_buffer; -*/ uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // we have to multiply the x position by the number of bytes per pixel @@ -504,7 +491,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob /* Go write the pixel */ nv3_size_16_t size = {0}; size.w = size.h = 1; - nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, true); + nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, true, false); } /* Ensure the correct monitor size */ @@ -605,7 +592,7 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) /* Blit to the monitor from GPU, current bpp */ -void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check) +void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer) { /* Ensure that we are in the correct mode. Modified SVGA core code */ nv3_render_ensure_screen_size(); @@ -641,16 +628,16 @@ void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t s fatal("NV3 - 4bpp not implemented (not even sure if it's SVGA only)"); break; case 8: - nv3_render_8bpp(pos, size, grobj); + nv3_render_8bpp(pos, size, grobj, use_destination_buffer); break; case 15: - nv3_render_15bpp(pos, size, grobj); + nv3_render_15bpp(pos, size, grobj, use_destination_buffer); break; case 16: - nv3_render_16bpp(pos, size, grobj); + nv3_render_16bpp(pos, size, grobj, use_destination_buffer); break; case 32: - nv3_render_32bpp(pos, size, grobj); + nv3_render_32bpp(pos, size, grobj, use_destination_buffer); break; } @@ -660,7 +647,7 @@ void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t s Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, indexed 8 bits per pixel format */ -void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -675,7 +662,10 @@ void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grob for (uint32_t y = 0; y < size.h; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; + if (use_destination_buffer) + vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + else + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; for (uint32_t x = 0; x < size.w; x++) { @@ -698,7 +688,7 @@ void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grob Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 15 bits per pixel format */ -void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -713,7 +703,10 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t y = 0; y < size.h; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; + if (use_destination_buffer) + vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + else + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; for (uint32_t x = 0; x < size.w; x++) { @@ -736,7 +729,7 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 16 bits per pixel format */ -void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -750,8 +743,11 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t y = 0; y < size.h; y++) { - /* re-get the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; + /* re-set the vram address because we are basically "jumping" halfway across a line here */ + if (use_destination_buffer) + vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + else + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; for (uint32_t x = 0; x < size.w; x++) { @@ -774,7 +770,7 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 32 bits per pixel format */ -void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj) +void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -788,9 +784,12 @@ void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro for (uint32_t y = 0; y < size.h; y++) { - /* re-get the vram address because we are basically "jumping" halfway across a line here */ - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - + /* re-set the vram address because we are basically "jumping" halfway across a line here */ + if (use_destination_buffer) + vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + else + vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; + for (uint32_t x = 0; x < size.w; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; From 1e5bdfbd160789f7eaaff568a4c233f97661091b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 21 Apr 2025 13:50:06 +0100 Subject: [PATCH 175/274] Fix OOB write in PGRAPH_CONTEXT_CACHE --- CMakePresets.json | 3 ++- src/video/nv/nv3/subsystems/nv3_pgraph.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/CMakePresets.json b/CMakePresets.json index 30feab8ab..b2ed64e97 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -36,7 +36,8 @@ "name": "debug", "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug", - "NV_LOG": "ON" + "NV_LOG": "ON", + "NV_LOG_ULTRA": "ON" }, "inherits": "base" }, diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index 20cb97076..dbca46216 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -478,7 +478,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE)) { // Addresses should be aligned to 4 bytes. - uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); + uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)) >> 2; nv_log_verbose_only("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value); nv3->pgraph.context_cache[entry] = value; From 2a511b8dc7a53a5deca1da872f5e79c7e5e96f42 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 22 Apr 2025 00:16:03 +0100 Subject: [PATCH 176/274] various fixes --- src/include/86box/nv/vid_nv3.h | 8 +++- src/video/nv/nv3/subsystems/nv3_pfifo.c | 57 +++++++++++++++---------- 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index fcfd2de72..00eeb0df1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -299,6 +299,9 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty #define NV3_PFIFO_CACHE1_STATUS_FULL 8 #define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218 +#define NV3_PFIFO_CACHE1_DMA_STATUS_STATE 0 +#define NV3_PFIFO_CACHE1_DMA_STATUS_STATE_IDLE 0x00 +#define NV3_PFIFO_CACHE1_DMA_STATUS_STATE_RUNNING 0x01 #define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220 #define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 #define NV3_PFIFO_CACHE1_DMA_CONFIG_2 0x3228 @@ -308,8 +311,11 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_AGP 0x03 // The type of bus we are sending over // Why does a gpu need its own translation lookaside buffer and pagetable format. Are they crazy +// Seems to be the same format as the notifier engine #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 -#define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA +#define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // pagetable entry for dma +#define NV3_PFIFO_CACHE1_DMA_TLB_PTE_IS_PRESENT 1 +#define NV3_PFIFO_CACHE1_DMA_TLB_FRAME_ADDRESS 12 // 31:12 #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA #define NV3_PFIFO_CACHE1_PULL0 0x3240 //todo: merge stuff diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 69b834df9..c5f13ae1b 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -61,14 +61,14 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put", NULL, NULL }, { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put", NULL, NULL }, //Cache1 exclusive stuff - { NV3_PFIFO_CACHE1_DMA_CONFIG_0, "PFIFO - Cache1 DMA Config0"}, - { NV3_PFIFO_CACHE1_DMA_CONFIG_1, "PFIFO - Cache1 DMA Config1"}, - { NV3_PFIFO_CACHE1_DMA_CONFIG_2, "PFIFO - Cache1 DMA Config2"}, - { NV3_PFIFO_CACHE1_DMA_CONFIG_3, "PFIFO - Cache1 DMA Config3"}, - { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status - PROBABLY TRIGGERING DMA"}, - { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA Translation Lookaside Buffer - Pagetable Base"}, - { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA Status"}, - { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_0, "PFIFO - Cache1 DMA Access (bit 0: is running, bit 4: is busy)"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_1, "PFIFO - Cache1 DMA Length"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_2, "PFIFO - Cache1 DMA Address"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_3, "PFIFO - Cache1 DMA Target Node"}, + { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA TLB - Pagetable Base"}, + { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA TLB - Pagetable Entry (31:12 - Frame Address; bit 0 - Is Present)"}, + { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA TLB - Tag"}, //Runout { NV3_PFIFO_RUNOUT_GET, "PFIFO Runout Get Address [8:3 if 512b, otherwise 12:3]"}, { NV3_PFIFO_RUNOUT_PUT, "PFIFO Runout Put Address [8:3 if 512b, otherwise 12:3]"}, @@ -354,31 +354,42 @@ void nv3_pfifo_trigger_dma_if_required(void) bool cache1_dma = false; /* Check that DMA is enabled */ - if (nv3->pfifo.cache1_settings.dma_state + if ((nv3->pfifo.cache1_settings.dma_state & NV3_PFIFO_CACHE1_DMA_STATUS_STATE_RUNNING) && nv3->pfifo.cache1_settings.dma_enabled) { uint32_t bytes_to_send = nv3->pfifo.cache1_settings.dma_length; uint32_t where_to_send = nv3->pfifo.cache1_settings.dma_address; - uint32_t target_node = nv3->pfifo.cache1_settings.dma_target_node; //2=pci, 3=agp. What does this even do + uint32_t target_node = nv3->pfifo.cache1_settings.dma_target_node; //2=pci, 3=agp. /* Pagetable information */ - uint32_t tlb_pt_base = nv3->pfifo.cache1_settings.dma_tlb_pt_base; - uint32_t tlb_pt_entry = nv3->pfifo.cache1_settings.dma_tlb_pte; + uint32_t tlb_pt_base = nv3->pfifo.cache1_settings.dma_tlb_pt_base; + uint32_t tlb_pt_entry = nv3->pfifo.cache1_settings.dma_tlb_pte; // notify_obj_page uint32_t tlb_pt_tag = nv3->pfifo.cache1_settings.dma_tlb_tag; // 0xFFFFFFFF usually? + + /* + going to treat the format the same as notifiers + */ + if (!(tlb_pt_entry & NV3_PFIFO_CACHE1_DMA_TLB_PTE_IS_PRESENT)) + { + warning("NV3: Tried to DMA to a non-existent page! Big Problem!"); + return; + } - /* PUSH - System to GPU (?) */ - if (nv3->pfifo.cache1_settings.push0) - { - /* PULL - GPU to System */ - nv_log("Initiating System to NV DMA - Probably we are trying to notify\n"); - } - else if (nv3->pfifo.cache1_settings.pull0) - { - /* PULL - GPU to System */ - nv_log("Initiating NV to System DMA - Probably we are trying to notify\n"); - } + uint32_t final_page_base = tlb_pt_entry & 0xFFFFF000; /* pull out 31:12 */ + + /* + page size is 0x1000 + */ + uint32_t final_address = final_page_base + (tlb_pt_entry << 10); //x86 page size is 0x1000 + + nv_log_verbose_only("DMA Engine: DMA to %08x length=%08x", final_address, bytes_to_send); + + dma_bm_write() } + + //we're done + nv3->pfifo.cache1_settings.dma_state &= ~NV3_PFIFO_CACHE1_DMA_STATUS_STATE_RUNNING; } void nv3_pfifo_write(uint32_t address, uint32_t val) From 00910aa6217cf3ef47499c7cff5bf63cb7deb7c1 Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Tue, 22 Apr 2025 08:44:10 -0500 Subject: [PATCH 177/274] Fix build --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index c5f13ae1b..32b6230ea 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -384,7 +384,7 @@ void nv3_pfifo_trigger_dma_if_required(void) nv_log_verbose_only("DMA Engine: DMA to %08x length=%08x", final_address, bytes_to_send); - dma_bm_write() + //dma_bm_write() } From 26ee11e8686d68a29fb8b50c52076e70cb1371f8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 23 Apr 2025 01:28:54 +0100 Subject: [PATCH 178/274] Refactor: Merge nv3_position_16 and nv3_size_16 into nv3_coord_16, same for bigy and combined: remove dead code --- .../86box/nv/classes/vid_nv3_classes.h | 114 ++++++++---------- src/include/86box/nv/render/vid_nv3_render.h | 16 +-- src/include/86box/nv/vid_nv3.h | 60 ++++----- .../nv/nv3/classes/nv3_class_007_rectangle.c | 6 +- .../classes/nv3_class_00c_win95_gdi_text.c | 48 ++++---- src/video/nv/nv3/classes/nv3_class_010_blit.c | 11 +- .../nv/nv3/classes/nv3_class_011_image.c | 12 +- src/video/nv/nv3/nv3_core.c | 6 +- src/video/nv/nv3/render/nv3_render_blit.c | 46 ++++--- src/video/nv/nv3/render/nv3_render_core.c | 76 ++++++------ .../nv/nv3/render/nv3_render_primitives.c | 26 ++-- src/video/nv/nv3/subsystems/nv3_pfifo.c | 7 +- 12 files changed, 203 insertions(+), 225 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 3b4f3b4a3..163b6464e 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -271,36 +271,29 @@ typedef struct nv3_color_argb_s uint8_t b; } nv3_color_argb_t; -/* Generic 16-bit position*/ -typedef struct nv3_position_16_s +/* Generic 16-bit coordinate*/ +typedef struct nv3_coord_16_s { uint16_t x; uint16_t y; -} nv3_position_16_t; +} nv3_coord_16_t; /* A big position format with 30:16 = y, 15:11 = nothing, 10:0 = x */ -typedef struct nv3_position_16_bigy_s +typedef struct nv3_coord_16_bigy_s { // WHOSE IDEA WAS THIS? uint16_t x : 11; uint8_t reserved : 5; uint16_t y : 15; bool reserved2 : 1; -} nv3_position_16_bigy_t; - -/* Generic 16-bit size */ -typedef struct nv3_size_16_s -{ - uint16_t w; - uint16_t h; -} nv3_size_16_t; +} nv3_coord_16_bigy_t; /* Generic 32-bit colour + 16-bit position */ -typedef struct nv3_color_and_position_16_s +typedef struct nv3_color_and_coord_16_s { nv3_color_expanded_t color; - nv3_position_16_t points; -} nv3_color_and_position_16_t; + nv3_coord_16_t points; +} nv3_color_and_coord_16_t; /* Generic 16-bit clip region */ typedef struct nv3_clip_16_s @@ -410,8 +403,8 @@ typedef struct nv3_object_class_005 uint32_t set_notify; // Set notifier /* 16-bit precision */ - nv3_position_16_t position; - nv3_size_16_t size; + nv3_coord_16_t position; + nv3_coord_16_t size; } nv3_clipping_rectangle_t; @@ -442,8 +435,8 @@ typedef struct nv3_object_class_007 nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint32_t set_notify; // Set notifier uint32_t color; // The colour of the object. - nv3_position_16_t position[16]; // The positions of up to 16 rectangles. - nv3_size_16_t size[16]; // The sizes of up to 16 rectangles + nv3_coord_16_t position[16]; // The positions of up to 16 rectangles. + nv3_coord_16_t size[16]; // The sizes of up to 16 rectangles } nv3_rectangle_t; @@ -451,7 +444,7 @@ typedef struct nv3_object_class_007 typedef struct nv3_object_class_008_cpoint_s { nv3_color_expanded_t color; // argb-format 32-bit color - nv3_position_16_t position; // position + nv3_coord_16_t position; // position } nv3_object_class_008_cpoint_t; /* @@ -465,7 +458,7 @@ typedef struct nv3_object_class_008 nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint32_t set_notify; // Set notifier nv3_color_expanded_t color; // argb? - nv3_position_16_t point[16]; // Boring points + nv3_coord_16_t point[16]; // Boring points nv3_position_32_t point32[16]; // Allows you to have points with full 32-bit precision nv3_object_class_008_cpoint_t cpoint[16]; // Allows you to have c o l o r f u l points! } nv3_point_t; @@ -473,8 +466,8 @@ typedef struct nv3_object_class_008 /* Normal line... */ typedef struct nv3_object_class_009_line_s { - nv3_position_16_t start; // presumably unless it's in reverse order...TODO: check the order - nv3_position_16_t end; + nv3_coord_16_t start; // presumably unless it's in reverse order...TODO: check the order + nv3_coord_16_t end; } nv3_object_class_009_line_t; @@ -506,7 +499,7 @@ typedef struct nv3_object_class_009 nv3_object_class_009_line32_t line32[8]; nv3_object_class_009_line_t polyline[32]; nv3_object_class_009_line32_t polyline32[16]; - nv3_color_and_position_16_t cpolyline[16]; // List of line points and colours. + nv3_color_and_coord_16_t cpolyline[16]; // List of line points and colours. } nv3_line_t; /* @@ -528,7 +521,7 @@ typedef struct nv3_object_class_00A nv3_object_class_009_line32_t line32[8]; nv3_object_class_009_line_t polyline[32]; nv3_object_class_009_line32_t polyline32[16]; - nv3_color_and_position_16_t cpolyline[16]; // List of line points and colours. + nv3_color_and_coord_16_t cpolyline[16]; // List of line points and colours. } nv3_lin_t; @@ -545,7 +538,7 @@ typedef struct nv3_object_class_00B uint32_t set_notify; // Set notifier nv3_color_expanded_t color; // argb? // The points of the triangle. - nv3_position_16_t points[3]; + nv3_coord_16_t points[3]; // Another way of filling out the points of the triangle uint32_t x0; @@ -555,10 +548,10 @@ typedef struct nv3_object_class_00B uint32_t y2; uint32_t x2; - nv3_position_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? + nv3_coord_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? nv3_position_32_t mesh32[16]; - nv3_color_and_position_16_t ctriangle[3]; // Triangle with colour - nv3_color_and_position_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours + nv3_color_and_coord_16_t ctriangle[3]; // Triangle with colour + nv3_color_and_coord_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours } nv3_triangle_t; /* @@ -567,7 +560,6 @@ typedef struct nv3_object_class_00B Also 0x4C in context IDs. GDI text acceleration for Windows 95. - How the fuck does this even work? */ typedef struct nv3_object_class_00C { @@ -575,8 +567,8 @@ typedef struct nv3_object_class_00C nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint32_t set_notify; // Set notifier uint32_t color_a; // Color for Clip A - nv3_position_16_t rect_a_position[64]; - nv3_size_16_t rect_a_size[64]; + nv3_coord_16_t rect_a_position[64]; + nv3_coord_16_t rect_a_size[64]; /* Clipped rect */ nv3_clip_16_t clip_b; uint32_t color_b; // Color for Clip B @@ -584,23 +576,23 @@ typedef struct nv3_object_class_00C /* Unclipped transparent bitmap */ nv3_clip_16_t clip_c; uint32_t color1_c; - nv3_size_16_t size_c; - nv3_position_16_t point_c; + nv3_coord_16_t size_c; + nv3_coord_16_t point_c; uint32_t bitmap_c[128]; /* Clipped transparent bitmap */ nv3_clip_16_t clip_d; uint32_t color1_d; - nv3_size_16_t size_in_d; - nv3_size_16_t size_out_d; - nv3_position_16_t point_d; + nv3_coord_16_t size_in_d; + nv3_coord_16_t size_out_d; + nv3_coord_16_t point_d; uint32_t bitmap_d[128]; /* Clipped 1bpp bitmap */ nv3_clip_16_t clip_e; uint32_t color0_e; uint32_t color1_e; - nv3_size_16_t size_in_e; - nv3_size_16_t size_out_e; - nv3_position_16_t point_e; + nv3_coord_16_t size_in_e; + nv3_coord_16_t size_out_e; + nv3_coord_16_t point_e; uint32_t bitmap_e[128]; } nv3_win95_text_t; @@ -637,14 +629,14 @@ typedef struct nv3_object_class_00E { nv3_class_ctx_switch_method_t set_notify_ctx_dma; uint32_t set_notify; - nv3_position_16_t clip_0; - nv3_size_16_t clip_1; - nv3_position_16_t rectangle_out_0; - nv3_size_16_t rectangle_out_1; + nv3_coord_16_t clip_0; + nv3_coord_16_t clip_1; + nv3_coord_16_t rectangle_out_0; + nv3_coord_16_t rectangle_out_1; // Calculus in a graphics card uint32_t delta_du_dx; uint32_t delta_dv_dy; - nv3_size_16_t size; // can be size_y if YUV420 + nv3_coord_16_t size; // can be size_y if YUV420 uint32_t pitch; uint32_t offset; uint32_t point; @@ -663,16 +655,16 @@ typedef struct nv3_object_class_00E 0x?? (drivers) Also 0x50 in context IDs. - Represents a blit. + Represents a screen to screen blit. I'm still figuring it out. */ typedef struct nv3_object_class_010 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; uint32_t set_notify; - nv3_position_16_t point_in; - nv3_position_16_t point_out; - nv3_size_16_t size; + nv3_coord_16_t point_in; + nv3_coord_16_t point_out; + nv3_coord_16_t size; } nv3_blit_t; /* @@ -686,9 +678,9 @@ typedef struct nv3_object_class_011 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; uint32_t set_notify; - nv3_position_16_t point; - nv3_size_16_t size; - nv3_size_16_t size_in; + nv3_coord_16_t point; + nv3_coord_16_t size; + nv3_coord_16_t size_in; nv3_color_expanded_t color[32]; // The colour to use } nv3_image_t; @@ -706,9 +698,9 @@ typedef struct nv3_object_class_012 uint32_t set_notify; nv3_color_expanded_t color_0; nv3_color_expanded_t color_1; - nv3_position_16_t point; // Top left(?) of the bitmap - nv3_size_16_t size; - nv3_size_16_t size_in; + nv3_coord_16_t point; // Top left(?) of the bitmap + nv3_coord_16_t size; + nv3_coord_16_t size_in; uint32_t monochrome_bitmap[32]; } nv3_bitmap_t; @@ -726,8 +718,8 @@ typedef struct nv3_object_class_014 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; uint32_t set_notify; - nv3_position_16_t point; - nv3_size_16_t size; + nv3_coord_16_t point; + nv3_coord_16_t size; uint32_t image_pitch; // bytes per row uint32_t image_start; } nv3_image_to_memory_t; @@ -744,11 +736,11 @@ typedef struct nv3_object_class_015 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; uint32_t set_notify; - nv3_size_16_t size_in; + nv3_coord_16_t size_in; uint32_t delta_dx_du; uint32_t delta_dy_dv; - nv3_position_16_t clip_0; - nv3_size_16_t clip_1; + nv3_coord_16_t clip_0; + nv3_coord_16_t clip_1; uint32_t point12d4; /* todo: fraction struct */ // no reserve needed } nv3_stretched_image_from_cpu_t; @@ -1154,7 +1146,7 @@ typedef struct nv3_object_class_018 uint32_t set_notify; nv3_d3d5_control_out_t control_out; nv3_d3d5_alpha_control_t alpha_control; - nv3_position_16_t point; + nv3_coord_16_t point; nv3_zeta_buffer_t zeta[8]; } nv3_point_with_zeta_buffer_t; diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 4b4f966ea..795bae979 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,20 +18,20 @@ #pragma once /* Core */ -void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer); +void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer); void nv3_render_current_bpp_dfb_8(uint32_t address); void nv3_render_current_bpp_dfb_16(uint32_t address); void nv3_render_current_bpp_dfb_32(uint32_t address); /* Pixel */ -void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj); -uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj); -uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj); +void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj); +uint8_t nv3_render_read_pixel_8(nv3_coord_16_t position, nv3_grobj_t grobj); +uint16_t nv3_render_read_pixel_16(nv3_coord_16_t position, nv3_grobj_t grobj); +uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj); /* Address */ -uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_get_vram_address_for_buffer(nv3_position_16_t position, nv3_grobj_t grobj, uint32_t buffer); +uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj); +uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, nv3_grobj_t grobj, uint32_t buffer); /* Colour Conversion */ uint32_t nv3_render_get_palette_index(uint8_t index); // Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) @@ -43,7 +43,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co void nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1); /* Primitives */ -void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj); // Render an A (unclipped) GDI rect +void nv3_render_rect(nv3_coord_16_t position, nv3_coord_16_t size, uint32_t color, nv3_grobj_t grobj); // Render an A (unclipped) GDI rect void nv3_render_rect_clipped(nv3_clip_16_t clip, uint32_t color, nv3_grobj_t grobj); // Render a B (clipped) GDI rect. /* Chroma */ diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 00eeb0df1..c27af6a1d 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -834,7 +834,7 @@ extern const device_config_t nv3t_config[]; // Confi // These are nvidia, licensed from weitek (25-63) -#define NV3_CRTC_REGISTER_RPC0 0x19 // What does this mean? +#define NV3_CRTC_REGISTER_RPC0 0x19 // 7:5 - [10:8] of CRTC. 4:0 - [20:16] of 21-bit display buffer address #define NV3_CRTC_REGISTER_RPC1 0x1A // What does this mean? #define NV3_CRTC_REGISTER_READ_BANK 0x1D #define NV3_CRTC_REGISTER_WRITE_BANK 0x1E @@ -1199,10 +1199,10 @@ typedef struct nv3_pgraph_s uint32_t abs_uclip_ymin; uint32_t abs_uclip_ymax; // Canvas stuff - nv3_position_16_bigy_t src_canvas_min; - nv3_position_16_bigy_t src_canvas_max; - nv3_position_16_bigy_t dst_canvas_min; - nv3_position_16_bigy_t dst_canvas_max; + nv3_coord_16_bigy_t src_canvas_min; + nv3_coord_16_bigy_t src_canvas_max; + nv3_coord_16_bigy_t dst_canvas_min; + nv3_coord_16_bigy_t dst_canvas_max; // Pattern stuff nv3_color_expanded_t pattern_color_0_rgb; // ignore alpha uint32_t pattern_color_0_alpha; // only 7:0 relevant @@ -1224,13 +1224,13 @@ typedef struct nv3_pgraph_s uint32_t notifier; bool notify_pending; // Determines if a notification is pending. /* Are these even used */ - nv3_position_16_bigy_t clip0_min; - nv3_position_16_bigy_t clip0_max; - nv3_position_16_bigy_t clip1_min; - nv3_position_16_bigy_t clip1_max; + nv3_coord_16_bigy_t clip0_min; + nv3_coord_16_bigy_t clip0_max; + nv3_coord_16_bigy_t clip1_min; + nv3_coord_16_bigy_t clip1_max; /* idk */ - nv3_position_16_t clip_start; // Start of the clipping region - nv3_position_16_t clip_size; // Size of the clipping region. + nv3_coord_16_t clip_start; // Start of the clipping region + nv3_coord_16_t clip_size; // Size of the clipping region. bool fifo_access; // Determines if PGRAPH can access PFIFO. nv3_pgraph_status_t status; // Current status of the 3D engine. uint32_t trapped_address; @@ -1253,12 +1253,12 @@ typedef struct nv3_pgraph_s struct nv3_object_class_00C win95_gdi_text; /* These are here so we can hold the current state of the image draw */ uint32_t win95_gdi_text_bit_count; - nv3_position_16_t win95_gdi_text_current_position; + nv3_coord_16_t win95_gdi_text_current_position; struct nv3_object_class_00D m2mf; struct nv3_object_class_00E scaled_image_from_memory; struct nv3_object_class_010 blit; struct nv3_object_class_011 image; - nv3_position_16_t image_current_position; /* This is here so we can hold the current state of the image */ + nv3_coord_16_t image_current_position; /* This is here so we can hold the current state of the image */ struct nv3_object_class_012 bitmap; struct nv3_object_class_014 transfer2memory; struct nv3_object_class_015 stretched_image_from_cpu; @@ -1439,26 +1439,26 @@ typedef struct nv3_s nv_base_t nvbase; // Base Nvidia structure // Config - nv3_straps_t straps; - nv3_pci_config_t pci_config; + nv3_straps_t straps; // OEM Configuration + nv3_pci_config_t pci_config; // PCI Configuration // Subsystems - nv3_pmc_t pmc; // Master Control - nv3_pfb_t pfb; // Framebuffer/VRAM - nv3_pbus_t pbus; // Bus Control - nv3_pfifo_t pfifo; // FIFO for command submission + nv3_pmc_t pmc; // Master Control + nv3_pfb_t pfb; // Framebuffer/VRAM + nv3_pbus_t pbus; // Bus Control + nv3_pfifo_t pfifo; // FIFO for command submission - nv3_pramdac_t pramdac; // RAMDAC (CLUT etc) - nv3_pgraph_t pgraph; // 2D/3D Graphics - nv3_pextdev_t pextdev; // Chip configuration - nv3_ptimer_t ptimer; // programmable interval timer - nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects - nv3_ramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission - nv3_ramin_ramfc_t ramfc; // context for unused channels - nv3_ramin_ramau_t ramau; // auxillary weirdnes - nv3_ramin_t pramin; // Ram for INput of DMA objects. Very important! - nv3_pvideo_t pvideo; // Video overlay - nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface + nv3_pramdac_t pramdac; // RAMDAC (CLUT etc) + nv3_pgraph_t pgraph; // 2D/3D Graphics + nv3_pextdev_t pextdev; // Chip configuration + nv3_ptimer_t ptimer; // programmable interval timer + nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects + nv3_ramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission + nv3_ramin_ramfc_t ramfc; // context for unused channels + nv3_ramin_ramau_t ramau; // auxillary weirdnes + nv3_ramin_t pramin; // Ram for INput of DMA objects. Very important! + nv3_pvideo_t pvideo; // Video overlay + nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface //more here } nv3_t; diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c index 6dfdf281e..d1273a84a 100644 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c @@ -44,10 +44,10 @@ void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // If the size is submitted, render it. if (method_id & 0x04) { - nv3->pgraph.rectangle.size[index].w = param & 0xFFFF; - nv3->pgraph.rectangle.size[index].h = (param >> 16) & 0xFFFF; + nv3->pgraph.rectangle.size[index].x = param & 0xFFFF; + nv3->pgraph.rectangle.size[index].y = (param >> 16) & 0xFFFF; - nv_log("Method Execution: Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].w, nv3->pgraph.rectangle.size[index].h, nv3->pgraph.rectangle.color); + nv_log("Method Execution: Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].x, nv3->pgraph.rectangle.size[index].y, nv3->pgraph.rectangle.color); nv3_render_rect(nv3->pgraph.rectangle.position[index], nv3->pgraph.rectangle.size[index], nv3->pgraph.rectangle.color, grobj); } diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c index c1085fe89..64d76c278 100644 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c @@ -60,11 +60,11 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: GDI-C Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color1_c); break; case NV3_W95TXT_C_CLIP_SIZE: - nv3->pgraph.win95_gdi_text.size_c.w = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_c.h = ((param >> 16) & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_c.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_c.y = ((param >> 16) & 0xFFFF); nv3->pgraph.win95_gdi_text_bit_count = 0; - nv_log("Method Execution: GDI-C Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_c.w, nv3->pgraph.win95_gdi_text.size_c.h); + nv_log("Method Execution: GDI-C Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_c.x, nv3->pgraph.win95_gdi_text.size_c.y); break; case NV3_W95TXT_C_CLIP_POSITION: nv3->pgraph.win95_gdi_text.point_c.x = (param & 0xFFFF); @@ -104,14 +104,14 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: GDI-D Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; case NV3_W95TXT_D_CLIP_SIZE_IN: - nv3->pgraph.win95_gdi_text.size_in_d.w = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_in_d.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-D Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_d.w, nv3->pgraph.win95_gdi_text.size_in_d.h); + nv3->pgraph.win95_gdi_text.size_in_d.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_in_d.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-D Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_d.x, nv3->pgraph.win95_gdi_text.size_in_d.y); break; case NV3_W95TXT_D_CLIP_SIZE_OUT: - nv3->pgraph.win95_gdi_text.size_out_d.w = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_out_d.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-D Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_d.w, nv3->pgraph.win95_gdi_text.size_out_d.h); + nv3->pgraph.win95_gdi_text.size_out_d.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_out_d.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-D Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_d.x, nv3->pgraph.win95_gdi_text.size_out_d.y); break; case NV3_W95TXT_D_CLIP_POSITION: nv3->pgraph.win95_gdi_text.point_d.x = (param & 0xFFFF); @@ -144,14 +144,14 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: GDI-E Color1 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); break; case NV3_W95TXT_E_CLIP_SIZE_IN: - nv3->pgraph.win95_gdi_text.size_in_e.w = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_in_e.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-E Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_e.w, nv3->pgraph.win95_gdi_text.size_in_e.h); + nv3->pgraph.win95_gdi_text.size_in_e.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_in_e.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-E Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_e.x, nv3->pgraph.win95_gdi_text.size_in_e.y); break; case NV3_W95TXT_E_CLIP_SIZE_OUT: - nv3->pgraph.win95_gdi_text.size_out_e.w = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_out_e.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-E Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_e.w, nv3->pgraph.win95_gdi_text.size_out_e.h); + nv3->pgraph.win95_gdi_text.size_out_e.x = (param & 0xFFFF); + nv3->pgraph.win95_gdi_text.size_out_e.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: GDI-E Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_e.x, nv3->pgraph.win95_gdi_text.size_out_e.y); break; case NV3_W95TXT_E_CLIP_POSITION: nv3->pgraph.win95_gdi_text.point_e.x = (param & 0xFFFF); @@ -173,11 +173,11 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ // If the size is submitted, render it. if (method_id & 0x04) { - nv3->pgraph.win95_gdi_text.rect_a_size[index].w = (param >> 16) & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_size[index].h = param & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].x = (param >> 16) & 0xFFFF; + nv3->pgraph.win95_gdi_text.rect_a_size[index].y = param & 0xFFFF; - nv_log("Method Execution: Rect GDI-A%d Size=%d,%d", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].w, - nv3->pgraph.win95_gdi_text.rect_a_size[index].h); + nv_log("Method Execution: Rect GDI-A%d Size=%d,%d", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].x, + nv3->pgraph.win95_gdi_text.rect_a_size[index].y); nv3_render_rect(nv3->pgraph.win95_gdi_text.rect_a_position[index], nv3->pgraph.win95_gdi_text.rect_a_size[index], nv3->pgraph.win95_gdi_text.color_a, grobj); @@ -231,7 +231,7 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* Mammoth logger! */ nv_log("Method Execution: Rect GDI-C%d Data=%08x Size%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", - index, param, nv3->pgraph.win95_gdi_text.size_c.w, nv3->pgraph.win95_gdi_text.size_c.h, + index, param, nv3->pgraph.win95_gdi_text.size_c.x, nv3->pgraph.win95_gdi_text.size_c.y, nv3->pgraph.win95_gdi_text.point_c.x, nv3->pgraph.win95_gdi_text.point_c.y, nv3->pgraph.win95_gdi_text.color1_c, nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.right, @@ -249,8 +249,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* Mammoth logger! */ nv_log("Method Execution: Rect GDI-D%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", - index, param, nv3->pgraph.win95_gdi_text.size_in_d.w, nv3->pgraph.win95_gdi_text.size_in_d.h, - nv3->pgraph.win95_gdi_text.size_out_d.w, nv3->pgraph.win95_gdi_text.size_out_d.h, + index, param, nv3->pgraph.win95_gdi_text.size_in_d.x, nv3->pgraph.win95_gdi_text.size_in_d.y, + nv3->pgraph.win95_gdi_text.size_out_d.x, nv3->pgraph.win95_gdi_text.size_out_d.y, nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y, nv3->pgraph.win95_gdi_text.color1_d, nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.right, @@ -268,8 +268,8 @@ void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ /* Mammoth logger! */ nv_log("Method Execution: Rect GDI-E%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", - index, param, nv3->pgraph.win95_gdi_text.size_in_e.w, nv3->pgraph.win95_gdi_text.size_in_e.h, - nv3->pgraph.win95_gdi_text.size_out_e.w, nv3->pgraph.win95_gdi_text.size_out_e.h, + index, param, nv3->pgraph.win95_gdi_text.size_in_e.x, nv3->pgraph.win95_gdi_text.size_in_e.y, + nv3->pgraph.win95_gdi_text.size_out_e.x, nv3->pgraph.win95_gdi_text.size_out_e.y, nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y, nv3->pgraph.win95_gdi_text.color1_e, nv3->pgraph.win95_gdi_text.clip_e.left, nv3->pgraph.win95_gdi_text.clip_e.right, nv3->pgraph.win95_gdi_text.clip_e.top, nv3->pgraph.win95_gdi_text.clip_e.bottom); diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c index 5f58ce6f9..ed1ac465b 100644 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c @@ -45,14 +45,9 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; case NV3_BLIT_SIZE: /* This is the last one*/ - nv3->pgraph.blit.size.w = (param & 0xFFFF); - nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB Size %d,%d grobj_0=0x%08x\n", nv3->pgraph.blit.size.w, nv3->pgraph.blit.size.h, grobj.grobj_0); - - /* Some of these seem to have sizes of 0, so skip */ - if (nv3->pgraph.blit.size.h == 0 - && nv3->pgraph.blit.size.w == 0) - return; + nv3->pgraph.blit.size.x = (param & 0xFFFF); + nv3->pgraph.blit.size.y = ((param >> 16) & 0xFFFF); + nv_log("Method Execution: S2SB Size %d,%d grobj_0=0x%08x\n", nv3->pgraph.blit.size.x, nv3->pgraph.blit.size.y, grobj.grobj_0); nv3_render_blit_screen2screen(grobj); diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c index bd5dfa6d3..1eda15df7 100644 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ b/src/video/nv/nv3/classes/nv3_class_011_image.c @@ -39,15 +39,15 @@ void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; /* Seems to allow scaling of the bitblt. */ case NV3_IMAGE_SIZE: - nv3->pgraph.image.size.w = (param & 0xFFFF); - nv3->pgraph.image.size.h = (param >> 16); - nv_log("Method Execution: Image Size (Clip)=%d,%d\n", nv3->pgraph.image.size.w, nv3->pgraph.image.size.h); + nv3->pgraph.image.size.x = (param & 0xFFFF); + nv3->pgraph.image.size.y = (param >> 16); + nv_log("Method Execution: Image Size (Clip)=%d,%d\n", nv3->pgraph.image.size.x, nv3->pgraph.image.size.y); break; case NV3_IMAGE_SIZE_IN: - nv3->pgraph.image.size_in.w = (param & 0xFFFF); - nv3->pgraph.image.size_in.h = (param >> 16); + nv3->pgraph.image.size_in.x = (param & 0xFFFF); + nv3->pgraph.image.size_in.y = (param >> 16); nv3->pgraph.image_current_position = nv3->pgraph.image.point; - nv_log("Method Execution: Image SizeIn=%d,%d\n", nv3->pgraph.image.size_in.w, nv3->pgraph.image.size_in.h); + nv_log("Method Execution: Image SizeIn=%d,%d\n", nv3->pgraph.image.size_in.x, nv3->pgraph.image.size_in.y); break; default: if (method_id >= NV3_IMAGE_COLOR_START && method_id <= NV3_IMAGE_COLOR_END) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 2875f3cbc..ad032abe9 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -271,7 +271,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) ret = (NV_PCI_DEVICE_NV3 >> 8); break; - // various capabilities + // various capabilities enabled by default // IO space enabled // Memory space enabled // Bus master enabled @@ -281,7 +281,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) // 66Mhz FSB capable case PCI_REG_COMMAND_L: - ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L] ; // we actually respond to the fucking + ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L]; break; case PCI_REG_COMMAND_H: @@ -536,7 +536,7 @@ void nv3_recalc_timings(svga_t* svga) case NV3_CRTC_REGISTER_PIXELMODE_16BPP: /* This is some sketchy shit that is an attempt at an educated guess at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, - this is what's causing it. Possibly fucking *ReactOS* of all things */ + this is what's causing it. Possibly fucking up *ReactOS* of all things */ if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01) svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; else diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 8b7d9cbf8..6d29965d4 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -34,10 +34,9 @@ void nv3_class_011_check_line_bounds(void) { uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x; - //uint32_t relative_y = nv3->pgraph.image_current_position.y - nv3->pgraph.image.point.y; - /* In theory, relative_y should never be exceeded...because it only submits enough pixels to render the image*/ - if (relative_x >= nv3->pgraph.image.size_in.w) + /* In the case of class 0x11 there is no requirement to check for relative_y because we have exceeded the size of the image */ + if (relative_x >= nv3->pgraph.image.size_in.x) { nv3->pgraph.image_current_position.y++; nv3->pgraph.image_current_position.x = nv3->pgraph.image.point.x; @@ -47,16 +46,13 @@ void nv3_class_011_check_line_bounds(void) /* Renders an image from cpu */ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) { - // shift left by 2 because it's 4 bits per size.. - uint32_t current_buffer = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - /* todo: a lot of stuff */ uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; /* Some extra data is sent as padding, we need to clip it off using size_out */ - uint16_t clip_x = nv3->pgraph.image.point.x + nv3->pgraph.image.size.w; + uint16_t clip_x = nv3->pgraph.image.point.x + nv3->pgraph.image.size.x; /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) @@ -126,9 +122,9 @@ uint32_t nv3_s2sb_line_buffer[NV3_MAX_HORIZONTAL_SIZE*NV3_MAX_VERTICAL_SIZE] = { void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { - if (nv3->pgraph.blit.size.w < NV3_MAX_HORIZONTAL_SIZE - && nv3->pgraph.blit.size.h < NV3_MAX_VERTICAL_SIZE) - memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.h) * (sizeof(uint32_t) * nv3->pgraph.blit.size.w)); + if (nv3->pgraph.blit.size.x < NV3_MAX_HORIZONTAL_SIZE + && nv3->pgraph.blit.size.y < NV3_MAX_VERTICAL_SIZE) + memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.y) * (sizeof(uint32_t) * nv3->pgraph.blit.size.x)); /* First calculate our source and destination buffer */ uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; @@ -141,11 +137,11 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) bool cross_buffer_blit = (nv3->pgraph.boffset[src_buffer] != nv3->pgraph.boffset[dst_buffer]); - nv3_position_16_t old_position = nv3->pgraph.blit.point_in; - nv3_position_16_t new_position = nv3->pgraph.blit.point_out; + nv3_coord_16_t old_position = nv3->pgraph.blit.point_in; + nv3_coord_16_t new_position = nv3->pgraph.blit.point_out; /* Coordinates for copying an entire line at a time */ - uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.w; + uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.x; /* Read the old pixel into the line buffer Assumption: All data is sent in an unpacked format. In the case of an NVIDIA GPU this means that all data is sent 32 bits at a time regardless of if @@ -161,9 +157,9 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) else if (nv3->nvbase.svga.bpp == 32) size_x <<= 2; - for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) + for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) { - buf_position = (nv3->pgraph.blit.size.w * y); + buf_position = (nv3->pgraph.blit.size.x * y); /* shouldn't matter in non-wtf mode */ vram_position = nv3_render_get_vram_address_for_buffer(old_position, grobj, src_buffer); @@ -173,9 +169,9 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) } /* simply write it all back to vram */ - for (int32_t y = 0; y < nv3->pgraph.blit.size.h; y++) + for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) { - buf_position = (nv3->pgraph.blit.size.w * y); + buf_position = (nv3->pgraph.blit.size.x * y); vram_position = nv3_render_get_vram_address_for_buffer(new_position, grobj, dst_buffer); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); @@ -187,8 +183,8 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) We also need to update all of the areas of the screen that moved. */ - nv3_position_16_t blit_position = {0}; - nv3_size_16_t blit_size = {0}; + nv3_coord_16_t blit_position = {0}; + nv3_coord_16_t blit_size = {0}; /* Change the smallest area of the screen that moved */ @@ -200,18 +196,18 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) else { if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) - blit_size.w = (nv3->pgraph.blit.point_out.x - nv3->pgraph.blit.point_in.x) + nv3->pgraph.blit.size.w; + blit_size.x = (nv3->pgraph.blit.point_out.x - nv3->pgraph.blit.point_in.x) + nv3->pgraph.blit.size.x; else if (nv3->pgraph.blit.point_out.x < nv3->pgraph.blit.point_in.x) - blit_size.w = (nv3->pgraph.blit.point_in.x - nv3->pgraph.blit.point_out.x) + nv3->pgraph.blit.size.w; + blit_size.x = (nv3->pgraph.blit.point_in.x - nv3->pgraph.blit.point_out.x) + nv3->pgraph.blit.size.x; else - blit_size.w = nv3->pgraph.blit.size.w; + blit_size.x = nv3->pgraph.blit.size.x; if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) - blit_size.h = (nv3->pgraph.blit.point_out.y - nv3->pgraph.blit.point_in.y) + nv3->pgraph.blit.size.h; + blit_size.y = (nv3->pgraph.blit.point_out.y - nv3->pgraph.blit.point_in.y) + nv3->pgraph.blit.size.y; else if (nv3->pgraph.blit.point_out.y < nv3->pgraph.blit.point_in.y) - blit_size.h = (nv3->pgraph.blit.point_in.y - nv3->pgraph.blit.point_out.y) + nv3->pgraph.blit.size.h; + blit_size.y = (nv3->pgraph.blit.point_in.y - nv3->pgraph.blit.point_out.y) + nv3->pgraph.blit.size.y; else - blit_size.h = nv3->pgraph.blit.size.h; + blit_size.y = nv3->pgraph.blit.size.y; if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) blit_position.x = nv3->pgraph.blit.point_in.x; diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 916717984..d03ee9481 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -31,10 +31,10 @@ #include <86box/utils/video_stdlib.h> /* Functions only used in this translation unit */ -void nv3_render_8bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); -void nv3_render_15bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); -void nv3_render_16bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); -void nv3_render_32bpp(nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_8bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_15bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_16bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_32bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); /* Expand a colour. NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! @@ -229,7 +229,7 @@ void nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_ } /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ -uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj) +uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj) { uint32_t vram_x = position.x; uint32_t vram_y = position.y; @@ -260,7 +260,7 @@ uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t gro /* Combine the current buffer with the pitch to get the address in the video ram for a specific position relative to a specific framebuffer */ -uint32_t nv3_render_get_vram_address_for_buffer(nv3_position_16_t position, nv3_grobj_t grobj, uint32_t buffer) +uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, nv3_grobj_t grobj, uint32_t buffer) { uint32_t vram_x = position.x; uint32_t vram_y = position.y; @@ -289,9 +289,9 @@ uint32_t nv3_render_get_vram_address_for_buffer(nv3_position_16_t position, nv3_ } /* Convert a dumb framebuffer address to a position. No buffer setup or anything, but just start at 0,0 for address 0. */ -nv3_position_16_t nv3_render_get_dfb_position(uint32_t vram_address) +nv3_coord_16_t nv3_render_get_dfb_position(uint32_t vram_address) { - nv3_position_16_t pos = {0}; + nv3_coord_16_t pos = {0}; uint32_t pitch = nv3->nvbase.svga.hdisp; @@ -321,7 +321,7 @@ nv3_position_16_t nv3_render_get_dfb_position(uint32_t vram_address) } /* Read an 8bpp pixel from the framebuffer. */ -uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj) +uint8_t nv3_render_read_pixel_8(nv3_coord_16_t position, nv3_grobj_t grobj) { // hope you call it with the right bit uint32_t vram_address = nv3_render_get_vram_address(position, grobj); @@ -330,7 +330,7 @@ uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj) } /* Read an 16bpp pixel from the framebuffer. */ -uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) +uint16_t nv3_render_read_pixel_16(nv3_coord_16_t position, nv3_grobj_t grobj) { // hope you call it with the right bit uint32_t vram_address = nv3_render_get_vram_address(position, grobj); @@ -342,7 +342,7 @@ uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj) } /* Read an 16bpp pixel from the framebuffer. */ -uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) +uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj) { // hope you call it with the right bit uint32_t vram_address = nv3_render_get_vram_address(position, grobj); @@ -354,16 +354,12 @@ uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj) } /* Plots a pixel. */ -void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj) +void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj) { // PFB_0 is always set to hardcoded "NO_TILING" value of 0x1114. // It seems, you are meant to - /* put this here for debugging + it may be needed later. */ - #ifdef DEBUG - uint8_t color_format_object = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_COLOR_FORMAT) & 0x07; - #endif bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too?z @@ -489,8 +485,8 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob } /* Go write the pixel */ - nv3_size_16_t size = {0}; - size.w = size.h = 1; + nv3_coord_16_t size = {0}; + size.x = size.y = 1; nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, true, false); } @@ -529,10 +525,10 @@ void nv3_render_ensure_screen_size(void) /* Blit to the monitor from DFB, 8bpp */ void nv3_render_current_bpp_dfb_8(uint32_t address) { - nv3_size_16_t size = {0}; - size.w = size.h = 1; + nv3_coord_16_t size = {0}; + size.x = size.y = 1; - nv3_position_16_t pos = nv3_render_get_dfb_position(address); + nv3_coord_16_t pos = nv3_render_get_dfb_position(address); uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); @@ -543,10 +539,10 @@ void nv3_render_current_bpp_dfb_8(uint32_t address) /* Blit to the monitor from DFB, 15/16bpp */ void nv3_render_current_bpp_dfb_16(uint32_t address) { - nv3_size_16_t size = {0}; - size.w = size.h = 1; + nv3_coord_16_t size = {0}; + size.x = size.y = 1; - nv3_position_16_t pos = nv3_render_get_dfb_position(address); + nv3_coord_16_t pos = nv3_render_get_dfb_position(address); uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); @@ -564,10 +560,10 @@ void nv3_render_current_bpp_dfb_16(uint32_t address) /* Blit to the monitor from DFB, 32bpp */ void nv3_render_current_bpp_dfb_32(uint32_t address) { - nv3_size_16_t size = {0}; - size.w = size.h = 1; + nv3_coord_16_t size = {0}; + size.x = size.y = 1; - nv3_position_16_t pos = nv3_render_get_dfb_position(address); + nv3_coord_16_t pos = nv3_render_get_dfb_position(address); uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); @@ -592,7 +588,7 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) /* Blit to the monitor from GPU, current bpp */ -void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer) +void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer) { /* Ensure that we are in the correct mode. Modified SVGA core code */ nv3_render_ensure_screen_size(); @@ -647,7 +643,7 @@ void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t s Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, indexed 8 bits per pixel format */ -void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_8bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -659,7 +655,7 @@ void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grob p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - for (uint32_t y = 0; y < size.h; y++) + for (uint32_t y = 0; y < size.y; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) @@ -667,7 +663,7 @@ void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grob else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - for (uint32_t x = 0; x < size.w; x++) + for (uint32_t x = 0; x < size.x; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; @@ -688,7 +684,7 @@ void nv3_render_8bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grob Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 15 bits per pixel format */ -void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_15bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -700,7 +696,7 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - for (uint32_t y = 0; y < size.h; y++) + for (uint32_t y = 0; y < size.y; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) @@ -708,7 +704,7 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - for (uint32_t x = 0; x < size.w; x++) + for (uint32_t x = 0; x < size.x; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; @@ -729,7 +725,7 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 16 bits per pixel format */ -void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_16bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -741,7 +737,7 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - for (uint32_t y = 0; y < size.h; y++) + for (uint32_t y = 0; y < size.y; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) @@ -749,7 +745,7 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - for (uint32_t x = 0; x < size.w; x++) + for (uint32_t x = 0; x < size.x; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; @@ -770,7 +766,7 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 32 bits per pixel format */ -void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_32bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { if (!nv3) return; @@ -782,7 +778,7 @@ void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - for (uint32_t y = 0; y < size.h; y++) + for (uint32_t y = 0; y < size.y; y++) { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) @@ -790,7 +786,7 @@ void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - for (uint32_t x = 0; x < size.w; x++) + for (uint32_t x = 0; x < size.x; x++) { p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c index c89fd2d6e..e2d088c3f 100644 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ b/src/video/nv/nv3/render/nv3_render_primitives.c @@ -29,15 +29,15 @@ #include <86box/nv/vid_nv3.h> #include <86box/utils/video_stdlib.h> -void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t color, nv3_grobj_t grobj) +void nv3_render_rect(nv3_coord_16_t position, nv3_coord_16_t size, uint32_t color, nv3_grobj_t grobj) { - nv3_position_16_t current_pos = {0}; + nv3_coord_16_t current_pos = {0}; - for (int32_t y = position.y; y < (position.y + size.h); y++) + for (int32_t y = position.y; y < (position.y + size.y); y++) { current_pos.y = y; - for (int32_t x = position.x; x < (position.x + size.w); x++) + for (int32_t x = position.x; x < (position.x + size.x); x++) { current_pos.x = x; @@ -49,7 +49,7 @@ void nv3_render_rect(nv3_position_16_t position, nv3_size_16_t size, uint32_t co /* Render GDI-B clipped rectangle */ void nv3_render_rect_clipped(nv3_clip_16_t clip, uint32_t color, nv3_grobj_t grobj) { - nv3_position_16_t current_pos = {0}; + nv3_coord_16_t current_pos = {0}; for (int32_t y = clip.top; y < clip.bottom; y++) { @@ -89,8 +89,8 @@ void nv3_render_gdi_transparent_bitmap_blit(bool bit, bool clip, uint32_t color, Also clip if we are outside of the SIZE_OUT range We only need to do this in one direction just to get rid of the crud sent by NV */ - uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_out_d.w); - uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_d.y + (nv3->pgraph.win95_gdi_text.size_out_d.h); + uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_out_d.x); + uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_d.y + (nv3->pgraph.win95_gdi_text.size_out_d.y); if (nv3->pgraph.win95_gdi_text_current_position.x >= clip_x || nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) @@ -106,7 +106,7 @@ void nv3_render_gdi_transparent_bitmap_blit(bool bit, bool clip, uint32_t color, Because we check the bits in reverse, we go forward (bits 7,6,5 were set for a 1x3 bitmap) */ - uint32_t end_x = (clip) ? nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.w : nv3->pgraph.win95_gdi_text.point_c.x + nv3->pgraph.win95_gdi_text.size_c.w; + uint32_t end_x = (clip) ? nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.x : nv3->pgraph.win95_gdi_text.point_c.x + nv3->pgraph.win95_gdi_text.size_c.x; nv3->pgraph.win95_gdi_text_current_position.x++; @@ -135,7 +135,7 @@ void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitma We store a global bit count for this purpose. */ - uint32_t bitmap_size = (clip) ? nv3->pgraph.win95_gdi_text.size_in_d.w * nv3->pgraph.win95_gdi_text.size_in_d.h : nv3->pgraph.win95_gdi_text.size_c.w * nv3->pgraph.win95_gdi_text.size_c.h; + uint32_t bitmap_size = (clip) ? nv3->pgraph.win95_gdi_text.size_in_d.x * nv3->pgraph.win95_gdi_text.size_in_d.y : nv3->pgraph.win95_gdi_text.size_c.x * nv3->pgraph.win95_gdi_text.size_c.y; uint32_t bits_remaining_in_bitmap = bitmap_size - nv3->pgraph.win95_gdi_text_bit_count; /* we have to interpret every bit in reverse bit order but in the right byte order */ @@ -231,8 +231,8 @@ void nv3_render_gdi_1bpp_bitmap_blit(bool bit, uint32_t color0, uint32_t color1, Also clip if we are outside of the SIZE_OUT range We only need to do this in one direction just to get rid of the crud sent by NV */ - uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_out_e.w); - uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + (nv3->pgraph.win95_gdi_text.size_out_e.h); + uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_out_e.x); + uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + (nv3->pgraph.win95_gdi_text.size_out_e.y); if (nv3->pgraph.win95_gdi_text_current_position.x >= clip_x || nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) @@ -253,7 +253,7 @@ void nv3_render_gdi_1bpp_bitmap_blit(bool bit, uint32_t color0, uint32_t color1, Because we check the bits in reverse, we go forward (bits 7,6,5 were set for a 1x3 bitmap) */ - uint32_t end_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_in_e.w; + uint32_t end_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_in_e.x; nv3->pgraph.win95_gdi_text_current_position.x++; @@ -278,7 +278,7 @@ void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitma We store a global bit count for this purpose. */ - uint32_t bitmap_size = nv3->pgraph.win95_gdi_text.size_in_e.w * nv3->pgraph.win95_gdi_text.size_in_e.h; + uint32_t bitmap_size = nv3->pgraph.win95_gdi_text.size_in_e.x * nv3->pgraph.win95_gdi_text.size_in_e.y; uint32_t bits_remaining_in_bitmap = bitmap_size - nv3->pgraph.win95_gdi_text_bit_count; /* we have to interpret every bit in reverse bit order but in the right byte order */ diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 32b6230ea..5a59ba51d 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -380,12 +380,11 @@ void nv3_pfifo_trigger_dma_if_required(void) /* page size is 0x1000 */ - uint32_t final_address = final_page_base + (tlb_pt_entry << 10); //x86 page size is 0x1000 + uint32_t final_address = final_page_base + (tlb_pt_entry << 10) + where_to_send; //x86 page size is 0x1000 (maybe rsh where_to_send by 2) nv_log_verbose_only("DMA Engine: DMA to %08x length=%08x", final_address, bytes_to_send); - //dma_bm_write() - + //-dma_bm_write() } //we're done @@ -576,7 +575,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.runout_put = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); break; - /* Cache1 is handled below */ + /* Cache1 Context is handled below */ case NV3_PFIFO_CACHE0_CTX: nv3->pfifo.cache0_settings.context[0] = val; break; From e791f25a6b1d2211d74b67f1ac968d104da1cd90 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 23 Apr 2025 23:55:57 +0100 Subject: [PATCH 179/274] Get rid of redundant code --- src/include/86box/nv/vid_nv3.h | 2 -- src/video/nv/nv3/subsystems/nv3_pramdac.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index c27af6a1d..25049dbce 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -44,8 +44,6 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_DMA_CHANNELS_TOTAL 0x7F // This is also used somewhere despite there only being 8*8 = 64 channels -#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1 // The amount by which we have to ration out the memory clock because it's not fast enough... - // Multiply by this value to get the real clock speed. #define NV3_LAST_VALID_GRAPHICS_OBJECT_ID 0x1F // The class ids are represented with 5 bits in PGRAPH, but 7 bits in PFIFO! diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index b24d3d201..88b910b6f 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -134,7 +134,7 @@ void nv3_pramdac_set_vram_clock(void) // Convert to microseconds frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); - double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box + double time = 1000000.0 / (double)frequency; // needs to be a double for 86box nv_log("Memory clock = %.2f MHz\n", frequency / 1000000.0f); @@ -182,7 +182,7 @@ void nv3_pramdac_set_pixel_clock(void) nv3->nvbase.svga.clock = cpuclock / frequency; - double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box + double time = 1000000.0 / (double)frequency; // needs to be a double for 86box nv_log("Pixel clock = %.2f MHz\n", frequency / 1000000.0f); From 99823f3fa4632adaebd79ceec29f09b232756d79 Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 24 Apr 2025 06:49:33 -0500 Subject: [PATCH 180/274] Fix build on macOS and NetBSD --- src/video/nv/nv3/nv3_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index ad032abe9..031827677 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -762,11 +762,13 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) nv3->nvbase.svga.hdisp += 0x100; break; case NV3_CRTC_REGISTER_I2C_GPIO: + { uint8_t scl = !!(val & 0x20); uint8_t sda = !!(val & 0x10); // Set an I2C GPIO register i2c_gpio_set(nv3->nvbase.i2c, scl, sda); break; + } } From ffa24e100271aee092dae4392263e316b30b3dc9 Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 24 Apr 2025 07:00:06 -0500 Subject: [PATCH 181/274] More NetBSD build fixes --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 5a59ba51d..2625adda4 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -558,7 +558,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.cache1_settings.get_address = val; break; case NV3_PFIFO_RUNOUT_GET: - + { uint32_t size_get = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (size_get == 0) //512b @@ -566,7 +566,9 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) else nv3->pfifo.runout_get = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); break; + } case NV3_PFIFO_RUNOUT_PUT: + { uint32_t size_put = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); if (size_put == 0) //512b @@ -575,6 +577,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) nv3->pfifo.runout_put = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); break; + } /* Cache1 Context is handled below */ case NV3_PFIFO_CACHE0_CTX: nv3->pfifo.cache0_settings.context[0] = val; From cd0e8b074117cec31a156081651cdeb6d5724331 Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 24 Apr 2025 07:15:27 -0500 Subject: [PATCH 182/274] More build fixes --- src/video/nv/nv3/classes/nv3_class_003_chroma_key.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c index 139099e78..f19a06932 100644 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c @@ -38,12 +38,14 @@ void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ break; case NV3_CHROMA_KEY: + { nv3_color_expanded_t expanded_color = nv3_render_expand_color(param, grobj); nv3->pgraph.chroma_key = nv3_render_to_chroma(expanded_color); nv_log("Method Execution: Chroma = 0x%08x", nv3->pgraph.chroma_key); - break; + break; + } default: warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); From 988c29064a9fa2a4e179a3838b7d1b48d14068c8 Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 24 Apr 2025 08:01:48 -0500 Subject: [PATCH 183/274] Fix --- src/video/nv/nv3/classes/nv3_class_006_pattern.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c index b66db499e..5aa5bf0fc 100644 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ b/src/video/nv/nv3/classes/nv3_class_006_pattern.c @@ -60,13 +60,17 @@ void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ case NV3_PATTERN_UNUSED_DRIVER_BUG: break; case NV3_PATTERN_COLOR0: + { nv3_color_expanded_t expanded_colour0 = nv3_render_expand_color(param, grobj); nv3_render_set_pattern_color(expanded_colour0, false); break; + } case NV3_PATTERN_COLOR1: + { nv3_color_expanded_t expanded_colour1 = nv3_render_expand_color(param, grobj); nv3_render_set_pattern_color(expanded_colour1, true); break; + } case NV3_PATTERN_BITMAP_HIGH: nv3->pgraph.pattern_bitmap = 0; //reset nv3->pgraph.pattern_bitmap |= ((uint64_t)param << 32); From 5c9a9404d5418d481a5abd4737db7366bfd0d3ca Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 24 Apr 2025 08:16:39 -0500 Subject: [PATCH 184/274] Fix --- src/video/nv/nv3/render/nv3_render_core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index d03ee9481..acbf9fa05 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -443,6 +443,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t break; case 15: case 16: + { uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 1; @@ -471,7 +472,9 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t nv3->nvbase.svga.changedvram[pixel_addr_vram >> 11] = changeframecount; break; + } case 32: + { uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 2; @@ -482,6 +485,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t nv3->nvbase.svga.changedvram[pixel_addr_vram >> 10] = changeframecount; break; + } } /* Go write the pixel */ From a4af738ede11afcbd02c2dd892b2dbff6d575c6c Mon Sep 17 00:00:00 2001 From: fuel-pcbox Date: Thu, 24 Apr 2025 08:20:19 -0500 Subject: [PATCH 185/274] More fixes --- src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index 5a1d08733..a35135672 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -38,6 +38,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ { /* Color format of the image */ case NV3_IMAGE_IN_MEMORY_COLOR_FORMAT: + { // convert to how the bpixel registers represent surface uint32_t real_format = 1; @@ -65,6 +66,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: Image in Memory BUF%d COLOR_FORMAT=0x%04x\n", src_buffer_id, param); break; + } /* DOn't log invalid */ case NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE: nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); From 2007e3d0e56cde208fa8cf3144a312d6e250d6d8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 27 Apr 2025 17:04:24 +0100 Subject: [PATCH 186/274] start working on visual gpu debugging window; rename nv3_position_32 to nv3_coord_32; first pass at hardware cursor --- doc/nvidia_notes/hardware cursor.txt | 21 +++ .../86box/nv/classes/vid_nv3_classes.h | 8 +- src/include/86box/nv/render/vid_nv3_render.h | 2 +- src/include/86box/nv/vid_nv3.h | 55 +++++--- src/qt/CMakeLists.txt | 6 +- src/qt/qt_gpudebug_vram.cpp | 1 + src/qt/qt_gpudebug_vram.hpp | 18 +++ src/qt/qt_gpudebug_vram.ui | 56 ++++++++ src/qt/qt_mainwindow.ui | 18 +++ src/video/nv/nv3/nv3_core.c | 127 ++++++++++++++++-- src/video/nv/nv3/render/nv3_render_blit.c | 4 +- src/video/nv/nv3/render/nv3_render_core.c | 10 +- src/video/nv/nv3/subsystems/nv3_pramdac.c | 15 ++- 13 files changed, 294 insertions(+), 47 deletions(-) create mode 100644 doc/nvidia_notes/hardware cursor.txt create mode 100644 src/qt/qt_gpudebug_vram.cpp create mode 100644 src/qt/qt_gpudebug_vram.hpp create mode 100644 src/qt/qt_gpudebug_vram.ui diff --git a/doc/nvidia_notes/hardware cursor.txt b/doc/nvidia_notes/hardware cursor.txt new file mode 100644 index 000000000..0845778f4 --- /dev/null +++ b/doc/nvidia_notes/hardware cursor.txt @@ -0,0 +1,21 @@ +NV3/NV3T/NV4 hardware cursor + +Unlock extended CRTC registers + +CIO_CRE_HCUR_ADDR0 + Bits [6:0] = Address + +CIO_CRE_HCUR_ADDR1 + Bits [7:3] = Bits [11:7] of address + Bit 1 = Cursor Doubling + Bit 0 = Enable + +PRAMDAC_CU_START_POS (MMIO 0x680300) + Bits [11:0] = X Pos + Bits [27:16] = Y Pos + +CursorAddress >> 16 written to addr0 +(((CursorAddress >> 11) & 0x1F) << 3) | 1 (for enable) written to addr1 + +Lock extended CRTC registers +Enable - write \ No newline at end of file diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 163b6464e..d5dc3ed43 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -306,11 +306,11 @@ typedef struct nv3_clip_16_s } nv3_clip_16_t; /* In case your positions weren't HIGH PRECISION enough */ -typedef struct nv3_position_32_s +typedef struct nv3_coord_32_s { uint32_t x; uint32_t y; -} nv3_position_32_t; +} nv3_coord_32_t; // COLOUR FORMATS @@ -459,7 +459,7 @@ typedef struct nv3_object_class_008 uint32_t set_notify; // Set notifier nv3_color_expanded_t color; // argb? nv3_coord_16_t point[16]; // Boring points - nv3_position_32_t point32[16]; // Allows you to have points with full 32-bit precision + nv3_coord_32_t point32[16]; // Allows you to have points with full 32-bit precision nv3_object_class_008_cpoint_t cpoint[16]; // Allows you to have c o l o r f u l points! } nv3_point_t; @@ -549,7 +549,7 @@ typedef struct nv3_object_class_00B uint32_t x2; nv3_coord_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? - nv3_position_32_t mesh32[16]; + nv3_coord_32_t mesh32[16]; nv3_color_and_coord_16_t ctriangle[3]; // Triangle with colour nv3_color_and_coord_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours } nv3_triangle_t; diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 795bae979..f4850b8f7 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -31,7 +31,7 @@ uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj); /* Address */ uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, nv3_grobj_t grobj, uint32_t buffer); +uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, uint32_t buffer); /* Colour Conversion */ uint32_t nv3_render_get_palette_index(uint8_t index); // Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 25049dbce..ebb7c0755 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -697,6 +697,11 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PVIDEO_END 0x6802FF #define NV3_PRAMDAC_START 0x680300 +#define NV3_PRAMDAC_CURSOR_START 0x680300 + +#define NV3_PRAMDAC_CURSOR_SIZE_X 32 +#define NV3_PRAMDAC_CURSOR_SIZE_Y 32 + #define NV3_PRAMDAC_CLOCK_MEMORY 0x680504 #define NV3_PRAMDAC_CLOCK_MEMORY_VDIV 7:0 #define NV3_PRAMDAC_CLOCK_MEMORY_NDIV 15:8 @@ -759,30 +764,30 @@ extern const device_config_t nv3t_config[]; // Confi // control structures for dma'd in graphics objects from pfifo // these all have configurable sizes, define them here -#define NV3_RAMIN_START 0x1C00000 +#define NV3_RAMIN_START 0x1C00000 -#define NV3_RAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects -#define NV3_RAMIN_RAMHT_END 0x1C00FFF -#define NV3_RAMIN_RAMHT_SIZE_0 0xFFF -#define NV3_RAMIN_RAMHT_SIZE_1 0x1FFF -#define NV3_RAMIN_RAMHT_SIZE_2 0x3FFF -#define NV3_RAMIN_RAMHT_SIZE_3 0x7FFF +#define NV3_RAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects +#define NV3_RAMIN_RAMHT_END 0x1C00FFF +#define NV3_RAMIN_RAMHT_SIZE_0 0xFFF +#define NV3_RAMIN_RAMHT_SIZE_1 0x1FFF +#define NV3_RAMIN_RAMHT_SIZE_2 0x3FFF +#define NV3_RAMIN_RAMHT_SIZE_3 0x7FFF /* OBSOLETE AREA for AUDIO probably. DO NOT USE! */ -#define NV3_RAMIN_RAMAU_START 0x1C01000 -#define NV3_RAMIN_RAMAU_END 0x1C01BFF -#define NV3_RAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels -#define NV3_RAMIN_RAMFC_END 0x1C01DFF -#define NV3_RAMIN_RAMFC_SIZE_0 0x1FF -#define NV3_RAMIN_RAMFC_SIZE_1 0xFFF -#define NV3_RAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions -#define NV3_RAMIN_RAMRO_SIZE_0 0x1FF -#define NV3_RAMIN_RAMRO_SIZE_1 0x1FFF -#define NV3_RAMIN_RAMRO_END 0x1C01FFF -#define NV3_RAMIN_RAMRM_START 0x1C02000 -#define NV3_RAMIN_RAMRM_END 0x1C02FFF +#define NV3_RAMIN_RAMAU_START 0x1C01000 +#define NV3_RAMIN_RAMAU_END 0x1C01BFF +#define NV3_RAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels +#define NV3_RAMIN_RAMFC_END 0x1C01DFF +#define NV3_RAMIN_RAMFC_SIZE_0 0x1FF +#define NV3_RAMIN_RAMFC_SIZE_1 0xFFF +#define NV3_RAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions +#define NV3_RAMIN_RAMRO_SIZE_0 0x1FF +#define NV3_RAMIN_RAMRO_SIZE_1 0x1FFF +#define NV3_RAMIN_RAMRO_END 0x1C01FFF +#define NV3_RAMIN_RAMRM_START 0x1C02000 +#define NV3_RAMIN_RAMRM_END 0x1C02FFF -#define NV3_RAMIN_END 0x1FFFFFF +#define NV3_RAMIN_END 0x1FFFFFF // not done @@ -814,6 +819,7 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_CRTC_REGISTER_PRESETROWSCAN 0x08 #define NV3_CRTC_REGISTER_MAXSCAN 0x09 #define NV3_CRTC_REGISTER_CURSOR_START 0x0A +#define NV3_CRTC_REGISTER_CURSOR_START_DISABLED 5 #define NV3_CRTC_REGISTER_CURSOR_END 0x0B #define NV3_CRTC_REGISTER_STARTADDR_HIGH 0x0C #define NV3_CRTC_REGISTER_STARTADDR_LOW 0x0D @@ -846,6 +852,9 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_CRTC_REGISTER_HEB 0x2D // HRS most significant bit +#define NV3_CRTC_REGISTER_CURSOR_ADDR0 0x30 // Cursor high +#define NV3_CRTC_REGISTER_CURSOR_ADDR1 0x31 // Cursor low (1:0 = enable) + #define NV3_CRTC_REGISTER_PIXELMODE_VGA 0x00 // vga textmode #define NV3_CRTC_REGISTER_PIXELMODE_8BPP 0x01 #define NV3_CRTC_REGISTER_PIXELMODE_16BPP 0x02 @@ -1084,7 +1093,10 @@ typedef struct nv3_pramdac_s uint8_t user_pixel_mask; // pixel mask for DAC lookup uint32_t user_read_mode_address; // user read mode address uint32_t user_write_mode_address; // user write mode address - uint8_t palette[NV3_USER_DAC_PALETTE_SIZE]; // Palette Info/CLUT - 256 entriesxr,g,b = 768 bytes + uint8_t palette[NV3_USER_DAC_PALETTE_SIZE]; // Palette Info/CLUT - 256 entries, 1 byte for r,g,b = 768 bytes + + uint32_t cursor_address; // cursor address start + nv3_coord_16_t cursor_start; } nv3_pramdac_t; /* Holds DMA channel context information */ @@ -1473,6 +1485,7 @@ extern nv3_t* nv3; void* nv3_init(const device_t *info); void nv3_close(void* priv); void nv3_speed_changed(void *priv); +void nv3_draw_cursor(svga_t* svga, int32_t drawline); void nv3_recalc_timings(svga_t* svga); void nv3_force_redraw(void* priv); diff --git a/src/qt/CMakeLists.txt b/src/qt/CMakeLists.txt index 4231034d5..c2e5e4df4 100644 --- a/src/qt/CMakeLists.txt +++ b/src/qt/CMakeLists.txt @@ -151,7 +151,11 @@ add_library(ui STATIC qt_newfloppydialog.ui qt_harddiskdialog.cpp qt_harddiskdialog.hpp - qt_harddiskdialog.ui + qt_harddiskdialog.ui + + qt_gpudebug_vram.cpp + qt_gpudebug_vram.hpp + qt_gpudebug_vram.ui qt_harddrive_common.cpp qt_harddrive_common.hpp diff --git a/src/qt/qt_gpudebug_vram.cpp b/src/qt/qt_gpudebug_vram.cpp new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/src/qt/qt_gpudebug_vram.cpp @@ -0,0 +1 @@ + diff --git a/src/qt/qt_gpudebug_vram.hpp b/src/qt/qt_gpudebug_vram.hpp new file mode 100644 index 000000000..975583f7f --- /dev/null +++ b/src/qt/qt_gpudebug_vram.hpp @@ -0,0 +1,18 @@ +#pragma once + +#include + +namespace Ui +{ + class GPUDebugVRAMDialog; +} + +class Ui::GPUDebugVRAMDialog : public QDialog +{ + public: + void Init(); + protected: + private: + + +}; \ No newline at end of file diff --git a/src/qt/qt_gpudebug_vram.ui b/src/qt/qt_gpudebug_vram.ui new file mode 100644 index 000000000..0f6c9931f --- /dev/null +++ b/src/qt/qt_gpudebug_vram.ui @@ -0,0 +1,56 @@ + + + + GPUDebugVRAMDialog + + + + 0 + 0 + 421 + 269 + + + + + 0 + 0 + + + + + 421 + 269 + + + + + 421 + 269 + + + + Dialog + + + + + + false + + + 0 + + + true + + + + + + + Sectors: + + + + diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index 83a80342b..2861b65be 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -222,11 +222,19 @@ + + + &Debugging Tools + + + + + @@ -899,6 +907,16 @@ Pen + + + GPU Debug - VRAM Viewer + + + + + GPU Debug - NV3 Visual Debugger + + diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 031827677..d08768e3c 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -725,18 +725,18 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) switch (crtcreg) { case NV3_CRTC_REGISTER_READ_BANK: - nv3->nvbase.cio_read_bank = val; - if (nv3->nvbase.svga.chain4) // chain4 addressing (planar?) - nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 15; - else - nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 13; // extended bank numbers + nv3->nvbase.cio_read_bank = val; + if (nv3->nvbase.svga.chain4) // chain4 addressing (planar?) + nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 15; + else + nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 13; // extended bank numbers break; case NV3_CRTC_REGISTER_WRITE_BANK: nv3->nvbase.cio_write_bank = val; - if (nv3->nvbase.svga.chain4) - nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 15; - else - nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 13; + if (nv3->nvbase.svga.chain4) + nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 15; + else + nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 13; break; case NV3_CRTC_REGISTER_RMA: nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX; @@ -769,6 +769,15 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) i2c_gpio_set(nv3->nvbase.i2c, scl, sda); break; } + /* [6:0] contains cursorAddr [23:17] */ + case NV3_CRTC_REGISTER_CURSOR_ADDR0: + nv3->pramdac.cursor_address |= val << 17; //bit7 technically ignored, but nv don't care, so neither do we + break; + /* [7:2] contains cursorAddr [16:11] */ + case NV3_CRTC_REGISTER_CURSOR_ADDR1: + nv3->pramdac.cursor_address |= (val >> 2) << 13; // bit0 and 1 aren't part of the address + break; + } @@ -852,11 +861,109 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) // sanity check if (!nv3) return; + + // if cursor disabled is set, return + if ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_CURSOR_START] >> NV3_CRTC_REGISTER_CURSOR_START_DISABLED) & 0x01) + return; // On windows, this shows up using NV_IMAGE_IN_MEMORY. // Do we need to emulate it? + uint32_t vram_cursor_base = nv3->pramdac.cursor_address; + /* let's just assume buffer 0 here...that code needs to be totally rewritten*/ + nv3_coord_16_t start_position = nv3->pramdac.cursor_start; - nv_log("nv3_draw_cursor drawline=0x%04x", drawline); + /* refuse to draw if thge cursor is offscreen */ + if (start_position.x >= nv3->nvbase.svga.hdisp + || start_position.y >= nv3->nvbase.svga.dispend) + { + return; + } + + nv_log("nv3_draw_cursor start=0x%04x,0x%04x", start_position.x, start_position.y); + + uint32_t final_position = nv3_render_get_vram_address_for_buffer(start_position, 0); + + uint16_t* vram_16 = (uint16_t*)nv3->nvbase.svga.vram; + uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; + + /* + We have to get a 32x32, "A"1R5G5B5-format cursor + out of video memory. The alpha bit actually means - XOR with display pixel if 0, replace if 1 + + Technically these are expanded to RGB10, but I don't see why this needs to happen. And our pipeline isn't set up for it anyway. + */ + for (int32_t y = 0; y < NV3_PRAMDAC_CURSOR_SIZE_Y; y++) + { + for (int32_t x = 0; x < NV3_PRAMDAC_CURSOR_SIZE_X; x++) + { + uint16_t current_pixel = vram_16[vram_cursor_base << 1]; + bool replace_bit = (current_pixel & 0x8000); + + switch (nv3->nvbase.svga.bpp) + { + /* this is indexed colour but... lol */ + case 8: + if (replace_bit) + { + uint8_t final = current_pixel ^ nv3->nvbase.svga.vram[final_position]; + nv3->nvbase.svga.vram[final_position] = final; + } + else // just override + nv3->nvbase.svga.vram[final_position] = current_pixel; + case 15 ... 16: // easy case (our cursor is 15bpp format) + uint32_t index_16 = final_position >> 1; + if (replace_bit) + { + uint16_t final = current_pixel ^ vram_16[index_16]; + vram_16[index_16] = final; + } + else // just override + vram_16[index_16] = current_pixel; + case 32: + uint32_t index_32 = final_position >> 2; + if (replace_bit) + { + uint16_t final = current_pixel ^ vram_32[index_32]; + vram_32[index_32] = final; + } + else // just override + vram_32[index_32] = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here + break; + } + + // increment vram position + vram_cursor_base += 2; + + // go + switch (nv3->nvbase.svga.bpp) + { + case 8: + final_position++; + case 15 ... 16: + final_position += 2; + break; + case 32: + final_position += 4; + break; + } + + start_position.x++; + } + + + start_position.y++; + start_position.x = nv3->pramdac.cursor_start.x; + + // reset at the end of each line so we "jump" to the start x + final_position = nv3_render_get_vram_address_for_buffer(start_position, 0); + } + + nv3_coord_16_t size = {0}; + size.x = size.y = 32; + nv3_grobj_t dummy = {0}; // need to clean it up + + /* do we need to update here? */ + nv3_render_current_bpp(&nv3->nvbase.svga, start_position, size, dummy, false, false); } // MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 6d29965d4..b7a45f9a8 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -161,7 +161,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { buf_position = (nv3->pgraph.blit.size.x * y); /* shouldn't matter in non-wtf mode */ - vram_position = nv3_render_get_vram_address_for_buffer(old_position, grobj, src_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(old_position, src_buffer); memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); old_position.y++; @@ -172,7 +172,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) { buf_position = (nv3->pgraph.blit.size.x * y); - vram_position = nv3_render_get_vram_address_for_buffer(new_position, grobj, dst_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(new_position, dst_buffer); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); new_position.y++; diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index acbf9fa05..6a1823883 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -260,7 +260,7 @@ uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj) /* Combine the current buffer with the pitch to get the address in the video ram for a specific position relative to a specific framebuffer */ -uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, nv3_grobj_t grobj, uint32_t buffer) +uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, uint32_t buffer) { uint32_t vram_x = position.x; uint32_t vram_y = position.y; @@ -663,7 +663,7 @@ void nv3_render_8bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; @@ -704,7 +704,7 @@ void nv3_render_15bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; @@ -745,7 +745,7 @@ void nv3_render_16bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; @@ -786,7 +786,7 @@ void nv3_render_32bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj { /* re-set the vram address because we are basically "jumping" halfway across a line here */ if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, grobj, 0); // hardcode to zero for now + vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now else vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index 88b910b6f..b7c984f26 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -182,7 +182,7 @@ void nv3_pramdac_set_pixel_clock(void) nv3->nvbase.svga.clock = cpuclock / frequency; - double time = 1000000.0 / (double)frequency; // needs to be a double for 86box + double time = 1000000.0 / (double)frequency; // needs to be a double for 86box nv_log("Pixel clock = %.2f MHz\n", frequency / 1000000.0f); @@ -205,6 +205,7 @@ void nv3_pramdac_set_pixel_clock(void) // NULL means handle in read functions nv_register_t pramdac_registers[] = { + { NV3_PRAMDAC_CURSOR_START, "PRAMDAC - Cursor Start Position"}, { NV3_PRAMDAC_CLOCK_PIXEL, "PRAMDAC - NV3 GPU Core - Pixel clock", nv3_pramdac_get_pixel_clock_register, nv3_pramdac_set_pixel_clock_register }, { NV3_PRAMDAC_CLOCK_MEMORY, "PRAMDAC - NV3 GPU Core - Memory clock", nv3_pramdac_get_vram_clock_register, nv3_pramdac_set_vram_clock_register }, { NV3_PRAMDAC_COEFF_SELECT, "PRAMDAC - PLL Clock Coefficient Select", NULL, NULL}, @@ -320,6 +321,9 @@ uint32_t nv3_pramdac_read(uint32_t address) ret = nv3->pramdac.palette[nv3->pramdac.user_read_mode_address]; nv3->pramdac.user_read_mode_address++; break; + case NV3_PRAMDAC_CURSOR_START: + ret = (nv3->pramdac.cursor_start.y << 16) | nv3->pramdac.cursor_start.x; + break; } } @@ -345,8 +349,6 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) // if the register actually exists if (reg) { - - // on-read function if (reg->on_write) reg->on_write(value); @@ -434,6 +436,13 @@ void nv3_pramdac_write(uint32_t address, uint32_t value) nv3->pramdac.user_write_mode_address++; break; + /* cursor start location */ + case NV3_PRAMDAC_CURSOR_START: + // only 12 bits are used here instead of 16 for some stupid reason + nv3->pramdac.cursor_start.y = (value >> 16) & 0xFFF; + nv3->pramdac.cursor_start.x = (value) & 0xFFF; + nv3_draw_cursor(&nv3->nvbase.svga, 0);//drawline doesn't matter here + break; } } From ff96ce99b649174ca1bce0542afbcc96c1b12a0a Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 27 Apr 2025 23:23:50 +0100 Subject: [PATCH 187/274] Add a very very early (8 Aug 1997), hitherto entirely undumped VBIOS. It has bugs that prevent it from being used in Windows 98 Setup. --- src/include/86box/nv/vid_nv3.h | 7 +++++-- src/video/nv/nv3/nv3_core_config.c | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index ebb7c0755..4fd3c6676 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -61,7 +61,10 @@ extern const device_config_t nv3t_config[]; // Confi // Coming soon: MIROmagic Premium BIOS (when I get mine dumped) //todo: move to hash system -// Oldest one of these - September 6, 1997 +// Oldest one of these - August 8, 1997 + +// This particular VBIOS is very early and has certain bugs +#define NV3_VBIOS_STB_V128_V160 "roms/video/nvidia/nv3/stb-velocity128-1.6.bin" // STB Velocity 128 3D (Riva 128) Ver.1.60 #define NV3_VBIOS_ERAZOR_V14700 "roms/video/nvidia/nv3/OLD_0000.BIN" // ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00) #define NV3_VBIOS_ERAZOR_V15403 "roms/video/nvidia/nv3/VCERAZOR.BIN" // ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS] #define NV3_VBIOS_ERAZOR_V15500 "roms/video/nvidia/nv3/Ver15500.rv_" // ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS] @@ -72,7 +75,7 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3T_VBIOS_ASUS_V170 "roms/video/nvidia/nv3/A170D03T.rom" // ASUS AGP-V3000 ZXTV BIOS - V1.70D.03 (C) 1996-98 Nvidia Corporation #define NV3T_VBIOS_REFERENCE_CEK_V171 "roms/video/nvidia/nv3/BIOS_49_Riva 128" // Reference BIOS: RIVA 128 ZX BIOS - V1.71B-N (C) 1996-98 NVidia Corporation #define NV3T_VBIOS_REFERENCE_CEK_V172 "roms/video/nvidia/nv3/vgasgram.rom" // Reference(?) BIOS: RIVA 128 ZX BIOS - V1.72B (C) 1996-98 NVidia Corporation - +# // The default VBIOS to use #define NV3_VBIOS_DEFAULT NV3_VBIOS_ERAZOR_V15403 diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c index ec7d46e30..b039ff82b 100644 --- a/src/video/nv/nv3/nv3_core_config.c +++ b/src/video/nv/nv3/nv3_core_config.c @@ -38,6 +38,7 @@ const device_config_t nv3_config[] = .default_int = 0, .bios = { + { .name = "ELSA VICTORY Erazor - Version 1.47.00", .files_no = 1, .internal_name = "NV3_VBIOS_ERAZOR_V14700", @@ -63,6 +64,11 @@ const device_config_t nv3_config[] = .internal_name = "NV3_VBIOS_ASUS_V3000_V151", .files = {NV3_VBIOS_ASUS_V3000_V151, ""}, }, + { + .name = "STB Velocity 128 - Version 1.60 [BUGGY]", .files_no = 1, + .internal_name = "NV3_VBIOS_STB_V128_V160", + .files = {NV3_VBIOS_STB_V128_V160, ""}, + }, { .name = "STB Velocity 128 - Version 1.82", .files_no = 1, .internal_name = "NV3_VBIOS_STB_V128_V182", From 44bf760861710e8c62376e49e667ef2e21d05dbc Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 28 Apr 2025 02:04:49 +0100 Subject: [PATCH 188/274] add vram viewer window --- src/qt/qt_gpudebug_vram.cpp | 53 +++++++++++++++++++++++++++++++++++++ src/qt/qt_gpudebug_vram.hpp | 26 ++++++++++++++++-- src/qt/qt_gpudebug_vram.ui | 32 +++++++--------------- src/qt/qt_mainwindow.cpp | 12 +++++++++ src/qt/qt_mainwindow.hpp | 1 + 5 files changed, 100 insertions(+), 24 deletions(-) diff --git a/src/qt/qt_gpudebug_vram.cpp b/src/qt/qt_gpudebug_vram.cpp index 8b1378917..000f41263 100644 --- a/src/qt/qt_gpudebug_vram.cpp +++ b/src/qt/qt_gpudebug_vram.cpp @@ -1 +1,54 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * GPU Debugging Tools - VRAM Viewer implementation + * + * + * + * Authors: starfrost + * + * Copyright 2025 starfrost + */ +/* C++ includes */ +#include +#include + + +/* Qt includes*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ui_qt_gpudebug_vram.h" + +/* 86Box core includes */ +extern "C" +{ + +} + +GPUDebugVRAMDialog::GPUDebugVRAMDialog(QWidget *parent) + : QDialog(parent) + , ui(new Ui::GPUDebugVRAMDialog) +{ + ui->setupUi(this); +} + +GPUDebugVRAMDialog::~GPUDebugVRAMDialog() +{ + +} \ No newline at end of file diff --git a/src/qt/qt_gpudebug_vram.hpp b/src/qt/qt_gpudebug_vram.hpp index 975583f7f..18b2e8c96 100644 --- a/src/qt/qt_gpudebug_vram.hpp +++ b/src/qt/qt_gpudebug_vram.hpp @@ -1,3 +1,21 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * GPU Debugging Tools - VRAM Viewer headers + * + * + * + * Authors: starfrost + * + * Copyright 2025 starfrost + */ + + #pragma once #include @@ -7,12 +25,16 @@ namespace Ui class GPUDebugVRAMDialog; } -class Ui::GPUDebugVRAMDialog : public QDialog +class GPUDebugVRAMDialog : public QDialog { + Q_OBJECT + public: - void Init(); + explicit GPUDebugVRAMDialog(QWidget *parent = nullptr); + ~GPUDebugVRAMDialog(); protected: private: + Ui::GPUDebugVRAMDialog* ui; }; \ No newline at end of file diff --git a/src/qt/qt_gpudebug_vram.ui b/src/qt/qt_gpudebug_vram.ui index 0f6c9931f..be2bd4a20 100644 --- a/src/qt/qt_gpudebug_vram.ui +++ b/src/qt/qt_gpudebug_vram.ui @@ -1,8 +1,7 @@ - GPUDebugVRAMDialog - + 0 @@ -30,27 +29,16 @@ - Dialog + VRAM Viewer - - - - false - - - 0 - - - true - - - - - - - Sectors: - - + + + + VRAM Viewer + + + + diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index 1fb9b3fb5..dc0b923b4 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -23,6 +23,7 @@ #include #include "qt_mainwindow.hpp" +#include "qt_gpudebug_vram.hpp" #include "ui_qt_mainwindow.h" #include "qt_specifydimensions.h" @@ -100,6 +101,8 @@ extern bool cpu_thread_running; #include "qt_mediamenu.hpp" #include "qt_util.hpp" +#include "qt_gpudebug_vram.hpp" + #if defined __unix__ && !defined __HAIKU__ # ifndef Q_OS_MACOS # include "evdev_keyboard.hpp" @@ -2267,3 +2270,12 @@ void MainWindow::on_actionACPI_Shutdown_triggered() { acpi_pwrbut_pressed = 1; } + +void MainWindow::on_actionDebug_GPUDebug_VRAM_triggered() +{ + GPUDebugVRAMDialog debugVramDialog(this); + debugVramDialog.setWindowFlag(Qt::CustomizeWindowHint, true); + debugVramDialog.setWindowFlag(Qt::WindowTitleHint, true); + debugVramDialog.setWindowFlag(Qt::WindowSystemMenuHint, false); + debugVramDialog.exec(); +} \ No newline at end of file diff --git a/src/qt/qt_mainwindow.hpp b/src/qt/qt_mainwindow.hpp index 5811ac36a..1798c8a75 100644 --- a/src/qt/qt_mainwindow.hpp +++ b/src/qt/qt_mainwindow.hpp @@ -125,6 +125,7 @@ private slots: void on_actionPreferences_triggered(); void on_actionEnable_Discord_integration_triggered(bool checked); void on_actionRenderer_options_triggered(); + void on_actionDebug_GPUDebug_VRAM_triggered(); void refreshMediaMenu(); void showMessage_(int flags, const QString &header, const QString &message, bool richText, std::atomic_bool* done = nullptr); From 6ebcbdb0026466120d29c2a90fd38f5cc454c7e9 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 29 Apr 2025 21:11:32 +0100 Subject: [PATCH 189/274] minor cleanups --- src/video/nv/nv3/render/nv3_render_core.c | 14 ++++++++++++-- src/video/nv/nv3/subsystems/nv3_pramin.c | 8 ++++---- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 6a1823883..42392a9ce 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -301,8 +301,6 @@ nv3_coord_16_t nv3_render_get_dfb_position(uint32_t vram_address) else if (nv3->nvbase.svga.bpp == 32) pitch <<= 2; - //vram_address -= nv3->pgraph.boffset[0]; - pos.y = (vram_address / pitch); pos.x = (vram_address % pitch); @@ -529,6 +527,10 @@ void nv3_render_ensure_screen_size(void) /* Blit to the monitor from DFB, 8bpp */ void nv3_render_current_bpp_dfb_8(uint32_t address) { + /* Broken as fuck early vbios does this. Wtf? */ + if (!nv3->nvbase.svga.hdisp) + return; + nv3_coord_16_t size = {0}; size.x = size.y = 1; @@ -543,6 +545,10 @@ void nv3_render_current_bpp_dfb_8(uint32_t address) /* Blit to the monitor from DFB, 15/16bpp */ void nv3_render_current_bpp_dfb_16(uint32_t address) { + /* Broken as fuck early vbios does this. Wtf? */ + if (!nv3->nvbase.svga.hdisp) + return; + nv3_coord_16_t size = {0}; size.x = size.y = 1; @@ -564,6 +570,10 @@ void nv3_render_current_bpp_dfb_16(uint32_t address) /* Blit to the monitor from DFB, 32bpp */ void nv3_render_current_bpp_dfb_32(uint32_t address) { + /* Broken as fuck early vbios does this. Wtf? */ + if (!nv3->nvbase.svga.hdisp) + return; + nv3_coord_16_t size = {0}; size.x = size.y = 1; diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 8556822f5..4cd6d10c3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -96,14 +96,14 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv) // Read 32-bit ramin uint32_t nv3_ramin_read32(uint32_t addr, void* priv) { - if (!nv3) return 0x00; + if (!nv3) + return 0x00; addr &= (nv3->nvbase.svga.vram_max - 1); // why does this not work in one line - svga_t* svga = &nv3->nvbase.svga; - uint32_t* vram_32bit = (uint32_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and + uint32_t* vram_32bit = (uint32_t*)nv3->nvbase.svga.vram; + uint32_t raw_addr = addr; // saved after and logged addr ^= (nv3->nvbase.svga.vram_max - 0x10); addr >>= 2; // what From cd4ecff05663d5dc8bcf3307299e43827d87e10f Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 3 May 2025 22:41:49 +0100 Subject: [PATCH 190/274] Acknowledge the existence of dpram --- src/include/86box/nv/vid_nv3.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 4fd3c6676..965e2d0e1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -622,6 +622,8 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PGRAPH_DMA_INTR_NOTIFY 16 #define NV3_PGRAPH_DMA_INTR_EN_0 0x401140 // PGRAPH DMA Interrupt Enable 0 +#define NV3_PGRAPH_DPRAM_SIZE 12288 // Size of the internal texture cache + // not sure about the class ids // these are NOT what each class is, just uSed to manipulate it (there isn't a one to one class->reg mapping anyway) #define NV3_PGRAPH_CLASS01_BETA_START 0x410000 // Beta blending factor @@ -1242,14 +1244,15 @@ typedef struct nv3_pgraph_s nv3_coord_16_bigy_t clip1_min; nv3_coord_16_bigy_t clip1_max; /* idk */ - nv3_coord_16_t clip_start; // Start of the clipping region - nv3_coord_16_t clip_size; // Size of the clipping region. + nv3_coord_16_t clip_start; // Start of the clipping region + nv3_coord_16_t clip_size; // Size of the clipping region. bool fifo_access; // Determines if PGRAPH can access PFIFO. nv3_pgraph_status_t status; // Current status of the 3D engine. uint32_t trapped_address; uint32_t trapped_data; uint32_t instance; // no idea what this is but possibly an object context uint32_t trapped_instance; + uint8_t dpram[NV3_PGRAPH_DPRAM_SIZE]; // Internal vertex/texturea cache. /* This area is used for holding universal representations of the U* registers, which are actually mapped into MMIO */ struct nv3_object_class_001 beta_factor_class; From aaaa4db881cb5e6ad7e909ce6f5aa612a1b4da2e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 18 May 2025 16:45:24 +0100 Subject: [PATCH 191/274] Fix various minor bugs; correctly use bpixel for rendering instead of svga->bpp. remove incorrect DBA check --- CMakePresets.json | 3 +- doc/nvidia_notes/NV128.xlsx | Bin 9708 -> 0 bytes src/include/86box/nv/render/vid_nv3_render.h | 2 +- src/qt/qt_gpudebug_vram.ui | 29 ++++++--- src/video/nv/nv3/nv3_core.c | 2 +- src/video/nv/nv3/render/nv3_render_blit.c | 13 ++-- src/video/nv/nv3/render/nv3_render_core.c | 59 ++++++++----------- src/video/nv/nv3/subsystems/nv3_pfb.c | 2 +- 8 files changed, 54 insertions(+), 56 deletions(-) delete mode 100644 doc/nvidia_notes/NV128.xlsx diff --git a/CMakePresets.json b/CMakePresets.json index b2ed64e97..30feab8ab 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -36,8 +36,7 @@ "name": "debug", "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug", - "NV_LOG": "ON", - "NV_LOG_ULTRA": "ON" + "NV_LOG": "ON" }, "inherits": "base" }, diff --git a/doc/nvidia_notes/NV128.xlsx b/doc/nvidia_notes/NV128.xlsx deleted file mode 100644 index fbf57c5eb136926abfc26b411f6aec0ae899a3fc..0000000000000000000000000000000000000000 GIT binary patch literal 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nv3_coord_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer); +void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); void nv3_render_current_bpp_dfb_8(uint32_t address); void nv3_render_current_bpp_dfb_16(uint32_t address); void nv3_render_current_bpp_dfb_32(uint32_t address); diff --git a/src/qt/qt_gpudebug_vram.ui b/src/qt/qt_gpudebug_vram.ui index be2bd4a20..12c64e3b4 100644 --- a/src/qt/qt_gpudebug_vram.ui +++ b/src/qt/qt_gpudebug_vram.ui @@ -32,13 +32,28 @@ VRAM Viewer - - - - VRAM Viewer - - + + + + VRAM + + + Qt::AlignmentFlag::AlignLeading|Qt::AlignmentFlag::AlignLeft|Qt::AlignmentFlag::AlignTop + + + + + + + TextLabel + + + Qt::AlignmentFlag::AlignBottom|Qt::AlignmentFlag::AlignLeading|Qt::AlignmentFlag::AlignLeft + + - + + + diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index d08768e3c..824d96405 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -963,7 +963,7 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) nv3_grobj_t dummy = {0}; // need to clean it up /* do we need to update here? */ - nv3_render_current_bpp(&nv3->nvbase.svga, start_position, size, dummy, false, false); + nv3_render_current_bpp(&nv3->nvbase.svga, start_position, size, dummy, false); } // MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index b7a45f9a8..da139b496 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -57,7 +57,7 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) /* the reverse order is due to the endianness */ switch (nv3->nvbase.svga.bpp) { - // 4pixels packed into one color + // 4 pixels packed into one color in 8bpp case 8: //pixel3 @@ -82,7 +82,7 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) nv3_class_011_check_line_bounds(); break; - //2pixels packed into one color + // 2 pixels packed into one color in 15/16bpp case 15: case 16: pixel1 = (color) & 0xFFFF; @@ -98,8 +98,7 @@ void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) break; // just one pixel in 32bpp case 32: - pixel0 = color; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); + if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, color, grobj); nv3->pgraph.image_current_position.x++; nv3_class_011_check_line_bounds(); @@ -183,8 +182,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) We also need to update all of the areas of the screen that moved. */ - nv3_coord_16_t blit_position = {0}; - nv3_coord_16_t blit_size = {0}; + nv3_coord_16_t blit_position = {0}, blit_size = {0}; /* Change the smallest area of the screen that moved */ @@ -223,7 +221,6 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) /* If the BUFFER_ADDRESS of the last buffer is not the DBA, we don't *actually* want to draw this, so let's not Apply stupid hack */ - - nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj, false, true); + nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj, true); } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 42392a9ce..3491c8df3 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -81,10 +81,10 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) break; case nv3_pgraph_pixel_format_r10g10b10: - color_final.a = (color << 31) & 0x01; - color_final.r = (color << 30) & 0x3FF; - color_final.g = (color << 20) & 0x1FF; - color_final.b = (color << 10); + color_final.a = (color >> 31) & 0x01; + color_final.r = (color >> 30) & 0x3FF; + color_final.g = (color >> 20) & 0x1FF; + color_final.b = (color >> 10); break; case nv3_pgraph_pixel_format_y8: @@ -138,7 +138,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co break; case nv3_pgraph_pixel_format_r10g10b10: /* sometimes alpha isn't used but we should incorporate it anyway */ - if (color.a > 0x00) packed_color | (1 << 31); + if (color.a > 0x00) packed_color |= (1 << 31); packed_color |= (color.r << 30); packed_color |= (color.g << 20); @@ -187,7 +187,7 @@ bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj) uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) { // convert the alpha to 1 bit. then return packed rgb10 - return !!expanded.a | (expanded.r << 30) | (expanded.b << 20) | (expanded.a << 10); + return !!expanded.a | (expanded.r << 30) | (expanded.b << 20) | (expanded.b << 10); } /* Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) */ @@ -360,6 +360,14 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + uint32_t dst_buffer = 0; // 5 = just use the source buffer + + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; + if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; + + uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too?z int32_t clip_end_x = nv3->pgraph.clip_start.x + nv3->pgraph.clip_size.x; @@ -426,12 +434,14 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t It seems we can skip the downconversion step *for now*, since (framebuffer bits per pixel) == (object bits per pixel) I'm not sure how games will react. But it depends on how the D3D drivers operate, we may need ro convert texture formats to the current bpp internally. - TODO: MOVE TO BPIXEL DEPTH or GROBJ0 to determine this, once we figure out how to get the bpixel depth. + We use the pixel format of the destination buffer to achieve this (thanks frostbite2000) */ - switch (framebuffer_bpp) + uint32_t destination_format = (nv3->pgraph.bpixel[dst_buffer]) & 0x03; + + switch (destination_format) { - case 8: + case bpixel_fmt_8bit: rop_src = color & 0xFF; rop_dst = nv3->nvbase.svga.vram[pixel_addr_vram]; nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern) & 0xFF; @@ -439,8 +449,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; break; - case 15: - case 16: + case bpixel_fmt_16bit: { uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 1; @@ -471,7 +480,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t break; } - case 32: + case bpixel_fmt_32bit: { uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); pixel_addr_vram >>= 2; @@ -489,7 +498,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t /* Go write the pixel */ nv3_coord_16_t size = {0}; size.x = size.y = 1; - nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, true, false); + nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, false); } /* Ensure the correct monitor size */ @@ -602,35 +611,13 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) /* Blit to the monitor from GPU, current bpp */ -void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer) +void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) { /* Ensure that we are in the correct mode. Modified SVGA core code */ nv3_render_ensure_screen_size(); /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM, so it can be used for s2sb's etc */ - /* Not needed for s2sb*/ - if (run_render_check) - { - /* Figure out the Display Buffer Address from the CRTCs */ - uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) - + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) - + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; - - /* Check our destination(?) buffer */ - uint32_t dst_buffer = 0; // 5 = just use the source buffer - - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; - - /* If the BUFFER_ADDRESS of the last buffer is not the DBA, we don't *actually* want to draw this, so let's not */ - if (nv3->pgraph.boffset[dst_buffer] != dba) - return; - } - - switch (nv3->nvbase.svga.bpp) { case 4: diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 3e6cd4271..7360a2c9a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -39,7 +39,7 @@ nv_register_t pfb_registers[] = { { NV3_PFB_GREEN_0, "PFB Green / Power Saving", NULL, NULL,}, { NV3_PFB_CONFIG_0, "PFB Framebuffer Config 0", nv3_pfb_config0_read, nv3_pfb_config0_write }, { NV3_PFB_CONFIG_1, "PFB Framebuffer Config 1", NULL, NULL }, - { NV3_PFB_RTL, "PFB RTL (Part of memory timings?)", NULL, NULL }, + { NV3_PFB_RTL, "PFB RTL (Part of memory timings)", NULL, NULL }, { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; From 6ba3d8981067d500ae4c5584995c71a1055ac803 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 18 May 2025 17:34:39 +0100 Subject: [PATCH 192/274] big rendering refactor --- src/include/86box/nv/render/vid_nv3_render.h | 2 +- src/video/nv/nv3/nv3_core.c | 7 - src/video/nv/nv3/render/nv3_render_blit.c | 47 ------ src/video/nv/nv3/render/nv3_render_core.c | 162 +++++++------------ src/video/nv/nv3/subsystems/nv3_pramdac.c | 1 + 5 files changed, 64 insertions(+), 155 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index c3e6182e5..9c7af77ab 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -18,7 +18,7 @@ #pragma once /* Core */ -void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_current_bpp(); void nv3_render_current_bpp_dfb_8(uint32_t address); void nv3_render_current_bpp_dfb_16(uint32_t address); void nv3_render_current_bpp_dfb_32(uint32_t address); diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 824d96405..21810386e 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -957,13 +957,6 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) // reset at the end of each line so we "jump" to the start x final_position = nv3_render_get_vram_address_for_buffer(start_position, 0); } - - nv3_coord_16_t size = {0}; - size.x = size.y = 32; - nv3_grobj_t dummy = {0}; // need to clean it up - - /* do we need to update here? */ - nv3_render_current_bpp(&nv3->nvbase.svga, start_position, size, dummy, false); } // MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index da139b496..0b0cb1c31 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -176,51 +176,4 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); new_position.y++; } - - /* - We need to blit manually here because we don't go through nv3_render_write_pixel - We also need to update all of the areas of the screen that moved. - */ - - nv3_coord_16_t blit_position = {0}, blit_size = {0}; - - /* Change the smallest area of the screen that moved */ - - if (cross_buffer_blit) - { - blit_position = nv3->pgraph.blit.point_out; - blit_size = nv3->pgraph.blit.size; - } - else - { - if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) - blit_size.x = (nv3->pgraph.blit.point_out.x - nv3->pgraph.blit.point_in.x) + nv3->pgraph.blit.size.x; - else if (nv3->pgraph.blit.point_out.x < nv3->pgraph.blit.point_in.x) - blit_size.x = (nv3->pgraph.blit.point_in.x - nv3->pgraph.blit.point_out.x) + nv3->pgraph.blit.size.x; - else - blit_size.x = nv3->pgraph.blit.size.x; - - if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) - blit_size.y = (nv3->pgraph.blit.point_out.y - nv3->pgraph.blit.point_in.y) + nv3->pgraph.blit.size.y; - else if (nv3->pgraph.blit.point_out.y < nv3->pgraph.blit.point_in.y) - blit_size.y = (nv3->pgraph.blit.point_in.y - nv3->pgraph.blit.point_out.y) + nv3->pgraph.blit.size.y; - else - blit_size.y = nv3->pgraph.blit.size.y; - - if (nv3->pgraph.blit.point_out.x > nv3->pgraph.blit.point_in.x) - blit_position.x = nv3->pgraph.blit.point_in.x; - else if (nv3->pgraph.blit.point_out.x <= nv3->pgraph.blit.point_in.x) // equals case, just use out - blit_position.x = nv3->pgraph.blit.point_out.x; - - if (nv3->pgraph.blit.point_out.y > nv3->pgraph.blit.point_in.y) - blit_position.y = nv3->pgraph.blit.point_in.y; - else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out - blit_position.y = nv3->pgraph.blit.point_out.y; - - } - - /* If the BUFFER_ADDRESS of the last buffer is not the DBA, we don't *actually* want to draw this, so let's not - Apply stupid hack */ - - nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj, true); } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 3491c8df3..72617c6aa 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -31,10 +31,10 @@ #include <86box/utils/video_stdlib.h> /* Functions only used in this translation unit */ -void nv3_render_8bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); -void nv3_render_15bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); -void nv3_render_16bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); -void nv3_render_32bpp(nv3_coord_16_t position, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer); +void nv3_render_8bpp(uint32_t vram_start, nv3_coord_16_t screen_size); +void nv3_render_15bpp(uint32_t vram_start, nv3_coord_16_t screen_size); +void nv3_render_16bpp(uint32_t vram_start, nv3_coord_16_t screen_size); +void nv3_render_32bpp(uint32_t vram_start, nv3_coord_16_t screen_size); /* Expand a colour. NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! @@ -494,11 +494,6 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t break; } } - - /* Go write the pixel */ - nv3_coord_16_t size = {0}; - size.x = size.y = 1; - nv3_render_current_bpp(&nv3->nvbase.svga, position, size, grobj, false); } /* Ensure the correct monitor size */ @@ -590,19 +585,16 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); + uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + if (nv3->nvbase.svga.bpp == 32) { - uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; *p = data; } /* Packed format */ else if (nv3->nvbase.svga.bpp == 15 || nv3->nvbase.svga.bpp == 16) { - //pos.x >>= 1; - - uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, nv3->nvbase.svga.bpp); *p++; *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, (data >> 16) & 0xFFFF, nv3->nvbase.svga.bpp); @@ -611,9 +603,20 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) /* Blit to the monitor from GPU, current bpp */ -void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_current_bpp() { - /* Ensure that we are in the correct mode. Modified SVGA core code */ + /* Figure out the Display Buffer Address from the CRTC */ + + uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) + + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) + + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; + + nv3_coord_16_t screen_size = {0}; + screen_size.x = nv3->nvbase.svga.hdisp; + screen_size.y = nv3->nvbase.svga.dispend; + + /* Ensure that we are + in the correct mode. Modified SVGA core code */ nv3_render_ensure_screen_size(); /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM, so it can be used for s2sb's etc */ @@ -625,16 +628,16 @@ void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t pos, nv3_coord_16_t siz fatal("NV3 - 4bpp not implemented (not even sure if it's SVGA only)"); break; case 8: - nv3_render_8bpp(pos, size, grobj, use_destination_buffer); + nv3_render_8bpp(dba, screen_size); break; case 15: - nv3_render_15bpp(pos, size, grobj, use_destination_buffer); + nv3_render_15bpp(dba, screen_size); break; case 16: - nv3_render_16bpp(pos, size, grobj, use_destination_buffer); + nv3_render_16bpp(dba, screen_size); break; - case 32: - nv3_render_32bpp(pos, size, grobj, use_destination_buffer); + case 32: + nv3_render_32bpp(dba, screen_size); break; } @@ -644,40 +647,29 @@ void nv3_render_current_bpp(svga_t *svga, nv3_coord_16_t pos, nv3_coord_16_t siz Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, indexed 8 bits per pixel format */ -void nv3_render_8bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_8bpp(uint32_t vram_start, nv3_coord_16_t screen_size) { if (!nv3) return; - uint32_t vram_base; //acquired for the start of each line + uint32_t vram_current_position = vram_start; uint32_t* p; - uint32_t data; - uint32_t start_x = pos.x; + uint32_t data = 0; - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - for (uint32_t y = 0; y < size.y; y++) + for (uint32_t y = 0; y < screen_size.y; y++) { - /* re-set the vram address because we are basically "jumping" halfway across a line here */ - if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now - else - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - - for (uint32_t x = 0; x < size.x; x++) + for (uint32_t x = 0; x < screen_size.x; x++) { - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; /* should just "tip over" to the next line */ *p = nv3_render_get_palette_index(data & 0xFF); - vram_base++; - pos.x++; + vram_current_position++; } - - pos.x = start_x; - pos.y++; } } @@ -685,40 +677,30 @@ void nv3_render_8bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 15 bits per pixel format */ -void nv3_render_15bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_15bpp(uint32_t vram_start, nv3_coord_16_t screen_size) { if (!nv3) return; - uint32_t vram_base; //acquired for the start of each line + uint32_t vram_current_position = vram_start; uint32_t* p; - uint32_t data; - uint32_t start_x = pos.x; + uint32_t data = 0; - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - for (uint32_t y = 0; y < size.y; y++) + for (uint32_t y = 0; y < screen_size.y; y++) { - /* re-set the vram address because we are basically "jumping" halfway across a line here */ - if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now - else - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - - for (uint32_t x = 0; x < size.x; x++) + for (uint32_t x = 0; x < screen_size.x; x++) { - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; /* should just "tip over" to the next line */ *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); - vram_base += 2; - pos.x++; + vram_current_position += 2; } - - pos.x = start_x; - pos.y++; + } } @@ -726,40 +708,31 @@ void nv3_render_15bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 16 bits per pixel format */ -void nv3_render_16bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_16bpp(uint32_t vram_start, nv3_coord_16_t screen_size) { if (!nv3) return; - uint32_t vram_base; //acquired for the start of each line + uint32_t vram_current_position = vram_start; uint32_t* p; - uint32_t data; - uint32_t start_x = pos.x; + uint32_t data = 0; - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - for (uint32_t y = 0; y < size.y; y++) + for (uint32_t y = 0; y < screen_size.y; y++) { - /* re-set the vram address because we are basically "jumping" halfway across a line here */ - if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now - else - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - - for (uint32_t x = 0; x < size.x; x++) + for (uint32_t x = 0; x < screen_size.x; x++) { - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; /* should just "tip over" to the next line */ *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); - vram_base += 2; - pos.x++; + vram_current_position += 2; + } - pos.x = start_x; - pos.y++; } } @@ -767,39 +740,28 @@ void nv3_render_16bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 32 bits per pixel format */ -void nv3_render_32bpp(nv3_coord_16_t pos, nv3_coord_16_t size, nv3_grobj_t grobj, bool use_destination_buffer) +void nv3_render_32bpp(uint32_t vram_start, nv3_coord_16_t screen_size) { if (!nv3) return; - uint32_t vram_base; + uint32_t vram_current_position = vram_start; uint32_t* p; - uint32_t data; - uint32_t start_x = pos.x; + uint32_t data = 0; - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - for (uint32_t y = 0; y < size.y; y++) + for (uint32_t y = 0; y < screen_size.y; y++) { - /* re-set the vram address because we are basically "jumping" halfway across a line here */ - if (use_destination_buffer) - vram_base = nv3_render_get_vram_address_for_buffer(pos, 0); // hardcode to zero for now - else - vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask; - - for (uint32_t x = 0; x < size.x; x++) + for (uint32_t x = 0; x < screen_size.x; x++) { - p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_base]; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; + data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; /* should just "tip over" to the next line */ *p = data; - vram_base += 4; - pos.x++; + vram_current_position += 4; } - - pos.y++; - pos.x = start_x; } } diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index b7c984f26..f179c8136 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -64,6 +64,7 @@ void nv3_pramdac_pixel_clock_poll(double real_time) if (nv3->nvbase.refresh_clock > nv3->nvbase.refresh_time) { /* Update the screen because something changed */ + nv3_render_current_bpp(); video_blit_memtoscreen(0, 0, xsize, ysize); nv3->nvbase.refresh_clock = 0; } From c1972f1b1389cbdbafbe22a862901e1dacb70374 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 18 May 2025 19:24:43 +0100 Subject: [PATCH 193/274] fix nv3_render_to_chroma --- src/video/nv/nv3/render/nv3_render_blit.c | 7 +++---- src/video/nv/nv3/render/nv3_render_core.c | 4 +++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 0b0cb1c31..596d7b7a1 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -133,8 +133,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; - - bool cross_buffer_blit = (nv3->pgraph.boffset[src_buffer] != nv3->pgraph.boffset[dst_buffer]); + nv3_coord_16_t old_position = nv3->pgraph.blit.point_in; nv3_coord_16_t new_position = nv3->pgraph.blit.point_out; @@ -160,7 +159,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { buf_position = (nv3->pgraph.blit.size.x * y); /* shouldn't matter in non-wtf mode */ - vram_position = nv3_render_get_vram_address_for_buffer(old_position, src_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(old_position, dst_buffer); memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); old_position.y++; @@ -171,7 +170,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) { buf_position = (nv3->pgraph.blit.size.x * y); - vram_position = nv3_render_get_vram_address_for_buffer(new_position, dst_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(new_position, src_buffer); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); new_position.y++; diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 72617c6aa..9611d8349 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -187,7 +187,7 @@ bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj) uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) { // convert the alpha to 1 bit. then return packed rgb10 - return !!expanded.a | (expanded.r << 30) | (expanded.b << 20) | (expanded.b << 10); + return !!expanded.a | (expanded.r << 30) | (expanded.g << 20) | (expanded.b << 10); } /* Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) */ @@ -611,6 +611,8 @@ void nv3_render_current_bpp() + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; + //uint32_t dba = 1920000; + nv3_coord_16_t screen_size = {0}; screen_size.x = nv3->nvbase.svga.hdisp; screen_size.y = nv3->nvbase.svga.dispend; From 28500a82baa6bb070e117739f1e057b153843f4b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 23 May 2025 15:59:54 +0100 Subject: [PATCH 194/274] sync --- doc/nvidia_notes/RIVA fansites.txt | 6 ++++-- src/include/86box/nv/vid_nv3.h | 8 ++++++++ src/video/nv/nv3/subsystems/nv3_pfifo.c | 1 - 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/doc/nvidia_notes/RIVA fansites.txt b/doc/nvidia_notes/RIVA fansites.txt index 5a3104837..d1cfaeb90 100644 --- a/doc/nvidia_notes/RIVA fansites.txt +++ b/doc/nvidia_notes/RIVA fansites.txt @@ -3,7 +3,7 @@ RIVA User's Group http://tiger.tnstate.edu:8080/ RIVA 128 Homepage http://pages.prodigy.net/babblin5/Main.html -> Riva3D (riva3d.com) Zone 128 http://www.tc.umn.edu/~reda0003/zone128/ RIVAZone https://web.archive.org/web/19981212032348/http://www.rivazone.com/ (Launched January 2, 1998) -Dimension 128 (early domain name that was never archived) -> d128.com (1999-2001) +Dimension 128 http://dimension128.smartcom.net (early domain name that was mostly not archived) -> d128.com (1999-2001) Riva3D https://web.archive.org/web/20000525110305/http://riva3d.gxnetwork.com/s3.html nVNews https://web.archive.org/web/20001205171202/http://www.nvnews.net/ (1999-2015) @@ -21,4 +21,6 @@ https://web.archive.org/web/19980615024744/http://www.ogr.com/columns/techtalk/t https://web.archive.org/web/20001002193706/http://www.rivazone.com/files/rivalog.txt -https://web.archive.org/web/20010422044820/http://www.rivazone.com/finger/finger.cgi?nick@finger.nvidia.com nvidia .plan files \ No newline at end of file +https://web.archive.org/web/20010422044820/http://www.rivazone.com/finger/finger.cgi?nick@finger.nvidia.com nvidia .plan files + +WAVE Report - april 1997 date for tapeout \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 965e2d0e1..e91afb5c9 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -462,6 +462,14 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PME_INTR 0x200100 // Mediaport: Interrupt Pending? #define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable #define NV3_PME_END 0x200FFF + +// THIS IS NOT A REAL REGISTER. +// This is so my software e.g. nvplayground can determine if the software is being run in an emulator on a real RIVA 128. +// This register should have some sort of open bus, garbage or 00/FF on a real NV3/NV3T but have a string. +#define NV3_EMULATED_MARKER_START 0x269420 + +#define NV3_EMULATED_MARKER 0x0D15EA5E + #define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part // PGRAPH Core diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 2625adda4..204d3f29c 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -955,7 +955,6 @@ void nv3_pfifo_cache1_pull(void) nv_log_verbose_only("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n"); - nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; nv3_debug_ramin_print_context_info(current_param, context_structure); From 9f3e189455ebec810e1ed624ded51f296dd5ae02 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 23 May 2025 16:07:04 +0100 Subject: [PATCH 195/274] minor changes for nvplay --- src/video/nv/nv3/nv3_core_arbiter.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 99aebb5e7..7182cc955 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -107,8 +107,15 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) ret = nv3_user_read(address); else { - warning("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); - return 0x00; + //nvplay stuff + #ifdef ENABLE_NV_LOG_ULTRA + warning("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); + #else + nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); + #endif + + // I don't know why the real hardware does this. But it does. + return (ret & 1) ? 0x20 : 0x07; } return ret; @@ -173,7 +180,13 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) //RAMIN is its own thing else { - warning("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address); + //nvplay stuff + #ifdef ENABLE_NV_LOG_ULTRA + warning("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); + #else + nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); + #endif + return; } } From 230b90954d43e8e72273f7f4e8fa8b39c594d6c5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 26 May 2025 01:41:10 +0100 Subject: [PATCH 196/274] don't force 1-byte packing of vid_nv3_classes --- src/include/86box/nv/classes/vid_nv3_classes.h | 2 -- src/include/86box/nv/vid_nv.h | 6 +++++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index d5dc3ed43..5c2cc5b8e 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -36,7 +36,6 @@ // or everything FUCKS UP // // DO NOT REMOVE! DO NOT REMOVE! DO NOT REMOVE! -#pragma pack(push, 1) // CLass names for debugging extern const char* nv3_class_names[]; @@ -1192,7 +1191,6 @@ typedef struct nv3_grobj_s uint32_t grobj_3; } nv3_grobj_t; // TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! -#pragma pack(pop) // return packing to whatever it was before this disaster // PIO Subchannel info #define NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE 0x0010 diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index ef5e80d71..84ccf5a15 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -6,7 +6,10 @@ * * This file is part of the 86Box distribution. * - * Shared implementation file for all NVIDIA GPUs (hopefully to be) emulated by 86box. + * The real Nvidia driver. + * Implements components shared by all variants of the Nvidia GPUs (hopefully to be) supported by 86Box. + * + * This driver draws on collaborative work by many people over many years. * * Credit to: * @@ -18,6 +21,7 @@ * - xemu developers https://github.com/xemu-project/xemu * - RivaTV developers https://rivatv.sourceforge.net (esp. https://rivatv.sourceforge.net/stuff/riva128.txt) * - Nvidia for leaking their driver symbols numerous times ;^) https://nvidia.com + * - Vort (Bochs GeForce fork) https://github.com/Vort/Bochs/tree/geforce * - People who prevented me from giving up (various) * * Authors: Connor Hyde / starfrost From ff0eaa7a6993dc1919f8744e1490269173943a94 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 3 Jun 2025 01:30:22 +0100 Subject: [PATCH 197/274] various minor fixes to how classes are defined --- .../86box/nv/classes/vid_nv3_classes.h | 75 ++++++++----------- src/include/86box/nv/vid_nv3.h | 4 +- src/video/nv/nv3/subsystems/nv3_pfifo.c | 12 +-- 3 files changed, 38 insertions(+), 53 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 5c2cc5b8e..e8fed0327 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -294,6 +294,15 @@ typedef struct nv3_color_and_coord_16_s nv3_coord_16_t points; } nv3_color_and_coord_16_t; +/* "UTRI" type triangle */ +typedef struct nv3_utri_s +{ + uint32_t color; // use nv3_color_expanded_t but changed for alignment reasons + nv3_coord_16_t point0; + nv3_coord_16_t point1; + nv3_coord_16_t point2; +} nv3_utri_t; + /* Generic 16-bit clip region */ typedef struct nv3_clip_16_s { @@ -322,35 +331,10 @@ typedef struct nv3_object_class_001 { nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) uint32_t set_notify; - uint8_t set_beta_factor_1d31; // 31:31 (?) value, 30:21 fraction + uint32_t set_beta_factor_1d31; // 31:31 (?) value, 30:21 fraction // Put the rest of it here } nv3_beta_factor_t; -/* Note: This is not used in the class, there are "special" rops that do certain things. So they need to be defined for code readability. It all gets optimised away -by the compiler anyway */ -typedef enum nv3_render_operation_type_e -{ - // Black - nv3_rop_blackness = 0x00, - // dst = !src - nv3_rop_dstinvert = 0x55, - // pattern invert - nv3_rop_patinvert = 0x5A, - // src ^ dst - nv3_rop_xor = 0x66, - // src & dst - nv3_rop_srcand = 0x88, - // dst = src (?) - nv3_rop_dstcopy = 0xAA, - // src = dst (?) - nv3_rop_srccopy = 0xCC, - // paint source - nv3_rop_srcpaint = 0xEE, - // pattern copy - nv3_rop_patcopy = 0xF0, - // White - nv3_rop_whiteness = 0xFF, -} nv3_render_operation_type; /* Object class 0x02 (real hardware) 0x14/0x43 (drivers) @@ -359,9 +343,9 @@ typedef enum nv3_render_operation_type_e */ typedef struct nv3_object_class_002 { - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint8_t rop; // ROP3 (ID = ????????) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint32_t set_notify; // Set notifier + uint8_t rop; // ROP3 (ID = ????????) } nv3_render_operation_t; /* @@ -372,9 +356,9 @@ typedef struct nv3_object_class_002 */ typedef struct nv3_object_class_003 { - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint8_t color; // ROP3 (ID = ????????) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint32_t set_notify; // Set notifier + uint32_t color; // ROP3 (ID = ????????) } nv3_chroma_key_t; /* @@ -385,9 +369,9 @@ typedef struct nv3_object_class_003 */ typedef struct nv3_object_class_004 { - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint8_t color; // ROP3 (ID = ????????) + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint32_t set_notify; // Set notifier + uint32_t color; // Plane mask } nv3_plane_mask_t; /* @@ -533,9 +517,9 @@ typedef struct nv3_object_class_00A */ typedef struct nv3_object_class_00B { - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - nv3_color_expanded_t color; // argb? + nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) + uint32_t set_notify; // Set notifier + nv3_color_expanded_t color; // argb? // The points of the triangle. nv3_coord_16_t points[3]; @@ -544,13 +528,14 @@ typedef struct nv3_object_class_00B uint32_t y0; uint32_t x1; uint32_t y1; - uint32_t y2; - uint32_t x2; + uint32_t x2; + uint32_t y2; - nv3_coord_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? - nv3_coord_32_t mesh32[16]; - nv3_color_and_coord_16_t ctriangle[3]; // Triangle with colour - nv3_color_and_coord_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours + nv3_coord_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? + nv3_coord_32_t mesh32[16]; // Mesh with 32-bit format + nv3_utri_t ctriangle[8]; // Triangles with colour + nv3_color_and_coord_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours + } nv3_triangle_t; /* @@ -834,13 +819,13 @@ typedef enum nv3_d3d5_texture_size_e nv3_d3d5_texture_size_128x128 = 7, - // Highest size supported natively by hardware? nv3_d3d5_texture_size_256x256 = 8, nv3_d3d5_texture_size_512x512 = 9, nv3_d3d5_texture_size_1024x1024 = 10, + // Kind of infeasible considering hardware VRAM size limitations nv3_d3d5_texture_size_2048x2048 = 11, diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index e91afb5c9..c89f2e9b2 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -269,7 +269,7 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_PUSH0 0x3000 +#define NV3_PFIFO_CACHE0_PUSH_ENABLED 0x3000 #define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 @@ -291,7 +291,7 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PFIFO_CACHE0_METHOD_END 0x3200 #define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 #define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 -#define NV3_PFIFO_CACHE1_PUSH0 0x3200 +#define NV3_PFIFO_CACHE1_PUSH_ENABLED 0x3200 #define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 204d3f29c..9dc66fc2e 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -48,8 +48,8 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CACHE0_PULLER_CTX_STATE, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CTX_STATE, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE0_PUSH0, "PFIFO - Cache0 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE1_PUSH0, "PFIFO - Cache1 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE0_ENABLED, "PFIFO - Cache0 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_ENABLED, "PFIFO - Cache1 Access", NULL, NULL, }, { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, @@ -160,10 +160,10 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; break; /* Does this automatically push? */ - case NV3_PFIFO_CACHE0_PUSH0: + case NV3_PFIFO_CACHE0_ENABLED: ret = nv3->pfifo.cache0_settings.push0; break; - case NV3_PFIFO_CACHE1_PUSH0: + case NV3_PFIFO_CACHE1_ENABLED: ret = nv3->pfifo.cache1_settings.push0; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: @@ -509,10 +509,10 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: nv3->pfifo.cache1_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; - case NV3_PFIFO_CACHE0_PUSH0: + case NV3_PFIFO_CACHE0_ENABLED: nv3->pfifo.cache0_settings.push0 = val; break; - case NV3_PFIFO_CACHE1_PUSH0: + case NV3_PFIFO_CACHE1_ENABLED: nv3->pfifo.cache1_settings.push0 = val; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: From 49da2e606c28a7f2d49ea95a3907d3b2841243b1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 3 Jun 2025 02:40:23 +0100 Subject: [PATCH 198/274] fix compile --- src/video/nv/nv3/subsystems/nv3_pfifo.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 9dc66fc2e..7cd7f71a9 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -48,8 +48,8 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CACHE0_PULLER_CTX_STATE, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CTX_STATE, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE0_ENABLED, "PFIFO - Cache0 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE1_ENABLED, "PFIFO - Cache1 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE0_PUSH_ENABLED, "PFIFO - Cache0 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH_ENABLED, "PFIFO - Cache1 Access", NULL, NULL, }, { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 Push Channel ID", NULL, NULL, }, { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, @@ -160,10 +160,10 @@ uint32_t nv3_pfifo_read(uint32_t address) ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; break; /* Does this automatically push? */ - case NV3_PFIFO_CACHE0_ENABLED: + case NV3_PFIFO_CACHE0_PUSH_ENABLED: ret = nv3->pfifo.cache0_settings.push0; break; - case NV3_PFIFO_CACHE1_ENABLED: + case NV3_PFIFO_CACHE1_PUSH_ENABLED: ret = nv3->pfifo.cache1_settings.push0; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: @@ -509,10 +509,10 @@ void nv3_pfifo_write(uint32_t address, uint32_t val) case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: nv3->pfifo.cache1_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; break; - case NV3_PFIFO_CACHE0_ENABLED: + case NV3_PFIFO_CACHE0_PUSH_ENABLED: nv3->pfifo.cache0_settings.push0 = val; break; - case NV3_PFIFO_CACHE1_ENABLED: + case NV3_PFIFO_CACHE1_PUSH_ENABLED: nv3->pfifo.cache1_settings.push0 = val; break; case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: From 2508b2e86b16fbf984fe141a95a21dab6b0e5011 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 22 Jun 2025 14:10:15 +0100 Subject: [PATCH 199/274] redesign gpu visual debugging windows --- src/qt/CMakeLists.txt | 4 + src/qt/qt_gpudebug_visualnv.cpp | 54 ++++++++ src/qt/qt_gpudebug_visualnv.hpp | 40 ++++++ src/qt/qt_gpudebug_visualnv.ui | 154 ++++++++++++++++++++++ src/qt/qt_gpudebug_vram.ui | 20 +-- src/qt/qt_mainwindow.cpp | 11 ++ src/qt/qt_mainwindow.hpp | 3 +- src/qt/qt_mainwindow.ui | 2 +- src/video/nv/nv3/render/nv3_render_blit.c | 13 +- src/video/vid_mda.c | 6 +- 10 files changed, 285 insertions(+), 22 deletions(-) create mode 100644 src/qt/qt_gpudebug_visualnv.cpp create mode 100644 src/qt/qt_gpudebug_visualnv.hpp create mode 100644 src/qt/qt_gpudebug_visualnv.ui diff --git a/src/qt/CMakeLists.txt b/src/qt/CMakeLists.txt index 64bcd01e5..5be854154 100644 --- a/src/qt/CMakeLists.txt +++ b/src/qt/CMakeLists.txt @@ -157,6 +157,10 @@ add_library(ui STATIC qt_gpudebug_vram.hpp qt_gpudebug_vram.ui + qt_gpudebug_visualnv.cpp + qt_gpudebug_visualnv.hpp + qt_gpudebug_visualnv.ui + qt_harddrive_common.cpp qt_harddrive_common.hpp qt_models_common.cpp diff --git a/src/qt/qt_gpudebug_visualnv.cpp b/src/qt/qt_gpudebug_visualnv.cpp new file mode 100644 index 000000000..4c0a52dde --- /dev/null +++ b/src/qt/qt_gpudebug_visualnv.cpp @@ -0,0 +1,54 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * GPU Debugging Tools - VRAM Viewer implementation + * + * + * + * Authors: starfrost + * + * Copyright 2025 starfrost + */ + +/* C++ includes */ +#include +#include + + +/* Qt includes*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ui_qt_gpudebug_visualnv.h" + +/* 86Box core includes */ +extern "C" +{ + +} + +VisualNVDialog::VisualNVDialog(QWidget *parent) + : QDialog(parent) + , ui(new Ui::VisualNVDialog) +{ + ui->setupUi(this); +} + +VisualNVDialog::~VisualNVDialog() +{ + +} \ No newline at end of file diff --git a/src/qt/qt_gpudebug_visualnv.hpp b/src/qt/qt_gpudebug_visualnv.hpp new file mode 100644 index 000000000..175d1c28a --- /dev/null +++ b/src/qt/qt_gpudebug_visualnv.hpp @@ -0,0 +1,40 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * GPU Debugging Tools - VRAM Viewer headers + * + * + * + * Authors: starfrost + * + * Copyright 2025 starfrost + */ + + +#pragma once + +#include + +namespace Ui +{ + class VisualNVDialog; +} + +class VisualNVDialog : public QDialog +{ + Q_OBJECT + + public: + explicit VisualNVDialog(QWidget *parent = nullptr); + ~VisualNVDialog(); + protected: + private: + Ui::VisualNVDialog* ui; + + +}; \ No newline at end of file diff --git a/src/qt/qt_gpudebug_visualnv.ui b/src/qt/qt_gpudebug_visualnv.ui new file mode 100644 index 000000000..e103ff03e --- /dev/null +++ b/src/qt/qt_gpudebug_visualnv.ui @@ -0,0 +1,154 @@ + + + VisualNVDialog + + + + 0 + 0 + 600 + 350 + + + + + 0 + 0 + + + + + 600 + 350 + + + + + 600 + 350 + + + + Nvidia GPU Realtime Debugger + + + + + + + + 10 + 0 + 201 + 171 + + + + PFIFO State + + + + + + 220 + 0 + 361 + 171 + + + + PGRAPH State + + + + + + 10 + 180 + 571 + 141 + + + + VRAM Control + + + + + 160 + 30 + 104 + 21 + + + + + + + 10 + 30 + 151 + 16 + + + + <html><head/><body><p>VRAM Visual Aperture Start</p></body></html> + + + + + + 420 + 30 + 91 + 16 + + + + <html><head/><body><p>FB Start Address:</p></body></html> + + + + + + 510 + 30 + 49 + 16 + + + + <html><head/><body><p><span style=" font-weight:700;">PLACEHOLDER 9000</span></p></body></html> + + + + + + 160 + 60 + 104 + 21 + + + + + + + 10 + 60 + 151 + 16 + + + + <html><head/><body><p>Pixel Depth</p></body></html> + + + + + + + + + + diff --git a/src/qt/qt_gpudebug_vram.ui b/src/qt/qt_gpudebug_vram.ui index 12c64e3b4..8118f0613 100644 --- a/src/qt/qt_gpudebug_vram.ui +++ b/src/qt/qt_gpudebug_vram.ui @@ -32,16 +32,6 @@ VRAM Viewer - - - - VRAM - - - Qt::AlignmentFlag::AlignLeading|Qt::AlignmentFlag::AlignLeft|Qt::AlignmentFlag::AlignTop - - - @@ -52,6 +42,16 @@ + + + + VRAM + + + Qt::AlignmentFlag::AlignLeading|Qt::AlignmentFlag::AlignLeft|Qt::AlignmentFlag::AlignTop + + + diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index eb238051f..7a9132031 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -24,6 +24,7 @@ #include "qt_mainwindow.hpp" #include "qt_gpudebug_vram.hpp" +#include "qt_gpudebug_visualnv.hpp" #include "ui_qt_mainwindow.h" #include "qt_specifydimensions.h" @@ -2326,4 +2327,14 @@ void MainWindow::on_actionDebug_GPUDebug_VRAM_triggered() debugVramDialog.setWindowFlag(Qt::WindowTitleHint, true); debugVramDialog.setWindowFlag(Qt::WindowSystemMenuHint, false); debugVramDialog.exec(); +} + + +void MainWindow::on_actionDebug_GPUDebug_VisualNv_triggered() +{ + VisualNVDialog visualNvDialog(this); + visualNvDialog.setWindowFlag(Qt::CustomizeWindowHint, true); + visualNvDialog.setWindowFlag(Qt::WindowTitleHint, true); + visualNvDialog.setWindowFlag(Qt::WindowSystemMenuHint, false); + visualNvDialog.exec(); } \ No newline at end of file diff --git a/src/qt/qt_mainwindow.hpp b/src/qt/qt_mainwindow.hpp index 5cda49fa8..c71dd1ffd 100644 --- a/src/qt/qt_mainwindow.hpp +++ b/src/qt/qt_mainwindow.hpp @@ -128,7 +128,8 @@ private slots: void on_actionEnable_Discord_integration_triggered(bool checked); void on_actionRenderer_options_triggered(); void on_actionDebug_GPUDebug_VRAM_triggered(); - + void on_actionDebug_GPUDebug_VisualNv_triggered(); + void refreshMediaMenu(); void showMessage_(int flags, const QString &header, const QString &message, bool richText, std::atomic_bool* done = nullptr); void getTitle_(wchar_t *title); diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index 2861b65be..762361ae1 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -914,7 +914,7 @@ - GPU Debug - NV3 Visual Debugger + GPU Realtime Debugger (NVIDIA ONLY) diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 596d7b7a1..9bf87ec6d 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -134,9 +134,8 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; - - nv3_coord_16_t old_position = nv3->pgraph.blit.point_in; - nv3_coord_16_t new_position = nv3->pgraph.blit.point_out; + nv3_coord_16_t in_position = nv3->pgraph.blit.point_in; + nv3_coord_16_t out_position = nv3->pgraph.blit.point_out; /* Coordinates for copying an entire line at a time */ uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.x; @@ -159,10 +158,10 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) { buf_position = (nv3->pgraph.blit.size.x * y); /* shouldn't matter in non-wtf mode */ - vram_position = nv3_render_get_vram_address_for_buffer(old_position, dst_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(in_position, src_buffer); memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); - old_position.y++; + in_position.y++; /* 32bit buffer */ } @@ -170,9 +169,9 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) { buf_position = (nv3->pgraph.blit.size.x * y); - vram_position = nv3_render_get_vram_address_for_buffer(new_position, src_buffer); + vram_position = nv3_render_get_vram_address_for_buffer(out_position, dst_buffer); memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); - new_position.y++; + out_position.y++; } } \ No newline at end of file diff --git a/src/video/vid_mda.c b/src/video/vid_mda.c index 7b6e54806..63bb2df07 100644 --- a/src/video/vid_mda.c +++ b/src/video/vid_mda.c @@ -317,7 +317,7 @@ mda_standalone_init(UNUSED(const device_t *info)) mda->vram = malloc(0x1000); - switch(device_get_config_int("font")) { + switch (device_get_config_int("font")) { case 0: loadfont(FONT_IBM_MDA_437_PATH, 0); break; @@ -375,7 +375,7 @@ mda_speed_changed(void *priv) } static const device_config_t mda_config[] = { - // clang-format off + // clang-format off { .name = "rgb_type", .description = "Display type", @@ -411,7 +411,7 @@ static const device_config_t mda_config[] = { .bios = { { 0 } } }, { .name = "", .description = "", .type = CONFIG_END } - // clang-format on + // clang-format on }; const device_t mda_device = { From d5a9411fe732fabe2dc2731b8715506db9d68ad4 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 22 Jun 2025 15:59:44 +0100 Subject: [PATCH 200/274] Implement hardware cursor support (9x now displays mouse cursor) --- src/include/86box/nv/vid_nv3.h | 11 ++- src/qt/qt_gpudebug_visualnv.ui | 31 ++++++--- src/video/nv/nv3/nv3_core.c | 92 +++++++++++++++---------- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- 4 files changed, 83 insertions(+), 53 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index c89f2e9b2..632ee01fa 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -463,13 +463,6 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable #define NV3_PME_END 0x200FFF -// THIS IS NOT A REAL REGISTER. -// This is so my software e.g. nvplayground can determine if the software is being run in an emulator on a real RIVA 128. -// This register should have some sort of open bus, garbage or 00/FF on a real NV3/NV3T but have a string. -#define NV3_EMULATED_MARKER_START 0x269420 - -#define NV3_EMULATED_MARKER 0x0D15EA5E - #define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part // PGRAPH Core @@ -800,6 +793,10 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_RAMIN_RAMRM_START 0x1C02000 #define NV3_RAMIN_RAMRM_END 0x1C02FFF +// I'm not sure if this can be moved. +// 4K of "PRAM" is listed at 0x6000. +#define NV3_RAMIN_OFFSET_CURSOR 0x6000 + #define NV3_RAMIN_END 0x1FFFFFF // not done diff --git a/src/qt/qt_gpudebug_visualnv.ui b/src/qt/qt_gpudebug_visualnv.ui index e103ff03e..313df859d 100644 --- a/src/qt/qt_gpudebug_visualnv.ui +++ b/src/qt/qt_gpudebug_visualnv.ui @@ -6,7 +6,7 @@ 0 0 - 600 + 620 350 @@ -18,13 +18,13 @@ - 600 + 620 350 - 600 + 620 350 @@ -88,7 +88,7 @@ 10 30 151 - 16 + 21 @@ -98,7 +98,7 @@ - 420 + 390 30 91 16 @@ -111,14 +111,14 @@ - 510 + 480 30 - 49 + 81 16 - <html><head/><body><p><span style=" font-weight:700;">PLACEHOLDER 9000</span></p></body></html> + <html><head/><body><p><span style=" font-weight:700;">PLACEHOLDER</span></p></body></html> @@ -137,13 +137,26 @@ 10 60 151 - 16 + 21 <html><head/><body><p>Pixel Depth</p></body></html> + + + + 10 + 110 + 231 + 24 + + + + Load nvplay savestate from real hardware + + diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 21810386e..39aa0178d 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -866,9 +866,14 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) if ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_CURSOR_START] >> NV3_CRTC_REGISTER_CURSOR_START_DISABLED) & 0x01) return; - // On windows, this shows up using NV_IMAGE_IN_MEMORY. + // NT GDI drivers: Load cursor using NV_IMAGE_FROM_MEMORY ("NV3LCD") + // 9x GDI drivers: Use H/W cursor in RAMIN + // Do we need to emulate it? - uint32_t vram_cursor_base = nv3->pramdac.cursor_address; + + // THIS IS CORRECT. BUT HOW DO WE FIND IT? + uint32_t ramin_cursor_position = NV3_RAMIN_OFFSET_CURSOR; + /* let's just assume buffer 0 here...that code needs to be totally rewritten*/ nv3_coord_16_t start_position = nv3->pramdac.cursor_start; @@ -890,49 +895,64 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline) We have to get a 32x32, "A"1R5G5B5-format cursor out of video memory. The alpha bit actually means - XOR with display pixel if 0, replace if 1 - Technically these are expanded to RGB10, but I don't see why this needs to happen. And our pipeline isn't set up for it anyway. + These are expanded to RGB10 only if they are XORed. We don't do this (we don't really need to + there is no grobj specified here so special casing + would be needed) so we just xor it with the current pixel format */ for (int32_t y = 0; y < NV3_PRAMDAC_CURSOR_SIZE_Y; y++) { for (int32_t x = 0; x < NV3_PRAMDAC_CURSOR_SIZE_X; x++) { - uint16_t current_pixel = vram_16[vram_cursor_base << 1]; - bool replace_bit = (current_pixel & 0x8000); - - switch (nv3->nvbase.svga.bpp) + uint16_t current_pixel = nv3_ramin_read16(ramin_cursor_position, nv3); + + // 0000 = transparent, so skip drawing + if (current_pixel) { - /* this is indexed colour but... lol */ - case 8: - if (replace_bit) - { - uint8_t final = current_pixel ^ nv3->nvbase.svga.vram[final_position]; - nv3->nvbase.svga.vram[final_position] = final; - } - else // just override - nv3->nvbase.svga.vram[final_position] = current_pixel; - case 15 ... 16: // easy case (our cursor is 15bpp format) - uint32_t index_16 = final_position >> 1; - if (replace_bit) - { - uint16_t final = current_pixel ^ vram_16[index_16]; - vram_16[index_16] = final; - } - else // just override - vram_16[index_16] = current_pixel; - case 32: - uint32_t index_32 = final_position >> 2; - if (replace_bit) - { - uint16_t final = current_pixel ^ vram_32[index_32]; - vram_32[index_32] = final; - } - else // just override - vram_32[index_32] = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here - break; + bool replace_bit = (current_pixel & 0x8000); + + // use buffer 0 BPIXEL + uint32_t bpixel_format = (nv3->pgraph.bpixel[0]) & 0x03; + + switch (bpixel_format) + { + case bpixel_fmt_8bit: + if (replace_bit) + nv3->nvbase.svga.vram[final_position] = current_pixel; + else //xor + { + // not sure what to do here. we'd have to search through the palette to find the closest possible colour. + uint8_t final = current_pixel ^ nv3->nvbase.svga.vram[final_position]; + nv3->nvbase.svga.vram[final_position] = final; + } + case bpixel_fmt_16bit: // easy case (our cursor is 15bpp format) + uint32_t index_16 = final_position >> 1; + + if (replace_bit) // just replace + vram_16[index_16] = current_pixel; + else // xor + { + current_pixel &= ~0x8000; // mask off the xor bit + uint16_t final = current_pixel ^ vram_16[index_16]; + vram_16[index_16] = final; + } + case bpixel_fmt_32bit: + uint32_t index_32 = final_position >> 2; + + if (replace_bit) // just replace + vram_32[index_32] = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here + else //xor + { + current_pixel &= ~0x8000; // mask off the xor bit + uint32_t current_pixel_32 = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here + + uint32_t final = current_pixel_32 ^ vram_32[index_32]; + vram_32[index_32] = final; + } + break; + } } // increment vram position - vram_cursor_base += 2; + ramin_cursor_position += 2; // go switch (nv3->nvbase.svga.bpp) diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 7cd7f71a9..542aa26fa 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -739,7 +739,7 @@ void nv3_pfifo_cache0_pull(void) uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries? uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; - // Tell the CPU if we found a software method + // Tell the CPU if we found a software method and turn off cache pulling if (!(current_context & 0x800000)) { nv_log("The object in CACHE0 is a software object\n"); From 305d305173a7b041fca1b76e6d98470d6ac2c7c6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 22 Jun 2025 17:34:54 +0100 Subject: [PATCH 201/274] Basic AGP support. Card is now detected, but can't get to desktop --- src/include/86box/nv/vid_nv.h | 1 + src/include/86box/nv/vid_nv3.h | 59 +++++++++++++++++ src/video/nv/nv3/nv3_core.c | 80 ++++++++++++++++++++++- src/video/nv/nv3/render/nv3_render_blit.c | 11 ++-- 4 files changed, 145 insertions(+), 6 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 84ccf5a15..8a8e2985c 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -131,6 +131,7 @@ typedef struct nv_base_s void* i2c; // I2C for monitor EDID void* ddc; // Display Data Channel for EDID uint32_t last_buffer_address; // Last buffer address. + bool agp_enabled; // AGP Enabled (for debugging) } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 632ee01fa..80307a5ea 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -140,6 +140,8 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PCI_CFG_VBIOS_BASE_L 0x32 #define NV3_PCI_CFG_VBIOS_BASE_H 0x33 +#define NV3_AGP_CAPABILITIES_POINTER 0x34 + #define NV3_PCI_CFG_INT_LINE 0x3C #define NV3_PCI_CFG_INT_PIN 0x3D @@ -151,6 +153,63 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PCI_CFG_MAX_LATENCY 0x3F #define NV3_PCI_CFG_MAX_LATENCY_DEFAULT 0x01 +// +// AGP configuration +// + +#define NV3_AGP_START 0x44 + +// stupid stupid pci system +#define NV3_AGP_CAPABILITIES_START 0x44 +#define NV3_AGP_CAPABILITIES_CAP_ID 0x44 +#define NV3_AGP_CAPABILITIES_CAP_ID_AGP 0x02 // "AGP" +#define NV3_AGP_CAPABILITIES_NEXT_PTR 0x45 +#define NV3_AGP_CAPABILITIES_AGP_VERSION 0x46 +#define NV3_AGP_CAPABILITIES_AGP_VERSION_MINOR 0 +#define NV3_AGP_CAPABILITIES_AGP_VERSION_MAJOR 4 +#define NV3_AGP_CAPABILITIES_H 0x47 + +#define NV3_AGP_STATUS_RATE 0x48 +#define NV3_AGP_STATUS_RATE_1X_SUPPORTED 0x1 +#define NV3_AGP_STATUS_RATE_2X_SUPPORTED 0x2 + +#define NV3_AGP_STATUS_BYTE1 0x49 +#define NV3_AGP_STATUS_BYTE1_SBA 1 +#define NV3_AGP_STATUS_SBA_SUPPORTED 0x0 +#define NV3_AGP_STATUS_SBA_UNSUPPORTED 0x1 +#define NV3_AGP_STATUS_MAX_REQUESTS 0x4B +#define NV3_AGP_STATUS_MAX_REQUESTS_AMOUNT 4 + +#define NV3_AGP_COMMAND 0x4C +#define NV3_AGP_COMMAND_DATA_RATE 0 +#define NV3_AGP_COMMAND_DATA_RATE_1X 0x1 +#define NV3_AGP_COMMAND_DATA_RATE_2X 0x2 +#define NV3_AGP_COMMAND_BYTE1 0x4D +#define NV3_AGP_COMMAND_BYTE1_ENABLE 0 +#define NV3_AGP_COMMAND_BYTE1_ENABLE_DISABLED 0x0 +#define NV3_AGP_COMMAND_BYTE1_ENABLE_ENABLED 0x1 +#define NV3_AGP_COMMAND_SBA_ENABLE 1 +#define NV3_AGP_COMMAND_SBA_ENABLE_DISABLED 0x0 +#define NV3_AGP_COMMAND_SBA_ENABLE_ENABLED 0x1 +#define NV3_AGP_COMMAND_REQUEST_DEPTH 0x4F + +#define NV3_AGP_END 0x4F + +// +// ACPI (NV3T only) +// TODO: IMPLEMENT THIS!!!!!! +// +#define NV3_POWER_CAP_ID 0x60 +#define NV3_POWER_NEXT_PTR 0x61 +#define NV3_POWER_VERSION 0x62 + +// "The RIVA128ZX does not physically change its power consumption when +// POWER_STATE is modified." +#define NV3_POWER_STATE 0x64 + +#define NV3_POWER_STATE_D0 0x0 +#define NV3_POWER_STATE_D3HOT 0x3 + // GPU Subsystems // These most likely correspond to functional blocks in the original design diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 39aa0178d..e97c5fa1f 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -235,6 +235,46 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) nv3_mmio_arbitrate_write(addr, val); } +// AGP read function +uint8_t nv3_agp_read(int32_t func, int32_t addr) +{ + uint8_t ret = 0x00; + + switch (addr) + { + case NV3_AGP_CAPABILITIES_CAP_ID: + ret = NV3_AGP_CAPABILITIES_CAP_ID_AGP; // AGP capable device + break; + case NV3_AGP_CAPABILITIES_NEXT_PTR: // Always off + ret = 0x00; + case NV3_AGP_CAPABILITIES_AGP_VERSION: + ret = (0x1 << NV3_AGP_CAPABILITIES_AGP_VERSION_MAJOR) | NV3_AGP_CAPABILITIES_AGP_VERSION_MINOR; + break; + case NV3_AGP_STATUS_RATE: + // NV3T = AGP 2X, NV3 = AGP 1X + if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) + ret = NV3_AGP_STATUS_RATE_1X_SUPPORTED | NV3_AGP_STATUS_RATE_2X_SUPPORTED; + else + ret = NV3_AGP_STATUS_RATE_1X_SUPPORTED; + break; + case NV3_AGP_STATUS_BYTE1: + ret = 0x00; // SBA not supported + break; + case NV3_AGP_STATUS_MAX_REQUESTS: + ret = NV3_AGP_STATUS_MAX_REQUESTS_AMOUNT; + break; + // This is also used for SBA but SBA is always off so we can use a bool + case NV3_AGP_COMMAND_BYTE1: + ret = nv3->nvbase.agp_enabled; + break; + default: + ret = nv3->pci_config.pci_regs[addr]; + break; + } + + return ret; +} + // PCI stuff // BAR0 Pointer to MMIO space // BAR1 Pointer to Linear Framebuffer (NV_USER) @@ -332,7 +372,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) case NV3_PCI_CFG_BAR0_L: case NV3_PCI_CFG_BAR1_L: // only bit that matters is bit 3 (prefetch bit) - ret =(NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED << NV3_PCI_CFG_BAR_PREFETCHABLE); + ret = (NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED << NV3_PCI_CFG_BAR_PREFETCHABLE); break; // These registers are hardwired to zero per the datasheet @@ -355,6 +395,13 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) ret = nv3->pci_config.vbios_enabled; break; + case NV3_AGP_CAPABILITIES_POINTER: + if (nv3->nvbase.bus_generation >= nv_bus_agp_1x) + ret = NV3_AGP_CAPABILITIES_START; + else + ret = 0x00; + break; + case NV3_PCI_CFG_INT_LINE: ret = nv3->pci_config.int_line; break; @@ -381,6 +428,15 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) ret = nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)]; break; + case NV3_AGP_START ... NV3_AGP_END: + if (nv3->nvbase.bus_generation < nv_bus_agp_1x) + break; + + ret = nv3_agp_read(func, addr); + + break; + + default: // by default just return pci_config.pci_regs ret = nv3->pci_config.pci_regs[addr]; break; @@ -391,6 +447,20 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) return ret; } +void nv3_agp_write(int32_t func, int32_t addr, uint8_t val) +{ + nv3->pci_config.pci_regs[addr] = val; + + switch (addr) + { + case NV3_AGP_COMMAND_BYTE1: + nv3->nvbase.agp_enabled = val; + break; + default: + break; + } +} + void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) { @@ -489,6 +559,14 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val; break; + case NV3_AGP_START ... NV3_AGP_END: + if (nv3->nvbase.bus_generation < nv_bus_agp_1x) + break; + + nv3_agp_write(func, addr, val); + + break; + default: break; } diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 9bf87ec6d..c1b221648 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -140,12 +140,13 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) /* Coordinates for copying an entire line at a time */ uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.x; - /* Read the old pixel into the line buffer - Assumption: All data is sent in an unpacked format. In the case of an NVIDIA GPU this means that all data is sent 32 bits at a time regardless of if - the actual source data is 32 bits in size or not. For pixel data, the upper bits are left as 0 in 8bpp/16bpp mode. For 86box purposes, the data is written - 8/16 bits at a time. + /* + Read the old pixel into the line buffer + Assumption: All data is sent in an unpacked format. In the case of an NVIDIA GPU this means that all data is sent 32 bits at a time regardless of if + the actual source data is 32 bits in size or not. For pixel data, the upper bits are left as 0 in 8bpp/16bpp mode. For 86box purposes, the data is written + 8/16 bits at a time. - TODO: CHECK FOR PACKED FORMAT!!!!! + TODO: CHECK FOR PACKED FORMAT!!!!! */ if (nv3->nvbase.svga.bpp == 15 From 4e2266e761ed39b6aef0fc11c85ab2493e927127 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 24 Jun 2025 11:46:16 +0100 Subject: [PATCH 202/274] update status.xlsx --- doc/nvidia_notes/status.xlsx | Bin 15953 -> 15945 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx index b73941d31dae703054ddc6f338acef9f0a12bcd4..bfeeb14528f00e6aa6a6f1d9e1f055ab1399947f 100644 GIT binary patch delta 6790 zcmZWuWl$VSw#J>H0|Xs{1s^PUNU-2;!Cit5?t{Az&fxAAG)Qolpg|@$1a}A)Uhdtk zy<7XvkFHbQU$s=9uaERM-x1%s4K!3am^Mrwx{F2w5g_(6vUx_n5FYSFQ`vvLEum*) zsnL`@DPJ^-$fSchzRW1AIRRO-EiF=L#Diy4tKoFroVVTP`1sxJPtPsHVU2iZ(cU7_ zMK_~ze*7{q-SSXOMJLZPlUlUPJ~7Rc@^f}R7ovaC=BexQ+Z^#7D~|^Ad~qCIbkrM3 z!?U<%i1CusH+tu9Sezi~#hAt86 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emulation. --- src/include/86box/nv/vid_nv3.h | 8 ++++---- src/video/CMakeLists.txt | 1 - src/video/nv/nv3/nv3_core.c | 2 +- src/video/nv/nv3/subsystems/nv3_pbus.c | 16 ++++------------ src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- 5 files changed, 10 insertions(+), 19 deletions(-) diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 80307a5ea..96d9d3dd1 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -908,7 +908,7 @@ extern const device_config_t nv3t_config[]; // Confi // These are nvidia, licensed from weitek (25-63) #define NV3_CRTC_REGISTER_RPC0 0x19 // 7:5 - [10:8] of CRTC. 4:0 - [20:16] of 21-bit display buffer address -#define NV3_CRTC_REGISTER_RPC1 0x1A // What does this mean? +#define NV3_CRTC_REGISTER_RPC1 0x1A // bit7=hsync enabled, bit6=vsync enabled, bit4="compatible text", bit2=large screen, bit1=6bit palette width (>1280) #define NV3_CRTC_REGISTER_READ_BANK 0x1D #define NV3_CRTC_REGISTER_WRITE_BANK 0x1E #define NV3_CRTC_REGISTER_FORMAT 0x25 @@ -921,8 +921,8 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_CRTC_REGISTER_HEB 0x2D // HRS most significant bit -#define NV3_CRTC_REGISTER_CURSOR_ADDR0 0x30 // Cursor high -#define NV3_CRTC_REGISTER_CURSOR_ADDR1 0x31 // Cursor low (1:0 = enable) +#define NV3_CRTC_REGISTER_CURSOR_ADDR0 0x30 // Cursor high 21:16 +#define NV3_CRTC_REGISTER_CURSOR_ADDR1 0x31 // Cursor low (1:0 = enable) 15:11 #define NV3_CRTC_REGISTER_PIXELMODE_VGA 0x00 // vga textmode #define NV3_CRTC_REGISTER_PIXELMODE_8BPP 0x01 @@ -1413,7 +1413,7 @@ typedef struct nv3_ptimer_s } nv3_ptimer_t; // Object name is just a uint32_t identifier it doesn't need a struct -// This is howt he cotnext is represented in ramin +// This is how the context is represented in ramin // IN PGRAPH IT IS DIFFERENT! ONLY 5 BITS FOR THE CLASS ID! WHY? typedef struct nv3_ramin_context_s { diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 6f9693e5a..fa6887b50 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -192,7 +192,6 @@ add_library(vid OBJECT # Generic vid_bochs_vbe.c - ) if(G100) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index e97c5fa1f..273582f84 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -585,7 +585,7 @@ void nv3_recalc_timings(svga_t* svga) nv3_t* nv3 = (nv3_t*)svga->priv; uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03; - svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; + svga->memaddr_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; /* Turn off override if we are in VGA mode */ svga->override = !(pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA); diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c index 16934998c..a2e340e85 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus.c @@ -164,13 +164,8 @@ uint8_t nv3_pbus_rma_read(uint16_t addr) ret = nv3_mmio_read8(real_final_address, NULL); else { - // ABOVE CODE IS TEMPORARY UNTIL PNVM EXISTS!!!!! - // would svga->fast work? - nv3->nvbase.svga.chain4 = true; - nv3->nvbase.svga.packed_chain4 = true; - ret = svga_read_linear((real_final_address - NV3_MMIO_SIZE) & (nv3->nvbase.svga.vram_max - 1), &nv3->nvbase.svga); - nv3->nvbase.svga.chain4 = false; - nv3->nvbase.svga.packed_chain4 = false; + /* Do we need to read RAMIN here? */ + ret = nv3->nvbase.svga.vram[real_final_address - NV3_MMIO_SIZE] & (nv3->nvbase.svga.vram_max - 1); } // log current location for vbios RE @@ -246,11 +241,8 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val) nv3_mmio_write32(nv3->pbus.rma.addr, nv3->pbus.rma.data, NULL); else // failsafe code, i don't think you will ever write outside of VRAM? { - nv3->nvbase.svga.chain4 = true; - nv3->nvbase.svga.packed_chain4 = true; - svga_writel_linear((nv3->pbus.rma.addr - NV3_MMIO_SIZE) & (nv3->nvbase.svga.vram_max - 1), nv3->pbus.rma.data, &nv3->nvbase.svga); - nv3->nvbase.svga.chain4 = false; - nv3->nvbase.svga.packed_chain4 = false; + uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; + vram_32[(nv3->pbus.rma.addr - NV3_MMIO_SIZE) >> 2] = nv3->pbus.rma.data; } diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 4cd6d10c3..59e3dcdbc 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -202,7 +202,7 @@ void nv3_pfifo_interrupt(uint32_t id, bool fire_now) /* RAMIN access arbitration functions -Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) (RAMAU?) +Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) unused audio memory (RAMAU?) and generic RAMIN Takes a pointer to a result integer. This is because we need to check its result in our normal write function. From 76a83d600197f140f424c94c3fde8ef1776f6476 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 4 Jul 2025 21:55:58 +0100 Subject: [PATCH 204/274] *manually* fix cmakelists conflict because stupid github won't let me reverse-merge fixes?? --- CMakeLists.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 504a563e3..2f654497d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -137,6 +137,11 @@ option(GDBSTUB "Enable GDB stub server for debugging" option(DEV_BRANCH "Development branch" OFF) option(DISCORD "Discord Rich Presence support" ON) option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) +# Remove when merged, should just be -D +option(NV_LOG "NVidia RIVA 128 debug logging" ON) +option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" OFF) +option(LIBASAN "Enable compilation with the addresss sanitizer" OFF) + # Remove when merged, should just be -D option(NV_LOG "NVidia RIVA 128 debug logging" ON) option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging" OFF) From ebea107e820ef7aa93738c30ec44d9b1625182ec Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Fri, 4 Jul 2025 23:54:39 +0100 Subject: [PATCH 205/274] Remove nvidia debugging option if not an nvidia card --- src/machine/machine_table.c | 1 + src/qt/qt_gpudebug_visualnv.cpp | 3 ++ src/qt/qt_gpudebug_vram.ui | 33 ++++++---------------- src/qt/qt_mainwindow.cpp | 50 ++++++++++++++++++++++++--------- src/qt/qt_mainwindow.hpp | 2 ++ 5 files changed, 50 insertions(+), 39 deletions(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 87dd38786..98619452c 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -16,6 +16,7 @@ * Copyright 2017-2025 Fred N. van Kempen. * Copyright 2025 Jasmine Iwanek. */ +#include #include #include #include diff --git a/src/qt/qt_gpudebug_visualnv.cpp b/src/qt/qt_gpudebug_visualnv.cpp index 4c0a52dde..42f108730 100644 --- a/src/qt/qt_gpudebug_visualnv.cpp +++ b/src/qt/qt_gpudebug_visualnv.cpp @@ -35,6 +35,9 @@ #include #include "ui_qt_gpudebug_visualnv.h" +/* NOTE: DO NOT REMOVE */ +#include <86box/nv/vid_nv3.h> + /* 86Box core includes */ extern "C" { diff --git a/src/qt/qt_gpudebug_vram.ui b/src/qt/qt_gpudebug_vram.ui index 8118f0613..a92a60306 100644 --- a/src/qt/qt_gpudebug_vram.ui +++ b/src/qt/qt_gpudebug_vram.ui @@ -6,8 +6,8 @@ 0 0 - 421 - 269 + 600 + 400 @@ -18,39 +18,22 @@ - 421 - 269 + 600 + 400 - 421 - 269 + 600 + 400 VRAM Viewer - - - - TextLabel - - - Qt::AlignmentFlag::AlignBottom|Qt::AlignmentFlag::AlignLeading|Qt::AlignmentFlag::AlignLeft - - - - - - - VRAM - - - Qt::AlignmentFlag::AlignLeading|Qt::AlignmentFlag::AlignLeft|Qt::AlignmentFlag::AlignTop - - + + diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index 330cee551..28200afac 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -268,20 +268,7 @@ MainWindow::MainWindow(QWidget *parent) this->setWindowTitle(QString("%1 - %2 %3").arg(vmname, EMU_NAME, EMU_VERSION_FULL)); connect(this, &MainWindow::hardResetCompleted, this, [this]() { - ui->actionMCA_devices->setVisible(machine_has_bus(machine, MACHINE_BUS_MCA)); - num_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); - scroll_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); - caps_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); - /* TODO: Base this on keyboard type instead when that's done. */ - kana_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD) && - machine_has_flags(machine, MACHINE_AX)); - while (QApplication::overrideCursor()) - QApplication::restoreOverrideCursor(); -#ifdef USE_WACOM - ui->menuTablet_tool->menuAction()->setVisible(mouse_input_mode >= 1); -#else - ui->menuTablet_tool->menuAction()->setVisible(false); -#endif + onHardResetCompleted(); }); connect(this, &MainWindow::showMessageForNonQtThread, this, &MainWindow::showMessage_, Qt::QueuedConnection); @@ -798,6 +785,41 @@ MainWindow::MainWindow(QWidget *parent) updateShortcuts(); } +void MainWindow::onHardResetCompleted() +{ + ui->actionMCA_devices->setVisible(machine_has_bus(machine, MACHINE_BUS_MCA)); + num_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); + scroll_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); + caps_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); + /* TODO: Base this on keyboard type instead when that's done. */ + kana_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD) && + machine_has_flags(machine, MACHINE_AX)); + while (QApplication::overrideCursor()) + QApplication::restoreOverrideCursor(); +#ifdef USE_WACOM + ui->menuTablet_tool->menuAction()->setVisible(mouse_input_mode >= 1); +#else + ui->menuTablet_tool->menuAction()->setVisible(false); +#endif + +#ifdef ENABLE_NV_LOG + /* + THIS CODE SUCKS AND THIS DESIGN IS TERRIBLE - EVERYTHING ABOUT IT IS BAD AND WRONG. + ENTIRE DEVICE SUBSYSTEM IDEALLY WOULD BE DECOUPLED FROM UI BUT MEH + */ + + const device_t* vid_device = video_card_getdevice(gfxcard[0]); + + bool is_nv3 = (vid_device == &nv3_device_agp + || vid_device == &nv3_device_pci + || vid_device == &nv3t_device_agp + || vid_device == &nv3t_device_pci); + + ui->actionDebug_GPUDebug_VisualNv->setVisible(is_nv3); +#endif +} + + void MainWindow::closeEvent(QCloseEvent *event) { diff --git a/src/qt/qt_mainwindow.hpp b/src/qt/qt_mainwindow.hpp index 5cf95e7b9..5db957d45 100644 --- a/src/qt/qt_mainwindow.hpp +++ b/src/qt/qt_mainwindow.hpp @@ -70,6 +70,8 @@ signals: public slots: void showSettings(); void hardReset(); + void onHardResetCompleted(); + void togglePause(); void initRendererMonitorSlot(int monitor_index); void destroyRendererMonitorSlot(int monitor_index); From 383a8f468d0957fa6c19bedaa4d85ea2709bfb07 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 5 Jul 2025 00:50:10 +0100 Subject: [PATCH 206/274] Cleanup some unused code + UI test --- .../86box/nv/classes/vid_nv3_classes.h | 7 +----- src/include/86box/nv/vid_nv3.h | 24 ++++--------------- src/qt/qt_gpudebug_visualnv.cpp | 22 +++++++++++++---- src/qt/qt_gpudebug_visualnv.hpp | 3 +++ src/qt/qt_gpudebug_visualnv.ui | 4 ++-- src/video/nv/nv3/nv3_core.c | 4 ++-- 6 files changed, 30 insertions(+), 34 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index e8fed0327..85979dd45 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -14,7 +14,7 @@ * (they are converted to pointers). In the case of NV3, these map directly to the PHYSICAL PGRAPH REGISTERS while sitting in RAMHT!!!!. * * Also, these class IDs don't relate to the internal architecture of the GPU. - * Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of + * Effectively, the NVIDIA drivers are faking shit. There are only 22 classes but the drivers recognise many more and have a different naming scheme. See nv3_object_classes_driver.txt for the list of * classes recognised by the driver. * This is why the Class IDs you see here are not the same as you may see in other places. * @@ -32,11 +32,6 @@ #include #include -// This is slower, but these need to map *****EXACTLY***** to the registers in PGRAPH, -// or everything FUCKS UP -// -// DO NOT REMOVE! DO NOT REMOVE! DO NOT REMOVE! - // CLass names for debugging extern const char* nv3_class_names[]; diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 96d9d3dd1..f103e0fb8 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -935,7 +935,6 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_CRTC_REGISTER_I2C 0x3E #define NV3_CRTC_REGISTER_I2C_GPIO 0x3F -// where the fuck is GDC? #define NV3_CRTC_BANKED_128K_A0000 0x00 #define NV3_CRTC_BANKED_64K_A0000 0x04 #define NV3_CRTC_BANKED_32K_B0000 0x08 @@ -1066,7 +1065,7 @@ typedef struct nv3_pbus_s typedef struct nv3_pfifo_cache_s { - bool push0; // Can we even access this cache? + bool push0; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. uint8_t channel; // The DMA channel ID of this cache. @@ -1180,7 +1179,7 @@ typedef struct nv3_pgraph_context_control_s } nv3_pgraph_context_control_t; /* DMA object context info - Context uploaded from CACHE0/CACH1 by DMA Puller + Context uploaded from CACHE0/CACHE1 by DMA Puller */ typedef struct nv3_pgraph_context_user_s { @@ -1193,7 +1192,7 @@ typedef struct nv3_pgraph_context_user_s bool reserved3 : 1; uint8_t channel : 7; uint8_t reserved2 : 3; - uint8_t class : 5; + uint8_t class_id : 5; uint8_t subchannel : 3; uint16_t reserved : 13; }; @@ -1468,19 +1467,6 @@ typedef enum nv3_ramin_ramro_reason_e } nv3_ramin_ramro_reason; -/* This is a gigantic error handling system */ -typedef struct nv3_ramin_ramro_entry_s -{ - - //todo -} nv3_ramin_ramro_entry_t; - -// Anti-fuckup device -typedef struct nv3_ramin_ramro_s -{ - -} nv3_ramin_ramro_t; - // context for unused channels typedef struct nv3_ramin_ramfc_s { @@ -1533,10 +1519,10 @@ typedef struct nv3_s nv3_pextdev_t pextdev; // Chip configuration nv3_ptimer_t ptimer; // programmable interval timer nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects - nv3_ramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission + // (ramro does not need a struct) nv3_ramin_ramfc_t ramfc; // context for unused channels nv3_ramin_ramau_t ramau; // auxillary weirdnes - nv3_ramin_t pramin; // Ram for INput of DMA objects. Very important! + nv3_ramin_t pramin; // INstance memory for graphics objects. Very important! nv3_pvideo_t pvideo; // Video overlay nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface //more here diff --git a/src/qt/qt_gpudebug_visualnv.cpp b/src/qt/qt_gpudebug_visualnv.cpp index 42f108730..dd56653e5 100644 --- a/src/qt/qt_gpudebug_visualnv.cpp +++ b/src/qt/qt_gpudebug_visualnv.cpp @@ -6,7 +6,7 @@ * * This file is part of the 86Box distribution. * - * GPU Debugging Tools - VRAM Viewer implementation + * GPU Debugging Tools - Visual NV Debugger implementation * * * @@ -35,13 +35,18 @@ #include #include "ui_qt_gpudebug_visualnv.h" -/* NOTE: DO NOT REMOVE */ -#include <86box/nv/vid_nv3.h> - /* 86Box core includes */ extern "C" { - + /* NOTE: DO NOT REMOVE */ + #include <86box/86box.h> + #include <86box/device.h> + #include <86box/mem.h> + #include <86box/pci.h> + #include <86box/rom.h> + #include <86box/video.h> + #include <86box/nv/vid_nv.h> + #include <86box/nv/vid_nv3.h> } VisualNVDialog::VisualNVDialog(QWidget *parent) @@ -49,9 +54,16 @@ VisualNVDialog::VisualNVDialog(QWidget *parent) , ui(new Ui::VisualNVDialog) { ui->setupUi(this); + connect(ui->btnLoadSavestate, &QPushButton::clicked, this, &VisualNVDialog::on_btnLoadSavestate_clicked); } +// VisualNV dialog destructor VisualNVDialog::~VisualNVDialog() { +} + +void VisualNVDialog::on_btnLoadSavestate_clicked() +{ + warning("THIS IS VisualNVDialog::on_btnLoadSavestate_clicked!!!! (throws into hole)"); } \ No newline at end of file diff --git a/src/qt/qt_gpudebug_visualnv.hpp b/src/qt/qt_gpudebug_visualnv.hpp index 175d1c28a..db7d66dc6 100644 --- a/src/qt/qt_gpudebug_visualnv.hpp +++ b/src/qt/qt_gpudebug_visualnv.hpp @@ -32,6 +32,9 @@ class VisualNVDialog : public QDialog public: explicit VisualNVDialog(QWidget *parent = nullptr); ~VisualNVDialog(); + + void on_btnLoadSavestate_clicked(); + protected: private: Ui::VisualNVDialog* ui; diff --git a/src/qt/qt_gpudebug_visualnv.ui b/src/qt/qt_gpudebug_visualnv.ui index 313df859d..5bae3bb19 100644 --- a/src/qt/qt_gpudebug_visualnv.ui +++ b/src/qt/qt_gpudebug_visualnv.ui @@ -1,7 +1,7 @@ VisualNVDialog - + 0 @@ -144,7 +144,7 @@ <html><head/><body><p>Pixel Depth</p></body></html> - + 10 diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 273582f84..146069e7e 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -614,7 +614,7 @@ void nv3_recalc_timings(svga_t* svga) case NV3_CRTC_REGISTER_PIXELMODE_16BPP: /* This is some sketchy shit that is an attempt at an educated guess at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, - this is what's causing it. Possibly fucking up *ReactOS* of all things */ + this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */ if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01) svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; else @@ -710,7 +710,7 @@ uint8_t nv3_svga_read(uint16_t addr, void* priv) ret = nv3->nvbase.svga.crtcreg; break; case NV3_CRTC_REGISTER_WTF: - ret = 0x08; // Required to not freeze in certain situations on v3.xx drivers + ret = 0x08; // Required to not freeze in certain situations on v3.xx drivers. Even though this register doesn't actually exist lol break; case NV3_CRTC_REGISTER_CURRENT: // Support the extended NVIDIA CRTC register range From 9968645f1d77ad3981ca31dfeecdbae6cf13e524 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 15 Jul 2025 16:45:40 +0100 Subject: [PATCH 207/274] Still increment the get address if a software method is found. This might cause slightly more cache errors and FIFO refills, but seems like the correct thing to do. It also prevents endless loops of finding bugs while debugging --- CMakePresets.json | 3 ++- src/include/86box/nv/vid_nv3.h | 3 --- src/video/nv/nv3/nv3_core_arbiter.c | 6 +++--- src/video/nv/nv3/subsystems/nv3_pfifo.c | 20 +++++++++++--------- src/video/nv/nv3/subsystems/nv3_pramin.c | 2 +- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/CMakePresets.json b/CMakePresets.json index 30feab8ab..b2ed64e97 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -36,7 +36,8 @@ "name": "debug", "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug", - "NV_LOG": "ON" + "NV_LOG": "ON", + "NV_LOG_ULTRA": "ON" }, "inherits": "base" }, diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index f103e0fb8..7a3fb0e36 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -951,9 +951,6 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F - - - /* STRUCTURES FOR THE GPU START HERE OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index 7182cc955..e23386cac 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -114,8 +114,8 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); #endif - // I don't know why the real hardware does this. But it does. - return (ret & 1) ? 0x20 : 0x07; + // The real hardware returns a garbage pattern + return 0x00; } return ret; @@ -132,7 +132,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) // Ensure the addresses are dword aligned. - // I don't know why this is needed because writepriv32 is always to dword align, but it crashes if you don't do this. + // I don't know why this is needed because writepriv32 is always dword aligned in Nvidia's drivers, but it crashes if you don't do this. // Exclude the 4bpp/8bpp CLUT for this purpose if (!(address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) address &= 0xFFFFFC; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 542aa26fa..b7b5a7dfb 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -927,7 +927,17 @@ void nv3_pfifo_cache1_pull(void) uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; - // Tell the CPU if we found a software method + + + // start by incrementing + uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1; + + if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX + next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); + else + next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); + + // Tell the CPU if we found a software method //bit23 unset=software //bit23 set=hardware if (!(current_context & 0x800000)) @@ -940,14 +950,6 @@ void nv3_pfifo_cache1_pull(void) return; } - // start by incrementing - uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1; - - if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX - next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); - else - next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); - // Is this needed? nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c index 59e3dcdbc..77e2d1a6a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ b/src/video/nv/nv3/subsystems/nv3_pramin.c @@ -508,7 +508,7 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte nv_log_verbose_only("Context:\n"); nv_log_verbose_only("DMA Channel %d (0-7 valid)\n", context.channel); - nv_log_verbose_only("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); + nv_log_verbose_only("Class ID: 0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); nv_log_verbose_only("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); nv_log_verbose_only("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); #endif From 991511197a53051ba96f3f263d6f9843ca0ac076 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 16 Jul 2025 12:27:55 +0100 Subject: [PATCH 208/274] Make visualnv window not modal and also allow writing to multiple destination buffers --- src/include/86box/nv/vid_nv.h | 7 ++- src/include/86box/nv/vid_nv3.h | 9 ++++ src/qt/qt_gpudebug_visualnv.cpp | 19 +++++++- src/qt/qt_gpudebug_visualnv.hpp | 1 + src/qt/qt_gpudebug_visualnv.ui | 48 ++++++++++++++++++- src/qt/qt_mainwindow.cpp | 24 +++++----- src/qt/qt_mainwindow.hpp | 8 ++++ .../classes/nv3_class_01c_image_in_memory.c | 4 +- src/video/nv/nv3/render/nv3_render_core.c | 47 ++++++++++-------- src/video/nv/nv3/subsystems/nv3_pfifo.c | 2 +- 10 files changed, 130 insertions(+), 39 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 8a8e2985c..655fb3950 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -130,8 +130,13 @@ typedef struct nv_base_s bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times void* i2c; // I2C for monitor EDID void* ddc; // Display Data Channel for EDID - uint32_t last_buffer_address; // Last buffer address. bool agp_enabled; // AGP Enabled (for debugging) + + // + // DEBUG UI STUFF + // + bool debug_dba_enabled; // Debug DBA override + uint32_t debug_dba; // Debug DBA } nv_base_t; #define NV_REG_LIST_END 0xD15EA5E diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 7a3fb0e36..8e3bd87da 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1032,6 +1032,7 @@ typedef struct nv3_pfb_s #define NV3_NOTIFICATION_PAGE_FRAME_ADDRESS 12 // The pageframe to use + // Core notification structure typedef struct nv3_notification_s { @@ -1248,6 +1249,14 @@ typedef enum nv3_pgraph_bpixel_format_e bpixel_fmt_32bit = 3, } nv3_pgraph_bpixel_format; +typedef enum nv3_pgraph_destination_buffer_e +{ + pgraph_dest_buffer0 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED), + pgraph_dest_buffer1 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED), + pgraph_dest_buffer2 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED), + pgraph_dest_buffer3 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED), +} nv3_pgraph_destination_buffer; + // Graphics Subsystem typedef struct nv3_pgraph_s { diff --git a/src/qt/qt_gpudebug_visualnv.cpp b/src/qt/qt_gpudebug_visualnv.cpp index dd56653e5..bbbd6c8ab 100644 --- a/src/qt/qt_gpudebug_visualnv.cpp +++ b/src/qt/qt_gpudebug_visualnv.cpp @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -55,6 +56,7 @@ VisualNVDialog::VisualNVDialog(QWidget *parent) { ui->setupUi(this); connect(ui->btnLoadSavestate, &QPushButton::clicked, this, &VisualNVDialog::on_btnLoadSavestate_clicked); + connect(ui->fbStartAddress, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_fbStartAddress_changed); } // VisualNV dialog destructor @@ -66,4 +68,19 @@ VisualNVDialog::~VisualNVDialog() void VisualNVDialog::on_btnLoadSavestate_clicked() { warning("THIS IS VisualNVDialog::on_btnLoadSavestate_clicked!!!! (throws into hole)"); -} \ No newline at end of file +} + +void VisualNVDialog::on_fbStartAddress_changed() +{ + if (nv3) + { + nv3->nvbase.debug_dba_enabled = true; + + bool ok = true; + + nv3->nvbase.debug_dba = ui->fbStartAddress->toPlainText().toInt(&ok); + + if (!ok) + nv3->nvbase.debug_dba_enabled = false; + } +} diff --git a/src/qt/qt_gpudebug_visualnv.hpp b/src/qt/qt_gpudebug_visualnv.hpp index db7d66dc6..effbff67b 100644 --- a/src/qt/qt_gpudebug_visualnv.hpp +++ b/src/qt/qt_gpudebug_visualnv.hpp @@ -34,6 +34,7 @@ class VisualNVDialog : public QDialog ~VisualNVDialog(); void on_btnLoadSavestate_clicked(); + void on_fbStartAddress_changed(); protected: private: diff --git a/src/qt/qt_gpudebug_visualnv.ui b/src/qt/qt_gpudebug_visualnv.ui index 5bae3bb19..3c7b7d659 100644 --- a/src/qt/qt_gpudebug_visualnv.ui +++ b/src/qt/qt_gpudebug_visualnv.ui @@ -72,7 +72,7 @@ VRAM Control - + 160 @@ -157,6 +157,52 @@ Load nvplay savestate from real hardware + + + + 390 + 60 + 61 + 16 + + + + <html><head/><body><p>BPITCH[0]:</p></body></html> + + + + + + 460 + 60 + 104 + 21 + + + + + + + 460 + 90 + 104 + 21 + + + + + + + 390 + 90 + 61 + 16 + + + + <html><head/><body><p>BPITCH[1]:</p></body></html> + + diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index 28200afac..fd8ccaa47 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -23,9 +23,9 @@ #include #include "qt_mainwindow.hpp" -#include "qt_gpudebug_vram.hpp" -#include "qt_gpudebug_visualnv.hpp" #include "ui_qt_mainwindow.h" +#include "ui_qt_gpudebug_vram.h" +#include "ui_qt_gpudebug_visualnv.h" #include "qt_specifydimensions.h" #include "qt_soundgain.hpp" @@ -2326,19 +2326,19 @@ void MainWindow::on_actionACPI_Shutdown_triggered() void MainWindow::on_actionDebug_GPUDebug_VRAM_triggered() { - GPUDebugVRAMDialog debugVramDialog(this); - debugVramDialog.setWindowFlag(Qt::CustomizeWindowHint, true); - debugVramDialog.setWindowFlag(Qt::WindowTitleHint, true); - debugVramDialog.setWindowFlag(Qt::WindowSystemMenuHint, false); - debugVramDialog.exec(); + debugVramDialog = new GPUDebugVRAMDialog; + debugVramDialog->setWindowFlag(Qt::CustomizeWindowHint, true); + debugVramDialog->setWindowFlag(Qt::WindowTitleHint, true); + debugVramDialog->setWindowFlag(Qt::WindowSystemMenuHint, false); + debugVramDialog->show(); } void MainWindow::on_actionDebug_GPUDebug_VisualNv_triggered() { - VisualNVDialog visualNvDialog(this); - visualNvDialog.setWindowFlag(Qt::CustomizeWindowHint, true); - visualNvDialog.setWindowFlag(Qt::WindowTitleHint, true); - visualNvDialog.setWindowFlag(Qt::WindowSystemMenuHint, false); - visualNvDialog.exec(); + visualNvDialog = new VisualNVDialog; + visualNvDialog->setWindowFlag(Qt::CustomizeWindowHint, true); + visualNvDialog->setWindowFlag(Qt::WindowTitleHint, true); + visualNvDialog->setWindowFlag(Qt::WindowSystemMenuHint, false); + visualNvDialog->show(); } \ No newline at end of file diff --git a/src/qt/qt_mainwindow.hpp b/src/qt/qt_mainwindow.hpp index 5db957d45..8f7d4d53c 100644 --- a/src/qt/qt_mainwindow.hpp +++ b/src/qt/qt_mainwindow.hpp @@ -15,6 +15,10 @@ #include "qt_vmmanager_protocol.hpp" +// NON-modal dialogs +#include "qt_gpudebug_vram.hpp" +#include "qt_gpudebug_visualnv.hpp" + class MediaMenu; class RendererStack; @@ -170,6 +174,10 @@ private slots: private: Ui::MainWindow *ui; + + // NON-modal dialogs - these use ::show() and therefore have to be maintained as objects + GPUDebugVRAMDialog *debugVramDialog; + VisualNVDialog *visualNvDialog; std::unique_ptr status; std::shared_ptr mm; diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index a35135672..eb7f266d2 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -84,9 +84,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv3->pgraph.boffset[src_buffer_id] = param & 0x7FFFFF; else nv3->pgraph.boffset[src_buffer_id] = param & 0x3FFFFF; - - nv3->nvbase.last_buffer_address = nv3->pgraph.boffset[src_buffer_id]; - + nv_log("Method Execution: Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x\n", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); break; case NV3_NVCLASS_CRAP_START ... NV3_NVCLASS_CRAP_END: diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 9611d8349..88c91688b 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -351,25 +351,10 @@ uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj) return vram_32[vram_address]; } -/* Plots a pixel. */ -void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj) +void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj, uint32_t buffer) { - - // PFB_0 is always set to hardcoded "NO_TILING" value of 0x1114. - // It seems, you are meant to - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; - uint32_t dst_buffer = 0; // 5 = just use the source buffer - - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; - - - uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; // maybe y16 too?z - int32_t clip_end_x = nv3->pgraph.clip_start.x + nv3->pgraph.clip_size.x; int32_t clip_end_y = nv3->pgraph.clip_start.y + nv3->pgraph.clip_size.y; @@ -388,7 +373,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t if (!nv3_render_chroma_test(color, grobj)) return; - uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj); + uint32_t pixel_addr_vram = nv3_render_get_vram_address_for_buffer(position, buffer); uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0; uint8_t bit = 0x00; @@ -437,7 +422,7 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t We use the pixel format of the destination buffer to achieve this (thanks frostbite2000) */ - uint32_t destination_format = (nv3->pgraph.bpixel[dst_buffer]) & 0x03; + uint32_t destination_format = (nv3->pgraph.bpixel[buffer]) & 0x03; switch (destination_format) { @@ -496,6 +481,26 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t } } +/* Plots a pixel. */ +void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj) +{ + // PFB_0 is always set to hardcoded "NO_TILING" value of 0x1114. + // It seems, you are meant to use the CRTC + + nv3_pgraph_destination_buffer dst_buffer = (nv3_pgraph_destination_buffer)grobj.grobj_0; + + if (dst_buffer & (pgraph_dest_buffer0)) + nv3_render_write_pixel_to_buffer(position, color, grobj, 0); + if (dst_buffer & (pgraph_dest_buffer1)) + nv3_render_write_pixel_to_buffer(position, color, grobj, 1); + if (dst_buffer & (pgraph_dest_buffer2)) + nv3_render_write_pixel_to_buffer(position, color, grobj, 2); + if (dst_buffer & (pgraph_dest_buffer3)) + nv3_render_write_pixel_to_buffer(position, color, grobj, 3); + + +} + /* Ensure the correct monitor size */ void nv3_render_ensure_screen_size(void) { @@ -606,12 +611,14 @@ void nv3_render_current_bpp_dfb_32(uint32_t address) void nv3_render_current_bpp() { /* Figure out the Display Buffer Address from the CRTC */ - + uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; - //uint32_t dba = 1920000; + if (nv3->nvbase.debug_dba_enabled + && nv3->nvbase.debug_dba > 0) + dba = nv3->nvbase.debug_dba; nv3_coord_16_t screen_size = {0}; screen_size.x = nv3->nvbase.svga.hdisp; diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index b7b5a7dfb..617bda649 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -819,7 +819,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) // 0x0 is used for creating the object. if (method_offset > 0 && method_offset < 0x100) { - // Reserved NVIDIA Objects + // Reserved nvidia methods oh_shit = true; oh_shit_reason = nv3_runout_reason_reserved_access; new_address |= (nv3_runout_reason_reserved_access << NV3_PFIFO_RUNOUT_RAMIN_ERR); From 5fc903fb48e138d38838a43786643255bfbabac8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 17 Jul 2025 19:16:39 +0100 Subject: [PATCH 209/274] Amazingly, if I make a 32-bit write to SVGA, it probably shouldn't write to four different CRTC registers..... --- src/video/nv/nv3/nv3_core.c | 16 ++++++++++++---- src/video/nv/nv3/render/nv3_render_core.c | 5 +---- src/video/nv/nv3/subsystems/nv3_pfifo.c | 3 ++- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 146069e7e..fbb248de7 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -197,7 +197,9 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_write(real_address, val & 0xFF, nv3); - nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); + + if (val > 0xFF) + nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); return; } @@ -225,9 +227,15 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_write(real_address, val & 0xFF, nv3); - nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); - nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3); - nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3); + + if (val > 0xFF) + nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); + + if (val > 0xFFFF) + nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3); + + if (val > 0xFFFFFF) + nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3); return; } diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 88c91688b..ac8789226 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -454,8 +454,7 @@ void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, n return; } - // convert to 16bpp - // forcing it to render in 15bpp fixes it, + // convert to 15bpp or 16bpp based on if we are in 16bpp mode rop_dst = vram_16[pixel_addr_vram]; @@ -497,8 +496,6 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t nv3_render_write_pixel_to_buffer(position, color, grobj, 2); if (dst_buffer & (pgraph_dest_buffer3)) nv3_render_write_pixel_to_buffer(position, color, grobj, 3); - - } /* Ensure the correct monitor size */ diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index 617bda649..9ddcda0d3 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -742,7 +742,7 @@ void nv3_pfifo_cache0_pull(void) // Tell the CPU if we found a software method and turn off cache pulling if (!(current_context & 0x800000)) { - nv_log("The object in CACHE0 is a software object\n"); + nv_log_verbose_only("The object in CACHE0 is a software object\n"); nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; @@ -923,6 +923,7 @@ void nv3_pfifo_cache1_pull(void) return; // interrupt was fired, and we went to ramro } + // should this be obtained from the grobj? Test on real nv3 h/w after drawrect.nvp works uint32_t current_context = nv3->pfifo.cache1_settings.context[current_subchannel]; // get the current subchannel uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; From 97c9888b9c01cf60273ad178cdca2649d856376b Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 27 Jul 2025 15:44:44 +0100 Subject: [PATCH 210/274] Load VRAM savestates.... --- .../86box/nv/classes/vid_nv3_classes.h | 11 ++- src/qt/qt_gpudebug_visualnv.cpp | 93 ++++++++++++++++++- src/qt/qt_gpudebug_visualnv.hpp | 2 + src/qt/qt_gpudebug_visualnv.ui | 6 +- src/qt/qt_mainwindow.cpp | 15 ++- src/qt/qt_mainwindow.ui | 2 +- src/video/nv/nv3/render/nv3_render_blit.c | 67 +++++++++++-- src/video/nv/nv3/render/nv3_render_core.c | 24 ++++- 8 files changed, 197 insertions(+), 23 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 85979dd45..15f4d37f1 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -239,9 +239,14 @@ typedef struct nv3_color_expanded_s uint8_t a; /* WARNING: The internal format is 10-bit RGB! */ - uint16_t r : 10; - uint16_t g : 10; - uint16_t b : 10; + uint16_t r; + uint16_t g; + uint16_t b; + + // YUV stuff + float y; + float u; + float v; // Indexed colour union diff --git a/src/qt/qt_gpudebug_visualnv.cpp b/src/qt/qt_gpudebug_visualnv.cpp index bbbd6c8ab..3b2ba8472 100644 --- a/src/qt/qt_gpudebug_visualnv.cpp +++ b/src/qt/qt_gpudebug_visualnv.cpp @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "ui_qt_gpudebug_visualnv.h" @@ -55,8 +56,11 @@ VisualNVDialog::VisualNVDialog(QWidget *parent) , ui(new Ui::VisualNVDialog) { ui->setupUi(this); + connect(ui->btnLoadSavestate, &QPushButton::clicked, this, &VisualNVDialog::on_btnLoadSavestate_clicked); connect(ui->fbStartAddress, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_fbStartAddress_changed); + connect(ui->bPitch0Value, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_bPitch0Value_changed); + connect(ui->bPitch1Value, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_bPitch1Value_changed); } // VisualNV dialog destructor @@ -67,7 +71,62 @@ VisualNVDialog::~VisualNVDialog() void VisualNVDialog::on_btnLoadSavestate_clicked() { - warning("THIS IS VisualNVDialog::on_btnLoadSavestate_clicked!!!! (throws into hole)"); + if (!nv3) + return; + + QString bar0_file_name = QFileDialog::getOpenFileName + ( + this, + tr("Please provide NVPlay 0.3.0.7+ NV3BAR0.BIN file"), + ".", + tr("NVPlay MMIO Dump Files (*.bin)") + ); + + QString bar1_file_name = QFileDialog::getOpenFileName + ( + this, + tr("Please provide NVPlay 0.3.0.7+ NV3BAR1.BIN file"), + ".", + tr("NVPlay VRAM/RAMIN Dump Files (*.bin)") + ); + + // + // Open both dump files + // + + QFile bar0(bar0_file_name); + QFile bar1(bar1_file_name); + + if (!bar0.open(QIODevice::ReadOnly)) + { + warning("Failed to open NV3BAR0.bin!"); + return; + } + + if (!bar1.open(QIODevice::ReadOnly)) + { + warning("Failed to open NV3BAR1.bin!"); + return; + } + + if (bar0.size() != NV3_MMIO_SIZE + || bar1.size() != NV3_MMIO_SIZE) + { + warning("NV3BAR0.bin and NV3BAR1.bin must be 16MB!"); + bar0.close(); + bar1.close(); + return; + } + + // Load VRAM contents only for now. Todo: MMIO+RAMIN + QString oldTitle = this->windowTitle(); + + this->setWindowTitle(tr("RIVA 128 Realtime Debugger: Savestate Loading...")); + + bar1.read((char*)nv3->nvbase.svga.vram, nv3->nvbase.vram_amount); + + this->setWindowTitle(oldTitle); + } void VisualNVDialog::on_fbStartAddress_changed() @@ -84,3 +143,35 @@ void VisualNVDialog::on_fbStartAddress_changed() nv3->nvbase.debug_dba_enabled = false; } } + +void VisualNVDialog::on_bPitch0Value_changed() +{ + if (nv3) + { + bool ok = true; + + uint32_t old_bpitch = nv3->pgraph.bpitch[0]; + + nv3->pgraph.bpitch[0] = ui->bPitch0Value->toPlainText().toInt(&ok); + + if (!ok) + nv3->pgraph.bpitch[0] = old_bpitch; + } + +} + +void VisualNVDialog::on_bPitch1Value_changed() +{ + if (nv3) + { + bool ok = true; + + uint32_t old_bpitch = nv3->pgraph.bpitch[1]; + + nv3->pgraph.bpitch[1] = ui->bPitch0Value->toPlainText().toInt(&ok); + + if (!ok) + nv3->pgraph.bpitch[1] = old_bpitch; + } + +} \ No newline at end of file diff --git a/src/qt/qt_gpudebug_visualnv.hpp b/src/qt/qt_gpudebug_visualnv.hpp index effbff67b..ee87dc0b3 100644 --- a/src/qt/qt_gpudebug_visualnv.hpp +++ b/src/qt/qt_gpudebug_visualnv.hpp @@ -35,6 +35,8 @@ class VisualNVDialog : public QDialog void on_btnLoadSavestate_clicked(); void on_fbStartAddress_changed(); + void on_bPitch0Value_changed(); + void on_bPitch1Value_changed(); protected: private: diff --git a/src/qt/qt_gpudebug_visualnv.ui b/src/qt/qt_gpudebug_visualnv.ui index 3c7b7d659..ce45c4e44 100644 --- a/src/qt/qt_gpudebug_visualnv.ui +++ b/src/qt/qt_gpudebug_visualnv.ui @@ -29,7 +29,7 @@ - Nvidia GPU Realtime Debugger + RIVA 128 Realtime Debugger @@ -170,7 +170,7 @@ <html><head/><body><p>BPITCH[0]:</p></body></html> - + 460 @@ -180,7 +180,7 @@ - + 460 diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index e5f52d0a7..11f6f2519 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -2328,19 +2328,26 @@ void MainWindow::on_actionACPI_Shutdown_triggered() void MainWindow::on_actionDebug_GPUDebug_VRAM_triggered() { - debugVramDialog = new GPUDebugVRAMDialog; + debugVramDialog = new GPUDebugVRAMDialog(this); debugVramDialog->setWindowFlag(Qt::CustomizeWindowHint, true); debugVramDialog->setWindowFlag(Qt::WindowTitleHint, true); debugVramDialog->setWindowFlag(Qt::WindowSystemMenuHint, false); - debugVramDialog->show(); + // If I have this as a NON-MODAL dialog, input is just eaten without doing anything + // WTF?!?!?!?!? + //debugVramDialog->show(); + debugVramDialog->exec(); + } void MainWindow::on_actionDebug_GPUDebug_VisualNv_triggered() { - visualNvDialog = new VisualNVDialog; + visualNvDialog = new VisualNVDialog(this); visualNvDialog->setWindowFlag(Qt::CustomizeWindowHint, true); visualNvDialog->setWindowFlag(Qt::WindowTitleHint, true); visualNvDialog->setWindowFlag(Qt::WindowSystemMenuHint, false); - visualNvDialog->show(); + // If I have this as a NON-MODAL dialog, input is just eaten without doing anything + // WTF?!?!?!?!? + //visualNvDialog->show(); + visualNvDialog->exec(); } \ No newline at end of file diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index 89db6f495..072a5a6a6 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -890,7 +890,7 @@ - GPU Realtime Debugger (NVIDIA ONLY) + RIVA 128 Realtime Debugger diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index c1b221648..0896bd199 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -119,20 +119,14 @@ This is LUDICROUSLY INEFFICIENT (2*O(n^2)) and COMPLETELY TERRIBLE code, but it' */ uint32_t nv3_s2sb_line_buffer[NV3_MAX_HORIZONTAL_SIZE*NV3_MAX_VERTICAL_SIZE] = {0}; -void nv3_render_blit_screen2screen(nv3_grobj_t grobj) +void nv3_render_blit_screen2screen_for_buffer(nv3_grobj_t grobj, uint32_t dst_buffer) { - if (nv3->pgraph.blit.size.x < NV3_MAX_HORIZONTAL_SIZE +if (nv3->pgraph.blit.size.x < NV3_MAX_HORIZONTAL_SIZE && nv3->pgraph.blit.size.y < NV3_MAX_VERTICAL_SIZE) memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.y) * (sizeof(uint32_t) * nv3->pgraph.blit.size.x)); /* First calculate our source and destination buffer */ uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; - uint32_t dst_buffer = 0; // 5 = just use the source buffer - - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) dst_buffer = 0; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) dst_buffer = 1; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) dst_buffer = 2; - if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) dst_buffer = 3; nv3_coord_16_t in_position = nv3->pgraph.blit.point_in; nv3_coord_16_t out_position = nv3->pgraph.blit.point_out; @@ -175,4 +169,61 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj) memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); out_position.y++; } + + /* + //32bit only as a test + uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; + + if (nv3->pgraph.boffset[src_buffer] != nv3->pgraph.boffset[dst_buffer]) + { + // stretch out the position to the new one + + nv3_coord_16_t current_pos_in; + nv3_coord_16_t current_pos_out; + + current_pos_in.x = nv3->pgraph.blit.point_in.x; + current_pos_in.y = nv3->pgraph.blit.point_in.y; + current_pos_out.x = nv3->pgraph.blit.point_out.x; + current_pos_out.y = nv3->pgraph.blit.point_out.y; + + for (uint32_t y = 0; y < nv3->pgraph.blit.size.y; y++) + { + current_pos_in.y = nv3->pgraph.blit.point_in.y + y; + current_pos_out.y = nv3->pgraph.blit.point_out.y + y; + + for (uint32_t x = 0; x < nv3->pgraph.blit.size.x; x++) + { + current_pos_in.x = nv3->pgraph.blit.point_in.x + x; + current_pos_out.x = nv3->pgraph.blit.point_out.x + x; + + uint32_t index = nv3_render_get_vram_address_for_buffer(current_pos_in, dst_buffer) >> 2; + uint32_t index_dst = nv3_render_get_vram_address_for_buffer(current_pos_out, src_buffer) >> 2; + + vram_32[index_dst] = vram_32[index]; + + //nv3_render_write_pixel(current_pos, vram_32[index], grobj); + } + + current_pos_in.x = nv3->pgraph.blit.point_in.x; + current_pos_out.x = nv3->pgraph.blit.point_out.x; + + } + } + */ +} + +void nv3_render_blit_screen2screen(nv3_grobj_t grobj) +{ + uint32_t dst_buffer = (nv3_pgraph_destination_buffer)grobj.grobj_0; // 5 = just use the source buffer + + if (dst_buffer & pgraph_dest_buffer0) + nv3_render_blit_screen2screen_for_buffer(grobj, 0); + if (dst_buffer & pgraph_dest_buffer1) + nv3_render_blit_screen2screen_for_buffer(grobj, 1); + if (dst_buffer & pgraph_dest_buffer2) + nv3_render_blit_screen2screen_for_buffer(grobj, 2); + if (dst_buffer & pgraph_dest_buffer3) + nv3_render_blit_screen2screen_for_buffer(grobj, 3); + + } \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index ac8789226..862d83371 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -100,6 +100,9 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) // yuv color_final.r = color_final.g = color_final.b = (color & 0xFFFF) * 4; // convert to rgb10 break; + case nv3_pgraph_pixel_format_y420: + warning("nv3_render_expand_color: YUV420 not implemented\n"); + break; default: warning("nv3_render_expand_color unknown format %d", format); break; @@ -148,8 +151,11 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co packed_color = nv3_render_get_palette_index((color.r >> 2) & 0xFF); break; case nv3_pgraph_pixel_format_y16: - warning("nv3_render_downconvert: Y16 not implemented"); + warning("nv3_render_downconvert_color: Y16 not implemented"); break; + case nv3_pgraph_pixel_format_y420: + warning("nv3_render_downconvert_color: YUV420 not implemented\n"); + break; default: warning("nv3_render_downconvert_color unknown format %d", format); break; @@ -668,6 +674,9 @@ void nv3_render_8bpp(uint32_t vram_start, nv3_coord_16_t screen_size) { for (uint32_t x = 0; x < screen_size.x; x++) { + if (vram_current_position >= nv3->nvbase.vram_amount) + return; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; @@ -698,6 +707,9 @@ void nv3_render_15bpp(uint32_t vram_start, nv3_coord_16_t screen_size) { for (uint32_t x = 0; x < screen_size.x; x++) { + if (vram_current_position >= nv3->nvbase.vram_amount) + return; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; @@ -728,7 +740,10 @@ void nv3_render_16bpp(uint32_t vram_start, nv3_coord_16_t screen_size) for (uint32_t y = 0; y < screen_size.y; y++) { for (uint32_t x = 0; x < screen_size.x; x++) - { + { + if (vram_current_position >= nv3->nvbase.vram_amount) + return; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; @@ -760,7 +775,10 @@ void nv3_render_32bpp(uint32_t vram_start, nv3_coord_16_t screen_size) for (uint32_t y = 0; y < screen_size.y; y++) { for (uint32_t x = 0; x < screen_size.x; x++) - { + { + if (vram_current_position >= nv3->nvbase.vram_amount) + return; + p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; From d470c9067913e6791ca7a128f7fb2de47675acf1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 12 Aug 2025 20:57:36 +0100 Subject: [PATCH 211/274] Partially fix S2SB. Makes Windows 95 behave a lot better! --- src/include/86box/nv/render/vid_nv3_render.h | 3 + src/include/86box/nv/vid_nv3.h | 80 ++++++++---- src/include/86box/utils/video_stdlib.h | 3 + .../classes/nv3_class_01c_image_in_memory.c | 2 +- src/video/nv/nv3/nv3_core_arbiter.c | 16 +-- src/video/nv/nv3/render/nv3_render_blit.c | 4 +- src/video/nv/nv3/render/nv3_render_core.c | 116 ++++++++++++++++-- src/video/nv/nv3/subsystems/nv3_pgraph.c | 8 +- 8 files changed, 186 insertions(+), 46 deletions(-) diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index 9c7af77ab..e0b28edd0 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -39,6 +39,9 @@ uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color); // Convert a colour from the current working format to RGB10 format. +/* ROP */ +uint8_t nv3_render_translate_nvrop(nv3_grobj_t grobj, uint32_t rop); + /* Pattern */ void nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1); diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 8e3bd87da..48170bfcd 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -607,24 +607,58 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 //todo: add what this does #define NV3_PGRAPH_INTR_EN_1 0x400144 // Interrupt Control for PGRAPH #2 (it can receive two at onc) -#define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // Holds the current PGRAPH context, switched by context switching +#define NV3_PGRAPH_CTX_SWITCH 0x400180 // Holds the current PGRAPH context, switched by context switching /* Contextual information for pgraph */ -#define NV3_PGRAPH_CONTEXT_SWITCH_COLOR_FORMAT 2 // Holds the current color format used for drawing operations. -#define NV3_PGRAPH_CONTEXT_SWITCH_ALPHA 3 // Holds a boolean if alpha transparency is currently enabled in drawing operations. -#define NV3_PGRAPH_CONTEXT_SWITCH_MONO_FORMAT 8 // Holds the current color format used for monochome drawing operations. -#define NV3_PGRAPH_CONTEXT_SWITCH_DAC_BYPASS 9 // Holds if PRAMDAC should be bypassed, and an external DAC drawn. -#define NV3_PGRAPH_CONTEXT_SWITCH_Z_WRITE 12 // Holds if we should write back to the zbuffer. -#define NV3_PGRAPH_CONTEXT_SWITCH_CHROMA_KEY 13 // Holds the current chroma mask used for drawing operations. -#define NV3_PGRAPH_CONTEXT_SWITCH_PLANE_MASK 14 // Holds the current plane mask used for drawing operations. -#define NV3_PGRAPH_CONTEXT_SWITCH_USER_CLIP 15 // Holds the user-specified clipping information used for drawing operations. -#define NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER 16 // Holds the buffer ID used for drawing operation (i.e. which bpixel/bpitch/boffset index to use) -#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED 20 // Holds a boolean indicating if buffer 0 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED 21 // Holds a boolean indicating if buffer 1 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED 22 // Holds a boolean indicating if buffer 2 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED 23 // Holds a boolean indicating if buffer 3 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CONTEXT_SWITCH_PATCH_CONFIG 24 // Something to do with an operation to do during a patchcord? -#define NV3_PGRAPH_CONTEXT_SWITCH_VOLATILE 31 // HUH +#define NV3_PGRAPH_CTX_SWITCH_COLOR_FORMAT 0 // Holds the current color format used for drawing operations. +#define NV3_PGRAPH_CTX_SWITCH_ALPHA 3 // Holds a boolean indicating in if alpha transparency is currently enabled in drawing operations. +#define NV3_PGRAPH_CTX_SWITCH_MONO_FORMAT 8 // Holds the current color format used for monochome drawing operations. +#define NV3_PGRAPH_CTX_SWITCH_DAC_BYPASS 9 // Holds if PRAMDAC should be bypassed, and an external DAC drawn. +#define NV3_PGRAPH_CTX_SWITCH_Z_WRITE 12 // Holds if we should write back to the zbuffer. +#define NV3_PGRAPH_CTX_SWITCH_CHROMA_KEY 13 // Holds the current chroma mask used for drawing operations. +#define NV3_PGRAPH_CTX_SWITCH_PLANE_MASK 14 // Holds the current plane mask used for drawing operations. +#define NV3_PGRAPH_CTX_SWITCH_USER_CLIP 15 // Holds the user-specified clipping information used for drawing operations. +#define NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER 16 // Holds the buffer ID used for drawing operation (i.e. which bpixel/bpitch/boffset index to use) +#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER0_ENABLED 20 // Holds a boolean indicating if buffer 0 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER1_ENABLED 21 // Holds a boolean indicating if buffer 1 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER2_ENABLED 22 // Holds a boolean indicating if buffer 2 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER3_ENABLED 23 // Holds a boolean indicating if buffer 3 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG 24 // ROP type + +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0 0x0 // Reserved +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_DST_SRC 0x1 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_DST 0x2 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_SRC 0x3 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_DST 0x4 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_SRC 0x5 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_DST 0x6 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_SRC0 0x7 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_SRC1 0x8 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_PAT 0x9 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_SRC 0xA +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_PAT 0xB +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_SRC 0xC +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_PAT 0xD +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_PAT_SRC 0xE +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD1 0xF +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_DST 0x10 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_DST_SRC 0x11 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_DST 0x12 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_PAT 0x13 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_PAT_SRC 0x14 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_PAT 0x15 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD2 0x16 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS 0x17 // Ignore +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD0 0x18 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_SRC_DST 0x19 +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_DST_SRC 0x1A +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD1 0x1B +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD2 0x1C +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_SRC 0x1D +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD3 0x1E +#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD4 0x1F + +#define NV3_PGRAPH_CTX_SWITCH_VOLATILE 31 // HUH #define NV3_PGRAPH_CONTEXT_CONTROL 0x400190 // DMA context control #define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename @@ -1166,10 +1200,10 @@ typedef struct nv3_pramdac_s } nv3_pramdac_t; /* Holds DMA channel context information */ -typedef struct nv3_pgraph_context_switch_s +typedef struct NV3_PGRAPH_CTX_SWITCH_s { /* TODO */ -} nv3_pgraph_context_switch_t; +} NV3_PGRAPH_CTX_SWITCH_t; typedef struct nv3_pgraph_context_control_s { @@ -1251,10 +1285,10 @@ typedef enum nv3_pgraph_bpixel_format_e typedef enum nv3_pgraph_destination_buffer_e { - pgraph_dest_buffer0 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED), - pgraph_dest_buffer1 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED), - pgraph_dest_buffer2 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED), - pgraph_dest_buffer3 = (1 << NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED), + pgraph_dest_buffer0 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER0_ENABLED), + pgraph_dest_buffer1 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER1_ENABLED), + pgraph_dest_buffer2 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER2_ENABLED), + pgraph_dest_buffer3 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER3_ENABLED), } nv3_pgraph_destination_buffer; // Graphics Subsystem @@ -1273,7 +1307,7 @@ typedef struct nv3_pgraph_s uint32_t context_switch; // TODO: Make this a struct, it's just going to be enormous lol. nv3_pgraph_context_control_t context_control; - nv3_pgraph_context_switch_t context_user_submit; + NV3_PGRAPH_CTX_SWITCH_t context_user_submit; nv3_pgraph_context_user_t context_user; uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE]; // DMA context cache (nv3_pgraph_context_user_t array?) diff --git a/src/include/86box/utils/video_stdlib.h b/src/include/86box/utils/video_stdlib.h index 4434ef43f..0d4b148d6 100644 --- a/src/include/86box/utils/video_stdlib.h +++ b/src/include/86box/utils/video_stdlib.h @@ -17,4 +17,7 @@ /* ROP */ + +#define VIDEO_ROP_SRC_COPY 0xCC + int32_t video_rop_gdi_ternary(int32_t rop, int32_t src, int32_t dst, int32_t pattern); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index eb7f266d2..12ac3fe6b 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -31,7 +31,7 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { /* We need this for a lot of methods, so may as well store it here. */ - uint32_t src_buffer_id = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + uint32_t src_buffer_id = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER) & 0x03; switch (method_id) diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c index e23386cac..3399ca9fe 100644 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ b/src/video/nv/nv3/nv3_core_arbiter.c @@ -108,11 +108,11 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address) else { //nvplay stuff - #ifdef ENABLE_NV_LOG_ULTRA - warning("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); - #else + //#ifdef ENABLE_NV_LOG_ULTRA + //warning("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); + //#else nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); - #endif + //#endif // The real hardware returns a garbage pattern return 0x00; @@ -181,11 +181,11 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) else { //nvplay stuff - #ifdef ENABLE_NV_LOG_ULTRA - warning("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); - #else + //#ifdef ENABLE_NV_LOG_ULTRA + //warning("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); + //#else nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); - #endif + //#endif return; } diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c index 0896bd199..92b657cd0 100644 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ b/src/video/nv/nv3/render/nv3_render_blit.c @@ -121,12 +121,12 @@ uint32_t nv3_s2sb_line_buffer[NV3_MAX_HORIZONTAL_SIZE*NV3_MAX_VERTICAL_SIZE] = { void nv3_render_blit_screen2screen_for_buffer(nv3_grobj_t grobj, uint32_t dst_buffer) { -if (nv3->pgraph.blit.size.x < NV3_MAX_HORIZONTAL_SIZE + if (nv3->pgraph.blit.size.x < NV3_MAX_HORIZONTAL_SIZE && nv3->pgraph.blit.size.y < NV3_MAX_VERTICAL_SIZE) memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.y) * (sizeof(uint32_t) * nv3->pgraph.blit.size.x)); /* First calculate our source and destination buffer */ - uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER) & 0x03; nv3_coord_16_t in_position = nv3->pgraph.blit.point_in; nv3_coord_16_t out_position = nv3->pgraph.blit.point_out; diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 862d83371..db7bdb06d 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -44,7 +44,7 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) // grobj0 = seems to share the format of PGRAPH_CONTEXT_SWITCH register. uint8_t format = (grobj.grobj_0 & 0x07); - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_ALPHA) & 0x01; nv3_color_expanded_t color_final; // set the pixel format @@ -119,7 +119,7 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color) { uint8_t format = (grobj.grobj_0 & 0x07); - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_ALPHA) & 0x01; nv_log_verbose_only("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); @@ -168,7 +168,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co /* Runs the chroma key/color key test */ bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj) { - bool chroma_enabled = ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_CHROMA_KEY) & 0x01); + bool chroma_enabled = ((grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_CHROMA_KEY) & 0x01); if (!chroma_enabled) return true; @@ -239,7 +239,7 @@ uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj) { uint32_t vram_x = position.x; uint32_t vram_y = position.y; - uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER) & 0x03; uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; @@ -359,7 +359,7 @@ uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj) void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj, uint32_t buffer) { - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01; + bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_ALPHA) & 0x01; int32_t clip_end_x = nv3->pgraph.clip_start.x + nv3->pgraph.clip_size.x; int32_t clip_end_y = nv3->pgraph.clip_start.y + nv3->pgraph.clip_size.y; @@ -428,6 +428,9 @@ void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, n We use the pixel format of the destination buffer to achieve this (thanks frostbite2000) */ + // translate the patch config to GDI rop + uint32_t final_rop = nv3_render_translate_nvrop(grobj, nv3->pgraph.rop); + uint32_t destination_format = (nv3->pgraph.bpixel[buffer]) & 0x03; switch (destination_format) @@ -435,7 +438,7 @@ void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, n case bpixel_fmt_8bit: rop_src = color & 0xFF; rop_dst = nv3->nvbase.svga.vram[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern) & 0xFF; + nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(final_rop, rop_src, rop_dst, rop_pattern) & 0xFF; nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; @@ -464,7 +467,7 @@ void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, n rop_dst = vram_16[pixel_addr_vram]; - vram_16[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern) & 0xFFFF; + vram_16[pixel_addr_vram] = video_rop_gdi_ternary(final_rop, rop_src, rop_dst, rop_pattern) & 0xFFFF; nv3->nvbase.svga.changedvram[pixel_addr_vram >> 11] = changeframecount; @@ -477,7 +480,7 @@ void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, n rop_src = color; rop_dst = vram_32[pixel_addr_vram]; - vram_32[pixel_addr_vram] = video_rop_gdi_ternary(nv3->pgraph.rop, rop_src, rop_dst, rop_pattern); + vram_32[pixel_addr_vram] = video_rop_gdi_ternary(final_rop, rop_src, rop_dst, rop_pattern); nv3->nvbase.svga.changedvram[pixel_addr_vram >> 10] = changeframecount; @@ -789,3 +792,100 @@ void nv3_render_32bpp(uint32_t vram_start, nv3_coord_16_t screen_size) } } } + +// Translate an "NV-ROP" into a GDI Ternary ROP +uint8_t nv3_render_translate_nvrop(nv3_grobj_t grobj, uint32_t rop) +{ + // Credit to envytools for this function: + // https://github.com/envytools/envytools/blob/f102b82381f3f11cee113d16374c87091db039d9/nvhw/pgraph.c + // How does one even go about reverse engineering this (I'm sure the behaviour is simpler when you don't have to translate this but...) Marcelina is a legend. + + uint32_t patch_config_rop = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG) & 0x1F; + + /* || patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0*/ + + // TODO: Blending + if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS) // 0x00 is used for "nothing here" it seems. + return VIDEO_ROP_SRC_COPY; + + uint8_t res = 0; + + int32_t swizzle[3]; + + if (patch_config_rop < 8) { + swizzle[0] = patch_config_rop >> 0 & 1; + swizzle[1] = patch_config_rop >> 1 & 1; + swizzle[2] = patch_config_rop >> 2 & 1; + } else if (patch_config_rop < 0x10) { + swizzle[0] = (patch_config_rop >> 0 & 1) + 1; + swizzle[1] = (patch_config_rop >> 1 & 1) + 1; + swizzle[2] = (patch_config_rop >> 2 & 1) + 1; + } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_DST) { + swizzle[0] = 0, swizzle[1] = 1, swizzle[2] = 2; + } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_DST_SRC) { + swizzle[0] = 1, swizzle[1] = 0, swizzle[2] = 2; + } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_DST) { + swizzle[0] = 0, swizzle[1] = 2, swizzle[2] = 1; + } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_PAT) { + swizzle[0] = 2, swizzle[1] = 0, swizzle[2] = 1; + } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_PAT_SRC) { + swizzle[0] = 1, swizzle[1] = 2, swizzle[2] = 0; + } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_PAT) { + swizzle[0] = 2, swizzle[1] = 1, swizzle[2] = 0; + } else { + warning("NV3 ROP: Invalid patch configuration %02x!", rop); + } + if (patch_config_rop == 0) { + if (rop & 0x01) + res |= 0x11; + if (rop & 0x16) + res |= 0x44; + if (rop & 0x68) + res |= 0x22; + if (rop & 0x80) + res |= 0x88; + } else if (patch_config_rop == 0xf) { + if (rop & 0x01) + res |= 0x03; + if (rop & 0x16) + res |= 0x0c; + if (rop & 0x68) + res |= 0x30; + if (rop & 0x80) + res |= 0xc0; + } else { + int32_t i; + for (i = 0; i < 8; i++) { + int32_t s0 = i >> swizzle[0] & 1; + int32_t s1 = i >> swizzle[1] & 1; + int32_t s2 = i >> swizzle[2] & 1; + int32_t s = s2 << 2 | s1 << 1 | s0; + if (rop >> s & 1) + res |= 1 << i; + } + } + return res; + + /* + uint32_t patch_config = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG) & 0x1F; + + // Wtf do these even do? + switch (patch_config) + { + // don't do anything + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD1: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD2: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD0: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD1: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD2: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD3: + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD4: + return src; + case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_DST: // S2SB + break; + + } + */ +} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c index dbca46216..3ad9fa2a1 100644 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c @@ -51,7 +51,7 @@ nv_register_t pgraph_registers[] = { { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL }, { NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL }, { NV3_PGRAPH_INTR_EN_1, "PGRAPH Interrupt Enable 1", NULL, NULL }, - { NV3_PGRAPH_CONTEXT_SWITCH, "PGRAPH DMA Context Switch", NULL, NULL }, + { NV3_PGRAPH_CTX_SWITCH, "PGRAPH DMA Context Switch", NULL, NULL }, { NV3_PGRAPH_CONTEXT_CONTROL, "PGRAPH DMA Context Control", NULL, NULL }, { NV3_PGRAPH_CONTEXT_USER, "PGRAPH DMA Context User", NULL, NULL }, //{ NV3_PGRAPH_CONTEXT_CACHE(0), "PGRAPH DMA Context Cache", NULL, NULL }, @@ -156,7 +156,7 @@ uint32_t nv3_pgraph_read(uint32_t address) // In the future, these will most likely have their own functions... // Context Swithcing (THIS IS CONTROLLED BY PFIFO!) - case NV3_PGRAPH_CONTEXT_SWITCH: + case NV3_PGRAPH_CTX_SWITCH: ret = nv3->pgraph.context_switch; break; case NV3_PGRAPH_CONTEXT_CONTROL: @@ -359,7 +359,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value) // In the future, these will most likely have their own functions... // Context Swithcing (THIS IS CONTROLLED BY PFIFO!) - case NV3_PGRAPH_CONTEXT_SWITCH: + case NV3_PGRAPH_CTX_SWITCH: nv3->pgraph.context_switch = value; break; case NV3_PGRAPH_CONTEXT_CONTROL: @@ -625,7 +625,7 @@ void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t switch (method) { default: - // Object Method orchestration + // Object Method arbitration nv3_pgraph_arbitrate_method(param, method, channel, subchannel, class_id, context); break; } From 0e439cf0aeb32bd06c340adaf0a489e5fe1dac34 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 12 Aug 2025 22:07:19 +0100 Subject: [PATCH 212/274] Move notifications to DMA code --- CMakePresets.json | 3 +- src/include/86box/nv/vid_nv3.h | 2 +- .../nv/nv3/classes/nv3_class_shared_methods.c | 115 ------------- src/video/nv/nv3/nv3_core.c | 2 +- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 153 +++++++++++++++++- 5 files changed, 155 insertions(+), 120 deletions(-) diff --git a/CMakePresets.json b/CMakePresets.json index b2ed64e97..30feab8ab 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -36,8 +36,7 @@ "name": "debug", "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug", - "NV_LOG": "ON", - "NV_LOG_ULTRA": "ON" + "NV_LOG": "ON" }, "inherits": "base" }, diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 48170bfcd..05281a5ac 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -75,7 +75,7 @@ extern const device_config_t nv3t_config[]; // Confi #define NV3T_VBIOS_ASUS_V170 "roms/video/nvidia/nv3/A170D03T.rom" // ASUS AGP-V3000 ZXTV BIOS - V1.70D.03 (C) 1996-98 Nvidia Corporation #define NV3T_VBIOS_REFERENCE_CEK_V171 "roms/video/nvidia/nv3/BIOS_49_Riva 128" // Reference BIOS: RIVA 128 ZX BIOS - V1.71B-N (C) 1996-98 NVidia Corporation #define NV3T_VBIOS_REFERENCE_CEK_V172 "roms/video/nvidia/nv3/vgasgram.rom" // Reference(?) BIOS: RIVA 128 ZX BIOS - V1.72B (C) 1996-98 NVidia Corporation -# + // The default VBIOS to use #define NV3_VBIOS_DEFAULT NV3_VBIOS_ERAZOR_V15403 diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c index 80c635a21..89473d829 100644 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c @@ -65,118 +65,3 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t return; } } - - -/* Sees if any notification is required after an object method is executed. If so, executes it... */ -void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - if (!nv3->pgraph.notify_pending) - return; - - uint32_t current_notification_object = nv3->pgraph.notifier; - uint32_t notification_type = ((current_notification_object >> NV3_PGRAPH_NOTIFY_REQUEST_TYPE) & 0x07); - - // check for a software method (0 = hardware, 1 = software) - if (notification_type != 0) - { - nv_log("Software Notification, firing interrupt"); - nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY); - //return; - } - - // set up the NvNotification structure - nv3_notification_t notify = {0}; - notify.nanoseconds = nv3->ptimer.time; - notify.status = NV3_NOTIFICATION_STATUS_DONE_OK; // it should be fine to just signal that it's ok - - // these are only nonzero when there is an error - notify.info32 = notify.info16 = 0; - - // notify object base=grobj_1 >> 12 - uint32_t notify_obj_base = grobj.grobj_1 >> 12; - - uint32_t notify_obj_info = nv3_ramin_read32(notify_obj_base, nv3); - uint32_t notify_obj_limit = nv3_ramin_read32(notify_obj_base + 0x04, nv3); - uint32_t notify_obj_page = nv3_ramin_read32(notify_obj_base + 0x08, nv3); - - /* extract some important information*/ - uint32_t info_adjust = notify_obj_info & 0xFFF; - bool info_pt_present = (notify_obj_info >> NV3_NOTIFICATION_PT_PRESENT) & 0x01; - uint8_t info_notification_target = (notify_obj_info >> NV3_NOTIFICATION_TARGET) & 0x03; - - /* paging information */ - bool page_is_present = notify_obj_page & 0x01; - bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); - uint32_t frame_base = notify_obj_page & 0xFFFFF000; - - // This code is temporary and will probably be moved somewhere else - // Print torns of debug info - #ifdef DEBUG - nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); - - nv_log_verbose_only("Notification Information:\n"); - nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust); - (info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n"); - - switch (info_notification_target) - { - case NV3_NOTIFICATION_TARGET_NVM: - nv_log_verbose_only("Notification Target: VRAM\n"); - break; - case NV3_NOTIFICATION_TARGET_CART: - nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); - break; - case NV3_NOTIFICATION_TARGET_PCI: - (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); - break; - case NV3_NOTIFICATION_TARGET_AGP: - (nv3->nvbase.bus_generation == nv_bus_agp_1x - || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); - break; - } - - nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit); - (page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n"); - (page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n"); - nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base); - #endif - - // set up the dma transfer. we need to translate to a physical address. - - uint32_t final_address = 0; - - /* Simple case: hardware notification, we can just take the pte since it's based on the type */ - if (notification_type == 0) - { - final_address = frame_base + info_adjust; - } - else - { - // for software we have to calculate the pte index - uint32_t pte_num = ((notification_type << 4) + info_adjust) >> 12; - - /* ramin entries are sorted - 1 object for each pte entry...*/ - final_address = nv3_ramin_read32(notify_obj_base + (0x10 * pte_num) + 8, nv3); - final_address += (info_adjust & 0xFFF); - } - - /* send the notification off */ - nv_log("About to send hardware notification to 0x%08x (Check target)\n", final_address); - - switch (info_notification_target) - { - case NV3_NOTIFICATION_TARGET_NVM: - svga_writel_linear(final_address, (notify.nanoseconds & 0xFFFFFFFF), &nv3->nvbase.svga); - svga_writel_linear(final_address + 4, (notify.nanoseconds >> 32), &nv3->nvbase.svga); - svga_writel_linear(final_address + 8, notify.info32, &nv3->nvbase.svga); - svga_writel_linear(final_address + 0x0C, (notify.info16 | notify.status), &nv3->nvbase.svga); - break; - case NV3_NOTIFICATION_TARGET_PCI: - case NV3_NOTIFICATION_TARGET_AGP: - dma_bm_write(final_address, (uint8_t*)¬ify, sizeof(nv3_notification_t), 4); - break; - } - - // we're done - nv3->pgraph.notify_pending = false; -} diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index fbb248de7..46b6cf9c3 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -315,7 +315,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) ret = (NV_PCI_DEVICE_NV3 & 0xFF); break; - case NV3_PCI_CFG_DEVICE_ID+1: + case NV3_PCI_CFG_DEVICE_ID + 1: ret = (NV_PCI_DEVICE_NV3 >> 8); break; diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index da068e07f..49c844404 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -30,7 +30,158 @@ /* Nvidia DMA Engine */ -void nv3_dma_translate_address(void) +void nv3_perform_dma_m2mf(nv3_grobj_t grobj) +{ + switch (method_id) + { + /* mthdCreate in software(?)*/ + case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: + //nv_log("mthdCreate obj_name=0x%08x\n", param); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + break; + // set up the current notification request/object + // and check for double notifiers. + case NV3_SET_NOTIFY: + if (nv3->pgraph.notify_pending) + { + nv_log("Executed method NV3_SET_NOTIFY with nv3->pgraph.notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); + nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); + nv3_debug_ramin_print_context_info(param, context); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + + // disable + nv3->pgraph.notify_pending = false; + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); + /* may need to disable fifo in this state */ + return; + } + + // set a notify as pending. + nv3->pgraph.notifier = param; + nv3->pgraph.notify_pending = true; + break; + default: + nv_log("Shared Generic Methods: Invalid or Unimplemented method 0x%04x", method_id); + nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + return; + } +} + + +/* Sees if any notification is required after an object method is executed. If so, executes it... */ +void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { + if (!nv3->pgraph.notify_pending) + return; + + uint32_t current_notification_object = nv3->pgraph.notifier; + uint32_t notification_type = ((current_notification_object >> NV3_PGRAPH_NOTIFY_REQUEST_TYPE) & 0x07); + + // check for a software method (0 = hardware, 1 = software) + if (notification_type != 0) + { + nv_log("Software Notification, firing interrupt"); + nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY); + //return; + } + + // set up the NvNotification structure + nv3_notification_t notify = {0}; + notify.nanoseconds = nv3->ptimer.time; + notify.status = NV3_NOTIFICATION_STATUS_DONE_OK; // it should be fine to just signal that it's ok + // these are only nonzero when there is an error + notify.info32 = notify.info16 = 0; + + // notify object base=grobj_1 >> 12 + uint32_t notify_obj_base = grobj.grobj_1 >> 12; + + uint32_t notify_obj_info = nv3_ramin_read32(notify_obj_base, nv3); + uint32_t notify_obj_limit = nv3_ramin_read32(notify_obj_base + 0x04, nv3); + uint32_t notify_obj_page = nv3_ramin_read32(notify_obj_base + 0x08, nv3); + + /* extract some important information*/ + uint32_t info_adjust = notify_obj_info & 0xFFF; + bool info_pt_present = (notify_obj_info >> NV3_NOTIFICATION_PT_PRESENT) & 0x01; + uint8_t info_notification_target = (notify_obj_info >> NV3_NOTIFICATION_TARGET) & 0x03; + + /* paging information */ + bool page_is_present = notify_obj_page & 0x01; + bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); + uint32_t frame_base = notify_obj_page & 0xFFFFF000; + + // This code is temporary and will probably be moved somewhere else + // Print torns of debug info + #ifdef DEBUG + nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); + + nv_log_verbose_only("Notification Information:\n"); + nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust); + (info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n"); + + switch (info_notification_target) + { + case NV3_NOTIFICATION_TARGET_NVM: + nv_log_verbose_only("Notification Target: VRAM\n"); + break; + case NV3_NOTIFICATION_TARGET_CART: + nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); + break; + case NV3_NOTIFICATION_TARGET_PCI: + (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); + break; + case NV3_NOTIFICATION_TARGET_AGP: + (nv3->nvbase.bus_generation == nv_bus_agp_1x + || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); + break; + } + + nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit); + (page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n"); + (page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n"); + nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base); + #endif + + // set up the dma transfer. we need to translate to a physical address. + + uint32_t final_address = 0; + + /* Simple case: hardware notification, we can just take the pte since it's based on the type */ + if (notification_type == 0) + { + final_address = frame_base + info_adjust; + } + else + { + // for software we have to calculate the pte index + uint32_t pte_num = ((notification_type << 4) + info_adjust) >> 12; + + /* ramin entries are sorted - 1 object for each pte entry...*/ + final_address = nv3_ramin_read32(notify_obj_base + (0x10 * pte_num) + 8, nv3); + final_address += (info_adjust & 0xFFF); + } + + /* send the notification off */ + nv_log("About to send hardware notification to 0x%08x (Check target)\n", final_address); + + switch (info_notification_target) + { + case NV3_NOTIFICATION_TARGET_NVM: + + uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; + + // increment by 1 because each index increments by 4 + vram_32[final_address] = (notify.nanoseconds & 0xFFFFFFFF); + vram_32[final_address + 1] = (notify.nanoseconds >> 32); + vram_32[final_address + 2] = notify.info32; + vram_32[final_address + 3] = (notify.info16 | notify.status); + break; + case NV3_NOTIFICATION_TARGET_PCI: + case NV3_NOTIFICATION_TARGET_AGP: + dma_bm_write(final_address, (uint8_t*)¬ify, sizeof(nv3_notification_t), 4); + break; + } + + // we're done + nv3->pgraph.notify_pending = false; } \ No newline at end of file From 12a56203fa40036ee011f21a64f43039e5bc90d6 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Tue, 12 Aug 2025 23:30:27 +0100 Subject: [PATCH 213/274] First attempt at M2MF. It sucks --- .../86box/nv/classes/vid_nv3_classes.h | 12 +- src/include/86box/nv/render/vid_nv3_render.h | 5 +- src/include/86box/nv/vid_nv3.h | 8 +- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 9 +- src/video/nv/nv3/render/nv3_render_core.c | 26 +-- src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 153 ++++++++++++++---- 6 files changed, 141 insertions(+), 72 deletions(-) diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 15f4d37f1..5106e5bff 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -124,12 +124,8 @@ typedef enum nv3_pgraph_class_e #define NV3_M2MF_FORMAT 0x0324 // M2MF formats (IN and OUT ORed together) -#define NV3_M2MF_FORMAT_INPUT_INC_1 0x1 -#define NV3_M2MF_FORMAT_INPUT_INC_2 0x2 -#define NV3_M2MF_FORMAT_INPUT_INC_4 0x4 -#define NV3_M2MF_FORMAT_OUTPUT_INC_1 0x100 -#define NV3_M2MF_FORMAT_OUTPUT_INC_2 0x200 -#define NV3_M2MF_FORMAT_OUTPUT_INC_4 0x400 +#define NV3_M2MF_FORMAT_INPUT 0 +#define NV3_M2MF_FORMAT_OUTPUT 8 #define NV3_M2MF_NOTIFY 0x0328 @@ -596,8 +592,8 @@ typedef struct nv3_object_class_00D uint32_t offset_out; uint32_t pitch_in; uint32_t pitch_out; - uint32_t line_length_in; // Stride? - uint32_t line_count; + uint32_t scanline_length; // Stride? + uint32_t num_scanlines; uint8_t format; // input increment 1 2 or 4, output increment 1 2 or 4 (represented by << 8) uint32_t buffer_notify; // Notify the Buffedr } nv3_memory_to_memory_format_t; diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h index e0b28edd0..cca3761be 100644 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ b/src/include/86box/nv/render/vid_nv3_render.h @@ -58,4 +58,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj); /* GDI */ void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitmap_data, nv3_grobj_t grobj); -void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj); /* GDI Type-E: Clipped 1bpp colour-expanded bitmap */ \ No newline at end of file +void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj); /* GDI Type-E: Clipped 1bpp colour-expanded bitmap */ + +/* DMA */ +void nv3_perform_dma_m2mf(nv3_grobj_t grobj); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 05281a5ac..b954355bb 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1054,10 +1054,10 @@ typedef struct nv3_pfb_s #define NV3_NOTIFICATION_INFO_ADJUST 0 // Wut #define NV3_NOTIFICATION_PT_PRESENT 16 // Determines if the pagetable exists. #define NV3_NOTIFICATION_TARGET 24 // Determines where this notification goes -#define NV3_NOTIFICATION_TARGET_NVM 0 // VRAM target for DMA -#define NV3_NOTIFICATION_TARGET_CART 1 // "Cartridge" target for dma, only mentioned in a few places, !!! NV2 LEFTOVER !!! -#define NV3_NOTIFICATION_TARGET_PCI 2 // Send the data to the host system over PCI -#define NV3_NOTIFICATION_TARGET_AGP 3 // Send the data to the host system over AGP +#define NV3_DMA_TARGET_NODE_VRAM 0 // VRAM target for DMA +#define NV3_DMA_TARGET_NODE_CART 1 // "Cartridge" target for dma, only mentioned in a few places, !!! NV2 LEFTOVER !!! +#define NV3_DMA_TARGET_NODE_PCI 2 // Send the data to the host system over PCI +#define NV3_DMA_TARGET_NODE_AGP 3 // Send the data to the host system over AGP #define NV3_NOTIFICATION_PAGE_IS_PRESENT 0 // Determines if the page really exists #define NV3_NOTIFICATION_PAGE_ACCESS 1 // Determines the page access type diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c index 4a6d2e39c..f07aab737 100644 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c @@ -49,16 +49,21 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_ nv_log("Method Execution: M2MF Pitch Out = 0x%08x", param); break; case NV3_M2MF_SCANLINE_LENGTH_IN_BYTES: - nv3->pgraph.m2mf.line_length_in = param; + nv3->pgraph.m2mf.scanline_length = param; nv_log("Method Execution: M2MF Scanline Length in Bytes = 0x%08x", param); break; case NV3_M2MF_NUM_SCANLINES: - nv3->pgraph.m2mf.line_count = param; + nv3->pgraph.m2mf.num_scanlines = param; nv_log("Method Execution: M2MF Num Scanlines = 0x%08x", param); break; case NV3_M2MF_FORMAT: nv3->pgraph.m2mf.format = param; nv_log("Method Execution: M2MF Format = 0x%08x", param); + + // Format Done - start m2mf + + nv3_perform_dma_m2mf(grobj); + break; case NV3_M2MF_NOTIFY: /* This is technically its own thing, but I don't know if it's ever a problem with how we've designed it */ diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index db7bdb06d..c40fa84a9 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -803,7 +803,7 @@ uint8_t nv3_render_translate_nvrop(nv3_grobj_t grobj, uint32_t rop) uint32_t patch_config_rop = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG) & 0x1F; /* || patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0*/ - + // TODO: Blending if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS) // 0x00 is used for "nothing here" it seems. return VIDEO_ROP_SRC_COPY; @@ -864,28 +864,6 @@ uint8_t nv3_render_translate_nvrop(nv3_grobj_t grobj, uint32_t rop) res |= 1 << i; } } + return res; - - /* - uint32_t patch_config = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG) & 0x1F; - - // Wtf do these even do? - switch (patch_config) - { - // don't do anything - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD1: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD2: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD0: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD1: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD2: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD3: - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD4: - return src; - case NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_DST: // S2SB - break; - - } - */ } \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c index 49c844404..3359e9079 100644 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c @@ -21,6 +21,7 @@ #include #include <86box/86box.h> #include <86box/device.h> +#include <86box/dma.h> #include <86box/mem.h> #include <86box/pci.h> #include <86box/rom.h> // DEPENDENT!!! @@ -31,40 +32,126 @@ /* Nvidia DMA Engine */ void nv3_perform_dma_m2mf(nv3_grobj_t grobj) -{ - switch (method_id) +{ + // notify object base=grobj_1 >> 12 + uint32_t notify_obj_base = grobj.grobj_1 >> 12; + + uint32_t notify_obj_info = nv3_ramin_read32(notify_obj_base, nv3); + uint32_t notify_obj_limit = nv3_ramin_read32(notify_obj_base + 0x04, nv3); + uint32_t notify_obj_page = nv3_ramin_read32(notify_obj_base + 0x08, nv3); + + /* extract some important information*/ + uint32_t info_adjust = notify_obj_info & 0xFFF; + bool info_pt_present = (notify_obj_info >> NV3_NOTIFICATION_PT_PRESENT) & 0x01; + uint8_t info_dma_target = (notify_obj_info >> NV3_NOTIFICATION_TARGET) & 0x03; + + /* paging information */ + bool page_is_present = notify_obj_page & 0x01; + bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); + uint32_t frame_base = notify_obj_page & 0xFFFFF000; + + // This code is temporary and will probably be moved somewhere else + // Print torns of debug info + #ifdef DEBUG + nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); + + nv_log_verbose_only("M2MF DMA Information:\n"); + nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust); + (info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n"); + + switch (info_dma_target) { - /* mthdCreate in software(?)*/ - case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - //nv_log("mthdCreate obj_name=0x%08x\n", param); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); + case NV3_DMA_TARGET_NODE_VRAM: + nv_log_verbose_only("Notification Target: VRAM\n"); break; - // set up the current notification request/object - // and check for double notifiers. - case NV3_SET_NOTIFY: - if (nv3->pgraph.notify_pending) + case NV3_DMA_TARGET_NODE_CART: + nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); + break; + case NV3_DMA_TARGET_NODE_PCI: + (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); + break; + case NV3_DMA_TARGET_NODE_AGP: + (nv3->nvbase.bus_generation == nv_bus_agp_1x + || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); + break; + } + + nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit); + (page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n"); + (page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n"); + nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base); + #endif + + // set up the dma transfer. we need to translate to a physical address. + + uint32_t final_address = 0; + + /* M2MF DMA only uses HW type */ + + final_address = frame_base + info_adjust; + + /* send the notification off */ + nv_log("About to send M2MF DMA to 0x%08x (Check target)\n", final_address); + + uint32_t offset_in = (nv3->pgraph.m2mf.offset_in); + uint32_t offset_out = (nv3->pgraph.m2mf.offset_out); + + uint32_t pitch_in = nv3->pgraph.m2mf.pitch_in; + uint32_t pitch_out = nv3->pgraph.m2mf.pitch_out; + + // pitch out surely can't be 0 + if (pitch_out == 0) + pitch_out = pitch_in; + + uint32_t bytes_per_scanline = nv3->pgraph.m2mf.scanline_length; + + uint8_t increment_in = (nv3->pgraph.m2mf.format) & 0x07; + uint8_t increment_out = (nv3->pgraph.m2mf.format >> NV3_M2MF_FORMAT_INPUT) & 0x07; + + for (uint32_t scanline = 0; scanline < nv3->pgraph.m2mf.num_scanlines; scanline++) + { + for (uint32_t pixel = offset_in; pixel < (offset_in + bytes_per_scanline); pixel += increment_in) + { + nv3->nvbase.svga.vram[offset_out] = nv3->nvbase.svga.vram[offset_in]; + offset_out += increment_out; + } + + offset_in += pitch_in; + offset_out += pitch_out; + } + + /* + switch (info_dma_target) + { + // for M2MF only NVM target node is used. + + case NV3_DMA_TARGET_NODE_VRAM: + + + uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; + + break; + case NV3_DMA_TARGET_NODE_PCI: + case NV3_DMA_TARGET_NODE_AGP: + // Idk how to implement increments of more than 1 but only 1 increments seem to be used with these. + uint32_t size_in = nv3->pgraph.m2mf.num_scanlines * nv3->pgraph.m2mf.pitch_in; + uint32_t size_out = nv3->pgraph.m2mf.num_scanlines * nv3->pgraph.m2mf.pitch_out; + + uint8_t* page_in = calloc(1, size_in); + + for (uint32_t scanline = 0; scanline < nv3->pgraph.m2mf.num_scanlines; scanline++) { - nv_log("Executed method NV3_SET_NOTIFY with nv3->pgraph.notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); - nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); - nv3_debug_ramin_print_context_info(param, context); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - // disable - nv3->pgraph.notify_pending = false; - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - /* may need to disable fifo in this state */ - return; } - // set a notify as pending. - nv3->pgraph.notifier = param; - nv3->pgraph.notify_pending = true; + dma_bm_read(offset_in, page_in, size_in, size_in); + dma_bm_write(offset_out, page_in, size_out, size_out); + break; - default: - nv_log("Shared Generic Methods: Invalid or Unimplemented method 0x%04x", method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; } +*/ + // we're done + nv3->pgraph.notify_pending = false; } @@ -121,16 +208,16 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t switch (info_notification_target) { - case NV3_NOTIFICATION_TARGET_NVM: + case NV3_DMA_TARGET_NODE_VRAM: nv_log_verbose_only("Notification Target: VRAM\n"); break; - case NV3_NOTIFICATION_TARGET_CART: + case NV3_DMA_TARGET_NODE_CART: nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); break; - case NV3_NOTIFICATION_TARGET_PCI: + case NV3_DMA_TARGET_NODE_PCI: (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); break; - case NV3_NOTIFICATION_TARGET_AGP: + case NV3_DMA_TARGET_NODE_AGP: (nv3->nvbase.bus_generation == nv_bus_agp_1x || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); break; @@ -166,7 +253,7 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t switch (info_notification_target) { - case NV3_NOTIFICATION_TARGET_NVM: + case NV3_DMA_TARGET_NODE_VRAM: uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; @@ -176,8 +263,8 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t vram_32[final_address + 2] = notify.info32; vram_32[final_address + 3] = (notify.info16 | notify.status); break; - case NV3_NOTIFICATION_TARGET_PCI: - case NV3_NOTIFICATION_TARGET_AGP: + case NV3_DMA_TARGET_NODE_PCI: + case NV3_DMA_TARGET_NODE_AGP: dma_bm_write(final_address, (uint8_t*)¬ify, sizeof(nv3_notification_t), 4); break; } From c12db12ec09b3f3243c031d7ab11a565bf8043a9 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 27 Aug 2025 17:35:07 +0100 Subject: [PATCH 214/274] fix ui compile --- src/qt/qt_mainwindow.ui | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index 752389779..9b1586104 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -895,6 +895,8 @@ &Pen + + GPU Debug - VRAM Viewer From ed9380c346cff01901c365156e444fd7c769f0c5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Wed, 27 Aug 2025 20:00:01 +0100 Subject: [PATCH 215/274] fully fix compile --- src/qt/qt_mainwindow.ui | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index 9b1586104..68f2c43b5 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -897,6 +897,11 @@ &Pen + + + &CGA composite settings... + + GPU Debug - VRAM Viewer From d8bbb1c1f2dc214eafdc9d4c2ce3d843774b75a4 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 31 Aug 2025 16:19:10 +0100 Subject: [PATCH 216/274] Merge alls hit from nvplayground --- src/include/86box/nv/vid_nv1.h | 161 +++++++++++++++++++++++++++++ src/include/86box/nv/vid_nv4.h | 141 +++++++++++++++++++++++++ src/include/86box/video.h | 3 + src/video/CMakeLists.txt | 8 ++ src/video/nv/nv1/nv1_core.c | 110 ++++++++++++++++++++ src/video/nv/nv1/nv1_core_config.c | 133 ++++++++++++++++++++++++ src/video/nv/nv4/nv4_core.c | 86 +++++++++++++++ src/video/nv/nv4/nv4_core_config.c | 96 +++++++++++++++++ src/video/vid_table.c | 3 + 9 files changed, 741 insertions(+) create mode 100644 src/include/86box/nv/vid_nv1.h create mode 100644 src/include/86box/nv/vid_nv4.h create mode 100644 src/video/nv/nv1/nv1_core.c create mode 100644 src/video/nv/nv1/nv1_core_config.c create mode 100644 src/video/nv/nv4/nv4_core.c create mode 100644 src/video/nv/nv4/nv4_core_config.c diff --git a/src/include/86box/nv/vid_nv1.h b/src/include/86box/nv/vid_nv1.h new file mode 100644 index 000000000..98518e530 --- /dev/null +++ b/src/include/86box/nv/vid_nv1.h @@ -0,0 +1,161 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Quadratic Heaven + * + * Authors: Connor Hyde + * + * Copyright 2024-2025 Connor Hyde + */ + +#pragma once + +#include +#include + +extern const device_config_t nv1_config[]; // Config for RIVA 128 (revision A/B) + +// +// PCI Bus Information +// + +#define NV1_PCI_BAR0_SIZE 0xFFFFFF + +// +// VRAM +// +#define NV1_VRAM_SIZE_1MB 0x100000 +#define NV1_VRAM_SIZE_2MB 0x200000 +#define NV1_VRAM_SIZE_4MB 0x400000 + +// Video BIOS +#define NV1_VBIOS_E3D_2X00 "roms/video/nvidia/nv1/Diamond_Edge_3D_2x00.BIN" +#define NV1_VBIOS_E3D_3X00 "roms/video/nvidia/nv1/Diamond_Edge_3D_3400_BIOS_M27C256.BIN" + +// +// PMC +// +#define NV1_PMC_BOOT_0 0x0 +#define NV1_PMC_BOOT_0_REVISION 0 + +#define NV1_PMC_BOOT_0_REVISION_A 0x0 // Prototype (1994) +#define NV1_PMC_BOOT_0_REVISION_B1 0x0 // Prototype (early 1995) +#define NV1_PMC_BOOT_0_REVISION_B2 0x0 // Prototype (mid 1995) +#define NV1_PMC_BOOT_0_REVISION_B3 0x0 // Final? +#define NV1_PMC_BOOT_0_REVISION_C 0x0 // Final? + +#define NV1_PMC_BOOT_0_IMPLEMENTATION 8 +#define NV1_PMC_BOOT_0_IMPLEMENTATION_NV0 0x1 // Nvidia Hardware Simulator (1993-1994) +#define NV1_PMC_BOOT_0_IMPLEMENTATION_NV1_D32 0x2 // NV1 + DRAM + SGS-Thomson STG-1732/1764 DAC +#define NV1_PMC_BOOT_0_IMPLEMENTATION_NV1_V32 0x3 // NV1 + VRAM + SGS-Thomson STG-1732/1764 DAC +#define NV1_PMC_BOOT_0_IMPLEMENTATION_PICASSO 0x4 // NV1 + VRAM + NV 128-bit DAC + + +// Defines the NV architecture version (NV1/NV2/...) +#define NV1_PMC_BOOT_0_ARCHITECTURE 16 +#define NV1_PMC_BOOT_0_ARCHITECTURE_NV0 0x0 // Nvidia Hardware Simulator (1993-1994) +#define NV1_PMC_BOOT_0_ARCHITECTURE_NV1 0x1 // NV1 (1995) +#define NV1_PMC_BOOT_0_ARCHITECTURE_NV2 0x2 // Mutara (1996, cancelled) + +#define NV1_PMC_DEBUG_0 0x80 + +#define NV1_PMC_INTR_0 0x100 +#define NV1_PMC_INTR_EN_0 0x140 + +#define NV1_PMC_INTR_EN_0_INTA 0 +#define NV1_PMC_INTR_EN_0_INTB 4 +#define NV1_PMC_INTR_EN_0_INTC 8 +#define NV1_PMC_INTR_EN_0_INTD 12 + +#define NV1_PMC_INTR_EN_0_DISABLED 0x0 +#define NV1_PMC_INTR_EN_0_HARDWARE 0x1 +#define NV1_PMC_INTR_EN_0_SOFTWARE 0x2 +#define NV1_PMC_INTR_EN_0_ALL 0x3 // (HARDWARE | SOFTWARE) + +#define NV1_PMC_INTR_READ 0x160 + +//TODO: DEFINE bits +#define NV1_PMC_ENABLE 0x200 + +// +// PRAMIN +// + +#define NV1_RAMIN_START 0x100000 + +// +// PAUTH +// Scary nvidia mode +// + +// Read only +#define NV1_PAUTH_DEBUG_0 0x605080 +#define NV1_PAUTH_DEBUG_0_BREACH_DETECTED 0 +#define NV1_PAUTH_DEBUG_0_EEPROM_INVALID 4 + +#define NV1_PAUTH_CHIP_TOKEN_0 0x605400 +#define NV1_PAUTH_CHIP_TOKEN_1 0x605404 +#define NV1_PAUTH_PASSWORD_0(i) 0x605800+(i*16) +#define NV1_PAUTH_PASSWORD_1(i) 0x605804+(i*16) +#define NV1_PAUTH_PASSWORD_2(i) 0x605808+(i*16) +#define NV1_PAUTH_PASSWORD_3(i) 0x60580C+(i*16) + +#define NV1_PAUTH_PASSWORD_SIZE 128 + +// +// PFB +// + +#define NV1_PFB_BOOT_0 0x600000 + +#define NV1_PFB_BOOT_0_RAM_AMOUNT 0 +#define NV1_PFB_BOOT_0_RAM_AMOUNT_1MB 0x0 +#define NV1_PFB_BOOT_0_RAM_AMOUNT_2MB 0x1 +#define NV1_PFB_BOOT_0_RAM_AMOUNT_4MB 0x2 + +// +// PEXTDEV +// + +#define NV1_STRAPS 0x608000 +#define NV1_STRAPS_STRAP_VENDOR 0 + +// +// PRAM+RAMIN +// + +#define NV1_PRAM_CONFIG 0x602200 +#define NV1_PRAM_CONFIG_SIZE 0 +#define NV1_PRAM_CONFIG_12KB 0 +#define NV1_PRAM_CONFIG_20KB 1 +#define NV1_PRAM_CONFIG_36KB 2 +#define NV1_PRAM_CONFIG_68KB 3 + +// Position of RAMPW in RAMIN +#define NV1_RAMPW_POSITION_CONFIG0 0x2c00 +#define NV1_RAMPW_POSITION_CONFIG1 0x4c00 +#define NV1_RAMPW_POSITION_CONFIG2 0x8c00 +#define NV1_RAMPW_POSITION_CONFIG3 0x10c00 + +// Static RAMPW mirror +#define NV1_PRAMPW 0x606000 +#define NV1_RAMPW_SIZE 0x400 + +// +// PROM +// +#define NV1_PROM 0x601000 +#define NV1_PROM_SIZE 32768 + +// Device Core +void nv1_init(); +void nv1_close(void* priv); +void nv1_speed_changed(void *priv); +void nv1_draw_cursor(svga_t* svga, int32_t drawline); +void nv1_recalc_timings(svga_t* svga); +void nv1_force_redraw(void* priv); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h new file mode 100644 index 000000000..8f2a20026 --- /dev/null +++ b/src/include/86box/nv/vid_nv4.h @@ -0,0 +1,141 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Riva TNT hardware defines + * + * Authors: Connor Hyde + * + * Copyright 2024-2025 Connor Hyde + */ + + +#pragma once + +extern const device_config_t nv4_config[]; // Config for RIVA 128 (revision A/B) + +// +// General +// +#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) +#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) +#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB +#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB +#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only + +#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! + +// +// VBIOS +// +#define NV4_VBIOS_STB_REVA "roms/video/nvidia/nv4/NV4_STB_velocity.rom" + +// +// PMC +// + +#define NV4_PMC_START 0x0 + +#define NV4_PMC_INTR 0x100 +#define NV4_PMC_INTR_PMEDIA_PENDING 4 +#define NV4_PMC_INTR_PFIFO_PENDING 8 +#define NV4_PMC_INTR_PGRAPH_PENDING 12 +#define NV4_PMC_INTR_PVIDEO_PENDING 16 +#define NV4_PMC_INTR_PTIMER_PENDING 20 +#define NV4_PMC_INTR_PCRTC_PENDING 24 +#define NV4_PMC_INTR_PBUS_PENDING 28 +#define NV4_PMC_INTR_SOFTWARE_PENDING 31 + +#define NV4_PMC_INTR_EN 0x140 +#define NV4_PMC_INTR_EN_DISABLED 0x0 +#define NV4_PMC_INTR_EN_SOFTWARE 0x1 +#define NV4_PMC_INTR_EN_HARDWARE 0x2 +#define NV4_PMC_INTR_EN_ALL 0x3 + +#define NV4_PMC_BOOT 0x0 +#define NV4_PMC_ENABLE 0x200 +#define NV4_PMC_ENABLE_PMEDIA 4 // Enable mediaport external MPEG decoder engine +#define NV4_PMC_ENABLE_PFIFO 8 // Enable FIFO +#define NV4_PMC_ENABLE_PGRAPH 12 +#define NV4_PMC_ENABLE_PPMI 16 +#define NV4_PMC_ENABLE_PFB 20 +#define NV4_PMC_ENABLE_PCRTC 24 +#define NV4_PMC_ENABLE_PVIDEO 28 + +// +// PFB +// + +#define NV4_PFB_START 0x100000 +#define NV4_PFB_BOOT 0x100000 +#define NV4_PFB_BOOT_RAM_AMOUNT 0 +#define NV4_PFB_BOOT_RAM_AMOUNT_2MB 0x0 +#define NV4_PFB_BOOT_RAM_AMOUNT_4MB 0x1 +#define NV4_PFB_BOOT_RAM_AMOUNT_8MB 0x2 +#define NV4_PFB_BOOT_RAM_AMOUNT_16MB 0x3 +#define NV5_PFB_BOOT_RAM_AMOUNT_32MB 0x0 + +#define NV4_PSTRAPS 0x101000 + +#define NV4_PSTRAPS_CRYSTAL 6 +#define NV4_PSTRAPS_CRYSTAL_13500K 0x0 +#define NV4_PSTRAPS_CRYSTAL_14318180 0x1 + +// +// PRAMDAC +// + +#define NV4_PRAMDAC_START 0x680300 +#define NV4_PRAMDAC_CURSOR_START_POSITION 0x680300 + +#define NV4_PRAMDAC_CURSOR_SIZE_X 32 +#define NV4_PRAMDAC_CURSOR_SIZE_Y 32 + +// Same for all 3 clocks +#define NV4_PRAMDAC_CLOCK_VDIV 0 +#define NV4_PRAMDAC_CLOCK_NDIV 8 +#define NV4_PRAMDAC_CLOCK_PDIV 16 + +#define NV4_PRAMDAC_CLOCK_CORE 0x680500 // NVPLL +#define NV4_PRAMDAC_CLOCK_MEMORY 0x680504 +#define NV4_PRAMDAC_CLOCK_PIXEL 0x680508 +#define NV4_PRAMDAC_COEFF_SELECT 0x68050C +#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE 0 +#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 +#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE_VIP 0x1 +#define NV4_PRAMDAC_COEFF_SELECT_SOURCE 8 // Bit not set = hardware, otherwise software +#define NV4_PRAMDAC_COEFF_SELECT_MPLL_IS_SOFTWARE 0x1 +#define NV4_PRAMDAC_COEFF_SELECT_VPLL_IS_SOFTWARE 0x2 +#define NV4_PRAMDAC_COEFF_SELECT_NVPLL_IS_SOFTWARE 0x4 +#define NV4_PRAMDAC_COEFF_SELECT_ALL_SOFTWARE 0x7 +#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV 16 +#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_NONE 0x0 +#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x1 +#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_PCLK 0x2 +#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_BOTH 0x3 +#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE 20 +#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE_EXT 0x0 +#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE_VIP 0x1 // VIP = Video Interface Port / Mediaport +#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO 24 +#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO_DB1 0x0 +#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO_DB2 0x1 +#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO 28 +#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO_DB1 0x0 +#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO_DB2 0x1 + +#define NV4_PRAMDAC_GENERAL_CONTROL 0x680600 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12 + +#define NV4_RAMIN_START 0x700000 // Nominal. In reality PROM is here on real NV4 + +// Device Core +void nv4_init(); +void nv4_close(void* priv); +void nv4_speed_changed(void *priv); +void nv4_draw_cursor(svga_t* svga, int32_t drawline); +void nv4_recalc_timings(svga_t* svga); +void nv4_force_redraw(void* priv); \ No newline at end of file diff --git a/src/include/86box/video.h b/src/include/86box/video.h index 4271c4f78..fd8d79e8d 100644 --- a/src/include/86box/video.h +++ b/src/include/86box/video.h @@ -626,10 +626,13 @@ extern const device_t voodoo_3_3500_se_agp_device; extern const device_t voodoo_3_3500_si_agp_device; extern const device_t velocity_100_agp_device; extern const device_t velocity_200_agp_device; +extern const device_t nv1_device_edge2k; +extern const device_t nv1_device_edge3k; extern const device_t nv3_device_pci; extern const device_t nv3_device_agp; extern const device_t nv3t_device_pci; extern const device_t nv3t_device_agp; +extern const device_t nv4_device_agp; /* Wyse 700 */ extern const device_t wy700_device; diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 4e490094c..edd5de3a9 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -139,6 +139,10 @@ add_library(vid OBJECT nv/nv_base.c nv/nv_rivatimer.c + # NVidia NV1 + nv/nv1/nv1_core.c + nv/nv1/nv1_core_config.c + # NVidia RIVA 128 - Subsystems nv/nv3/nv3_core.c nv/nv3/nv3_core_config.c @@ -192,6 +196,10 @@ add_library(vid OBJECT nv/nv3/render/nv3_render_primitives.c nv/nv3/render/nv3_render_blit.c + # NVidia RIVA TNT/TNT2 - Core + nv/nv4/nv4_core.c + nv/nv4/nv4_core_config.c + # Generic vid_bochs_vbe.c ) diff --git a/src/video/nv/nv1/nv1_core.c b/src/video/nv/nv1/nv1_core.c new file mode 100644 index 000000000..3de528b26 --- /dev/null +++ b/src/video/nv/nv1/nv1_core.c @@ -0,0 +1,110 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 bringup and device emulation. + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv1.h> + + +void nv1_init() +{ + +} + +void* nv1_init_edge2k(const device_t *info) +{ + +} + +void* nv1_init_edge3k(const device_t *info) +{ + +} + +void nv1_close(void* priv) +{ + +} + +void nv1_speed_changed(void *priv) +{ + +} + +void nv1_draw_cursor(svga_t* svga, int32_t drawline) +{ + +} + +void nv1_recalc_timings(svga_t* svga) +{ + +} + +void nv1_force_redraw(void* priv) +{ + +} + +// See if the bios rom is available. +int32_t nv1_available(void) +{ + return (rom_present(NV1_VBIOS_E3D_2X00) + || rom_present(NV1_VBIOS_E3D_3X00)); +} + +// NV3 (RIVA 128) +// PCI +// 2MB or 4MB VRAM +const device_t nv1_device_edge2k = +{ + .name = "nVIDIA NV1 [Diamond Edge 3D 2x00] [Not Direct3D Compatible]", + .internal_name = "nv1_edge2k", + .flags = DEVICE_PCI, + .local = 0, + .init = nv1_init_edge2k, + .close = nv1_close, + .speed_changed = nv1_speed_changed, + .force_redraw = nv1_force_redraw, + .available = nv1_available, + .config = nv1_config, +}; + +// NV3 (RIVA 128) +// AGP +// 2MB or 4MB VRAM +const device_t nv1_device_edge3k = +{ + .name = "nVIDIA NV1 [Diamond Edge 3D 3x00] [Not Direct3D Compatible]", + .internal_name = "nv1_edge3k", + .flags = DEVICE_PCI, + .local = 0, + .init = nv1_init_edge3k, + .close = nv1_close, + .speed_changed = nv1_speed_changed, + .force_redraw = nv1_force_redraw, + .available = nv1_available, + .config = nv1_config, +}; diff --git a/src/video/nv/nv1/nv1_core_config.c b/src/video/nv/nv1/nv1_core_config.c new file mode 100644 index 000000000..460067f6f --- /dev/null +++ b/src/video/nv/nv1/nv1_core_config.c @@ -0,0 +1,133 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Provides NV4 configuration + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv1.h> + +const device_config_t nv1_config[] = +{ + // Memory configuration + { + .name = "vram_size", + .description = "VRAM Size", + .type = CONFIG_SELECTION, + .default_int = NV1_VRAM_SIZE_4MB, + .selection = + { + // I thought this was never released, but it seems that at least one was released: + // The card was called the "NEC G7AGK" + { + .description = "1 MB", + .value = NV1_VRAM_SIZE_1MB, + }, + { + .description = "2 MB", + .value = NV1_VRAM_SIZE_2MB, + }, + { + .description = "4 MB", + .value = NV1_VRAM_SIZE_4MB, + }, + } + + }, + // Multithreading configuration + { + + .name = "pgraph_threads", +#ifndef RELEASE_BUILD + .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", +#else + .description = "Render threads", +#endif + .type = CONFIG_SELECTION, + .default_int = 1, // todo: change later + .selection = + { + { + .description = "1 thread (Only use if issues appear with more threads)", + .value = 1, + }, + { + .description = "2 threads", + .value = 2, + }, + { + .description = "4 threads", + .value = 4, + }, + { + .description = "8 threads", + .value = 8, + }, + }, + }, + { + .name = "RAMDAC Type", + .description = "SGS-Thomson RAMDAC type", + .default_int = 0x1764, + .type = CONFIG_SELECTION, + .selection = + { + { + .description = "SGS-Thomson STG-1732X", + .value = 0x1732, + }, + { + .description = "SGS-Thomson STG-1764X/NVDAC64", + .value = 0x1764, + }, + } + }, + { + .name = "Chip type", + .description = "Chip type", + .default_int = 0x1, + .type = CONFIG_SELECTION, + .selection = + { + { + .description = "SGS-Thomson STG-2000", + .value = 0x2000, + }, + { + .description = "Nvidia NV1", + .value = 0x1, + }, + } + }, +#ifndef RELEASE_BUILD + { + .name = "nv_debug_fulllog", + .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", + .type = CONFIG_BINARY, + .default_int = 0, + }, +#endif + { + .type = CONFIG_END + } +}; \ No newline at end of file diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c new file mode 100644 index 000000000..2af47f22a --- /dev/null +++ b/src/video/nv/nv4/nv4_core.c @@ -0,0 +1,86 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV3 bringup and device emulation. + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv4.h> + +void nv4_init() +{ + +} + +void* nv4_init_stb4400(const device_t *info) +{ + +} + +void nv4_close(void* priv) +{ + +} + +void nv4_speed_changed(void *priv) +{ + +} + +void nv4_draw_cursor(svga_t* svga, int32_t drawline) +{ + +} + +void nv4_recalc_timings(svga_t* svga) +{ + +} + +void nv4_force_redraw(void* priv) +{ + +} + +// See if the bios rom is available. +int32_t nv4_available(void) +{ + return (rom_present(NV4_VBIOS_STB_REVA)); +} + +// NV3 (RIVA 128) +// AGP +// 8MB or 16MB VRAM +const device_t nv4_device_agp = +{ + .name = "nVIDIA RIVA TNT [STB Velocity 4400]", + .internal_name = "nv4_stb4400", + .flags = DEVICE_AGP, + .local = 0, + .init = nv4_init_stb4400, + .close = nv4_close, + .speed_changed = nv4_speed_changed, + .force_redraw = nv4_force_redraw, + .available = nv4_available, + .config = nv4_config, +}; diff --git a/src/video/nv/nv4/nv4_core_config.c b/src/video/nv/nv4/nv4_core_config.c new file mode 100644 index 000000000..ea9ef9332 --- /dev/null +++ b/src/video/nv/nv4/nv4_core_config.c @@ -0,0 +1,96 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Provides NV4 configuration + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv4.h> + +const device_config_t nv4_config[] = +{ + // Memory configuration + { + .name = "vram_size", + .description = "VRAM Size", + .type = CONFIG_SELECTION, + .default_int = NV4_VRAM_SIZE_16MB, + .selection = + { + // I thought this was never released, but it seems that at least one was released: + // The card was called the "NEC G7AGK" + { + .description = "8 MB", + .value = NV4_VRAM_SIZE_8MB, + }, + + { + .description = "16 MB", + .value = NV4_VRAM_SIZE_16MB, + }, + } + + }, + // Multithreading configuration + { + + .name = "pgraph_threads", +#ifndef RELEASE_BUILD + .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", +#else + .description = "Render threads", +#endif + .type = CONFIG_SELECTION, + .default_int = 1, // todo: change later + .selection = + { + { + .description = "1 thread (Only use if issues appear with more threads)", + .value = 1, + }, + { + .description = "2 threads", + .value = 2, + }, + { + .description = "4 threads", + .value = 4, + }, + { + .description = "8 threads", + .value = 8, + }, + }, + }, +#ifndef RELEASE_BUILD + { + .name = "nv_debug_fulllog", + .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", + .type = CONFIG_BINARY, + .default_int = 0, + }, +#endif + { + .type = CONFIG_END + } +}; \ No newline at end of file diff --git a/src/video/vid_table.c b/src/video/vid_table.c index db05e13ab..e2b9b3542 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -261,10 +261,13 @@ video_cards[] = { { .device = &compaq_voodoo_3_3500_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &voodoo_3_3500_se_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &voodoo_3_3500_si_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, + { .device = &nv1_device_edge2k, .flags = VIDEO_FLAG_TYPE_NONE }, + { .device = &nv1_device_edge3k, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &nv3_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &nv3_device_pci, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &nv3t_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &nv3t_device_pci, .flags = VIDEO_FLAG_TYPE_NONE }, + { .device = &nv4_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = NULL, .flags = VIDEO_FLAG_TYPE_NONE } // clang-format on }; From e9b09082b91a548277ed45a86144d572361e18bd Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 31 Aug 2025 16:24:41 +0100 Subject: [PATCH 217/274] remove duplicate actions --- src/qt/qt_mainwindow.ui | 80 ----------------------------------------- 1 file changed, 80 deletions(-) diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index 194c595e1..8f5f8c1cf 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -1125,86 +1125,6 @@ &1x - - - true - - - &0.5x - - - - - true - - - &1x - - - - - true - - - 1.&5x - - - - - true - - - &2x - - - - - true - - - &3x - - - - - true - - - &4x - - - - - true - - - &5x - - - - - true - - - &6x - - - - - true - - - &7x - - - - - true - - - &8x - - From 5f6efd5742f55f9e14d11c4c498f77968cbf833d Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 31 Aug 2025 23:51:16 +0100 Subject: [PATCH 218/274] Add nv4 defines --- src/include/86box/nv/vid_nv1.h | 7 + src/include/86box/nv/vid_nv4.h | 120 +- src/include/86box/nv/vid_nv4_defines.h | 4314 ++++++++++++++++++++++++ 3 files changed, 4330 insertions(+), 111 deletions(-) create mode 100644 src/include/86box/nv/vid_nv4_defines.h diff --git a/src/include/86box/nv/vid_nv1.h b/src/include/86box/nv/vid_nv1.h index 98518e530..9d08bb186 100644 --- a/src/include/86box/nv/vid_nv1.h +++ b/src/include/86box/nv/vid_nv1.h @@ -17,6 +17,7 @@ #include #include +#include <86Box/nv/vid_nv.h> extern const device_config_t nv1_config[]; // Config for RIVA 128 (revision A/B) @@ -152,6 +153,12 @@ extern const device_config_t nv1_config[]; // Confi #define NV1_PROM 0x601000 #define NV1_PROM_SIZE 32768 +// Structures +typedef struct nv1_s +{ + nv_base_t nvbase; // Base Nvidia structure +} nv1_t; + // Device Core void nv1_init(); void nv1_close(void* priv); diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 8f2a20026..7fef843d4 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -16,121 +16,19 @@ #pragma once +#include +#include +#include <86Box/nv/vid_nv.h> +#include <86Box/nv/vid_nv4_defines.h> extern const device_config_t nv4_config[]; // Config for RIVA 128 (revision A/B) -// -// General -// -#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) -#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) -#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB -#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB -#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only -#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! -// -// VBIOS -// -#define NV4_VBIOS_STB_REVA "roms/video/nvidia/nv4/NV4_STB_velocity.rom" - -// -// PMC -// - -#define NV4_PMC_START 0x0 - -#define NV4_PMC_INTR 0x100 -#define NV4_PMC_INTR_PMEDIA_PENDING 4 -#define NV4_PMC_INTR_PFIFO_PENDING 8 -#define NV4_PMC_INTR_PGRAPH_PENDING 12 -#define NV4_PMC_INTR_PVIDEO_PENDING 16 -#define NV4_PMC_INTR_PTIMER_PENDING 20 -#define NV4_PMC_INTR_PCRTC_PENDING 24 -#define NV4_PMC_INTR_PBUS_PENDING 28 -#define NV4_PMC_INTR_SOFTWARE_PENDING 31 - -#define NV4_PMC_INTR_EN 0x140 -#define NV4_PMC_INTR_EN_DISABLED 0x0 -#define NV4_PMC_INTR_EN_SOFTWARE 0x1 -#define NV4_PMC_INTR_EN_HARDWARE 0x2 -#define NV4_PMC_INTR_EN_ALL 0x3 - -#define NV4_PMC_BOOT 0x0 -#define NV4_PMC_ENABLE 0x200 -#define NV4_PMC_ENABLE_PMEDIA 4 // Enable mediaport external MPEG decoder engine -#define NV4_PMC_ENABLE_PFIFO 8 // Enable FIFO -#define NV4_PMC_ENABLE_PGRAPH 12 -#define NV4_PMC_ENABLE_PPMI 16 -#define NV4_PMC_ENABLE_PFB 20 -#define NV4_PMC_ENABLE_PCRTC 24 -#define NV4_PMC_ENABLE_PVIDEO 28 - -// -// PFB -// - -#define NV4_PFB_START 0x100000 -#define NV4_PFB_BOOT 0x100000 -#define NV4_PFB_BOOT_RAM_AMOUNT 0 -#define NV4_PFB_BOOT_RAM_AMOUNT_2MB 0x0 -#define NV4_PFB_BOOT_RAM_AMOUNT_4MB 0x1 -#define NV4_PFB_BOOT_RAM_AMOUNT_8MB 0x2 -#define NV4_PFB_BOOT_RAM_AMOUNT_16MB 0x3 -#define NV5_PFB_BOOT_RAM_AMOUNT_32MB 0x0 - -#define NV4_PSTRAPS 0x101000 - -#define NV4_PSTRAPS_CRYSTAL 6 -#define NV4_PSTRAPS_CRYSTAL_13500K 0x0 -#define NV4_PSTRAPS_CRYSTAL_14318180 0x1 - -// -// PRAMDAC -// - -#define NV4_PRAMDAC_START 0x680300 -#define NV4_PRAMDAC_CURSOR_START_POSITION 0x680300 - -#define NV4_PRAMDAC_CURSOR_SIZE_X 32 -#define NV4_PRAMDAC_CURSOR_SIZE_Y 32 - -// Same for all 3 clocks -#define NV4_PRAMDAC_CLOCK_VDIV 0 -#define NV4_PRAMDAC_CLOCK_NDIV 8 -#define NV4_PRAMDAC_CLOCK_PDIV 16 - -#define NV4_PRAMDAC_CLOCK_CORE 0x680500 // NVPLL -#define NV4_PRAMDAC_CLOCK_MEMORY 0x680504 -#define NV4_PRAMDAC_CLOCK_PIXEL 0x680508 -#define NV4_PRAMDAC_COEFF_SELECT 0x68050C -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE 0 -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_SOURCE_VIP 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_SOURCE 8 // Bit not set = hardware, otherwise software -#define NV4_PRAMDAC_COEFF_SELECT_MPLL_IS_SOFTWARE 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_VPLL_IS_SOFTWARE 0x2 -#define NV4_PRAMDAC_COEFF_SELECT_NVPLL_IS_SOFTWARE 0x4 -#define NV4_PRAMDAC_COEFF_SELECT_ALL_SOFTWARE 0x7 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV 16 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_NONE 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_PCLK 0x2 -#define NV4_PRAMDAC_COEFF_SELECT_VS_PCLK_TV_BOTH 0x3 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE 20 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE_EXT 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_SOURCE_VIP 0x1 // VIP = Video Interface Port / Mediaport -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO 24 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO_DB1 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_TVCLK_RATIO_DB2 0x1 -#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO 28 -#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO_DB1 0x0 -#define NV4_PRAMDAC_COEFF_SELECT_VCLK_RATIO_DB2 0x1 - -#define NV4_PRAMDAC_GENERAL_CONTROL 0x680600 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12 - -#define NV4_RAMIN_START 0x700000 // Nominal. In reality PROM is here on real NV4 +// Structures +typedef struct nv4_s +{ + nv_base_t nvbase; // Base Nvidia structure +} nv4_t; // Device Core void nv4_init(); diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h new file mode 100644 index 000000000..f7499e3a8 --- /dev/null +++ b/src/include/86box/nv/vid_nv4_defines.h @@ -0,0 +1,4314 @@ +#pragma once + +#include +#include + +// +// General +// +#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) +#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) +#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB +#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB +#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only + +#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! + +// +// VBIOS +// +#define NV4_VBIOS_STB_REVA "roms/video/nvidia/nv4/NV4_STB_velocity.rom" + +#define NV4_PRMIO_START 0x7000 +#define NV4_PRMIO_END 0x7FFF +#define NV4_PRMIO_RMA_ID 0x7100 +#define NV4_PRMIO_RMA_ID_CODE 0 +#define NV4_PRMIO_RMA_ID_CODE_VALID 0x2B16D065 +#define NV4_PRMIO_RMA_PTR 0x7104 +#define NV4_PRMIO_RMA_PTR_ADDRESS 2 +#define NV4_PRMIO_RMA_DATA 0x7108 +#define NV4_PRMIO_RMA_DATA_PORT 0 +#define NV4_PRMIO_RMA_DATA32 0x710C +#define NV4_PRMIO_RMA_DATA32_BYTE2 16 +#define NV4_PRMIO_RMA_DATA32_BYTE1 8 +#define NV4_PRMIO_RMA_DATA32_BYTE0 0 + +#define NV4_PRAMDAC_START 0x680300 +#define NV4_PRAMDAC_END 0x680FFF + +#define NV4_PRAMDAC_CU_START_POS 0x680300 +#define NV4_PRAMDAC_CU_START_POS_X 0 +#define NV4_PRAMDAC_CU_START_POS_Y 16 +#define NV4_PRAMDAC_NVPLL_COEFF 0x680500 +#define NV4_PRAMDAC_NVPLL_COEFF_MDIV 0 +#define NV4_PRAMDAC_NVPLL_COEFF_NDIV 8 +#define NV4_PRAMDAC_NVPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_MPLL_COEFF 0x680504 +#define NV4_PRAMDAC_MPLL_COEFF_MDIV 0 +#define NV4_PRAMDAC_MPLL_COEFF_NDIV 8 +#define NV4_PRAMDAC_MPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_VPLL_COEFF 0x680508 +#define NV4_PRAMDAC_VPLL_COEFF_MDIV 0 +#define NV4_PRAMDAC_VPLL_COEFF_NDIV 8 +#define NV4_PRAMDAC_VPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_PLL_COEFF_SELECT 0x68050C +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_VIP 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE 8 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_DEFAULT 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL 0x2 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL 0x4 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_ALL 0x7 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV 16 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_NONE 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_PCLK 0x2 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_BOTH 0x3 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE 20 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE_EXT 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE_VIP 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO 24 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB1 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB2 0x1 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x0 +#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x1 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL 0x680510 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_VALUE 0 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_VAL 0x44E +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN 12 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_ON 0x0 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_MPLL 0x1 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_VPLL 0x2 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_NVPLL 0x4 +#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_OFF 0x7 +#define NV4_PRAMDAC_PLL_TEST_COUNTER 0x680514 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NOOFIPCLKS 0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VALUE 0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE 16 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE_DEASSERTED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE_ASSERTED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET 20 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET_DEASSERTED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET_ASSERTED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE 24 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_MCLK 0x2 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_VCLK 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_NVCLK 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIV_RST 28 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_DEASSERTED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_ASSERTED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK 29 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_NOTLOCKED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCKED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK 30 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_NOTLOCKED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCKED 0x1 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK 31 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_NOTLOCKED 0x0 +#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCKED 0x1 +#define NV4_PRAMDAC_PALETTE_TEST 0x680518 +#define NV4_PRAMDAC_PALETTE_TEST_BLUE_DATA 0 +#define NV4_PRAMDAC_PALETTE_TEST_GREEN_DATA 8 +#define NV4_PRAMDAC_PALETTE_TEST_RED_DATA 16 +#define NV4_PRAMDAC_PALETTE_TEST_MODE 24 +#define NV4_PRAMDAC_PALETTE_TEST_MODE_8BIT 0x0 +#define NV4_PRAMDAC_PALETTE_TEST_MODE_24BIT 0x1 +#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC 28 +#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC_READWRITE 0x0 +#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC_WRITEONLY 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL 0x680600 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT 0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_24 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_31 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX 4 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_OFF 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_POS 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_NEG 0x2 +#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON 0x3 +#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8 +#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSEL 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_NOTSEL 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_15 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_16 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_24 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_30 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16 +#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION 17 +#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_BPC 20 +#define NV4_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24 +#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x1 +#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28 +#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x0 +#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x1 +#define NV4_PRAMDAC_PALETTE_RECOVERY 0x680604 +#define NV4_PRAMDAC_PALETTE_RECOVERY_ACTIVE_ADDRESS 0 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER 8 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_RED 0x1 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_GREEN 0x2 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_BLUE 0x4 +#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE 12 +#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_WRITE 0x0 +#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_READ 0x3 +#define NV4_PRAMDAC_PALETTE_RECOVERY_RED_DATA 16 +#define NV4_PRAMDAC_PALETTE_RECOVERY_GREEN_DATA 24 +#define NV4_PRAMDAC_TEST_CONTROL 0x680608 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET 0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET_DEASSERTED 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET_ASSERTED 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE 4 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL 8 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_BLUE 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_GREEN 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_RED 0x2 +#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN 12 +#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN_DEASSERTED 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC 16 +#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_ON 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_DACTM 20 +#define NV4_PRAMDAC_TEST_CONTROL_DACTM_NORMAL 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_DACTM_TEST 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH1 24 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH1_CLEAR 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH1_SET 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH31 25 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH31_CLEAR 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_TPATH31_SET 0x1 +#define NV4_PRAMDAC_TEST_CONTROL_SENSEB 28 +#define NV4_PRAMDAC_TEST_CONTROL_SENSEB_SOMELO 0x0 +#define NV4_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI 0x1 +#define NV4_PRAMDAC_CHECKSUM 0x68060C +#define NV4_PRAMDAC_CHECKSUM_VALUE 0 +#define NV4_PRAMDAC_TESTPOINT_DATA 0x680610 +#define NV4_PRAMDAC_TESTPOINT_DATA_RED 0 +#define NV4_PRAMDAC_TESTPOINT_DATA_GREEN 10 +#define NV4_PRAMDAC_TESTPOINT_DATA_BLUE 20 +#define NV4_PRAMDAC_TESTPOINT_DATA_BLACK 30 +#define NV4_PRAMDAC_TESTPOINT_DATA_NOTBLANK 31 +#define NV4_PRAMDAC_TV_SETUP 0x680700 +#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE 0 +#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE_SLAVE 0x0 +#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE_MASTER 0x1 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT 4 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_555 0x0 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_565 0x1 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_888 0x2 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_101010 0x3 +#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_YUV 0x4 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC 8 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_COMP 0x0 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_SCALER 0x1 +#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_VIP 0x2 +#define NV4_PRAMDAC_TV_SETUP_COMP_SRC 12 +#define NV4_PRAMDAC_TV_SETUP_COMP_SRC_SCALER 0x0 +#define NV4_PRAMDAC_TV_SETUP_COMP_SRC_NO_SCALER 0x1 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL 16 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_NONE 0x0 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_HSYNC 0x1 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_VSYNC 0x2 +#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_BOTH 0x3 +#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC 20 +#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC_LEAD 0x0 +#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC_TRAIL 0x1 +#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS 24 +#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS_7_0 0x0 +#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS_11_4 0x1 +#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD 28 +#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD_0 0x0 +#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD_1 0x1 +#define NV4_PRAMDAC_TV_VBLANK_START 0x680704 +#define NV4_PRAMDAC_TV_VBLANK_START_VAL 0 +#define NV4_PRAMDAC_TV_VBLANK_END 0x680708 +#define NV4_PRAMDAC_TV_VBLANK_END_VAL 0 +#define NV4_PRAMDAC_TV_HBLANK_START 0x68070C +#define NV4_PRAMDAC_TV_HBLANK_START_VAL 0 +#define NV4_PRAMDAC_TV_HBLANK_END 0x680710 +#define NV4_PRAMDAC_TV_HBLANK_END_VAL 0 +#define NV4_PRAMDAC_BLANK_COLOR 0x680714 +#define NV4_PRAMDAC_BLANK_COLOR_VAL 0 +#define NV4_PRAMDAC_TV_CHECKSUM 0x680718 +#define NV4_PRAMDAC_TV_CHECKSUM_VAL 0 +#define NV4_PRAMDAC_TV_VSYNC 28 +#define NV4_PRAMDAC_TV_VSYNC_ACTIVE 0x0 +#define NV4_PRAMDAC_TV_VSYNC_INACTIVE 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL 0x68071c +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET 0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_DEASSERTED 0x0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_ASSERTED 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE 4 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL 8 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_7_0 0x0 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_15_8 0x1 +#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_23_16 0x2 + +#define NV4_USER_DAC_START 0x681200 +#define NV4_USER_DAC_END 0x681FFF + +#define NV4_USER_DAC_PIXEL_MASK 0x6813C6 +#define NV4_USER_DAC_PIXEL_MASK_VALUE 0 +#define NV4_USER_DAC_PIXEL_MASK_MASK 0xFF +#define NV4_USER_DAC_READ_MODE_ADDRESS 0x6813C7 +#define NV4_USER_DAC_READ_MODE_ADDRESS_VALUE 0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_WO_VALUE 0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE 0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE_WRITE 0x0 +#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE_READ 0x3 +#define NV4_USER_DAC_WRITE_MODE_ADDRESS 0x6813C8 +#define NV4_USER_DAC_WRITE_MODE_ADDRESS_VALUE 0 +#define NV4_USER_DAC_PALETTE_DATA 0x6813C9 +#define NV4_USER_DAC_PALETTE_DATA_VALUE 0 + +#define NV4_PRMDIO_START 0x681000 +#define NV4_PRMDIO_END 0x681FFF + +#define NV4_IO_MPU_401_DATA 0x330 +#define NV4_IO_MPU_401_DATA_ALIAS_1 0x300 +#define NV4_IO_MPU_401_DATA_ALIAS_2 0x230 +#define NV4_IO_MPU_401_DATA_VALUE 0 +#define NV4_IO_MPU_401_DATA_ACK 0xFE +#define NV4_IO_MPU_401_STATUS 0x331 +#define NV4_IO_MPU_401_STATUS_ALIAS_1 0x301 +#define NV4_IO_MPU_401_STATUS_ALIAS_2 0x231 +#define NV4_IO_MPU_401_STATUS_DATA 0 +#define NV4_IO_MPU_401_STATUS_WRITE 6 +#define NV4_IO_MPU_401_STATUS_WRITE_EMPTY 0x0 +#define NV4_IO_MPU_401_STATUS_WRITE_FULL 0x1 +#define NV4_IO_MPU_401_STATUS_READ 7 +#define NV4_IO_MPU_401_STATUS_READ_FULL 0x0 +#define NV4_IO_MPU_401_STATUS_READ_EMPTY 0x1 +#define NV4_IO_MPU_401_COM 0x331 +#define NV4_IO_MPU_401_COM_ALIAS_1 0x301 +#define NV4_IO_MPU_401_COM_ALIAS_2 0x231 +#define NV4_IO_MPU_401_COM_UART_MODE 0 +#define NV4_IO_MPU_401_COM_UART_MODE_COMPLEX 0xff +#define NV4_IO_MPU_401_COM_UART_MODE_SIMPLE 0x3f + +#define NV4_PMC_START 0x0 +#define NV4_PMC_END 0xFFF + +#define NV4_PMC_BOOT_0 0x0 +#define NV4_PMC_BOOT_0_MINOR_REVISION 0 +#define NV4_PMC_BOOT_0_MINOR_REVISION_0 0x0 +#define NV4_PMC_BOOT_0_MAJOR_REVISION 4 +#define NV4_PMC_BOOT_0_MAJOR_REVISION_A 0x0 +#define NV4_PMC_BOOT_0_MAJOR_REVISION_B 0x1 +#define NV4_PMC_BOOT_0_IMPLEMENTATION 8 +#define NV4_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x0 +#define NV4_PMC_BOOT_0_ARCHITECTURE 12 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV0 0x0 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV1 0x1 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV2 0x2 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV3 0x3 +#define NV4_PMC_BOOT_0_ARCHITECTURE_NV4 0x4 +#define NV4_PMC_BOOT_0_FIB_REVISION 16 +#define NV4_PMC_BOOT_0_FIB_REVISION_0 0x0 +#define NV4_PMC_BOOT_0_MASK_REVISION 20 +#define NV4_PMC_BOOT_0_MASK_REVISION_A 0x0 +#define NV4_PMC_BOOT_0_MASK_REVISION_B 0x1 +#define NV4_PMC_BOOT_0_MASK_REVISION_C 0x2 +#define NV4_PMC_BOOT_0_MANUFACTURER 24 +#define NV4_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x0 +#define NV4_PMC_BOOT_0_FOUNDRY 28 +#define NV4_PMC_BOOT_0_FOUNDRY_SGS 0x0 +#define NV4_PMC_BOOT_0_FOUNDRY_HELIOS 0x1 +#define NV4_PMC_BOOT_0_FOUNDRY_TSMC 0x2 +#define NV4_PMC_INTR_0 0x100 +#define NV4_PMC_INTR_0_PMEDIA 4 +#define NV4_PMC_INTR_0_PMEDIA_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PMEDIA_PENDING 0x1 +#define NV4_PMC_INTR_0_PFIFO 8 +#define NV4_PMC_INTR_0_PFIFO_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PFIFO_PENDING 0x1 +#define NV4_PMC_INTR_0_PGRAPH 12 +#define NV4_PMC_INTR_0_PGRAPH_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PGRAPH_PENDING 0x1 +#define NV4_PMC_INTR_0_PVIDEO 16 +#define NV4_PMC_INTR_0_PVIDEO_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PVIDEO_PENDING 0x1 +#define NV4_PMC_INTR_0_PTIMER 20 +#define NV4_PMC_INTR_0_PTIMER_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PTIMER_PENDING 0x1 +#define NV4_PMC_INTR_0_PCRTC 24 +#define NV4_PMC_INTR_0_PCRTC_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PCRTC_PENDING 0x1 +#define NV4_PMC_INTR_0_PBUS 28 +#define NV4_PMC_INTR_0_PBUS_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_PBUS_PENDING 0x1 +#define NV4_PMC_INTR_0_SOFTWARE 31 +#define NV4_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x0 +#define NV4_PMC_INTR_0_SOFTWARE_PENDING 0x1 +#define NV4_PMC_INTR_EN_0 0x140 +#define NV4_PMC_INTR_EN_0_INTA 0 +#define NV4_PMC_INTR_EN_0_INTA_DISABLED 0x0 +#define NV4_PMC_INTR_EN_0_INTA_HARDWARE 0x1 +#define NV4_PMC_INTR_EN_0_INTA_SOFTWARE 0x2 +#define NV4_PMC_INTR_READ_0 0x160 +#define NV4_PMC_INTR_READ_0_INTA 0 +#define NV4_PMC_INTR_READ_0_INTA_LOW 0x0 +#define NV4_PMC_INTR_READ_0_INTA_HIGH 0x1 +#define NV4_PMC_ENABLE 0x200 +#define NV4_PMC_ENABLE_PMEDIA 4 +#define NV4_PMC_ENABLE_PMEDIA_ENABLED 0x1 +#define NV4_PMC_ENABLE_PFIFO 8 +#define NV4_PMC_ENABLE_PFIFO_ENABLED 0x1 +#define NV4_PMC_ENABLE_PGRAPH 12 +#define NV4_PMC_ENABLE_PGRAPH_ENABLED 0x1 +#define NV4_PMC_ENABLE_PPMI 16 +#define NV4_PMC_ENABLE_PPMI_ENABLED 0x1 +#define NV4_PMC_ENABLE_PFB 20 +#define NV4_PMC_ENABLE_PFB_ENABLED 0x1 +#define NV4_PMC_ENABLE_PCRTC 24 +#define NV4_PMC_ENABLE_PCRTC_ENABLED 0x1 +#define NV4_PMC_ENABLE_PVIDEO 28 +#define NV4_PMC_ENABLE_PVIDEO_ENABLED 0x1 + +#define NV4_PBUS_START 0x1000 +#define NV4_PBUS_END 0x1FFF + +#define NV4_PBUS_DEBUG_0 0x1080 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_DELAY 0 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC 4 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_DELAY 8 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC 12 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_DELAY 16 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC 20 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_DELAY 24 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_DELAY_8 0x8 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC 28 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_1 0x1084 +#define NV4_PBUS_DEBUG_1_PCIM_THROTTLE 0 +#define NV4_PBUS_DEBUG_1_PCIM_THROTTLE_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIM_CMD 1 +#define NV4_PBUS_DEBUG_1_PCIM_CMD_SIZE_BASED 0x0 +#define NV4_PBUS_DEBUG_1_PCIM_CMD_MRL_ONLY 0x1 +#define NV4_PBUS_DEBUG_1_HASH_DECODE 2 +#define NV4_PBUS_DEBUG_1_HASH_DECODE_1FF 0x0 +#define NV4_PBUS_DEBUG_1_HASH_DECODE_2FF 0x1 +#define NV4_PBUS_DEBUG_1_AGPM_CMD 3 +#define NV4_PBUS_DEBUG_1_AGPM_CMD_HP_ON_1ST 0x0 +#define NV4_PBUS_DEBUG_1_AGPM_CMD_LP_ONLY 0x1 +#define NV4_PBUS_DEBUG_1_AGPM_CMD_HP_ONLY 0x2 +#define NV4_PBUS_DEBUG_1_PCIS_WRITE 5 +#define NV4_PBUS_DEBUG_1_PCIS_WRITE_0_CYCLE 0x0 +#define NV4_PBUS_DEBUG_1_PCIS_WRITE_1_CYCLE 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_2_1 6 +#define NV4_PBUS_DEBUG_1_PCIS_2_1_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_RETRY 7 +#define NV4_PBUS_DEBUG_1_PCIS_RETRY_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_RD_BURST 8 +#define NV4_PBUS_DEBUG_1_PCIS_RD_BURST_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_WR_BURST 9 +#define NV4_PBUS_DEBUG_1_PCIS_WR_BURST_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_EARLY_RTY 10 +#define NV4_PBUS_DEBUG_1_PCIS_EARLY_RTY_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_PCIS_CPUQ 12 +#define NV4_PBUS_DEBUG_1_PCIS_CPUQ_ENABLED 0x1 +#define NV4_PBUS_DEBUG_1_DPSH_DECODE 13 +#define NV4_PBUS_DEBUG_1_DPSH_DECODE_NV4 0x0 +#define NV4_PBUS_DEBUG_1_DPSH_DECODE_NV3 0x1 +#define NV4_PBUS_DEBUG_1_SPARE1 14 +#define NV4_PBUS_DEBUG_1_SPARE2 15 +#define NV4_PBUS_DEBUG_1_SPARE3 16 +#define NV4_PBUS_DEBUG_1_SPARE4 17 +#define NV4_PBUS_DEBUG_1_SPARE5 18 +#define NV4_PBUS_DEBUG_1_SPARE6 19 +#define NV4_PBUS_DEBUG_1_SPARE7 20 +#define NV4_PBUS_DEBUG_1_SPARE8 21 +#define NV4_PBUS_DEBUG_1_SPARE9 22 +#define NV4_PBUS_DEBUG_1_SPARE10 23 +#define NV4_PBUS_DEBUG_2 0x1088 +#define NV4_PBUS_DEBUG_2_AGP_DIFFERENTIAL 0 +#define NV4_PBUS_DEBUG_2_AGP_DIFFERENTIAL_ENABLED 0x1 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_DELAY 9:4 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_DELAY_34 0x22 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC 12 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC_NORMAL 0x0 +#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC_OVERRIDE 0x1 +#define NV4_PBUS_DEBUG_3 0x108C +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE 0 +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_UNLIMITED 0x0 +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_32_BYTES 0x1 +#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_64_BYTES 0x2 +#define NV4_PBUS_DEBUG_CTL 0x1090 +#define NV4_PBUS_DEBUG_CTL_MODE 0 +#define NV4_PBUS_DEBUG_CTL_MODE_ENABLED 0x1 +#define NV4_PBUS_DEBUG_CTL_READ_SELECT 4 +#define NV4_PBUS_DEBUG_CTL_READ_SELECT_0 0x0 +#define NV4_PBUS_DEBUG_CTL_READ_SELECT_1 0x1 +#define NV4_PBUS_DEBUG_READ 0x1094 +#define NV4_PBUS_DEBUG_READ_DATA 0 +#define NV4_PBUS_DEBUG_HOST 0x109C +#define NV4_PBUS_DEBUG_HOST_SEL 0 +#define NV4_PBUS_DEBUG_SEL_0 0x10A0 +#define NV4_PBUS_DEBUG_SEL_0_X 0 +#define NV4_PBUS_DEBUG_SEL_1 0x10A4 +#define NV4_PBUS_DEBUG_SEL_1_X 0 +#define NV4_PBUS_DEBUG_SEL_2 0x10A8 +#define NV4_PBUS_DEBUG_SEL_2_X 0 +#define NV4_PBUS_DEBUG_SEL_3 0x10AC +#define NV4_PBUS_DEBUG_SEL_3_X 0 +#define NV4_PBUS_INTR_0 0x1100 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR 0 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_NOT_PENDING 0x0 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_PENDING 0x1 +#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_RESET 0x1 +#define NV4_PBUS_INTR_EN_0 0x1140 +#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR 0 +#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR_ENABLED 0x1 +#define NV4_PBUS_ROM_CONFIG 0x1200 +#define NV4_PBUS_ROM_CONFIG_TW1 0 +#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF +#define NV4_PBUS_ROM_CONFIG_TW0 4 +#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3 +#define NV4_PBUS_PCI_NV_0 0x1800 +#define NV4_PBUS_PCI_NV_0_VENDOR_ID 0 +#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA_SGS 0x12D2 +#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA 0x10DE +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC 16 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC_VGA 0x0 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP 3 19 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV0 0x0 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV1 0x1 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV2 0x2 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV3 0x3 +#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV4 0x4 +#define NV4_PBUS_PCI_NV_1 0x1804 +#define NV4_PBUS_PCI_NV_1_IO_SPACE 0 +#define NV4_PBUS_PCI_NV_1_IO_SPACE_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE 1 +#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_BUS_MASTER 2 +#define NV4_PBUS_PCI_NV_1_BUS_MASTER_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL 4 +#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP 5 +#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_1_CAPLIST 20 +#define NV4_PBUS_PCI_NV_1_CAPLIST_NOT_PRESENT 0x0 +#define NV4_PBUS_PCI_NV_1_CAPLIST_PRESENT 0x1 +#define NV4_PBUS_PCI_NV_1_66MHZ 21 +#define NV4_PBUS_PCI_NV_1_66MHZ_INCAPABLE 0x0 +#define NV4_PBUS_PCI_NV_1_66MHZ_CAPABLE 0x1 +#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK 23 +#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_INCAPABLE 0x0 +#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_CAPABLE 0x1 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING 25 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_FAST 0x0 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_MEDIUM 0x1 +#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_SLOW 0x2 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET 27 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_NO_ABORT 0x0 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_ABORT 0x1 +#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_CLEAR 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET 28 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_NO_ABORT 0x0 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_ABORT 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_CLEAR 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER 29 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_NO_ABORT 0x0 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_ABORT 0x1 +#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_CLEAR 0x1 +#define NV4_PBUS_PCI_NV_2 0x1808 +#define NV4_PBUS_PCI_NV_2_REVISION_ID 0 +#define NV4_PBUS_PCI_NV_2_REVISION_ID_A01 0x0 +#define NV4_PBUS_PCI_NV_2_REVISION_ID_B01 0x10 +#define NV4_PBUS_PCI_NV_2_CLASS_CODE 8 +#define NV4_PBUS_PCI_NV_2_CLASS_CODE_VGA 0x30000 +#define NV4_PBUS_PCI_NV_2_CLASS_CODE_MULTIMEDIA 0x48000 +#define NV4_PBUS_PCI_NV_3 0x180C +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER 11 +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x0 +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x1 +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x1E +#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x1F +#define NV4_PBUS_PCI_NV_3_HEADER_TYPE 16 +#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_SINGLEFUNC 0x0 +#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_MULTIFUNC 0x80 +#define NV4_PBUS_PCI_NV_4 0x1810 +#define NV4_PBUS_PCI_NV_4_SPACE_TYPE 0 +#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_MEMORY 0x0 +#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_IO 0x1 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE 1 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_32_BIT 0x0 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_20_BIT 0x1 +#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_64_BIT 0x2 +#define NV4_PBUS_PCI_NV_4_PREFETCHABLE 3 +#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_NOT 0x0 +#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_MERGABLE 0x1 +#define NV4_PBUS_PCI_NV_4_BASE_ADDRESS 24 +#define NV4_PBUS_PCI_NV_5 0x1814 +#define NV4_PBUS_PCI_NV_5_SPACE_TYPE 0 +#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_MEMORY 0x0 +#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_IO 0x1 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE 2:1 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_32_BIT 0x0 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_20_BIT 0x1 +#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x2 +#define NV4_PBUS_PCI_NV_5_PREFETCHABLE 3 +#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_NOT 0x0 +#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_MERGABLE 0x1 +#define NV4_PBUS_PCI_NV_5_BASE_ADDRESS 24 +#define NV4_PBUS_PCI_NV_6(i) (0x1818+(i)*4) +#define NV4_PBUS_PCI_NV_6_SIZE_1 5 +#define NV4_PBUS_PCI_NV_6_RESERVED 0 +#define NV4_PBUS_PCI_NV_6_RESERVED_0 0x0 +#define NV4_PBUS_PCI_NV_11 0x182C +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID 0 +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID 16 +#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_12 0x1830 +#define NV4_PBUS_PCI_NV_12_ROM_DECODE 0 +#define NV4_PBUS_PCI_NV_12_ROM_DECODE_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_12_ROM_BASE 16 +#define NV4_PBUS_PCI_NV_13 0x1834 +#define NV4_PBUS_PCI_NV_13_CAP_PTR 0 +#define NV4_PBUS_PCI_NV_13_CAP_PTR_AGP 0x44 +#define NV4_PBUS_PCI_NV_13_CAP_PTR_POWER_MGMT 0x60 +#define NV4_PBUS_PCI_NV_14 0x1838 +#define NV4_PBUS_PCI_NV_14_RESERVED 0 +#define NV4_PBUS_PCI_NV_14_RESERVED_0 0x0 +#define NV4_PBUS_PCI_NV_15 0x183C +#define NV4_PBUS_PCI_NV_15_INTR_LINE 0 +#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ0 0x0 +#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ1 0x1 +#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ15 0xF +#define NV4_PBUS_PCI_NV_15_INTR_LINE_UNKNOWN 0xFF +#define NV4_PBUS_PCI_NV_15_INTR_PIN 8 +#define NV4_PBUS_PCI_NV_15_INTR_PIN_INTA 0x1 +#define NV4_PBUS_PCI_NV_15_MIN_GNT 16 +#define NV4_PBUS_PCI_NV_15_MIN_GNT_NO_REQUIREMENTS 0x0 +#define NV4_PBUS_PCI_NV_15_MIN_GNT_750NS 0x3 +#define NV4_PBUS_PCI_NV_15_MIN_GNT_1250NS 0x5 +#define NV4_PBUS_PCI_NV_15_MAX_LAT 24 +#define NV4_PBUS_PCI_NV_15_MAX_LAT_NO_REQUIREMENTS 0x0 +#define NV4_PBUS_PCI_NV_15_MAX_LAT_250NS 0x1 +#define NV4_PBUS_PCI_NV_16 0x1840 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID 0 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID 16 +#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID_NONE 0x0 +#define NV4_PBUS_PCI_NV_17 0x1844 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR 20 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR_1 0x1 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR 16 +#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR_0 0x0 +#define NV4_PBUS_PCI_NV_17_NEXT_PTR 8 +#define NV4_PBUS_PCI_NV_17_NEXT_PTR_NULL 0x0 +#define NV4_PBUS_PCI_NV_17_CAP_ID 0 +#define NV4_PBUS_PCI_NV_17_CAP_ID_AGP 0x2 +#define NV4_PBUS_PCI_NV_18 0x1848 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ 24 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ_16 0xF +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA 9 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_NONE 0x0 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_CAPABLE 0x1 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE 0 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X 0x1 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_2X 0x2 +#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X_AND_2X 0x3 +#define NV4_PBUS_PCI_NV_19 0x184C +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH 24 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH_0 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE 9 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_OFF 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_ON 0x1 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE 8 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_OFF 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_ON 0x1 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE 0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_OFF 0x0 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_1X 0x1 +#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_2X 0x2 +#define NV4_PBUS_PCI_NV_20 0x1850 +#define NV4_PBUS_PCI_NV_20_ROM_SHADOW 0 +#define NV4_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_21 0x1854 +#define NV4_PBUS_PCI_NV_21_VGA 0 +#define NV4_PBUS_PCI_NV_21_VGA_ENABLED 0x1 +#define NV4_PBUS_PCI_NV_22 0x1858 +#define NV4_PBUS_PCI_NV_22_SCRATCH 0 +#define NV4_PBUS_PCI_NV_22_SCRATCH_DEFAULT 0x23D6CE +#define NV4_PBUS_PCI_NV_23 0x185C +#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT 0 +#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT_16 0xF +#define NV4_PBUS_PCI_NV_24 0x1860 +#define NV4_PBUS_PCI_NV_24_PME_D3_COLD 31 +#define NV4_PBUS_PCI_NV_24_PME_D3_COLD_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D3_HOT 30 +#define NV4_PBUS_PCI_NV_24_PME_D3_HOT_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D2 29 +#define NV4_PBUS_PCI_NV_24_PME_D2_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D1 28 +#define NV4_PBUS_PCI_NV_24_PME_D1_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_PME_D0 27 +#define NV4_PBUS_PCI_NV_24_PME_D0_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_D2 26 +#define NV4_PBUS_PCI_NV_24_D2_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_D2_NOT_SUPPORTED 0x0 +#define NV4_PBUS_PCI_NV_24_D1 25 +#define NV4_PBUS_PCI_NV_24_D1_SUPPORTED 0x1 +#define NV4_PBUS_PCI_NV_24_D1_NOT_SUPPORTED 0x0 +#define NV4_PBUS_PCI_NV_24_DSI 21 +#define NV4_PBUS_PCI_NV_24_DSI_NOT_REQUIRED 0x0 +#define NV4_PBUS_PCI_NV_24_PME_CLOCK 19 +#define NV4_PBUS_PCI_NV_24_PME_CLOCK_NOT_REQUIRED 0x0 +#define NV4_PBUS_PCI_NV_24_VERSION 16 +#define NV4_PBUS_PCI_NV_24_VERSION_1 0x1 +#define NV4_PBUS_PCI_NV_24_NEXT_PTR 8 +#define NV4_PBUS_PCI_NV_24_NEXT_PTR_NULL 0x0 +#define NV4_PBUS_PCI_NV_24_NEXT_PTR_AGP 0x44 +#define NV4_PBUS_PCI_NV_24_CAP_ID 0 +#define NV4_PBUS_PCI_NV_24_CAP_ID_POWER_MGMT 0x1 +#define NV4_PBUS_PCI_NV_25 0x1864 +#define NV4_PBUS_PCI_NV_25_POWER_STATE 0 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D3_HOT 0x3 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D2 0x2 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D1 0x1 +#define NV4_PBUS_PCI_NV_25_POWER_STATE_D0 0x0 +#define NV4_PBUS_PCI_NV_26(i) (0x1868+(i)*4) +#define NV4_PBUS_PCI_NV_26_SIZE_1 38 +#define NV4_PBUS_PCI_NV_26_RESERVED 0 +#define NV4_PBUS_PCI_NV_26_RESERVED_0 0x0 + +#define NV4_PFIFO_START 0x2000 +#define NV4_PFIFO_END 0x3FFF + +#define NV4_PFIFO_DELAY_0 0x2040 +#define NV4_PFIFO_DELAY_0_WAIT_RETRY 0 +#define NV4_PFIFO_DELAY_0_WAIT_RETRY_0 0x0 +#define NV4_PFIFO_DMA_TIMESLICE 0x2044 +#define NV4_PFIFO_DMA_TIMESLICE_SELECT 0 +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_1 0x0 +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_16K 0x3fff +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_32K 0x7fff +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_64K 0xffff +#define NV4_PFIFO_DMA_TIMESLICE_SELECT_128K 0x1ffff +#define NV4_PFIFO_DMA_TIMESLICE_TIMEOUT 24 +#define NV4_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x1 +#define NV4_PFIFO_PIO_TIMESLICE 0x2048 +#define NV4_PFIFO_PIO_TIMESLICE_SELECT 0 +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_1 0x0 +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_16K 0x3fff +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_32K 0x7fff +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_64K 0xffff +#define NV4_PFIFO_PIO_TIMESLICE_SELECT_128K 0x1ffff +#define NV4_PFIFO_PIO_TIMESLICE_TIMEOUT 24 +#define NV4_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x1 +#define NV4_PFIFO_TIMESLICE 0x204C +#define NV4_PFIFO_TIMESLICE_TIMER 0 +#define NV4_PFIFO_TIMESLICE_TIMER_EXPIRED 0x3FFFF +#define NV4_PFIFO_NEXT_CHANNEL 0x2050 +#define NV4_PFIFO_NEXT_CHANNEL_CHID 0 +#define NV4_PFIFO_NEXT_CHANNEL_MODE 8 +#define NV4_PFIFO_NEXT_CHANNEL_MODE_PIO 0x0 +#define NV4_PFIFO_NEXT_CHANNEL_MODE_DMA 0x1 +#define NV4_PFIFO_NEXT_CHANNEL_SWITCH 12 +#define NV4_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x0 +#define NV4_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x1 +#define NV4_PFIFO_DEBUG_0 0x2080 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0 0 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x0 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x1 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1 4 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x0 +#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x1 +#define NV4_PFIFO_INTR_0 0x2100 +#define NV4_PFIFO_INTR_0_CACHE_ERROR 0 +#define NV4_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x1 +#define NV4_PFIFO_INTR_0_CACHE_ERROR_RESET 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT 4 +#define NV4_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_RUNOUT_PENDING 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT_RESET 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW 8 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x1 +#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x1 +#define NV4_PFIFO_INTR_0_DMA_PUSHER 12 +#define NV4_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x1 +#define NV4_PFIFO_INTR_0_DMA_PUSHER_RESET 0x1 +#define NV4_PFIFO_INTR_0_DMA_PT 16 +#define NV4_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x0 +#define NV4_PFIFO_INTR_0_DMA_PT_PENDING 0x1 +#define NV4_PFIFO_INTR_0_DMA_PT_RESET 0x1 +#define NV4_PFIFO_INTR_EN_0 0x2140 +#define NV4_PFIFO_INTR_EN_0_CACHE_ERROR 0 +#define NV4_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_RUNOUT 4 +#define NV4_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8 +#define NV4_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_DMA_PUSHER 12 +#define NV4_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x1 +#define NV4_PFIFO_INTR_EN_0_DMA_PT 16 +#define NV4_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x1 +#define NV4_PFIFO_RAMHT 0x2210 +#define NV4_PFIFO_RAMHT_BASE_ADDRESS 4 +#define NV4_PFIFO_RAMHT_BASE_ADDRESS_10000 0x10 +#define NV4_PFIFO_RAMHT_SIZE 16 +#define NV4_PFIFO_RAMHT_SIZE_4K 0x0 +#define NV4_PFIFO_RAMHT_SIZE_8K 0x1 +#define NV4_PFIFO_RAMHT_SIZE_16K 0x2 +#define NV4_PFIFO_RAMHT_SIZE_32K 0x3 +#define NV4_PFIFO_RAMHT_SEARCH 24 +#define NV4_PFIFO_RAMHT_SEARCH_16 0x0 +#define NV4_PFIFO_RAMHT_SEARCH_32 0x1 +#define NV4_PFIFO_RAMHT_SEARCH_64 0x2 +#define NV4_PFIFO_RAMHT_SEARCH_128 0x3 +#define NV4_PFIFO_RAMFC 0x2214 +#define NV4_PFIFO_RAMFC_BASE_ADDRESS 1 +#define NV4_PFIFO_RAMFC_BASE_ADDRESS_11000 0x88 +#define NV4_PFIFO_RAMRO 0x2218 +#define NV4_PFIFO_RAMRO_BASE_ADDRESS 1 +#define NV4_PFIFO_RAMRO_BASE_ADDRESS_11200 0x89 +#define NV4_PFIFO_RAMRO_BASE_ADDRESS_12000 0x90 +#define NV4_PFIFO_RAMRO_SIZE 16 +#define NV4_PFIFO_RAMRO_SIZE_512 0x0 +#define NV4_PFIFO_RAMRO_SIZE_8K 0x1 +#define NV4_PFIFO_CACHES 0x2500 +#define NV4_PFIFO_CACHES_REASSIGN 0 +#define NV4_PFIFO_CACHES_REASSIGN_ENABLED 0x1 +#define NV4_PFIFO_CACHES_DMA_SUSPEND 4 +#define NV4_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x0 +#define NV4_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x1 +#define NV4_PFIFO_MODE 0x2504 +// Valid for all 16 channels. Do we need thees at all? +#define NV4_PFIFO_MODE_CHANNEL_IS_PIO 0x0 +#define NV4_PFIFO_MODE_CHANNEL_IS_DMA 0x1 +#define NV4_PFIFO_MODE_CHANNEL_0 0 +#define NV4_PFIFO_MODE_CHANNEL_1 1 +#define NV4_PFIFO_MODE_CHANNEL_2 2 +#define NV4_PFIFO_MODE_CHANNEL_3 3 +#define NV4_PFIFO_MODE_CHANNEL_4 4 +#define NV4_PFIFO_MODE_CHANNEL_5 5 +#define NV4_PFIFO_MODE_CHANNEL_6 6 +#define NV4_PFIFO_MODE_CHANNEL_7 7 +#define NV4_PFIFO_MODE_CHANNEL_8 8 +#define NV4_PFIFO_MODE_CHANNEL_9 9 +#define NV4_PFIFO_MODE_CHANNEL_10 10 +#define NV4_PFIFO_MODE_CHANNEL_11 11 +#define NV4_PFIFO_MODE_CHANNEL_12 12 +#define NV4_PFIFO_MODE_CHANNEL_13 13 +#define NV4_PFIFO_MODE_CHANNEL_14 14 +#define NV4_PFIFO_MODE_CHANNEL_15 15 +#define NV4_PFIFO_DMA 0x2508 +// 0 = not pending (Valid for all channels) +#define NV4_PFIFO_DMA_CHANNEL_IS_PENDING 0x1 +#define NV4_PFIFO_DMA_CHANNEL_0 0 +#define NV4_PFIFO_DMA_CHANNEL_1 1 +#define NV4_PFIFO_DMA_CHANNEL_2 2 +#define NV4_PFIFO_DMA_CHANNEL_3 3 +#define NV4_PFIFO_DMA_CHANNEL_4 4 +#define NV4_PFIFO_DMA_CHANNEL_5 5 +#define NV4_PFIFO_DMA_CHANNEL_6 6 +#define NV4_PFIFO_DMA_CHANNEL_7 7 +#define NV4_PFIFO_DMA_CHANNEL_8 8 +#define NV4_PFIFO_DMA_CHANNEL_9 9 +#define NV4_PFIFO_DMA_CHANNEL_10 10 +#define NV4_PFIFO_DMA_CHANNEL_11 11 +#define NV4_PFIFO_DMA_CHANNEL_12 12 +#define NV4_PFIFO_DMA_CHANNEL_13 13 +#define NV4_PFIFO_DMA_CHANNEL_14 14 +#define NV4_PFIFO_DMA_CHANNEL_15 15 +#define NV4_PFIFO_SIZE 0x250C +// Valid for all channels +#define NV4_PFIFO_SIZE_CHANNEL_SIZE_IS_124_BYTES 0x0 +#define NV4_PFIFO_SIZE_CHANNEL_SIZE_IS_512_BYTES 0x1 +#define NV4_PFIFO_SIZE_CHANNEL_0 0 +#define NV4_PFIFO_SIZE_CHANNEL_1 1 +#define NV4_PFIFO_SIZE_CHANNEL_2 2 +#define NV4_PFIFO_SIZE_CHANNEL_3 3 +#define NV4_PFIFO_SIZE_CHANNEL_4 4 +#define NV4_PFIFO_SIZE_CHANNEL_5 5 +#define NV4_PFIFO_SIZE_CHANNEL_6 6 +#define NV4_PFIFO_SIZE_CHANNEL_7 7 +#define NV4_PFIFO_SIZE_CHANNEL_8 8 +#define NV4_PFIFO_SIZE_CHANNEL_9 9 +#define NV4_PFIFO_SIZE_CHANNEL_10 10 +#define NV4_PFIFO_SIZE_CHANNEL_11 11 +#define NV4_PFIFO_SIZE_CHANNEL_12 12 +#define NV4_PFIFO_SIZE_CHANNEL_13 13 +#define NV4_PFIFO_SIZE_CHANNEL_14 14 +#define NV4_PFIFO_SIZE_CHANNEL_15 15 +#define NV4_PFIFO_CACHE0_PUSH0 0x3000 +#define NV4_PFIFO_CACHE0_PUSH0_ACCESS 0 +#define NV4_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE1_PUSH0 0x3200 +#define NV4_PFIFO_CACHE1_PUSH0_ACCESS 0 +#define NV4_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE0_PUSH1 0x3004 +#define NV4_PFIFO_CACHE0_PUSH1_CHID 0 +#define NV4_PFIFO_CACHE1_PUSH1 0x3204 +#define NV4_PFIFO_CACHE1_PUSH1_CHID 0 +#define NV4_PFIFO_CACHE1_PUSH1_MODE 8 +#define NV4_PFIFO_CACHE1_PUSH1_MODE_PIO 0x0 +#define NV4_PFIFO_CACHE1_PUSH1_MODE_DMA 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH 0x3220 +#define NV4_PFIFO_CACHE1_DMA_PUSH_ACCESS 0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE 4 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER 8 +#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x1 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS 12 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x0 +#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x1 +#define NV4_PFIFO_CACHE1_DMA_FETCH 0x3224 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x0 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x1 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x2 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x3 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x4 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x5 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x6 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x7 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x8 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x9 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0xA +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0xB +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0xC +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0xD +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0xE +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0xF +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x10 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x11 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x12 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x13 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x14 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x15 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x16 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x17 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x18 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x19 +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x1A +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x1B +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x1C +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x1D +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x1E +#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x1F +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE 13 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x0 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x1 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x2 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x3 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x4 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x5 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x6 +#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x7 +// This is a count. 0x0-0xF = number of requests +#define NV4_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 16 +#define NV4_PFIFO_CACHE1_DMA_PUT 0x3240 +#define NV4_PFIFO_CACHE1_DMA_PUT_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_GET 0x3244 +#define NV4_PFIFO_CACHE1_DMA_GET_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_DCOUNT 0x32A0 +#define NV4_PFIFO_CACHE1_DMA_DCOUNT_VALUE 2 +#define NV4_PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x32A4 +#define NV4_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_RSVD_SHADOW 0x32A8 +#define NV4_PFIFO_CACHE1_DMA_RSVD_SHADOW_CMD 0 +#define NV4_PFIFO_CACHE1_DMA_DATA_SHADOW 0x32AC +#define NV4_PFIFO_CACHE1_DMA_DATA_SHADOW_VALUE 0 +#define NV4_PFIFO_CACHE1_DMA_STATE 0x3228 +#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD 2 +#define NV4_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 13 +#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 18 +#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x0 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR 30 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x0 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x1 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x2 +#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x3 +#define NV4_PFIFO_CACHE1_DMA_INSTANCE 0x322C +#define NV4_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0 +#define NV4_PFIFO_CACHE1_DMA_CTL 0x3230 +#define NV4_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x1 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x1 +#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 16 +#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x2 +#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x3 +#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO 31 +#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x0 +#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x1 +#define NV4_PFIFO_CACHE1_DMA_LIMIT 0x3234 +#define NV4_PFIFO_CACHE1_DMA_LIMIT_OFFSET 2 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG 0x3238 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x0 +#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x1 +#define NV4_PFIFO_CACHE1_DMA_TLB_PTE 0x323C +#define NV4_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 12 +#define NV4_PFIFO_CACHE0_PULL0 0x3050 +#define NV4_PFIFO_CACHE0_PULL0_ACCESS 0 +#define NV4_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE0_PULL0_HASH 4 +#define NV4_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x0 +#define NV4_PFIFO_CACHE0_PULL0_HASH_FAILED 0x1 +#define NV4_PFIFO_CACHE0_PULL0_DEVICE 8 +#define NV4_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x0 +#define NV4_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x1 +#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE 12 +#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x0 +#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x1 +#define NV4_PFIFO_CACHE1_PULL0 0x3250 +#define NV4_PFIFO_CACHE1_PULL0_ACCESS 0 +#define NV4_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x1 +#define NV4_PFIFO_CACHE1_PULL0_HASH 4 +#define NV4_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x0 +#define NV4_PFIFO_CACHE1_PULL0_HASH_FAILED 0x1 +#define NV4_PFIFO_CACHE1_PULL0_DEVICE 8 +#define NV4_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x0 +#define NV4_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x1 +#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE 12 +#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x0 +#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x1 +#define NV4_PFIFO_CACHE0_PULL1 0x3054 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE 0 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE_SW 0x0 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x1 +#define NV4_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x2 +#define NV4_PFIFO_CACHE1_PULL1 0x3254 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE 0 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE_SW 0x0 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x1 +#define NV4_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x2 +#define NV4_PFIFO_CACHE0_HASH 0x3058 +#define NV4_PFIFO_CACHE0_HASH_INSTANCE 0 +#define NV4_PFIFO_CACHE0_HASH_VALID 16 +#define NV4_PFIFO_CACHE1_HASH 0x3258 +#define NV4_PFIFO_CACHE1_HASH_INSTANCE 0 +#define NV4_PFIFO_CACHE1_HASH_VALID 16 +#define NV4_PFIFO_CACHE0_STATUS 0x3014 +#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK 4 +#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x0 +#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x1 +#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK 8 +#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x0 +#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x1 +#define NV4_PFIFO_CACHE1_STATUS 0x3214 +#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK 4 +#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x0 +#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x1 +#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK 8 +#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x0 +#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x1 +#define NV4_PFIFO_CACHE1_STATUS1 0x3218 +#define NV4_PFIFO_CACHE1_STATUS1_RANOUT 0 +#define NV4_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x1 +#define NV4_PFIFO_CACHE0_PUT 0x3010 +#define NV4_PFIFO_CACHE0_PUT_ADDRESS 2 +#define NV4_PFIFO_CACHE1_PUT 0x3210 +#define NV4_PFIFO_CACHE1_PUT_ADDRESS 2 +#define NV4_PFIFO_CACHE0_GET 0x3070 +#define NV4_PFIFO_CACHE0_GET_ADDRESS 2 +#define NV4_PFIFO_CACHE1_GET 0x3270 +#define NV4_PFIFO_CACHE1_GET_ADDRESS 2 +#define NV4_PFIFO_ENGINE_SW 0x0 +#define NV4_PFIFO_ENGINE_GRAPHICS 0x1 +#define NV4_PFIFO_ENGINE_DVD 0x2 +#define NV4_PFIFO_CACHE0_ENGINE 0x3080 +// For these, see above +#define NV4_PFIFO_CACHE0_SUBCHANNEL_0_ENGINE 0 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_1_ENGINE 4 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_2_ENGINE 8 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_3_ENGINE 12 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_4_ENGINE 16 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_5_ENGINE 20 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_6_ENGINE 24 +#define NV4_PFIFO_CACHE0_SUBCHANNEL_7_ENGINE 28 +#define NV4_PFIFO_CACHE1_ENGINE 0x3280 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_0_ENGINE 0 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_1_ENGINE 4 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_2_ENGINE 8 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_3_ENGINE 12 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_4_ENGINE 16 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_5_ENGINE 20 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_6_ENGINE 24 +#define NV4_PFIFO_CACHE1_SUBCHANNEL_7_ENGINE 28 +#define NV4_PFIFO_CACHE0_METHOD(i) (0x3100+(i)*8) +#define NV4_PFIFO_CACHE0_METHOD_SIZE_1 1 +#define NV4_PFIFO_CACHE0_METHOD_ADDRESS 2 +#define NV4_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 +#define NV4_PFIFO_CACHE1_METHOD(i) (0x3800+(i)*8) +#define NV4_PFIFO_CACHE1_METHOD_SIZE_1 128 +#define NV4_PFIFO_CACHE1_METHOD_ADDRESS 2 +#define NV4_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 +#define NV4_PFIFO_CACHE1_METHOD_ALIAS(i) (0x3C00+(i)*8) +#define NV4_PFIFO_CACHE1_METHOD_ALIAS_SIZE_1 128 +#define NV4_PFIFO_CACHE0_DATA(i) (0x3104+(i)*8) +#define NV4_PFIFO_CACHE0_DATA_SIZE_1 1 +#define NV4_PFIFO_CACHE0_DATA_VALUE 0 +#define NV4_PFIFO_CACHE1_DATA(i) (0x3804+(i)*8) +#define NV4_PFIFO_CACHE1_DATA_SIZE_1 128 +#define NV4_PFIFO_CACHE1_DATA_VALUE 0 +#define NV4_PFIFO_CACHE1_DATA_ALIAS(i) (0x3C04+(i)*8) +#define NV4_PFIFO_CACHE1_DATA_ALIAS_SIZE_1 128 +#define NV4_PFIFO_DEVICE(i) (0x2800+(i)*4) +#define NV4_PFIFO_DEVICE_SIZE_1 128 +#define NV4_PFIFO_DEVICE_CHID 0 +#define NV4_PFIFO_DEVICE_SWITCH 24 +#define NV4_PFIFO_DEVICE_SWITCH_AVAILABLE 0x1 +#define NV4_PFIFO_RUNOUT_STATUS 0x2400 +#define NV4_PFIFO_RUNOUT_STATUS_RANOUT 0 +#define NV4_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x1 +#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK 4 +#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x0 +#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x1 +#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK 8 +#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x0 +#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x1 +#define NV4_PFIFO_RUNOUT_PUT 0x2410 +#define NV4_PFIFO_RUNOUT_PUT_ADDRESS 3 // if size=0, 8:3, otherwise 12:3 +#define NV4_PFIFO_RUNOUT_GET 0x2420 +#define NV4_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 + +#define NV4_PGRAPH_START 0x400000 +#define NV4_PGRAPH_END 0x401FFF + +#define NV4_PGRAPH_DEBUG_0 0x400080 +#define NV4_PGRAPH_DEBUG_0_STATE 0 +#define NV4_PGRAPH_DEBUG_0_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_FE_STATE 1 +#define NV4_PGRAPH_DEBUG_0_FE_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_FE_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_CACHE_STATE 2 +#define NV4_PGRAPH_DEBUG_0_CACHE_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_CACHE_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE 3 +#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_PREROP_STATE 4 +#define NV4_PGRAPH_DEBUG_0_PREROP_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_PREROP_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_ROP_STATE 5 +#define NV4_PGRAPH_DEBUG_0_ROP_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_ROP_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_RSTR_STATE 6 +#define NV4_PGRAPH_DEBUG_0_RSTR_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_RSTR_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE 7 +#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_DMA_STATE 8 +#define NV4_PGRAPH_DEBUG_0_DMA_STATE_NORMAL 0x0 +#define NV4_PGRAPH_DEBUG_0_DMA_STATE_RESET 0x1 +#define NV4_PGRAPH_DEBUG_0_SPARE1 12 +#define NV4_PGRAPH_DEBUG_0_SPARE2 13 +#define NV4_PGRAPH_DEBUG_0_MINUSD5 14 +#define NV4_PGRAPH_DEBUG_0_MINUSD5_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_BLIT_DST_LIMIT 15 +#define NV4_PGRAPH_DEBUG_0_BLIT_DST_LIMIT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_LIMIT_CHECK 16 +#define NV4_PGRAPH_DEBUG_0_LIMIT_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_LIMIT_INT 17 +#define NV4_PGRAPH_DEBUG_0_LIMIT_INT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_OVRFLW_INT 18 +#define NV4_PGRAPH_DEBUG_0_OVRFLW_INT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D 21 +#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_AUTO 24 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_AUTO_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y 25 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y_DECR 0x0 +#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y_INCR 0x1 +#define NV4_PGRAPH_DEBUG_0_ALPHA_ABORT 28 +#define NV4_PGRAPH_DEBUG_0_ALPHA_ABORT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1 0x400084 +#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET 0 +#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x0 +#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x1 +#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY 4 +#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY_IGNORE 0x0 +#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 0x1 +#define NV4_PGRAPH_DEBUG_1_PATCH_INV 8 +#define NV4_PGRAPH_DEBUG_1_PATCH_INV_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_ALT_RW_SEQ 10 +#define NV4_PGRAPH_DEBUG_1_ALT_RW_SEQ_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_TRI_OPTS 12 +#define NV4_PGRAPH_DEBUG_1_TRI_OPTS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_TRICLIP_OPTS 13 +#define NV4_PGRAPH_DEBUG_1_TRICLIP_OPTS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_INSTANCE 16 +#define NV4_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_ALOM_BURST 17 +#define NV4_PGRAPH_DEBUG_1_ALOM_BURST_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_BIDIR_DRAIN 18 +#define NV4_PGRAPH_DEBUG_1_BIDIR_DRAIN_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_EARLY_POST 19 +#define NV4_PGRAPH_DEBUG_1_EARLY_POST_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_CTX 20 +#define NV4_PGRAPH_DEBUG_1_CTX_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_FIXED_ADRS 21 +#define NV4_PGRAPH_DEBUG_1_FIXED_ADRS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_2D 22 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_3D 23 +#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_CACHE 24 +#define NV4_PGRAPH_DEBUG_1_CACHE_IGNORE 0x0 +#define NV4_PGRAPH_DEBUG_1_CACHE_FLUSH 0x1 +#define NV4_PGRAPH_DEBUG_1_CACHE_MODE 25 +#define NV4_PGRAPH_DEBUG_1_CACHE_MODE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_ZCLAMP 28 +#define NV4_PGRAPH_DEBUG_1_ZCLAMP_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_UCLAMP 29 +#define NV4_PGRAPH_DEBUG_1_UCLAMP_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_RCLAMP 30 +#define NV4_PGRAPH_DEBUG_1_RCLAMP_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_1_DX6_2PIXMODE 31 +#define NV4_PGRAPH_DEBUG_1_DX6_2PIXMODE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2 0x400088 +#define NV4_PGRAPH_DEBUG_2_HONOR_SRCFMT 0 +#define NV4_PGRAPH_DEBUG_2_HONOR_SRCFMT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_PINGPONG 0 +#define NV4_PGRAPH_DEBUG_2_PINGPONG_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_SPARE1 4 +#define NV4_PGRAPH_DEBUG_2_SPARE2 5 +#define NV4_PGRAPH_DEBUG_2_SPARE3 6 +#define NV4_PGRAPH_DEBUG_2_SPARE4 7 +#define NV4_PGRAPH_DEBUG_2_SPARE5 8 +#define NV4_PGRAPH_DEBUG_2_SPARE6 9 +#define NV4_PGRAPH_DEBUG_2_SPARE7 10 +#define NV4_PGRAPH_DEBUG_2_MCLK_RECTS 11 +#define NV4_PGRAPH_DEBUG_2_MCLK_RECTS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_BILINEAR_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_ANISOTROPIC_3D 13 +#define NV4_PGRAPH_DEBUG_2_ANISOTROPIC_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_FOG_3D 14 +#define NV4_PGRAPH_DEBUG_2_FOG_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_SPECULAR_3D 15 +#define NV4_PGRAPH_DEBUG_2_SPECULAR_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_ALPHA_3D 16 +#define NV4_PGRAPH_DEBUG_2_ALPHA_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ 17 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_CRZRWCW 0x0 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_ZRWCRW 0x1 +#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_AUTO 0x2 +#define NV4_PGRAPH_DEBUG_2_COELESCE_D3D 20 +#define NV4_PGRAPH_DEBUG_2_COELESCE_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_COELESCE_2D 22 +#define NV4_PGRAPH_DEBUG_2_COELESCE_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_FAST_VERTEX_LOAD 23 +#define NV4_PGRAPH_DEBUG_2_FAST_VERTEX_LOAD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_BLIT_MULTILINE 24 +#define NV4_PGRAPH_DEBUG_2_BLIT_MULTILINE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_2_VOLATILE_RESET 28 +#define NV4_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3 0x40008C +#define NV4_PGRAPH_DEBUG_3_CULLING 0 +#define NV4_PGRAPH_DEBUG_3_CULLING_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE 1 +#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE_DX3 0x0 +#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE_DX5 0x1 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_STRTCH 4 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_STRTCH_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_D3D 5 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_IMAGE 6 +#define NV4_PGRAPH_DEBUG_3_FAST_DATA_IMAGE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_ZFLUSH 7 +#define NV4_PGRAPH_DEBUG_3_ZFLUSH_IGNORE 0x0 +#define NV4_PGRAPH_DEBUG_3_ZFLUSH_ACTIVATE 0x1 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_PTZ 8 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_PTZ_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D 9 +#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_PTZ 10 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_PTZ_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D 11 +#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_2D 12 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_3D 13 +#define NV4_PGRAPH_DEBUG_3_POSTDITHER_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_2D 14 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_2D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_3D 15 +#define NV4_PGRAPH_DEBUG_3_PREDITHER_3D_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FORCE_CREAD 16 +#define NV4_PGRAPH_DEBUG_3_FORCE_CREAD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FORCE_ZREAD 17 +#define NV4_PGRAPH_DEBUG_3_FORCE_ZREAD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_EARLYZ_ABORT 18 +#define NV4_PGRAPH_DEBUG_3_EARLYZ_ABORT_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_TRIEND_FLUSH 19 +#define NV4_PGRAPH_DEBUG_3_TRIEND_FLUSH_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK 20 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21 +#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_FAIL_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_FORMAT_CHECK 22 +#define NV4_PGRAPH_DEBUG_3_FORMAT_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_DMA_CHECK 23 +#define NV4_PGRAPH_DEBUG_3_DMA_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_RAMREADBACK 24 +#define NV4_PGRAPH_DEBUG_3_RAMREADBACK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_CLIP_METHODS 25 +#define NV4_PGRAPH_DEBUG_3_CLIP_METHODS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_EXCLUDE_ROP_IN_IDLE 27 +#define NV4_PGRAPH_DEBUG_3_EXCLUDE_ROP_IN_IDLE_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_STATE_CHECK 28 +#define NV4_PGRAPH_DEBUG_3_STATE_CHECK_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_CONTEXT_METHODS 29 +#define NV4_PGRAPH_DEBUG_3_CONTEXT_METHODS_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_OPERATION_METHOD 30 +#define NV4_PGRAPH_DEBUG_3_OPERATION_METHOD_ENABLED 0x1 +#define NV4_PGRAPH_DEBUG_3_IGNORE_PATCHVALID 31 +#define NV4_PGRAPH_DEBUG_3_IGNORE_PATCHVALID_ENABLED 0x1 +#define NV4_PGRAPH_INTR 0x400100 +#define NV4_PGRAPH_INTR_NOTIFY 0 +#define NV4_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_NOTIFY_PENDING 0x1 +#define NV4_PGRAPH_INTR_NOTIFY_RESET 0x1 +#define NV4_PGRAPH_INTR_MISSING_HW 4 +#define NV4_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_MISSING_HW_PENDING 0x1 +#define NV4_PGRAPH_INTR_MISSING_HW_RESET 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A 8 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B 9 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x1 +#define NV4_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x1 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH 12 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x1 +#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x1 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY 16 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x0 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x1 +#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x1 +#define NV4_PGRAPH_NSTATUS 0x400104 +#define NV4_PGRAPH_NSTATUS_STATE_IN_USE 11 +#define NV4_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x1 +#define NV4_PGRAPH_NSTATUS_INVALID_STATE 12 +#define NV4_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x1 +#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT 13 +#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x1 +#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT 14 +#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE 0x400108 +#define NV4_PGRAPH_NSOURCE_NOTIFICATION 0 +#define NV4_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DATA_ERROR 1 +#define NV4_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR 2 +#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION 3 +#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR 4 +#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_ 5 +#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD 6 +#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION 7 +#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION 8 +#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9 +#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION 10 +#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_STATE_INVALID 11 +#define NV4_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12 +#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE 13 +#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_METHOD_CNT 14 +#define NV4_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x1 +#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION 15 +#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x0 +#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x1 +#define NV4_PGRAPH_INTR_EN 0x400140 +#define NV4_PGRAPH_INTR_EN_NOTIFY 0 +#define NV4_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_MISSING_HW 4 +#define NV4_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_A 8 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_B 9 +#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_CONTEXT_SWITCH 12 +#define NV4_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x1 +#define NV4_PGRAPH_INTR_EN_BUFFER_NOTIFY 16 +#define NV4_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x1 +#define NV4_PGRAPH_CTX_SWITCH1 0x400160 +#define NV4_PGRAPH_CTX_SWITCH1_GRCLASS 0 +#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12 +#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP 13 +#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE 14 +#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x2 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x3 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x4 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x5 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE 20 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_COMPATIBILITY 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_DITHER 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_TRUNCATE 0x2 +#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_MS 0x3 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25 +#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x1 +#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31 +#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x0 +#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x1 +#define NV4_PGRAPH_CTX_SWITCH2 0x400164 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT 0 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 +#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 +#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 +#define NV4_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 16 +#define NV4_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH3 0x400168 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 0 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 16 +#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x00 +#define NV4_PGRAPH_CTX_SWITCH4 0x40016C +#define NV4_PGRAPH_CTX_SWITCH4_USER_INSTANCE 0 +#define NV4_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x00 +#define NV4_PGRAPH_CTX_CACHE1(i) (0x400180+(i)*4) +#define NV4_PGRAPH_CTX_CACHE1_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE1_GRCLASS 0 +#define NV4_PGRAPH_CTX_CACHE1_CHROMA_KEY 12 +#define NV4_PGRAPH_CTX_CACHE1_USER_CLIP 13 +#define NV4_PGRAPH_CTX_CACHE1_SWIZZLE 14 +#define NV4_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 +#define NV4_PGRAPH_CTX_CACHE1_SPARE1 20 +#define NV4_PGRAPH_CTX_CACHE1_PATCH_STATUS 24 +#define NV4_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25 +#define NV4_PGRAPH_CTX_CACHE2(i) (0x4001a0+(i)*4) +#define NV4_PGRAPH_CTX_CACHE2_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE2_MONO_FORMAT 0 +#define NV4_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 +#define NV4_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 16 +#define NV4_PGRAPH_CTX_CACHE3(i) (0x4001c0+(i)*4) +#define NV4_PGRAPH_CTX_CACHE3_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 0 +#define NV4_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 16 +#define NV4_PGRAPH_CTX_CACHE4(i) (0x4001e0+(i)*4) +#define NV4_PGRAPH_CTX_CACHE4_SIZE_1 8 +#define NV4_PGRAPH_CTX_CACHE4_USER_INSTANCE 0 +#define NV4_PGRAPH_CTX_CONTROL 0x400170 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME 0 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x0 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x1 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x2 +#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x3 +#define NV4_PGRAPH_CTX_CONTROL_TIME 8 +#define NV4_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x0 +#define NV4_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x1 +#define NV4_PGRAPH_CTX_CONTROL_CHID 16 +#define NV4_PGRAPH_CTX_CONTROL_CHID_INVALID 0x0 +#define NV4_PGRAPH_CTX_CONTROL_CHID_VALID 0x1 +#define NV4_PGRAPH_CTX_CONTROL_CHANGE 20 +#define NV4_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x0 +#define NV4_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x1 +#define NV4_PGRAPH_CTX_CONTROL_SWITCHING 24 +#define NV4_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x0 +#define NV4_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x1 +#define NV4_PGRAPH_CTX_CONTROL_DEVICE 28 +#define NV4_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x0 +#define NV4_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x1 +#define NV4_PGRAPH_CTX_USER 0x400174 +#define NV4_PGRAPH_CTX_USER_SUBCH 13 +#define NV4_PGRAPH_CTX_USER_SUBCH_0 0x0 +#define NV4_PGRAPH_CTX_USER_CHID 24 +#define NV4_PGRAPH_CTX_USER_CHID_0 0x0 +#define NV4_PGRAPH_FIFO 0x400720 +#define NV4_PGRAPH_FIFO_ACCESS 0 +#define NV4_PGRAPH_FIFO_ACCESS_DISABLED 0x0 +#define NV4_PGRAPH_FIFO_ACCESS_ENABLED 0x1 +#define NV4_PGRAPH_FFINTFC_FIFO_0(i) (0x400730+(i)*4) +#define NV4_PGRAPH_FFINTFC_FIFO_0_SIZE_1 4 +#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG 0 +#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x0 +#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x1 +// Note: shift left by 1 (3:1). Subch number = 0-7 +#define NV4_PGRAPH_FFINTFC_FIFO_0_SUBCH 1 +#define NV4_PGRAPH_FFINTFC_FIFO_0_MTHD 4 +#define NV4_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x0 +#define NV4_PGRAPH_FFINTFC_FIFO_1(i) (0x400740+(i)*4) +#define NV4_PGRAPH_FFINTFC_FIFO_1_SIZE_1 4 +#define NV4_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 0 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR 0x400750 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_WRITE 0 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x0 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_READ 4 +#define NV4_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x0 +#define NV4_PGRAPH_FFINTFC_ST2 0x400754 +#define NV4_PGRAPH_FFINTFC_ST2_STATUS 0 +#define NV4_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_MTHD 1 +#define NV4_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH 12 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_0 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_1 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_2 0x2 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_3 0x3 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_4 0x4 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_5 0x5 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_6 0x6 +#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_7 0x7 +#define NV4_PGRAPH_FFINTFC_ST2_CHID 15 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_0 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_1 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_2 0x2 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_3 0x3 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_4 0x4 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_5 0x5 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_6 0x6 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_7 0x7 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_8 0x8 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_9 0x9 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_10 0xA +#define NV4_PGRAPH_FFINTFC_ST2_CHID_11 0xB +#define NV4_PGRAPH_FFINTFC_ST2_CHID_12 0xC +#define NV4_PGRAPH_FFINTFC_ST2_CHID_13 0xD +#define NV4_PGRAPH_FFINTFC_ST2_CHID_14 0xE +#define NV4_PGRAPH_FFINTFC_ST2_CHID_15 0xF +#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS 19 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT 20 +#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT_CLEAR 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT_SET 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD 21 +#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD_CLEAR 0x0 +#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD_SET 0x1 +#define NV4_PGRAPH_FFINTFC_ST2_D 0x400758 +#define NV4_PGRAPH_FFINTFC_ST2_D_ARGUMENT 0 +#define NV4_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x0 +#define NV4_PGRAPH_STATUS 0x400700 +#define NV4_PGRAPH_STATUS_STATE 0 +#define NV4_PGRAPH_STATUS_STATE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_STATE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_XY_LOGIC 4 +#define NV4_PGRAPH_STATUS_XY_LOGIC_IDLE 0x0 +#define NV4_PGRAPH_STATUS_XY_LOGIC_BUSY 0x1 +#define NV4_PGRAPH_STATUS_FE 5 +#define NV4_PGRAPH_STATUS_FE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_FE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_RASTERIZER 6 +#define NV4_PGRAPH_STATUS_RASTERIZER_IDLE 0x0 +#define NV4_PGRAPH_STATUS_RASTERIZER_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_NOTIFY 8 +#define NV4_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_REGISTER 12 +#define NV4_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_DMA 16 +#define NV4_PGRAPH_STATUS_PORT_DMA_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_DMA_BUSY 0x1 +#define NV4_PGRAPH_STATUS_DMA_ENGINE 17 +#define NV4_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_DMA_NOTIFY 20 +#define NV4_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x0 +#define NV4_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x1 +#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21 +#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x0 +#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x1 +#define NV4_PGRAPH_STATUS_D3D 24 +#define NV4_PGRAPH_STATUS_D3D_IDLE 0x0 +#define NV4_PGRAPH_STATUS_D3D_BUSY 0x1 +#define NV4_PGRAPH_STATUS_CACHE 25 +#define NV4_PGRAPH_STATUS_CACHE_IDLE 0x0 +#define NV4_PGRAPH_STATUS_CACHE_BUSY 0x1 +#define NV4_PGRAPH_STATUS_LIGHTING 26 +#define NV4_PGRAPH_STATUS_LIGHTING_IDLE 0x0 +#define NV4_PGRAPH_STATUS_LIGHTING_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PREROP 27 +#define NV4_PGRAPH_STATUS_PREROP_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PREROP_BUSY 0x1 +#define NV4_PGRAPH_STATUS_ROP 28 +#define NV4_PGRAPH_STATUS_ROP_IDLE 0x0 +#define NV4_PGRAPH_STATUS_ROP_BUSY 0x1 +#define NV4_PGRAPH_STATUS_PORT_USER 29 +#define NV4_PGRAPH_STATUS_PORT_USER_IDLE 0x0 +#define NV4_PGRAPH_STATUS_PORT_USER_BUSY 0x1 +#define NV4_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV4_PGRAPH_TRAPPED_ADDR_MTHD 2 +#define NV4_PGRAPH_TRAPPED_ADDR_SUBCH 13 +#define NV4_PGRAPH_TRAPPED_ADDR_CHID 24 +#define NV4_PGRAPH_TRAPPED_DATA 0x400708 +#define NV4_PGRAPH_TRAPPED_DATA_VALUE 0 +#define NV4_PGRAPH_SURFACE 0x40070C +#define NV4_PGRAPH_SURFACE_TYPE 0 +#define NV4_PGRAPH_SURFACE_TYPE_INVALID 0x0 +#define NV4_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x1 +#define NV4_PGRAPH_SURFACE_TYPE_SWIZZLE 0x2 +#define NV4_PGRAPH_NOTIFY 0x400714 +#define NV4_PGRAPH_NOTIFY_BUFFER_REQ 0 +#define NV4_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x0 +#define NV4_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x1 +#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE 8 +#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x0 +#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x1 +#define NV4_PGRAPH_NOTIFY_REQ 16 +#define NV4_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x0 +#define NV4_PGRAPH_NOTIFY_REQ_PENDING 0x1 +#define NV4_PGRAPH_NOTIFY_STYLE 20 +#define NV4_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x0 +#define NV4_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x1 +#define NV4_PGRAPH_BOFFSET(i) (0x400640+(i)*4) +//used for all +#define NV4_PGRAPH_BOFFSET_LINADRS_DEFAULT 0x0 +#define NV4_PGRAPH_BOFFSET_SIZE_1 6 +#define NV4_PGRAPH_BOFFSET_LINADRS 0 +#define NV4_PGRAPH_BOFFSET_LINADRS_0 0x0 +#define NV4_PGRAPH_BOFFSET0 0x400640 +#define NV4_PGRAPH_BOFFSET0_ALIAS_1 NV_PGRAPH_BOFFSET(0) +#define NV4_PGRAPH_BOFFSET0_LINADRS 0 +#define NV4_PGRAPH_BOFFSET1 0x400644 +#define NV4_PGRAPH_BOFFSET1_ALIAS_1 NV_PGRAPH_BOFFSET(1) +#define NV4_PGRAPH_BOFFSET1_LINADRS 0 +#define NV4_PGRAPH_BOFFSET2 0x400648 +#define NV4_PGRAPH_BOFFSET2_ALIAS_1 NV_PGRAPH_BOFFSET(2) +#define NV4_PGRAPH_BOFFSET2_LINADRS 0 +#define NV4_PGRAPH_BOFFSET3 0x40064C +#define NV4_PGRAPH_BOFFSET3_ALIAS_1 NV_PGRAPH_BOFFSET(3) +#define NV4_PGRAPH_BOFFSET3_LINADRS 0 +#define NV4_PGRAPH_BOFFSET4 0x400650 +#define NV4_PGRAPH_BOFFSET4_ALIAS_1 NV_PGRAPH_BOFFSET(4) +#define NV4_PGRAPH_BOFFSET4_LINADRS 0 +#define NV4_PGRAPH_BOFFSET5 0x400654 +#define NV4_PGRAPH_BOFFSET5_ALIAS_1 NV_PGRAPH_BOFFSET(5) +#define NV4_PGRAPH_BOFFSET5_LINADRS 0 +#define NV4_PGRAPH_BBASE(i) (0x400658+(i)*4) +//used for all +#define NV4_PGRAPH_BBASE_LINADRS_DEFAULT 0x0 +#define NV4_PGRAPH_BBASE_SIZE_1 6 +#define NV4_PGRAPH_BBASE_LINADRS 0 +#define NV4_PGRAPH_BBASE0 0x400658 +#define NV4_PGRAPH_BBASE0_ALIAS_1 NV_PGRAPH_BBASE(0) +#define NV4_PGRAPH_BBASE0_LINADRS 0 +#define NV4_PGRAPH_BBASE1 0x40065c +#define NV4_PGRAPH_BBASE1_ALIAS_1 NV_PGRAPH_BBASE(1) +#define NV4_PGRAPH_BBASE1_LINADRS 0 +#define NV4_PGRAPH_BBASE2 0x400660 +#define NV4_PGRAPH_BBASE2_ALIAS_1 NV_PGRAPH_BBASE(2) +#define NV4_PGRAPH_BBASE2_LINADRS 0 +#define NV4_PGRAPH_BBASE3 0x400664 +#define NV4_PGRAPH_BBASE3_ALIAS_1 NV_PGRAPH_BBASE(3) +#define NV4_PGRAPH_BBASE3_LINADRS 0 +#define NV4_PGRAPH_BBASE4 0x400668 +#define NV4_PGRAPH_BBASE4_ALIAS_1 NV_PGRAPH_BBASE(4) +#define NV4_PGRAPH_BBASE4_LINADRS 0 +#define NV4_PGRAPH_BBASE5 0x40066C +#define NV4_PGRAPH_BBASE5_ALIAS_1 NV_PGRAPH_BBASE(5) +#define NV4_PGRAPH_BBASE5_LINADRS 0 +#define NV4_PGRAPH_BPITCH(i) (0x400670+(i)*4) +//used for all +#define NV4_PGRAPH_BPITCH_LINADRS_DEFAULT 0x0 +#define NV4_PGRAPH_BPITCH_SIZE_1 5 +#define NV4_PGRAPH_BPITCH_VALUE 0 // use bit 0 for all +#define NV4_PGRAPH_BPITCH_VALUE_0 0x0 +#define NV4_PGRAPH_BPITCH0 0x400670 +#define NV4_PGRAPH_BPITCH0_ALIAS_1 NV_PGRAPH_BPITCH(0) +#define NV4_PGRAPH_BPITCH1 0x400674 +#define NV4_PGRAPH_BPITCH1_ALIAS_1 NV_PGRAPH_BPITCH(1) +#define NV4_PGRAPH_BPITCH2 0x400678 +#define NV4_PGRAPH_BPITCH2_ALIAS_1 NV_PGRAPH_BPITCH(2) +#define NV4_PGRAPH_BPITCH3 0x40067C +#define NV4_PGRAPH_BPITCH3_ALIAS_1 NV_PGRAPH_BPITCH(3) +#define NV4_PGRAPH_BPITCH4 0x400680 +#define NV4_PGRAPH_BPITCH4_ALIAS_1 NV_PGRAPH_BPITCH(4) +#define NV4_PGRAPH_BLIMIT(i) (0x400684+(i)*4) +//following two used for all +#define NV4_PGRAPH_BLIMIT_SIZE_1 6 +#define NV4_PGRAPH_BLIMIT_VALUE 0 +#define NV4_PGRAPH_BLIMIT_TYPE 31 +#define NV4_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x0 +#define NV4_PGRAPH_BLIMIT_TYPE_NULL 0x1 +#define NV4_PGRAPH_BLIMIT0 0x400684 +#define NV4_PGRAPH_BLIMIT0_ALIAS_1 NV_PGRAPH_BLIMIT(0) +#define NV4_PGRAPH_BLIMIT1 0x400688 +#define NV4_PGRAPH_BLIMIT1_ALIAS_1 NV_PGRAPH_BLIMIT(1) +#define NV4_PGRAPH_BLIMIT2 0x40068c +#define NV4_PGRAPH_BLIMIT2_ALIAS_1 NV_PGRAPH_BLIMIT(2) +#define NV4_PGRAPH_BLIMIT3 0x400690 +#define NV4_PGRAPH_BLIMIT3_ALIAS_1 NV_PGRAPH_BLIMIT(3) +#define NV4_PGRAPH_BLIMIT4 0x400694 +#define NV4_PGRAPH_BLIMIT4_ALIAS_1 NV_PGRAPH_BLIMIT(4) +#define NV4_PGRAPH_BLIMIT5 0x400698 +#define NV4_PGRAPH_BLIMIT5_ALIAS_1 NV_PGRAPH_BLIMIT(5) +#define NV4_PGRAPH_BSWIZZLE2 0x40069c +#define NV4_PGRAPH_BSWIZZLE2_WIDTH 16 +#define NV4_PGRAPH_BSWIZZLE2_WIDTH_0 0x0 +#define NV4_PGRAPH_BSWIZZLE2_HEIGHT 24 +#define NV4_PGRAPH_BSWIZZLE2_HEIGHT_0 0x0 +#define NV4_PGRAPH_BSWIZZLE5 0x4006a0 +#define NV4_PGRAPH_BSWIZZLE5_WIDTH 16 +#define NV4_PGRAPH_BSWIZZLE5_WIDTH_0 0x0 +#define NV4_PGRAPH_BSWIZZLE5_HEIGHT 24 +#define NV4_PGRAPH_BSWIZZLE5_HEIGHT_0 0x0 +#define NV4_PGRAPH_BPIXEL 0x400724 +#define NV4_PGRAPH_BPIXEL_DEPTH0 0 +#define NV4_PGRAPH_BPIXEL_DEPTH1 4 +#define NV4_PGRAPH_BPIXEL_DEPTH2 8 +#define NV4_PGRAPH_BPIXEL_DEPTH3 12 +#define NV4_PGRAPH_BPIXEL_DEPTH4 16 +#define NV4_PGRAPH_BPIXEL_DEPTH5 20 + +// valid for depth0-depth5 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_INVALID 0x0 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y8 0x1 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1R5G5B5_Z1R5G5B5 0x2 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1R5G5B5_O1R5G5B5 0x3 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_A1R5G5B5 0x4 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_R5G6B5 0x5 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y16 0x6 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_Z8R8G8B8 0x7 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_O1Z7R8G8B8 0x8 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x9 +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1A7R8G8B8_O1A7R8G8B8 0xA +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_O8R8G8B8 0xB +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_A8R8G8B8 0xC +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y32 0xD +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_V8YB8U8YA8 0xE +#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_YB8V8YA8U8 0xF + +#define NV4_PGRAPH_LIMIT_VIOL_PIX 0x400610 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_ADRS 0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT 29 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_Z 0x400614 +#define NV4_PGRAPH_LIMIT_VIOL_Z_ADRS 0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT 30 +#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x1 +#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31 +#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x0 +#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x1 +#define NV4_PGRAPH_STATE 0x400710 +#define NV4_PGRAPH_STATE_BUFFER_0 0 +#define NV4_PGRAPH_STATE_BUFFER_0_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_0_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_1 1 +#define NV4_PGRAPH_STATE_BUFFER_1_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_1_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_2 2 +#define NV4_PGRAPH_STATE_BUFFER_2_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_2_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_3 3 +#define NV4_PGRAPH_STATE_BUFFER_3_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_3_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_4 4 +#define NV4_PGRAPH_STATE_BUFFER_4_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_4_VALID 0x1 +#define NV4_PGRAPH_STATE_BUFFER_5 5 +#define NV4_PGRAPH_STATE_BUFFER_5_INVALID 0x0 +#define NV4_PGRAPH_STATE_BUFFER_5_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_0 8 +#define NV4_PGRAPH_STATE_PITCH_0_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_0_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_1 9 +#define NV4_PGRAPH_STATE_PITCH_1_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_1_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_2 10 +#define NV4_PGRAPH_STATE_PITCH_2_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_2_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_3 11 +#define NV4_PGRAPH_STATE_PITCH_3_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_3_VALID 0x1 +#define NV4_PGRAPH_STATE_PITCH_4 12 +#define NV4_PGRAPH_STATE_PITCH_4_INVALID 0x0 +#define NV4_PGRAPH_STATE_PITCH_4_VALID 0x1 +#define NV4_PGRAPH_STATE_CHROMA_COLOR 16 +#define NV4_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x0 +#define NV4_PGRAPH_STATE_CHROMA_COLOR_VALID 0x1 +#define NV4_PGRAPH_STATE_CHROMA_COLORFMT 17 +#define NV4_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x1 +#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT 20 +#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x1 +#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT 21 +#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x1 +#define NV4_PGRAPH_STATE_CPATTERN_SELECT 22 +#define NV4_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x0 +#define NV4_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_COLOR0 24 +#define NV4_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_COLOR1 25 +#define NV4_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_PATT0 26 +#define NV4_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_PATT0_VALID 0x1 +#define NV4_PGRAPH_STATE_PATTERN_PATT1 27 +#define NV4_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x0 +#define NV4_PGRAPH_STATE_PATTERN_PATT1_VALID 0x1 +#define NV4_PGRAPH_CACHE_INDEX 0x400728 +#define NV4_PGRAPH_CACHE_INDEX_BANK 2 +#define NV4_PGRAPH_CACHE_INDEX_BANK_10 0x0 +#define NV4_PGRAPH_CACHE_INDEX_BANK_32 0x1 +#define NV4_PGRAPH_CACHE_INDEX_ADRS 3 +#define NV4_PGRAPH_CACHE_INDEX_ADRS_0 0x0 +#define NV4_PGRAPH_CACHE_INDEX_ADRS_1024 0x400 +#define NV4_PGRAPH_CACHE_INDEX_OP 13 +#define NV4_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x0 +#define NV4_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x1 +#define NV4_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x2 +#define NV4_PGRAPH_CACHE_RAM 0x40072c +#define NV4_PGRAPH_CACHE_RAM_VALUE 0 +#define NV4_PGRAPH_DMA_PITCH 0x400760 +#define NV4_PGRAPH_DMA_PITCH_S0 0 +#define NV4_PGRAPH_DMA_PITCH_S1 16 +#define NV4_PGRAPH_DVD_COLORFMT 0x400764 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE 0 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 +#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY 8 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 +#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 +#define NV4_PGRAPH_SCALED_FORMAT 0x400768 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN 16 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x0 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x1 +#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x2 +#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24 +#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x0 +#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x1 +#define NV4_PGRAPH_PATT_COLOR0 0x400800 +#define NV4_PGRAPH_PATT_COLOR0_VALUE 0 +#define NV4_PGRAPH_PATT_COLOR1 0x400804 +#define NV4_PGRAPH_PATT_COLOR1_VALUE 0 +#define NV4_PGRAPH_PATT_COLORRAM(i) (0x400900+(i)*4) +#define NV4_PGRAPH_PATT_COLORRAM_SIZE_1 64 +#define NV4_PGRAPH_PATT_COLORRAM_VALUE 0 +#define NV4_PGRAPH_PATTERN(i) (0x400808+(i)*4) +#define NV4_PGRAPH_PATTERN_SIZE_1 2 +#define NV4_PGRAPH_PATTERN_BITMAP 0 +#define NV4_PGRAPH_PATTERN_SHAPE 0x400810 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE 0 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x0 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x1 +#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x2 +#define NV4_PGRAPH_PATTERN_SHAPE_SELECT 4 +#define NV4_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x0 +#define NV4_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x1 +#define NV4_PGRAPH_MONO_COLOR0 0x400600 +#define NV4_PGRAPH_MONO_COLOR0_VALUE 0 +#define NV4_PGRAPH_ROP3 0x400604 +#define NV4_PGRAPH_ROP3_VALUE 0 +#define NV4_PGRAPH_CHROMA 0x400814 +#define NV4_PGRAPH_CHROMA_VALUE 0 +#define NV4_PGRAPH_BETA_AND 0x400608 +#define NV4_PGRAPH_BETA_AND_VALUE_FRACTION 23 +#define NV4_PGRAPH_BETA_PREMULT 0x40060c +#define NV4_PGRAPH_BETA_PREMULT_VALUE 0 +#define NV4_PGRAPH_CONTROL0 0x400818 +#define NV4_PGRAPH_CONTROL0_ALPHAREF 0 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC 8 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_NEVER 0x1 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_LESS 0x2 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_EQUAL 0x3 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_LESSEQUAL 0x4 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_GREATER 0x5 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_NOTEQUAL 0x6 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_GREATEREQUAL 0x7 +#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_ALWAYS 0x8 +#define NV4_PGRAPH_CONTROL0_ALPHATESTENABLE 12 +#define NV4_PGRAPH_CONTROL0_ALPHATESTENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ZENABLE 14 +#define NV4_PGRAPH_CONTROL0_ZENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_ZENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ZFUNC 16 +#define NV4_PGRAPH_CONTROL0_ZFUNC_NEVER 0x1 +#define NV4_PGRAPH_CONTROL0_ZFUNC_LESS 0x2 +#define NV4_PGRAPH_CONTROL0_ZFUNC_EQUAL 0x3 +#define NV4_PGRAPH_CONTROL0_ZFUNC_LESSEQUAL 0x4 +#define NV4_PGRAPH_CONTROL0_ZFUNC_GREATER 0x5 +#define NV4_PGRAPH_CONTROL0_ZFUNC_NOTEQUAL 0x6 +#define NV4_PGRAPH_CONTROL0_ZFUNC_GREATEREQUAL 0x7 +#define NV4_PGRAPH_CONTROL0_ZFUNC_ALWAYS 0x8 +#define NV4_PGRAPH_CONTROL0_CULLMODE 20 +#define NV4_PGRAPH_CONTROL0_CULLMODE_NONE 0x1 +#define NV4_PGRAPH_CONTROL0_CULLMODE_CW 0x2 +#define NV4_PGRAPH_CONTROL0_CULLMODE_CCW 0x3 +#define NV4_PGRAPH_CONTROL0_DITHERENABLE 22 +#define NV4_PGRAPH_CONTROL0_DITHERENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_DITHERENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE 23 +#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE 24 +#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE 25 +#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE 26 +#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE 27 +#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE 28 +#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE 29 +#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL0_Z_FORMAT 30 +#define NV4_PGRAPH_CONTROL0_Z_FORMAT_FIXED 0x1 +#define NV4_PGRAPH_CONTROL0_Z_FORMAT_FLOAT 0x2 +#define NV4_PGRAPH_CONTROL1 0x40081c +#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE 0 +#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC 4 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_NEVER 0x1 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_LESS 0x2 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_EQUAL 0x3 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_LESSEQUAL 0x4 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_GREATER 0x5 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_NOTEQUAL 0x6 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_GREATEREQUAL 0x7 +#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_ALWAYS 0x8 +#define NV4_PGRAPH_CONTROL1_STENCIL_REF 8 +#define NV4_PGRAPH_CONTROL1_STENCIL_MASK_READ 16 +#define NV4_PGRAPH_CONTROL1_STENCIL_MASK_WRITE 24 +#define NV4_PGRAPH_CONTROL2 0x400820 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL 0 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_KEEP 0x1 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_ZERO 0x2 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_REPLACE 0x3 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INCRSAT 0x4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_DECRSAT 0x5 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INVERT 0x6 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INCR 0x7 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_DECR 0x8 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL 4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_KEEP 0x1 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_ZERO 0x2 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_REPLACE 0x3 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INCRSAT 0x4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_DECRSAT 0x5 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INVERT 0x6 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INCR 0x7 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_DECR 0x8 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS 8 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_KEEP 0x1 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_ZERO 0x2 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_REPLACE 0x3 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INCRSAT 0x4 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_DECRSAT 0x5 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INVERT 0x6 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INCR 0x7 +#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_DECR 0x8 +#define NV4_PGRAPH_BLEND 0x400824 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND 0 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECAL 0x1 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATE 0x2 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x3 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x4 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECALMASK 0x5 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x6 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_COPY 0x7 +#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_ADD 0x8 +#define NV4_PGRAPH_BLEND_MASK_BIT 4 +#define NV4_PGRAPH_BLEND_MASK_BIT_LSB 0x1 +#define NV4_PGRAPH_BLEND_MASK_BIT_MSB 0x2 +#define NV4_PGRAPH_BLEND_SHADEMODE 6 +#define NV4_PGRAPH_BLEND_SHADEMODE_FLAT 0x1 +#define NV4_PGRAPH_BLEND_SHADEMODE_GOURAUD 0x2 +#define NV4_PGRAPH_BLEND_SHADEMODE_PHONG 0x3 +#define NV4_PGRAPH_BLEND_TEXTUREPERSPECTIVE 8 +#define NV4_PGRAPH_BLEND_TEXTUREPERSPECTIVE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_SPECULARENABLE 12 +#define NV4_PGRAPH_BLEND_SPECULARENABLE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_FOGENABLE 16 +#define NV4_PGRAPH_BLEND_FOGENABLE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_ALPHABLENDENABLE 20 +#define NV4_PGRAPH_BLEND_ALPHABLENDENABLE_TRUE 0x1 +#define NV4_PGRAPH_BLEND_SRCBLEND 24 +#define NV4_PGRAPH_BLEND_SRCBLEND_ZERO 0x1 +#define NV4_PGRAPH_BLEND_SRCBLEND_ONE 0x2 +#define NV4_PGRAPH_BLEND_SRCBLEND_SRCCOLOR 0x3 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCCOLOR 0x4 +#define NV4_PGRAPH_BLEND_SRCBLEND_SRCALPHA 0x5 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCALPHA 0x6 +#define NV4_PGRAPH_BLEND_SRCBLEND_DESTALPHA 0x7 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVDESTALPHA 0x8 +#define NV4_PGRAPH_BLEND_SRCBLEND_DESTCOLOR 0x9 +#define NV4_PGRAPH_BLEND_SRCBLEND_INVDESTCOLOR 0xA +#define NV4_PGRAPH_BLEND_SRCBLEND_SRCALPHASAT 0xB +#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCALPHASAT 0xC +#define NV4_PGRAPH_BLEND_SRCBLEND_BETA 0xD +#define NV4_PGRAPH_BLEND_DESTBLEND 28 +#define NV4_PGRAPH_BLEND_DESTBLEND_ZERO 0x1 +#define NV4_PGRAPH_BLEND_DESTBLEND_ONE 0x2 +#define NV4_PGRAPH_BLEND_DESTBLEND_SRCCOLOR 0x3 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVSRCCOLOR 0x4 +#define NV4_PGRAPH_BLEND_DESTBLEND_SRCALPHA 0x5 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVSRCALPHA 0x6 +#define NV4_PGRAPH_BLEND_DESTBLEND_DESTALPHA 0x7 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVDESTALPHA 0x8 +#define NV4_PGRAPH_BLEND_DESTBLEND_DESTCOLOR 0x9 +#define NV4_PGRAPH_BLEND_DESTBLEND_INVDESTCOLOR 0xA +#define NV4_PGRAPH_BLEND_DESTBLEND_SRCALPHASAT 0xB +#define NV4_PGRAPH_DPRAM_INDEX 0x400828 +#define NV4_PGRAPH_DPRAM_INDEX_ADRS 0 +#define NV4_PGRAPH_DPRAM_INDEX_ADRS_0 0x0 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT 8 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x0 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x1 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x2 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x3 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x4 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x5 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x6 +#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x7 +#define NV4_PGRAPH_DPRAM_DATA 0x40082c +#define NV4_PGRAPH_DPRAM_DATA_VALUE 0 +#define NV4_PGRAPH_DPRAM_ADRS_0 0x40082c +#define NV4_PGRAPH_DPRAM_ADRS_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ADRS_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_ADRS_1 0x40082c +#define NV4_PGRAPH_DPRAM_ADRS_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ADRS_1_VALUE 0 +#define NV4_PGRAPH_DPRAM_DATA_0 0x40082c +#define NV4_PGRAPH_DPRAM_DATA_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_DATA_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_DATA_1 0x40082c +#define NV4_PGRAPH_DPRAM_DATA_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_DATA_1_VALUE 0 +#define NV4_PGRAPH_DPRAM_WE_0 0x40082c +#define NV4_PGRAPH_DPRAM_WE_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_WE_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_WE_1 0x40082c +#define NV4_PGRAPH_DPRAM_WE_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_WE_1_VALUE 0 +#define NV4_PGRAPH_DPRAM_ALPHA_0 0x40082c +#define NV4_PGRAPH_DPRAM_ALPHA_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ALPHA_0_VALUE 0 +#define NV4_PGRAPH_DPRAM_ALPHA_1 0x40082c +#define NV4_PGRAPH_DPRAM_ALPHA_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA +#define NV4_PGRAPH_DPRAM_ALPHA_1_VALUE 0 +#define NV4_PGRAPH_STORED_FMT 0x400830 +#define NV4_PGRAPH_STORED_FMT_MONO0 0 +#define NV4_PGRAPH_STORED_FMT_PATT0 8 +#define NV4_PGRAPH_STORED_FMT_PATT1 16 +#define NV4_PGRAPH_STORED_FMT_CHROMA 24 +#define NV4_PGRAPH_FORMATS 0x400618 +#define NV4_PGRAPH_FORMATS_ROP 0 +#define NV4_PGRAPH_FORMATS_ROP_Y8 0x0 +#define NV4_PGRAPH_FORMATS_ROP_RGB15 0x1 +#define NV4_PGRAPH_FORMATS_ROP_RGB16 0x2 +#define NV4_PGRAPH_FORMATS_ROP_Y16 0x3 +#define NV4_PGRAPH_FORMATS_ROP_INVALID 0x4 +#define NV4_PGRAPH_FORMATS_ROP_RGB24 0x5 +#define NV4_PGRAPH_FORMATS_ROP_RGB30 0x6 +#define NV4_PGRAPH_FORMATS_ROP_Y32 0x7 +#define NV4_PGRAPH_FORMATS_SRC 4 +#define NV4_PGRAPH_FORMATS_SRC_INVALID 0x0 +#define NV4_PGRAPH_FORMATS_SRC_LE_Y8 0x1 +#define NV4_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x2 +#define NV4_PGRAPH_FORMATS_SRC_LE_X24Y8 0x3 +#define NV4_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x6 +#define NV4_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x7 +#define NV4_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x8 +#define NV4_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x9 +#define NV4_PGRAPH_FORMATS_SRC_LE_R5G6B5 0xA +#define NV4_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0xB +#define NV4_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0xC +#define NV4_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0xD +#define NV4_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0xE +#define NV4_PGRAPH_FORMATS_SRC_LE_Y16 0xF +#define NV4_PGRAPH_FORMATS_SRC_LE_A16Y16 0x10 +#define NV4_PGRAPH_FORMATS_SRC_LE_X16Y16 0x11 +#define NV4_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x12 +#define NV4_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x13 +#define NV4_PGRAPH_FORMATS_SRC_LE_Y32 0x14 +#define NV4_PGRAPH_FORMATS_FB 12 +#define NV4_PGRAPH_FORMATS_FB_INVALID 0x0 +#define NV4_PGRAPH_FORMATS_FB_Y8 0x1 +#define NV4_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x2 +#define NV4_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x3 +#define NV4_PGRAPH_FORMATS_FB_A1R5G5B5 0x4 +#define NV4_PGRAPH_FORMATS_FB_R5G6B5 0x5 +#define NV4_PGRAPH_FORMATS_FB_Y16 0x6 +#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x7 +#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x8 +#define NV4_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x9 +#define NV4_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0xA +#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0xB +#define NV4_PGRAPH_FORMATS_FB_A8R8G8B8 0xC +#define NV4_PGRAPH_FORMATS_FB_Y32 0xD +#define NV4_PGRAPH_FORMATS_FB_V8YB8U8YA8 0xE +#define NV4_PGRAPH_FORMATS_FB_YB8V8YA8U8 0xF +#define NV4_PGRAPH_ABS_X_RAM(i) (0x400400+(i)*4) +#define NV4_PGRAPH_ABS_X_RAM_SIZE_1 32 +#define NV4_PGRAPH_ABS_X_RAM_VALUE 0 +#define NV4_PGRAPH_X_RAM_BPORT(i) (0x400c00+(i)*4) +#define NV4_PGRAPH_X_RAM_BPORT_SIZE_1 32 +#define NV4_PGRAPH_X_RAM_BPORT_VALUE 0 +#define NV4_PGRAPH_ABS_Y_RAM(i) (0x400480+(i)*4) +#define NV4_PGRAPH_ABS_Y_RAM_SIZE_1 32 +#define NV4_PGRAPH_ABS_Y_RAM_VALUE 0 +#define NV4_PGRAPH_Y_RAM_BPORT(i) (0x400c80+(i)*4) +#define NV4_PGRAPH_Y_RAM_BPORT_SIZE_1 32 +#define NV4_PGRAPH_Y_RAM_BPORT_VALUE 0 +#define NV4_PGRAPH_XY_LOGIC_MISC0 0x400514 +#define NV4_PGRAPH_XY_LOGIC_MISC0_COUNTER 0 +#define NV4_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20 +#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC0_INDEX 28 +#define NV4_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1 0x400518 +#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL 0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2 0x40051C +#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3 0x400520 +#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x1 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 16 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x0 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 24 +#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x0 +#define NV4_PGRAPH_X_MISC 0x400500 +#define NV4_PGRAPH_X_MISC_BIT33_0 0 +#define NV4_PGRAPH_X_MISC_BIT33_0_0 0x0 +#define NV4_PGRAPH_X_MISC_BIT33_1 1 +#define NV4_PGRAPH_X_MISC_BIT33_1_0 0x0 +#define NV4_PGRAPH_X_MISC_BIT33_2 2 +#define NV4_PGRAPH_X_MISC_BIT33_2_0 0x0 +#define NV4_PGRAPH_X_MISC_BIT33_3 3 +#define NV4_PGRAPH_X_MISC_BIT33_3_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_0 4 +#define NV4_PGRAPH_X_MISC_RANGE_0_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_1 5 +#define NV4_PGRAPH_X_MISC_RANGE_1_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_2 6 +#define NV4_PGRAPH_X_MISC_RANGE_2_0 0x0 +#define NV4_PGRAPH_X_MISC_RANGE_3 7 +#define NV4_PGRAPH_X_MISC_RANGE_3_0 0x0 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT 28 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x0 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x1 +#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x2 +#define NV4_PGRAPH_Y_MISC 0x400504 +#define NV4_PGRAPH_Y_MISC_BIT33_0 0 +#define NV4_PGRAPH_Y_MISC_BIT33_0_0 0x0 +#define NV4_PGRAPH_Y_MISC_BIT33_1 1 +#define NV4_PGRAPH_Y_MISC_BIT33_1_0 0x0 +#define NV4_PGRAPH_Y_MISC_BIT33_2 2 +#define NV4_PGRAPH_Y_MISC_BIT33_2_0 0x0 +#define NV4_PGRAPH_Y_MISC_BIT33_3 3 +#define NV4_PGRAPH_Y_MISC_BIT33_3_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_0 4 +#define NV4_PGRAPH_Y_MISC_RANGE_0_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_1 5 +#define NV4_PGRAPH_Y_MISC_RANGE_1_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_2 6 +#define NV4_PGRAPH_Y_MISC_RANGE_2_0 0x0 +#define NV4_PGRAPH_Y_MISC_RANGE_3 7 +#define NV4_PGRAPH_Y_MISC_RANGE_3_0 0x0 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT 28 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x0 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x1 +#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x2 +#define NV4_PGRAPH_ABS_UCLIP_XMIN 0x40053C +#define NV4_PGRAPH_ABS_UCLIP_XMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIP_XMAX 0x400544 +#define NV4_PGRAPH_ABS_UCLIP_XMAX_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIP_YMIN 0x400540 +#define NV4_PGRAPH_ABS_UCLIP_YMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIP_YMAX 0x400548 +#define NV4_PGRAPH_ABS_UCLIP_YMAX_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_XMIN 0x400560 +#define NV4_PGRAPH_ABS_UCLIPA_XMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_XMAX 0x400568 +#define NV4_PGRAPH_ABS_UCLIPA_XMAX_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_YMIN 0x400564 +#define NV4_PGRAPH_ABS_UCLIPA_YMIN_VALUE 0 +#define NV4_PGRAPH_ABS_UCLIPA_YMAX 0x40056C +#define NV4_PGRAPH_ABS_UCLIPA_YMAX_VALUE 0 +#define NV4_PGRAPH_SOURCE_COLOR 0x40050C +#define NV4_PGRAPH_SOURCE_COLOR_VALUE 0 +#define NV4_PGRAPH_SOURCE_COLOR_VALUE_0 0x0 +#define NV4_PGRAPH_VALID1 0x400508 +#define NV4_PGRAPH_VALID1_VLD 0 +#define NV4_PGRAPH_VALID1_VLD_0 0x0 +#define NV4_PGRAPH_VALID1_VLD_NOCLIP (0x1<<19) +#define NV4_PGRAPH_VALID1_VLD_SRCCOLOR (0x1<<16) +#define NV4_PGRAPH_VALID1_VLD_GOTMOVE (0x1<<21) +#define NV4_PGRAPH_VALID1_VLD_GOTX01 (0x3<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTX02 (0x7<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTX03 (0xF<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN01 (0x3<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN02 (0x7<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN03 (0xF<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTY01 (0x3<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTY02 (0x7<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTY03 (0xF<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN01 (0x3<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN02 (0x7<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN03 (0xF<<12) +#define NV4_PGRAPH_VALID1_VLD_X_OFFSET (0x1<<0) +#define NV4_PGRAPH_VALID1_VLD_XCHAIN_OFFSET (0x1<<4) +#define NV4_PGRAPH_VALID1_VLD_Y_OFFSET (0x1<<8) +#define NV4_PGRAPH_VALID1_VLD_YCHAIN_OFFSET (0x1<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTCOLOR0 (0x1<<17) +#define NV4_PGRAPH_VALID1_VLD_GOTCOLOR1 (0x1<<18) +#define NV4_PGRAPH_VALID1_VLD_GOTCLIP (0x1<<20) +#define NV4_PGRAPH_VALID1_VLD_GOTFONT (0x1<<22) +#define NV4_PGRAPH_VALID1_VLD_GOTOFFSET (0x1<<22) +#define NV4_PGRAPH_VALID1_VLD_GOTBPITCH (0x1<<2) +#define NV4_PGRAPH_VALID1_VLD_GOTBOFFSET (0x1<<3) +#define NV4_PGRAPH_VALID1_VLD_GOTDUDX (0x1<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTDVDY (0x1<<5) +#define NV4_PGRAPH_VALID1_VLD_GOTPOINT (0x1<<8) +#define NV4_PGRAPH_VALID1_VLD_GOTSIZE (0x1<<9) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCH (0x1<<10) +#define NV4_PGRAPH_VALID1_VLD_GOTSTART (0x1<<11) +#define NV4_PGRAPH_VALID1_VLD_GOTDUDX2 (0x1<<12) +#define NV4_PGRAPH_VALID1_VLD_GOTDVDY2 (0x1<<13) +#define NV4_PGRAPH_VALID1_VLD_GOTPOINT2 (0x1<<14) +#define NV4_PGRAPH_VALID1_VLD_GOTSIZE2 (0x1<<15) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCH2 (0x1<<16) +#define NV4_PGRAPH_VALID1_VLD_GOTSTART2 (0x1<<17) +#define NV4_PGRAPH_VALID1_VLD_GOTOFFSIN (0x1<<0) +#define NV4_PGRAPH_VALID1_VLD_GOTOFFSOUT (0x1<<1) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCHIN (0x1<<2) +#define NV4_PGRAPH_VALID1_VLD_GOTPITCHOUT (0x1<<3) +#define NV4_PGRAPH_VALID1_VLD_GOTLENGTH (0x1<<4) +#define NV4_PGRAPH_VALID1_VLD_GOTCOUNT (0x1<<5) +#define NV4_PGRAPH_VALID1_VLD_GOTFORMAT (0x1<<6) +#define NV4_PGRAPH_VALID1_VLD_GOTNOTIFY (0x1<<7) +#define NV4_PGRAPH_VALID1_CLIP_MIN 28 +#define NV4_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIP_MIN_ONLY 0x1 +#define NV4_PGRAPH_VALID1_CLIPA_MIN 29 +#define NV4_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x1 +#define NV4_PGRAPH_VALID1_CLIP_MAX 30 +#define NV4_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIP_MAX_ONLY 0x1 +#define NV4_PGRAPH_VALID1_CLIPA_MAX 31 +#define NV4_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x0 +#define NV4_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x1 +#define NV4_PGRAPH_VALID2 0x400578 +#define NV4_PGRAPH_VALID2_VLD2 0 +#define NV4_PGRAPH_VALID2_VLD2_0 0x0 +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE0A (1<<28) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE0C (1<<27) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE1A (1<<26) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE1C (1<<25) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBFACTOR (1<<24) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FILTER1 (1<<23) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_OFFSET1 (1<<22) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FORMAT1 (1<<21) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_BLEND (1<<20) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL2 (1<<19) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL1 (1<<18) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL0 (1<<17) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FILTER0 (1<<16) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FORMAT0 (1<<15) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_OFFSET0 (1<<14) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FOGCOLOR (1<<13) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COLORKEY (1<<12) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_V1 (1<<9) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_U1 (1<<8) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_V0 (1<<7) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_U0 (1<<6) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_X (1<<5) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_Y (1<<4) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_ZETA (1<<3) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_M (1<<2) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COLOR (1<<1) +#define NV4_PGRAPH_VALID2_VLD2_GOT3D_SPECULAR (1<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX3FULLVERTEX (0x7f<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX5FULLVERTEX (0x7f<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX6FULLVERTEX (0x1ff<<0) +#define NV4_PGRAPH_VALID2_VLD2_DX3FULLSTATE (0x3f<<13) +#define NV4_PGRAPH_VALID2_VLD2_DX5FULLSTATE (0x1ff<<12) +#define NV4_PGRAPH_VALID2_VLD2_DX6FULLSTATE (0xFfff<<13) +#define NV4_PGRAPH_ABS_ICLIP_XMAX 0x400534 +#define NV4_PGRAPH_ABS_ICLIP_XMAX_VALUE 0 +#define NV4_PGRAPH_ABS_ICLIP_YMAX 0x400538 +#define NV4_PGRAPH_ABS_ICLIP_YMAX_VALUE 0 +#define NV4_PGRAPH_CLIPX_0 0x400524 +// Valid for all clips! +#define NV4_PGRAPH_CLIP_CONDITION_IS_GT 0x0 +#define NV4_PGRAPH_CLIP_CONDITION_IS_LT 0x1 +#define NV4_PGRAPH_CLIP_CONDITION_IS_EQ 0x2 +#define NV4_PGRAPH_CLIPX_0_CLIP0_MIN 0 +#define NV4_PGRAPH_CLIPX_0_CLIP0_MAX 2 +#define NV4_PGRAPH_CLIPX_0_CLIP1_MIN 4 +#define NV4_PGRAPH_CLIPX_0_CLIP1_MAX 6 +#define NV4_PGRAPH_CLIPX_0_CLIP2_MIN 8 +#define NV4_PGRAPH_CLIPX_0_CLIP2_MAX 10 +#define NV4_PGRAPH_CLIPX_0_CLIP3_MIN 12 +#define NV4_PGRAPH_CLIPX_0_CLIP3_MAX 14 +#define NV4_PGRAPH_CLIPX_0_CLIP4_MIN 16 +#define NV4_PGRAPH_CLIPX_0_CLIP4_MAX 18 +#define NV4_PGRAPH_CLIPX_0_CLIP5_MIN 20 +#define NV4_PGRAPH_CLIPX_0_CLIP5_MAX 22 +#define NV4_PGRAPH_CLIPX_0_CLIP6_MIN 24 +#define NV4_PGRAPH_CLIPX_0_CLIP6_MAX 26 +#define NV4_PGRAPH_CLIPX_0_CLIP7_MIN 28 +#define NV4_PGRAPH_CLIPX_0_CLIP7_MAX 30 +#define NV4_PGRAPH_CLIPX_1 0x400528 +#define NV4_PGRAPH_CLIPX_1_CLIP8_MIN 0 +#define NV4_PGRAPH_CLIPX_1_CLIP8_MAX 2 +#define NV4_PGRAPH_CLIPX_1_CLIP9_MIN 4 +#define NV4_PGRAPH_CLIPX_1_CLIP9_MAX 6 +#define NV4_PGRAPH_CLIPX_1_CLIP10_MIN 8 +#define NV4_PGRAPH_CLIPX_1_CLIP10_MAX 10 +#define NV4_PGRAPH_CLIPX_1_CLIP11_MIN 12 +#define NV4_PGRAPH_CLIPX_1_CLIP11_MAX 14 +#define NV4_PGRAPH_CLIPX_1_CLIP12_MIN 16 +#define NV4_PGRAPH_CLIPX_1_CLIP12_MAX 18 +#define NV4_PGRAPH_CLIPX_1_CLIP13_MIN 20 +#define NV4_PGRAPH_CLIPX_1_CLIP13_MAX 22 +#define NV4_PGRAPH_CLIPX_1_CLIP14_MIN 24 +#define NV4_PGRAPH_CLIPX_1_CLIP14_MAX 26 +#define NV4_PGRAPH_CLIPX_1_CLIP15_MIN 28 +#define NV4_PGRAPH_CLIPX_1_CLIP15_MAX 30 +#define NV4_PGRAPH_CLIPY_0 0x40052c +#define NV4_PGRAPH_CLIPY_0_CLIP0_MIN 0 +#define NV4_PGRAPH_CLIPY_0_CLIP0_MAX 2 +#define NV4_PGRAPH_CLIPY_0_CLIP1_MIN 4 +#define NV4_PGRAPH_CLIPY_0_CLIP1_MAX 6 +#define NV4_PGRAPH_CLIPY_0_CLIP2_MIN 8 +#define NV4_PGRAPH_CLIPY_0_CLIP2_MAX 10 +#define NV4_PGRAPH_CLIPY_0_CLIP3_MIN 12 +#define NV4_PGRAPH_CLIPY_0_CLIP3_MAX 14 +#define NV4_PGRAPH_CLIPY_0_CLIP4_MIN 16 +#define NV4_PGRAPH_CLIPY_0_CLIP4_MAX 18 +#define NV4_PGRAPH_CLIPY_0_CLIP5_MIN 20 +#define NV4_PGRAPH_CLIPY_0_CLIP5_MAX 22 +#define NV4_PGRAPH_CLIPY_0_CLIP6_MIN 24 +#define NV4_PGRAPH_CLIPY_0_CLIP6_MAX 26 +#define NV4_PGRAPH_CLIPY_0_CLIP7_MIN 28 +#define NV4_PGRAPH_CLIPY_0_CLIP7_MAX 30 +#define NV4_PGRAPH_CLIPY_1 0x400530 +#define NV4_PGRAPH_CLIPY_1_CLIP8_MIN 0 +#define NV4_PGRAPH_CLIPY_1_CLIP8_MAX 2 +#define NV4_PGRAPH_CLIPY_1_CLIP9_MIN 4 +#define NV4_PGRAPH_CLIPY_1_CLIP9_MAX 6 +#define NV4_PGRAPH_CLIPY_1_CLIP10_MIN 8 +#define NV4_PGRAPH_CLIPY_1_CLIP10_MAX 10 +#define NV4_PGRAPH_CLIPY_1_CLIP11_MIN 12 +#define NV4_PGRAPH_CLIPY_1_CLIP11_MAX 14 +#define NV4_PGRAPH_CLIPY_1_CLIP12_MIN 16 +#define NV4_PGRAPH_CLIPY_1_CLIP12_MAX 18 +#define NV4_PGRAPH_CLIPY_1_CLIP13_MIN 20 +#define NV4_PGRAPH_CLIPY_1_CLIP13_MAX 22 +#define NV4_PGRAPH_CLIPY_1_CLIP14_MIN 24 +#define NV4_PGRAPH_CLIPY_1_CLIP14_MAX 26 +#define NV4_PGRAPH_CLIPY_1_CLIP15_MIN 28 +#define NV4_PGRAPH_CLIPY_1_CLIP15_MAX 30 +#define NV4_PGRAPH_MISC24_0 0x400510 +#define NV4_PGRAPH_MISC24_0_VALUE 0 +#define NV4_PGRAPH_MISC24_1 0x400570 +#define NV4_PGRAPH_MISC24_1_VALUE 0 +#define NV4_PGRAPH_MISC24_2 0x400574 +#define NV4_PGRAPH_MISC24_2_VALUE 0 +#define NV4_PGRAPH_PASSTHRU_0 0x40057C +#define NV4_PGRAPH_PASSTHRU_0_VALUE 0 +#define NV4_PGRAPH_PASSTHRU_1 0x400580 +#define NV4_PGRAPH_PASSTHRU_1_VALUE 0 +#define NV4_PGRAPH_PASSTHRU_2 0x400584 +#define NV4_PGRAPH_PASSTHRU_2_VALUE 0 +#define NV4_PGRAPH_U_RAM(i) (0x400d00+(i)*4) +#define NV4_PGRAPH_U_RAM_SIZE_1 16 +#define NV4_PGRAPH_U_RAM_VALUE 6 +#define NV4_PGRAPH_V_RAM(i) (0x400d40+(i)*4) +#define NV4_PGRAPH_V_RAM_SIZE_1 16 +#define NV4_PGRAPH_V_RAM_VALUE 6 +#define NV4_PGRAPH_M_RAM(i) (0x400d80+(i)*4) +#define NV4_PGRAPH_M_RAM_SIZE_1 16 +#define NV4_PGRAPH_M_RAM_VALUE 6 +#define NV4_PGRAPH_D3D_XY 0x4005c0 +#define NV4_PGRAPH_D3D_XY_X_VALUE 0 +#define NV4_PGRAPH_D3D_XY_Y_VALUE 16 +#define NV4_PGRAPH_D3D_U0 0x4005c4 +#define NV4_PGRAPH_D3D_U0_VALUE 6 +#define NV4_PGRAPH_D3D_V0 0x4005c8 +#define NV4_PGRAPH_D3D_V0_VALUE 6 +#define NV4_PGRAPH_D3D_U1 0x4005cc +#define NV4_PGRAPH_D3D_U1_VALUE 6 +#define NV4_PGRAPH_D3D_V1 0x4005d0 +#define NV4_PGRAPH_D3D_V1_VALUE 6 +#define NV4_PGRAPH_D3D_ZETA 0x4005d4 +#define NV4_PGRAPH_D3D_ZETA_VALUE 0 +#define NV4_PGRAPH_D3D_RGB 0x4005d8 +#define NV4_PGRAPH_D3D_RGB_VALUE 0 +#define NV4_PGRAPH_D3D_S 0x4005dc +#define NV4_PGRAPH_D3D_S_VALUE 0 +#define NV4_PGRAPH_D3D_M 0x4005e0 +#define NV4_PGRAPH_D3D_M_VALUE 6 +#define NV4_PGRAPH_FORMAT0 0x4005A8 +#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA 1 +#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA_A 0x0 +#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA_B 0x1 +#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE 2 +#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE_FALSE 0x0 +#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE_TRUE 0x1 +#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH 5 +#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH 7 +#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT0_COLOR 8 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_Y8 0x0 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_AY8 0x1 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_A1R5G5B5 0x2 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_X1R5G5B5 0x3 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_A4R4G4B4 0x4 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_R5G6B5 0x5 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_A8R8G8B8 0x6 +#define NV4_PGRAPH_FORMAT0_COLOR_LE_X8R8G8B8 0x7 +// 0x1-0Xf used for 1-16 mipmap levels +#define NV4_PGRAPH_FORMAT0_MIPMAP_LEVELS 12 +#define NV4_PGRAPH_FORMAT0_MIPMAP_LEVELS_INVALID 0x0 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U 16 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_1 0x0 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_2 0x1 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_4 0x2 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_8 0x3 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_16 0x4 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_32 0x5 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_64 0x6 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_128 0x7 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_256 0x8 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_512 0x9 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_1024 0xA +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_2048 0xB +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V 20 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_1 0x0 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_2 0x1 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_4 0x2 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_8 0x3 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_16 0x4 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_32 0x5 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_64 0x6 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_128 0x7 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_256 0x8 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_512 0x9 +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_1024 0xA +#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_2048 0xB +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU 24 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_WRAP 0x1 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_BORDER 0x4 +#define NV4_PGRAPH_FORMAT0_WRAPU 27 +#define NV4_PGRAPH_FORMAT0_WRAPU_FALSE 0x0 +#define NV4_PGRAPH_FORMAT0_WRAPU_TRUE 0x1 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV 28 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_WRAP 0x1 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_BORDER 0x4 +#define NV4_PGRAPH_FORMAT0_WRAPV 31 +#define NV4_PGRAPH_FORMAT0_WRAPV_FALSE 0x0 +#define NV4_PGRAPH_FORMAT0_WRAPV_TRUE 0x1 +#define NV4_PGRAPH_FORMAT1 0x4005AC +#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA 1 +#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA_A 0x0 +#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA_B 0x1 +#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE 2 +#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE_FALSE 0x0 +#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE_TRUE 0x1 +#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH 5 +#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH 7 +#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH_CENTER 0x0 +#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH_CORNER 0x1 +#define NV4_PGRAPH_FORMAT1_COLOR 8 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_Y8 0x0 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_AY8 0x1 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_A1R5G5B5 0x2 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_X1R5G5B5 0x3 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_A4R4G4B4 0x4 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_R5G6B5 0x5 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_A8R8G8B8 0x6 +#define NV4_PGRAPH_FORMAT1_COLOR_LE_X8R8G8B8 0x7 +// 15:12 = number of mipmap levels (1-15. 0 = invalid). Stupid defines removed here +#define NV4_PGRAPH_FORMAT1_MIPMAP_LEVELS 12 +#define NV4_PGRAPH_FORMAT1_MIPMAP_LEVELS_INVALID 0x0 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U 16 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_1 0x0 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_2 0x1 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_4 0x2 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_8 0x3 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_16 0x4 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_32 0x5 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_64 0x6 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_128 0x7 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_256 0x8 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_512 0x9 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_1024 0xA +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_2048 0xB +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V 20 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_1 0x0 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_2 0x1 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_4 0x2 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_8 0x3 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_16 0x4 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_32 0x5 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_64 0x6 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_128 0x7 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_256 0x8 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_512 0x9 +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_1024 0xA +#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_2048 0xB +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU 24 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_WRAP 0x1 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_BORDER 0x4 +#define NV4_PGRAPH_FORMAT1_WRAPU 27 +#define NV4_PGRAPH_FORMAT1_WRAPU_TRUE 0x1 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV 28 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_WRAP 0x1 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_MIRROR 0x2 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_CLAMP 0x3 +#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_BORDER 0x4 +#define NV4_PGRAPH_FORMAT1_WRAPV 31 +#define NV4_PGRAPH_FORMAT1_WRAPV_TRUE 0x1 +#define NV4_PGRAPH_FILTER0 0x4005B0 +#define NV4_PGRAPH_FILTER0_KERNEL_SIZE_X 1 +#define NV4_PGRAPH_FILTER0_KERNEL_SIZE_Y 9 +#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE 15 +#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE_FALSE 0x0 +#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER0_MIPMAPLODBIAS 16 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN 24 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_NEAREST 0x1 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEAR 0x2 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MIN_ENABLE 27 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MIN_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG 28 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_NEAREST 0x1 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEAR 0x2 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MAG_ENABLE 31 +#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MAG_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER1 0x4005B4 +#define NV4_PGRAPH_FILTER1_KERNEL_SIZE_X 1 +#define NV4_PGRAPH_FILTER1_KERNEL_SIZE_Y 9 +#define NV4_PGRAPH_FILTER1_MIPMAP_DITHER_ENABLE 15 +#define NV4_PGRAPH_FILTER1_MIPMAP_DITHER_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER1_MIPMAPLODBIAS 16 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN 24 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_NEAREST 0x1 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEAR 0x2 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MIN_ENABLE 27 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MIN_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG 28 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_NEAREST 0x1 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEAR 0x2 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_MIPNEAREST 0x3 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_MIPLINEAR 0x4 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEARMIPNEAREST 0x5 +#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEARMIPLINEAR 0x6 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MAG_ENABLE 31 +#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MAG_ENABLE_TRUE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA 0x400590 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION 29 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_COMBINE0COLOR 0x400594 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0 1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1 9 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2 17 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3 25 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3_COLOR 0x0 +#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURELOD 0x7 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION 29 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_COMBINE1ALPHA 0x400598 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION 29 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_COMBINE1COLOR 0x40059C +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0 0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0 1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1 8 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1 9 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1 10 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2 16 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2 17 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2 18 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3 24 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3_NORMAL 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3_INVERSE 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3 25 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3_COLOR 0x0 +#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3_ALPHA 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3 26 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_ZERO 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_FACTOR 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_DIFFUSE 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_INPUT 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_TEXTURE0 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_TEXTURE1 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION 29 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD 0x1 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD2 0x2 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD4 0x3 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDSIGNED 0x4 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_MUX 0x5 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDCOMPLEMENT 0x6 +#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDSIGNED2 0x7 +#define NV4_PGRAPH_DMA_START_0 0x401000 +#define NV4_PGRAPH_DMA_START_0_VALUE 0 +#define NV4_PGRAPH_DMA_START_1 0x401004 +#define NV4_PGRAPH_DMA_START_1_VALUE 0 +#define NV4_PGRAPH_DMA_LENGTH 0x401008 +#define NV4_PGRAPH_DMA_LENGTH_VALUE 0 +#define NV4_PGRAPH_DMA_MISC 0x40100C +#define NV4_PGRAPH_DMA_MISC_COUNT 0 +#define NV4_PGRAPH_DMA_MISC_FMT_SRC 16 +#define NV4_PGRAPH_DMA_MISC_FMT_DST 20 +#define NV4_PGRAPH_DMA_DATA_0 0x401020 +#define NV4_PGRAPH_DMA_DATA_0_VALUE 0 +#define NV4_PGRAPH_DMA_DATA_1 0x401024 +#define NV4_PGRAPH_DMA_DATA_1_VALUE 0 +#define NV4_PGRAPH_DMA_RM 0x401030 +#define NV4_PGRAPH_DMA_RM_ASSIST_A 0 +#define NV4_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x0 +#define NV4_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x1 +#define NV4_PGRAPH_DMA_RM_ASSIST_A_RESET 0x1 +#define NV4_PGRAPH_DMA_RM_ASSIST_B 1 +#define NV4_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x0 +#define NV4_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x1 +#define NV4_PGRAPH_DMA_RM_ASSIST_B_RESET 0x1 +#define NV4_PGRAPH_DMA_RM_WRITE_REQ 4 +#define NV4_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x0 +#define NV4_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x1 +#define NV4_PGRAPH_DMA_A_XLATE_INST 0x401040 +#define NV4_PGRAPH_DMA_A_XLATE_INST_VALUE 0 +#define NV4_PGRAPH_DMA_A_CONTROL 0x401044 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x1 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x1 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE 16 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x0 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x2 +#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x3 +#define NV4_PGRAPH_DMA_A_CONTROL_ADJUST 20 +#define NV4_PGRAPH_DMA_A_LIMIT 0x401048 +#define NV4_PGRAPH_DMA_A_LIMIT_OFFSET 0 +#define NV4_PGRAPH_DMA_A_TLB_PTE 0x40104C +#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS 1 +#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x0 +#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x1 +#define NV4_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 12 +#define NV4_PGRAPH_DMA_A_TLB_TAG 0x401050 +#define NV4_PGRAPH_DMA_A_TLB_TAG_ADDRESS 12 +#define NV4_PGRAPH_DMA_A_ADJ_OFFSET 0x401054 +#define NV4_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_A_OFFSET 0x401058 +#define NV4_PGRAPH_DMA_A_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_A_SIZE 0x40105C +#define NV4_PGRAPH_DMA_A_SIZE_VALUE 0 +#define NV4_PGRAPH_DMA_A_Y_SIZE 0x401060 +#define NV4_PGRAPH_DMA_A_Y_SIZE_VALUE 0 +#define NV4_PGRAPH_DMA_B_XLATE_INST 0x401080 +#define NV4_PGRAPH_DMA_B_XLATE_INST_VALUE 0 +#define NV4_PGRAPH_DMA_B_CONTROL 0x401084 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x1 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x1 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE 16 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x0 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x2 +#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x3 +#define NV4_PGRAPH_DMA_B_CONTROL_ADJUST 20 +#define NV4_PGRAPH_DMA_B_LIMIT 0x401088 +#define NV4_PGRAPH_DMA_B_LIMIT_OFFSET 0 +#define NV4_PGRAPH_DMA_B_TLB_PTE 0x40108C +#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS 1 +#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x0 +#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x1 +#define NV4_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 12 +#define NV4_PGRAPH_DMA_B_TLB_TAG 0x401090 +#define NV4_PGRAPH_DMA_B_TLB_TAG_ADDRESS 12 +#define NV4_PGRAPH_DMA_B_ADJ_OFFSET 0x401094 +#define NV4_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_B_OFFSET 0x401098 +#define NV4_PGRAPH_DMA_B_OFFSET_VALUE 0 +#define NV4_PGRAPH_DMA_B_SIZE 0x40109C +#define NV4_PGRAPH_DMA_B_SIZE_VALUE 0 +#define NV4_PGRAPH_DMA_B_Y_SIZE 0x4010A0 +#define NV4_PGRAPH_DMA_B_Y_SIZE_VALUE 0 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR 0 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_ZOH_MS 0x0 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_ZOH 0x1 +#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_FOH 0x2 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U 4 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_CYLINDRICAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_WRAP 0x1 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_MIRROR 0x2 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_CLAMP 0x3 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V 6 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_CYLINDRICAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_WRAP 0x1 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_MIRROR 0x2 +#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_CLAMP 0x3 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT 8 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT_LE_X8R8G8B8 0x0 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT_LE_A8R8G8B8 0x1 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR 10 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_NORMAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_COLOR_INVERSE 0x1 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_ALPHA_INVERSE 0x2 +#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_ALPHA_ONE 0x3 +#define NV4_PGRAPH_CONTROL_OUT_CULLING 12 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_ILLEGAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_NONE 0x1 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_COUNTERCLOCKWISE 0x2 +#define NV4_PGRAPH_CONTROL_OUT_CULLING_CLOCKWISE 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER 15 +#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER_SCREEN 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER_LINEAR 0x1 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE 16 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_ILLEGAL 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_FALSE 0x1 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_LT 0x2 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_EQ 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_LE 0x4 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_GT 0x5 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_NE 0x6 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_GE 0x7 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_TRUE 0x8 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE 20 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_NEVER 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALPHA 0x1 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALPHA_ZETA 0x2 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ZETA 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALWAYS 0x4 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE 24 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_NEVER 0x0 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ALPHA 0x1 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ALPHA_ZETA 0x2 +#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ZETA 0x3 +#define NV4_PGRAPH_CONTROL_OUT_ROP 28 +#define NV4_PGRAPH_CONTROL_OUT_ROP_BLEND_AND 0x0 +#define NV4_PGRAPH_CONTROL_OUT_ROP_ADD_WITH_SATURATION 0x1 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA 29 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA_SRCALPHA 0x0 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA_DESTCOLOR 0x1 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0 30 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0_DESTCOLOR 0x0 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0_ZERO 0x1 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1 31 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1_SRCCOLOR 0x0 +#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1_ZERO 0x1 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_KEY 0 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE 8 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_ILLEGAL 0x0 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_FALSE 0x1 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_LT 0x2 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_EQ 0x3 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_LE 0x4 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_GT 0x5 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_NE 0x6 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_GE 0x7 +#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_TRUE 0x8 + +#define NV4_PVIDEO_START 0x680000 +#define NV4_PVIDEO_END 0x6802FF + +#define NV4_PVIDEO_INTR_0 0x680100 +#define NV4_PVIDEO_INTR_0_NOTIFY 0 +#define NV4_PVIDEO_INTR_0_NOTIFY_NOT_PENDING 0x0 +#define NV4_PVIDEO_INTR_0_NOTIFY_PENDING 0x1 +#define NV4_PVIDEO_INTR_0_NOTIFY_RESET 0x1 +#define NV4_PVIDEO_INTR_EN_0 0x680140 +#define NV4_PVIDEO_INTR_EN_0_NOTIFY 0 +#define NV4_PVIDEO_INTR_EN_0_NOTIFY_ENABLED 0x1 +#define NV4_PVIDEO_STEP_SIZE 0x680200 +#define NV4_PVIDEO_STEP_SIZE_X 0 +#define NV4_PVIDEO_STEP_SIZE_Y 16 +#define NV4_PVIDEO_CONTROL_Y 0x680204 +#define NV4_PVIDEO_CONTROL_Y_BLUR 0 +#define NV4_PVIDEO_CONTROL_Y_BLUR_OFF 0x0 +#define NV4_PVIDEO_CONTROL_Y_BLUR_ON 0x1 +#define NV4_PVIDEO_CONTROL_Y_LINE 4 +#define NV4_PVIDEO_CONTROL_Y_LINE_HALF 0x0 +#define NV4_PVIDEO_CONTROL_Y_LINE_FULL 0x1 +#define NV4_PVIDEO_CONTROL_X 0x680208 +#define NV4_PVIDEO_CONTROL_X_WEIGHT 0 +#define NV4_PVIDEO_CONTROL_X_WEIGHT_LIGHT 0x0 +#define NV4_PVIDEO_CONTROL_X_WEIGHT_HEAVY 0x1 +#define NV4_PVIDEO_CONTROL_X_SHARPENING 4 +#define NV4_PVIDEO_CONTROL_X_SHARPENING_OFF 0x0 +#define NV4_PVIDEO_CONTROL_X_SHARPENING_ON 0x1 +#define NV4_PVIDEO_CONTROL_X_SMOOTHING 8 +#define NV4_PVIDEO_CONTROL_X_SMOOTHING_OFF 0x0 +#define NV4_PVIDEO_CONTROL_X_SMOOTHING_ON 0x1 +#define NV4_PVIDEO_BUFF0_START 0x68020c +#define NV4_PVIDEO_BUFF0_START_ADDRESS 2 +#define NV4_PVIDEO_BUFF1_START 0x680210 +#define NV4_PVIDEO_BUFF1_START_ADDRESS 2 +#define NV4_PVIDEO_BUFF0_PITCH 0x680214 +#define NV4_PVIDEO_BUFF0_PITCH_LENGTH 4 +#define NV4_PVIDEO_BUFF1_PITCH 0x680218 +#define NV4_PVIDEO_BUFF1_PITCH_LENGTH 4 +#define NV4_PVIDEO_BUFF0_OFFSET 0x68021c +#define NV4_PVIDEO_BUFF0_OFFSET_X 0 +#define NV4_PVIDEO_BUFF0_OFFSET_Y 4 +#define NV4_PVIDEO_BUFF0_OFFSET_Y_OFF 0x0 +#define NV4_PVIDEO_BUFF0_OFFSET_Y_QUARTER 0x1 +#define NV4_PVIDEO_BUFF0_OFFSET_Y_HALF 0x2 +#define NV4_PVIDEO_BUFF1_OFFSET 0x680220 +#define NV4_PVIDEO_BUFF1_OFFSET_X 0 +#define NV4_PVIDEO_BUFF1_OFFSET_Y 4 +#define NV4_PVIDEO_BUFF1_OFFSET_Y_OFF 0x0 +#define NV4_PVIDEO_BUFF1_OFFSET_Y_QUARTER 0x1 +#define NV4_PVIDEO_BUFF1_OFFSET_Y_HALF 0x2 +#define NV4_PVIDEO_OE_STATE 0x680224 +#define NV4_PVIDEO_OE_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PVIDEO_OE_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PVIDEO_OE_STATE_BUFF0_ERROR 8 +#define NV4_PVIDEO_OE_STATE_BUFF1_ERROR 12 +#define NV4_PVIDEO_OE_STATE_BUFF0_IN_USE 16 +#define NV4_PVIDEO_OE_STATE_BUFF1_IN_USE 20 +#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER 24 +#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PVIDEO_SU_STATE 0x680228 +#define NV4_PVIDEO_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PVIDEO_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PVIDEO_RM_STATE 0x68022c +#define NV4_PVIDEO_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PVIDEO_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PVIDEO_WINDOW_START 0x680230 +#define NV4_PVIDEO_WINDOW_START_X 0 +#define NV4_PVIDEO_WINDOW_START_Y 16 +#define NV4_PVIDEO_WINDOW_SIZE 0x680234 +#define NV4_PVIDEO_WINDOW_SIZE_X 0 +#define NV4_PVIDEO_WINDOW_SIZE_Y 16 +#define NV4_PVIDEO_FIFO_THRES 0x680238 +#define NV4_PVIDEO_FIFO_THRES_SIZE 3 +#define NV4_PVIDEO_FIFO_BURST 0x68023c +#define NV4_PVIDEO_FIFO_BURST_LENGTH 0 +#define NV4_PVIDEO_FIFO_BURST_LENGTH_32 0x1 +#define NV4_PVIDEO_FIFO_BURST_LENGTH_64 0x2 +#define NV4_PVIDEO_FIFO_BURST_LENGTH_128 0x3 +#define NV4_PVIDEO_KEY 0x680240 +#define NV4_PVIDEO_KEY_INDEX 0 +#define NV4_PVIDEO_KEY_565 0 +#define NV4_PVIDEO_KEY_555 0 +#define NV4_PVIDEO_KEY_888 0 +#define NV4_PVIDEO_KEY_PACK 24 +#define NV4_PVIDEO_OVERLAY 0x680244 +#define NV4_PVIDEO_OVERLAY_VIDEO 0 +#define NV4_PVIDEO_OVERLAY_VIDEO_OFF 0x0 +#define NV4_PVIDEO_OVERLAY_VIDEO_ON 0x1 +#define NV4_PVIDEO_OVERLAY_KEY 4 +#define NV4_PVIDEO_OVERLAY_KEY_OFF 0x0 +#define NV4_PVIDEO_OVERLAY_KEY_ON 0x1 +#define NV4_PVIDEO_OVERLAY_FORMAT 8 +#define NV4_PVIDEO_OVERLAY_FORMAT_CCIR 0x0 +#define NV4_PVIDEO_OVERLAY_FORMAT_YUY2 0x1 +#define NV4_PVIDEO_RED_CSC 0x680280 +#define NV4_PVIDEO_RED_CSC_OFFSET 0 +#define NV4_PVIDEO_GREEN_CSC 0x680284 +#define NV4_PVIDEO_GREEN_CSC_OFFSET 0 +#define NV4_PVIDEO_BLUE_CSC 0x680288 +#define NV4_PVIDEO_BLUE_CSC_OFFSET 0 +#define NV4_PVIDEO_CSC_ADJUST 0x68028c +#define NV4_PVIDEO_CSC_ADJUST_B_FLAG 0 +#define NV4_PVIDEO_CSC_ADJUST_B_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_B_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_G_FLAG 4 +#define NV4_PVIDEO_CSC_ADJUST_G_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_G_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_R_FLAG 8 +#define NV4_PVIDEO_CSC_ADJUST_R_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_R_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_L_FLAG 12 +#define NV4_PVIDEO_CSC_ADJUST_L_FLAG_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_L_FLAG_ON 0x1 +#define NV4_PVIDEO_CSC_ADJUST_CHROMA 16 +#define NV4_PVIDEO_CSC_ADJUST_CHROMA_OFF 0x0 +#define NV4_PVIDEO_CSC_ADJUST_CHROMA_ON 0x1 + +#define NV4_PRMCIO_START 0x601000 +#define NV4_PRMCIO_END 0x601FFF + +#define NV4_PRMCIO_INP0 0x6013c2 +#define NV4_PRMCIO_INP0_MONO 0x6013ba +#define NV4_PRMCIO_INP0_COLOR 0x6013da +#define NV4_PRMCIO_INP0_READ_MONO 0x6013ca +#define NV4_PRMCIO_INP0_WRITE_MONO 0x6013ba +#define NV4_PRMCIO_INP0_WRITE_COLOR 0x6013da +// DEFAULT = Palette +#define NV4_PRMCIO_ARX 0x6013c0 +#define NV4_PRMCIO_AR_WRITE 0x6013c0 // After ARX +#define NV4_PRMCIO_AR_READ 0x6013c1 +#define NV4_PRMCIO_AR_PALETTE_WRITE 0x6013c0 +#define NV4_PRMCIO_AR_PALETTE_READ 0x6013c1 +#define NV4_PRMCIO_AR_MODE_INDEX 0x10 +#define NV4_PRMCIO_AR_OSCAN_INDEX 0x11 +#define NV4_PRMCIO_AR_PLANE_INDEX 0x12 +#define NV4_PRMCIO_AR_HPP_INDEX 0x13 +#define NV4_PRMCIO_AR_CSEL_INDEX 0x14 +#define NV4_PRMCIO_CRX_MONO 0x6013b4 +#define NV4_PRMCIO_CRX_COLOR 0x6013d4 +#define NV4_PRMCIO_CR_MONO 0x6013b5 +#define NV4_PRMCIO_CR_COLOR 0x6013d5 +#define NV4_PRMCIO_CRE_MONO 0x6013b5 +#define NV4_PRMCIO_CRE_COLOR 0x6013d5 + +#define NV4_PCRTC_INTR_0 0x600100 +#define NV4_PCRTC_INTR_0_VBLANK 0 +#define NV4_PCRTC_INTR_0_VBLANK_NOT_PENDING 0x0 +#define NV4_PCRTC_INTR_0_VBLANK_PENDING 0x1 +#define NV4_PCRTC_INTR_0_VBLANK_RESET 0x1 +#define NV4_PCRTC_INTR_EN_0 0x600140 +#define NV4_PCRTC_INTR_EN_0_VBLANK 0 +#define NV4_PCRTC_INTR_EN_0_VBLANK_ENABLED 0x1 +#define NV4_PCRTC_START 0x600800 +#define NV4_PCRTC_START_ADDRESS 2 +#define NV4_PCRTC_CONFIG 0x600804 +#define NV4_PCRTC_CONFIG_START_ADDRESS 0 +#define NV4_PCRTC_CONFIG_START_ADDRESS_VGA 0x0 +#define NV4_PCRTC_CONFIG_START_ADDRESS_NON_VGA 0x1 +#define NV4_PCRTC_CONFIG_START_ADDRESS_HSYNC 0x2 +#define NV4_PCRTC_RASTER 0x600808 +#define NV4_PCRTC_RASTER_POSITION 0 +#define NV4_PCRTC_RASTER_SA_LOAD 12 +#define NV4_PCRTC_RASTER_SA_LOAD_DISPLAY 0x0 +#define NV4_PCRTC_RASTER_SA_LOAD_BEFORE 0x1 +#define NV4_PCRTC_RASTER_SA_LOAD_AFTER 0x2 +#define NV4_PCRTC_RASTER_VERT_BLANK 16 +#define NV4_PCRTC_RASTER_VERT_BLANK_ACTIVE 0x1 +#define NV4_PCRTC_RASTER_VERT_BLANK_INACTIVE 0x0 + +#define NV4_CIO_START 0x3B0 +#define NV4_CIO_END 0x3DF + + +#define NV4_CIO_INP0 0x3c2 +#define NV4_CIO_INP0_MONO 0x3ba +#define NV4_CIO_INP0_COLOR 0x3da +#define NV4_CIO_INP0_READ_MONO 0x3ca +#define NV4_CIO_INP0_WRITE_MONO 0x3ba +#define NV4_CIO_INP0_WRITE_COLOR 0x3da +#define NV4_CIO_ARX 0x3c0 // if index is not 0x10-0x13 write palette +#define NV4_CIO_AR_PALETTE_WRITE 0x3c0 +#define NV4_CIO_AR_PALETTE_READ 0x3c1 +#define NV4_CIO_AR_MODE_WRITE 0x3c0 +#define NV4_CIO_AR_MODE_READ 0x3c1 +#define NV4_CIO_AR_MODE_INDEX 0x10 +#define NV4_CIO_AR_OSCAN_WRITE 0x3c0 +#define NV4_CIO_AR_OSCAN_READ 0x3c1 +#define NV4_CIO_AR_OSCAN_INDEX 0x11 +#define NV4_CIO_AR_PLANE_WRITE 0x3c0 +#define NV4_CIO_AR_PLANE_READ 0x3c1 +#define NV4_CIO_AR_PLANE_INDEX 0x12 +#define NV4_CIO_AR_HPP_WRITE 0x3c0 +#define NV4_CIO_AR_HPP_READ 0x3c1 +#define NV4_CIO_AR_HPP_INDEX 0x13 +#define NV4_CIO_AR_CSEL_WRITE 0x3c0 +#define NV4_CIO_AR_CSEL_READ 0x3c1 +#define NV4_CIO_AR_CSEL_INDEX 0x14 +#define NV4_CIO_CRX_MONO 0x3b4 +#define NV4_CIO_CRX_COLOR 0x3d4 +#define NV4_CIO_CR_MONO 0x3b5 +#define NV4_CIO_CR_COLOR 0x3d5 +#define NV4_CIO_CR_HDT_INDEX 0x0 +#define NV4_CIO_CR_HDE_INDEX 0x1 +#define NV4_CIO_CR_HBS_INDEX 0x2 +#define NV4_CIO_CR_HBE_INDEX 0x3 +#define NV4_CIO_CR_HBE_4_0 0 +#define NV4_CIO_CR_HRS_INDEX 0x4 +#define NV4_CIO_CR_HRE_INDEX 0x5 +#define NV4_CIO_CR_HRE_HBE_5 7 +#define NV4_CIO_CR_HRE_4_0 0 +#define NV4_CIO_CR_VDT_INDEX 0x6 +#define NV4_CIO_CR_OVL_INDEX 0x7 +#define NV4_CIO_CR_OVL_VDE_8 1 +#define NV4_CIO_CR_OVL_VDE_9 6 +#define NV4_CIO_CR_OVL_VDT_8 0 +#define NV4_CIO_CR_OVL_VDT_9 5 +#define NV4_CIO_CR_OVL_VBS_8 3 +#define NV4_CIO_CR_OVL_VRS_8 2 +#define NV4_CIO_CR_OVL_VRS_9 7 +#define NV4_CIO_CR_RSAL_INDEX 0x8 +#define NV4_CIO_CR_RSAL_PANNING 5 +#define NV4_CIO_CR_CELL_HT_INDEX 0x9 +#define NV4_CIO_CR_CELL_HT_SCANDBL 7 +#define NV4_CIO_CR_CELL_HT_VBS_9 5 +#define NV4_CIO_CR_CURS_ST_INDEX 0xA +#define NV4_CIO_CR_CURS_END_INDEX 0xB +#define NV4_CIO_CR_SA_HI_INDEX 0xC +#define NV4_CIO_CR_SA_LO_INDEX 0xD +#define NV4_CIO_CR_TCOFF_HI_INDEX 0xE +#define NV4_CIO_CR_TCOFF_LO_INDEX 0xF +#define NV4_CIO_CR_VRS_INDEX 0x10 +#define NV4_CIO_CR_VRE_INDEX 0x11 +#define NV4_CIO_CR_VRE_3_0 0 +#define NV4_CIO_CR_VDE_INDEX 0x12 +#define NV4_CIO_CR_OFFSET_INDEX 0x13 +#define NV4_CIO_CR_ULINE_INDEX 0x14 +#define NV4_CIO_CR_VBS_INDEX 0x15 +#define NV4_CIO_CR_VBE_INDEX 0x16 +#define NV4_CIO_CR_MODE_INDEX 0x17 +#define NV4_CIO_CR_LCOMP_INDEX 0x18 +#define NV4_CIO_CR_GDATA_INDEX 0x22 +#define NV4_CIO_CR_ARFF_INDEX 0x24 +#define NV4_CIO_CR_ARX_INDEX 0x26 +#define NV4_CIO_CRE_MONO 0x3b5 +#define NV4_CIO_CRE_COLOR 0x3d5 +#define NV4_CIO_CRE_RPC0_INDEX 0x19 +#define NV4_CIO_CRE_RPC0_START 0 +#define NV4_CIO_CRE_RPC0_OFFSET_10_8 5 +#define NV4_CIO_CRE_RPC1_INDEX 0x1A +#define NV4_CIO_CRE_RPC1_LARGE 2 +#define NV4_CIO_CRE_FF_INDEX 0x1B +#define NV4_CIO_CRE_FF_BURST 0 +#define NV4_CIO_CRE_FF_BURST_8 0x0 +#define NV4_CIO_CRE_FF_BURST_32 0x1 +#define NV4_CIO_CRE_FF_BURST_64 0x2 +#define NV4_CIO_CRE_FF_BURST_128 0x3 +#define NV4_CIO_CRE_FF_BURST_256 0x4 +#define NV4_CIO_CRE_ENH_INDEX 0x1C +#define NV4_CIO_CRE_PAGE0_INDEX 0x1D +#define NV4_CIO_CRE_PAGE1_INDEX 0x1E +#define NV4_CIO_SR_LOCK_INDEX 0x1F +#define NV4_CIO_SR_UNLOCK_RW_VALUE 0x57 +#define NV4_CIO_SR_UNLOCK_RO_VALUE 0x75 +#define NV4_CIO_SR_LOCK_VALUE 0x99 +#define NV4_SR_UNLOCK_RW_VALUE 0x57 +#define NV4_SR_UNLOCK_RO_VALUE 0x75 +#define NV4_SR_LOCK_VALUE 0x99 +#define NV4_CIO_CRE_FFLWM_INDEX 0x20 +#define NV4_CIO_CRE_FFLWM_LWM 0 +#define NV4_CIO_CRE_FABID_INDEX 0x25 +#define NV4_CIO_CRE_LSR_INDEX 0x25 +#define NV4_CIO_CRE_LSR_VDE_10 1 +#define NV4_CIO_CRE_LSR_VDT_10 0 +#define NV4_CIO_CRE_LSR_HBE_6 4 +#define NV4_CIO_CRE_LSR_VBS_10 3 +#define NV4_CIO_CRE_LSR_VRS_10 2 +#define NV4_CIO_CRE_CHIP_ID_INDEX 0x27 +#define NV4_CIO_CRE_PIXEL_INDEX 0x28 +#define NV4_CIO_CRE_PIXEL_TV_ADJ 3 +#define NV4_CIO_CRE_PIXEL_FORMAT 0 +#define NV4_CIO_CRE_PIXEL_FORMAT_VGA 0x0 +#define NV4_CIO_CRE_PIXEL_FORMAT_8BPP 0x1 +#define NV4_CIO_CRE_PIXEL_FORMAT_16BPP 0x2 +#define NV4_CIO_CRE_PIXEL_FORMAT_32BPP 0x3 +#define NV4_CIO_CRE_PAGE_OVFL_INDEX 0x29 +#define NV4_CIO_CRE_OSCOL_INDEX 0x2A +#define NV4_CIO_CRE_SCRATCH0_INDEX 0x2B +#define NV4_CIO_CRE_SCRATCH1_INDEX 0x2C +#define NV4_CIO_CRE_HEB_INDEX 0x2D +#define NV4_CIO_CRE_HEB_SA_23 5 +#define NV4_CIO_CRE_HEB_ILC_8 4 +#define NV4_CIO_CRE_HEB_HRS_8 3 +#define NV4_CIO_CRE_HEB_HBS_8 2 +#define NV4_CIO_CRE_HEB_HDE_8 1 +#define NV4_CIO_CRE_HEB_HDT_8 0 +#define NV4_CIO_CRE_HCUR_ADDR2_INDEX 0x2f +#define NV4_CIO_CRE_HCUR_ADDR0_INDEX 0x30 +#define NV4_CIO_CRE_HCUR_ASI 7 +#define NV4_CIO_CRE_HCUR_ASI_FRAMEBUFFER 0x1 +#define NV4_CIO_CRE_HCUR_ASI_INSTMEM 0x0 +#define NV4_CIO_CRE_HCUR_ADDR0_ADR 0 +#define NV4_CIO_CRE_HCUR_ADDR1_INDEX 0x31 +#define NV4_CIO_CRE_HCUR_ADDR1_ADR 2 +#define NV4_CIO_CRE_HCUR_ADDR1_CUR_DBL 1 +#define NV4_CIO_CRE_HCUR_ADDR1_ENABLE 0 +#define NV4_CIO_CRE_VID_END0_INDEX 0x32 +#define NV4_CIO_CRE_VID_END_7_0 0 +#define NV4_CIO_CRE_VID_END1_INDEX 0x33 +#define NV4_CIO_CRE_VID_END_ENABLE 4 +#define NV4_CIO_CRE_VID_END_10_8 0 +#define NV4_CIO_CRE_RL0_INDEX 0x34 +#define NV4_CIO_CRE_RL1_INDEX 0x35 +#define NV4_CIO_CRE_RMA_INDEX 0x38 +#define NV4_CIO_CRE_ILACE_INDEX 0x39 +#define NV4_CIO_CRE_SCRATCH2_INDEX 0x3A +#define NV4_CIO_CRE_SCRATCH3_INDEX 0x3B +#define NV4_CIO_CRE_SCRATCH4_INDEX 0x3C +#define NV4_CIO_CRE_TREG_INDEX 0x3D +#define NV4_CIO_CRE_TREG_HCNT 6 +#define NV4_CIO_CRE_TREG_VCNT 4 +#define NV4_CIO_CRE_TREG_SHADOW 0 +#define NV4_CIO_CRE_TREG_HCNT_INDEX 0x0 +#define NV4_CIO_CRE_TREG_VCNTA_INDEX 0x6 +#define NV4_CIO_CRE_TREG_VCNTB_INDEX 0x7 +#define NV4_CIO_CRE_DDC_STATUS_INDEX 0x3E +#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F +#define NV4_CIO_CRE_PCI_TO_INDEX 0x40 +#define NV4_CIO_CRE_PCI_TO_DELAY 0 + +#define NV4_VIO_MBEN 0x94 +#define NV4_VIO_ADDEN 0x46e8 +#define NV4_VIO_VSE1 0x102 +#define NV4_VIO_VSE2 0x3c3 +#define NV4_VIO_MISC_READ 0x3cc +#define NV4_VIO_MISC_WRITE 0x3c2 +#define NV4_VIO_SRX 0x3c4 +#define NV4_VIO_SR 0x3c5 +#define NV4_VIO_SR_RESET_INDEX 0x0 +#define NV4_VIO_SR_CLOCK_INDEX 0x1 +#define NV4_VIO_SR_PLANE_MASK_INDEX 0x2 +#define NV4_VIO_SR_CHAR_MAP_INDEX 0x3 +#define NV4_VIO_SR_MEM_MODE_INDEX 0x4 +#define NV4_VIO_GRX 0x3ce +#define NV4_VIO_GX_SR 0x3cf +#define NV4_VIO_GX_SR_INDEX 0x0 +#define NV4_VIO_GX_SREN_INDEX 0x1 +#define NV4_VIO_GX_CCOMP_INDEX 0x2 +#define NV4_VIO_GX_ROP_INDEX 0x3 +#define NV4_VIO_GX_READ_MAP_INDEX 0x4 +#define NV4_VIO_GX_MODE_INDEX 0x5 +#define NV4_VIO_GX_MISC_INDEX 0x6 +#define NV4_VIO_GX_DONT_CARE_INDEX 0x7 +#define NV4_VIO_GX_BIT_MASK_INDEX 0x8 + +#define NV4_PRMVIO_START 0xC0000 +#define NV4_PRMVIO_END 0xC7FFF + +#define NV4_PRMVIO_MBEN 0xC0094 +#define NV4_PRMVIO_ADDEN 0xC46e8 +#define NV4_PRMVIO_VSE1 0xC0102 +#define NV4_PRMVIO_VSE2 0xC03c3 +#define NV4_PRMVIO_MISC_READ 0xC03cc +#define NV4_PRMVIO_MISC_WRITE 0xC03c2 +#define NV4_PRMVIO_SRX 0xC03c4 +#define NV4_PRMVIO_SR_RESET 0xC03c5 +#define NV4_PRMVIO_SR_RESET_INDEX 0x0 +#define NV4_PRMVIO_SR_CLOCK_INDEX 0x1 +#define NV4_PRMVIO_SR_PLANE_MASK_INDEX 0x2 +#define NV4_PRMVIO_SR_CHAR_MAP_INDEX 0x3 +#define NV4_PRMVIO_SR_MEM_MODE_INDEX 0x4 +#define NV4_PRMVIO_GX_SR 0xC03cf +#define NV4_PRMVIO_GX_SR_INDEX 0x0 +#define NV4_PRMVIO_GX_SREN_INDEX 0x1 +#define NV4_PRMVIO_GX_CCOMP_INDEX 0x2 +#define NV4_PRMVIO_GX_ROP_INDEX 0x3 +#define NV4_PRMVIO_GX_READ_MAP_INDEX 0x4 +#define NV4_PRMVIO_GX_MODE_INDEX 0x5 +#define NV4_PRMVIO_GX_MISC_INDEX 0x6 +#define NV4_PRMVIO_GX_DONT_CARE_INDEX 0x7 +#define NV4_PRMVIO_GX_BIT_MASK_INDEX 0x8 + +#define NV4_PRMVGA 0xA0000 +#define NV4_PRMVGA_END 0xBFFFF + +#define NV4_PME 0x200FFF:0x200000 +#define NV4_PME_DEBUG_0 0x200080 +#define NV4_PME_DEBUG_0_DET_FIELD_SWITCH 0 +#define NV4_PME_DEBUG_0_DET_FIELD_SWITCH_ENABLED 0x1 +#define NV4_PME_DEBUG_0_CAPTURE_00_FF 4 +#define NV4_PME_DEBUG_0_CAPTURE_00_FF_ENABLED 0x1 +#define NV4_PME_DEBUG_1 0x200084 +#define NV4_PME_DEBUG_1_SEL 0 +#define NV4_PME_DEBUG_1_SEL_VIPCLK 0x0 +#define NV4_PME_DEBUG_1_SEL_MCLK 0x1 +#define NV4_PME_DEBUG_1_SEL_GLOB 0x2 +#define NV4_PME_DEBUG_1_VIPCLK_SEL 4 +#define NV4_PME_DEBUG_1_VIPCLK_SEL_DEFAULT 0x0 +#define NV4_PME_DEBUG_1_MCLK_SEL 8 +#define NV4_PME_DEBUG_1_MCLK_SEL_DEFAULT 0x0 +#define NV4_PME_INTR_0 0x200100 +#define NV4_PME_INTR_0_IMAGE_NOTIFY 0 +#define NV4_PME_INTR_0_IMAGE_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_IMAGE_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_IMAGE_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_VBI_NOTIFY 4 +#define NV4_PME_INTR_0_VBI_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_VBI_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_VBI_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_VID_NOTIFY 8 +#define NV4_PME_INTR_0_VID_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_VID_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_VID_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_AUD_NOTIFY 12 +#define NV4_PME_INTR_0_AUD_NOTIFY_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_AUD_NOTIFY_PENDING 0x1 +#define NV4_PME_INTR_0_AUD_NOTIFY_RESET 0x1 +#define NV4_PME_INTR_0_VMI 16 +#define NV4_PME_INTR_0_VMI_NOT_PENDING 0x0 +#define NV4_PME_INTR_0_VMI_PENDING 0x1 +#define NV4_PME_INTR_0_VMI_RESET 0x1 +#define NV4_PME_INTR_EN_0 0x200140 +#define NV4_PME_INTR_EN_0_IMAGE_NOTIFY 0 +#define NV4_PME_INTR_EN_0_IMAGE_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_VBI_NOTIFY 4 +#define NV4_PME_INTR_EN_0_VBI_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_VID_NOTIFY 8 +#define NV4_PME_INTR_EN_0_VID_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_AUD_NOTIFY 12 +#define NV4_PME_INTR_EN_0_AUD_NOTIFY_ENABLED 0x1 +#define NV4_PME_INTR_EN_0_VMI 16 +#define NV4_PME_INTR_EN_0_VMI_ENABLED 0x1 +#define NV4_PME_CONFIG_0 0x200200 +#define NV4_PME_CONFIG_0_BUS_MODE 0 +#define NV4_PME_CONFIG_0_BUS_MODE_DISABLED 0x0 +#define NV4_PME_CONFIG_0_BUS_MODE_VMI 0x1 +#define NV4_PME_CONFIG_0_BUS_MODE_CCIR656 0x2 +#define NV4_PME_CONFIG_0_IMAGE 4 +#define NV4_PME_CONFIG_0_IMAGE_ENABLED 0x1 +#define NV4_PME_CONFIG_0_VBI_MODE 8 +#define NV4_PME_CONFIG_0_VBI_MODE_DISABLED 0x0 +#define NV4_PME_CONFIG_0_VBI_MODE_1 0x1 +#define NV4_PME_CONFIG_0_VBI_MODE_2 0x2 +#define NV4_PME_CONFIG_0_VID_CD 12 +#define NV4_PME_CONFIG_0_VID_CD_ENABLED 0x1 +#define NV4_PME_CONFIG_0_AUD_CD 16 +#define NV4_PME_CONFIG_0_AUD_CD_ENABLED 0x1 +#define NV4_PME_CONFIG_1 0x200204 +#define NV4_PME_CONFIG_1_BUFFS 0 +#define NV4_PME_CONFIG_1_BUFFS_PNVM 0x0 +#define NV4_PME_CONFIG_1_BUFFS_SYS 0x1 +#define NV4_PME_CONFIG_1_HOST 4 +#define NV4_PME_CONFIG_1_HOST_PCI 0x0 +#define NV4_PME_CONFIG_1_HOST_AGP 0x1 +#define NV4_PME_NULL_DATA 0x200208 +#define NV4_PME_NULL_DATA_COMPARE 0 +#define NV4_PME_NULL_DATA_COMPARE_ENABLED 0x1 +#define NV4_PME_NULL_DATA_LINE_DETECT 4 +#define NV4_PME_NULL_DATA_LINE_DETECT_ENABLED 0x1 +#define NV4_PME_NULL_DATA_BYTE 24 +#define NV4_PME_VID_BUFF0_START_SYS 0x200300 +#define NV4_PME_VID_BUFF0_START_SYS_ADDRESS 4 +#define NV4_PME_VID_BUFF1_START_SYS 0x200304 +#define NV4_PME_VID_BUFF1_START_SYS_ADDRESS 4 +#define NV4_PME_VID_BUFF0_START_PNVM 0x200308 +#define NV4_PME_VID_BUFF0_START_PNVM_ADDRESS 4 +#define NV4_PME_VID_BUFF1_START_PNVM 0x20030c +#define NV4_PME_VID_BUFF1_START_PNVM_ADDRESS 4 +#define NV4_PME_VID_BUFF0_LENGTH 0x200310 +#define NV4_PME_VID_BUFF0_LENGTH_BITS 12 +#define NV4_PME_VID_BUFF1_LENGTH 0x200314 +#define NV4_PME_VID_BUFF1_LENGTH_BITS 12 +#define NV4_PME_VID_ME_STATE 0x200318 +#define NV4_PME_VID_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VID_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VID_ME_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_VID_ME_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_VID_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VID_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_VID_SU_STATE 0x20031c +#define NV4_PME_VID_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VID_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VID_RM_STATE 0x200320 +#define NV4_PME_VID_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VID_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VID_RM_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_VID_RM_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_VID_CURRENT 0x200324 +#define NV4_PME_VID_CURRENT_POS 2 +#define NV4_PME_AUD_BUFF0_START_SYS 0x200340 +#define NV4_PME_AUD_BUFF0_START_SYS_ADDRESS 4 +#define NV4_PME_AUD_BUFF1_START_SYS 0x200344 +#define NV4_PME_AUD_BUFF1_START_SYS_ADDRESS 4 +#define NV4_PME_AUD_BUFF0_START_PNVM 0x200348 +#define NV4_PME_AUD_BUFF0_START_PNVM_ADDRESS 4 +#define NV4_PME_AUD_BUFF1_START_PNVM 0x20034c +#define NV4_PME_AUD_BUFF1_START_PNVM_ADDRESS 4 +#define NV4_PME_AUD_BUFF0_LENGTH 0x200350 +#define NV4_PME_AUD_BUFF0_LENGTH_BITS 10 +#define NV4_PME_AUD_BUFF1_LENGTH 0x200354 +#define NV4_PME_AUD_BUFF1_LENGTH_BITS 10 +#define NV4_PME_AUD_ME_STATE 0x200358 +#define NV4_PME_AUD_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_AUD_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_AUD_ME_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_AUD_ME_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_AUD_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_AUD_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_AUD_SU_STATE 0x20035c +#define NV4_PME_AUD_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_AUD_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_AUD_RM_STATE 0x200360 +#define NV4_PME_AUD_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_AUD_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_AUD_RM_STATE_BUFF0_INTR_CHAINGAP 8 +#define NV4_PME_AUD_RM_STATE_BUFF1_INTR_CHAINGAP 12 +#define NV4_PME_AUD_CURRENT 0x200364 +#define NV4_PME_AUD_CURRENT_POS 2 +#define NV4_PME_VBI_BUFF0_START 0x200380 +#define NV4_PME_VBI_BUFF0_START_ADDRESS 4 +#define NV4_PME_VBI_BUFF1_START 0x200384 +#define NV4_PME_VBI_BUFF1_START_ADDRESS 4 +#define NV4_PME_VBI_BUFF0_PITCH 0x200388 +#define NV4_PME_VBI_BUFF0_PITCH_VALUE 4 +#define NV4_PME_VBI_BUFF1_PITCH 0x20038c +#define NV4_PME_VBI_BUFF1_PITCH_VALUE 4 +#define NV4_PME_VBI_BUFF0_LENGTH 0x200390 +#define NV4_PME_VBI_BUFF0_LENGTH_BITS 4 +#define NV4_PME_VBI_BUFF1_LENGTH 0x200394 +#define NV4_PME_VBI_BUFF1_LENGTH_BITS 4 +#define NV4_PME_VBI_ME_STATE 0x200398 +#define NV4_PME_VBI_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VBI_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VBI_ME_STATE_BUFF0_ERROR_CODE 8 +#define NV4_PME_VBI_ME_STATE_BUFF1_ERROR_CODE 12 +#define NV4_PME_VBI_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VBI_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_VBI_SU_STATE 0x20039c +#define NV4_PME_VBI_SU_STATE_BUFF0_FIELD 8 +#define NV4_PME_VBI_SU_STATE_BUFF1_FIELD 12 +#define NV4_PME_VBI_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_VBI_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_VBI_RM_STATE 0x2003a0 +#define NV4_PME_VBI_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_VBI_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_VBI 0x2003a4 +#define NV4_PME_VBI_START_LINE 0 +#define NV4_PME_VBI_NUM_LINES 16 +#define NV4_PME_IMAGE_BUFF0_START 0x200400 +#define NV4_PME_IMAGE_BUFF0_START_ADDRESS 4 +#define NV4_PME_IMAGE_BUFF1_START 0x200404 +#define NV4_PME_IMAGE_BUFF1_START_ADDRESS 4 +#define NV4_PME_IMAGE_BUFF0_PITCH 0x200408 +#define NV4_PME_IMAGE_BUFF0_PITCH_VALUE 4 +#define NV4_PME_IMAGE_BUFF1_PITCH 0x20040c +#define NV4_PME_IMAGE_BUFF1_PITCH_VALUE 4 +#define NV4_PME_IMAGE_BUFF0_LENGTH 0x200410 +#define NV4_PME_IMAGE_BUFF0_LENGTH_BITS 4 +#define NV4_PME_IMAGE_BUFF1_LENGTH 0x200414 +#define NV4_PME_IMAGE_BUFF1_LENGTH_BITS 4 +#define NV4_PME_IMAGE_ME_STATE 0x200418 +#define NV4_PME_IMAGE_ME_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_IMAGE_ME_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_IMAGE_ME_STATE_BUFF0_ERROR_CODE 8 +#define NV4_PME_IMAGE_ME_STATE_BUFF1_ERROR_CODE 12 +#define NV4_PME_IMAGE_ME_STATE_BUFF0_IN_USE 16 +#define NV4_PME_IMAGE_ME_STATE_BUFF1_IN_USE 20 +#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER 24 +#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER_0 0x0 +#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER_1 0x1 +#define NV4_PME_IMAGE_SU_STATE 0x20041c +#define NV4_PME_IMAGE_SU_STATE_BUFF0_FIELD 8 +#define NV4_PME_IMAGE_SU_STATE_BUFF1_FIELD 12 +#define NV4_PME_IMAGE_SU_STATE_BUFF0_IN_USE 16 +#define NV4_PME_IMAGE_SU_STATE_BUFF1_IN_USE 20 +#define NV4_PME_IMAGE_RM_STATE 0x200420 +#define NV4_PME_IMAGE_RM_STATE_BUFF0_INTR_NOTIFY 0 +#define NV4_PME_IMAGE_RM_STATE_BUFF1_INTR_NOTIFY 4 +#define NV4_PME_IMAGE_BUFF0_SCALE_INCR 0x200424 +#define NV4_PME_IMAGE_BUFF0_SCALE_INCR_Y 16 +#define NV4_PME_IMAGE_BUFF0_SCALE_INCR_X 0 +#define NV4_PME_IMAGE_BUFF1_SCALE_INCR 0x200428 +#define NV4_PME_IMAGE_BUFF1_SCALE_INCR_Y 16 +#define NV4_PME_IMAGE_BUFF1_SCALE_INCR_X 0 +#define NV4_PME_IMAGE_Y_CROP 0x20042c +#define NV4_PME_IMAGE_Y_CROP_STARTLINE 0 +#define NV4_PME_FIFO_LINE_START 0x200480 +#define NV4_PME_FIFO_LINE_START_ADDRESS 4 +#define NV4_PME_FIFO_CURRENT 0x200484 +#define NV4_PME_FIFO_CURRENT_ADDRESS 2 +#define NV4_PME_VMI_POLL 0x200488 +#define NV4_PME_VMI_POLL_UNCD 0 +#define NV4_PME_VMI_POLL_UNCD_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_UNCD_PENDING 0x1 +#define NV4_PME_VMI_POLL_VIDCD 1 +#define NV4_PME_VMI_POLL_VIDCD_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_VIDCD_PENDING 0x1 +#define NV4_PME_VMI_POLL_AUDCD 2 +#define NV4_PME_VMI_POLL_AUDCD_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_AUDCD_PENDING 0x1 +#define NV4_PME_VMI_POLL_INT 3 +#define NV4_PME_VMI_POLL_INT_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_INT_PENDING 0x1 +#define NV4_PME_VMI_POLL_CPURDREC 4 +#define NV4_PME_VMI_POLL_CPURDREC_NOT_PENDING 0x0 +#define NV4_PME_VMI_POLL_CPURDREC_PENDING 0x1 +#define NV4_PME_EXTERNAL(i) (0x200600+(i)*4) +#define NV4_PME_EXTERNAL_SIZE_1 256 +#define NV4_PME_EXTERNAL_DATA 0 + +#define NV4_PFB_START 0x100000 +#define NV4_PFB_END 0x100FFF + +#define NV4_PFB_BOOT_0 0x100000 +#define NV4_PFB_BOOT_0_RAM_AMOUNT 0 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_2MB 0x0 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_4MB 0x1 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_8MB 0x2 +#define NV4_PFB_BOOT_0_RAM_AMOUNT_16MB 0x3 +#define NV4_PFB_BOOT_0_RAM_WIDTH_128 2 +#define NV4_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x0 +#define NV4_PFB_BOOT_0_RAM_WIDTH_128_ON 0x1 +#define NV4_PFB_BOOT_0_RAM_TYPE 3 +#define NV4_PFB_BOOT_0_RAM_TYPE_256K 0x0 +#define NV4_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x1 +#define NV4_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x2 +#define NV4_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x3 +#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x0 +#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x1 +#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x2 +#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x3 +#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x4 +#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x5 +#define NV4_PFB_BOOT_0_UMA 8 +#define NV4_PFB_BOOT_0_UMA_DISABLE 0x0 +#define NV4_PFB_BOOT_0_UMA_ENABLE 0x1 +#define NV4_PFB_BOOT_0_UMA_SIZE 12 +#define NV4_PFB_BOOT_0_UMA_SIZE_DEFAULT 0x7 +#define NV4_PFB_BOOT_0_UMA_SIZE_2M 0x0 +#define NV4_PFB_BOOT_0_UMA_SIZE_4M 0x1 +#define NV4_PFB_BOOT_0_UMA_SIZE_6M 0x2 +#define NV4_PFB_BOOT_0_UMA_SIZE_8M 0x3 +#define NV4_PFB_BOOT_0_UMA_SIZE_10M 0x4 +#define NV4_PFB_BOOT_0_UMA_SIZE_12M 0x5 +#define NV4_PFB_BOOT_0_UMA_SIZE_14M 0x6 +#define NV4_PFB_BOOT_0_UMA_SIZE_16M 0x7 +#define NV4_PFB_BOOT_0_UMA_SIZE_18M 0x8 +#define NV4_PFB_BOOT_0_UMA_SIZE_20M 0x9 +#define NV4_PFB_BOOT_0_UMA_SIZE_22M 0xA +#define NV4_PFB_BOOT_0_UMA_SIZE_24M 0xB +#define NV4_PFB_BOOT_0_UMA_SIZE_26M 0xC +#define NV4_PFB_BOOT_0_UMA_SIZE_28M 0xD +#define NV4_PFB_BOOT_0_UMA_SIZE_30M 0xE +#define NV4_PFB_BOOT_0_UMA_SIZE_32M 0xF +#define NV4_PFB_DEBUG_0 0x100080 +#define NV4_PFB_DEBUG_0_PAGE_MODE 0 +#define NV4_PFB_DEBUG_0_PAGE_MODE_ENABLED 0x0 +#define NV4_PFB_DEBUG_0_PAGE_MODE_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_REFRESH 4 +#define NV4_PFB_DEBUG_0_REFRESH_ENABLED 0x0 +#define NV4_PFB_DEBUG_0_REFRESH_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_REFRESH_COUNTX64 8 +#define NV4_PFB_DEBUG_0_REFRESH_COUNTX64_DEFAULT 0x10 +#define NV4_PFB_DEBUG_0_REFRESH_SLOW_CLK 14 +#define NV4_PFB_DEBUG_0_REFRESH_SLOW_CLK_ENABLED 0x1 +#define NV4_PFB_DEBUG_0_CASOE 20 +#define NV4_PFB_DEBUG_0_CASOE_ENABLED 0x0 +#define NV4_PFB_DEBUG_0_CASOE_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_CKE_INVERT 28 +#define NV4_PFB_DEBUG_0_CKE_INVERT_OFF 0x0 +#define NV4_PFB_DEBUG_0_CKE_INVERT_ON 0x1 +#define NV4_PFB_DEBUG_0_REFINC 29 +#define NV4_PFB_DEBUG_0_REFINC_DISABLED 0x0 +#define NV4_PFB_DEBUG_0_REFINC_ENABLED 0x1 +#define NV4_PFB_DEBUG_0_SAVE_POWER 30 +#define NV4_PFB_DEBUG_0_SAVE_POWER_ON 0x0 +#define NV4_PFB_DEBUG_0_SAVE_POWER_OFF 0x1 +#define NV4_PFB_GREEN_0 0x1000C0 +#define NV4_PFB_GREEN_0_LEVEL 0 +#define NV4_PFB_GREEN_0_LEVEL_VIDEO_ENABLED 0x0 +#define NV4_PFB_GREEN_0_LEVEL_VIDEO_DISABLED 0x1 +#define NV4_PFB_GREEN_0_LEVEL_TIMING_DISABLED 0x2 +#define NV4_PFB_GREEN_0_LEVEL_MEMORY_DISABLED 0x3 +#define NV4_PFB_CONFIG_0 0x100200 +#define NV4_PFB_CONFIG_0_TYPE 0 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x120 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x220 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x320 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x4120 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x4220 +#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x4320 +#define NV4_PFB_CONFIG_0_TYPE_TETRIS 0x2000 +#define NV4_PFB_CONFIG_0_TYPE_NOTILING 0x1114 +#define NV4_PFB_CONFIG_0_TETRIS_MODE 15 +// 18:15 = tetris mode # +#define NV4_PFB_CONFIG_0_TETRIS_MODE_PASS 0x0 +// 18 = shift # +#define NV4_PFB_CONFIG_0_TETRIS_SHIFT 18 +#define NV4_PFB_CONFIG_0_BANK_SWAP 20 +#define NV4_PFB_CONFIG_0_BANK_SWAP_OFF 0x0 +#define NV4_PFB_CONFIG_0_BANK_SWAP_1M 0x1 +#define NV4_PFB_CONFIG_0_BANK_SWAP_2M 0x5 +#define NV4_PFB_CONFIG_0_BANK_SWAP_4M 0x7 +#define NV4_PFB_CONFIG_0_UNUSED 23 +#define NV4_PFB_CONFIG_0_SCRAMBLE_EN 29 +#define NV4_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x0 +#define NV4_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x1 +#define NV4_PFB_CONFIG_0_PRAMIN_WR 28 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_INIT 0x0 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x1 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK 24 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x0 +#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0xF +#define NV4_PFB_CONFIG_1 0x100204 +#define NV4_PFB_CONFIG_1_CAS_LATENCY 0 +#define NV4_PFB_CONFIG_1_CAS_LATENCY_3 0x3 +#define NV4_PFB_CONFIG_1_CAS_LATENCY_2 0x2 +#define NV4_PFB_CONFIG_1_CAS_LATENCY_4 0x4 +#define NV4_PFB_CONFIG_1_RAS_RAS 4 +#define NV4_PFB_CONFIG_1_RAS_RAS_DEFAULT 0x9 +#define NV4_PFB_CONFIG_1_RAS_RAS_9CYCLES 0x8 +#define NV4_PFB_CONFIG_1_RAS_RAS_8CYCLES 0x7 +#define NV4_PFB_CONFIG_1_RAS_RAS_7CYCLES 0x6 +#define NV4_PFB_CONFIG_1_RAS_PCHG 8 +#define NV4_PFB_CONFIG_1_RAS_PCHG_DEFAULT 0x2 +#define NV4_PFB_CONFIG_1_RAS_PCHG_2CYCLES 0x1 +#define NV4_PFB_CONFIG_1_RAS_LOW 12 +#define NV4_PFB_CONFIG_1_RAS_LOW_DEFAULT 0x6 +#define NV4_PFB_CONFIG_1_RAS_LOW_7CYCLES 0x7 +#define NV4_PFB_CONFIG_1_RAS_LOW_5CYCLES 0x5 +#define NV4_PFB_CONFIG_1_RAS_LOW_4CYCLES 0x4 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS 16 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS_DEFAULT 0x1 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS_2CYCLES 0x2 +#define NV4_PFB_CONFIG_1_MRS_TO_RAS_0CYCLES 0x0 +#define NV4_PFB_CONFIG_1_WRITE_TO_READ 20 +#define NV4_PFB_CONFIG_1_WRITE_TO_READ_DEFAULT 0x0 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1 24 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_DEFAULT 0x1 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_2CYCLES 0x2 +#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_0CYCLES 0x0 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE 28 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_DEFAULT 0x4 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_5CYCLES 0x5 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_3CYCLES 0x3 +#define NV4_PFB_CONFIG_1_READ_TO_WRITE_2CYCLES 0x2 +#define NV4_PFB_CONFIG_1_READ_TO_PCHG 31 +#define NV4_PFB_CONFIG_1_READ_TO_PCHG_ON 0x1 +#define NV4_PFB_CONFIG_1_READ_TO_PCHG_OFF 0x0 +#define NV4_PFB_RTL 0x100300 +#define NV4_PFB_RTL_H 0 +#define NV4_PFB_RTL_H_DEFAULT 0x0 +#define NV4_PFB_RTL_MC 1 +#define NV4_PFB_RTL_MC_DEFAULT 0x0 +#define NV4_PFB_RTL_V 2 +#define NV4_PFB_RTL_V_DEFAULT 0x0 +#define NV4_PFB_RTL_G 3 +#define NV4_PFB_RTL_G_DEFAULT 0x0 +#define NV4_PFB_RTL_GB 4 +#define NV4_PFB_RTL_GB_DEFAULT 0x0 +#define NV4_PFB_SCRAMBLE(i) (0x100400+((i)*4)) +#define NV4_PFB_SCRAMBLE_SIZE_1 8 +#define NV4_PFB_SCRAMBLE_w0 0 +#define NV4_PFB_SCRAMBLE_w1 8 +#define NV4_PFB_SCRAMBLE_w2 16 +#define NV4_PFB_SCRAMBLE_w3 24 +#define NV4_PFB_SCRAMBLE_EN 0x100420 +#define NV4_PFB_SCRAMBLE_VALUE_0 0x03020100 +#define NV4_PFB_SCRAMBLE_VALUE_1 0x07060504 +#define NV4_PFB_SCRAMBLE_VALUE_2 0x0b0a0908 +#define NV4_PFB_SCRAMBLE_VALUE_3 0x0f0e0d0c +#define NV4_PFB_SCRAMBLE_VALUE_4 0x13121110 +#define NV4_PFB_SCRAMBLE_VALUE_5 0x17161514 +#define NV4_PFB_SCRAMBLE_VALUE_6 0x1b1a1918 +#define NV4_PFB_SCRAMBLE_VALUE_7 0x1f1e1d1c +#define NV4_PFB_CONFIG_0_RESOLUTION 0 +#define NV4_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0xA +#define NV4_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0xD +#define NV4_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0xF +#define NV4_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x10 +#define NV4_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x14 +#define NV4_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x19 +#define NV4_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x1e +#define NV4_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x20 +#define NV4_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x24 +#define NV4_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x28 +#define NV4_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x32 +#define NV4_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x14 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH 8 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x1 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x2 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x3 +#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x1 +#define NV4_PFB_CONFIG_0_TILING 12 +#define NV4_PFB_CONFIG_0_TILING_ENABLED 0x0 +#define NV4_PFB_CONFIG_0_TILING_DISABLED 0x1 +#define NV4_PFB_CONFIG_0_TILING_DEBUG 13 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_DISABLED 0x0 +#define NV4_PFB_CONFIG_0_TILE 12 +#define NV4_PFB_CONFIG_0_TILE_OLD1024_FIXED 0x0 +#define NV4_PFB_CONFIG_0_TILE_OLD1024_VARIABLE 0x4 +#define NV4_PFB_CONFIG_0_TILE_TETRIS_ALLOW 0x1 +#define NV4_PFB_CONFIG_0_TILE_TETRIS_REDUNDANT 0x2 +#define NV4_PFB_CONFIG_0_TILE_TETRIS_REDUNDANT2 0x3 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON 13 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON_ENABLED 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON_DISABLED 0x1 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE 14 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE_FIXED 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE_VARIABLE 0x1 +// tetris mode # = 17:15 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_MODE 15 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_MODE_PASS 0x0 +// tetris shift # = 18 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_SHIFT 18 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP 20 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_OFF 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_ON 0x1 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB 21 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_1M 0x0 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_2M 0x2 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_4M 0x3 +#define NV4_PFB_CONFIG_0_TILING_DEBUG_UNUSED 23 +#define NV4_PFB_CONFIG_1_SGRAM100 3 +#define NV4_PFB_CONFIG_1_SGRAM100_ENABLED 0x0 +#define NV4_PFB_CONFIG_1_SGRAM100_DISABLED 0x1 +#define NV4_PFB_DEBUG_0_CKE_ALWAYSON 29 +#define NV4_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x0 +#define NV4_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x1 + +// WARNING! WARNING! WARNING! +// STB V4400 has shown PROM at 0x700000 instead of 0x300000 (errata), clashing with first 0x10000 of instance memory +// Nvidia never ran into this issue because they never used that area +// But this part may not work +#define NV4_PRAMIN_START 0x700000 +#define NV4_PRAMIN_END 0x7FFFFF + +#define NV4_PRAMIN_CONTEXT_0 ( 0*32+31):( 0*32+ 0) +#define NV4_PRAMIN_CONTEXT_1 ( 1*32+31):( 1*32+ 0) +#define NV4_PRAMIN_CONTEXT_2 ( 2*32+31):( 2*32+ 0) +#define NV4_PRAMIN_CONTEXT_3 ( 3*32+31):( 3*32+ 0) +#define NV4_PRAMIN_RAMHT_START 0x710000 +#define NV4_PRAMIN_RAMHT_END 0x710FFF +#define NV4_PRAMIN_RAMFC_START 0x711000 +#define NV4_PRAMIN_RAMFC_END 0x7111FF +#define NV4_PRAMIN_RAMRO_START 0x711200 +#define NV4_PRAMIN_RAMRO_END 0x7113FF +#define NV4_PRAMIN_CTX_0(i) (0x700000 + (i)*16) +// This is the same format as PGRAPH_CTX_SWITCH +#define NV4_PRAMIN_CTX_0_SIZE_1 0x10000 +#define NV4_PRAMIN_CTX_0_NVCLASS 0 +#define NV4_PRAMIN_CTX_0_CHROMA_KEY 12 +#define NV4_PRAMIN_CTX_0_CHROMA_KEY_ENABLE 0x1 +#define NV4_PRAMIN_CTX_0_USER_CLIP 13 +#define NV4_PRAMIN_CTX_0_USER_CLIP_ENABLE 0x1 +#define NV4_PRAMIN_CTX_0_SWIZZLE 14 +#define NV4_PRAMIN_CTX_0_SWIZZLE_ENABLE 0x1 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG 17:15 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_AND 0x0 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_ROP_AND 0x1 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_AND 0x2 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY 0x3 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_PRE 0x4 +#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_PRE 0x5 +#define NV4_PRAMIN_CTX_0_PATCH_STATUS 24 +#define NV4_PRAMIN_CTX_0_PATCH_STATUS_INVALID 0x0 +#define NV4_PRAMIN_CTX_0_PATCH_STATUS_VALID 0x1 +#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE 25 +#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE_INVALID 0x0 +#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE_VALID 0x1 +#define NV4_PRAMIN_CTX_1(i) (0x700004 + (i)*16) +#define NV4_PRAMIN_CTX_1_SIZE_1 0x10000 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT 0 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT_INVALID 0x00 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT_CGA6_M1 0x01 +#define NV4_PRAMIN_CTX_1_MONO_FORMAT_LE_M1 0x02 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT 8 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_INVALID 0x00 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y8 0x01 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A8Y8 0x02 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X24Y8 0x03 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A1R5G5B5 0x06 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X1R5G5B5 0x07 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X17R5G5B5 0x09 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_R5G6B5 0x0A +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16R5G6B5 0x0B +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16R5G6B5 0x0C +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A8R8G8B8 0x0D +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X8R8G8B8 0x0E +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y16 0x0F +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16Y16 0x10 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16Y16 0x11 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 +#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y32 0x14 +#define NV4_PRAMIN_CTX_1_NOTIFY_INSTANCE 16 +#define NV4_PRAMIN_CTX_1_NOTIFY_INSTANCE_INVALID 0x00 +#define NV4_PRAMIN_CTX_2(i) (0x700008 + (i)*16) +#define NV4_PRAMIN_CTX_2_SIZE_1 0x10000 +#define NV4_PRAMIN_CTX_2_DMA_0_INSTANCE 0 +#define NV4_PRAMIN_CTX_2_DMA_0_INSTANCE_INVALID 0x00 +#define NV4_PRAMIN_CTX_2_DMA_1_INSTANCE 16 +#define NV4_PRAMIN_CTX_2_DMA_1_INSTANCE_INVALID 0x00 + +#define NV4_FIFO_DMA_OPCODE ( 0*32+31):( 0*32+29) +#define NV4_FIFO_DMA_OPCODE_METHOD 0x0 +#define NV4_FIFO_DMA_OPCODE_JUMP 0x1 +#define NV4_FIFO_DMA_METHOD_COUNT ( 0*32+28):( 0*32+18) +#define NV4_FIFO_DMA_METHOD_SUBCHANNEL ( 0*32+15):( 0*32+13) +#define NV4_FIFO_DMA_METHOD_ADDRESS ( 0*32+12):( 0*32+ 2) +#define NV4_FIFO_DMA_DATA ( 1*32+31):( 1*32+ 0) +#define NV4_FIFO_DMA_JUMP_OFFSET 2 + +// DFB is in BAR1. Access it as VRAM + +#define NV4_PEXTDEV_BOOT_0 0x101000 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1 +#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 2 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x3 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6 +#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE 7 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x1 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x2 +#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x3 +#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11 +#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x0 +#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x1 + +#define NV4_PDAC_START 0x680000 +#define NV4_PDAC_END 0x680FFF + +#define NV4_PDAC_DATA(i) (0x680000+(i)*4) +#define NV4_PDAC_DATA_SIZE_1 16 +#define NV4_PDAC_DATA_VALUE 0 + +// WARNING! +// This has shown up at 0x700000 on real NV4 +#define NV4_PROM_START 0x300000 +#define NV4_PROM_END 0x30FFFF +#define NV4_PROM_DATA(i) (NV4_PROM_START+(i)) +#define NV4_PROM_SIZE 65536 + +#define NV4_PROM_ERRATA_START 0x700000 +#define NV4_PROM_ERRATA_END 0x70FFFF +#define NV4_PROM_ERRATA_DATA(i) (NV4_PROM_ERRATA_START+(i)) + +#define NV4_PRM 0x5FFF:0x4000 +#define NV4_PRM_INTR_0 0x4100 +#define NV4_PRM_INTR_0_TRACE_MPU401 0 +#define NV4_PRM_INTR_0_TRACE_MPU401_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_MPU401_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_MPU401_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_FM 4 +#define NV4_PRM_INTR_0_TRACE_FM_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_FM_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_FM_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL 8 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER 12 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_SB_MIXER_RESET 0x1 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW 16 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW_NOT_PENDING 0x0 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW_PENDING 0x1 +#define NV4_PRM_INTR_0_TRACE_OVERFLOW_RESET 0x1 +#define NV4_PRM_INTR_EN_0 0x4140 +#define NV4_PRM_INTR_EN_0_TRACE_MPU401 0 +#define NV4_PRM_INTR_EN_0_TRACE_MPU401_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_FM 4 +#define NV4_PRM_INTR_EN_0_TRACE_FM_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_SB_DIGITAL 8 +#define NV4_PRM_INTR_EN_0_TRACE_SB_DIGITAL_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_SB_MIXER 12 +#define NV4_PRM_INTR_EN_0_TRACE_SB_MIXER_ENABLED 0x1 +#define NV4_PRM_INTR_EN_0_TRACE_OVERFLOW 16 +#define NV4_PRM_INTR_EN_0_TRACE_OVERFLOW_ENABLED 0x1 +#define NV4_PRM_RAMRM 0x4200 +#define NV4_PRM_RAMRM_BASE_ADDRESS 12 +#define NV4_PRM_RAMRM_BASE_ADDRESS_2000 0x2000 +#define NV4_PRM_TRACE 0x4300 +#define NV4_PRM_TRACE_IO_CAPTURE 0 +#define NV4_PRM_TRACE_IO_CAPTURE_DISABLED 0x0 +#define NV4_PRM_TRACE_IO_CAPTURE_WRITES 0x1 +#define NV4_PRM_TRACE_IO_CAPTURE_READS 0x2 +#define NV4_PRM_TRACE_IO_CAPTURE_READS_WRITES 0x3 +#define NV4_PRM_TRACE_IO_WRITE 4 +#define NV4_PRM_TRACE_IO_WRITE_NONE 0x0 +#define NV4_PRM_TRACE_IO_WRITE_OCCURED 0x1 +#define NV4_PRM_TRACE_IO_WRITE_RESET 0x1 +#define NV4_PRM_TRACE_IO_READ 5 +#define NV4_PRM_TRACE_IO_READ_NONE 0x0 +#define NV4_PRM_TRACE_IO_READ_OCCURED 0x1 +#define NV4_PRM_TRACE_IO_READ_RESET 0x1 +#define NV4_PRM_TRACE_INDEX 0x4310 +#define NV4_PRM_TRACE_INDEX_ADDRESS 0 +#define NV4_PRM_TRACE_INDEX_ADDRESS_0 0x0 +#define NV4_PRM_IGNORE_0 0x4320 +#define NV4_PRM_IGNORE_0_MPU401 0 +#define NV4_PRM_IGNORE_0_MPU401_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_MPU401_WRITES 0x1 +#define NV4_PRM_IGNORE_0_MPU401_READS 0x2 +#define NV4_PRM_IGNORE_0_MPU401_READS_WRITES 0x3 +#define NV4_PRM_IGNORE_0_FM 4 +#define NV4_PRM_IGNORE_0_FM_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_FM_WRITES 0x1 +#define NV4_PRM_IGNORE_0_FM_READS 0x2 +#define NV4_PRM_IGNORE_0_FM_READS_WRITES 0x3 +#define NV4_PRM_IGNORE_0_SB_DIGITAL 8 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_WRITES 0x1 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_READS 0x2 +#define NV4_PRM_IGNORE_0_SB_DIGITAL_READS_WRITES 0x3 +#define NV4_PRM_IGNORE_0_SB_MIXER 12 +#define NV4_PRM_IGNORE_0_SB_MIXER_DISABLED 0x0 +#define NV4_PRM_IGNORE_0_SB_MIXER_WRITES 0x1 +#define NV4_PRM_IGNORE_0_SB_MIXER_READS 0x2 +#define NV4_PRM_IGNORE_0_SB_MIXER_READS_WRITES 0x3 + +// +// PIO submission +// + +#define NV4_USER_START 0x800000 +#define NV4_USER_END 0xFFFFFF + +#define NV4_USER_OBJECT(i,j) (0x800000+(i)*0x10000+(j)*0x2000) +#define NV4_USER_OBJECT_SIZE_1 16 +#define NV4_USER_OBJECT_SIZE_2 8 +#define NV4_USER_OBJECT_HANDLE 0 +#define NV4_USER_FREE016(i,j) (0x800010+(i)*65536+(j)*8192) +#define NV4_USER_FREE016_SIZE_1 16 +#define NV4_USER_FREE016_SIZE_2 8 +#define NV4_USER_FREE016_COUNT_LO 0 +#define NV4_USER_FREE016_COUNT_LO_0 0x0 +#define NV4_USER_FREE016_COUNT 2 +#define NV4_USER_FREE016_COUNT_HI 10 +#define NV4_USER_FREE016_COUNT_HI_0 0x0 +#define NV4_USER_FREE032(i,j) (0x800010+(i)*65536+(j)*8192) +#define NV4_USER_FREE032_SIZE_1 16 +#define NV4_USER_FREE032_SIZE_2 8 +#define NV4_USER_FREE032_COUNT_LO 0 +#define NV4_USER_FREE032_COUNT_LO_0 0x0 +#define NV4_USER_FREE032_COUNT 2 +#define NV4_USER_FREE032_COUNT_HI 10 +#define NV4_USER_FREE032_COUNT_HI_0 0x0 +#define NV4_USER_ZERO016(i,j,k) (0x0800012+(i)*65536+(j)*8192+(k)*2) +#define NV4_USER_ZERO016_SIZE_1 16 +#define NV4_USER_ZERO016_SIZE_2 8 +#define NV4_USER_ZERO016_SIZE_3 7 +#define NV4_USER_ZERO016_COUNT 0 +#define NV4_USER_ZERO016_COUNT_0 0x0 +#define NV4_USER_ZERO032(i,j,k) (0x0800014+(i)*65536+(j)*8192+(k)*4) +#define NV4_USER_ZERO032_SIZE_1 16 +#define NV4_USER_ZERO032_SIZE_2 8 +#define NV4_USER_ZERO032_SIZE_3 3 +#define NV4_USER_ZERO032_COUNT 0 +#define NV4_USER_ZERO032_COUNT_0 0x0 +#define NV4_USER_DMA_PUT(i,j) (0x800040+(i)*0x10000+(j)*0x2000) +#define NV4_USER_DMA_PUT_OFFSET 2 +#define NV4_USER_DMA_GET(i,j) (0x800044+(i)*0x10000+(j)*0x2000) +#define NV4_USER_DMA_GET_OFFSET 2 + +#define NV4_USER_ADR_CHID 16 +#define NV4_USER_ADR_SUBCHID 13 +#define NV4_USER_ADR_METHOD 0 +#define NV4_USER_DEVICE 16 + +#define NV4_PTIMER_START 0x9000 +#define NV4_PTIMER_END 0x9FFF + +#define NV4_PTIMER_INTR_0 0x9100 +#define NV4_PTIMER_INTR_0_ALARM 0 +#define NV4_PTIMER_INTR_0_ALARM_NOT_PENDING 0x0 +#define NV4_PTIMER_INTR_0_ALARM_PENDING 0x1 +#define NV4_PTIMER_INTR_0_ALARM_RESET 0x1 +#define NV4_PTIMER_INTR_EN_0 0x9140 +#define NV4_PTIMER_INTR_EN_0_ALARM 0 +#define NV4_PTIMER_INTR_EN_0_ALARM_ENABLED 0x1 // 0 = disabled +#define NV4_PTIMER_NUMERATOR 0x9200 +#define NV4_PTIMER_NUMERATOR_VALUE 0 +#define NV4_PTIMER_NUMERATOR_VALUE_0 0x0 +#define NV4_PTIMER_DENOMINATOR 0x9210 +#define NV4_PTIMER_DENOMINATOR_VALUE 0 +#define NV4_PTIMER_DENOMINATOR_VALUE_0 0x0 +#define NV4_PTIMER_TIME_0 0x9400 +#define NV4_PTIMER_TIME_0_NSEC 31:5 +#define NV4_PTIMER_TIME_1 0x9410 +#define NV4_PTIMER_TIME_1_NSEC 0 +#define NV4_PTIMER_ALARM_0 0x9420 +#define NV4_PTIMER_ALARM_0_NSEC 31:5 + +#define NV4_TRACE 0xFFFF: 0x0 +#define NV4_TRACE_DATA ( 0*32+ 7):( 0*32+ 0) +#define NV4_TRACE_ACCESS ( 0*32+14):( 0*32+14) +#define NV4_TRACE_ACCESS_WRITE 0x0 +#define NV4_TRACE_ACCESS_READ 0x1 +#define NV4_TRACE_TYPE ( 0*32+15):( 0*32+15) +#define NV4_TRACE_TYPE_IO 0x0 +#define NV4_TRACE_TYPE_MEMORY 0x1 +#define NV4_TRACE_ADDRESS ( 0*32+31):( 0*32+16) + +#define NV4_RAMHT_SIZE_0 0xFFF +#define NV4_RAMHT_SIZE_1 0x1FFF +#define NV4_RAMHT_SIZE_2 0x3FFF +#define NV4_RAMHT_SIZE_3 0x7FFF +#define NV4_RAMHT_HANDLE ( 0*32+31):( 0*32+ 0) +#define NV4_RAMHT_INSTANCE ( 1*32+15):( 1*32+ 0) +#define NV4_RAMHT_ENGINE ( 1*32+17):( 1*32+16) +#define NV4_RAMHT_ENGINE_SW 0x0 +#define NV4_RAMHT_ENGINE_GRAPHICS 0x1 +#define NV4_RAMHT_ENGINE_DVD 0x2 +#define NV4_RAMHT_CHID ( 1*32+27):( 1*32+24) +#define NV4_RAMHT_STATUS ( 1*32+31):( 1*32+31) +#define NV4_RAMHT_STATUS_INVALID 0x0 +#define NV4_RAMHT_STATUS_VALID 0x1 + +#define NV4_RAMRO_SIZE_0 0x1FF +#define NV4_RAMRO_SIZE_1 0x1FFF +#define NV4_RAMRO_METHOD ( 0*32+12):( 0*32+ 0) +#define NV4_RAMRO_SUBCHANNEL ( 0*32+15):( 0*32+13) +#define NV4_RAMRO_CHID ( 0*32+22):( 0*32+16) +#define NV4_RAMRO_TYPE ( 0*32+23):( 0*32+23) +#define NV4_RAMRO_TYPE_WRITE 0x0 +#define NV4_RAMRO_TYPE_READ 0x1 +#define NV4_RAMRO_BYTE_ENABLES ( 0*32+27):( 0*32+24) +#define NV4_RAMRO_REASON ( 0*32+31):( 0*32+28) +#define NV4_RAMRO_REASON_ILLEGAL_ACCESS 0x0 +#define NV4_RAMRO_REASON_NO_CACHE_AVAILABLE 0x1 +#define NV4_RAMRO_REASON_CACHE_RAN_OUT 0x2 +#define NV4_RAMRO_REASON_FREE_COUNT_OVERRUN 0x3 +#define NV4_RAMRO_REASON_CAUGHT_LYING 0x4 +#define NV4_RAMRO_REASON_RESERVED_ACCESS 0x5 +#define NV4_RAMRO_DATA ( 1*32+31):( 1*32+ 0) + +#define NV4_RAMFC_SIZE_0 0x1FF +#define NV4_RAMFC_DMA_PUT ( 0*32+28):( 0*32+ 2) +#define NV4_RAMFC_DMA_GET ( 1*32+28):( 1*32+ 2) +#define NV4_RAMFC_DMA_INST ( 2*32+15):( 2*32+ 0) +#define NV4_RAMFC_DMA_METHOD ( 3*32+12):( 3*32+ 2) +#define NV4_RAMFC_DMA_SUBCHANNEL ( 3*32+15):( 3*32+13) +#define NV4_RAMFC_DMA_METHOD_COUNT ( 3*32+28):( 3*32+18) +#define NV4_RAMFC_DMA_FETCH_TRIG ( 4*32+ 7):( 4*32+ 3) +#define NV4_RAMFC_DMA_FETCH_SIZE ( 4*32+15):( 4*32+13) +#define NV4_RAMFC_DMA_FETCH_MAX_REQS ( 4*32+19):( 4*32+16) +#define NV4_RAMFC_ENGINE_SUB_0 ( 5*32+ 1):( 5*32+ 0) +#define NV4_RAMFC_ENGINE_SUB_1 ( 5*32+ 5):( 5*32+ 4) +#define NV4_RAMFC_ENGINE_SUB_2 ( 5*32+ 9):( 5*32+ 8) +#define NV4_RAMFC_ENGINE_SUB_3 ( 5*32+13):( 5*32+12) +#define NV4_RAMFC_ENGINE_SUB_4 ( 5*32+17):( 5*32+16) +#define NV4_RAMFC_ENGINE_SUB_5 ( 5*32+21):( 5*32+20) +#define NV4_RAMFC_ENGINE_SUB_6 ( 5*32+25):( 5*32+24) +#define NV4_RAMFC_ENGINE_SUB_7 ( 5*32+29):( 5*32+28) +#define NV4_RAMFC_ENGINE_SW 0x0 +#define NV4_RAMFC_ENGINE_GRAPHICS 0x1 +#define NV4_RAMFC_ENGINE_DVD 0x2 +#define NV4_RAMFC_PULL1_ENGINE ( 6*32+ 1):( 6*32+ 0) +#define NV4_RAMFC_PULL1_ENGINE_SW 0x0 +#define NV4_RAMFC_PULL1_ENGINE_GRAPHICS 0x1 +#define NV4_RAMFC_PULL1_ENGINE_DVD 0x2 + + +#define NV4_RAMDVD_CTX_TABLE (63*32+31):( 0*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT(c,s) (((c)*4+((s)/2))*32+((s)%2)*16+15):(((c)*4+((s)/2))*32+((s)%2)*16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_0 ( 0*32+15):( 0*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_1 ( 0*32+31):( 0*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_2 ( 1*32+15):( 1*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_3 ( 1*32+31):( 1*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_4 ( 2*32+15):( 2*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_5 ( 2*32+31):( 2*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_6 ( 3*32+15):( 3*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_7 ( 3*32+31):( 3*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_0 (60*32+15):(60*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_1 (60*32+31):(60*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_2 (61*32+15):(61*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_3 (61*32+31):(61*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_4 (62*32+15):(62*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_5 (62*32+31):(62*32+16) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_6 (63*32+15):(63*32+ 0) +#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_7 (63*32+31):(63*32+16) + +#define NV4_DMA_CLASS ( 0*32+11):( 0*32+ 0) +#define NV4_DMA_PAGE_TABLE ( 0*32+12):( 0*32+12) +#define NV4_DMA_PAGE_TABLE_NOT_PRESENT 0x0 +#define NV4_DMA_PAGE_TABLE_PRESENT 0x1 +#define NV4_DMA_PAGE_ENTRY ( 0*32+13):( 0*32+13) +#define NV4_DMA_PAGE_ENTRY_NOT_LINEAR 0x0 +#define NV4_DMA_PAGE_ENTRY_LINEAR 0x1 +#define NV4_DMA_TARGET_NODE ( 0*32+17):( 0*32+16) +#define NV4_DMA_TARGET_NODE_NVM 0x0 +#define NV4_DMA_TARGET_NODE_PCI 0x2 +#define NV4_DMA_TARGET_NODE_AGP 0x3 +#define NV4_DMA_ADJUST ( 0*32+31):( 0*32+20) +#define NV4_DMA_LIMIT ( 1*32+31):( 1*32+ 0) +#define NV4_DMA_ACCESS ( 2*32+ 1):( 2*32+ 1) +#define NV4_DMA_ACCESS_READ_ONLY 0x0 +#define NV4_DMA_ACCESS_READ_AND_WRITE 0x1 +#define NV4_DMA_FRAME_ADDRESS ( 2*32+31):( 2*32+12) + +#define NV4_SUBCHAN_CTX_SWITCH ( 0*32+31):( 0*32+ 0) +#define NV4_SUBCHAN_DMA_INSTANCE ( 1*32+15):( 1*32+ 0) +#define NV4_SUBCHAN_NOTIFY_INSTANCE ( 1*32+31):( 1*32+16) +#define NV4_SUBCHAN_MEMFMT_INSTANCE ( 2*32+15):( 2*32+ 0) +#define NV4_SUBCHAN_MEMFMT_LINEAR ( 2*32+16):( 2*32+16) +#define NV4_SUBCHAN_MEMFMT_LINEAR_OUT 0x0 +#define NV4_SUBCHAN_MEMFMT_LINEAR_IN 0x1 \ No newline at end of file From 984660794c9512c5557b8d3d5eea872a4521be44 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 11 Sep 2025 14:46:37 +0100 Subject: [PATCH 219/274] NV4 Timer is the same as NV3 Timer. Some minor stuff and start working on the "new way" of doing things... --- src/include/86box/nv/vid_nv4.h | 22 +- src/include/86box/nv/vid_nv4_defines.h | 26 +-- src/video/nv/nv4/nv4_core.c | 9 +- src/video/nv/nv4/nv4_debug_register_list.c | 0 src/video/nv/nv4/subsystems/nv4_ptimer.c | 226 +++++++++++++++++++++ 5 files changed, 266 insertions(+), 17 deletions(-) create mode 100644 src/video/nv/nv4/nv4_debug_register_list.c create mode 100644 src/video/nv/nv4/subsystems/nv4_ptimer.c diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 7fef843d4..6e94024a6 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -20,9 +20,10 @@ #include #include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv4_defines.h> -extern const device_config_t nv4_config[]; // Config for RIVA 128 (revision A/B) +extern const device_config_t nv4_config[]; +extern nv4_t* nv4; // Allocated at device startup // Structures typedef struct nv4_s @@ -30,6 +31,25 @@ typedef struct nv4_s nv_base_t nvbase; // Base Nvidia structure } nv4_t; +// +// PTIMER +// + +typedef struct nv4_ptimer_s +{ + uint32_t interrupt_status; // PTIMER Interrupt status + uint32_t interrupt_enable; // PTIMER Interrupt enable + uint32_t clock_numerator; // PTIMER (tick?) numerator + uint32_t clock_denominator; // PTIMER (tick?) denominator + uint64_t time; // time + uint32_t alarm; // The value of time when there should be an alarm +} nv4_ptimer_t; + + +// +// Functions +// + // Device Core void nv4_init(); void nv4_close(void* priv); diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h index f7499e3a8..e27ff091e 100644 --- a/src/include/86box/nv/vid_nv4_defines.h +++ b/src/include/86box/nv/vid_nv4_defines.h @@ -2745,7 +2745,7 @@ #define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0 1 #define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_COLOR 0x0 #define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0 2 #define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_ZERO 0x1 #define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_FACTOR 0x2 #define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_DIFFUSE 0x3 @@ -2807,7 +2807,7 @@ #define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0 0 #define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_NORMAL 0x0 #define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0 4:2 +#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0 2 #define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_ZERO 0x1 #define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_FACTOR 0x2 #define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_DIFFUSE 0x3 @@ -4177,14 +4177,14 @@ #define NV4_PTIMER_START 0x9000 #define NV4_PTIMER_END 0x9FFF -#define NV4_PTIMER_INTR_0 0x9100 -#define NV4_PTIMER_INTR_0_ALARM 0 -#define NV4_PTIMER_INTR_0_ALARM_NOT_PENDING 0x0 -#define NV4_PTIMER_INTR_0_ALARM_PENDING 0x1 -#define NV4_PTIMER_INTR_0_ALARM_RESET 0x1 -#define NV4_PTIMER_INTR_EN_0 0x9140 -#define NV4_PTIMER_INTR_EN_0_ALARM 0 -#define NV4_PTIMER_INTR_EN_0_ALARM_ENABLED 0x1 // 0 = disabled +#define NV4_PTIMER_INTR 0x9100 +#define NV4_PTIMER_INTR_ALARM 0 +#define NV4_PTIMER_INTR_ALARM_NOT_PENDING 0x0 +#define NV4_PTIMER_INTR_ALARM_PENDING 0x1 +#define NV4_PTIMER_INTR_ALARM_RESET 0x1 +#define NV4_PTIMER_INTR_EN 0x9140 +#define NV4_PTIMER_INTR_EN_ALARM 0 +#define NV4_PTIMER_INTR_EN_ALARM_ENABLED 0x1 // 0 = disabled #define NV4_PTIMER_NUMERATOR 0x9200 #define NV4_PTIMER_NUMERATOR_VALUE 0 #define NV4_PTIMER_NUMERATOR_VALUE_0 0x0 @@ -4192,11 +4192,11 @@ #define NV4_PTIMER_DENOMINATOR_VALUE 0 #define NV4_PTIMER_DENOMINATOR_VALUE_0 0x0 #define NV4_PTIMER_TIME_0 0x9400 -#define NV4_PTIMER_TIME_0_NSEC 31:5 +#define NV4_PTIMER_TIME_0_NSEC 5 #define NV4_PTIMER_TIME_1 0x9410 #define NV4_PTIMER_TIME_1_NSEC 0 -#define NV4_PTIMER_ALARM_0 0x9420 -#define NV4_PTIMER_ALARM_0_NSEC 31:5 +#define NV4_PTIMER_ALARM 0x9420 +#define NV4_PTIMER_ALARM_NSEC 5 #define NV4_TRACE 0xFFFF: 0x0 #define NV4_TRACE_DATA ( 0*32+ 7):( 0*32+ 0) diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c index 2af47f22a..d020e44e6 100644 --- a/src/video/nv/nv4/nv4_core.c +++ b/src/video/nv/nv4/nv4_core.c @@ -27,19 +27,22 @@ #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv4.h> +nv4_t* nv4; + void nv4_init() { - + nv4 = calloc(1, sizeof(nv4_t)); } void* nv4_init_stb4400(const device_t *info) { - + nv4_init(); + return nv4; } void nv4_close(void* priv) { - + free(nv4); } void nv4_speed_changed(void *priv) diff --git a/src/video/nv/nv4/nv4_debug_register_list.c b/src/video/nv/nv4/nv4_debug_register_list.c new file mode 100644 index 000000000..e69de29bb diff --git a/src/video/nv/nv4/subsystems/nv4_ptimer.c b/src/video/nv/nv4/subsystems/nv4_ptimer.c new file mode 100644 index 000000000..b52f79f17 --- /dev/null +++ b/src/video/nv/nv4/subsystems/nv4_ptimer.c @@ -0,0 +1,226 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Nvidia RIVA TNT (NV4 architecture) - Timer emulation + * + * + * + * Authors: Connor Hyde, + * + * Copyright 2024-2025 starfrost + */ + +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv4.h> + +nv_register_t ptimer_registers[] = { + { NV4_PTIMER_INTR, "NV4 PTIMER - Interrupt Status", NULL, NULL}, + { NV4_PTIMER_INTR_EN, "NV4 PTIMER - Interrupt Enable", NULL, NULL,}, + { NV4_PTIMER_NUMERATOR, "NV4 PTIMER - Numerator", NULL, NULL, }, + { NV4_PTIMER_DENOMINATOR, "NV4 PTIMER - Denominator", NULL, NULL, }, + { NV4_PTIMER_TIME_0_NSEC, "NV4 PTIMER - Time0", NULL, NULL, }, + { NV4_PTIMER_TIME_1_NSEC, "NV4 PTIMER - Time1", NULL, NULL, }, + { NV4_PTIMER_ALARM_NSEC, "NV4 PTIMER - Alarm", NULL, NULL, }, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +// ptimer init code +void nv4_ptimer_init(void) +{ + nv_log("Initialising PTIMER..."); + + nv_log("Done!\n"); +} + +// Handles the PTIMER alarm interrupt +void nv4_ptimer_interrupt(uint32_t num) +{ + nv4->ptimer.interrupt_status |= (1 << num); + + nv4_pmc_handle_interrupts(true); +} + +// Ticks the timer. +void nv4_ptimer_tick(double real_time) +{ + // prevent a divide by zero + if (nv4->ptimer.clock_numerator == 0 + || nv4->ptimer.clock_denominator == 0) + return; + + // get the current time + + // See Envytools. We need to use the frequency as a source. + // We need to figure out how many cycles actually occurred because this counts up every cycle... + // However it seems that their formula is wrong. I can't be bothered to figure out what's going on and, based on documentation from NVIDIA, + // timer_0 is meant to roll over every 4 seconds. Multiplying by 10 basically does the job. + + // Convert to microseconds + double freq_base = (real_time / 1000000.0f) / ((double)1.0 / nv4->nvbase.memory_clock_frequency) * 10.0f; + double current_time = freq_base * ((double)nv4->ptimer.clock_numerator) / (double)nv4->ptimer.clock_denominator; // *10.0? + + // truncate it + nv4->ptimer.time += (uint64_t)current_time; + + // Check if the alarm has actually triggered.. + // Only log on ptimer alarm. Otherwise, it's too much spam. + if (nv4->ptimer.time >= nv4->ptimer.alarm) + { + nv_log_verbose_only("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv4->ptimer.alarm); + nv4_ptimer_interrupt(NV4_PTIMER_INTR_ALARM); + } +} + +uint32_t nv4_ptimer_read(uint32_t address) +{ + // always enabled + + nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); + + // Only log these when tehy actually tick + if (address != NV4_PTIMER_TIME_0_NSEC + && address != NV4_PTIMER_TIME_1_NSEC) + { + nv_log_verbose_only("PTIMER Read from 0x%08x", address); + } + + uint32_t ret = 0x00; + + // if the register actually exists + if (reg) + { + // on-read function + if (reg->on_read) + ret = reg->on_read(); + else + { + // Interrupt state: + // Bit 0: Alarm + + switch (reg->address) + { + case NV4_PTIMER_INTR: + ret = nv4->ptimer.interrupt_status; + break; + case NV4_PTIMER_INTR_EN: + ret = nv4->ptimer.interrupt_enable; + break; + case NV4_PTIMER_NUMERATOR: + ret = nv4->ptimer.clock_numerator; // 15:0 + break; + case NV4_PTIMER_DENOMINATOR: + ret = nv4->ptimer.clock_denominator ; //15:0 + break; + // 64-bit value + // High part + case NV4_PTIMER_TIME_0_NSEC: + ret = nv4->ptimer.time & 0xFFFFFFFF; //28:0 + break; + // Low part + case NV4_PTIMER_TIME_1_NSEC: + ret = nv4->ptimer.time >> 32; // 31:5 + break; + case NV4_PTIMER_ALARM_NSEC: + ret = nv4->ptimer.alarm; // 31:5 + break; + } + + } + //TIME0 and TIME1 produce too much log spam that slows everything down + if (reg->address != NV4_PTIMER_TIME_0_NSEC + && reg->address != NV4_PTIMER_TIME_1_NSEC) + { + if (reg->friendly_name) + nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); + else + nv_log_verbose_only("\n"); + } + } + else + { + nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); + } + + return ret; +} + +void nv4_ptimer_write(uint32_t address, uint32_t value) +{ + // before doing anything, check the subsystem enablement + nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); + + nv_log_verbose_only("PTIMER Write 0x%08x -> 0x%08x", value, address); + + // if the register actually exists + if (reg) + { + if (reg->friendly_name) + nv_log_verbose_only(": %s\n", reg->friendly_name); + else + nv_log_verbose_only("\n"); + + // on-read function + if (reg->on_write) + reg->on_write(value); + else + { + switch (reg->address) + { + // Interrupt state: + // Bit 0 - Alarm + + case NV4_PTIMER_INTR: + nv4->ptimer.interrupt_status &= ~value; + nv4_pmc_clear_interrupts(); + break; + + // Interrupt enablement state + case NV4_PTIMER_INTR_EN: + nv4->ptimer.interrupt_enable = value & 0x1; + break; + // nUMERATOR + case NV4_PTIMER_NUMERATOR: + nv4->ptimer.clock_numerator = value & 0xFFFF; // 15:0 + break; + case NV4_PTIMER_DENOMINATOR: + // prevent Div0 + if (!value) + value = 1; + + nv4->ptimer.clock_denominator = value & 0xFFFF; //15:0 + break; + // 64-bit value + // High part + case NV4_PTIMER_TIME_0_NSEC: + nv4->ptimer.time |= (value) & 0xFFFFFFE0; //28:0 + break; + // Low part + case NV4_PTIMER_TIME_1_NSEC: + nv4->ptimer.time |= ((uint64_t)(value & 0xFFFFFFE0) << 32); // 31:5 + break; + case NV4_PTIMER_ALARM: + nv4->ptimer.alarm = value & 0xFFFFFFE0; // 31:5 + break; + } + } + } + else /* Completely unknown */ + { + nv_log(": Unknown register write (address=0x%08x)\n", address); + } +} \ No newline at end of file From f73e6af2e5ff7d6f03bed72f36b28fa7650f4637 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Thu, 11 Sep 2025 14:49:28 +0100 Subject: [PATCH 220/274] fix compile [again] --- src/include/86box/nv/vid_nv1.h | 1 - src/include/86box/nv/vid_nv4.h | 12 +++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/include/86box/nv/vid_nv1.h b/src/include/86box/nv/vid_nv1.h index 9d08bb186..be6895c8b 100644 --- a/src/include/86box/nv/vid_nv1.h +++ b/src/include/86box/nv/vid_nv1.h @@ -17,7 +17,6 @@ #include #include -#include <86Box/nv/vid_nv.h> extern const device_config_t nv1_config[]; // Config for RIVA 128 (revision A/B) diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 6e94024a6..3415f065b 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -18,13 +18,8 @@ #include #include -#include <86Box/nv/vid_nv.h> #include <86Box/nv/vid_nv4_defines.h> -extern const device_config_t nv4_config[]; - -extern nv4_t* nv4; // Allocated at device startup - // Structures typedef struct nv4_s { @@ -46,6 +41,13 @@ typedef struct nv4_ptimer_s } nv4_ptimer_t; +// +// Globals +// +extern const device_config_t nv4_config[]; + +extern nv4_t* nv4; // Allocated at device startup + // // Functions // From d6388a825ce32eeaac0e232f002b1fcb7934308e Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 13 Sep 2025 17:22:04 +0100 Subject: [PATCH 221/274] Initial port of core nv3 stuff to nv4 --- src/include/86box/nv/vid_nv.h | 12 +- src/include/86box/nv/vid_nv3.h | 11 +- src/include/86box/nv/vid_nv4.h | 74 +- src/include/86box/nv/vid_nv4_defines.h | 471 ++++----- src/video/CMakeLists.txt | 1 + src/video/nv/nv3/nv3_core.c | 84 +- src/video/nv/nv4/nv4_core.c | 173 +++- src/video/nv/nv4/nv4_core_io.c | 1310 ++++++++++++++++++++++++ 8 files changed, 1819 insertions(+), 317 deletions(-) create mode 100644 src/video/nv/nv4/nv4_core_io.c diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 655fb3950..3d69f75c7 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -97,10 +97,19 @@ typedef enum nv_bus_generation_e } nv_bus_generation; +// PCI configuration +typedef struct nv_pci_config_s +{ + uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability) + bool vbios_enabled; // is the vbios enabled? + uint8_t int_line; +} nv_pci_config_t; + // NV Base typedef struct nv_base_s { rom_t vbios; // NVIDIA/OEm VBIOS + nv_pci_config_t pci_config; // PCI configuration // move to nv3_cio_t? svga_t svga; // SVGA core (separate to nv3) - Weitek licensed uint32_t vram_amount; // The amount of VRAM @@ -113,7 +122,7 @@ typedef struct nv_base_s mem_mapping_t mmio_mapping; // mmio mapping (32MB unified MMIO) mem_mapping_t framebuffer_mapping_mirror; // Mirror of LFB mapping mem_mapping_t ramin_mapping; // RAM INput area mapping - mem_mapping_t ramin_mapping_mirror; // RAM INput area mapping (mirrored) + mem_mapping_t ramin_mapping_mirror; // RAM INput area mapping (mirrored) - NV3 ONLY uint8_t pci_slot; // pci slot number uint8_t pci_irq_state; // current PCI irq state uint32_t bar0_mmio_base; // PCI Base Address Register 0 - MMIO Base @@ -131,6 +140,7 @@ typedef struct nv_base_s void* i2c; // I2C for monitor EDID void* ddc; // Display Data Channel for EDID bool agp_enabled; // AGP Enabled (for debugging) + bool agp_sba_enabled; // AGP Sideband Addressing enabled // // DEBUG UI STUFF diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index b954355bb..3726ecc03 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -1013,15 +1013,7 @@ typedef struct nv3_pmc_s } nv3_pmc_t; -typedef struct nv3_pci_config_s -{ - uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability) - bool vbios_enabled; // is the vbios enabled? - uint8_t int_line; -} nv3_pci_config_t; - - -// add enums for eac +// add enums for eac // Chip configuration typedef struct nv3_straps_s { @@ -1546,7 +1538,6 @@ typedef struct nv3_s // Config nv3_straps_t straps; // OEM Configuration - nv3_pci_config_t pci_config; // PCI Configuration // Subsystems nv3_pmc_t pmc; // Master Control diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 3415f065b..7fda0fca4 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -20,11 +20,28 @@ #include #include <86Box/nv/vid_nv4_defines.h> -// Structures -typedef struct nv4_s + +// +// PBUS/RMA +// + +// Access the GPU from real-mode +typedef struct nv4_pbus_rma_s { - nv_base_t nvbase; // Base Nvidia structure -} nv4_t; + uint32_t addr; // Address to RMA to + uint32_t data; // Data to send to MMIO + uint8_t mode; // the current state of the rma shifting engin + uint8_t rma_regs[NV4_RMA_NUM_REGS]; // The rma registers (saved) +} nv4_pbus_rma_t; + +// Bus Configuration +typedef struct nv4_pbus_s +{ + uint32_t debug_0; + uint32_t interrupt_status; // Interrupt status + uint32_t interrupt_enable; // Interrupt enable + nv4_pbus_rma_t rma; +} nv4_pbus_t; // // PTIMER @@ -40,6 +57,27 @@ typedef struct nv4_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv4_ptimer_t; +// +// PRAMDAC +// +typedef struct nv4_pramdac_s +{ + uint32_t mclk; + uint32_t vclk; + uint32_t nvclk; + uint32_t cursor_address; +} nv4_pramdac_t; + +// Structures +typedef struct nv4_s +{ + nv_base_t nvbase; // Base Nvidia structure + uint32_t straps; // Straps. See defines + nv4_pbus_t pbus; + nv4_ptimer_t ptimer; + nv4_pramdac_t pramdac; +} nv4_t; + // // Globals @@ -58,4 +96,30 @@ void nv4_close(void* priv); void nv4_speed_changed(void *priv); void nv4_draw_cursor(svga_t* svga, int32_t drawline); void nv4_recalc_timings(svga_t* svga); -void nv4_force_redraw(void* priv); \ No newline at end of file +void nv4_force_redraw(void* priv); + +// I/o +uint8_t nv4_mmio_read8(uint32_t addr, void* priv); +uint16_t nv4_mmio_read16(uint32_t addr, void* priv); +uint32_t nv4_mmio_read32(uint32_t addr, void* priv); +void nv4_mmio_write8(uint32_t addr, uint8_t val, void* priv); +void nv4_mmio_write16(uint32_t addr, uint16_t val, void* priv); +void nv4_mmio_write32(uint32_t addr, uint32_t val, void* priv); +uint8_t nv4_dfb_read8(uint32_t addr, void* priv); +uint16_t nv4_dfb_read16(uint32_t addr, void* priv); +uint32_t nv4_dfb_read32(uint32_t addr, void* priv); +void nv4_dfb_write8(uint32_t addr, uint8_t val, void* priv); +void nv4_dfb_write16(uint32_t addr, uint16_t val, void* priv); +void nv4_dfb_write32(uint32_t addr, uint32_t val, void* priv); +uint8_t nv4_ramin_read8(uint32_t addr, void* priv); +uint16_t nv4_ramin_read16(uint32_t addr, void* priv); +uint32_t nv4_ramin_read32(uint32_t addr, void* priv); +void nv4_ramin_write8(uint32_t addr, uint8_t val, void* priv); +void nv4_ramin_write16(uint32_t addr, uint16_t val, void* priv); +void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv); + + +uint8_t nv4_svga_read(uint16_t addr, void* priv); +void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); + +void nv4_update_mappings(); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h index e27ff091e..21cf5739a 100644 --- a/src/include/86box/nv/vid_nv4_defines.h +++ b/src/include/86box/nv/vid_nv4_defines.h @@ -7,12 +7,12 @@ // General // #define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) -#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) -#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB -#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB -#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only +#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) +#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB +#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB +#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only -#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! +#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! // // VBIOS @@ -21,6 +21,12 @@ #define NV4_PRMIO_START 0x7000 #define NV4_PRMIO_END 0x7FFF + +// NV4 Legacy I/O space +#define NV4_RMA_REGISTER_START 0x3D0 +#define NV4_RMA_REGISTER_END 0x3D3 +#define NV4_RMA_NUM_REGS 4 + #define NV4_PRMIO_RMA_ID 0x7100 #define NV4_PRMIO_RMA_ID_CODE 0 #define NV4_PRMIO_RMA_ID_CODE_VALID 0x2B16D065 @@ -32,6 +38,7 @@ #define NV4_PRMIO_RMA_DATA32_BYTE2 16 #define NV4_PRMIO_RMA_DATA32_BYTE1 8 #define NV4_PRMIO_RMA_DATA32_BYTE0 0 +#define NV4_PRMIO_RMA_MODE_MAX 0x0F #define NV4_PRAMDAC_START 0x680300 #define NV4_PRAMDAC_END 0x680FFF @@ -261,6 +268,8 @@ #define NV4_USER_DAC_START 0x681200 #define NV4_USER_DAC_END 0x681FFF +#define NV4_USER_DAC_PALETTE_START 0x6813C6 +#define NV4_USER_DAC_PALETTE_END 0x6813C9 #define NV4_USER_DAC_PIXEL_MASK 0x6813C6 #define NV4_USER_DAC_PIXEL_MASK_VALUE 0 @@ -486,223 +495,181 @@ #define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR_ENABLED 0x1 #define NV4_PBUS_ROM_CONFIG 0x1200 #define NV4_PBUS_ROM_CONFIG_TW1 0 -#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF -#define NV4_PBUS_ROM_CONFIG_TW0 4 -#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3 -#define NV4_PBUS_PCI_NV_0 0x1800 -#define NV4_PBUS_PCI_NV_0_VENDOR_ID 0 -#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA_SGS 0x12D2 -#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA 0x10DE -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC 16 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC_VGA 0x0 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP 3 19 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV0 0x0 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV1 0x1 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV2 0x2 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV3 0x3 -#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV4 0x4 -#define NV4_PBUS_PCI_NV_1 0x1804 -#define NV4_PBUS_PCI_NV_1_IO_SPACE 0 -#define NV4_PBUS_PCI_NV_1_IO_SPACE_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE 1 -#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_1_BUS_MASTER 2 -#define NV4_PBUS_PCI_NV_1_BUS_MASTER_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL 4 -#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP 5 -#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_1_CAPLIST 20 -#define NV4_PBUS_PCI_NV_1_CAPLIST_NOT_PRESENT 0x0 -#define NV4_PBUS_PCI_NV_1_CAPLIST_PRESENT 0x1 -#define NV4_PBUS_PCI_NV_1_66MHZ 21 -#define NV4_PBUS_PCI_NV_1_66MHZ_INCAPABLE 0x0 -#define NV4_PBUS_PCI_NV_1_66MHZ_CAPABLE 0x1 -#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK 23 -#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_INCAPABLE 0x0 -#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_CAPABLE 0x1 -#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING 25 -#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_FAST 0x0 -#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_MEDIUM 0x1 -#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_SLOW 0x2 -#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET 27 -#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_NO_ABORT 0x0 -#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_ABORT 0x1 -#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_CLEAR 0x1 -#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET 28 -#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_NO_ABORT 0x0 -#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_ABORT 0x1 -#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_CLEAR 0x1 -#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER 29 -#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_NO_ABORT 0x0 -#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_ABORT 0x1 -#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_CLEAR 0x1 -#define NV4_PBUS_PCI_NV_2 0x1808 -#define NV4_PBUS_PCI_NV_2_REVISION_ID 0 -#define NV4_PBUS_PCI_NV_2_REVISION_ID_A01 0x0 -#define NV4_PBUS_PCI_NV_2_REVISION_ID_B01 0x10 -#define NV4_PBUS_PCI_NV_2_CLASS_CODE 8 -#define NV4_PBUS_PCI_NV_2_CLASS_CODE_VGA 0x30000 -#define NV4_PBUS_PCI_NV_2_CLASS_CODE_MULTIMEDIA 0x48000 -#define NV4_PBUS_PCI_NV_3 0x180C -#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER 11 -#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x0 -#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x1 -#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x1E -#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x1F -#define NV4_PBUS_PCI_NV_3_HEADER_TYPE 16 -#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_SINGLEFUNC 0x0 -#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_MULTIFUNC 0x80 -#define NV4_PBUS_PCI_NV_4 0x1810 -#define NV4_PBUS_PCI_NV_4_SPACE_TYPE 0 -#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_MEMORY 0x0 -#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_IO 0x1 -#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE 1 -#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_32_BIT 0x0 -#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_20_BIT 0x1 -#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_64_BIT 0x2 -#define NV4_PBUS_PCI_NV_4_PREFETCHABLE 3 -#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_NOT 0x0 -#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_MERGABLE 0x1 -#define NV4_PBUS_PCI_NV_4_BASE_ADDRESS 24 -#define NV4_PBUS_PCI_NV_5 0x1814 -#define NV4_PBUS_PCI_NV_5_SPACE_TYPE 0 -#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_MEMORY 0x0 -#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_IO 0x1 -#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE 2:1 -#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_32_BIT 0x0 -#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_20_BIT 0x1 -#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x2 -#define NV4_PBUS_PCI_NV_5_PREFETCHABLE 3 -#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_NOT 0x0 -#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_MERGABLE 0x1 -#define NV4_PBUS_PCI_NV_5_BASE_ADDRESS 24 -#define NV4_PBUS_PCI_NV_6(i) (0x1818+(i)*4) -#define NV4_PBUS_PCI_NV_6_SIZE_1 5 -#define NV4_PBUS_PCI_NV_6_RESERVED 0 -#define NV4_PBUS_PCI_NV_6_RESERVED_0 0x0 -#define NV4_PBUS_PCI_NV_11 0x182C -#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID 0 -#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x0 -#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID 16 -#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID_NONE 0x0 -#define NV4_PBUS_PCI_NV_12 0x1830 -#define NV4_PBUS_PCI_NV_12_ROM_DECODE 0 -#define NV4_PBUS_PCI_NV_12_ROM_DECODE_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_12_ROM_BASE 16 -#define NV4_PBUS_PCI_NV_13 0x1834 -#define NV4_PBUS_PCI_NV_13_CAP_PTR 0 -#define NV4_PBUS_PCI_NV_13_CAP_PTR_AGP 0x44 -#define NV4_PBUS_PCI_NV_13_CAP_PTR_POWER_MGMT 0x60 -#define NV4_PBUS_PCI_NV_14 0x1838 -#define NV4_PBUS_PCI_NV_14_RESERVED 0 -#define NV4_PBUS_PCI_NV_14_RESERVED_0 0x0 -#define NV4_PBUS_PCI_NV_15 0x183C -#define NV4_PBUS_PCI_NV_15_INTR_LINE 0 -#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ0 0x0 -#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ1 0x1 -#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ15 0xF -#define NV4_PBUS_PCI_NV_15_INTR_LINE_UNKNOWN 0xFF -#define NV4_PBUS_PCI_NV_15_INTR_PIN 8 -#define NV4_PBUS_PCI_NV_15_INTR_PIN_INTA 0x1 -#define NV4_PBUS_PCI_NV_15_MIN_GNT 16 -#define NV4_PBUS_PCI_NV_15_MIN_GNT_NO_REQUIREMENTS 0x0 -#define NV4_PBUS_PCI_NV_15_MIN_GNT_750NS 0x3 -#define NV4_PBUS_PCI_NV_15_MIN_GNT_1250NS 0x5 -#define NV4_PBUS_PCI_NV_15_MAX_LAT 24 -#define NV4_PBUS_PCI_NV_15_MAX_LAT_NO_REQUIREMENTS 0x0 -#define NV4_PBUS_PCI_NV_15_MAX_LAT_250NS 0x1 -#define NV4_PBUS_PCI_NV_16 0x1840 -#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID 0 -#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID_NONE 0x0 -#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID 16 -#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID_NONE 0x0 -#define NV4_PBUS_PCI_NV_17 0x1844 -#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR 20 -#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR_1 0x1 -#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR 16 -#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR_0 0x0 -#define NV4_PBUS_PCI_NV_17_NEXT_PTR 8 -#define NV4_PBUS_PCI_NV_17_NEXT_PTR_NULL 0x0 -#define NV4_PBUS_PCI_NV_17_CAP_ID 0 -#define NV4_PBUS_PCI_NV_17_CAP_ID_AGP 0x2 -#define NV4_PBUS_PCI_NV_18 0x1848 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ 24 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ_16 0xF -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA 9 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_NONE 0x0 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_CAPABLE 0x1 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE 0 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X 0x1 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_2X 0x2 -#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X_AND_2X 0x3 -#define NV4_PBUS_PCI_NV_19 0x184C -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH 24 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH_0 0x0 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE 9 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_OFF 0x0 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_ON 0x1 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE 8 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_OFF 0x0 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_ON 0x1 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE 0 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_OFF 0x0 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_1X 0x1 -#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_2X 0x2 -#define NV4_PBUS_PCI_NV_20 0x1850 -#define NV4_PBUS_PCI_NV_20_ROM_SHADOW 0 -#define NV4_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_21 0x1854 -#define NV4_PBUS_PCI_NV_21_VGA 0 -#define NV4_PBUS_PCI_NV_21_VGA_ENABLED 0x1 -#define NV4_PBUS_PCI_NV_22 0x1858 -#define NV4_PBUS_PCI_NV_22_SCRATCH 0 -#define NV4_PBUS_PCI_NV_22_SCRATCH_DEFAULT 0x23D6CE -#define NV4_PBUS_PCI_NV_23 0x185C -#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT 0 -#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT_16 0xF -#define NV4_PBUS_PCI_NV_24 0x1860 -#define NV4_PBUS_PCI_NV_24_PME_D3_COLD 31 -#define NV4_PBUS_PCI_NV_24_PME_D3_COLD_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_PME_D3_HOT 30 -#define NV4_PBUS_PCI_NV_24_PME_D3_HOT_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_PME_D2 29 -#define NV4_PBUS_PCI_NV_24_PME_D2_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_PME_D1 28 -#define NV4_PBUS_PCI_NV_24_PME_D1_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_PME_D0 27 -#define NV4_PBUS_PCI_NV_24_PME_D0_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_D2 26 -#define NV4_PBUS_PCI_NV_24_D2_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_D2_NOT_SUPPORTED 0x0 -#define NV4_PBUS_PCI_NV_24_D1 25 -#define NV4_PBUS_PCI_NV_24_D1_SUPPORTED 0x1 -#define NV4_PBUS_PCI_NV_24_D1_NOT_SUPPORTED 0x0 -#define NV4_PBUS_PCI_NV_24_DSI 21 -#define NV4_PBUS_PCI_NV_24_DSI_NOT_REQUIRED 0x0 -#define NV4_PBUS_PCI_NV_24_PME_CLOCK 19 -#define NV4_PBUS_PCI_NV_24_PME_CLOCK_NOT_REQUIRED 0x0 -#define NV4_PBUS_PCI_NV_24_VERSION 16 -#define NV4_PBUS_PCI_NV_24_VERSION_1 0x1 -#define NV4_PBUS_PCI_NV_24_NEXT_PTR 8 -#define NV4_PBUS_PCI_NV_24_NEXT_PTR_NULL 0x0 -#define NV4_PBUS_PCI_NV_24_NEXT_PTR_AGP 0x44 -#define NV4_PBUS_PCI_NV_24_CAP_ID 0 -#define NV4_PBUS_PCI_NV_24_CAP_ID_POWER_MGMT 0x1 -#define NV4_PBUS_PCI_NV_25 0x1864 -#define NV4_PBUS_PCI_NV_25_POWER_STATE 0 -#define NV4_PBUS_PCI_NV_25_POWER_STATE_D3_HOT 0x3 -#define NV4_PBUS_PCI_NV_25_POWER_STATE_D2 0x2 -#define NV4_PBUS_PCI_NV_25_POWER_STATE_D1 0x1 -#define NV4_PBUS_PCI_NV_25_POWER_STATE_D0 0x0 -#define NV4_PBUS_PCI_NV_26(i) (0x1868+(i)*4) -#define NV4_PBUS_PCI_NV_26_SIZE_1 38 -#define NV4_PBUS_PCI_NV_26_RESERVED 0 -#define NV4_PBUS_PCI_NV_26_RESERVED_0 0x0 +#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF +#define NV4_PBUS_ROM_CONFIG_TW0 4 +#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3 +// 86Box uses 8-bit PCI registers so this section was rewritten +#define NV4_PBUS_PCI_VENDOR_ID 0x1800 +#define NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA 0x10DE +#define NV4_PBUS_PCI_DEVICE_ID 0x1802 +#define NV4_PBUS_PCI_DEVICE_ID_NV4 0x0020 // Chip (19:17)= NV4, Func = VGA +#define NV4_PBUS_PCI_COMMAND 0x1804 +#define NV4_PBUS_PCI_COMMAND_IO_SPACE 0 +#define NV4_PBUS_PCI_COMMAND_IO_SPACE_ENABLED 0x1 +#define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE 1 +#define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE_ENABLED 0x1 +#define NV4_PBUS_PCI_COMMAND_BUS_MASTER 2 +#define NV4_PBUS_PCI_COMMAND_BUS_MASTER_ENABLED 0x1 +#define NV4_PBUS_PCI_COMMAND_WRITE_AND_INVAL 4 +#define NV4_PBUS_PCI_COMMAND_WRITE_AND_INVAL_ENABLED 0x1 +#define NV4_PBUS_PCI_COMMAND_PALETTE_SNOOP 5 +#define NV4_PBUS_PCI_COMMAND_PALETTE_SNOOP_ENABLED 0x1 +#define NV4_PBUS_PCI_STATUS 0x1806 +#define NV4_PBUS_PCI_STATUS_CAPLIST 4 +#define NV4_PBUS_PCI_STATUS_CAPLIST_NOT_PRESENT 0x0 +#define NV4_PBUS_PCI_STATUS_CAPLIST_PRESENT 0x1 +#define NV4_PBUS_PCI_STATUS_66MHZ 5 +#define NV4_PBUS_PCI_STATUS_66MHZ_INCAPABLE 0x0 +#define NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE 0x1 +#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK 7 +#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK_INCAPABLE 0x0 +#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK_CAPABLE 0x1 +#define NV4_PBUS_PCI_STATUS_2 0x1807 +#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING 1 +#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST 0x0 +#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_MEDIUM 0x1 +#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_SLOW 0x2 +#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET 3 +#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_NO_ABORT 0x0 +#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_ABORT 0x1 +#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_CLEAR 0x1 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET 4 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_NO_ABORT 0x0 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_ABORT 0x1 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_CLEAR 0x1 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER 5 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_NO_ABORT 0x0 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_ABORT 0x1 +#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_CLEAR 0x1 +#define NV4_PBUS_PCI_REVISION_ID 0x1808 +#define NV4_PBUS_PCI_REVISION_ID_A01 0x0 +#define NV4_PBUS_PCI_REVISION_ID_B01 0x1 +#define NV4_PBUS_PCI_CLASS_CODE 0x180B +#define NV4_PBUS_PCI_CLASS_CODE_VGA 0x30000 +#define NV4_PBUS_PCI_LATENCY_TIMER 0x180D +// Shift left by 3 to get the real value in clocks. 0x0 = 0, 0x1 = 8, 0x1E = 240, 0x1F = 248 are values used. +#define NV4_PBUS_PCI_LATENCY_TIMER_VALUE 3 +// 0x0 = single function (only value that matters) +#define NV4_PBUS_PCI_HEADER_TYPE 0x180E +#define NV4_PBUS_PCI_BAR_SPACE_TYPE 0 +#define NV4_PBUS_PCI_BAR_SPACE_TYPE_MEMORY 0x0 +#define NV4_PBUS_PCI_BAR_SPACE_TYPE_IO 0x1 +#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE 1 +#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_32_BIT 0x0 +#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_20_BIT 0x1 +#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_64_BIT 0x2 +#define NV4_PBUS_PCI_BAR_PREFETCHABLE 3 +#define NV4_PBUS_PCI_BAR_PREFETCHABLE_NOT 0x0 +#define NV4_PBUS_PCI_BAR_PREFETCHABLE_MERGABLE 0x1 +// Bits 23:4 are resedrved +#define NV4_PBUS_PCI_BAR0_INFO 0x1810 +#define NV4_PBUS_PCI_BAR0_UNUSED1 0x1811 +#define NV4_PBUS_PCI_BAR0_UNUSED2 0x1812 +#define NV4_PBUS_PCI_BAR0_BASE_31_TO_24 0x1813 // Must align to 16MByte +#define NV4_PBUS_PCI_BAR1_INFO 0x1814 +#define NV4_PBUS_PCI_BAR1_UNUSED1 0x1814 +#define NV4_PBUS_PCI_BAR1_UNUSED2 0x1815 +#define NV4_PBUS_PCI_BAR1_BASE_31_TO_24 0x1816 // Must align to 16MByte +//BAR2-5 reserved +#define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID 0x182C +#define NV4_PBUS_PCI_SUBSYSTEM_ID 0x182E +#define NV4_PBUS_PCI_ROM 0x1830 +#define NV4_PBUS_PCI_ROM_DECODE 0 +#define NV4_PBUS_PCI_ROM_DECODE_ENABLED 0x1 +#define NV4_PBUS_PCI_ROM_BASE 0x1832 +#define NV4_PBUS_PCI_NEXT_PTR 0x1834 +#define NV4_PBUS_PCI_CAP_PTR_AGP 0x44 +#define NV4_PBUS_PCI_CAP_PTR_POWER_MGMT 0x60 +// 0xFF = unknown, otherwise 0x0-0xF = IRQ0-15 +#define NV4_PBUS_PCI_INTR_LINE 0x183C +#define NV4_PBUS_PCI_INTR_LINE_IRQ_NUM 0 +#define NV4_PBUS_PCI_INTR_LINE_IRQ_NUM_UNKNOWN 0xFF +#define NV4_PBUS_PCI_INTR_PIN 0x183D +#define NV4_PBUS_PCI_INTR_PIN_INTA 0x1 +#define NV4_PBUS_PCI_MIN_GNT 0x183E +#define NV4_PBUS_PCI_MIN_GNT_NO_REQUIREMENTS 0x0 +#define NV4_PBUS_PCI_MIN_GNT_750NS 0x3 +#define NV4_PBUS_PCI_MIN_GNT_1250NS 0x5 +#define NV4_PBUS_PCI_MAX_LAT 0x183F +#define NV4_PBUS_PCI_MAX_LAT_NO_REQUIREMENTS 0x0 +#define NV4_PBUS_PCI_MAX_LAT_250NS 0x1 +#define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE 0x1840 +#define NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE 0x1842 +#define NV4_PBUS_AGP 0x44 +#define NV4_PBUS_AGP_CAPABILITIES 0x1844 +#define NV4_PBUS_AGP_CAPABILITY_AGP 0x2 +// Should be null! + +#define NV4_PBUS_AGP_NEXT_PTR 0x1845 +#define NV4_PBUS_AGP_REV 0x1846 +#define NV4_PBUS_AGP_REV_MINOR 0 +#define NV4_PBUS_AGP_REV_MINOR_0 0x0 +#define NV4_PBUS_AGP_REV_MAJOR 4 +#define NV4_PBUS_AGP_REV_MAJOR_1 0x1 +#define NV4_PBUS_AGP_STATUS_RATE 0x1848 +#define NV4_PBUS_AGP_STATUS_RATE_1X 0x1 +#define NV4_PBUS_AGP_STATUS_RATE_2X 0x2 +#define NV4_PBUS_AGP_STATUS_RATE_1X_AND_2X 0x3 +#define NV4_PBUS_AGP_STATUS_RQ 0x184B +#define NV4_PBUS_AGP_STATUS_RQ_16 0xF +#define NV4_PBUS_AGP_STATUS_SBA 0x1849 +#define NV4_PBUS_AGP_STATUS_SBA_STATUS 1 +#define NV4_PBUS_AGP_STATUS_SBA_STATUS_NONE 0x0 +#define NV4_PBUS_AGP_STATUS_SBA_STATUS_CAPABLE 0x1 +#define NV4_PBUS_AGP_COMMAND 0x184C +#define NV4_PBUS_AGP_COMMAND_DATA_RATE 0 +#define NV4_PBUS_AGP_COMMAND_DATA_RATE_OFF 0x0 +#define NV4_PBUS_AGP_COMMAND_DATA_RATE_1X 0x1 +#define NV4_PBUS_AGP_COMMAND_DATA_RATE_2X 0x2 +#define NV4_PBUS_AGP_COMMAND_2 0x184D +#define NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED 0 // 1 = enabled, 0 = disabled +#define NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED 1 // 1 = enabled, 0 = disabled +#define NV4_PBUS_AGP_COMMAND_RQ_DEPTH 0x184F //DEFAUlt 0 +#define NV4_PBUS_PCI_ROM_SHADOW 0x1850 +#define NV4_PBUS_PCI_ROM_SHADOW_IS_ENABLED 0 // 1 = enabled, 0 = disabled +#define NV4_PBUS_PCI_VGA 0x1854 +#define NV4_PBUS_PCI_VGA_IS_ENABLED 0 // 1 = enabled, 0 = disabled +#define NV4_PBUS_PCI_SCRATCH 0x1858 +#define NV4_PBUS_PCI_SCRATCH_DEFAULT 0x23D6CE +#define NV4_PBUS_PCI_DT 0x185C +#define NV4_PBUS_PCI_DT_TIMEOUT 0 +#define NV4_PBUS_PCI_DT_TIMEOUT_16 0xF +//TODO: Implement +#define NV4_PBUS_PCIPOWER 0x1860 +#define NV4_PBUS_PCIPOWER_CAP_ID 0 +#define NV4_PBUS_PCIPOWER_CAP_ID_POWER_MGMT 0x1 +#define NV4_PBUS_PCIPOWER_NEXT_PTR 0x1861 // should be 0x44=AGP +#define NV4_PBUS_PCIPOWER_2 0x1862 +#define NV4_PBUS_PCIPOWER_2_VERSION 0 +#define NV4_PBUS_PCIPOWER_2_VERSION_1 0x1 +#define NV4_PBUS_PCIPOWER_2_CLOCK 3 +#define NV4_PBUS_PCIPOWER_2_CLOCK_NOT_REQUIRED 0x0 +#define NV4_PBUS_PCIPOWER_2_DSI 5 +#define NV4_PBUS_PCIPOWER_2_DSI_NOT_REQUIRED 0x0 +#define NV4_PBUS_PCIPOWER_SUPPORTED_STATES 0x1863 +#define NV4_PBUS_PCIPOWER_D1 1 +#define NV4_PBUS_PCIPOWER_D1_SUPPORTED 0x1 // 1 = supported +#define NV4_PBUS_PCIPOWER_D2 2 +#define NV4_PBUS_PCIPOWER_D2_SUPPORTED 0x1 // 0 = not supported +#define NV4_PBUS_PCIPOWER_PME_D0 3 +#define NV4_PBUS_PCIPOWER_PME_D0_SUPPORTED 0x1 +#define NV4_PBUS_PCIPOWER_PME_D1 4 +#define NV4_PBUS_PCIPOWER_PME_D1_SUPPORTED 0x1 +#define NV4_PBUS_PCIPOWER_PME_D2 5 +#define NV4_PBUS_PCIPOWER_PME_D2_SUPPORTED 0x1 +#define NV4_PBUS_PCIPOWER_PME_D3_HOT 6 +#define NV4_PBUS_PCIPOWER_PME_D3_HOT_SUPPORTED 0x1 +#define NV4_PBUS_PCIPOWER_PME_D3_COLD 7 +#define NV4_PBUS_PCIPOWER_PME_D3_COLD_SUPPORTED 0x1 +#define NV4_PBUS_PCIPOWER_STATE_CURRENT 0x1864 +#define NV4_PBUS_PCIPOWER_STATE 0 +#define NV4_PBUS_PCIPOWER_STATE_D3_HOT 0x3 +#define NV4_PBUS_PCIPOWER_STATE_D2 0x2 +#define NV4_PBUS_PCIPOWER_STATE_D1 0x1 +#define NV4_PBUS_PCIPOWER_STATE_D0 0x0 #define NV4_PFIFO_START 0x2000 #define NV4_PFIFO_END 0x3FFF - #define NV4_PFIFO_DELAY_0 0x2040 #define NV4_PFIFO_DELAY_0_WAIT_RETRY 0 #define NV4_PFIFO_DELAY_0_WAIT_RETRY_0 0x0 @@ -3249,6 +3216,7 @@ #define NV4_CIO_START 0x3B0 #define NV4_CIO_END 0x3DF +#define NV4_CIO_SIZE NV4_CIO_END - NV4_CIO_START #define NV4_CIO_INP0 0x3c2 @@ -3403,7 +3371,7 @@ #define NV4_CIO_CRE_TREG_VCNTA_INDEX 0x6 #define NV4_CIO_CRE_TREG_VCNTB_INDEX 0x7 #define NV4_CIO_CRE_DDC_STATUS_INDEX 0x3E -#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F +#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F // Write to i2c for EDID/DDC #define NV4_CIO_CRE_PCI_TO_INDEX 0x40 #define NV4_CIO_CRE_PCI_TO_DELAY 0 @@ -3456,6 +3424,10 @@ #define NV4_PRMVIO_GX_READ_MAP_INDEX 0x4 #define NV4_PRMVIO_GX_MODE_INDEX 0x5 #define NV4_PRMVIO_GX_MISC_INDEX 0x6 +#define NV4_PRMVIO_GX_MISC_BANKED_128K_A0000 0x00 +#define NV4_PRMVIO_GX_MISC_BANKED_64K_A0000 0x04 +#define NV4_PRMVIO_GX_MISC_BANKED_32K_B0000 0x08 +#define NV4_PRMVIO_GX_MISC_BANKED_32K_B8000 0x0C #define NV4_PRMVIO_GX_DONT_CARE_INDEX 0x7 #define NV4_PRMVIO_GX_BIT_MASK_INDEX 0x8 @@ -3922,6 +3894,7 @@ // But this part may not work #define NV4_PRAMIN_START 0x700000 #define NV4_PRAMIN_END 0x7FFFFF +#define NV4_PRAMIN_SIZE 0xFFFFF #define NV4_PRAMIN_CONTEXT_0 ( 0*32+31):( 0*32+ 0) #define NV4_PRAMIN_CONTEXT_1 ( 1*32+31):( 1*32+ 0) @@ -4002,35 +3975,35 @@ // DFB is in BAR1. Access it as VRAM -#define NV4_PEXTDEV_BOOT_0 0x101000 -#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0 -#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1 -#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 2 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x3 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5 -#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6 -#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE 7 -#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x1 -#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x2 -#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x3 -#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11 -#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x0 -#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x1 +#define NV4_PEXTDEV_BOOT_0 0x101000 +#define NV4_STRAP_BUS_SPEED 0 +#define NV4_STRAP_BUS_SPEED_33MHZ 0x0 +#define NV4_STRAP_BUS_SPEED_66MHZ 0x1 +#define NV4_STRAP_SUB_VENDOR 1 +#define NV4_STRAP_SUB_VENDOR_NO_BIOS 0x0 +#define NV4_STRAP_SUB_VENDOR_BIOS 0x1 +#define NV4_STRAP_RAM_TYPE 2 +#define NV4_STRAP_RAM_TYPE_SGRAM_256K 0x0 +#define NV4_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1 +#define NV4_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2 +#define NV4_STRAP_RAM_TYPE_1024K_2BANK 0x3 +#define NV4_STRAP_RAM_WIDTH 4 +#define NV4_STRAP_RAM_WIDTH_64 0x0 +#define NV4_STRAP_RAM_WIDTH_128 0x1 +#define NV4_STRAP_BUS_TYPE 5 +#define NV4_STRAP_BUS_TYPE_PCI 0x0 +#define NV4_STRAP_BUS_TYPE_AGP 0x1 +#define NV4_STRAP_CRYSTAL 6 +#define NV4_STRAP_CRYSTAL_13500K 0x0 +#define NV4_STRAP_CRYSTAL_14318180 0x1 +#define NV4_STRAP_TVMODE 7 +#define NV4_STRAP_TVMODE_SECAM 0x0 +#define NV4_STRAP_TVMODE_NTSC 0x1 +#define NV4_STRAP_TVMODE_PAL 0x2 +#define NV4_STRAP_TVMODE_DISABLED 0x3 +#define NV4_STRAP_OVERWRITE 11 +#define NV4_STRAP_OVERWRITE_DISABLED 0x0 +#define NV4_STRAP_OVERWRITE_ENABLED 0x1 #define NV4_PDAC_START 0x680000 #define NV4_PDAC_END 0x680FFF diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index 41ff22447..c03ac15c9 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -199,6 +199,7 @@ add_library(vid OBJECT # NVidia RIVA TNT/TNT2 - Core nv/nv4/nv4_core.c + nv/nv4/nv4_core_io.c nv/nv4/nv4_core_config.c # Generic diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index 46b6cf9c3..d051a8f15 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -197,9 +197,7 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_write(real_address, val & 0xFF, nv3); - - if (val > 0xFF) - nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); + nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); return; } @@ -227,15 +225,9 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); nv3_svga_write(real_address, val & 0xFF, nv3); - - if (val > 0xFF) - nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); - - if (val > 0xFFFF) - nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3); - - if (val > 0xFFFFFF) - nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3); + nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); + nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3); + nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3); return; } @@ -276,7 +268,7 @@ uint8_t nv3_agp_read(int32_t func, int32_t addr) ret = nv3->nvbase.agp_enabled; break; default: - ret = nv3->pci_config.pci_regs[addr]; + ret = nv3->nvbase.pci_config.pci_regs[addr]; break; } @@ -329,25 +321,25 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) // 66Mhz FSB capable case PCI_REG_COMMAND_L: - ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L]; + ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L]; break; case PCI_REG_COMMAND_H: - ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] & NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back + ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] & NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back break; // pci status register case PCI_REG_STATUS_L: if (nv3->pextdev.straps & NV3_PSTRAPS_BUS_SPEED_66MHZ) - ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE); + ret = (nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE); else - ret = nv3->pci_config.pci_regs[PCI_REG_STATUS_L]; + ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L]; break; case PCI_REG_STATUS_H: - ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); + ret = (nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); break; case NV3_PCI_CFG_REVISION: @@ -400,7 +392,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) break; case NV3_PCI_CFG_ENABLE_VBIOS: - ret = nv3->pci_config.vbios_enabled; + ret = nv3->nvbase.pci_config.vbios_enabled; break; case NV3_AGP_CAPABILITIES_POINTER: @@ -411,7 +403,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) break; case NV3_PCI_CFG_INT_LINE: - ret = nv3->pci_config.int_line; + ret = nv3->nvbase.pci_config.int_line; break; case NV3_PCI_CFG_INT_PIN: @@ -433,7 +425,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START: case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END: - ret = nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)]; + ret = nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)]; break; case NV3_AGP_START ... NV3_AGP_END: @@ -446,7 +438,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) default: // by default just return pci_config.pci_regs - ret = nv3->pci_config.pci_regs[addr]; + ret = nv3->nvbase.pci_config.pci_regs[addr]; break; } @@ -457,7 +449,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) void nv3_agp_write(int32_t func, int32_t addr, uint8_t val) { - nv3->pci_config.pci_regs[addr] = val; + nv3->nvbase.pci_config.pci_regs[addr] = val; switch (addr) { @@ -471,7 +463,6 @@ void nv3_agp_write(int32_t func, int32_t addr, uint8_t val) void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) { - // sanity check if (!nv3) return; @@ -484,29 +475,28 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) nv_log("nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); - nv3->pci_config.pci_regs[addr] = val; + nv3->nvbase.pci_config.pci_regs[addr] = val; switch (addr) { // standard pci command stuff case PCI_REG_COMMAND_L: - nv3->pci_config.pci_regs[PCI_REG_COMMAND_L] = val; + nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L] = val; // actually update the mappings nv3_update_mappings(); break; case PCI_REG_COMMAND_H: - nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] = val; + nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] = val; // actually update the mappings nv3_update_mappings(); break; // pci status register case PCI_REG_STATUS_L: - nv3->pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE); + nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE); break; case PCI_REG_STATUS_H: - nv3->pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); + nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); break; - //TODO: ACTUALLY REMAP THE MMIO AND NV_USER case NV3_PCI_CFG_BAR0_BASE_ADDRESS: nv3->nvbase.bar0_mmio_base = val << 24; nv3_update_mappings(); @@ -520,9 +510,9 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) // make sure we are actually toggling the vbios, not the rom base if (addr == NV3_PCI_CFG_ENABLE_VBIOS) - nv3->pci_config.vbios_enabled = (val & 0x01); + nv3->nvbase.pci_config.vbios_enabled = (val & 0x01); - if (nv3->pci_config.vbios_enabled) + if (nv3->nvbase.pci_config.vbios_enabled) { // First see if we simply wanted to change the VBIOS location @@ -533,8 +523,8 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) { uint32_t old_addr = nv3->nvbase.vbios.mapping.base; // 9bit register - uint32_t new_addr = nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 | - nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16; + uint32_t new_addr = nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 | + nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16; // move it mem_mapping_set_addr(&nv3->nvbase.vbios.mapping, new_addr, 0x8000); @@ -555,7 +545,7 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) } break; case NV3_PCI_CFG_INT_LINE: - nv3->pci_config.int_line = val; + nv3->nvbase.pci_config.int_line = val; break; //bar2-5 are not used and can't be written to case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END: @@ -564,7 +554,7 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) // these are mirrored to the subsystem id and also stored in the ROMBIOS case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START: case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END: - nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val; + nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val; break; case NV3_AGP_START ... NV3_AGP_END: @@ -855,16 +845,14 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) i2c_gpio_set(nv3->nvbase.i2c, scl, sda); break; } - /* [6:0] contains cursorAddr [23:17] */ + /* [6:0] contains cursorAddr [22:16] */ case NV3_CRTC_REGISTER_CURSOR_ADDR0: - nv3->pramdac.cursor_address |= val << 17; //bit7 technically ignored, but nv don't care, so neither do we + nv3->pramdac.cursor_address |= ((val & 0x7F) << 12); //bit7 technically ignored, but nv don't care, so neither do we break; /* [7:2] contains cursorAddr [16:11] */ case NV3_CRTC_REGISTER_CURSOR_ADDR1: - nv3->pramdac.cursor_address |= (val >> 2) << 13; // bit0 and 1 aren't part of the address + nv3->pramdac.cursor_address |= ((val & 0xF8) << 4); // bit0 and 1 aren't part of the address break; - - } /* Recalculate the timings if we actually changed them @@ -1130,7 +1118,6 @@ void nv3_init_mappings_mmio(void) nv3_ramin_write32, NULL, MEM_MAPPING_EXTERNAL, nv3); - mem_mapping_add(&nv3->nvbase.ramin_mapping_mirror, 0, 0, nv3_ramin_read8, nv3_ramin_read16, @@ -1140,14 +1127,11 @@ void nv3_init_mappings_mmio(void) nv3_ramin_write32, NULL, MEM_MAPPING_EXTERNAL, nv3); - } void nv3_init_mappings_svga(void) { nv_log("Initialising SVGA core memory mapping\n"); - - // setup the svga mappings mem_mapping_add(&nv3->nvbase.framebuffer_mapping, 0, 0, nv3_dfb_read8, @@ -1191,20 +1175,20 @@ void nv3_update_mappings(void) nv_log("\nMemory Mapping Config Change:\n"); - (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); + (nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); io_removehandler(0x03c0, 0x0020, nv3_svga_read, NULL, NULL, nv3_svga_write, NULL, NULL, nv3); - if (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) + if (nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) io_sethandler(0x03c0, 0x0020, nv3_svga_read, NULL, NULL, nv3_svga_write, NULL, NULL, nv3); - if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) + if (!(nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) { nv_log("The memory was turned off, not much is going to happen.\n"); return; @@ -1412,8 +1396,8 @@ void* nv3_init(const device_t *info) nv3_init_mappings(); // make us actually exist - nv3->pci_config.int_line = 0xFF; // per datasheet - nv3->pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM; + nv3->nvbase.pci_config.int_line = 0xFF; // per datasheet + nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM; // svga is done, so now initialise the real gpu diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c index d020e44e6..58aba93b1 100644 --- a/src/video/nv/nv4/nv4_core.c +++ b/src/video/nv/nv4/nv4_core.c @@ -6,7 +6,7 @@ * * This file is part of the 86Box distribution. * - * NV3 bringup and device emulation. + * NV4 bringup and device emulation. * * * Authors: Connor Hyde, I need a better email address ;^) @@ -29,9 +29,178 @@ nv4_t* nv4; +// Initialise the MMIO mappings +void nv4_init_mappings_mmio(void) +{ + nv_log("Initialising MMIO mapping\n"); + + // 0x0 - 1000000: regs + // 0x1000000-2000000 + + // initialize the mmio mapping + mem_mapping_add(&nv4->nvbase.mmio_mapping, 0, 0, + nv4_mmio_read8, + nv4_mmio_read16, + nv4_mmio_read32, + nv4_mmio_write8, + nv4_mmio_write16, + nv4_mmio_write32, + NULL, MEM_MAPPING_EXTERNAL, nv4); + + // initialize the mmio mapping + mem_mapping_add(&nv4->nvbase.ramin_mapping, 0, 0, + nv4_ramin_read8, + nv4_ramin_read16, + nv4_ramin_read32, + nv4_ramin_write8, + nv4_ramin_write16, + nv4_ramin_write32, + NULL, MEM_MAPPING_EXTERNAL, nv4); + +} + +void nv4_init_mappings_svga(void) +{ + nv_log("Initialising SVGA core memory mapping\n"); + // setup the svga mappings + mem_mapping_add(&nv4->nvbase.framebuffer_mapping, 0, 0, + nv4_dfb_read8, + nv4_dfb_read16, + nv4_dfb_read32, + nv4_dfb_write8, + nv4_dfb_write16, + nv4_dfb_write32, + nv4->nvbase.svga.vram, 0, &nv4->nvbase.svga); + + // the SVGA/LFB mapping is also mirrored + mem_mapping_add(&nv4->nvbase.framebuffer_mapping_mirror, 0, 0, + nv4_dfb_read8, + nv4_dfb_read16, + nv4_dfb_read32, + nv4_dfb_write8, + nv4_dfb_write16, + nv4_dfb_write32, + nv4->nvbase.svga.vram, 0, &nv4->nvbase.svga); + + io_sethandler(NV4_CIO_START, NV4_CIO_SIZE, + nv4_svga_read, NULL, NULL, + nv4_svga_write, NULL, NULL, + nv4); +} + +void nv4_init_mappings(void) +{ + nv4_init_mappings_mmio(); + nv4_init_mappings_svga(); +} + +// Updates the mappings after initialisation. +void nv4_update_mappings(void) +{ + // sanity check + if (!nv4) + return; + + // setting this to 0 doesn't seem to disable it, based on the datasheet + + nv_log("\nMemory Mapping Config Change:\n"); + + (nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); + + io_removehandler(NV4_CIO_START, NV4_CIO_SIZE, + nv4_svga_read, NULL, NULL, + nv4_svga_write, NULL, NULL, + nv4); + + if (nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) + io_sethandler(NV4_CIO_START, NV4_CIO_SIZE, + nv4_svga_read, NULL, NULL, + nv4_svga_write, NULL, NULL, + nv4); + + if (!(nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) + { + nv_log("The memory was turned off, not much is going to happen.\n"); + return; + } + + // turn off bar0 and bar1 by defualt + mem_mapping_disable(&nv4->nvbase.mmio_mapping); + mem_mapping_disable(&nv4->nvbase.framebuffer_mapping); + mem_mapping_disable(&nv4->nvbase.framebuffer_mapping_mirror); + mem_mapping_disable(&nv4->nvbase.ramin_mapping); + + // Setup BAR0 (MMIO) + + nv_log("BAR0 (MMIO Base) = 0x%08x\n", nv4->nvbase.bar0_mmio_base); + + if (nv4->nvbase.bar0_mmio_base) + { + mem_mapping_set_addr(&nv4->nvbase.mmio_mapping, nv4->nvbase.bar0_mmio_base, NV4_MMIO_SIZE); + mem_mapping_set_addr(&nv4->nvbase.ramin_mapping, nv4->nvbase.bar0_mmio_base + NV4_PRAMIN_START, NV4_PRAMIN_SIZE); + } + + // if this breaks anything, remove it + nv_log("BAR1 (Linear Framebuffer & VRAM) = 0x%08x\n", nv4->nvbase.bar1_lfb_base); + + if (nv4->nvbase.bar1_lfb_base) + { + if (nv4->nvbase.vram_amount == NV4_VRAM_SIZE_16MB) + { + // we don't need this one in the case of 16mb, + mem_mapping_disable(&nv4->nvbase.framebuffer_mapping_mirror); + mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping, nv4->nvbase.bar1_lfb_base, NV4_VRAM_SIZE_16MB); + } + else if (nv4->nvbase.vram_amount == NV4_VRAM_SIZE_8MB) + { + mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping, nv4->nvbase.bar1_lfb_base, NV4_VRAM_SIZE_8MB); + mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping_mirror, nv4->nvbase.bar1_lfb_base + NV4_VRAM_SIZE_8MB, NV4_VRAM_SIZE_8MB); + } + } + + // Did we change the banked SVGA mode? + switch (nv4->nvbase.svga.gdcreg[NV4_PRMVIO_GX_MISC_INDEX] & 0x0c) + { + case NV4_PRMVIO_GX_MISC_BANKED_128K_A0000: + nv_log("SVGA Banked Mode = 128K @ A0000h\n"); + mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000 + nv4->nvbase.svga.banked_mask = 0x1FFFF; + break; + case NV4_PRMVIO_GX_MISC_BANKED_64K_A0000: + nv_log("SVGA Banked Mode = 64K @ A0000h\n"); + mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000 + nv4->nvbase.svga.banked_mask = 0xFFFF; + break; + case NV4_PRMVIO_GX_MISC_BANKED_32K_B0000: + nv_log("SVGA Banked Mode = 32K @ B0000h\n"); + mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000 + nv4->nvbase.svga.banked_mask = 0x7FFF; + break; + case NV4_PRMVIO_GX_MISC_BANKED_32K_B8000: + nv_log("SVGA Banked Mode = 32K @ B8000h\n"); + mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000 + nv4->nvbase.svga.banked_mask = 0x7FFF; + break; + } +} + + void nv4_init() { nv4 = calloc(1, sizeof(nv4_t)); + + if (!nv4->nvbase.vram_amount) + nv4->nvbase.vram_amount = device_get_config_int("vram_size"); + + /* Set log device name based on card model */ + const char* log_device_name = "NV4"; + + if (device_get_config_int("nv_debug_fulllog")) + nv4->nvbase.log = log_open("NV4"); + else + nv4->nvbase.log = log_open_cyclic("NV4"); + + nv_log_set_device(nv4->nvbase.log); } void* nv4_init_stb4400(const device_t *info) @@ -71,7 +240,7 @@ int32_t nv4_available(void) return (rom_present(NV4_VBIOS_STB_REVA)); } -// NV3 (RIVA 128) +// NV4 (RIVA 128) // AGP // 8MB or 16MB VRAM const device_t nv4_device_agp = diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c new file mode 100644 index 000000000..a7fe0d0c8 --- /dev/null +++ b/src/video/nv/nv4/nv4_core_io.c @@ -0,0 +1,1310 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV4 I/O, including Real-Mode Access (RMA), memory mapping, PCI, AGP, SVGA and MMIO via PCI BARs + * + * MMIO dumps are available at: https://nvwiki.org/misc/NVDumps/ + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ + + +// Prototypes for functions only used in this translation unit + +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv4.h> + + +void nv4_init_mappings_mmio(void); +void nv4_init_mappings_svga(void); +bool nv4_is_svga_redirect_address(uint32_t addr); + +uint8_t nv4_svga_read(uint16_t addr, void* priv); +void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); + + +uint32_t nv4_mmio_arbitrate_read(uint32_t addr) +{ + +} + +void nv4_mmio_arbitrate_write(uint32_t addr, uint32_t val) +{ + +} + +// Determine if this address needs to be redirected to the SVGA subsystem. + +bool nv4_is_svga_redirect_address(uint32_t addr) +{ + return (addr >= NV4_PRMVIO_START && addr <= NV4_PRMVIO_END) // VGA + || (addr >= NV4_PRMCIO_START && addr <= NV4_PRMCIO_END) // CRTC + || (addr >= NV4_USER_DAC_START && addr <= NV4_USER_DAC_END); // Note: 6813c6-6813c9 are ignored somewhere else +} + +uint8_t nv4_rma_read(uint16_t addr) +{ + addr &= 0xFF; + uint32_t real_final_address = 0x0; + uint8_t ret = 0x0; + + switch (addr) + { + // signature so you know reads work + case 0x00: + ret = NV4_PRMIO_RMA_ID_CODE_VALID & 0xFF; + break; + case 0x01: + ret = (NV4_PRMIO_RMA_ID_CODE_VALID >> 8) & 0xFF; + break; + case 0x02: + ret = (NV4_PRMIO_RMA_ID_CODE_VALID >> 16) & 0xFF; + break; + case 0x03: + ret = (NV4_PRMIO_RMA_ID_CODE_VALID >> 24) & 0xFF; + break; + case 0x08 ... 0x0B: + // reads must be dword aligned + real_final_address = (nv4->pbus.rma.addr + (addr & 0x03)); + + if (nv4->pbus.rma.addr < NV4_MMIO_SIZE) + ret = nv4_mmio_read8(real_final_address, NULL); + else + { + /* Do we need to read RAMIN here? */ + ret = nv4->nvbase.svga.vram[real_final_address - NV4_MMIO_SIZE] & (nv4->nvbase.svga.vram_max - 1); + } + + // log current location for vbios RE + nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + addr, real_final_address, ret); + + break; + } + + return ret; +} + +// Implements a 32-bit write using 16 bit port number +void nv4_rma_write(uint16_t addr, uint8_t val) +{ + // addresses are in reality 8bit so just mask it to be safe + addr &= 0xFF; + + // format: + // 0x00 ID + // 0x04 Pointer to data + // 0x08 Data port(?) + // 0x0B Data - 32bit. SENT IN THE RIGHT ORDER FOR ONCE WAHOO! + // 0x10 Increment (?) data - implemented the same as data for now + + if (addr < 0x08) + { + switch (addr % 0x04) + { + case 0x00: // lowest byte + nv4->pbus.rma.addr &= ~0xff; + nv4->pbus.rma.addr |= val; + break; + case 0x01: // 2nd highest byte + nv4->pbus.rma.addr &= ~0xff00; + nv4->pbus.rma.addr |= (val << 8); + break; + case 0x02: // 3rd highest byte + nv4->pbus.rma.addr &= ~0xff0000; + nv4->pbus.rma.addr |= (val << 16); + break; + case 0x03: // 4th highest byte + nv4->pbus.rma.addr &= ~0xff000000; + nv4->pbus.rma.addr |= (val << 24); + break; + } + } + // Data to send to MMIO + else + { + switch (addr % 0x04) + { + case 0x00: // lowest byte + nv4->pbus.rma.data &= ~0xff; + nv4->pbus.rma.data |= val; + break; + case 0x01: // 2nd highest byte + nv4->pbus.rma.data &= ~0xff00; + nv4->pbus.rma.data |= (val << 8); + break; + case 0x02: // 3rd highest byte + nv4->pbus.rma.data &= ~0xff0000; + nv4->pbus.rma.data |= (val << 16); + break; + case 0x03: // 4th highest byte + nv4->pbus.rma.data &= ~0xff000000; + nv4->pbus.rma.data |= (val << 24); + + nv_log_verbose_only("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + addr, nv4->pbus.rma.addr, nv4->pbus.rma.data); + + if (nv4->pbus.rma.addr < NV4_MMIO_SIZE) + nv4_mmio_write32(nv4->pbus.rma.addr, nv4->pbus.rma.data, NULL); + else // failsafe code, i don't think you will ever write outside of VRAM? + { + uint32_t* vram_32 = (uint32_t*)nv4->nvbase.svga.vram; + vram_32[(nv4->pbus.rma.addr - NV4_MMIO_SIZE) >> 2] = nv4->pbus.rma.data; + } + + + break; + } + } + + if (addr & 0x10) + nv4->pbus.rma.addr += 0x04; // Alignment +} + + + +// All MMIO regs are 32-bit i believe internally +// so we have to do some munging to get this to read + +// Read 8-bit MMIO +uint8_t nv4_mmio_read8(uint32_t addr, void* priv) +{ + uint32_t ret = 0x00; + + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + addr &= 0xFFFFFF; + + // We need to specifically exclude this particular set of registers + // so we can write the 4/8bpp CLUT + if (addr >= NV4_USER_DAC_PALETTE_START && addr <= NV4_USER_DAC_PALETTE_END) + { + // Throw directly into PRAMDAC + return nv4_mmio_arbitrate_read(addr); + } + + if (nv4_is_svga_redirect_address(addr)) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + ret = nv4_svga_read(real_address, nv4); + + nv_log_verbose_only("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + + return ret; + } + + // see if unaligned reads are a problem + ret = nv4_mmio_read32(addr, priv); + return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFF); +} + +// Read 16-bit MMIO +uint16_t nv4_mmio_read16(uint32_t addr, void* priv) +{ + uint32_t ret = 0x00; + + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + addr &= 0xFFFFFF; + + if (nv4_is_svga_redirect_address(addr)) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + ret = nv4_svga_read(real_address, nv4) + | (nv4_svga_read(real_address + 1, nv4) << 8); + + nv_log_verbose_only("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + + return ret; + } + + ret = nv4_mmio_read32(addr, priv); + return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFFFF); +} + +// Read 32-bit MMIO +uint32_t nv4_mmio_read32(uint32_t addr, void* priv) +{ + uint32_t ret = 0x00; + + // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. + addr &= 0xFFFFFF; + + if (nv4_is_svga_redirect_address(addr)) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + ret = nv4_svga_read(real_address, nv4) + | (nv4_svga_read(real_address + 1, nv4) << 8) + | (nv4_svga_read(real_address + 2, nv4) << 16) + | (nv4_svga_read(real_address + 3, nv4) << 24); + + nv_log_verbose_only("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); + + return ret; + } + + ret = nv4_mmio_arbitrate_read(addr); + + return ret; +} + +// Write 8-bit MMIO +void nv4_mmio_write8(uint32_t addr, uint8_t val, void* priv) +{ + addr &= 0xFFFFFF; + + // We need to specifically exclude this particular set of registers + // so we can write the 4/8bpp CLUT + if (addr >= NV4_USER_DAC_PALETTE_START && addr <= NV4_USER_DAC_PALETTE_END) + { + // Throw directly into PRAMDAC + nv4_mmio_arbitrate_write(addr, val); + return; + } + + // This is weitek vga stuff + // If we need to add more of these we can convert these to a switch statement + if (nv4_is_svga_redirect_address(addr)) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + nv_log_verbose_only("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + + nv4_svga_write(real_address, val & 0xFF, nv4); + + return; + } + + // overwrite first 8bits of a 32 bit value + uint32_t new_val = nv4_mmio_read32(addr, NULL); + + new_val &= (~0xFF << (addr & 3) << 3); + new_val |= (val << ((addr & 3) << 3)); + + nv4_mmio_write32(addr, new_val, priv); +} + +// Write 16-bit MMIO +void nv4_mmio_write16(uint32_t addr, uint16_t val, void* priv) +{ + addr &= 0xFFFFFF; + + // This is weitek vga stuff + if (nv4_is_svga_redirect_address(addr)) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + + nv4_svga_write(real_address, val & 0xFF, nv4); + nv4_svga_write(real_address + 1, (val >> 8) & 0xFF, nv4); + + return; + } + + // overwrite first 16bits of a 32 bit value + uint32_t new_val = nv4_mmio_read32(addr, NULL); + + new_val &= (~0xFFFF << (addr & 3) << 3); + new_val |= (val << ((addr & 3) << 3)); + + nv4_mmio_write32(addr, new_val, priv); +} + +// Write 32-bit MMIO +void nv4_mmio_write32(uint32_t addr, uint32_t val, void* priv) +{ + addr &= 0xFFFFFF; + + // This is weitek vga stuff + if (nv4_is_svga_redirect_address(addr)) + { + // svga writes are not logged anyway rn + uint32_t real_address = addr & 0x3FF; + + nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); + + nv4_svga_write(real_address, val & 0xFF, nv4); + nv4_svga_write(real_address + 1, (val >> 8) & 0xFF, nv4); + nv4_svga_write(real_address + 2, (val >> 16) & 0xFF, nv4); + nv4_svga_write(real_address + 3, (val >> 24) & 0xFF, nv4); + + return; + } + + nv4_mmio_arbitrate_write(addr, val); +} + +// PCI stuff +// BAR0 Pointer to MMIO space & RAMIN +// BAR1 Pointer to Linear Framebuffer +uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv) +{ + uint8_t ret = 0x00; + + // sanity check + if (!nv4) + return ret; + + // Convert to the MMIO addresses + if (addr <= 0xFF) + addr += 0x1800; + + // Anything not listed is 0x00 + // PCI values extracted from https://nvwiki.org/misc/NVDumps/RivaMobileNV4/Nv4win_HL/nv4bar0.bin + // STB V4400 (running Half-Life) + switch (addr) + { + // Get the pci vendor id.. + + case NV4_PBUS_PCI_VENDOR_ID: + ret = (NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA & 0xFF); + break; + + case NV4_PBUS_PCI_VENDOR_ID + 1: // all access 8bit + ret = (NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA >> 8); + break; + + // device id + + case NV4_PBUS_PCI_DEVICE_ID: + ret = (NV_PCI_DEVICE_NV4 & 0xFF); + break; + + case NV4_PBUS_PCI_DEVICE_ID + 1: + ret = (NV_PCI_DEVICE_NV4 >> 8); + break; + + // various capabilities enabled by default + // IO space enabled + // Memory space enabled + // Bus master enabled + // Write/inval enabled + // Pal snoop enabled + // Capabiliies list enabled + // 66Mhz FSB capable + + case NV4_PBUS_PCI_COMMAND: + ret = nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L]; + break; + // COMMAND_L not used + + // pci status register + case NV4_PBUS_PCI_STATUS: + if (nv4->straps + & NV4_STRAP_BUS_SPEED_66MHZ) + ret = (nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] | NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE); + else + ret = nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L]; + + break; + + case NV4_PBUS_PCI_STATUS_2: + ret = (nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST << NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING); + break; + + case NV4_PBUS_PCI_REVISION_ID: + ret = nv4->nvbase.gpu_revision; // Commercial release + break; + + case PCI_REG_PROG_IF: + ret = 0x00; + break; + + // We only need to return 0x30 since the VGA class code is 0x30000 + case NV4_PBUS_PCI_CLASS_CODE: + ret = (NV4_PBUS_PCI_CLASS_CODE_VGA) >> 12; // CLASS_CODE_VGA + break; + + + case NV4_PBUS_PCI_LATENCY_TIMER: + case NV4_PBUS_PCI_HEADER_TYPE: + ret = 0x00; + break; + + // BARs are marked as prefetchable per the datasheet + case NV4_PBUS_PCI_BAR0_INFO: + case NV4_PBUS_PCI_BAR1_INFO: + // only bit that matters is bit 3 (prefetch bit) + ret = (NV4_PBUS_PCI_BAR_PREFETCHABLE_MERGABLE << NV4_PBUS_PCI_BAR_PREFETCHABLE); + break; + + // MMIO base address + case NV4_PBUS_PCI_BAR0_BASE_31_TO_24: + ret = nv4->nvbase.bar0_mmio_base >> 24;//8bit value + break; + + case NV4_PBUS_PCI_BAR1_BASE_31_TO_24: + ret = nv4->nvbase.bar1_lfb_base >> 24; //8bit value + break; + + case NV4_PBUS_PCI_ROM: + ret = nv4->nvbase.pci_config.vbios_enabled; + break; + + case NV4_PBUS_PCI_INTR_LINE: + ret = nv4->nvbase.pci_config.int_line; + break; + + case NV4_PBUS_PCI_INTR_PIN: + ret = PCI_INTA; + break; + + // + // Capabilities pointers + // + + case NV4_PBUS_PCI_NEXT_PTR: + ret = NV4_PBUS_PCI_CAP_PTR_POWER_MGMT; + break; + + case NV4_PBUS_PCIPOWER_NEXT_PTR: + ret = NV4_PBUS_PCI_CAP_PTR_AGP; + break; + + // AGP is the end of the chain + case NV4_PBUS_AGP_NEXT_PTR: + ret = 0x00; + break; + + case NV4_PBUS_PCI_MAX_LAT: + ret = NV4_PBUS_PCI_MAX_LAT_250NS; + break; + + // these map to the subsystem + // todo: port this bugfix to NV4 + case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE: + case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE + 1: + case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE: + case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE + 1: + ret = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_SUBSYSTEM_ID + (addr & 0x03)]; + break; + case NV4_PBUS_AGP_CAPABILITIES: + ret = NV4_PBUS_AGP_CAPABILITY_AGP; // AGP capable device + break; + case NV4_PBUS_AGP_REV: + ret = (NV4_PBUS_AGP_REV_MAJOR_1 << NV4_PBUS_AGP_REV_MAJOR) | NV4_PBUS_AGP_REV_MINOR; + break; + case NV4_PBUS_AGP_STATUS_RATE: + ret = NV4_PBUS_AGP_STATUS_RATE_1X_AND_2X; + break; + case NV4_PBUS_AGP_STATUS_SBA: + ret = (NV4_PBUS_AGP_STATUS_SBA_STATUS_CAPABLE) << NV4_PBUS_AGP_STATUS_SBA_STATUS; // Sideband is supported on NV4 + break; + case NV4_PBUS_AGP_STATUS_RQ: + ret = NV4_PBUS_AGP_STATUS_RQ_16; + break; + case NV4_PBUS_AGP_COMMAND_2: + ret = (nv4->nvbase.agp_enabled) << NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED + | (nv4->nvbase.agp_sba_enabled) << NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED; + break; + default: // by default just return pci_config.pci_regs (default value for nonwritten registers is 0x00) + ret = nv4->nvbase.pci_config.pci_regs[addr]; + break; + + } + + nv_log("nv4_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret); + return ret; +} + + +// nv4 pci/agp write +void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) +{ + // sanity check + if (!nv4) + return; + + // Convert to the MMIO addresses + if (addr <= 0xFF) + addr += 0x1800; + // some addresses are not writable so can't have any effect and can't be allowed to be modified using this code + // as an example, only the most significant byte of the PCI BARs can be modified + if (addr == NV4_PBUS_PCI_BAR0_UNUSED1 || addr == NV4_PBUS_PCI_BAR0_UNUSED2 + && addr == NV4_PBUS_PCI_BAR1_UNUSED1 || addr == NV4_PBUS_PCI_BAR1_UNUSED2) + return; + + nv_log("nv4_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); + + nv4->nvbase.pci_config.pci_regs[addr] = val; + + switch (addr) + { + // standard pci command stuff + case PCI_REG_COMMAND_L: + nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L] = val; + // actually update the mappings + nv4_update_mappings(); + break; + case PCI_REG_COMMAND_H: + nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] = val; + // actually update the mappings + nv4_update_mappings(); + break; + // pci status register + case PCI_REG_STATUS_L: + nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE << NV4_PBUS_PCI_STATUS_66MHZ); + break; + case PCI_REG_STATUS_H: + nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST << NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING); + break; + //TODO: ACTUALLY REMAP THE MMIO AND NV_USER + case NV4_PBUS_PCI_BAR0_BASE_31_TO_24: + nv4->nvbase.bar0_mmio_base = val << 24; + nv4_update_mappings(); + break; + case NV4_PBUS_PCI_BAR1_BASE_31_TO_24: + nv4->nvbase.bar1_lfb_base = val << 24; + nv4_update_mappings(); + break; + case NV4_PBUS_PCI_ROM: + case NV4_PBUS_PCI_ROM_BASE: + + // make sure we are actually toggling the vbios, not the rom base + if (addr == NV4_PBUS_PCI_ROM) + nv4->nvbase.pci_config.vbios_enabled = (val & 0x01); + + if (nv4->nvbase.pci_config.vbios_enabled) + { + // First see if we simply wanted to change the VBIOS location + + // Enable it in case it was disabled before + mem_mapping_enable(&nv4->nvbase.vbios.mapping); + + if (addr != NV4_PBUS_PCI_ROM) + { + uint32_t old_addr = nv4->nvbase.vbios.mapping.base; + // 9bit register + uint32_t new_addr = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM + 1] << 24 | + nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM] << 16; + + // move it + mem_mapping_set_addr(&nv4->nvbase.vbios.mapping, new_addr, 0x8000); + + nv_log("...i like to move it move it (VBIOS Relocation) 0x%04x -> 0x%04x\n", old_addr, new_addr); + + } + else + { + nv_log("...VBIOS Enable\n"); + } + } + else + { + nv_log("...VBIOS Disable\n"); + mem_mapping_disable(&nv4->nvbase.vbios.mapping); + + } + break; + case NV4_PBUS_PCI_INTR_LINE: + nv4->nvbase.pci_config.int_line = val; + break; + // these are mirrored to the subsystem id and also stored in the ROMBIOS + //todo: port to pci + case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE: + case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE + 1: + case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE: + case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE + 1: + nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_SUBSYSTEM_ID + (addr & 0x03)] = val; + break; + case NV4_PBUS_AGP_COMMAND_2: + nv4->nvbase.agp_enabled = (val >> NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED) & 0x01; + nv4->nvbase.agp_sba_enabled = (val >> NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED) & 0x01; + break; + default: + break; + } +} + + +// +// SVGA functions +// +void nv4_recalc_timings(svga_t* svga) +{ + // sanity check + if (!nv4) + return; + + + nv4_t* nv4 = (nv4_t*)svga->priv; + + // TODO: Everything, this code sucks, incl. NV4_PRAMDAC_GENERAL_CONTROL_BPC and the OFFSET register + uint32_t pixel_mode = svga->crtc[NV4_CIO_CRE_PIXEL_INDEX] & 0x03; + + svga->memaddr_latch += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0x1F) << 16; + + /* Turn off override if we are in VGA mode */ + svga->override = !(pixel_mode == NV4_CIO_CRE_PIXEL_FORMAT_VGA); + + /* NOTE: The RIVA 128 draws in a way almost completely separate to any other 86Box GPU. + + Basically, we only blit to buffer32 when something changes and we don't even bother using a timer. We only render when there is something to actually render. + + This is because there is no linear relationship between the contents of VRAM and the contents of the display which 86box's SVGA subsystem cannot tolerate. + In fact, the position in VRAM and pitch can be changed at any time via an NV_IMAGE_IN_MEMORY object. + + Therefore, we need to completely bypass it using svga->override and draw our own rendering functions. This allows us to use a neat optimisation trick + to only ever actually draw when we need to do something. This shouldn't be a problem in games, because the drivers will read the current refresh rate from + the Windows settings, and then, just submit objects at that pace for anything that changes on the screen. + */ + + // Set the pixel mode + switch (pixel_mode) + { + case NV4_CIO_CRE_PIXEL_FORMAT_8BPP: + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 1; // ????? + svga->bpp = 8; + svga->lowres = 0; + svga->map8 = svga->pallook; + break; + case NV4_CIO_CRE_PIXEL_FORMAT_16BPP: + /* This is some sketchy shit that is an attempt at an educated guess + at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, + this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */ + if ((svga->crtc[NV4_CIO_CR_VRS_INDEX] >> 1) & 0x01) + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 2; + else + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; + + // 15bpp mode is removed on NV4 + // TODO: Not svga + svga->bpp = 16; + svga->lowres = 0; + + break; + case NV4_CIO_CRE_PIXEL_FORMAT_32BPP: + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; + + svga->bpp = 32; + svga->lowres = 0; + //svga->render = nv4_render_32bpp; + break; + } + + + if (((svga->miscout >> 2) & 2) == 2) + { + // set clocks + //nv4_pramdac_set_pixel_clock(); + //nv4_pramdac_set_vram_clock(); + } +} + +void nv4_speed_changed(void* priv) +{ + // sanity check + if (!nv4) + return; + + nv4_recalc_timings(&nv4->nvbase.svga); +} + +// Force Redraw +// Reset etc. +void nv4_force_redraw(void* priv) +{ + // sanity check + if (!nv4) + return; + + nv4->nvbase.svga.fullchange = changeframecount; +} + +// CHECK that ramin is the smae as nv4 + +// Read 8-bit ramin +uint8_t nv4_ramin_read8(uint32_t addr, void* priv) +{ + if (!nv4) return 0x00; + + addr &= (nv4->nvbase.svga.vram_max - 1); + uint32_t raw_addr = addr; // saved after and + + addr ^= (nv4->nvbase.svga.vram_max - 0x10); + + uint32_t val = 0x00; + + //if (!nv4_ramin_arbitrate_read(addr, &val)) // Oh well + //{ + val = (uint8_t)nv4->nvbase.svga.vram[addr]; + nv_log_verbose_only("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + //} + + return (uint8_t)val; +} + +// Read 16-bit ramin +uint16_t nv4_ramin_read16(uint32_t addr, void* priv) +{ + if (!nv4) return 0x00; + + addr &= (nv4->nvbase.svga.vram_max - 1); + + // why does this not work in one line + svga_t* svga = &nv4->nvbase.svga; + uint16_t* vram_16bit = (uint16_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (nv4->nvbase.svga.vram_max - 0x10); + addr >>= 1; // what + + uint32_t val = 0x00; + + //if (!nv4_ramin_arbitrate_read(addr, &val)) + //{ + val = (uint16_t)vram_16bit[addr]; + nv_log_verbose_only("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); + //} + + return val; +} + +// Read 32-bit ramin +uint32_t nv4_ramin_read32(uint32_t addr, void* priv) +{ + if (!nv4) + return 0x00; + + addr &= (nv4->nvbase.svga.vram_max - 1); + + // why does this not work in one line + uint32_t* vram_32bit = (uint32_t*)nv4->nvbase.svga.vram; + uint32_t raw_addr = addr; // saved after and logged + + addr ^= (nv4->nvbase.svga.vram_max - 0x10); + addr >>= 2; // what + + uint32_t val = 0x00; + + //if (!nv4_ramin_arbitrate_read(addr, &val)) + //{ + val = vram_32bit[addr]; + nv_log_verbose_only("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr); + //} + + return val; +} + +// Write 8-bit ramin +void nv4_ramin_write8(uint32_t addr, uint8_t val, void* priv) +{ + if (!nv4) return; + + addr &= (nv4->nvbase.svga.vram_max - 1); + uint32_t raw_addr = addr; // saved after and + + // Structures in RAMIN are stored from the bottom of vram up in reverse order + // this can be explained without bitwise math like so: + // real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) + // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv4t only and 2mb...i haven't found a 22mb card) + addr ^= (nv4->nvbase.svga.vram_max - 0x10); + + uint32_t val32 = (uint32_t)val; + + //if (!nv4_ramin_arbitrate_write(addr, val32)) + //{ + nv4->nvbase.svga.vram[addr] = val; + nv_log_verbose_only("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); + //} +} + +// Write 16-bit ramin +void nv4_ramin_write16(uint32_t addr, uint16_t val, void* priv) +{ + if (!nv4) return; + + addr &= (nv4->nvbase.svga.vram_max - 1); + + // why does this not work in one line + svga_t* svga = &nv4->nvbase.svga; + uint16_t* vram_16bit = (uint16_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (nv4->nvbase.svga.vram_max - 0x10); + addr >>= 1; // what + + uint32_t val32 = (uint32_t)val; + + //if (!nv4_ramin_arbitrate_write(addr, val32)) + //{ + vram_16bit[addr] = val; + nv_log_verbose_only("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); + //} + + +} + +// Write 32-bit ramin +void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv) +{ + if (!nv4) return; + + addr &= (nv4->nvbase.svga.vram_max - 1); + + // why does this not work in one line + svga_t* svga = &nv4->nvbase.svga; + uint32_t* vram_32bit = (uint32_t*)svga->vram; + uint32_t raw_addr = addr; // saved after and + + addr ^= (nv4->nvbase.svga.vram_max - 0x10); + addr >>= 2; // what + + //if (!nv4_ramin_arbitrate_write(addr, val)) + //{ + vram_32bit[addr] = val; + nv_log_verbose_only("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); + //} +} + +// Read from SVGA core memory +uint8_t nv4_svga_read(uint16_t addr, void* priv) +{ + // CR = CRTC Controller + // CRE = CRTC Controller Extended (weitek) + + nv4_t* nv4 = (nv4_t*)priv; + + uint8_t ret = 0x00; + + // sanity check + if (!nv4) + return ret; + + // If we need to RMA from GPU MMIO, go do that + if (addr >= NV4_RMA_REGISTER_START + && addr <= NV4_RMA_REGISTER_END) + { + if (!(nv4->pbus.rma.mode & 0x01)) + return ret; + + // must be dword aligned + uint32_t real_rma_read_addr = ((nv4->pbus.rma.mode & 0x0E) << 1) + (addr & 0x03); + ret = nv4_rma_read(real_rma_read_addr); + return ret; + } + + // mask off b0/d0 registers + if ((((addr & 0xFFF0) == 0x3D0 + || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) + && !(nv4->nvbase.svga.miscout & 1)) + addr ^= 0x60; + + switch (addr) + { + // Alias for "get current SVGA CRTC register ID" + case NV4_CIO_CRX_COLOR: + ret = nv4->nvbase.svga.crtcreg; + break; + case NV4_CIO_CR_COLOR: + // Support the extended NVIDIA CRTC register range + switch (nv4->nvbase.svga.crtcreg) + { + case NV4_CIO_CRE_RL0_INDEX: + ret = nv4->nvbase.svga.displine & 0xFF; + break; + /* Is rl1?*/ + case NV4_CIO_CRE_RL1_INDEX: + ret = (nv4->nvbase.svga.displine >> 8) & 7; + break; + case NV4_CIO_CRE_DDC_STATUS_INDEX: + ret = i2c_gpio_get_sda(nv4->nvbase.i2c) << 3 + | i2c_gpio_get_scl(nv4->nvbase.i2c) << 2; + + break; + default: + ret = nv4->nvbase.svga.crtc[nv4->nvbase.svga.crtcreg]; + } + break; + default: + ret = svga_in(addr, &nv4->nvbase.svga); + break; + } + + return ret; //TEMP +} + +// Write to SVGA core memory +void nv4_svga_write(uint16_t addr, uint8_t val, void* priv) +{ + // sanity check + if (!nv4) + return; + + // If we need to RMA to GPU MMIO, go do that + if (addr >= NV4_RMA_REGISTER_START + && addr <= NV4_RMA_REGISTER_END) + { + // we don't need to store these registers... + nv4->pbus.rma.rma_regs[addr & 3] = val; + + if (!(nv4->pbus.rma.mode & 0x01)) // we are halfway through sending something + return; + + uint32_t real_rma_write_addr = ((nv4->pbus.rma.mode & (0x0E)) << 1) + (addr & 0x03); + + nv4_rma_write(real_rma_write_addr, nv4->pbus.rma.rma_regs[addr & 0x03]); + return; + } + + // mask off b0/d0 registers + if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) + && addr < 0x3de) + && !(nv4->nvbase.svga.miscout & 1))//miscout bit 7 controls mappping + addr ^= 0x60; + + uint8_t crtcreg = nv4->nvbase.svga.crtcreg; + uint8_t old_val = 0x00; + + // todo: + // Pixel formats (8bit vs 555 vs 565) + // VBE 3.0? + + switch (addr) + { + case NV4_CIO_CRX_COLOR: + // real mode access to GPU MMIO space... + nv4->nvbase.svga.crtcreg = val; + break; + // support the extended crtc regs and debug this out + case NV4_CIO_CR_COLOR: + + // Implements the VGA Protect register + if ((nv4->nvbase.svga.crtcreg < NV4_CIO_CR_OVL_INDEX) && (nv4->nvbase.svga.crtc[NV4_CIO_CR_VRE_INDEX] & 0x80)) + return; + + // Ignore certain bits when VGA Protect register set and we are writing to CRTC register=07h + if ((nv4->nvbase.svga.crtcreg == NV4_CIO_CR_OVL_INDEX) && (nv4->nvbase.svga.crtc[NV4_CIO_CR_VRE_INDEX] & 0x80)) + val = (nv4->nvbase.svga.crtc[NV4_CIO_CR_OVL_INDEX] & ~0x10) | (val & 0x10); + + // set the register value... + old_val = nv4->nvbase.svga.crtc[crtcreg]; + + nv4->nvbase.svga.crtc[crtcreg] = val; + // ...now act on it + + // Handle nvidia extended Bank0/Bank1 IDs + switch (crtcreg) + { + case NV4_CIO_CRE_PAGE0_INDEX: + nv4->nvbase.cio_read_bank = val; + if (nv4->nvbase.svga.chain4) // chain4 addressing (planar?) + nv4->nvbase.svga.read_bank = nv4->nvbase.cio_read_bank << 15; + else + nv4->nvbase.svga.read_bank = nv4->nvbase.cio_read_bank << 13; // extended bank numbers + break; + case NV4_CIO_CRE_PAGE1_INDEX: + nv4->nvbase.cio_write_bank = val; + if (nv4->nvbase.svga.chain4) + nv4->nvbase.svga.write_bank = nv4->nvbase.cio_write_bank << 15; + else + nv4->nvbase.svga.write_bank = nv4->nvbase.cio_write_bank << 13; + break; + case NV4_CIO_CRE_RMA_INDEX: + nv4->pbus.rma.mode = val & NV4_PRMIO_RMA_MODE_MAX; + break; + /* Handle some large screen stuff */ + case NV4_CIO_CRE_PIXEL_INDEX: + if (val & 1 << (NV4_CIO_CRE_LSR_VDT_10)) + nv4->nvbase.svga.vtotal += 0x400; + if (val & 1 << (NV4_CIO_CRE_LSR_VRS_10)) + nv4->nvbase.svga.vblankstart += 0x400; + if (val & 1 << (NV4_CIO_CRE_LSR_VBS_10)) + nv4->nvbase.svga.vsyncstart += 0x400; + if (val & 1 << (NV4_CIO_CRE_LSR_HBE_6)) + nv4->nvbase.svga.hdisp += 0x400; + + /* Make sure dispend and vblankstart are right if we are displaying above 1024 vert */ + if (nv4->nvbase.svga.crtc[NV4_CIO_CRE_PIXEL_INDEX] & 1 << (NV4_CIO_CRE_LSR_VDE_10)) + nv4->nvbase.svga.dispend += 0x400; + + break; + case NV4_CIO_CRE_HEB_INDEX: // large screen bit + if (val & 0x01) + nv4->nvbase.svga.hdisp += 0x100; + break; + case NV4_CIO_CRE_DDC_WR_INDEX: + { + uint8_t scl = !!(val & 0x20); + uint8_t sda = !!(val & 0x10); + // Set an I2C GPIO register + i2c_gpio_set(nv4->nvbase.i2c, scl, sda); + break; + } + /* [6:0] contains cursorAddr [23:17] */ + case NV4_CIO_CRE_HCUR_ADDR0_INDEX: + nv4->pramdac.cursor_address |= (val & 0x7F) << 13; //bit7 technically ignored, but nv don't care, so neither do we + break; + /* [7:2] contains cursorAddr [16:11] */ + case NV4_CIO_CRE_HCUR_ADDR1_INDEX: + nv4->pramdac.cursor_address |= (val & 0xFC) << 5; // bit0 and 1 aren't part of the address + break; + + + } + + /* Recalculate the timings if we actually changed them + Additionally only do it if the value actually changed*/ + if (old_val != val) + { + // Thx to Fuel who basically wrote most of the SVGA compatibility code already (although I fixed some issues), because VGA is boring + // and in the words of an ex-Rendition/3dfx/NVIDIA engineer, "VGA was basically an undocumented bundle of steaming you-know-what. + // And it was essential that any cores the PC 3D startups acquired had to work with all the undocumented modes and timing tweaks (mode X, etc.)" + if (nv4->nvbase.svga.crtcreg < 0xE + || nv4->nvbase.svga.crtcreg > 0x10) + { + nv4->nvbase.svga.fullchange = changeframecount; + nv4_recalc_timings(&nv4->nvbase.svga); + } + } + + break; + default: + svga_out(addr, val, &nv4->nvbase.svga); + break; + } + +} + +/* DFB, sets up a dumb framebuffer */ +uint8_t nv4_dfb_read8(uint32_t addr, void* priv) +{ + addr &= (nv4->nvbase.svga.vram_mask); + return nv4->nvbase.svga.vram[addr]; +} + +uint16_t nv4_dfb_read16(uint32_t addr, void* priv) +{ + addr &= (nv4->nvbase.svga.vram_mask); + return (nv4->nvbase.svga.vram[addr + 1] << 8) | nv4->nvbase.svga.vram[addr]; +} + +uint32_t nv4_dfb_read32(uint32_t addr, void* priv) +{ + addr &= (nv4->nvbase.svga.vram_mask); + return (nv4->nvbase.svga.vram[addr + 3] << 24) | (nv4->nvbase.svga.vram[addr + 2] << 16) + + (nv4->nvbase.svga.vram[addr + 1] << 8) | nv4->nvbase.svga.vram[addr]; +} + +void nv4_dfb_write8(uint32_t addr, uint8_t val, void* priv) +{ + addr &= (nv4->nvbase.svga.vram_mask); + nv4->nvbase.svga.vram[addr] = val; + nv4->nvbase.svga.changedvram[addr >> 12] = val; + //nv4_render_current_bpp_dfb_8(addr); +} + +void nv4_dfb_write16(uint32_t addr, uint16_t val, void* priv) +{ + addr &= (nv4->nvbase.svga.vram_mask); + nv4->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; + nv4->nvbase.svga.vram[addr] = (val) & 0xFF; + nv4->nvbase.svga.changedvram[addr >> 12] = val; + + //nv4_render_current_bpp_dfb_16(addr); + +} + +void nv4_dfb_write32(uint32_t addr, uint32_t val, void* priv) +{ + addr &= (nv4->nvbase.svga.vram_mask); + nv4->nvbase.svga.vram[addr + 3] = (val >> 24) & 0xFF; + nv4->nvbase.svga.vram[addr + 2] = (val >> 16) & 0xFF; + nv4->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; + nv4->nvbase.svga.vram[addr] = (val) & 0xFF; + nv4->nvbase.svga.changedvram[addr >> 12] = val; + + //removed until there is a render pipeline + //nv4_render_current_bpp_dfb_32(addr); + +} + +/* Cursor shit */ +void nv4_draw_cursor(svga_t* svga, int32_t drawline) +{ + // sanity check + if (!nv4) + return; + + /* + Commented out until we have a real graphics pipeline going here + + // if cursor disabled is set, return + if ((nv4->nvbase.svga.crtc[NV4_CRTC_REGISTER_CURSOR_START] >> NV4_CRTC_REGISTER_CURSOR_START_DISABLED) & 0x01) + return; + + // NT GDI drivers: Load cursor using NV_IMAGE_FROM_MEMORY ("NV4LCD") + // 9x GDI drivers: Use H/W cursor in RAMIN + + // Do we need to emulate it? + + // THIS IS CORRECT. BUT HOW DO WE FIND IT? + uint32_t ramin_cursor_position = NV4_RAMIN_OFFSET_CURSOR; + + /* let's just assume buffer 0 here...that code needs to be totally rewritten + nv4_coord_16_t start_position = nv4->pramdac.cursor_start; + + /* refuse to draw if thge cursor is offscreen + if (start_position.x >= nv4->nvbase.svga.hdisp + || start_position.y >= nv4->nvbase.svga.dispend) + { + return; + } + + nv_log("nv4_draw_cursor start=0x%04x,0x%04x", start_position.x, start_position.y); + + uint32_t final_position = nv4_render_get_vram_address_for_buffer(start_position, 0); + + uint16_t* vram_16 = (uint16_t*)nv4->nvbase.svga.vram; + uint32_t* vram_32 = (uint32_t*)nv4->nvbase.svga.vram; + + /* + We have to get a 32x32, "A"1R5G5B5-format cursor + out of video memory. The alpha bit actually means - XOR with display pixel if 0, replace if 1 + + These are expanded to RGB10 only if they are XORed. We don't do this (we don't really need to + there is no grobj specified here so special casing + would be needed) so we just xor it with the current pixel format + + for (int32_t y = 0; y < NV4_PRAMDAC_CURSOR_SIZE_Y; y++) + { + for (int32_t x = 0; x < NV4_PRAMDAC_CURSOR_SIZE_X; x++) + { + uint16_t current_pixel = nv4_ramin_read16(ramin_cursor_position, nv4); + + // 0000 = transparent, so skip drawing + if (current_pixel) + { + bool replace_bit = (current_pixel & 0x8000); + + // use buffer 0 BPIXEL + uint32_t bpixel_format = (nv4->pgraph.bpixel[0]) & 0x03; + + switch (bpixel_format) + { + case bpixel_fmt_8bit: + if (replace_bit) + nv4->nvbase.svga.vram[final_position] = current_pixel; + else //xor + { + // not sure what to do here. we'd have to search through the palette to find the closest possible colour. + uint8_t final = current_pixel ^ nv4->nvbase.svga.vram[final_position]; + nv4->nvbase.svga.vram[final_position] = final; + } + case bpixel_fmt_16bit: // easy case (our cursor is 15bpp format) + uint32_t index_16 = final_position >> 1; + + if (replace_bit) // just replace + vram_16[index_16] = current_pixel; + else // xor + { + current_pixel &= ~0x8000; // mask off the xor bit + uint16_t final = current_pixel ^ vram_16[index_16]; + vram_16[index_16] = final; + } + case bpixel_fmt_32bit: + uint32_t index_32 = final_position >> 2; + + if (replace_bit) // just replace + vram_32[index_32] = nv4->nvbase.svga.conv_16to32(&nv4->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here + else //xor + { + current_pixel &= ~0x8000; // mask off the xor bit + uint32_t current_pixel_32 = nv4->nvbase.svga.conv_16to32(&nv4->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here + + uint32_t final = current_pixel_32 ^ vram_32[index_32]; + vram_32[index_32] = final; + } + break; + } + } + + // increment vram position + ramin_cursor_position += 2; + + // go + switch (nv4->nvbase.svga.bpp) + { + case 8: + final_position++; + case 15 ... 16: + final_position += 2; + break; + case 32: + final_position += 4; + break; + } + + start_position.x++; + } + + + start_position.y++; + start_position.x = nv4->pramdac.cursor_start.x; + + // reset at the end of each line so we "jump" to the start x + final_position = nv4_render_get_vram_address_for_buffer(start_position, 0); + }*/ +} + +// MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. +// Note this area is 64kb and the vbios is only 32kb. See below.. + +uint8_t nv4_prom_read(uint32_t address) +{ + // prom area is 64k, so... + // first see if we even have a rom of 64kb in size + uint32_t max_rom_size = NV4_PROM_END - NV4_PROM_START; + uint32_t real_rom_size = max_rom_size; + + // set it + if (nv4->nvbase.vbios.sz < max_rom_size) + real_rom_size = nv4->nvbase.vbios.sz; + + //get our real address + uint8_t rom_address = address & max_rom_size; + + // Does this mirror on real hardware? + if (rom_address >= real_rom_size) + { + nv_log("PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); + return 0xFF; + } + else + { + uint8_t val = nv4->nvbase.vbios.rom[rom_address]; + nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); + return val; + } +} + +void nv4_prom_write(uint32_t address, uint32_t value) +{ + uint32_t real_addr = address & 0x1FFFF; + nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", real_addr, value); +} From 51f009b1e033dbd5ffdd129d8a72a4a2bba7be26 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 13 Sep 2025 17:23:59 +0100 Subject: [PATCH 222/274] log read/write --- src/video/nv/nv4/nv4_core_io.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c index a7fe0d0c8..87614b8c2 100644 --- a/src/video/nv/nv4/nv4_core_io.c +++ b/src/video/nv/nv4/nv4_core_io.c @@ -44,12 +44,12 @@ void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); uint32_t nv4_mmio_arbitrate_read(uint32_t addr) { - + nv_log_verbose_only("MMIO read from address=0x%08x", addr); } void nv4_mmio_arbitrate_write(uint32_t addr, uint32_t val) { - + nv_log_verbose_only("MMIO write to address=0x%08x value %08x", addr, val); } // Determine if this address needs to be redirected to the SVGA subsystem. From 3f27fab2db6e247df640ad6f911c2b9079e03d58 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 13 Sep 2025 19:24:16 +0100 Subject: [PATCH 223/274] actually initialise mappings --- src/include/86box/nv/vid_nv4.h | 7 +++- src/video/CMakeLists.txt | 1 + src/video/nv/nv3/nv3_core.c | 3 -- src/video/nv/nv4/nv4_core.c | 42 ++++++++++++++++++++++-- src/video/nv/nv4/nv4_core_config.c | 4 --- src/video/nv/nv4/subsystems/nv4_ptimer.c | 15 +++++---- 6 files changed, 54 insertions(+), 18 deletions(-) diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 7fda0fca4..47c62853a 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -91,7 +91,10 @@ extern nv4_t* nv4; // Alloc // // Device Core -void nv4_init(); +bool nv4_init(); + +void* nv4_init_stb4400(const device_t* info); + void nv4_close(void* priv); void nv4_speed_changed(void *priv); void nv4_draw_cursor(svga_t* svga, int32_t drawline); @@ -117,6 +120,8 @@ uint32_t nv4_ramin_read32(uint32_t addr, void* priv); void nv4_ramin_write8(uint32_t addr, uint8_t val, void* priv); void nv4_ramin_write16(uint32_t addr, uint16_t val, void* priv); void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv); +uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv); +void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); uint8_t nv4_svga_read(uint16_t addr, void* priv); diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index c03ac15c9..b9c735be8 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -201,6 +201,7 @@ add_library(vid OBJECT nv/nv4/nv4_core.c nv/nv4/nv4_core_io.c nv/nv4/nv4_core_config.c + nv/nv4/subsystems/nv4_ptimer.c # Generic vid_bochs_vbe.c diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index d051a8f15..ec5fe5f92 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -138,10 +138,7 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) return ret; } - ret = nv3_mmio_arbitrate_read(addr); - - return ret; } diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c index 58aba93b1..c210b0424 100644 --- a/src/video/nv/nv4/nv4_core.c +++ b/src/video/nv/nv4/nv4_core.c @@ -29,6 +29,9 @@ nv4_t* nv4; +// Stolen from Voodoo 3 +static video_timings_t timing_nv4_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; + // Initialise the MMIO mappings void nv4_init_mappings_mmio(void) { @@ -185,7 +188,7 @@ void nv4_update_mappings(void) } -void nv4_init() +bool nv4_init() { nv4 = calloc(1, sizeof(nv4_t)); @@ -200,13 +203,46 @@ void nv4_init() else nv4->nvbase.log = log_open_cyclic("NV4"); + nv4->nvbase.bus_generation = nv_bus_agp_2x; + nv_log_set_device(nv4->nvbase.log); + // Figure out which vbios the user selected + // This depends on the bus we are using and if the gpu is rev a/b or rev c + + const char* vbios_file = NV4_VBIOS_STB_REVA; + + int32_t err = rom_init(&nv4->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); + + if (err) + { + nv_log("NV4 FATAL: failed to load VBIOS err=%d\n", err); + fatal("Nvidia NV4 init failed: Somehow selected a nonexistent VBIOS? err=%d\n", err); + return false; + } + else + nv_log("Successfully loaded VBIOS located at %s\n", vbios_file); + + pci_add_card(PCI_ADD_AGP, nv4_pci_read, nv4_pci_write, NULL, &nv4->nvbase.pci_slot); + + svga_init(&nv4_device_agp, &nv4->nvbase.svga, nv4, nv4->nvbase.vram_amount, + nv4_recalc_timings, nv4_svga_read, nv4_svga_write, nv4_draw_cursor, NULL); + + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv4_agp); + + nv4_init_mappings(); + //nv4_update_mappings(); + + return true; } void* nv4_init_stb4400(const device_t *info) { - nv4_init(); - return nv4; + bool successful = nv4_init(); + + if (successful) + return nv4; + else + return NULL; } void nv4_close(void* priv) diff --git a/src/video/nv/nv4/nv4_core_config.c b/src/video/nv/nv4/nv4_core_config.c index ea9ef9332..2dd88eed6 100644 --- a/src/video/nv/nv4/nv4_core_config.c +++ b/src/video/nv/nv4/nv4_core_config.c @@ -55,11 +55,7 @@ const device_config_t nv4_config[] = { .name = "pgraph_threads", -#ifndef RELEASE_BUILD - .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", -#else .description = "Render threads", -#endif .type = CONFIG_SELECTION, .default_int = 1, // todo: change later .selection = diff --git a/src/video/nv/nv4/subsystems/nv4_ptimer.c b/src/video/nv/nv4/subsystems/nv4_ptimer.c index b52f79f17..29df0168b 100644 --- a/src/video/nv/nv4/subsystems/nv4_ptimer.c +++ b/src/video/nv/nv4/subsystems/nv4_ptimer.c @@ -52,7 +52,8 @@ void nv4_ptimer_interrupt(uint32_t num) { nv4->ptimer.interrupt_status |= (1 << num); - nv4_pmc_handle_interrupts(true); + //todo + //nv4_pmc_handle_interrupts(true); } // Ticks the timer. @@ -128,14 +129,14 @@ uint32_t nv4_ptimer_read(uint32_t address) break; // 64-bit value // High part - case NV4_PTIMER_TIME_0_NSEC: + case NV4_PTIMER_TIME_0: ret = nv4->ptimer.time & 0xFFFFFFFF; //28:0 break; // Low part - case NV4_PTIMER_TIME_1_NSEC: + case NV4_PTIMER_TIME_1: ret = nv4->ptimer.time >> 32; // 31:5 break; - case NV4_PTIMER_ALARM_NSEC: + case NV4_PTIMER_ALARM: ret = nv4->ptimer.alarm; // 31:5 break; } @@ -186,7 +187,7 @@ void nv4_ptimer_write(uint32_t address, uint32_t value) case NV4_PTIMER_INTR: nv4->ptimer.interrupt_status &= ~value; - nv4_pmc_clear_interrupts(); + //TODO nv4_pmc_clear_interrupts(); break; // Interrupt enablement state @@ -206,11 +207,11 @@ void nv4_ptimer_write(uint32_t address, uint32_t value) break; // 64-bit value // High part - case NV4_PTIMER_TIME_0_NSEC: + case NV4_PTIMER_TIME_0: nv4->ptimer.time |= (value) & 0xFFFFFFE0; //28:0 break; // Low part - case NV4_PTIMER_TIME_1_NSEC: + case NV4_PTIMER_TIME_1: nv4->ptimer.time |= ((uint64_t)(value & 0xFFFFFFE0) << 32); // 31:5 break; case NV4_PTIMER_ALARM: From accf4997905b3763f7b7d3a353911022894470a5 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 13 Sep 2025 22:55:01 +0100 Subject: [PATCH 224/274] RIVA TNT Video BIOS now runs. --- src/include/86box/nv/vid_nv4_defines.h | 10 ++- src/video/nv/nv3/nv3_core.c | 1 - src/video/nv/nv4/nv4_core.c | 88 +++++++++++++++++-- src/video/nv/nv4/nv4_core_io.c | 114 ++++++------------------- 4 files changed, 116 insertions(+), 97 deletions(-) diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h index 21cf5739a..3bda4dc1c 100644 --- a/src/include/86box/nv/vid_nv4_defines.h +++ b/src/include/86box/nv/vid_nv4_defines.h @@ -505,6 +505,7 @@ #define NV4_PBUS_PCI_DEVICE_ID 0x1802 #define NV4_PBUS_PCI_DEVICE_ID_NV4 0x0020 // Chip (19:17)= NV4, Func = VGA #define NV4_PBUS_PCI_COMMAND 0x1804 +#define NV4_PBUS_PCI_COMMAND_H 0x1805 #define NV4_PBUS_PCI_COMMAND_IO_SPACE 0 #define NV4_PBUS_PCI_COMMAND_IO_SPACE_ENABLED 0x1 #define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE 1 @@ -568,9 +569,12 @@ #define NV4_PBUS_PCI_BAR0_UNUSED2 0x1812 #define NV4_PBUS_PCI_BAR0_BASE_31_TO_24 0x1813 // Must align to 16MByte #define NV4_PBUS_PCI_BAR1_INFO 0x1814 -#define NV4_PBUS_PCI_BAR1_UNUSED1 0x1814 -#define NV4_PBUS_PCI_BAR1_UNUSED2 0x1815 -#define NV4_PBUS_PCI_BAR1_BASE_31_TO_24 0x1816 // Must align to 16MByte +#define NV4_PBUS_PCI_BAR1_UNUSED1 0x1815 +#define NV4_PBUS_PCI_BAR1_UNUSED2 0x1816 +#define NV4_PBUS_PCI_BAR1_BASE_31_TO_24 0x1817 // Must align to 16MByte +#define NV4_PBUS_PCI_BAR_RESERVED_START 0x1818 +#define NV4_PBUS_PCI_BAR_RESERVED_END 0x182B + //BAR2-5 reserved #define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID 0x182C #define NV4_PBUS_PCI_SUBSYSTEM_ID 0x182E diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index ec5fe5f92..01af9100d 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -137,7 +137,6 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv) return ret; } - ret = nv3_mmio_arbitrate_read(addr); return ret; diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c index c210b0424..285988800 100644 --- a/src/video/nv/nv4/nv4_core.c +++ b/src/video/nv/nv4/nv4_core.c @@ -66,6 +66,7 @@ void nv4_init_mappings_svga(void) { nv_log("Initialising SVGA core memory mapping\n"); // setup the svga mappings + mem_mapping_add(&nv4->nvbase.framebuffer_mapping, 0, 0, nv4_dfb_read8, nv4_dfb_read16, @@ -198,14 +199,18 @@ bool nv4_init() /* Set log device name based on card model */ const char* log_device_name = "NV4"; + + /* Just hardcode full logging */ + if (device_get_config_int("nv_debug_fulllog")) - nv4->nvbase.log = log_open("NV4"); + nv4->nvbase.log = log_open(log_device_name); else - nv4->nvbase.log = log_open_cyclic("NV4"); + nv4->nvbase.log = log_open_cyclic(log_device_name); + + nv_log_set_device(nv4->nvbase.log); nv4->nvbase.bus_generation = nv_bus_agp_2x; - nv_log_set_device(nv4->nvbase.log); // Figure out which vbios the user selected // This depends on the bus we are using and if the gpu is rev a/b or rev c @@ -260,11 +265,82 @@ void nv4_draw_cursor(svga_t* svga, int32_t drawline) } -void nv4_recalc_timings(svga_t* svga) -{ +// +// SVGA functions +// +void nv4_recalc_timings(svga_t* svga) +{ + // sanity check + if (!nv4) + return; + + + nv4_t* nv4 = (nv4_t*)svga->priv; + + // TODO: Everything, this code sucks, incl. NV4_PRAMDAC_GENERAL_CONTROL_BPC and the OFFSET register + uint32_t pixel_mode = svga->crtc[NV4_CIO_CRE_PIXEL_INDEX] & 0x03; + + svga->memaddr_latch += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0x1F) << 16; + + /* Turn off override if we are in VGA mode */ + svga->override = !(pixel_mode == NV4_CIO_CRE_PIXEL_FORMAT_VGA); + + /* NOTE: The RIVA 128 draws in a way almost completely separate to any other 86Box GPU. + + Basically, we only blit to buffer32 when something changes and we don't even bother using a timer. We only render when there is something to actually render. + + This is because there is no linear relationship between the contents of VRAM and the contents of the display which 86box's SVGA subsystem cannot tolerate. + In fact, the position in VRAM and pitch can be changed at any time via an NV_IMAGE_IN_MEMORY object. + + Therefore, we need to completely bypass it using svga->override and draw our own rendering functions. This allows us to use a neat optimisation trick + to only ever actually draw when we need to do something. This shouldn't be a problem in games, because the drivers will read the current refresh rate from + the Windows settings, and then, just submit objects at that pace for anything that changes on the screen. + */ + + // Set the pixel mode + switch (pixel_mode) + { + case NV4_CIO_CRE_PIXEL_FORMAT_8BPP: + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 1; // ????? + svga->bpp = 8; + svga->lowres = 0; + svga->map8 = svga->pallook; + break; + case NV4_CIO_CRE_PIXEL_FORMAT_16BPP: + /* This is some sketchy shit that is an attempt at an educated guess + at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, + this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */ + if ((svga->crtc[NV4_CIO_CR_VRS_INDEX] >> 1) & 0x01) + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 2; + else + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; + + // 15bpp mode is removed on NV4 + // TODO: Not svga + svga->bpp = 16; + svga->lowres = 0; + + break; + case NV4_CIO_CRE_PIXEL_FORMAT_32BPP: + svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; + + svga->bpp = 32; + svga->lowres = 0; + //svga->render = nv4_render_32bpp; + break; + } + + + if (((svga->miscout >> 2) & 2) == 2) + { + // set clocks + //nv4_pramdac_set_pixel_clock(); + //nv4_pramdac_set_vram_clock(); + } } + void nv4_force_redraw(void* priv) { @@ -281,7 +357,7 @@ int32_t nv4_available(void) // 8MB or 16MB VRAM const device_t nv4_device_agp = { - .name = "nVIDIA RIVA TNT [STB Velocity 4400]", + .name = "nVIDIA RIVA TNT (STB Velocity 4400)", .internal_name = "nv4_stb4400", .flags = DEVICE_AGP, .local = 0, diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c index 87614b8c2..2849efac1 100644 --- a/src/video/nv/nv4/nv4_core_io.c +++ b/src/video/nv/nv4/nv4_core_io.c @@ -438,7 +438,7 @@ uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv) // We only need to return 0x30 since the VGA class code is 0x30000 case NV4_PBUS_PCI_CLASS_CODE: - ret = (NV4_PBUS_PCI_CLASS_CODE_VGA) >> 12; // CLASS_CODE_VGA + ret = (NV4_PBUS_PCI_CLASS_CODE_VGA) >> 16; // CLASS_CODE_VGA break; @@ -462,6 +462,15 @@ uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv) case NV4_PBUS_PCI_BAR1_BASE_31_TO_24: ret = nv4->nvbase.bar1_lfb_base >> 24; //8bit value break; + + case NV4_PBUS_PCI_BAR_RESERVED_START ... NV4_PBUS_PCI_BAR_RESERVED_END: + case NV4_PBUS_PCI_BAR0_UNUSED1: + case NV4_PBUS_PCI_BAR0_UNUSED2: + case NV4_PBUS_PCI_BAR1_UNUSED1: + case NV4_PBUS_PCI_BAR1_UNUSED2: + + ret = 0x00; // hard lock + break; case NV4_PBUS_PCI_ROM: ret = nv4->nvbase.pci_config.vbios_enabled; @@ -504,6 +513,7 @@ uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv) case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE + 1: ret = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_SUBSYSTEM_ID + (addr & 0x03)]; break; + case NV4_PBUS_AGP_CAPABILITIES: ret = NV4_PBUS_AGP_CAPABILITY_AGP; // AGP capable device break; @@ -529,7 +539,7 @@ uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv) } - nv_log("nv4_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret); + nv_log("nv4_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr & 0xFF, ret); return ret; } @@ -550,28 +560,28 @@ void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) && addr == NV4_PBUS_PCI_BAR1_UNUSED1 || addr == NV4_PBUS_PCI_BAR1_UNUSED2) return; - nv_log("nv4_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); + nv_log("nv4_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr & 0xFF, val); nv4->nvbase.pci_config.pci_regs[addr] = val; switch (addr) { // standard pci command stuff - case PCI_REG_COMMAND_L: + case NV4_PBUS_PCI_COMMAND: nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L] = val; // actually update the mappings nv4_update_mappings(); break; - case PCI_REG_COMMAND_H: + case NV4_PBUS_PCI_COMMAND_H: nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] = val; // actually update the mappings nv4_update_mappings(); break; // pci status register - case PCI_REG_STATUS_L: + case NV4_PBUS_PCI_STATUS: nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE << NV4_PBUS_PCI_STATUS_66MHZ); break; - case PCI_REG_STATUS_H: + case NV4_PBUS_PCI_STATUS_2: nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST << NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING); break; //TODO: ACTUALLY REMAP THE MMIO AND NV_USER @@ -583,6 +593,7 @@ void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) nv4->nvbase.bar1_lfb_base = val << 24; nv4_update_mappings(); break; + case NV4_PBUS_PCI_ROM: case NV4_PBUS_PCI_ROM_BASE: @@ -601,13 +612,16 @@ void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) { uint32_t old_addr = nv4->nvbase.vbios.mapping.base; // 9bit register - uint32_t new_addr = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM + 1] << 24 | - nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM] << 16; + uint32_t new_addr = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM + 3] << 24 | + nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM + 2] << 16; + + // only bits 31;22 matter + //new_addr &= 0xFFC00000; // move it mem_mapping_set_addr(&nv4->nvbase.vbios.mapping, new_addr, 0x8000); - nv_log("...i like to move it move it (VBIOS Relocation) 0x%04x -> 0x%04x\n", old_addr, new_addr); + nv_log("...i like to move it move it (VBIOS Relocation) 0x%x -> 0x%x\n", old_addr, new_addr); } else @@ -643,80 +657,6 @@ void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) } -// -// SVGA functions -// -void nv4_recalc_timings(svga_t* svga) -{ - // sanity check - if (!nv4) - return; - - - nv4_t* nv4 = (nv4_t*)svga->priv; - - // TODO: Everything, this code sucks, incl. NV4_PRAMDAC_GENERAL_CONTROL_BPC and the OFFSET register - uint32_t pixel_mode = svga->crtc[NV4_CIO_CRE_PIXEL_INDEX] & 0x03; - - svga->memaddr_latch += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0x1F) << 16; - - /* Turn off override if we are in VGA mode */ - svga->override = !(pixel_mode == NV4_CIO_CRE_PIXEL_FORMAT_VGA); - - /* NOTE: The RIVA 128 draws in a way almost completely separate to any other 86Box GPU. - - Basically, we only blit to buffer32 when something changes and we don't even bother using a timer. We only render when there is something to actually render. - - This is because there is no linear relationship between the contents of VRAM and the contents of the display which 86box's SVGA subsystem cannot tolerate. - In fact, the position in VRAM and pitch can be changed at any time via an NV_IMAGE_IN_MEMORY object. - - Therefore, we need to completely bypass it using svga->override and draw our own rendering functions. This allows us to use a neat optimisation trick - to only ever actually draw when we need to do something. This shouldn't be a problem in games, because the drivers will read the current refresh rate from - the Windows settings, and then, just submit objects at that pace for anything that changes on the screen. - */ - - // Set the pixel mode - switch (pixel_mode) - { - case NV4_CIO_CRE_PIXEL_FORMAT_8BPP: - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 1; // ????? - svga->bpp = 8; - svga->lowres = 0; - svga->map8 = svga->pallook; - break; - case NV4_CIO_CRE_PIXEL_FORMAT_16BPP: - /* This is some sketchy shit that is an attempt at an educated guess - at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, - this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */ - if ((svga->crtc[NV4_CIO_CR_VRS_INDEX] >> 1) & 0x01) - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 2; - else - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; - - // 15bpp mode is removed on NV4 - // TODO: Not svga - svga->bpp = 16; - svga->lowres = 0; - - break; - case NV4_CIO_CRE_PIXEL_FORMAT_32BPP: - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; - - svga->bpp = 32; - svga->lowres = 0; - //svga->render = nv4_render_32bpp; - break; - } - - - if (((svga->miscout >> 2) & 2) == 2) - { - // set clocks - //nv4_pramdac_set_pixel_clock(); - //nv4_pramdac_set_vram_clock(); - } -} - void nv4_speed_changed(void* priv) { // sanity check @@ -888,9 +828,6 @@ uint8_t nv4_svga_read(uint16_t addr, void* priv) { // CR = CRTC Controller // CRE = CRTC Controller Extended (weitek) - - nv4_t* nv4 = (nv4_t*)priv; - uint8_t ret = 0x00; // sanity check @@ -947,6 +884,8 @@ uint8_t nv4_svga_read(uint16_t addr, void* priv) break; } + nv_log("SVGA read 0x%04x value 0x%02x\n", addr, ret); + return ret; //TEMP } @@ -1090,6 +1029,7 @@ void nv4_svga_write(uint16_t addr, uint8_t val, void* priv) break; } + nv_log("SVGA write 0x%04x value 0x%02x\n", addr, val); } /* DFB, sets up a dumb framebuffer */ From b073c1d66a99633e5db3fe00f319066eabd8c12c Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 14 Sep 2025 00:18:54 +0100 Subject: [PATCH 225/274] Fix force redraw so hard reset not needed --- CMakePresets.json | 4 +++- src/include/86box/nv/vid_nv4.h | 20 +++++++++----------- src/video/nv/nv4/nv4_core.c | 5 ----- src/video/nv/nv4/nv4_core_io.c | 2 -- src/video/nv/nv4/subsystems/nv4_pramdac.c | 16 ++++++++++++++++ 5 files changed, 28 insertions(+), 19 deletions(-) create mode 100644 src/video/nv/nv4/subsystems/nv4_pramdac.c diff --git a/CMakePresets.json b/CMakePresets.json index 30feab8ab..53ddffc74 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -36,7 +36,9 @@ "name": "debug", "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug", - "NV_LOG": "ON" + "NV_LOG": "ON", + "NV_LOG_ULTRA": "ON" + }, "inherits": "base" }, diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index 47c62853a..bcdfb4dd0 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -20,12 +20,13 @@ #include #include <86Box/nv/vid_nv4_defines.h> - // -// PBUS/RMA +// Structures // -// Access the GPU from real-mode + +// PBUS +// RMA: Access the GPU from real-mode typedef struct nv4_pbus_rma_s { uint32_t addr; // Address to RMA to @@ -43,10 +44,8 @@ typedef struct nv4_pbus_s nv4_pbus_rma_t rma; } nv4_pbus_t; -// -// PTIMER -// +// PTIMER typedef struct nv4_ptimer_s { uint32_t interrupt_status; // PTIMER Interrupt status @@ -57,9 +56,7 @@ typedef struct nv4_ptimer_s uint32_t alarm; // The value of time when there should be an alarm } nv4_ptimer_t; -// // PRAMDAC -// typedef struct nv4_pramdac_s { uint32_t mclk; @@ -68,7 +65,7 @@ typedef struct nv4_pramdac_s uint32_t cursor_address; } nv4_pramdac_t; -// Structures +// Device Core typedef struct nv4_s { nv_base_t nvbase; // Base Nvidia structure @@ -78,10 +75,10 @@ typedef struct nv4_s nv4_pramdac_t pramdac; } nv4_t; - // // Globals // + extern const device_config_t nv4_config[]; extern nv4_t* nv4; // Allocated at device startup @@ -101,7 +98,7 @@ void nv4_draw_cursor(svga_t* svga, int32_t drawline); void nv4_recalc_timings(svga_t* svga); void nv4_force_redraw(void* priv); -// I/o +// I/O uint8_t nv4_mmio_read8(uint32_t addr, void* priv); uint16_t nv4_mmio_read16(uint32_t addr, void* priv); uint32_t nv4_mmio_read32(uint32_t addr, void* priv); @@ -123,6 +120,7 @@ void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv); uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv); void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); +// PRAMDAC uint8_t nv4_svga_read(uint16_t addr, void* priv); void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c index 285988800..13f9df321 100644 --- a/src/video/nv/nv4/nv4_core.c +++ b/src/video/nv/nv4/nv4_core.c @@ -341,11 +341,6 @@ void nv4_recalc_timings(svga_t* svga) } -void nv4_force_redraw(void* priv) -{ - -} - // See if the bios rom is available. int32_t nv4_available(void) { diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c index 2849efac1..51a702bd3 100644 --- a/src/video/nv/nv4/nv4_core_io.c +++ b/src/video/nv/nv4/nv4_core_io.c @@ -884,7 +884,6 @@ uint8_t nv4_svga_read(uint16_t addr, void* priv) break; } - nv_log("SVGA read 0x%04x value 0x%02x\n", addr, ret); return ret; //TEMP } @@ -1029,7 +1028,6 @@ void nv4_svga_write(uint16_t addr, uint8_t val, void* priv) break; } - nv_log("SVGA write 0x%04x value 0x%02x\n", addr, val); } /* DFB, sets up a dumb framebuffer */ diff --git a/src/video/nv/nv4/subsystems/nv4_pramdac.c b/src/video/nv/nv4/subsystems/nv4_pramdac.c new file mode 100644 index 000000000..d8d4883ec --- /dev/null +++ b/src/video/nv/nv4/subsystems/nv4_pramdac.c @@ -0,0 +1,16 @@ +/* +* 86Box A hypervisor and IBM PC system emulator that specializes in +* running old operating systems and software designed for IBM +* PC systems and compatibles from 1981 through fairly recent +* system designs based on the PCI bus. +* +* This file is part of the 86Box distribution. +* +* NV4/Riva TNT - RAMDAC +* +* +* Authors: Connor Hyde, I need a better email address ;^) +* +* Copyright 2024-2025 starfrost +*/ + From ec40252a71bead4468ca5b00eb7c0bb0eb430947 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 14 Sep 2025 01:08:13 +0100 Subject: [PATCH 226/274] slightly clarify some divs --- src/include/86box/nv/vid_nv4_defines.h | 6 +++--- src/video/nv/nv3/subsystems/nv3_pramdac.c | 2 -- src/video/nv/nv4/nv4_core_io.c | 6 +++--- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h index 3bda4dc1c..2a959670c 100644 --- a/src/include/86box/nv/vid_nv4_defines.h +++ b/src/include/86box/nv/vid_nv4_defines.h @@ -49,15 +49,15 @@ #define NV4_PRAMDAC_NVPLL_COEFF 0x680500 #define NV4_PRAMDAC_NVPLL_COEFF_MDIV 0 #define NV4_PRAMDAC_NVPLL_COEFF_NDIV 8 -#define NV4_PRAMDAC_NVPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_NVPLL_COEFF_PDIV 16 // 18:16 #define NV4_PRAMDAC_MPLL_COEFF 0x680504 #define NV4_PRAMDAC_MPLL_COEFF_MDIV 0 #define NV4_PRAMDAC_MPLL_COEFF_NDIV 8 -#define NV4_PRAMDAC_MPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_MPLL_COEFF_PDIV 16 // 18:16 #define NV4_PRAMDAC_VPLL_COEFF 0x680508 #define NV4_PRAMDAC_VPLL_COEFF_MDIV 0 #define NV4_PRAMDAC_VPLL_COEFF_NDIV 8 -#define NV4_PRAMDAC_VPLL_COEFF_PDIV 16 +#define NV4_PRAMDAC_VPLL_COEFF_PDIV 16 // 18:16 #define NV4_PRAMDAC_PLL_COEFF_SELECT 0x68050C #define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 0 #define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c index f179c8136..9ce5a189a 100644 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c @@ -156,8 +156,6 @@ void nv3_pramdac_set_pixel_clock(void) // frequency divider algorithm from old varcem/86box/pcbox riva driver, // verified by reversing NT drivers v1.50e CalcMNP [symbols] function - // todo: actually implement it - // missing section // not really needed. // if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500) diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c index 51a702bd3..d9fa6f58a 100644 --- a/src/video/nv/nv4/nv4_core_io.c +++ b/src/video/nv/nv4/nv4_core_io.c @@ -44,12 +44,12 @@ void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); uint32_t nv4_mmio_arbitrate_read(uint32_t addr) { - nv_log_verbose_only("MMIO read from address=0x%08x", addr); + nv_log_verbose_only("MMIO read from address=0x%08x\n", addr); } void nv4_mmio_arbitrate_write(uint32_t addr, uint32_t val) { - nv_log_verbose_only("MMIO write to address=0x%08x value %08x", addr, val); + nv_log_verbose_only("MMIO write to address=0x%08x value %08x\n", addr, val); } // Determine if this address needs to be redirected to the SVGA subsystem. @@ -95,7 +95,7 @@ uint8_t nv4_rma_read(uint16_t addr) } // log current location for vbios RE - nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", + nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%08x final RMA MMIO address=0x%08x data=0x%08x\n", addr, real_final_address, ret); break; From 599b3910951c85220ef26a319fc8fdbf1acb16f8 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 21 Sep 2025 18:45:32 +0100 Subject: [PATCH 227/274] Add register framework --- src/include/86box/nv/vid_nv.h | 4 ++ src/include/86box/nv/vid_nv4.h | 27 ++++++++- src/video/CMakeLists.txt | 2 + src/video/nv/nv4/nv4_core.c | 27 ++++++++- src/video/nv/nv4/nv4_core_io.c | 39 ++++++++++++- src/video/nv/nv4/nv4_debug_register_list.c | 46 +++++++++++++++ src/video/nv/nv4/subsystems/nv4_pramdac.c | 68 ++++++++++++++++++++++ 7 files changed, 206 insertions(+), 7 deletions(-) diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h index 3d69f75c7..83f94c167 100644 --- a/src/include/86box/nv/vid_nv.h +++ b/src/include/86box/nv/vid_nv.h @@ -136,6 +136,10 @@ typedef struct nv_base_s bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times double memory_clock_frequency; // Source Frequency for PTIMER rivatimer_t* memory_clock_timer; // Timer for measuring memory/gpu clock + + // VCLK / NVCLK do not have timers set here. + pc_timer_t* nv4_vclk_timer; // NV4+ MCLK (Video RAM) timer + bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times void* i2c; // I2C for monitor EDID void* ddc; // Display Data Channel for EDID diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h index bcdfb4dd0..0f2aad285 100644 --- a/src/include/86box/nv/vid_nv4.h +++ b/src/include/86box/nv/vid_nv4.h @@ -62,6 +62,7 @@ typedef struct nv4_pramdac_s uint32_t mclk; uint32_t vclk; uint32_t nvclk; + uint32_t clk_coeff_select; // Clock coefficient selection uint32_t cursor_address; } nv4_pramdac_t; @@ -83,6 +84,13 @@ extern const device_config_t nv4_config[]; extern nv4_t* nv4; // Allocated at device startup +#ifdef NV_LOG + +// Debug register list +extern nv_register_t nv4_registers[]; + +#endif + // // Functions // @@ -120,9 +128,22 @@ void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv); uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv); void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); -// PRAMDAC - +// SVGA uint8_t nv4_svga_read(uint16_t addr, void* priv); void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); -void nv4_update_mappings(); \ No newline at end of file +// Memory +void nv4_update_mappings(); + +// PRAMDAC +uint32_t nv4_pramdac_read(uint32_t address); +void nv4_pramdac_write(uint32_t address, uint32_t data); + +// We don't implement NVCLK/VCLK because they are too fast +void nv4_pramdac_set_vclk(); + +void nv4_vclk_tick(); + +// PTIMER +uint32_t nv4_ptimer_read(uint32_t address); +void nv4_ptimer_write(uint32_t address, uint32_t data); \ No newline at end of file diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index b9c735be8..f1d755dba 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -201,6 +201,8 @@ add_library(vid OBJECT nv/nv4/nv4_core.c nv/nv4/nv4_core_io.c nv/nv4/nv4_core_config.c + nv/nv4/nv4_debug_register_list.c + nv/nv4/subsystems/nv4_pramdac.c nv/nv4/subsystems/nv4_ptimer.c # Generic diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c index 13f9df321..5712cf7d1 100644 --- a/src/video/nv/nv4/nv4_core.c +++ b/src/video/nv/nv4/nv4_core.c @@ -199,7 +199,6 @@ bool nv4_init() /* Set log device name based on card model */ const char* log_device_name = "NV4"; - /* Just hardcode full logging */ if (device_get_config_int("nv_debug_fulllog")) @@ -234,6 +233,15 @@ bool nv4_init() video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv4_agp); + // Setup clock information. These values don't matter, I pulled them out of an STB BIOS, we don't need to macro them + nv4->pramdac.nvclk = 0x17809; + nv4->pramdac.mclk = 0x1a30a; + nv4->pramdac.vclk = 0x1400c; + + //timer_add(nv4->pramdac.nvclk, ) + + + nv4_init_mappings(); //nv4_update_mappings(); @@ -250,6 +258,21 @@ void* nv4_init_stb4400(const device_t *info) return NULL; } +void nv4_nvclk_tick() +{ + +} + +void nv4_mclk_tick() +{ + +} + +void nv4_vclk_tick() +{ + +} + void nv4_close(void* priv) { free(nv4); @@ -278,7 +301,7 @@ void nv4_recalc_timings(svga_t* svga) nv4_t* nv4 = (nv4_t*)svga->priv; - // TODO: Everything, this code sucks, incl. NV4_PRAMDAC_GENERAL_CONTROL_BPC and the OFFSET register + // TODO: Everything, this code sucks, incl. NV4_PRAMDAC_GENERAL_CONTROL_BPC and the offset register uint32_t pixel_mode = svga->crtc[NV4_CIO_CRE_PIXEL_INDEX] & 0x03; svga->memaddr_latch += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0x1F) << 16; diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c index d9fa6f58a..4c5aa5a40 100644 --- a/src/video/nv/nv4/nv4_core_io.c +++ b/src/video/nv/nv4/nv4_core_io.c @@ -44,12 +44,47 @@ void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); uint32_t nv4_mmio_arbitrate_read(uint32_t addr) { - nv_log_verbose_only("MMIO read from address=0x%08x\n", addr); + uint32_t ret = 0x00; + + if (addr >= NV4_PTIMER_START && addr <= NV4_PTIMER_END) + ret = nv4_ptimer_read(addr); + else if (addr >= NV4_PRAMDAC_START && addr <= NV4_PRAMDAC_END) + ret = nv4_pramdac_read(addr); + + #ifdef NV_LOG + nv_register_t reg = nv_get_register(addr, &nv4_registers, sizeof(nv4_registers)/sizeof(nv4_registers[0])); + + if (reg) + { + if (reg->on_read) + ret = reg->on_read(); + + nv_log_verbose_only("Register read from 0x%08x value=%08x", addr, ret); + + } + #endif + } void nv4_mmio_arbitrate_write(uint32_t addr, uint32_t val) { - nv_log_verbose_only("MMIO write to address=0x%08x value %08x\n", addr, val); + if (addr >= NV4_PTIMER_START && addr <= NV4_PTIMER_END) + nv4_ptimer_write(addr, val); + else if (addr >= NV4_PRAMDAC_START && addr <= NV4_PRAMDAC_END) + nv4_pramdac_write(addr, val); + + #ifdef NV_LOG + nv_register_t reg = nv_get_register(addr, &nv4_registers, sizeof(nv4_registers)/sizeof(nv4_registers[0])); + + if (reg) + { + if (reg->on_write) + reg->on_write(val); + + nv_log_verbose_only("Register write from 0x%08x value=%08x", addr, val); + + } + #endif } // Determine if this address needs to be redirected to the SVGA subsystem. diff --git a/src/video/nv/nv4/nv4_debug_register_list.c b/src/video/nv/nv4/nv4_debug_register_list.c index e69de29bb..32516be0c 100644 --- a/src/video/nv/nv4/nv4_debug_register_list.c +++ b/src/video/nv/nv4/nv4_debug_register_list.c @@ -0,0 +1,46 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * NV4 debug register list + * + * + * Authors: Connor Hyde, I need a better email address ;^) + * + * Copyright 2024-2025 starfrost + */ +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/pci.h> +#include <86box/rom.h> +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv4.h> + +#ifdef NV_LOG + +nv_register_t nv4_registers[] = { + { NV4_PTIMER_INTR, "NV4 PTIMER - Interrupt Status", NULL, NULL}, + { NV4_PTIMER_INTR_EN, "NV4 PTIMER - Interrupt Enable", NULL, NULL,}, + { NV4_PTIMER_NUMERATOR, "NV4 PTIMER - Numerator", NULL, NULL, }, + { NV4_PTIMER_DENOMINATOR, "NV4 PTIMER - Denominator", NULL, NULL, }, + { NV4_PTIMER_TIME_0_NSEC, "NV4 PTIMER - Time0", NULL, NULL, }, + { NV4_PTIMER_TIME_1_NSEC, "NV4 PTIMER - Time1", NULL, NULL, }, + { NV4_PTIMER_ALARM_NSEC, "NV4 PTIMER - Alarm", NULL, NULL, }, + { NV4_PRAMDAC_VPLL_COEFF, "NV4 PRAMDAC - Pixel Clock Coefficient", NULL, NULL, }, + { NV4_PRAMDAC_NVPLL_COEFF, "NV4 PRAMDAC - GPU Core Clock Coefficient", NULL, NULL, }, + { NV4_PRAMDAC_MPLL_COEFF, "NV4 PRAMDAC - VRAM Clock Coefficient", NULL, NULL, }, + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value +}; + +#endif \ No newline at end of file diff --git a/src/video/nv/nv4/subsystems/nv4_pramdac.c b/src/video/nv/nv4/subsystems/nv4_pramdac.c index d8d4883ec..8460f6df4 100644 --- a/src/video/nv/nv4/subsystems/nv4_pramdac.c +++ b/src/video/nv/nv4/subsystems/nv4_pramdac.c @@ -14,3 +14,71 @@ * Copyright 2024-2025 starfrost */ +#include +#include +#include +#include +#include <86box/86box.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/rom.h> // DEPENDENT!!! +#include <86box/video.h> +#include <86box/nv/vid_nv.h> +#include <86box/nv/vid_nv4.h> + + +uint64_t nv4_pramdac_get_hz(uint32_t coeff, bool apply_divider) +{ + uint32_t m = coeff & 0xFF; + uint32_t n = (coeff >> 8) & 0xFF; + uint32_t p = (coeff >> 16) & 0x07; + + // Check clock base + uint32_t hz_base = (nv4->straps & (1 << NV4_STRAP_CRYSTAL)) ? 14318180 : 13500000; + uint32_t final_hz = (hz_base * n) / (m << p); + + // Check VCLK divider + + if (apply_divider) + { + if (nv4->pramdac.clk_coeff_select & (1 << NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO)) + final_hz >>= 1; + } + + return final_hz; +} + +void nv4_pramdac_set_vclk() +{ + uint64_t final_hz = nv4_pramdac_get_hz(nv4->pramdac.nvclk, false); + + //TODO: Everything + if (!nv4->nvbase.nv4_vclk_timer) + timer_set_delay_u64(nv4->nvbase.nv4_vclk_timer, final_hz / TIMER_USEC); + +} + +uint32_t nv4_pramdac_read(uint32_t address) +{ + uint32_t ret = 0x00; + + switch (address) + { + case NV4_PRAMDAC_VPLL_COEFF: // Pixel clock + ret = nv4->pramdac.vclk; + break; + case NV4_PRAMDAC_NVPLL_COEFF: // System clock + ret = nv4->pramdac.nvclk; + break; + case NV4_PRAMDAC_MPLL_COEFF: // Memory clock + ret = nv4->pramdac.mclk; + break; + + } +} + +void nv4_pramdac_write(uint32_t address, uint32_t data) +{ + +} From 8254a7f3aa3f1ce5327fe10960b67def005584a1 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sun, 21 Sep 2025 20:08:19 +0100 Subject: [PATCH 228/274] set the timer if it exists... --- src/video/nv/nv4/subsystems/nv4_pramdac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video/nv/nv4/subsystems/nv4_pramdac.c b/src/video/nv/nv4/subsystems/nv4_pramdac.c index 8460f6df4..0b8292796 100644 --- a/src/video/nv/nv4/subsystems/nv4_pramdac.c +++ b/src/video/nv/nv4/subsystems/nv4_pramdac.c @@ -54,7 +54,7 @@ void nv4_pramdac_set_vclk() uint64_t final_hz = nv4_pramdac_get_hz(nv4->pramdac.nvclk, false); //TODO: Everything - if (!nv4->nvbase.nv4_vclk_timer) + if (nv4->nvbase.nv4_vclk_timer) timer_set_delay_u64(nv4->nvbase.nv4_vclk_timer, final_hz / TIMER_USEC); } From b1e1596e2b4e1f59fd18ca895c6a3ba98019e7e6 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Tue, 23 Sep 2025 18:26:32 +0600 Subject: [PATCH 229/274] Remove other remnants of OpenGL ES support (#6213) * Remove other remnants of OpenGL ES support * Force OpenGL surface format if possible --- src/qt/qt_openglrenderer.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/qt/qt_openglrenderer.cpp b/src/qt/qt_openglrenderer.cpp index b74b74202..71f4e724c 100644 --- a/src/qt/qt_openglrenderer.cpp +++ b/src/qt/qt_openglrenderer.cpp @@ -814,10 +814,7 @@ OpenGLRenderer::OpenGLRenderer(QWidget *parent) format.setVersion(3, 2); #endif format.setProfile(QSurfaceFormat::OpenGLContextProfile::CoreProfile); - - if (QOpenGLContext::openGLModuleType() == QOpenGLContext::LibGLES) - format.setRenderableType(QSurfaceFormat::OpenGLES); - + format.setRenderableType(QSurfaceFormat::OpenGL); format.setSwapInterval(video_vsync ? 1 : 0); setFormat(format); From 1d9f84b02598fd207e4c6ee77b39789425dbea24 Mon Sep 17 00:00:00 2001 From: RichardG867 Date: Tue, 23 Sep 2025 12:34:46 -0300 Subject: [PATCH 230/274] Revert "Bump GLSL version of default shaders to 1.50" This reverts commit 999812e9b986229fc5be853419dfdd178b84058b. --- src/qt/qt_openglrenderer.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/qt/qt_openglrenderer.cpp b/src/qt/qt_openglrenderer.cpp index 71f4e724c..7f8a5e2fa 100644 --- a/src/qt/qt_openglrenderer.cpp +++ b/src/qt/qt_openglrenderer.cpp @@ -75,7 +75,11 @@ extern int video_focus_dim; extern int video_refresh_rate; const char* vertex_shader_default_tex_src = +#ifdef __APPLE__ "#version 150\n" +#else + "#version 130\n" +#endif "\n" "in vec4 VertexCoord;\n" "in vec2 TexCoord;\n" @@ -89,7 +93,11 @@ const char* vertex_shader_default_tex_src = "}\n"; const char* fragment_shader_default_tex_src = +#ifdef __APPLE__ "#version 150\n" +#else + "#version 130\n" +#endif "\n" "in vec2 texCoord;\n" "uniform sampler2D Texture;\n" @@ -103,7 +111,11 @@ const char* fragment_shader_default_tex_src = "}\n"; const char* vertex_shader_default_color_src = +#ifdef __APPLE__ "#version 150\n" +#else + "#version 130\n" +#endif "\n" "in vec4 VertexCoord;\n" "in vec4 Color;\n" @@ -117,7 +129,11 @@ const char* vertex_shader_default_color_src = "}\n"; const char* fragment_shader_default_color_src = +#ifdef __APPLE__ "#version 150\n" +#else + "#version 130\n" +#endif "\n" "in vec4 color;\n" "\n" From c2607f8671052b77a5423d1a589d3c44a27327e5 Mon Sep 17 00:00:00 2001 From: RichardG867 Date: Tue, 23 Sep 2025 12:35:04 -0300 Subject: [PATCH 231/274] Remoe FDD samples as they're now part of the romset --- ...-5_5.25_1.2MB_motor_loop_48000_16_1_PCM.wav | Bin 138308 -> 0 bytes ...5_5.25_1.2MB_motor_start_48000_16_1_PCM.wav | Bin 94708 -> 0 bytes ...-5_5.25_1.2MB_motor_stop_48000_16_1_PCM.wav | Bin 122478 -> 0 bytes ...acks_285ms_5ms_per_track_48000_16_1_PCM.wav | Bin 27378 -> 0 bytes ...acks_285ms_5ms_per_track_48000_16_1_PCM.wav | Bin 27378 -> 0 bytes ...-5_5.25_1.2MB_track_step_48000_16_1_PCM.wav | Bin 4232 -> 0 bytes ...FR_5.25_1.2MB_motor_loop_48000_16_1_PCM.wav | Bin 62924 -> 0 bytes ...R_5.25_1.2MB_motor_start_48000_16_1_PCM.wav | Bin 31146 -> 0 bytes ...FR_5.25_1.2MB_motor_stop_48000_16_1_PCM.wav | Bin 64278 -> 0 bytes ...FR_5.25_1.2MB_track_step_48000_16_1_PCM.wav | Bin 13188 -> 0 bytes ...ekupdown_80_tracks1100ms_48000_16_1_PCM.wav | Bin 106992 -> 0 bytes ...offseek_80_tracks_1000ms_48000_16_1_PCM.wav | Bin 94412 -> 0 bytes ...umi_seek_80_tracks_380ms_48000_16_1_PCM.wav | Bin 37754 -> 0 bytes ...umi_seek_80_tracks_495ms_48000_16_1_PCM.wav | Bin 47530 -> 0 bytes ...tsumi_spindle_motor_loop_48000_16_1_PCM.wav | Bin 172700 -> 0 bytes ...sumi_spindle_motor_start_48000_16_1_PCM.wav | Bin 44172 -> 0 bytes ...tsumi_spindle_motor_stop_48000_16_1_PCM.wav | Bin 50200 -> 0 bytes samples/mitsumi_track_step_48000_16_1_PCM.wav | Bin 8952 -> 0 bytes samples/readme.txt | 13 ------------- 19 files changed, 13 deletions(-) delete mode 100644 samples/Panasonic_JU-475-5_5.25_1.2MB_motor_loop_48000_16_1_PCM.wav delete mode 100644 samples/Panasonic_JU-475-5_5.25_1.2MB_motor_start_48000_16_1_PCM.wav delete mode 100644 samples/Panasonic_JU-475-5_5.25_1.2MB_motor_stop_48000_16_1_PCM.wav delete mode 100644 samples/Panasonic_JU-475-5_5.25_1.2MB_seekdown_40_tracks_285ms_5ms_per_track_48000_16_1_PCM.wav delete mode 100644 samples/Panasonic_JU-475-5_5.25_1.2MB_seekup_40_tracks_285ms_5ms_per_track_48000_16_1_PCM.wav delete mode 100644 samples/Panasonic_JU-475-5_5.25_1.2MB_track_step_48000_16_1_PCM.wav delete mode 100644 samples/TeacFD-55GFR_5.25_1.2MB_motor_loop_48000_16_1_PCM.wav delete mode 100644 samples/TeacFD-55GFR_5.25_1.2MB_motor_start_48000_16_1_PCM.wav delete mode 100644 samples/TeacFD-55GFR_5.25_1.2MB_motor_stop_48000_16_1_PCM.wav delete mode 100644 samples/TeacFD-55GFR_5.25_1.2MB_track_step_48000_16_1_PCM.wav delete mode 100644 samples/TeacFD_55GFR_5.25_1.2MB_seekupdown_80_tracks1100ms_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_offseek_80_tracks_1000ms_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_seek_80_tracks_380ms_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_seek_80_tracks_495ms_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_spindle_motor_loop_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_spindle_motor_start_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_spindle_motor_stop_48000_16_1_PCM.wav delete mode 100644 samples/mitsumi_track_step_48000_16_1_PCM.wav delete mode 100644 samples/readme.txt diff --git a/samples/Panasonic_JU-475-5_5.25_1.2MB_motor_loop_48000_16_1_PCM.wav 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-http://shiru.untergrund.net/files/flopster.zip - -Original samples can edited and used separately from the Flopster VSTi under the -Creative Commons Attribution (CC-BY) license terms. - -Installation instructions -- Currently these samples need to be manually copied to the 86box executable path under '/samples' - or to the same directory with 86box executable. -- The samples are 48kHz 16bit 1 channel PCM WAVE samples. Immersive86box code does not make any resampling, - and assumes that the host audio system is using 48kHz 16bit output. \ No newline at end of file From 288b6454eeeb0cbd813ad75a94a6efdc112d6be9 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 23 Sep 2025 17:55:46 +0200 Subject: [PATCH 232/274] AdLib Gold: Correctly use separate pseudo-stereo X and Y for the two sources. --- src/include/86box/filters.h | 18 +++++++++--------- src/sound/snd_adlibgold.c | 6 +++--- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/include/86box/filters.h b/src/include/86box/filters.h index d11e79512..3e20fa653 100644 --- a/src/include/86box/filters.h +++ b/src/include/86box/filters.h @@ -75,7 +75,7 @@ adgold_lowpass_iir(int c, int i, float NewSample) /* fc=56Hz */ static inline float -adgold_pseudo_stereo_iir(float NewSample) +adgold_pseudo_stereo_iir(int i, float NewSample) { float ACoef[NCoef + 1] = { 0.00001409030866231767, @@ -89,23 +89,23 @@ adgold_pseudo_stereo_iir(float NewSample) 0.98738361004063568000 }; - static float y[NCoef + 1]; /* output samples */ - static float x[NCoef + 1]; /* input samples */ + static float y[2][NCoef + 1]; /* output samples */ + static float x[2][NCoef + 1]; /* input samples */ int n; /* shift the old samples */ for (n = NCoef; n > 0; n--) { - x[n] = x[n - 1]; - y[n] = y[n - 1]; + x[i][n] = x[i][n - 1]; + y[i][n] = y[i][n - 1]; } /* Calculate the new output */ - x[0] = NewSample; - y[0] = ACoef[0] * x[0]; + x[i][0] = NewSample; + y[i][0] = ACoef[0] * x[i][0]; for (n = 1; n <= NCoef; n++) - y[0] += ACoef[n] * x[n] - BCoef[n] * y[n]; + y[i][0] += ACoef[n] * x[i][n] - BCoef[n] * y[i][n]; - return y[0]; + return y[i][0]; } /* fc=3.2kHz - probably incorrect */ diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index 360da3fec..3be304cd7 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -82,7 +82,7 @@ typedef struct adgold_t { int treble; int bass; - int16_t opl_buffer[SOUNDBUFLEN * 2]; + int16_t opl_buffer[MUSICBUFLEN * 2]; int16_t mma_buffer[2][SOUNDBUFLEN]; int pos; @@ -829,7 +829,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) /*Filter left channel, leave right channel unchanged*/ /*Filter cutoff is largely a guess*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] += adgold_pseudo_stereo_iir(adgold_buffer[c]); + adgold_buffer[c] += adgold_pseudo_stereo_iir(0, adgold_buffer[c]); break; case 0x18: /*Spatial stereo*/ /*Quite probably wrong, I only have the diagram in the TDA8425 datasheet @@ -944,7 +944,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) /*Filter left channel, leave right channel unchanged*/ /*Filter cutoff is largely a guess*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] += adgold_pseudo_stereo_iir(adgold_buffer[c]); + adgold_buffer[c] += adgold_pseudo_stereo_iir(1, adgold_buffer[c]); break; case 0x18: /*Spatial stereo*/ /*Quite probably wrong, I only have the diagram in the TDA8425 datasheet From 236007b4c8571c474fc808c5bcd875390941a4c8 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Tue, 23 Sep 2025 22:31:12 +0600 Subject: [PATCH 233/274] Force AlphaBuffer to be 0 (#6217) --- src/qt/qt_openglrenderer.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/qt/qt_openglrenderer.cpp b/src/qt/qt_openglrenderer.cpp index 7f8a5e2fa..492acb630 100644 --- a/src/qt/qt_openglrenderer.cpp +++ b/src/qt/qt_openglrenderer.cpp @@ -832,6 +832,7 @@ OpenGLRenderer::OpenGLRenderer(QWidget *parent) format.setProfile(QSurfaceFormat::OpenGLContextProfile::CoreProfile); format.setRenderableType(QSurfaceFormat::OpenGL); format.setSwapInterval(video_vsync ? 1 : 0); + format.setAlphaBufferSize(0); setFormat(format); From c71811f57994e624ae1aea55b05e2b845af1727d Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 23 Sep 2025 19:36:26 +0200 Subject: [PATCH 234/274] Attempt to halve the output volume. --- src/sound/snd_adlibgold.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index 3be304cd7..e41726b00 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -853,7 +853,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) int32_t highpass; /*Output is deliberately halved to avoid clipping*/ - temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 17; + temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 18; lowpass = adgold_lowpass_iir(0, 0, temp); highpass = adgold_highpass_iir(0, 0, temp); if (adgold->bass > 6) @@ -870,7 +870,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) temp = 32767; buffer[c] += temp; - temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 17; + temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 18; lowpass = adgold_lowpass_iir(0, 1, temp); highpass = adgold_highpass_iir(0, 1, temp); if (adgold->bass > 6) @@ -968,7 +968,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) int32_t highpass; /*Output is deliberately halved to avoid clipping*/ - temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 17; + temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 18; lowpass = adgold_lowpass_iir(1, 0, temp); highpass = adgold_highpass_iir(1, 0, temp); if (adgold->bass > 6) @@ -985,7 +985,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) temp = 32767; buffer[c] += temp; - temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 17; + temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 18; lowpass = adgold_lowpass_iir(1, 1, temp); highpass = adgold_highpass_iir(1, 1, temp); if (adgold->bass > 6) From a87bcd410e920a6269a63b828b1237538b0894a9 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Tue, 23 Sep 2025 19:49:15 +0200 Subject: [PATCH 235/274] AdLib Gold changes of the day (September 23rd, 2025) (#6218) 1. Make sure the check to the Surround module is properly placed when disabled/enabled. 2. Replace local adgold_buffer with opl_buffer from its struct to improve the audio output and less clipping. --- src/sound/snd_adlibgold.c | 71 +++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 41 deletions(-) diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index e41726b00..f708b6967 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -291,7 +291,8 @@ adgold_write(uint16_t addr, uint8_t val, void *priv) case 0x18: /*Surround*/ adgold->adgold_38x_regs[0x18] = val; - ym7128_write(&adgold->ym7128, val); + if (adgold->surround_enabled) + ym7128_write(&adgold->ym7128, val); break; default: @@ -782,34 +783,30 @@ static void adgold_get_buffer(int32_t *buffer, int len, void *priv) { adgold_t *adgold = (adgold_t *) priv; - int16_t *adgold_buffer = malloc(sizeof(int16_t) * len * 2); - if (adgold_buffer == NULL) - fatal("adgold_buffer = NULL"); - int c; adgold_update(adgold); for (c = 0; c < len * 2; c += 2) { - adgold_buffer[c] = ((adgold->mma_buffer[0][c >> 1] * adgold->samp_vol_l) >> 7) / 4; - adgold_buffer[c + 1] = ((adgold->mma_buffer[1][c >> 1] * adgold->samp_vol_r) >> 7) / 4; + adgold->opl_buffer[c] = ((adgold->mma_buffer[0][c >> 1] * adgold->samp_vol_l) >> 7) / 4; + adgold->opl_buffer[c + 1] = ((adgold->mma_buffer[1][c >> 1] * adgold->samp_vol_r) >> 7) / 4; } if (adgold->surround_enabled) - ym7128_apply(&adgold->ym7128, adgold_buffer, len); + ym7128_apply(&adgold->ym7128, adgold->opl_buffer, len); switch (adgold->adgold_38x_regs[0x8] & 6) { case 0: for (c = 0; c < len * 2; c++) - adgold_buffer[c] = 0; + adgold->opl_buffer[c] = 0; break; case 2: /*Left channel only*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c + 1] = adgold_buffer[c]; + adgold->opl_buffer[c + 1] = adgold->opl_buffer[c]; break; case 4: /*Right channel only*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] = adgold_buffer[c + 1]; + adgold->opl_buffer[c] = adgold->opl_buffer[c + 1]; break; case 6: /*Left and right channels*/ break; @@ -821,7 +818,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) switch (adgold->adgold_38x_regs[0x8] & 0x18) { case 0x00: /*Forced mono*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] = adgold_buffer[c + 1] = ((int32_t) adgold_buffer[c] + (int32_t) adgold_buffer[c + 1]) / 2; + adgold->opl_buffer[c] = adgold->opl_buffer[c + 1] = ((int32_t) adgold->opl_buffer[c] + (int32_t) adgold->opl_buffer[c + 1]) / 2; break; case 0x08: /*Linear stereo*/ break; @@ -829,17 +826,17 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) /*Filter left channel, leave right channel unchanged*/ /*Filter cutoff is largely a guess*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] += adgold_pseudo_stereo_iir(0, adgold_buffer[c]); + adgold->opl_buffer[c] += adgold_pseudo_stereo_iir(0, adgold->opl_buffer[c]); break; case 0x18: /*Spatial stereo*/ /*Quite probably wrong, I only have the diagram in the TDA8425 datasheet and a very vague understanding of how op-amps work to go on*/ for (c = 0; c < len * 2; c += 2) { - int16_t l = adgold_buffer[c]; - int16_t r = adgold_buffer[c + 1]; + int16_t l = adgold->opl_buffer[c]; + int16_t r = adgold->opl_buffer[c + 1]; - adgold_buffer[c] += (r / 3) + ((l * 2) / 3); - adgold_buffer[c + 1] += (l / 3) + ((r * 2) / 3); + adgold->opl_buffer[c] += (r / 3) + ((l * 2) / 3); + adgold->opl_buffer[c + 1] += (l / 3) + ((r * 2) / 3); } break; @@ -853,7 +850,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) int32_t highpass; /*Output is deliberately halved to avoid clipping*/ - temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 18; + temp = ((int32_t) adgold->opl_buffer[c] * adgold->vol_l) >> 18; lowpass = adgold_lowpass_iir(0, 0, temp); highpass = adgold_highpass_iir(0, 0, temp); if (adgold->bass > 6) @@ -870,7 +867,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) temp = 32767; buffer[c] += temp; - temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 18; + temp = ((int32_t) adgold->opl_buffer[c + 1] * adgold->vol_r) >> 18; lowpass = adgold_lowpass_iir(0, 1, temp); highpass = adgold_highpass_iir(0, 1, temp); if (adgold->bass > 6) @@ -889,42 +886,36 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) } adgold->pos = 0; - - free(adgold_buffer); } static void adgold_get_music_buffer(int32_t *buffer, int len, void *priv) { adgold_t *adgold = (adgold_t *) priv; - int16_t *adgold_buffer = malloc(sizeof(int16_t) * len * 2); - if (adgold_buffer == NULL) - fatal("adgold_buffer = NULL"); - int c; const int32_t *opl_buf = adgold->opl.update(adgold->opl.priv); for (c = 0; c < len * 2; c += 2) { - adgold_buffer[c] = ((opl_buf[c] * adgold->fm_vol_l) >> 7) / 2; - adgold_buffer[c + 1] = ((opl_buf[c + 1] * adgold->fm_vol_r) >> 7) / 2; + adgold->opl_buffer[c] = ((opl_buf[c] * adgold->fm_vol_l) >> 7) / 2; + adgold->opl_buffer[c + 1] = ((opl_buf[c + 1] * adgold->fm_vol_r) >> 7) / 2; } if (adgold->surround_enabled) - ym7128_apply(&adgold->ym7128, adgold_buffer, len); + ym7128_apply(&adgold->ym7128, adgold->opl_buffer, len); switch (adgold->adgold_38x_regs[0x8] & 6) { case 0: for (c = 0; c < len * 2; c++) - adgold_buffer[c] = 0; + adgold->opl_buffer[c] = 0; break; case 2: /*Left channel only*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c + 1] = adgold_buffer[c]; + adgold->opl_buffer[c + 1] = adgold->opl_buffer[c]; break; case 4: /*Right channel only*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] = adgold_buffer[c + 1]; + adgold->opl_buffer[c] = adgold->opl_buffer[c + 1]; break; case 6: /*Left and right channels*/ break; @@ -936,7 +927,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) switch (adgold->adgold_38x_regs[0x8] & 0x18) { case 0x00: /*Forced mono*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] = adgold_buffer[c + 1] = ((int32_t) adgold_buffer[c] + (int32_t) adgold_buffer[c + 1]) / 2; + adgold->opl_buffer[c] = adgold->opl_buffer[c + 1] = ((int32_t) adgold->opl_buffer[c] + (int32_t) adgold->opl_buffer[c + 1]) / 2; break; case 0x08: /*Linear stereo*/ break; @@ -944,17 +935,17 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) /*Filter left channel, leave right channel unchanged*/ /*Filter cutoff is largely a guess*/ for (c = 0; c < len * 2; c += 2) - adgold_buffer[c] += adgold_pseudo_stereo_iir(1, adgold_buffer[c]); + adgold->opl_buffer[c] += adgold_pseudo_stereo_iir(1, adgold->opl_buffer[c]); break; case 0x18: /*Spatial stereo*/ /*Quite probably wrong, I only have the diagram in the TDA8425 datasheet and a very vague understanding of how op-amps work to go on*/ for (c = 0; c < len * 2; c += 2) { - int16_t l = adgold_buffer[c]; - int16_t r = adgold_buffer[c + 1]; + int16_t l = adgold->opl_buffer[c]; + int16_t r = adgold->opl_buffer[c + 1]; - adgold_buffer[c] += (r / 3) + ((l * 2) / 3); - adgold_buffer[c + 1] += (l / 3) + ((r * 2) / 3); + adgold->opl_buffer[c] += (r / 3) + ((l * 2) / 3); + adgold->opl_buffer[c + 1] += (l / 3) + ((r * 2) / 3); } break; @@ -968,7 +959,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) int32_t highpass; /*Output is deliberately halved to avoid clipping*/ - temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 18; + temp = ((int32_t) adgold->opl_buffer[c] * adgold->vol_l) >> 18; lowpass = adgold_lowpass_iir(1, 0, temp); highpass = adgold_highpass_iir(1, 0, temp); if (adgold->bass > 6) @@ -985,7 +976,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) temp = 32767; buffer[c] += temp; - temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 18; + temp = ((int32_t) adgold->opl_buffer[c + 1] * adgold->vol_r) >> 18; lowpass = adgold_lowpass_iir(1, 1, temp); highpass = adgold_highpass_iir(1, 1, temp); if (adgold->bass > 6) @@ -1004,8 +995,6 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) } adgold->opl.reset_buffer(adgold->opl.priv); - - free(adgold_buffer); } static void From 087a0056640d944c926f8d5ea15f201add3de8a4 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 23 Sep 2025 20:46:24 +0200 Subject: [PATCH 236/274] More AdLib Gold fixes. --- src/include/86box/snd_ym7128.h | 12 ++++++------ src/sound/snd_adlibgold.c | 35 +++++++++++++++++----------------- src/sound/snd_ym7128.c | 24 +++++++++++------------ 3 files changed, 36 insertions(+), 35 deletions(-) diff --git a/src/include/86box/snd_ym7128.h b/src/include/86box/snd_ym7128.h index a0796b1fa..f0657425f 100644 --- a/src/include/86box/snd_ym7128.h +++ b/src/include/86box/snd_ym7128.h @@ -19,18 +19,18 @@ typedef struct ym7128_t { int c1; int t[9]; - int16_t filter_dat; - int16_t prev_l; - int16_t prev_r; + int16_t filter_dat[2]; + int16_t prev_l[2]; + int16_t prev_r[2]; - int16_t delay_buffer[2400]; - int delay_pos; + int16_t delay_buffer[2][2400]; + int delay_pos[2]; int16_t last_samp; } ym7128_t; void ym7128_init(ym7128_t *ym7128); void ym7128_write(ym7128_t *ym7128, uint8_t val); -void ym7128_apply(ym7128_t *ym7128, int16_t *buffer, int len); +void ym7128_apply(ym7128_t *ym7128, int16_t *buffer, int i, int len); #endif /*SOUND_YM7128_H*/ diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index f708b6967..0181db72e 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -82,6 +82,7 @@ typedef struct adgold_t { int treble; int bass; + int16_t samp_buffer[SOUNDBUFLEN * 2]; int16_t opl_buffer[MUSICBUFLEN * 2]; int16_t mma_buffer[2][SOUNDBUFLEN]; @@ -788,25 +789,25 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) adgold_update(adgold); for (c = 0; c < len * 2; c += 2) { - adgold->opl_buffer[c] = ((adgold->mma_buffer[0][c >> 1] * adgold->samp_vol_l) >> 7) / 4; - adgold->opl_buffer[c + 1] = ((adgold->mma_buffer[1][c >> 1] * adgold->samp_vol_r) >> 7) / 4; + adgold->samp_buffer[c] = ((adgold->mma_buffer[0][c >> 1] * adgold->samp_vol_l) >> 7) / 4; + adgold->samp_buffer[c + 1] = ((adgold->mma_buffer[1][c >> 1] * adgold->samp_vol_r) >> 7) / 4; } if (adgold->surround_enabled) - ym7128_apply(&adgold->ym7128, adgold->opl_buffer, len); + ym7128_apply(&adgold->ym7128, adgold->samp_buffer, 0, len); switch (adgold->adgold_38x_regs[0x8] & 6) { case 0: for (c = 0; c < len * 2; c++) - adgold->opl_buffer[c] = 0; + adgold->samp_buffer[c] = 0; break; case 2: /*Left channel only*/ for (c = 0; c < len * 2; c += 2) - adgold->opl_buffer[c + 1] = adgold->opl_buffer[c]; + adgold->samp_buffer[c + 1] = adgold->samp_buffer[c]; break; case 4: /*Right channel only*/ for (c = 0; c < len * 2; c += 2) - adgold->opl_buffer[c] = adgold->opl_buffer[c + 1]; + adgold->samp_buffer[c] = adgold->samp_buffer[c + 1]; break; case 6: /*Left and right channels*/ break; @@ -818,7 +819,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) switch (adgold->adgold_38x_regs[0x8] & 0x18) { case 0x00: /*Forced mono*/ for (c = 0; c < len * 2; c += 2) - adgold->opl_buffer[c] = adgold->opl_buffer[c + 1] = ((int32_t) adgold->opl_buffer[c] + (int32_t) adgold->opl_buffer[c + 1]) / 2; + adgold->samp_buffer[c] = adgold->samp_buffer[c + 1] = ((int32_t) adgold->samp_buffer[c] + (int32_t) adgold->samp_buffer[c + 1]) / 2; break; case 0x08: /*Linear stereo*/ break; @@ -826,17 +827,17 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) /*Filter left channel, leave right channel unchanged*/ /*Filter cutoff is largely a guess*/ for (c = 0; c < len * 2; c += 2) - adgold->opl_buffer[c] += adgold_pseudo_stereo_iir(0, adgold->opl_buffer[c]); + adgold->samp_buffer[c] += adgold_pseudo_stereo_iir(0, adgold->samp_buffer[c]); break; case 0x18: /*Spatial stereo*/ /*Quite probably wrong, I only have the diagram in the TDA8425 datasheet and a very vague understanding of how op-amps work to go on*/ for (c = 0; c < len * 2; c += 2) { - int16_t l = adgold->opl_buffer[c]; - int16_t r = adgold->opl_buffer[c + 1]; + int16_t l = adgold->samp_buffer[c]; + int16_t r = adgold->samp_buffer[c + 1]; - adgold->opl_buffer[c] += (r / 3) + ((l * 2) / 3); - adgold->opl_buffer[c + 1] += (l / 3) + ((r * 2) / 3); + adgold->samp_buffer[c] += (r / 3) + ((l * 2) / 3); + adgold->samp_buffer[c + 1] += (l / 3) + ((r * 2) / 3); } break; @@ -850,7 +851,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) int32_t highpass; /*Output is deliberately halved to avoid clipping*/ - temp = ((int32_t) adgold->opl_buffer[c] * adgold->vol_l) >> 18; + temp = ((int32_t) adgold->samp_buffer[c] * adgold->vol_l) >> 17; lowpass = adgold_lowpass_iir(0, 0, temp); highpass = adgold_highpass_iir(0, 0, temp); if (adgold->bass > 6) @@ -867,7 +868,7 @@ adgold_get_buffer(int32_t *buffer, int len, void *priv) temp = 32767; buffer[c] += temp; - temp = ((int32_t) adgold->opl_buffer[c + 1] * adgold->vol_r) >> 18; + temp = ((int32_t) adgold->samp_buffer[c + 1] * adgold->vol_r) >> 17; lowpass = adgold_lowpass_iir(0, 1, temp); highpass = adgold_highpass_iir(0, 1, temp); if (adgold->bass > 6) @@ -902,7 +903,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) } if (adgold->surround_enabled) - ym7128_apply(&adgold->ym7128, adgold->opl_buffer, len); + ym7128_apply(&adgold->ym7128, adgold->opl_buffer, 1, len); switch (adgold->adgold_38x_regs[0x8] & 6) { case 0: @@ -959,7 +960,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) int32_t highpass; /*Output is deliberately halved to avoid clipping*/ - temp = ((int32_t) adgold->opl_buffer[c] * adgold->vol_l) >> 18; + temp = ((int32_t) adgold->opl_buffer[c] * adgold->vol_l) >> 17; lowpass = adgold_lowpass_iir(1, 0, temp); highpass = adgold_highpass_iir(1, 0, temp); if (adgold->bass > 6) @@ -976,7 +977,7 @@ adgold_get_music_buffer(int32_t *buffer, int len, void *priv) temp = 32767; buffer[c] += temp; - temp = ((int32_t) adgold->opl_buffer[c + 1] * adgold->vol_r) >> 18; + temp = ((int32_t) adgold->opl_buffer[c + 1] * adgold->vol_r) >> 17; lowpass = adgold_lowpass_iir(1, 1, temp); highpass = adgold_highpass_iir(1, 1, temp); if (adgold->bass > 6) diff --git a/src/sound/snd_ym7128.c b/src/sound/snd_ym7128.c index 59e5691e9..08b33f414 100644 --- a/src/sound/snd_ym7128.c +++ b/src/sound/snd_ym7128.c @@ -111,10 +111,10 @@ ym7128_write(ym7128_t *ym7128, uint8_t val) ym7128->a0 = new_a0; } -#define GET_DELAY_SAMPLE(ym7128, offset) (((ym7128->delay_pos - offset) < 0) ? ym7128->delay_buffer[(ym7128->delay_pos - offset) + 2400] : ym7128->delay_buffer[ym7128->delay_pos - offset]) +#define GET_DELAY_SAMPLE(ym7128, offset) (((ym7128->delay_pos[i] - offset) < 0) ? ym7128->delay_buffer[i][(ym7128->delay_pos[i] - offset) + 2400] : ym7128->delay_buffer[i][ym7128->delay_pos[i] - offset]) void -ym7128_apply(ym7128_t *ym7128, int16_t *buffer, int len) +ym7128_apply(ym7128_t *ym7128, int16_t *buffer, int i, int len) { for (int c = 0; c < len * 2; c += 4) { /*YM7128 samples a mono stream at ~24 kHz, so downsample*/ @@ -125,13 +125,13 @@ ym7128_apply(ym7128_t *ym7128, int16_t *buffer, int len) int32_t samp_r = 0; filter_temp = GET_DELAY_SAMPLE(ym7128, ym7128->t[0]); - filter_out = ((filter_temp * ym7128->c0) >> 11) + ((ym7128->filter_dat * ym7128->c1) >> 11); + filter_out = ((filter_temp * ym7128->c0) >> 11) + ((ym7128->filter_dat[i] * ym7128->c1) >> 11); filter_out = (filter_out * ym7128->vc) >> 16; samp = (samp * ym7128->vm) >> 16; samp += filter_out; - ym7128->delay_buffer[ym7128->delay_pos] = samp; + ym7128->delay_buffer[i][ym7128->delay_pos[i]] = samp; for (uint8_t d = 0; d < 8; d++) { samp_l += (GET_DELAY_SAMPLE(ym7128, ym7128->t[d + 1]) * ym7128->gl[d]) >> 16; @@ -141,17 +141,17 @@ ym7128_apply(ym7128_t *ym7128, int16_t *buffer, int len) samp_l = (samp_l * ym7128->vl * 2) >> 16; samp_r = (samp_r * ym7128->vr * 2) >> 16; - buffer[c] += (samp_l + (int32_t) ym7128->prev_l) / 2; - buffer[c + 1] += (samp_r + (int32_t) ym7128->prev_r) / 2; + buffer[c] += (samp_l + (int32_t) ym7128->prev_l[i]) / 2; + buffer[c + 1] += (samp_r + (int32_t) ym7128->prev_r[i]) / 2; buffer[c + 2] += samp_l; buffer[c + 3] += samp_r; - ym7128->delay_pos++; - if (ym7128->delay_pos >= 2400) - ym7128->delay_pos = 0; + ym7128->delay_pos[i]++; + if (ym7128->delay_pos[i] >= 2400) + ym7128->delay_pos[i] = 0; - ym7128->filter_dat = filter_temp; - ym7128->prev_l = samp_l; - ym7128->prev_r = samp_r; + ym7128->filter_dat[i] = filter_temp; + ym7128->prev_l[i] = samp_l; + ym7128->prev_r[i] = samp_r; } } From d99d052b826d5306679728cad3b8b30967f7348c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Sep 2025 01:16:20 +0200 Subject: [PATCH 237/274] AdLib Gold: Use the YMF289. --- src/sound/snd_adlibgold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index 0181db72e..4c4c17341 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -1063,7 +1063,7 @@ adgold_init(UNUSED(const device_t *info)) adgold->surround_enabled = device_get_config_int("surround"); adgold->gameport_enabled = device_get_config_int("gameport"); - fm_driver_get(FM_YMF262, &adgold->opl); + fm_driver_get(FM_YMF289, &adgold->opl); if (adgold->surround_enabled) ym7128_init(&adgold->ym7128); From ba9c1732f7907d99b6986aadb95bbc183b586bc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Wed, 24 Sep 2025 01:41:00 +0200 Subject: [PATCH 238/274] Actually, it's 289B. --- src/sound/snd_adlibgold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index 4c4c17341..870e473b0 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -1063,7 +1063,7 @@ adgold_init(UNUSED(const device_t *info)) adgold->surround_enabled = device_get_config_int("surround"); adgold->gameport_enabled = device_get_config_int("gameport"); - fm_driver_get(FM_YMF289, &adgold->opl); + fm_driver_get(FM_YMF289B, &adgold->opl); if (adgold->surround_enabled) ym7128_init(&adgold->ym7128); From d29b0d51833584fd47a6111fd95bce1c6e456311 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Wed, 24 Sep 2025 17:59:29 +0600 Subject: [PATCH 239/274] Set up default surface formats before QApplication creation (#6221) --- src/qt/qt_main.cpp | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/qt/qt_main.cpp b/src/qt/qt_main.cpp index a48fde924..d667cfdb9 100644 --- a/src/qt/qt_main.cpp +++ b/src/qt/qt_main.cpp @@ -542,6 +542,17 @@ main(int argc, char *argv[]) #endif QApplication::setAttribute(Qt::AA_UseDesktopOpenGL); + QSurfaceFormat fmt = QSurfaceFormat::defaultFormat(); + fmt.setSwapInterval(0); + fmt.setProfile(QSurfaceFormat::OpenGLContextProfile::CoreProfile); + fmt.setRenderableType(QSurfaceFormat::OpenGL); +#ifdef Q_OS_MACOS + fmt.setVersion(4, 1); +#else + fmt.setVersion(3, 2); +#endif + QSurfaceFormat::setDefaultFormat(fmt); + QApplication app(argc, argv); QLocale::setDefault(QLocale::C); setlocale(LC_NUMERIC, "C"); @@ -573,9 +584,6 @@ main(int argc, char *argv[]) Q_INIT_RESOURCE(qt_resources); Q_INIT_RESOURCE(qt_translations); - QSurfaceFormat fmt = QSurfaceFormat::defaultFormat(); - fmt.setSwapInterval(0); - QSurfaceFormat::setDefaultFormat(fmt); #ifdef __APPLE__ CocoaEventFilter cocoafilter; From 01c410479b57b9fdcbc7fbd68b00ac9aec8766a3 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Sep 2025 15:16:59 +0200 Subject: [PATCH 240/274] RTL8019AS and ISA PnP fixes: fixes PNPODI.COM. RTL8019AS now detects the card but thinks there's an IRQ conflict. --- src/device/isapnp.c | 60 ++++++++- src/include/86box/isapnp.h | 30 +++-- src/mem/nmc93cxx.c | 1 + src/network/net_dp8390.c | 2 +- src/network/net_ne2000.c | 256 +++++++++++++++++++++++++++++-------- 5 files changed, 274 insertions(+), 75 deletions(-) diff --git a/src/device/isapnp.c b/src/device/isapnp.c index 64f6a1d5f..675d9adf7 100644 --- a/src/device/isapnp.c +++ b/src/device/isapnp.c @@ -25,6 +25,7 @@ #include <86box/io.h> #include <86box/isapnp.h> #include <86box/plat_unused.h> +#include "cpu.h" #define CHECK_CURRENT_LD() \ if (!ld) { \ @@ -42,6 +43,11 @@ const uint8_t isapnp_init_key[32] = { 0x6A, 0xB5, 0xDA, 0xED, 0xF6, 0xFB 0xDF, 0x6F, 0x37, 0x1B, 0x0D, 0x86, 0xC3, 0x61, 0xB0, 0x58, 0x2C, 0x16, 0x8B, 0x45, 0xA2, 0xD1, 0xE8, 0x74, 0x3A, 0x9D, 0xCE, 0xE7, 0x73, 0x39 }; +/* Required for the RTL8019AS. */ +const uint8_t isapnp_init_key2[32] = { 0xDA, 0x6D, 0x36, 0x1B, 0x8D, 0x46, 0x23, 0x91, + 0x48, 0xA4, 0xD2, 0x69, 0x34, 0x9A, 0x4D, 0x26, + 0x13, 0x89, 0x44, 0xA2, 0x51, 0x28, 0x94, 0xCA, + 0x65, 0x32, 0x19, 0x0C, 0x86, 0x43, 0xA1, 0x50 }; static const device_t isapnp_device; #ifdef ENABLE_ISAPNP_LOG @@ -85,11 +91,13 @@ typedef struct _isapnp_card_ { uint8_t enable; uint8_t state; uint8_t csn; + uint8_t csnsav; uint8_t ld; uint8_t id_checksum; uint8_t serial_read; uint8_t serial_read_pair; uint8_t serial_read_pos; + uint8_t is_rt; uint8_t *rom; uint16_t rom_pos; uint16_t rom_size; @@ -109,6 +117,7 @@ typedef struct _isapnp_card_ { typedef struct { uint8_t in_isolation; + uint8_t using_key2; uint8_t reg; uint8_t key_pos : 5; uint16_t read_data_addr; @@ -166,7 +175,7 @@ isapnp_device_config_changed(isapnp_card_t *card, isapnp_device_t *ld) } for (uint8_t i = 0; i < 8; i++) { reg_base = 0x60 + (2 * i); - if (ld->regs[0x31] & 0x02) + if (!(ld->regs[0x30] & 0x01) && (ld->regs[0x31] & 0x02)) card->config.io[i].base = 0; /* let us handle I/O range check reads */ else card->config.io[i].base = (ld->regs[reg_base] << 8) | ld->regs[reg_base + 1]; @@ -288,7 +297,7 @@ isapnp_read_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uint case 0x01: /* Serial Isolation */ card = dev->first_card; while (card) { - if (card->enable && card->rom && (card->state == PNP_STATE_ISOLATION)) + if (card->enable && (card->rom != NULL) && (card->state == PNP_STATE_ISOLATION)) break; card = card->next; } @@ -374,6 +383,7 @@ vendor_defined: default: if (reg >= 0x30) { + CHECK_CURRENT_CARD(); CHECK_CURRENT_LD(); isapnp_log("ISAPnP: Read register %02X from CSN %02X device %02X\n", reg, card->csn, ld->number); ret = ld->regs[reg]; @@ -397,7 +407,8 @@ isapnp_read_data(UNUSED(uint16_t addr), void *priv) card = card->next; } - isapnp_log("ISAPnP: read_data() => "); + // isapnp_log("ISAPnP: read_data() => "); + isapnp_log("[%04X:%08X] ISAPnP: read_data() => ", CS, cpu_state.pc); return isapnp_read_common(dev, card, dev->current_ld, dev->reg); } @@ -432,12 +443,14 @@ isapnp_write_addr(UNUSED(uint16_t addr), uint8_t val, void *priv) if (card->state == PNP_STATE_WAIT_FOR_KEY) { /* checking only the first card should be fine */ /* Check written value against LFSR key. */ - if (val == isapnp_init_key[dev->key_pos]) { + if ((val == isapnp_init_key[dev->key_pos]) || (val == isapnp_init_key2[dev->key_pos])) { + dev->using_key2 = (val == isapnp_init_key2[dev->key_pos]); dev->key_pos++; if (!dev->key_pos) { isapnp_log("ISAPnP: Key unlocked, putting cards to SLEEP\n"); while (card) { - if (card->enable && (card->enable != ISAPNP_CARD_NO_KEY) && (card->state == PNP_STATE_WAIT_FOR_KEY)) + int is_rt = (!dev->using_key2 || card->is_rt); + if (card->enable && is_rt && (card->enable != ISAPNP_CARD_NO_KEY) && (card->state == PNP_STATE_WAIT_FOR_KEY)) card->state = PNP_STATE_SLEEP; card = card->next; } @@ -493,6 +506,7 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin card->state = PNP_STATE_WAIT_FOR_KEY; card = card->next; } + dev->key_pos = 0; } if (val & 0x04) { isapnp_log("ISAPnP: Reset CSN\n"); @@ -566,6 +580,20 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin ld->regs[reg] = val & 0x01; isapnp_device_config_changed(card, ld); + for (uint8_t i = 0; i < 8; i++) { + if (!ld->io_len[i]) + continue; + + io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)]; + if (val & 0x01) { + if (ld->regs[0x31] & 0x02) + io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); + } else { + if (ld->regs[0x31] & 0x02) + io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); + } + } + break; case 0x31: /* I/O Range Check */ @@ -578,7 +606,7 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)]; if (ld->regs[reg] & 0x02) io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); - if (val & 0x02) + if ((val & 0x02) && !(ld->regs[0x30] & 0x01)) io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); } @@ -601,6 +629,7 @@ vendor_defined: default: if (reg >= 0x40) { + CHECK_CURRENT_CARD(); CHECK_CURRENT_LD(); isapnp_log("ISAPnP: Write %02X to register %02X on CSN %02X device %02X\n", val, reg, card->csn, ld->number); @@ -670,7 +699,8 @@ isapnp_write_data(UNUSED(uint16_t addr), uint8_t val, void *priv) } } - isapnp_log("ISAPnP: write_data(%02X) => ", val); + // isapnp_log("ISAPnP: write_data(%02X) => ", val); + isapnp_log("[%04X:%08X] ISAPnP: write_data(%02X) => ", CS, cpu_state.pc, val); isapnp_write_common(dev, card, dev->current_ld, dev->reg, val); } @@ -1163,6 +1193,22 @@ isapnp_read_reg(void *priv, uint8_t ldn, uint8_t reg) return isapnp_read_common(device_get_priv(&isapnp_device), card, ld, reg); } +void +isapnp_set_rt(void *priv, uint8_t is_rt) +{ + isapnp_card_t *card = (isapnp_card_t *) priv; + + card->is_rt = is_rt; +} + +uint8_t * +isapnp_get_csnsav(void *priv) +{ + isapnp_card_t *card = (isapnp_card_t *) priv; + + return &card->csnsav; +} + void isapnp_write_reg(void *priv, uint8_t ldn, uint8_t reg, uint8_t val) { diff --git a/src/include/86box/isapnp.h b/src/include/86box/isapnp.h index 6f7eb1185..2ffbd2d66 100644 --- a/src/include/86box/isapnp.h +++ b/src/include/86box/isapnp.h @@ -57,19 +57,21 @@ typedef struct isapnp_device_config_t { extern const uint8_t isapnp_init_key[32]; -void *isapnp_add_card(uint8_t *rom, uint16_t rom_size, - void (*config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv), - void (*csn_changed)(uint8_t csn, void *priv), - uint8_t (*read_vendor_reg)(uint8_t ld, uint8_t reg, void *priv), - void (*write_vendor_reg)(uint8_t ld, uint8_t reg, uint8_t val, void *priv), - void *priv); -void isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size); -void isapnp_enable_card(void *priv, uint8_t enable); -void isapnp_set_csn(void *priv, uint8_t csn); -uint8_t isapnp_read_reg(void *priv, uint8_t ldn, uint8_t reg); -void isapnp_write_reg(void *priv, uint8_t ldn, uint8_t reg, uint8_t val); -void isapnp_set_device_defaults(void *priv, uint8_t ldn, const isapnp_device_config_t *config); -void isapnp_reset_card(void *priv); -void isapnp_reset_device(void *priv, uint8_t ld); +extern void *isapnp_add_card(uint8_t *rom, uint16_t rom_size, + void (*config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv), + void (*csn_changed)(uint8_t csn, void *priv), + uint8_t (*read_vendor_reg)(uint8_t ld, uint8_t reg, void *priv), + void (*write_vendor_reg)(uint8_t ld, uint8_t reg, uint8_t val, void *priv), + void *priv); +extern void isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size); +extern void isapnp_enable_card(void *priv, uint8_t enable); +extern void isapnp_set_csn(void *priv, uint8_t csn); +extern uint8_t isapnp_read_reg(void *priv, uint8_t ldn, uint8_t reg); +extern void isapnp_write_reg(void *priv, uint8_t ldn, uint8_t reg, uint8_t val); +extern void isapnp_set_device_defaults(void *priv, uint8_t ldn, const isapnp_device_config_t *config); +extern void isapnp_reset_card(void *priv); +extern void isapnp_reset_device(void *priv, uint8_t ld); +extern void isapnp_set_rt(void *priv, uint8_t is_rt); +extern uint8_t *isapnp_get_csnsav(void *priv); #endif /*EMU_ISAPNP_H*/ diff --git a/src/mem/nmc93cxx.c b/src/mem/nmc93cxx.c index 17d97591e..a0d24b872 100644 --- a/src/mem/nmc93cxx.c +++ b/src/mem/nmc93cxx.c @@ -29,6 +29,7 @@ #include <86box/nmc93cxx.h> #include <86box/plat_unused.h> +#define ENABLE_NMC93CXX_EEPROM_LOG 3 #ifdef ENABLE_NMC93CXX_EEPROM_LOG int nmc93cxx_eeprom_do_log = ENABLE_NMC93CXX_EEPROM_LOG; diff --git a/src/network/net_dp8390.c b/src/network/net_dp8390.c index 7f3490877..0bf3e9d3b 100644 --- a/src/network/net_dp8390.c +++ b/src/network/net_dp8390.c @@ -514,7 +514,7 @@ dp8390_page0_write(dp8390_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned le { uint8_t val2; - dp8390_log("DP839: Page0 write to register 0x%02x, value=0x%02x\n", + dp8390_log("DP8390: Page0 write to register 0x%02x, value=0x%02x\n", off, val); switch (off) { diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 0ce0190ac..d7e4e28a0 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -65,6 +65,7 @@ #include <86box/network.h> #include <86box/net_dp8390.h> #include <86box/net_ne2000.h> +#include <86box/nmc93cxx.h> #include <86box/isapnp.h> #include <86box/plat_fallthrough.h> #include <86box/plat_unused.h> @@ -85,25 +86,26 @@ typedef struct nic_t { const char *name; - uint8_t pnp_csnsav; uint8_t pci_slot; uint8_t irq_state; - uint8_t pad; + uint8_t csnsav; /* RTL8019AS/RTL8029AS registers */ uint8_t config0; + uint8_t config1; uint8_t config2; uint8_t config3; uint8_t _9346cr; uint8_t pci_regs[PCI_REGSIZE]; - uint8_t eeprom[128]; /* for RTL8029AS */ uint8_t maclocal[6]; /* configured MAC (local) address */ /* POS registers, MCA boards only */ uint8_t pos_regs[8]; + uint8_t eeprom_data[128]; + int board; int is_pci; int is_mca; @@ -121,6 +123,9 @@ typedef struct nic_t { rom_t bios_rom; void *pnp_card; + uint8_t *pnp_csnsav; + + nmc93cxx_eeprom_t *eeprom; } nic_t; #ifdef ENABLE_NE2K_LOG @@ -144,7 +149,11 @@ nelog(int lvl, const char *fmt, ...) static void nic_interrupt(void *priv, int set) { - nic_t *dev = (nic_t *) priv; + nic_t *dev = (nic_t *) priv; + int enabled = 1; + + if (dev->board == NE2K_RTL8019AS_PNP) + enabled = dev->config1 & 0x80; if (dev->is_pci) { if (set) @@ -152,9 +161,12 @@ nic_interrupt(void *priv, int set) else pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state); } else { - if (set) - picint(1 << dev->base_irq); - else + if (enabled && (dev->base_irq != 0x02)) { + if (set) + picint(1 << dev->base_irq); + else + picintc(1 << dev->base_irq); + } else if (dev->base_irq != 0x02) picintc(1 << dev->base_irq); } } @@ -236,6 +248,7 @@ asic_read(nic_t *dev, uint32_t off, unsigned int len) /* If all bytes have been written, signal remote-DMA complete */ if (dev->dp8390->remote_bytes == 0) { + nelog(3, "%s: DMA read: done (%i)\n", dev->name, dev->dp8390->IMR.rdma_inte); dev->dp8390->ISR.rdma_done = 1; if (dev->dp8390->IMR.rdma_inte) nic_interrupt(dev, 1); @@ -262,6 +275,11 @@ asic_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) dev->name, (unsigned) off, (unsigned) val); switch (off) { + default: /* this is invalid, but happens under win95 device detection */ + nelog(3, "%s: ASIC write invalid address %04x, ignoring\n", + dev->name, (unsigned) off); + break; + case 0x00: /* Data register - see asic_read for a description */ if ((len > 1) && (dev->dp8390->DCR.wdsize == 0)) { nelog(3, "%s: DMA write length %d on byte mode operation\n", @@ -299,11 +317,6 @@ asic_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) case 0x0f: /* Reset register */ /* end of reset pulse */ break; - - default: /* this is invalid, but happens under win95 device detection */ - nelog(3, "%s: ASIC write invalid address %04x, ignoring\n", - dev->name, (unsigned) off); - break; } } @@ -311,59 +324,137 @@ asic_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) static uint32_t page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len)) { + uint8_t ret = 0x00; + if (dev->board >= NE2K_RTL8019AS_PNP) switch (off) { - case 0x1: /* 9346CR */ - return (dev->_9346cr); + default: + break; - case 0x3: /* CONFIG0 */ - return 0x00; /* Cable not BNC */ + case 0x1: /* 9346CR */ + ret = (dev->_9346cr & 0xfe); + + if (((ret & 0xc0) == 0x80) && nmc93cxx_eeprom_read(dev->eeprom)) + ret |= 0x01; + break; + + case 0x3: /* CONFIG0 */ + if (dev->board == NE2K_RTL8019AS_PNP) + ret = (dev->config0 & 0xc0) | 0x10; /* Cable not BNC */ + else + ret = 0x00; /* Cable not BNC */ + break; + + case 0x4: /* CONFIG1 */ + if (dev->board == NE2K_RTL8019AS_PNP) + ret = dev->config1; + break; case 0x5: /* CONFIG2 */ - return (dev->config2 & 0xe0); + if (dev->board == NE2K_RTL8019AS_PNP) + ret = dev->config2; + else + ret = (dev->config2 & 0xe0); + break; case 0x6: /* CONFIG3 */ - return (dev->config3 & 0x46); + if (dev->board == NE2K_RTL8019AS_PNP) + ret = dev->config3; + else + ret = (dev->config3 & 0x46); + break; case 0x8: /* CSNSAV */ - return ((dev->board == NE2K_RTL8019AS_PNP) ? dev->pnp_csnsav : 0x00); + ret = ((dev->board == NE2K_RTL8019AS_PNP) ? *dev->pnp_csnsav : 0x00); + break; + + case 0xb: /* INTR */ + if (dev->board == NE2K_RTL8019AS_PNP) { + ret = (pic2.irr & 0x02) ? 0x01 : 0x00; + ret |= (pic.irr & 0x08) ? 0x02 : 0x00; + ret |= (pic.irr & 0x10) ? 0x04 : 0x00; + ret |= (pic.irr & 0x20) ? 0x08 : 0x00; + ret |= (pic2.irr & 0x04) ? 0x10 : 0x00; + ret |= (pic2.irr & 0x08) ? 0x20 : 0x00; + ret |= (pic2.irr & 0x10) ? 0x40 : 0x00; + ret |= (pic2.irr & 0x80) ? 0x80 : 0x00; + } + break; + + case 0xd: /* CONFIG4 */ + if (dev->board == NE2K_RTL8019AS_PNP) { + uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + ret = data[0x03]; + } + break; case 0xe: /* 8029ASID0 */ if (dev->board == NE2K_RTL8029AS) - return 0x29; + ret = 0x29; break; case 0xf: /* 8029ASID1 */ if (dev->board == NE2K_RTL8029AS) - return 0x80; - break; - - default: + ret = 0x80; break; } - nelog(3, "%s: Page3 read register 0x%02x attempted\n", dev->name, off); - return 0x00; + nelog(3, "%s: Page3 read register 0x%02x, value=0x%04x\n", dev->name, off, ret); + return ret; } static void page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) { + int cfg_write_enable = ((dev->_9346cr & 0xc0) == 0xc0); + if (dev->board >= NE2K_RTL8019AS_PNP) { - nelog(3, "%s: Page2 write to register 0x%02x, len=%u, value=0x%04x\n", + nelog(3, "%s: Page3 write to register 0x%02x, len=%u, value=0x%04x\n", dev->name, off, len, val); switch (off) { case 0x01: /* 9346CR */ dev->_9346cr = (val & 0xfe); + if ((val & 0xc0) == 0x80) + nmc93cxx_eeprom_write(dev->eeprom, !!(val & 0x08), !!(val & 0x04), !!(val & 0x02)); + else if ((val & 0xc0) == 0x40) { + uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + + data[0x00] = 0x80; + data[0x01] = 0x00; + data[0x02] = 0x80; + data[0x03] = 0x00; + + dev->_9346cr = 0x21; + } + break; + + case 0x03: /* CONFIG0 */ + if (cfg_write_enable && (dev->board == NE2K_RTL8019AS_PNP)) + dev->config0 = (val & 0xc0); + break; + + case 0x04: /* CONFIG1 */ + if (cfg_write_enable && (dev->board == NE2K_RTL8019AS_PNP)) + dev->config1 = (dev->config1 & 0x7f) | (val & 0x80); break; case 0x05: /* CONFIG2 */ - dev->config2 = (val & 0xe0); + if (cfg_write_enable) { + if (dev->board == NE2K_RTL8019AS_PNP) + dev->config2 = val; + else + dev->config2 = (val & 0xe0); + } break; case 0x06: /* CONFIG3 */ - dev->config3 = (val & 0x46); + if (cfg_write_enable) { + if (dev->board == NE2K_RTL8019AS_PNP) + dev->config3 = val; + else + dev->config3 = (val & 0x46); + } break; case 0x09: /* HLTCLK */ @@ -491,6 +582,10 @@ static void nic_ioremove(nic_t *dev, uint16_t addr); static void nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) { + uint8_t irq_map[16] = { 0x00, 0x00, 0x00, 0x10, 0x20, 0x30, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x50, 0x60, 0x00, 0x00, 0x70 }; + uint8_t ios = 0x00; + if (ld) return; @@ -502,10 +597,22 @@ nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) } dev->base_address = config->io[0].base; - dev->base_irq = config->irq[0].irq; - if (config->activate && (dev->base_address != ISAPNP_IO_DISABLED)) + nic_interrupt(dev, 0); + dev->base_irq = config->irq[0].irq; + if ((dev->base_irq >= 0x00) && (dev->base_irq <= 0x0f)) + dev->config1 = (dev->config1 & 0x8f) | irq_map[dev->base_irq]; + else + dev->config1 = (dev->config1 & 0x8f); + + if (config->activate && (dev->base_address != ISAPNP_IO_DISABLED)) { nic_ioset(dev, dev->base_address); + ios |= (dev->base_address & 0x0100) ? 0x00 : 0x04; + ios |= (dev->base_address & 0x0080) ? 0x08 : 0x00; + ios |= (dev->base_address & 0x0040) ? 0x02 : 0x00; + ios |= (dev->base_address & 0x0020) ? 0x01 : 0x00; + dev->config1 = (dev->config1 & 0xf0) | ios; + } } static void @@ -513,7 +620,7 @@ nic_pnp_csn_changed(uint8_t csn, void *priv) { nic_t *dev = (nic_t *) priv; - dev->pnp_csnsav = csn; + *dev->pnp_csnsav = csn; } static uint8_t @@ -525,17 +632,21 @@ nic_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv) const nic_t *dev = (nic_t *) priv; switch (reg) { - case 0xF0: - return dev->config0; + case 0xf0: /* CONFIG0 */ + return 0x00; /* Cable not BNC */ - case 0xF2: + case 0xf1: /* CONFIG1 */ + return dev->config1; + break; + + case 0xf2: /* CONFIG2 */ return dev->config2; - case 0xF3: + case 0xf3: /* CONFIG3 */ return dev->config3; - case 0xF5: - return dev->pnp_csnsav; + case 0xf5: + return *dev->pnp_csnsav; default: break; @@ -550,9 +661,9 @@ nic_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv) nic_t *dev = (nic_t *) priv; if ((ld == 0) && (reg == 0xf6) && (val & 0x04)) { - uint8_t csn = dev->pnp_csnsav; + uint8_t csn = *dev->pnp_csnsav; isapnp_set_csn(dev->pnp_card, 0); - dev->pnp_csnsav = csn; + *dev->pnp_csnsav = csn; } } @@ -913,6 +1024,7 @@ nic_init(const device_t *info) char *rom = NULL; nic_t *dev; int set_oui = 0; + int use_nvr = 0; dev = calloc(1, sizeof(nic_t)); dev->name = info->name; @@ -1144,26 +1256,33 @@ nic_init(const device_t *info) } /* Initialize the RTL80x9 EEPROM. */ - memset(dev->eeprom, 0x00, sizeof(dev->eeprom)); + memset(dev->eeprom_data, 0x00, sizeof(dev->eeprom_data)); if (dev->board == NE2K_RTL8029AS) { - memcpy(&dev->eeprom[0x02], dev->maclocal, 6); + dev->eeprom_data[0x00] = 0x00; + dev->eeprom_data[0x01] = 0x00; - dev->eeprom[0x76] = dev->eeprom[0x7A] = dev->eeprom[0x7E] = (PCI_DEVID & 0xff); - dev->eeprom[0x77] = dev->eeprom[0x7B] = dev->eeprom[0x7F] = (PCI_DEVID >> 8); - dev->eeprom[0x78] = dev->eeprom[0x7C] = (PCI_VENDID & 0xff); - dev->eeprom[0x79] = dev->eeprom[0x7D] = (PCI_VENDID >> 8); + memcpy(&dev->eeprom_data[0x02], dev->maclocal, 6); + + dev->eeprom_data[0x76] = dev->eeprom_data[0x7a] = dev->eeprom_data[0x7e] = (PCI_DEVID & 0xff); + dev->eeprom_data[0x77] = dev->eeprom_data[0x7b] = dev->eeprom_data[0x7f] = (PCI_DEVID >> 8); + dev->eeprom_data[0x78] = dev->eeprom_data[0x7c] = (PCI_VENDID & 0xff); + dev->eeprom_data[0x79] = dev->eeprom_data[0x7d] = (PCI_VENDID >> 8); + + use_nvr = 1; } else { const char *pnp_rom_file = NULL; int pnp_rom_len = 0x4a; switch (dev->board) { case NE2K_RTL8019AS_PNP: pnp_rom_file = "roms/network/rtl8019as/RTL8019A.BIN"; + use_nvr = 1; break; case NE2K_DE220P: pnp_rom_file = "roms/network/de220p/dlk2201a.bin"; - pnp_rom_len = 0x43; + pnp_rom_len = 0x43; + use_nvr = 1; break; default: @@ -1174,8 +1293,8 @@ nic_init(const device_t *info) if (pnp_rom_file) { FILE *fp = rom_fopen(pnp_rom_file, "rb"); if (fp) { - if (fread(&dev->eeprom[0x12], 1, pnp_rom_len, fp) == pnp_rom_len) - pnp_rom = &dev->eeprom[0x12]; + if (fread(&dev->eeprom_data[0x12], 1, pnp_rom_len, fp) == pnp_rom_len) + pnp_rom = &dev->eeprom_data[0x12]; fclose(fp); } } @@ -1183,10 +1302,22 @@ nic_init(const device_t *info) switch (info->local) { case NE2K_RTL8019AS_PNP: case NE2K_DE220P: - dev->pnp_card = isapnp_add_card(pnp_rom, pnp_rom_len, - nic_pnp_config_changed, nic_pnp_csn_changed, - nic_pnp_read_vendor_reg, nic_pnp_write_vendor_reg, - dev); + dev->pnp_card = isapnp_add_card(pnp_rom, pnp_rom_len, + nic_pnp_config_changed, nic_pnp_csn_changed, + nic_pnp_read_vendor_reg, nic_pnp_write_vendor_reg, + dev); + dev->pnp_csnsav = isapnp_get_csnsav(dev->pnp_card); + dev->config0 = 0x00; + dev->config1 = 0x80; + dev->config2 = 0x00; + dev->config3 = 0x80; + isapnp_set_rt(dev->pnp_card, 1); + + dev->eeprom_data[0x00] = 0x80; + dev->eeprom_data[0x01] = 0x00; + dev->eeprom_data[0x02] = 0x80; + dev->eeprom_data[0x03] = 0x01; + memcpy(&dev->eeprom_data[0x04], dev->maclocal, 6); break; default: @@ -1195,6 +1326,25 @@ nic_init(const device_t *info) } } + if (use_nvr) { + nmc93cxx_eeprom_params_t params; + char filename[1024] = { 0 }; + + params.nwords = 64; + params.default_content = (uint16_t *) dev->eeprom_data; + params.filename = filename; + int inst = device_get_instance(); + snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, inst); + dev->eeprom = device_add_inst_params(&nmc93cxx_device, inst, ¶ms); + if (dev->eeprom == NULL) { + free(dev); + return NULL; + } + } + + if (dev->pnp_csnsav == NULL) + dev->pnp_csnsav = &dev->csnsav; + if (dev->board != NE2K_ETHERNEXT_MC) /* Reset the board. */ nic_reset(dev); From f04346bf31b2559bb08718839746b06cf6ca47e9 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Sep 2025 15:19:24 +0200 Subject: [PATCH 241/274] 93c46: Disable excess logging. --- src/mem/nmc93cxx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mem/nmc93cxx.c b/src/mem/nmc93cxx.c index a0d24b872..17d97591e 100644 --- a/src/mem/nmc93cxx.c +++ b/src/mem/nmc93cxx.c @@ -29,7 +29,6 @@ #include <86box/nmc93cxx.h> #include <86box/plat_unused.h> -#define ENABLE_NMC93CXX_EEPROM_LOG 3 #ifdef ENABLE_NMC93CXX_EEPROM_LOG int nmc93cxx_eeprom_do_log = ENABLE_NMC93CXX_EEPROM_LOG; From 085b0eb30a4b87cfece3c04b3b9b76e5196f6990 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 24 Sep 2025 23:03:08 +0200 Subject: [PATCH 242/274] Temporarily force Qt 6 on. --- CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 29fedd6ad..4f10a1e56 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -67,6 +67,8 @@ if(VCPKG_TOOLCHAIN) set(USE_QT6 ON) endif() +set(USE_QT6 ON) + if(WIN32) # Prefer static builds on Windows set(PREFER_STATIC ON) From b2b5acfa3f91311b3d99add9a027e8b8f8c20824 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Sep 2025 00:53:16 +0200 Subject: [PATCH 243/274] Revert the Qt 6 forcing. --- CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4f10a1e56..29fedd6ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -67,8 +67,6 @@ if(VCPKG_TOOLCHAIN) set(USE_QT6 ON) endif() -set(USE_QT6 ON) - if(WIN32) # Prefer static builds on Windows set(PREFER_STATIC ON) From ae369dc34d8b9b43b112b1435dedaa4c18eb6070 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Sep 2025 00:58:53 +0200 Subject: [PATCH 244/274] RTL8019AS and ISA PnP: More fixes. --- src/device/isapnp.c | 103 +++++++++++++++++++++++++++++-------- src/include/86box/isapnp.h | 3 ++ src/network/net_ne2000.c | 86 ++++++++++++++++++++++--------- 3 files changed, 147 insertions(+), 45 deletions(-) diff --git a/src/device/isapnp.c b/src/device/isapnp.c index 675d9adf7..46cd52c24 100644 --- a/src/device/isapnp.c +++ b/src/device/isapnp.c @@ -98,6 +98,8 @@ typedef struct _isapnp_card_ { uint8_t serial_read_pair; uint8_t serial_read_pos; uint8_t is_rt; + uint8_t normal; + uint8_t multiple_lds; uint8_t *rom; uint16_t rom_pos; uint16_t rom_size; @@ -449,15 +451,16 @@ isapnp_write_addr(UNUSED(uint16_t addr), uint8_t val, void *priv) if (!dev->key_pos) { isapnp_log("ISAPnP: Key unlocked, putting cards to SLEEP\n"); while (card) { - int is_rt = (!dev->using_key2 || card->is_rt); - if (card->enable && is_rt && (card->enable != ISAPNP_CARD_NO_KEY) && (card->state == PNP_STATE_WAIT_FOR_KEY)) + int match_rt = (dev->using_key2 && card->is_rt); + int match_normal = (!dev->using_key2 && card->normal); + if (card->enable && (match_rt || match_normal) && + (card->enable != ISAPNP_CARD_NO_KEY) && (card->state == PNP_STATE_WAIT_FOR_KEY)) card->state = PNP_STATE_SLEEP; card = card->next; } } - } else { + } else dev->key_pos = 0; - } } } @@ -527,8 +530,22 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin if (card->csn == val) { card->rom_pos = 0; card->id_checksum = isapnp_init_key[0]; - if (card->state == PNP_STATE_SLEEP) + if (card->state == PNP_STATE_SLEEP) { card->state = (val == 0) ? PNP_STATE_ISOLATION : PNP_STATE_CONFIG; + + if (!card->multiple_lds) { + ld = card->first_ld; + while (ld) { + if (ld->number == 0x00) { + isapnp_log("ISAPnP: Select CSN %02X device 00\n", card->csn); + dev->current_ld_card = card; + dev->current_ld = ld; + break; + } + ld = ld->next; + } + } + } } else card->state = PNP_STATE_SLEEP; @@ -549,27 +566,28 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin break; case 0x07: /* Logical Device Number */ - CHECK_CURRENT_CARD(); + if (card->multiple_lds) { + CHECK_CURRENT_CARD(); - card->ld = val; - ld = card->first_ld; - while (ld) { - if (ld->number == val) { - isapnp_log("ISAPnP: Select CSN %02X device %02X\n", card->csn, val); - dev->current_ld_card = card; - dev->current_ld = ld; - break; + card->ld = val; + ld = card->first_ld; + while (ld) { + if (ld->number == val) { + isapnp_log("ISAPnP: Select CSN %02X device %02X\n", card->csn, val); + dev->current_ld_card = card; + dev->current_ld = ld; + break; + } + ld = ld->next; } - ld = ld->next; - } - if (!ld) { - isapnp_log("ISAPnP: CSN %02X has no device %02X, creating one\n", card->csn, val); - dev->current_ld_card = card; - dev->current_ld = isapnp_create_ld(card); - dev->current_ld->number = val; + if (!ld) { + isapnp_log("ISAPnP: CSN %02X has no device %02X, creating one\n", card->csn, val); + dev->current_ld_card = card; + dev->current_ld = isapnp_create_ld(card); + dev->current_ld->number = val; + } } - break; case 0x30: /* Activate */ @@ -759,11 +777,13 @@ isapnp_add_card(uint8_t *rom, uint16_t rom_size, isapnp_card_t *card = (isapnp_card_t *) calloc(1, sizeof(isapnp_card_t)); card->enable = 1; + card->normal = 1; card->priv = priv; card->config_changed = config_changed; card->csn_changed = csn_changed; card->read_vendor_reg = read_vendor_reg; card->write_vendor_reg = write_vendor_reg; + card->multiple_lds = 1; if (!dev->first_card) { dev->first_card = card; @@ -1201,6 +1221,45 @@ isapnp_set_rt(void *priv, uint8_t is_rt) card->is_rt = is_rt; } +void +isapnp_set_normal(void *priv, uint8_t normal) +{ + isapnp_card_t *card = (isapnp_card_t *) priv; + + card->normal = normal; +} + +void +isapnp_activate(void *priv, uint16_t base, uint8_t irq) +{ + isapnp_card_t *card = (isapnp_card_t *) priv; + isapnp_device_t *ld = card->first_ld; + + while (ld) { + if (ld->number == 0x00) + break; + ld = ld->next; + } + + if (ld != NULL) { + ld->regs[0x30] = 0x01; + ld->regs[0x60] = base >> 4; + if (!(ld->io_16bit & (1 << ((0x60 >> 1) & 0x07)))) + ld->regs[0x60] &= 0x03; + ld->regs[0x61] = base & 0x0f; + ld->regs[0x70] = irq; + } +} + +void +isapnp_set_single_ld(void *priv) +{ + isapnp_card_t *card = (isapnp_card_t *) priv; + + card->multiple_lds = 0; + card->ld = 0x00; +} + uint8_t * isapnp_get_csnsav(void *priv) { diff --git a/src/include/86box/isapnp.h b/src/include/86box/isapnp.h index 2ffbd2d66..7d730564a 100644 --- a/src/include/86box/isapnp.h +++ b/src/include/86box/isapnp.h @@ -72,6 +72,9 @@ extern void isapnp_set_device_defaults(void *priv, uint8_t ldn, const isapnp extern void isapnp_reset_card(void *priv); extern void isapnp_reset_device(void *priv, uint8_t ld); extern void isapnp_set_rt(void *priv, uint8_t is_rt); +extern void isapnp_set_normal(void *priv, uint8_t normal); +extern void isapnp_activate(void *priv, uint16_t base, uint8_t irq); +extern void isapnp_set_single_ld(void *priv); extern uint8_t *isapnp_get_csnsav(void *priv); #endif /*EMU_ISAPNP_H*/ diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index d7e4e28a0..2a9f3f551 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -69,6 +69,7 @@ #include <86box/isapnp.h> #include <86box/plat_fallthrough.h> #include <86box/plat_unused.h> +#include "cpu.h" /* ROM BIOS file paths. */ #define ROM_PATH_NE1000 "roms/network/ne1000/ne1000.rom" @@ -340,7 +341,7 @@ page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len)) case 0x3: /* CONFIG0 */ if (dev->board == NE2K_RTL8019AS_PNP) - ret = (dev->config0 & 0xc0) | 0x10; /* Cable not BNC */ + ret = dev->config0; else ret = 0x00; /* Cable not BNC */ break; @@ -418,20 +419,20 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) if ((val & 0xc0) == 0x80) nmc93cxx_eeprom_write(dev->eeprom, !!(val & 0x08), !!(val & 0x04), !!(val & 0x02)); else if ((val & 0xc0) == 0x40) { - uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); - data[0x00] = 0x80; - data[0x01] = 0x00; - data[0x02] = 0x80; - data[0x03] = 0x00; + dev->config1 = (data[0x00] & 0x7f) | 0x80; + dev->config2 = (data[0x01] & 0xdf); + dev->config3 = (data[0x02] & 0x77) | 0x80; + dev->_9346cr = 0x21; - dev->_9346cr = 0x21; + isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); } break; case 0x03: /* CONFIG0 */ if (cfg_write_enable && (dev->board == NE2K_RTL8019AS_PNP)) - dev->config0 = (val & 0xc0); + dev->config0 = (dev->config0 & 0x3f) | (val & 0xc0); break; case 0x04: /* CONFIG1 */ @@ -442,7 +443,7 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) case 0x05: /* CONFIG2 */ if (cfg_write_enable) { if (dev->board == NE2K_RTL8019AS_PNP) - dev->config2 = val; + dev->config2 = (dev->config2 & 0x1f) | (val & 0xe0); else dev->config2 = (val & 0xe0); } @@ -451,7 +452,7 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) case 0x06: /* CONFIG3 */ if (cfg_write_enable) { if (dev->board == NE2K_RTL8019AS_PNP) - dev->config3 = val; + dev->config3 = (dev->config3 & 0xf9) | (val & 0x06); else dev->config3 = (val & 0x46); } @@ -582,9 +583,11 @@ static void nic_ioremove(nic_t *dev, uint16_t addr); static void nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) { +#if 0 uint8_t irq_map[16] = { 0x00, 0x00, 0x00, 0x10, 0x20, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x50, 0x60, 0x00, 0x00, 0x70 }; uint8_t ios = 0x00; +#endif if (ld) return; @@ -600,18 +603,22 @@ nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) nic_interrupt(dev, 0); dev->base_irq = config->irq[0].irq; +#if 0 if ((dev->base_irq >= 0x00) && (dev->base_irq <= 0x0f)) dev->config1 = (dev->config1 & 0x8f) | irq_map[dev->base_irq]; else dev->config1 = (dev->config1 & 0x8f); +#endif if (config->activate && (dev->base_address != ISAPNP_IO_DISABLED)) { nic_ioset(dev, dev->base_address); +#if 0 ios |= (dev->base_address & 0x0100) ? 0x00 : 0x04; ios |= (dev->base_address & 0x0080) ? 0x08 : 0x00; ios |= (dev->base_address & 0x0040) ? 0x02 : 0x00; ios |= (dev->base_address & 0x0020) ? 0x01 : 0x00; dev->config1 = (dev->config1 & 0xf0) | ios; +#endif } } @@ -626,33 +633,38 @@ nic_pnp_csn_changed(uint8_t csn, void *priv) static uint8_t nic_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv) { - if (ld != 0) - return 0x00; + uint8_t ret = 0x00; const nic_t *dev = (nic_t *) priv; - switch (reg) { + if (ld == 0) switch (reg) { + default: + break; + case 0xf0: /* CONFIG0 */ - return 0x00; /* Cable not BNC */ + ret = dev->config0; + break; case 0xf1: /* CONFIG1 */ - return dev->config1; + ret = dev->config1; break; case 0xf2: /* CONFIG2 */ - return dev->config2; + ret = dev->config2; + break; case 0xf3: /* CONFIG3 */ - return dev->config3; + ret = dev->config3; + break; case 0xf5: - return *dev->pnp_csnsav; - - default: + ret = *dev->pnp_csnsav; break; } - return 0x00; + nelog(3, "[R] Vendor register: %02X (LD = %02X) = %02X\n", reg, ld, ret); + + return ret; } static void @@ -660,6 +672,8 @@ nic_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv) { nic_t *dev = (nic_t *) priv; + nelog(3, "[W] Vendor register: %02X (LD = %02X) = %02X\n", reg, ld, val); + if ((ld == 0) && (reg == 0xf6) && (val & 0x04)) { uint8_t csn = *dev->pnp_csnsav; isapnp_set_csn(dev->pnp_card, 0); @@ -1307,7 +1321,7 @@ nic_init(const device_t *info) nic_pnp_read_vendor_reg, nic_pnp_write_vendor_reg, dev); dev->pnp_csnsav = isapnp_get_csnsav(dev->pnp_card); - dev->config0 = 0x00; + dev->config0 = 0x10 /* Cable not BNC */; dev->config1 = 0x80; dev->config2 = 0x00; dev->config3 = 0x80; @@ -1315,7 +1329,7 @@ nic_init(const device_t *info) dev->eeprom_data[0x00] = 0x80; dev->eeprom_data[0x01] = 0x00; - dev->eeprom_data[0x02] = 0x80; + dev->eeprom_data[0x02] = 0x81; dev->eeprom_data[0x03] = 0x01; memcpy(&dev->eeprom_data[0x04], dev->maclocal, 6); break; @@ -1340,6 +1354,32 @@ nic_init(const device_t *info) free(dev); return NULL; } + if (info->local == NE2K_RTL8019AS_PNP) { + uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + + dev->config1 = (data[0x00] & 0x7f) | 0x80; + dev->config2 = (data[0x01] & 0xdf); + dev->config3 = (data[0x02] & 0xf7); + + isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); + isapnp_set_single_ld(dev->pnp_card); + + if (!(dev->config3 & 0x01)) { + uint8_t irq_map[8] = { 9, 3, 4, 5, 10, 11, 12, 15 }; + dev->base_address = 0x0000; + + dev->base_irq = irq_map[(dev->config1 >> 4) & 0x07]; + + dev->base_address = (dev->config1 & 0x01) ? 0x0020 : 0x0000; + dev->base_address |= (dev->config1 & 0x02) ? 0x0040 : 0x0000; + dev->base_address |= (dev->config1 & 0x04) ? 0x0000 : 0x0100; + dev->base_address |= (dev->config1 & 0x08) ? 0x0080 : 0x0000; + + nic_ioset(dev, dev->base_address); + + isapnp_activate(dev->pnp_card, dev->base_address, dev->base_irq); + } + } } if (dev->pnp_csnsav == NULL) From 6819b2c3d0a8b3c0c0a2b27b703e06a7095d8d73 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Thu, 25 Sep 2025 01:01:09 +0200 Subject: [PATCH 245/274] Revert "Merge branch 'master' into master" This reverts commit dbafb3e8a4f9bd8a4ed387e8d72dc68b869a4764, reversing changes made to f04346bf31b2559bb08718839746b06cf6ca47e9. --- CMakeLists.txt | 13 +- CMakePresets.json | 5 +- doc/nvidia_notes/2025-01-24.txt | 1 - .../B = BUFFER. REMEMBER THESE!!!.txt | 1 - .../How to optimise riva 128 applications.txt | 6 - doc/nvidia_notes/Memory map (RIVA 128).txt | 81 - doc/nvidia_notes/NV3 DMA Engine.txt | 54 - doc/nvidia_notes/NV_PFB_CONFIG_0.txt | 29 - doc/nvidia_notes/PFIFO RAMHT RAMRO.txt | 38 - doc/nvidia_notes/RIVA fansites.txt | 26 - doc/nvidia_notes/Versions.txt | 8 - doc/nvidia_notes/gpucompanies.txt | 63 - doc/nvidia_notes/hardware cursor.txt | 21 - doc/nvidia_notes/multithreading.pdn | Bin 106011 -> 0 bytes doc/nvidia_notes/multithreading.png | Bin 117148 -> 0 bytes doc/nvidia_notes/nv3 driver init status.txt | 112 - .../nv3 driver init status_2025-02-10.txt | 90 - doc/nvidia_notes/nv3_object_classes.txt | 37 - doc/nvidia_notes/nv3d3d_t.txt | 161 - doc/nvidia_notes/old nouveau wiki.txt | 9 - doc/nvidia_notes/rivatv_riva128.txt | 2238 --------- doc/nvidia_notes/status.xlsx | Bin 15945 -> 0 bytes .../86box/nv/classes/vid_nv3_classes.h | 1179 ----- src/include/86box/nv/render/vid_nv3_render.h | 64 - src/include/86box/nv/vid_nv.h | 178 - src/include/86box/nv/vid_nv1.h | 167 - src/include/86box/nv/vid_nv3.h | 1764 ------- src/include/86box/nv/vid_nv4.h | 149 - src/include/86box/nv/vid_nv4_defines.h | 4291 ----------------- src/include/86box/utils/video_stdlib.h | 23 - src/include/86box/video.h | 7 - src/qt/CMakeLists.txt | 10 +- src/qt/qt_gpudebug_visualnv.cpp | 177 - src/qt/qt_gpudebug_visualnv.hpp | 46 - src/qt/qt_gpudebug_visualnv.ui | 213 - src/qt/qt_gpudebug_vram.cpp | 54 - src/qt/qt_gpudebug_vram.hpp | 40 - src/qt/qt_gpudebug_vram.ui | 42 - src/qt/qt_mainwindow.cpp | 98 +- src/qt/qt_mainwindow.hpp | 15 +- src/qt/qt_mainwindow.ui | 78 +- src/sound/snd_emu8k.c | 2 +- src/sound/snd_sb.c | 4 +- src/utils/CMakeLists.txt | 3 - src/utils/log.c | 19 +- src/utils/video/video_rop.c | 790 --- src/video/CMakeLists.txt | 71 +- src/video/nv/nv1/nv1_core.c | 110 - src/video/nv/nv1/nv1_core_config.c | 133 - .../nv3/classes/nv3_class_001_beta_factor.c | 50 - src/video/nv/nv3/classes/nv3_class_002_rop.c | 44 - .../nv/nv3/classes/nv3_class_003_chroma_key.c | 54 - .../nv/nv3/classes/nv3_class_004_plane_mask.c | 40 - .../nv3_class_005_clipping_rectangle.c | 49 - .../nv/nv3/classes/nv3_class_006_pattern.c | 86 - .../nv/nv3/classes/nv3_class_007_rectangle.c | 69 - .../nv/nv3/classes/nv3_class_008_point.c | 40 - src/video/nv/nv3/classes/nv3_class_009_line.c | 40 - src/video/nv/nv3/classes/nv3_class_00a_lin.c | 41 - .../nv/nv3/classes/nv3_class_00b_triangle.c | 40 - .../classes/nv3_class_00c_win95_gdi_text.c | 285 -- src/video/nv/nv3/classes/nv3_class_00d_m2mf.c | 94 - .../nv3_class_00e_scaled_image_from_mem.c | 40 - src/video/nv/nv3/classes/nv3_class_010_blit.c | 60 - .../nv/nv3/classes/nv3_class_011_image.c | 67 - .../nv/nv3/classes/nv3_class_012_bitmap.c | 41 - .../classes/nv3_class_014_transfer2memory.c | 41 - .../nv3_class_015_stretched_image_from_cpu.c | 40 - .../nv3_class_017_d3d5_tri_zeta_buffer.c | 40 - .../classes/nv3_class_018_point_zeta_buffer.c | 42 - .../classes/nv3_class_01c_image_in_memory.c | 99 - src/video/nv/nv3/classes/nv3_class_names.c | 67 - .../nv/nv3/classes/nv3_class_shared_methods.c | 67 - src/video/nv/nv3/nv3_core.c | 1567 ------ src/video/nv/nv3/nv3_core_arbiter.c | 213 - src/video/nv/nv3/nv3_core_config.c | 240 - src/video/nv/nv3/render/nv3_render_blit.c | 229 - src/video/nv/nv3/render/nv3_render_core.c | 869 ---- .../nv/nv3/render/nv3_render_primitives.c | 355 -- src/video/nv/nv3/subsystems/nv3_pbus.c | 255 - src/video/nv/nv3/subsystems/nv3_pbus_dma.c | 274 -- src/video/nv/nv3/subsystems/nv3_pextdev.c | 161 - src/video/nv/nv3/subsystems/nv3_pfb.c | 204 - src/video/nv/nv3/subsystems/nv3_pfifo.c | 985 ---- src/video/nv/nv3/subsystems/nv3_pgraph.c | 632 --- src/video/nv/nv3/subsystems/nv3_pmc.c | 274 -- src/video/nv/nv3/subsystems/nv3_pme.c | 136 - src/video/nv/nv3/subsystems/nv3_pramdac.c | 458 -- src/video/nv/nv3/subsystems/nv3_pramin.c | 515 -- .../nv/nv3/subsystems/nv3_pramin_ramfc.c | 40 - .../nv/nv3/subsystems/nv3_pramin_ramht.c | 56 - .../nv/nv3/subsystems/nv3_pramin_ramro.c | 40 - src/video/nv/nv3/subsystems/nv3_ptimer.c | 227 - src/video/nv/nv3/subsystems/nv3_pvideo.c | 159 - src/video/nv/nv3/subsystems/nv3_user.c | 70 - src/video/nv/nv4/nv4_core.c | 388 -- src/video/nv/nv4/nv4_core_config.c | 92 - src/video/nv/nv4/nv4_core_io.c | 1283 ----- src/video/nv/nv4/nv4_debug_register_list.c | 46 - src/video/nv/nv4/subsystems/nv4_pramdac.c | 84 - src/video/nv/nv4/subsystems/nv4_ptimer.c | 227 - src/video/nv/nv_base.c | 107 - src/video/vid_table.c | 7 - src/video/vid_voodoo.c | 2 +- 104 files changed, 38 insertions(+), 24413 deletions(-) delete mode 100644 doc/nvidia_notes/2025-01-24.txt delete mode 100644 doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt delete mode 100644 doc/nvidia_notes/How to optimise riva 128 applications.txt delete mode 100644 doc/nvidia_notes/Memory map (RIVA 128).txt delete mode 100644 doc/nvidia_notes/NV3 DMA Engine.txt delete mode 100644 doc/nvidia_notes/NV_PFB_CONFIG_0.txt delete mode 100644 doc/nvidia_notes/PFIFO RAMHT RAMRO.txt delete mode 100644 doc/nvidia_notes/RIVA fansites.txt delete mode 100644 doc/nvidia_notes/Versions.txt delete mode 100644 doc/nvidia_notes/gpucompanies.txt delete mode 100644 doc/nvidia_notes/hardware cursor.txt delete mode 100644 doc/nvidia_notes/multithreading.pdn delete mode 100644 doc/nvidia_notes/multithreading.png delete mode 100644 doc/nvidia_notes/nv3 driver init status.txt delete mode 100644 doc/nvidia_notes/nv3 driver init status_2025-02-10.txt delete mode 100644 doc/nvidia_notes/nv3_object_classes.txt delete mode 100644 doc/nvidia_notes/nv3d3d_t.txt delete mode 100644 doc/nvidia_notes/old nouveau wiki.txt delete mode 100644 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src/video/nv/nv3/classes/nv3_class_001_beta_factor.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_002_rop.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_003_chroma_key.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_004_plane_mask.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_006_pattern.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_007_rectangle.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_008_point.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_009_line.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_00a_lin.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_00b_triangle.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_00d_m2mf.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_010_blit.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_011_image.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_012_bitmap.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_names.c delete mode 100644 src/video/nv/nv3/classes/nv3_class_shared_methods.c delete mode 100644 src/video/nv/nv3/nv3_core.c delete mode 100644 src/video/nv/nv3/nv3_core_arbiter.c delete mode 100644 src/video/nv/nv3/nv3_core_config.c delete mode 100644 src/video/nv/nv3/render/nv3_render_blit.c delete mode 100644 src/video/nv/nv3/render/nv3_render_core.c delete mode 100644 src/video/nv/nv3/render/nv3_render_primitives.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pbus.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pbus_dma.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pextdev.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pfb.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pfifo.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pgraph.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pmc.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pme.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pramdac.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pramin.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pramin_ramht.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pramin_ramro.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_ptimer.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_pvideo.c delete mode 100644 src/video/nv/nv3/subsystems/nv3_user.c delete mode 100644 src/video/nv/nv4/nv4_core.c delete mode 100644 src/video/nv/nv4/nv4_core_config.c delete mode 100644 src/video/nv/nv4/nv4_core_io.c delete mode 100644 src/video/nv/nv4/nv4_debug_register_list.c delete mode 100644 src/video/nv/nv4/subsystems/nv4_pramdac.c delete mode 100644 src/video/nv/nv4/subsystems/nv4_ptimer.c delete mode 100644 src/video/nv/nv_base.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 7ba7e9a75..29fedd6ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -139,15 +139,7 @@ option(DISCORD "Discord Rich Presence support" option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF) option(LIBASAN "Enable compilation with the addresss sanitizer" OFF) -if (NV_LOG) - add_compile_definitions(ENABLE_NV_LOG) -endif() - -if (NV_LOG_ULTRA) - add_compile_definitions(ENABLE_NV_LOG_ULTRA) -endif() - -if((ARCH STREQUAL "arm64") OR (ARCH STREQUAL "arm")) +if((ARCH STREQUAL "arm64")) set(NEW_DYNAREC ON) else() option(NEW_DYNAREC "Use the PCem v15 (\"new\") dynamic recompiler" OFF) @@ -192,12 +184,9 @@ cmake_dependent_option(PCL "Generic PCL5e Printer" cmake_dependent_option(SIO_DETECT "Super I/O Detection Helper" ON "DEV_BRANCH" OFF) cmake_dependent_option(WACOM "Wacom Input Devices" ON "DEV_BRANCH" OFF) cmake_dependent_option(XL24 "ATI VGA Wonder XL24 (ATI-28800-6)" ON "DEV_BRANCH" OFF) -cmake_dependent_option(NV3 "NVidia RIVA 128/128ZX (NV3/NV3T)" ON "DEV_BRANCH" OFF) - cmake_dependent_option(NETSWITCH "Network Switch Support" ON "DEV_BRANCH" OFF) cmake_dependent_option(VFIO "Virtual Function I/O" ON "DEV_BRANCH" OFF) - # Ditto but for Qt if(QT) option(USE_QT6 "Use Qt6 instead of Qt5" OFF) diff --git a/CMakePresets.json b/CMakePresets.json index 53ddffc74..be6615088 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -35,10 +35,7 @@ { "name": "debug", "cacheVariables": { - "CMAKE_BUILD_TYPE": "Debug", - "NV_LOG": "ON", - "NV_LOG_ULTRA": "ON" - + "CMAKE_BUILD_TYPE": "Debug" }, "inherits": "base" }, diff --git a/doc/nvidia_notes/2025-01-24.txt b/doc/nvidia_notes/2025-01-24.txt deleted file mode 100644 index e35818dc0..000000000 --- a/doc/nvidia_notes/2025-01-24.txt +++ /dev/null @@ -1 +0,0 @@ -THIS IS FIFOSERVICE!!!!!!!!!!!! \ No newline at end of file diff --git a/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt b/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt deleted file mode 100644 index e8f183240..000000000 --- a/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt +++ /dev/null @@ -1 +0,0 @@ -B = BUFFER. REMEMBER THESE!!! \ No newline at end of file diff --git a/doc/nvidia_notes/How to optimise riva 128 applications.txt b/doc/nvidia_notes/How to optimise riva 128 applications.txt deleted file mode 100644 index 004593a21..000000000 --- a/doc/nvidia_notes/How to optimise riva 128 applications.txt +++ /dev/null @@ -1,6 +0,0 @@ -How to optimise riva 128 applications: -* Ensure any set of polygons with one texture is close to a multiple of 128 polygons. -* Try to sort areas of a model with one texture to as close to 128 polygons as possible for efficient submission due to the lack of texturing. -* Try to have around (32*128) for nv3 or (64*128) for nv3t polygons -* Get coding -* Alcohol \ No newline at end of file diff --git a/doc/nvidia_notes/Memory map (RIVA 128).txt b/doc/nvidia_notes/Memory map (RIVA 128).txt deleted file mode 100644 index fbfe9074f..000000000 --- a/doc/nvidia_notes/Memory map (RIVA 128).txt +++ /dev/null @@ -1,81 +0,0 @@ -Memory map (RIVA 128) - -32 megabytes of MMIO starting at 0x0000000-0x01FFFFFF - -MC (Master Control) 0x00000000-0x00000FFF - Config/Boot 0x00000000-0x000000FF - Master Config 0x00000100-0x00000FFF - Also used to define DMA channel IDs? - -MPU-401 I/O 0x00000330-0x00000331 Probably NV1 leftover, NV1 has mpu401 emulation -- no audio in nv3 -VGA emulated ports 0x000003B0-0x000003DF Emulated I/O ports for VGA - -Bus Control (PBUS) 0x00001000-0x00001FFF -FIFO (PFIFO) 0x00002000-0x00003FFF Submit starting at 0x00800000. Used to configure RAMHT,RAMFC,RAMRO structures & cache - -PRM 0x00004000-0x00005FFF Realmode DOS device support - -PRMIO 0x00007000-0x00007FFF Realmode access to PCI BAR (Base Address Register) + PCI I/O -PTIMER 0x00009000-0x00009FFF Timer - -VGA emulation 0x0000A000-0x0000BFFF - -VGA vram emulation 0x000A0000-0x000BFFFF (PRMVGA) -VGA 0x000C0000-0x000C7FFF VGA sequencer + graph controller registers (PRMVIO) - -(All of this up to 0x0000FFFF can be traced) - -PFB (Framebuffer) 0x00100000-0x00100FFF Interface to vram -PEXTDEV 0x00101000-0x00101FFF External device interface - contains straps - Straps 0x00101000 11 bits of cfg - -ROM (VBIOS?) 0x00110000-0x0011FFFF -PALT (?) 0x00120000-0x00120FFF - -PEXTDEV 0x00101000-0x00101FFF External Devices - -Media Engine (PME) 0x00200000-0x00200FFF Allows for external video capture according to envytools? - -PGRAPH (3D rendering) 0x00400000-0x00401FFF - -PGRAPH objects (using RAMHT???) -*i assume that when you submit an object these are the registers used to actually draw the current object - -Beta blending factor 0x00410000-0x00411FFF -ROP 0x00420000-0x00421FFF Global bitwise operation (Render OPeration) for filtering the final pixel -Color Key 0x00430000-0x00431FFF -Plane Switch 0x00440000-0x00441FFF Something to do with color formats and objects? -Clipping 0x00450000-0x00451FFF -Blend Pattern 0x00460000-0x00461FFF Used for specific blending modes -Quad [OBSOLETE] 0x00470000-0x00471FFF A rectangle. NV1 LEFTOVER, OBSOLETE -Point 0x00480000-0x00481FFF A single point -Line 0x00490000-0x00491FFF A line (with an optional colour). Can also draw a polygon made out of lines - polyline -Lin 0x004A0000-0x004A1FFF A line, without starting or ending pixel (with an optional colour). Can also draw a "polylin" -Triangle [OBSOLETE] 0x004B0000-0x004B1FFF A triangle. NV1 LEFTOVER, OBSOLETE? -Win95 GDI text 0x004C0000-0x004C1FFF Win95 text acceleration -Memory to memory xfer 0x004D0000-0x004D1FFF Represents a memory to memory transfer -Scaled image from vram 0x004E0000-0x004E1FFF Scaled image from GPU VRAM -Image blit from vram 0x00500000-0x00501FFF Image from GPU VRAM -Image blit from cpu 0x00510000-0x00511FFF Image from CPU -Bitmap from cpu 0x00520000-0x00521FFF Bitmap from CPU -Image to memory 0x00540000-0x00541FFF Image to GPU VRAM -Stretch image from cpu 0x00550000-0x00551FFF Stretched image from CPU -Direct3D 5.0 triangle 0x00570000-0x00571FFF A triangle optimised explicitly for directx3/directx5 rendering - supercedes UTRI -PointZ 0x00580000-0x00581FFF A single point with "zeta factor" (not sure what this is yet) -Image in memory 0x005C0000-0x005C0FFF Image in vram(?) - -PVIDEO (Video Control) 0x00680000-0x006802FF -External DAC 0x00680000-0x006800FF - -PRMCIO 0x00601000-0x00601FFF VGA emulation - CRTC + attribute controller - -PRAMDAC 0x00680300-0x00680FFF (used for color lookup tables, hardware cursor, video overlay, PLL for clocking and pixel generation) -"USER" DAC 0x00681200-0x00681FFF - -DMA submission w/FIFO 0x00800000-0x00FFFFFF NV_USER - uses FIFO buffer - -PNVM / PDFB / VRAM 0x01000000-0x017FFFFF (actual VRAM amount depends on card, but max is 8MB) - -RAMIN 0x01C00000-0x01FFFFFF (note that this is actually mapped in the last 1mb of vram) - -contains ramht that has obj parameters for submission, configurable \ No newline at end of file diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt deleted file mode 100644 index 380e0281e..000000000 --- a/doc/nvidia_notes/NV3 DMA Engine.txt +++ /dev/null @@ -1,54 +0,0 @@ -NV3 DMA Engine -(DirectDraw Driver) - -Initially set CACHES, CACHE1_PULL0, CACHE1_PULL1, CACHE1_DMA0 to 1 - -Same for other areas - -CACHE1_PUSH1 contains CHID - -If it's different: - -If RmFifoFlushContext failed: Do nothing - -Set PULL0, PUSH0, Caches to 1, return false - - -If it's not: -DMA TLB PTE seems to be 1 for direct programming, maybe RM does it differently -Tag=FFFFFFFF -CACHE1_DMA1 - Number of bytes to send -CACHE1_DMA2 - Get offset -CACHE1_DMA3 - Bus address space (Area BAR0 mapped to? Or bar1?) - -TO START: -To set up DMA for for Cache1 Puller: CACHE1_PULL0 -> 1, changes to 0 when done -To set up DMA Cache1 Push: CACHE1_PUsh0 -> 1, changes to 0 when done -Set CACHES to 1 - -GO: Set DMA0 to 1 - -***** Implementation in Driver ****** - -You can dma to "localvidmem:", "sysvidmem:" or "sysmem:", this is represented by a driver - -CAUSE OF FAILURE: -the pfifo is never free because it never processes the submitted objects -which means that the FIFO is never free -which means that the drivers spin forever waiting for the fifo to be free - -DMA_OBJECT STRUCTURE IN RESOURCE MANAGER: -0x328: Valid -0x34c: base address? -0x374: actually do the transfer - -some objects don't actually need to do dma, for example, video patchcord, it just creates a structure in the driver, and rop just allocate ssome memory to put the data for the patchcord/rop thing - -dma start=nv3_mini dc67 -call of mthdCreate for ***DRIVER*** CLASS ID: a7b44, check ptr - - - - - - diff --git a/doc/nvidia_notes/NV_PFB_CONFIG_0.txt b/doc/nvidia_notes/NV_PFB_CONFIG_0.txt deleted file mode 100644 index dee3b646c..000000000 --- a/doc/nvidia_notes/NV_PFB_CONFIG_0.txt +++ /dev/null @@ -1,29 +0,0 @@ -NV_PFB_CONFIG_0 - -Observed Valus: -Drivers 0x1000 -BIOS 0x1114 - -Bits -5:0 Resolution -9:8 Pixel depth -12:12 Tiling -13:13 Tiling Debug -14:14 Tiling Debug Tile Size -17:15 "Tetris" tiling -19:18 "Tetris" tiling shift -22:20 Bank Swap -23 Unused - -NV_PFB_CONFIG_1 -2:0 CAS Latency -3:3 NEC Mode (PC-98?) -7:4 RAS Default / 9 Cycles -10:8 RAS PCHG -14:12 RAS Low -18:16 MRS to RAS -22:20 Write to Read -26:24 RAS to CAS -30:28 Read to Write -31:31 Read to PCFg - diff --git a/doc/nvidia_notes/PFIFO RAMHT RAMRO.txt b/doc/nvidia_notes/PFIFO RAMHT RAMRO.txt deleted file mode 100644 index 9b4c94718..000000000 --- a/doc/nvidia_notes/PFIFO RAMHT RAMRO.txt +++ /dev/null @@ -1,38 +0,0 @@ -PIO VS dma - -driver is DIRECTLY modifying pfifo - -8X8 channel setup - -Names are 32-bit integers >4096 - -RAMFC - DMA Context object 0,0 to 8,8 - -context = channel, render object, object type, offset in instance memory - -for a rectangle (type 0x47), object render = 1, channel 0, at 0x0400 in the ramht memory - -=0x00c70400 as the context - -the ramht hash : - -xor every byte of the hash individually and then xor that with the channel number - -so obj id 01020304 in channel 0 is 1 xor 2 xor 3 xor 4 xor 0 - -Store in RAMHT at + 4*16 = name -Store in RAMHT at + 4*16 + 4 = context - -then the ramin stuff starts at *0xc04000 since c00000 is the start of ramin [PCI BAR1] which is where you put the contents of the class struct - -nv_user - -Consider the 8x8 channels as 64 subchannels. -Now you can do: - -They seem to end at 0x880000 - -(0x880000)/64 = 0x2000 for each channel - -FAILURE -> RAMRO! - diff --git a/doc/nvidia_notes/RIVA fansites.txt b/doc/nvidia_notes/RIVA fansites.txt deleted file mode 100644 index d1cfaeb90..000000000 --- a/doc/nvidia_notes/RIVA fansites.txt +++ /dev/null @@ -1,26 +0,0 @@ -RIVA fansites (?????): -RIVA User's Group http://tiger.tnstate.edu:8080/ -RIVA 128 Homepage http://pages.prodigy.net/babblin5/Main.html -> Riva3D (riva3d.com) -Zone 128 http://www.tc.umn.edu/~reda0003/zone128/ -RIVAZone https://web.archive.org/web/19981212032348/http://www.rivazone.com/ (Launched January 2, 1998) -Dimension 128 http://dimension128.smartcom.net (early domain name that was mostly not archived) -> d128.com (1999-2001) -Riva3D https://web.archive.org/web/20000525110305/http://riva3d.gxnetwork.com/s3.html -nVNews https://web.archive.org/web/20001205171202/http://www.nvnews.net/ (1999-2015) - -BluesNews has stuff https://www.bluesnews.com/archives/ -(July 1996-present!) - -https://www.bluesnews.com/archives/july97-3.html July 21, 1997 ("unreleased nvidia RIVA chipset is indeed faster than 3dfx" (carmack) - -"However, using the nvidia RIVA 128 chip it runs 1 f/s faster" - -https://web.archive.org/web/19980615024744/http://www.ogr.com/columns/techtalk/technology_talk_0611_2.shtml First mention of NV10 (June 1998) - -"RIVA 128 Turbo" early ZX name -"Riva4" early TNT name - -https://web.archive.org/web/20001002193706/http://www.rivazone.com/files/rivalog.txt - -https://web.archive.org/web/20010422044820/http://www.rivazone.com/finger/finger.cgi?nick@finger.nvidia.com nvidia .plan files - -WAVE Report - april 1997 date for tapeout \ No newline at end of file diff --git a/doc/nvidia_notes/Versions.txt b/doc/nvidia_notes/Versions.txt deleted file mode 100644 index 052de854f..000000000 --- a/doc/nvidia_notes/Versions.txt +++ /dev/null @@ -1,8 +0,0 @@ -Name Base Version Notes Date API Support Platform -0.75_nt4 Version 0.75 No Resource Manager (miniport) 1997-08-15 GDI NT4.0 -0.77_win9x Version 0.77 Symbols (COFF/VXD) 1997-09-02 GDI, D3D5 -nv3quake.zip Version 1.21 OpenGL Alpha 1 1997-11-14 GDI, D3D5, OpenGL 1.1 (alpha; Build 151) Win9x -quakea2f.zip Version 1.21 OpenGL Alpha 2 1997-12-02 GDI, D3D5, OpenGL 1.1 (alpha; Build 258) Win9x -win95_131.zip Version 1.31 OpenGL Beta 1 1998-02-04 GDI, D3D5, OpenGL 1.1 (beta; Build 661) Win9x - - diff --git a/doc/nvidia_notes/gpucompanies.txt b/doc/nvidia_notes/gpucompanies.txt deleted file mode 100644 index 08a6c61c5..000000000 --- a/doc/nvidia_notes/gpucompanies.txt +++ /dev/null @@ -1,63 +0,0 @@ -GPU companies (the period they made gpus) - -DEC 19xx-1998 -HP 19xx-2000+ (possibly until present) -IBM 19xx-2002+ (possibly until present) -E&S 1968-2006 -Intergraph 1969-2000 -Apple 1976-present (some break) -Motorola 1977-1994+ (???) -TI 1979-1988+ -Matrox 1979-2014 -Hitachi 1981-1986 -SGI 1981-2009 -Intel 1983-present -Number Nine 1983-2000 -Tseng Labs 1983-1997 -Cirrus Logic 1984-1998 -Video 7 1985-1991 -C&T 1985-1999 -Imagination 1985-present -NCR 1986-1993 -Paradise/WD 1986-1996 -Gemini 1987-1990 -Genoa Systems 1987-1991 -Trident 1987-2003 -Oak Technology 1988-1997 -Realtek 1988-1997 -Compaq 1989-1991 -Sun 1989-2002(+?) -S3 Graphics 1989-2010 -Macronix 1989-1998 -Winbond 1989-1996+ -Tamarack 198x-1991+ -UMC 198x-1993 -Sigma Designs 198x-1996 -Acer 198x-1998 (roughly) -Fujitsu 198x-1998 -AMD 1991-present (really starting in 2006) -HMC 1991-1994 -Avance Logic 1991-1995 -Weitek <1991-1996 -Bitboys 1991-2006 -IIT 1992-1994 -Weitek 1992-1996(?) -Rendition 1993-1998 -ARK Logic 1993-1999 -S-MOS/Stellar 1994-1999 -Nvidia 1993-present -Alliance 1994-1997 -iGS 1994-1999 -3dfx 1994-2000 -3dlabs 1994-2006 -Silicon Motion 1995-200? -SiS 1995-2007 -Dynamic Pictures1996-1997 -NeoMagic 1996-2000 -GigaPixel 1997-2000 -Philips 1997-199x -Tatung 199x-199x -ASPEED 2004-present -Jingjia 2006-present - - diff --git a/doc/nvidia_notes/hardware cursor.txt b/doc/nvidia_notes/hardware cursor.txt deleted file mode 100644 index 0845778f4..000000000 --- a/doc/nvidia_notes/hardware cursor.txt +++ /dev/null @@ -1,21 +0,0 @@ -NV3/NV3T/NV4 hardware cursor - -Unlock extended CRTC registers - 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status.txt +++ /dev/null @@ -1,112 +0,0 @@ -Driver version: Windows 2000 Version 3.37 (23 March 1999) - SDK: Windows 2000 build 1996.1 -Features: - -Resource Manager Yes -DirectDraw Yes -OpenGL Yes -Direct3D No - - -get started: -MUST USE X86 WINDBG -Does older windbg support coff??? - -sxe ld nv3_mini.sys -bp nv3_mini + 0x409ac - 0x10000 (nv3_mini+0x309ac) - -offset purpose -30a1a RmInitRm call - -6be7 initClientInfo call -6878 initClientInfo -6bec Check for initClientInfo success -6bf4 initGrPatchPool call -6bf9 Check for initGrPatchPool success -6c01 initDmaListElementPool call -6c06 Check for initDmaListElementPool -6c1c initDisplayInfo call - -6c26 rmInitRm End - Success: eax=FFFFFFFFh / -1 -6c26 Fail eax=0 - -30c8b NvFindAdapter -30cb6 NvFindAdapter -> NVIsPresent call -1010 NVIsPresent function -102f NVIsPresent VideoPortGetAccessRanges call -103b NVIsPresent VideoPortGetAccessRanges call success check (only possible way to fail) -127c NVIsPresent end -30cbb NvFindAdapter -> NVIsPresent success check - Success: al=1 - Failure: al=0 -30cca NVIsPresent NVMapMemoryRanges call -e9e NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #1 [PCI Space] -ea4 NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #1 success check [PCI Space] -ebd NVIsPresent NVMapMemoryRanges VideoPortFreeDeviceBase [conditional] -ec3 NVIsPresent NVMapMemoryRanges VideoPortFreeDeviceBase [conditional] success check -ed6 NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #2 [MMIO] -edc NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #2 success check [MMIO] -f0c NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #3 [LFB/RAMIN?] -f12 NVIsPresent NVMapMemoryRanges VideoPortGetDeviceBase call #3 success check [LFB/RAMIN?] - -30ccf NvFindAdapter NVMapMemoryRanges success check - Success: eax=0 - Failure: eax=87 -30cf1 NvFindAdapter RmInitNvMapping call -6ce6 NvFindAdapter RmInitNvMapping -30cf6 NVIsPresent RmInitNvMapping success check - Success: eax!=0 (in practice 0xFFFFFFFF/-1) - Failure: eax=0 -30d5c NvFindAdapter -30d64 NvFindAdapter RmPostNvDevice call -6d88 RmPostNvDevice function -6d91 NvFindAdapter DevinitInitializeDevice call -6d96 NvFindAdapter DevinitInitializeDevice success check - Success: eax=0 (?) - Failure: eax=1 -e546 DevinitInitializeDevice function - [very complicated] - [several register reads] -e61d DevinitPrepDeviceForInit call -e641 DevinitPrepDeviceForInit function -e627 InitNV call -e67a InitNV function - -30d64 NVIsPresent RmPostNvDevice success check - Success: eax=0 (?) - Failure: eax=1 -30d78 NVIsPresent NVGetNVInfo call -30d7d NVIsPresent NVGetNVInfo success check - -3e9a NvFindAdapter end - Success: eax=0 - Fail eax=55 (RmInitNvMapping or NVIsPresent failed) - Fail eax=87 (NVMapMemoryRanges or NVMapFrameBuffer failed) - -30ea3 NVInitialize -30f02 NVStartIO -2aa6 NVInterrupt -30a2d NVGetChildDescriptor -30a9c NVGetPowerState -30b20 NVSetPowerState - - -Driver Init Status: -DriverEntry Success -rmInitRm -> initClientInfo Success -rmInitRm -> initGrPatchPool Success -rmInitRm -> initDmaListElementPool Success -rmInitRm -> initDisplayInfo Success -rmInitRm overall Success -NvFindAdapter Success 17:32 27/11/2024 -NvFindAdapter -> NvIsPresent Success 16:19 24/11/2024 -NvFindAdapter -> NvMapMemoryRanges Success 19:15 26/11/2024 -NvFindAdapter -> RmInitNvMapping Success 19:18 26/11/2024 -NvFindAdapter -> RmPostNvDevice Success 17:32 27/11/2024 -NvFindAdapter -> NVGetNVInfo Success 17:32 27/11/2024 -NvFindAdapter -> NVMapFrameBuffer Success 17:32 27/11/2024 - -00:00 30/12/2024: stateGr -> i2c_Write -22:31 31/12/2024: fifoService - -fix ptimer issue \ No newline at end of file diff --git a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt b/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt deleted file mode 100644 index b5643a2ea..000000000 --- a/doc/nvidia_notes/nv3 driver init status_2025-02-10.txt +++ /dev/null @@ -1,90 +0,0 @@ -nv3_disp: - -0x10fe -> DrvBitBlt -0x19be -> DrvCopyBits -0x597c -> DrvCreateDeviceBitmap -0x5a6e -> DrvDeleteDeviceBitmap -0x60b8 -> DrvTextOut -0x6248 -> DrvDestroyFont -0x64b8 -> DrvRealizeBrush -0x6a46 -> DrvDitherColor -0x797a -> DrvGetDirectDrawInfo -0x7b14 -> DrvEnableDirectDraw -0x7b70 -> DrvDisableDirectDraw -0x817c -> DrvPaint -0x81c2 -> DrvResetPDEV -0x82dc -> DrvEnableDriver -0x8312 -> DrvEnablePDEV -0x83ee -> DrvDisablePDEV -0x840a -> DrvCompletePDEV -0x8418 -> DrvSynchronise -0x845a -> DrvEnableSurface -0x851a -> DrvDisableSurface -0x8554 -> DrvAssertMode -0x8690 -> DrvGetModes -0xe59a -> DrvEscape -0xf3ee -> DrvFillPath -0xf3f6 -> DrvStrokePath -0xfa08 -> DrvLineTo -0x12fee -> DrvSetPalette -0x132a4 -> DrvMovePointer -0x13d20 -> DrvSetPointerShape -0x13dea -> DrvStretchBlt -0x147f2 -> DrvSetPixelFormat -0x1483c -> DrvDescribePixelFormat -0x1495a -> DrvClipChanged -0x255b8 -> DrvSwapBuffers - -DrvEnableDriver SUCCESS -DrvEnablePDEV SUCCESS 23:28 09/02/2025 - Check for cjCaps >= 0x130 && cjDevInfo >= 0x12C SUCCESS 23:31 09/02/2025 - EngAllocMem call SUCCESS 23:38 09/02/2025 - CreateOglGlobalMemory call SUCCESS 23:40 09/02/2025 - bInitializeModeFields call SUCCESS 23:41 09/02/2025 - bInitializePalette call SUCCESS 23:42 09/02/2025 - EngDeviceIoControl IOCTL 0x232020 (CHECK mini) SUCCESS - EngDeviceIoControl IOCTL 0x232044 (CHECK mini) SUCCESS (eax=0) -DrvCompletePDEV SUCCESS 23:52 09/02/2025 -DrvEnableSurface - bEnableHardware call SUCCESS 22:36 13/02/2025 - EngCreateSemaphore call #1 csCrtc SUCCESS 00:55 10/02/2025 - EngCreateSemaphore call #2 csFifo SUCCESS 00:57 10/02/2025 - EngDeviceIoControl IOCTL 0x230460 SUCCESS 00:57 10/02/2025 - EngDeviceIoControl IOCTL 0x230458 SUCCESS 00:57 10/02/2025 - NvAllocRoot SUCCESS 01:03 10/02/2025 - NvAllocDevice SUCCESS 01:04 10/02/2025 - NV3/NV4 architecture check SUCCESS 01:14 10/02/2025 - bAssertModeHardware call (bEnable=1) SUCCESS Passing starting with build at 02:23 10/02/2025 - EngDeviceIoControl IOCTL 0x23040C] SUCCESS Passing starting with build at 02:23 10/02/2025 - nv3_mini NVStartIO ioctlcode=0x23040C - NVSetMode - NV3SetMode SUCCESS 01:53 10/02/2025 - RmUnloadState SUCCESS 01:48 10/02/2025 - VBESetModeEx SUCCESS 01:51 10/02/2025 - NV_OEMEnableExtensions SUCCESS 01:52 10/02/2025 - UpdateArbitrationSettings SUCCESS 01:52 10/02/2025 - RmLoadState SUCCESS 01:53 10/02/2025 - NV3EnableCursor SUCCESS 01:54 10/02/2025 - NV3WaitUntilFinished SUCCESS 02:23 10/02/2025 - EngDeviceIoControl IOCTL 0x230408 SUCCESS 02:26 10/02/2025 - EngDeviceIoControl IOCTL 0x232024 SUCCESS 02:26 10/02/2025 - NvAllocHardware SUCCESS 02:29 10/02/2025 - bCreateStdPatches(?) SUCCESS (EAX=1!!!) 22:24 13/02/2025 - CHECK - NV4 N/A - vDestroyStdPatches(?) N/A - NV3_WaitForOneVerticalRefresh SUCCESS - EngDeviceIoControl IOCTL 0x230410 SUCCESS - - - SET UP CORRECT FUNCTION POINTERS - Indirect call (call dword [edi]) to NV3_WaitWhileGraphicsEngineBusy HANG 22:14 16/02/2025 - _heap_init call - bEnableOffscreenHeap call - bEnablePointer call - bEnableText call - bEnablePalette call - bEnableDirectDraw call - EngCreateBitmap call - EngAssociateBitmap call - -DrvDisableSurface: ONLY IN THE CASE OF FAILURE diff --git a/doc/nvidia_notes/nv3_object_classes.txt b/doc/nvidia_notes/nv3_object_classes.txt deleted file mode 100644 index 05d1d9bf3..000000000 --- a/doc/nvidia_notes/nv3_object_classes.txt +++ /dev/null @@ -1,37 +0,0 @@ -Object classes as understood by the GPU. - -(May be represented, in RAMFC, as 0x40+ 22:16) - -0x00 = Invalid -0x01 = beta factor -0x02 = ROP5 operation -0x03 = Chroma key -0x04 = Plane mask -0x05 = Clipping rectangle -0x06 = Pattern -0x07 = Rectangle -0x08 = Point -0x09 = Line -0x0A = Lin (line without starting or ending pixel) -0x0B = Triangle -0x0C = Windows 95 GDI text acceleration -0x0D = Memory to memory format -0x0E = Scaled image from memory -0x0F = INVALID -0x10 = Blit -0x11 = Image -0x12 = Bitmap -0x13 = INVALID -0x14 = Transfer to Memory -0x15 = Stretched image from CPU -0x16 = INVALID -0x17 = Direct3D 5.0 accelerated textured triangle w/zeta buffer -0x18 = Point w/zeta buffer -0x19 = INVALID -0x1A = INVALID -0x1B = INVALID -0x1C = Image in memory -0x1D = INVALID -0x1E = INVALID -0x1F = INVALID - \ No newline at end of file diff --git a/doc/nvidia_notes/nv3d3d_t.txt b/doc/nvidia_notes/nv3d3d_t.txt deleted file mode 100644 index c8579fd6c..000000000 --- a/doc/nvidia_notes/nv3d3d_t.txt +++ /dev/null @@ -1,161 +0,0 @@ -12=unk_int12 -16=unk_short16 -22=unk_short22 (seems to determine if nv_sys_ptr is valid) -24=unk_short24 -26=unk_short26 -44=unk_int44 -56=unk_int56 -60=unk_int60 -64=unk_short64 -66=unk_short66 - -82=unk_short82 - -362..822: - big_struct - (weird alignment?) - 477 - 489 - 505 - -1140=nv_sys_ptr - - -1156=unk_int1156 [start of structure] -1160=unk_int1160 - -1168=unk_int1168 [possibly a byte array of up to 16 bytes) - -1184=unk_int1184 - -1208=unk_int1208 -1212=unk_int1212 -1216=unk_int1216 -1220=unk_int1220 -1224=unk_int1224 - -1236=unk_int1236 -1240=unk_int1240 -1244=unk_int1244 -1248=unk_int1248 - -1256=unk_int1256 -1260=fog_table_enable -1264=unk_int1264 -1270=unk_int1270 -1272=unk_byte1272 -1273=unk_byte1273 -1274=unk_byte1274 (?) -1275=unk_byte1275 - -1316=unk_int1316 -1320=unk_int1320 - -1332=unk_int1332 - -1340=unk_int1340 -1344=unk_int1344 - -1356=unk_int1356 -1360=d3d_clear_enabled -1364=texture_enabled -1368=mipmap_size_max -1372=mipmap_levels -1376=user_mipmaps -1380=zoh_mode (bool) -1384=tex_heap -1388=text_size -1392=video_texture -1396=min_video_tex_size -1400=draw_prim -1404=spread_x -1408=spread_y -1412=size_adj -1416=turbo_adj -1420=dma_min_push_count -1424=dma_push_enable - -1436=unk_int1436 -1440=unk_int1440 - -1448=unk_int1448 -1452=unk_int1452 (set to value of unk_int1908) -1456=unk_int1456 (set to value of unk_int1956) -1460=unk_int1460 (set to value of unk_int2020) - -1516=unk_int1516 -1520=unk_int1520 -1524=unk_int1524 -1528=unk_int1528 -1532=unk_int1532 - -1548=unk_int1548 -1552=unk_int1552 -1556=unk_int1556 -1560=unk_int1560 -1564=unk_int1564 - -1600=unk_int1600 - -1612=unk_int1612 -1616=unk_int1616 -1620=unk_int1620 - -1632=unk_int1632 - -1640=unk_int1640 -1644=unk_ptr1644 - -1676=unk_int1676 -1680=unk_int1680 -1684=unk_int1684 -1688=unk_int1688 -1692=unk_int1692 -1696=unk_int1696 -1700=unk_int1700 - -1716=unk_int1716 -1720=unk_int1720 -1724=unk_int1724 -1728=unk_ptr1728 - -1848=unk_int1848 -1852=unk_int1852 -1856=unk_int1856 (unk_int1552 | 0x800) -1864=unk_func_ptr1864 -1868=unk_int1868 - -1884=unk_int1884 -1888=ptr_to_start_of_structure? -1892=hInstDll -1896=unk_int1896 -1900=unk_int1900 - -1908=unk_int1908 -1912=unk_int1912 -1916=unk_func_ptr1916 -1920=unk_func_ptr1920 - -1932=unk_func_ptr1932 -1936=unk_func_ptr1936 -1944=unk_func_ptr1944 - -1956..2020: Set of function pointrs - 1956=unk_int1956 - 1960=unk_int1960 - 1960=unk_func_ptr1960 - 1964=unk_func_ptr1964 - 1968=unk_func_ptr1968 - 1976=unk_func_ptr1976 - 1980=unk_func_ptr1980 - 1988=unk_func_ptr1988 - 1996=unk_func_ptr1996 - 2000=unk_func_ptr2000 - 2004=unk_func_ptr2004 - 2008=unk_func_ptr2008 - - 2020=unk_int2020 - -2024=unk_int2024 -2028=unk_int2028 -2032=unk_int2032 diff --git a/doc/nvidia_notes/old nouveau wiki.txt b/doc/nvidia_notes/old nouveau wiki.txt deleted file mode 100644 index c875954fd..000000000 --- a/doc/nvidia_notes/old nouveau wiki.txt +++ /dev/null @@ -1,9 +0,0 @@ -old nouveau wiki: -real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) - -nv3=16 bytes - -0x400000 - ((0x100000) - (0x100000 % 16)) - 16 + (0x100000 % 16) = 2ffff0 - - - \ No newline at end of file diff --git a/doc/nvidia_notes/rivatv_riva128.txt b/doc/nvidia_notes/rivatv_riva128.txt deleted file mode 100644 index 780ad5edd..000000000 --- a/doc/nvidia_notes/rivatv_riva128.txt +++ /dev/null @@ -1,2238 +0,0 @@ - - -Riva 128 documentation -====================== - -This document is based on kernel sources, XFree86 sources, open sources -released by nVidia and pure deduction. To make nVidia happy: - - /***************************************************************************\ -|* *| -|* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| -|* the copyright and as design patents pending on the design and *| -|* interface of the NV chips. Users and possessors of this source *| -|* code are hereby granted a nonexclusive, royalty-free copyright *| -|* and design patent license to use this code in individual and *| -|* commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *| -|* pending in the U.S. and foreign countries. *| -|* *| -|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| -|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| -|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| -|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| -|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| -|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| -|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| -|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| -|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| -|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| -|* PERFORMANCE OF THIS SOURCE CODE. *| -|* *| - \***************************************************************************/ - -Feel free to send me corrections, updates, suggestions about this document to: -fero@drama.obuda.kando.hu or rivatv-devel@lists.sourceforge.net -Any kind of info, hint or idea may be helpful. -Please visit the rivatv homepage at: -http://fero.koli.kando.hu/rivatv/ - - - -Rendering -========= - -DMA vs PIO ----------- - -Theese two methods are used to program the hardware. DMA method provides -better performance but it is harder to implement. Almost all of the released -sources uses PIO method. The rest of this document describes the PIO method. - - -Objects -------- - -The Riva rendering engine is an object-oriented hardware. (See the nVidia -docs at https://www.nvidia.com/nv/nvarch.nsf/Home?OpenView -> Documents -> -NV Programmer's Reference Manual) Do not take it serious, it's simplified -for the hardware, it is not like C++. -Each object has a name. The name is 32 bits long and should be unique. - - -FIFO Channels -------------- - -There are 8 channels for submitting graphical objects to the rendering engine. -Each channel contains 8 subchannels. The rules how channels and subchannels -are working is not clear for me yet. Channel 0 is usable without extra coding. -Other channels can not be used until the 'context switching' code is done. -FIFO channels are located in the CTRL memory at 0x00800000-0x0087FFFF. Each -channel is 64 kbytes long, each subchannel is 8 kbytes long. Registers of -subchannels are variable: their function depends on the type of the submitted -object. Registers are write only and 32 bits long except the 'Free' register. - -Offset Name(s) Valid object types ------- ----------------------------- ------------------ -0000 Object all -0010 Free (2 bytes, read only!) all -0100 Synchronize t V s3 -0100 NoOperation BKPCLTRbISMr DG -0104 StopAlarm t -0104 Notify BKPCLTRbISMr DG -0104 StopImage V -0108 StopCursor V -010c StopDac V -0180 DmaNotifies tBKPCLTRbISMrVDGs3 -0184 ClipRectangle LTR -0184 ColorKey bIS -0184 DmaImage M V -0184 DmaTexture D -0184 Pattern G -0184 DmaSource s -0184 DmaSurfaces 3 -0188 Pattern LTR SM -0188 ClipRectangle bI D -0188 Rop G -0188 DmaDestin s -018c Rop LTR SM -018c Pattern bI -018c DmaLut V -018c Surfaces3D D -018c Beta1 G -0190 Beta1 LTR SM -0190 Rop bI -0190 Surfaces G -0194 Surfaces LTR SM -0194 Beta1 bI -0194 DmaCursor V -0198 Surfaces I -019c Surfaces b -02fc Operation LTRbIS G -02fc Get V -0300 Time0 t -0300 Beta1d31 B -0300 ColorFormat KP LTR ISM G -0300 Point C -0300 ControlPointIn b -0300 Rop r -0300 Image V -0300 Format s -0300 Pitch 3 -0304 Time1 t -0304 Color K LTR -0304 MonochromeFormat P G -0304 Size C -0304 ControlPointOut b -0304 Point I -0304 SizeIn S -0304 TextureOffset D -0304 Pitch s -0304 OffsetColor 3 -0300 Operation M -0308 AlarmNotify t -0308 MonochromeShape P -0308 Size b -0308 SizeOut I -0308 DxDu S -0308 ClipPoint M -0308 TextureFormat D -0308 OffsetSource s -0308 OffsetZeta 3 -030c SizeIn I -030c DyDv S -030c ClipSize M -030c TextureFilter D -030c OffsetDestin s -0310 MonochromeColor0 P -0310 TrianglePoint0 T -0310 ClipPoint S -0310 ImageOutPoint M -0310 FogColor D -0314 MonochromeColor1 P -0314 TrianglePoint1 T -0314 ClipSize S -0314 ImageOutSize M -0314 Control0 D -0318 MonochromePattern0 P -0318 TrianglePoint2 T -0318 Point12d4 S -0318 DxDu M -0318 Control1 D -031c MonochromePattern1 P -031c DyDv M -0320 Triangle32Point0X T -0324 Triangle32Point0Y T -0328 Triangle32Point1X T -032c Triangle32Point1Y T -0330 Triangle32Point2X T -0334 Triangle32Point2Y T -0340 Cursor V -0358 CursorPointOutA V -0380 Dac V -03a0 PixelClock V -03fc Color1A G -0400 Lin L -0400 Trimesh T -0400 Rectangle R -0400 Color IS -0400 ImageInSize M -0400 UnclippedRectangle G -0404 ImageInFormat M -0408 ImageInOffset M -040c ImageInPoint M -0480 Lin32 L -0480 Trimesh32 T -0500 PolyLin L -0500 ColorTriangle T -0580 PolyLin32 L -0580 ColorTrimesh T -0600 ColorPolyLin L -07f4 ClipPoint0B G -07f8 ClipPoint0B G -07fc Color1B G -0800 ClippedRectangle G -0bec ClipPoint0C G -0bf0 ClipPoint1C G -0bf4 Color1C G -0bf8 SizeC G -0bfc PointC G -0c00 MonochromeColor1C G -0fe8 ClipPoint0D G -0fec ClipPoint1D G -0ff0 Color1D G -0ff4 SizeInD G -0ff8 SizeOutD G -0ffc PointD G -1000 Tlvertex D -1000 MonochromeColor1D G -13e4 ClipPoint0E G -13e8 ClipPoint1E G -13ec Color0E G -13f0 Color1E G -13f4 SizeInE G -13f8 SizeOutE G -13fc PointE G -1400 MonochromeColor01E G - -t=timer -B=beta1 (0x41) -K=color key (0x43) -P=pattern (0x46) -C=clip rectangle (0x45) -L=solid line (0x4a) -T=solid triangle (0x4b) -R=solid rectangle (0x47) -b=image blit (0x50) -I=image from CPU (0x51) -S=stretched image from CPU (0x55) -M=scaled image from memory (0x4e) -r=raster operation (0x42) -V=video lut cursor dac -D=DX3 textured triangle (0x57) -G=GDI rectangle text (0x4c?) -s=Surfaces 2D -3=Surfaces 3D - -Contexts --------- - -Context is a 32 bit record of channel id, object type and pointer to the -object. - -Bits 24-30: channel id -Bit 23: rendering - 0x0 other object (DMA?) - 0x1 renderable object -Bits 16-22: object type - 0x41 beta1 - 0x42 raster operation - 0x43 color key - 0x44 plane - 0x45 clipping rectangle - 0x46 pattern - 0x47 solid rectangle - 0x49 unknown line - 0x4A solid line - 0x4B solid triangle - 0x4C GDI rectangle - 0x4E scaled image from memory - 0x50 blit - 0x51 image from CPU - 0x52 bitmap - 0x55 streched image from CPU - 0x57 DX3 textured triangle - 0x?? Surfaces 2D - 0x?? Surfaces 3D - 0x?? Timer - 0x?? Video lut cursor dac - and many more... -Bits 0-15: offset in instance memory (RAMIN) / 16 - -Each graphic object has a context. Context determines the type (triangle, -raster operation, bitmap, etc) of the object. Don't ask me why this thingy -is called context: I really don't know. - - -Hash table ----------- - -The hash table (HT) is located in the instance memory area (RAMIN). -See RAMHT register in section FIFO registers. -The HT contains 8 byte length records of object names and contexts. Each -record is placed in the table by it's hash key. The key is computed as -follows: each byte of the object's name and the channel id are XOR-ed -together, and this value is multiplied by the hash depth. More explanation -on hash tables can be found in database books. -The purpose of HT is to provide connection between object names and contexts -for the graphic hardware. But it may be useful for your software driver too. - - -FIFO context table ------------------- - -The FIFO context table (FC) is located in the instance memory area (RAMIN). -See RAMFC register in section FIFO registers. -FC contains the context values for each subchannel. E.g. if FC begins -at 0x1C00: -0x1C00 Context of object in channel 0, subchannel 0 -0x1C04 Context of object in channel 0, subchannel 1 -0x1C08 Context of object in channel 0, subchannel 2 -... -0x1C1C Context of object in channel 0, subchannel 7 -0x1C20 Context of object in channel 1, subchannel 0 -0x1C24 Context of object in channel 1, subchannel 1 -... -0x1CFC Context of object in channel 7, subchannel 7 - - -Example: How to render a solid rectangle? ------------------------------------------ - -- Choose a name for your rectangle. E.g.: 0x01020304 -- Select an unused area in the instance memory. Let it be 0x00c04000 -- Calculate the context: - Channel = 0x00 - Render object = 1 - Object type = 0x47 (rectangle) - Offset in intance memory = 0x4000 / 16 = 0x0400 - Context = 0x00c70400 -- Place the name - context pair in the hash table (HT begins at 0x00c00000): - Hash key = 01 xor 02 xor 03 xor 04 xor 00 = 0x04 - (each byte of the name) (channel id) - *(0x00c00000 + 0x04 * 16) = 0x00000001; // name - *(0x00c00000 + 0x04 * 16) + 4 = 0x00c70400; // context -- Fill in the instace ram: - *(0x00c04000) = 0x00100000; // 15bpp (TODO: decode this magic) - *(0x00c04004) = 0x00000000; // not used yet - *(0x00c04008) = 0x00000000; // not used yet - *(0x00c0400c) = 0x00000000; // not used yet -- At this point the FIFO channel is ready for submitting rectangles. -- Submit the first rectangle: - write the object's name to channel 0 (subchannel 0): - *(0x00800000) = 0x00000001; -- At this point subchannel 0 becomes a rectangle. -- Submit the attributes of the rectangle: - write x,y coordinates: - (0x00800400) = 0x01000200; // x=0x100 y=0x200 - size: - (0x00800404) = 0x00100020; // width=0x10 height=0x20 -- After size is submitted, our rectangle appears on the screen. -- Subsequent rectangles may be submitted by re-sending new attributes. - - -Speculation: How to make video in working? ------------------------------------------- - -V4L stuff and hardware rendered rectangles have some similarities: -- both have color keys -- both have clipping rectangles -- both are stretchable -I suppose video in feature is implemented by rendered objects. A chroma-keyed -and clipped rectangle with 'live texture' is blitted on the screen. -Thats all. :) - - - -Memory layout -============= - -Three memory regions are accessible via the PCI (or AGP) interface: -- CTRL region (PCI base 0) -- FB region (PCI base 1) -- BIOS ROM (PCI base 2) - - -CTRL region ------------ - -The CTRL region contains memory mapped IO ports. Most of them are 32-bit -registers. The registers are grouped by functionality: - -- MC: master control (0x00000000-0x00000FFF) -- BUS: (0x00001000-0x00001FFF) -- FIFO: for DMA and PIO stuff (0x00002000-0x00003FFF) -- TIMER: built-in timer (0x00009000-0x00009FFF) -- VIO: 8 bit SVGA (MISC, GRAPH, SEQ) registers (0x000C0000-0x00C00FFF) -- FB: framebuffer properties (0x00100000-0x00100FFF) -- EXTDEV: external devices (0x00101000-0x00101FFF) -- GRAPH: (0x00400000-0x00401FFF) -- PCIO: 8 bit SVGA (CRTC, ATTR) registers (0x00601000-0x00601FFF) -- RAMDAC: RAMDAC timings (0x00680000-0x00680FFF) -- PDIO: 8 bit registers (0x00681000-0x00681FFF) -- FIFO channels: (0x00800000-0x0087FFFF) -(List in not complete.) - - -FB region ---------- - -This region contains the video memory and the instance memory. -Video memory begins at offset 0x00000000. Instance memory (RAMIN) -begins at offset 0x00C00000. (Note: Riva TNT (and higher) cards have -their instance memory in the CTRL region.) - - - -Master control -============== - -The MC registers begin at 0x00000000 in the CTRL region. They control the -master IRQ. - -Interrupt 0 register --------------------- -Name: INTR_0 -Offset: 0x00000100 -4 bytes, read-write - -Bit 0: PAUDIO (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 4: PMEDIA (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 8: PFIFO (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 12: PGRAPH0 (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 13: PGRAPH1 (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 16: PVIDEO (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 20: PTIMER (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 24: PFB (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 28: PBUS (-V, read-only) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - -Bit 31: SOFTWARE (IV, read-write) - NOT_PENDING 0x0 (default, read-write) - PENDING 0x1 (read-write) - -Interrupt 0 enable register ---------------------------- -Name: INTR_EN_0 -Offset: 0x00000140 -4 bytes, read-write - -Bits 0-1: INTA (IV, read-write) - DISABLED 0x0 (default, read-write) - HARDWARE 0x1 (read-write) - SOFTWARE 0x2 (read-write) - -Enable (what?) register ------------------------ -Name: ENABLE -Offset: 0x00000200 -4 bytes, read-write - - - -Bus -=== - -The BUS registers begin at 0x00001000 in the CTRL region. They are -undiscovered. - -Debug 0 register ----------------- -Name: DEBUG_0 -Offset: 0x00001080 -4 bytes, read-write - -Bit 0: MODE (IV, read-write) - MODE_DISABLED 0x0 (default, read-write) - MODE_ENABLED 0x1 (read-write) - -Bit 4: DESKEWER (IV, read-write) - ENABLED 0x0 (default, read-write) - -Bits 8-11: FBIO_SCLK_DELAY (IV, read-write) - 0x0 (default, read-write) - -Bits 12-15: FBIO_FBCLK_DELAY (IV, read-write) - 0x3 (default, read-write) - -Debug 1 register ----------------- -Name: DEBUG_1 -Offset: 0x00001084 -4 bytes, read-write - -Bit 0: PCIM_THROTTLE (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -Bit 1: PCIM_CMD (IV, read-write) - SIZE_BASED 0x0 (default, read-write) - MRL_ONLY 0x1 (read-write) - -Bit 2: PCIM_AGP (IV, read-write) - IS_AGP 0x0 (default, read-write) - IS_PCI 0x1 (read-write) - -Bits 3-4: AGPM_CMD (IV, read-write) - HP_ON_1ST 0x0 (read-write) - LP_ONLY 0x1 (default, read-write) - HP_ONLY 0x2 (read-write) - -Bit 5: PCIS_WRITE (IV, read-write) - 0_CYCLE 0x0 (read-write) - 1_CYCLE 0x1 (default, read-write) - -Bit 6: PCIS_2_1 (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -Bit 7: PCIS_RETRY (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -Bit 8: PCIS_RD_BURST (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 9: PCIS_WR_BURST (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 10: PCIS_EARLY_RTY (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -Bit 11: PCIS_RMAIO (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -Bit 12: PCIS_CPUQ (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -Bit 13: DPSH_PIPE (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 14: SPARE1 (IV, read-write) - ZERO 0x0 (default, read-write) - ONE 0x1 (read-write) - -Bit 15: SPARE2 (IV, read-write) - ZERO 0x0 (default, read-write) - ONE 0x1 (read-write) - -Bit 16: SPARE3 (IV, read-write) - ZERO 0x0 (default, read-write) - ONE 0x1 (read-write) - - - -FIFO -==== - -The BUS registers begin at 0x00002000 in the CTRL region. - -Interrupt 0 register --------------------- - -Name: INTR_0 -Offset: 0x00002100 -4 bytes, read-write - -Bit 0: CACHE_ERROR (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 4: RUNOUT (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 8: RUNOUT_OVERFLOW (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 12: DMA_PUSHER (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 16: DMA_PTE (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Interrupt 0 enable register ---------------------------- - -Name: INTR_EN_0 -Offset: 0x00002140 -4 bytes, read-write - -Bit 0: CACHE_ERROR (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 4: RUNOUT (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 8: RUNOUT_OVERFLOW (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Config 0 register ------------------ - -Name: CONFIG_0 -Offset: 0x00002200 -4 bytes, read-write - -Hash table register -------------------- - -Hardware hash table offset (in instance memory) and size. - -Name: RAMHT -Offset: 0x00002210 -4 bytes, read-write - -Bits 12-15: BASE_ADDRESS (XV, read-write) - -Bits 16-17: SIZE (XV, read-write) - 4K 0x0 (default, read-write) - 8K 0x1 (read-write) - 16K 0x2 (read-write) - 32K 0x3 (read-write) - -FIFO context table offset -------------------------- - -Name: RAMFC -Offset: 0x00002214 -4 bytes, read-write - -Bits 9-15: BASE_ADDRESS (XV, read-write) - -Runout table register ---------------------- - -FIFO runout table offset and size. - -Name: RAMRO -Offset: 0x00002218 -4 bytes, read-write - -Bits 9-15: BASE_ADDRESS (XV, read-write) - -Bit 16: SIZE (XV, read-write) - 512 0x0 (default, read-write) - 8K 0x1 (read-write) - -Runout status register ----------------------- - -Name: RUNOUT_STATUS -Offset: 0x00002400 -4 bytes, read-only - -Runout put register -------------------- - -Index in runout table. - -Name: RUNOUT_PUT -Offset: 0x00002410 -4 bytes, read-write - -Runout get register -------------------- - -Index in runout table. - -Name: RUNOUT_GET -Offset: 0x00002420 -4 bytes, read-write - -Caches register ---------------- - -Name: CACHES -Offset: 0x00002500 -4 bytes, read-write - -Bit 0: REASSIGN (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Cache 0 push 0 register ------------------------ - -Name: CACHE0_PUSH0 -Offset: 0x00003000 -4 bytes, read-write - -Bit 0: ACCESS (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Cache 0 push 1 register ------------------------ - -Name: CACHE0_PUSH1 -Offset: 0x00003004 -4 bytes, read-write - -Bits 0-6: CHID (XU, read-write) - -Cache 0 pull 0 register ------------------------ - -Name: CACHE0_PULL0 -Offset: 0x00003040 -4 bytes, read-write - -Bit 0: ACCESS (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Cache 1 push 0 register ------------------------ - -Name: CACHE1_PUSH0 -Offset: 0x00003200 -4 bytes, read-write - -Bit 0: ACCESS (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Cache 1 push 1 register ------------------------ - -Name: CACHE1_PUSH1 -Offset: 0x00003204 -4 bytes, read-write - -Bits 0-6: CHID (XU, read-write) - -Cache 1 put register --------------------- - -Name: CACHE1_PUT -Offset: 0x00003210 -4 bytes, read-write - -Bits 2-6: ADDRESS (XU, read-write) - -Cache 1 DMA 0 register ------------------------ - -Name: CACHE1_DMA0 -Offset: 0x00003220 -4 bytes, read-write - -Cache 1 DMA 1 register ------------------------ - -Name: CACHE1_DMA1 -Offset: 0x00003224 -4 bytes, read-write - -Cache 1 DMA 2 register ------------------------ - -Name: CACHE1_DMA2 -Offset: 0x00003228 -4 bytes, read-write - -Cache 1 pull 0 register ------------------------ - -Name: CACHE1_PULL0 -Offset: 0x00003240 -4 bytes, read-write - -Bit 0: ACCESS (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Cache 1 pull 1 register ------------------------ - -Name: CACHE1_PULL1 -Offset: 0x00003250 -4 bytes, read-write - -Bit 4: CTX (XV, read-write) - CLEAN 0x0 (read-write) - DIRTY 0x1 (read-write) - -Cache 1 get register --------------------- - -Name: CACHE1_GET -Offset: 0x00003270 -4 bytes, read-write - -Bits 2-6: ADDRESS (XU, read-write) - -Cache 1 context registers -------------------------- - -8 context registers for each channel (I guess). - -Name: CACHE1_CTX -Offset: 0x00003280+i*16 (0 <= i < 8) -8*16(4?) bytes, read-write - - - -Framebuffer properties -====================== - -The FB registers begin at 0x00100000 in the CTRL region. - -Boot 0 register ---------------- - -Name: BOOT_0 -Offset: 0x00100000 -4 bytes, read-write - -Bits 0-1: RAM_AMOUNT (IV, read-write) - 1MB 0x0 (read-write) - 2MB 0x1 (read-write) - 4MB 0x2 (read-write) - 8MB 0x0 (read-write) - UNDEFINED 0x3 (read-write) - DEFAULT 0x2 (default, read-write) - -Bit 2: RAM_WIDTH_128 (-V, read-write) - OFF 0x0 (read-write) - ON 0x1 (read-write) - -Bit 3: RAM_BANKS (IV, read-write) - 2BANK 0x0 (default, read-write) - 4BANK 0x1 (read-write) - -Bit 4: RAMDATA_TWIDDLE (IV, read-write) - OFF 0x0 (default, read-write) - ON 0x1 (read-write) - -Bit 5: RAM_AMOUNT_EXTENSION (IV, read-write) - OFF 0x0 (default, read-write) - 8MB 0x1 (read-write) - -Delay 1 register ----------------- - -Name: DELAY_1 -Offset: 0x00100044 -4 bytes, read-write - -Bits 0-1: WRITE_ENABLE_RISE (IU, read-write) - WRITE_ENABLE_RISE_0 0x0 (default, read-write) - -Bits 4-5: WRITE_ENABLE_FALL (IU, read-write) - WRITE_ENABLE_FALL_0 0x0 (default, read-write) - -Bits 8-9: CAS_ENABLE_RISE (IU, read-write) - CAS_ENABLE_RISE_0 0x0 (default, read-write) - -Bits 12-13: CAS_ENABLE_FALL (IU, read-write) - CAS_ENABLE_FALL_0 0x0 (default, read-write) - -Bits 16-17: OUTPUT_DATA (IU, read-write) - OUTPUT_DATA_0 0x0 (default, read-write) - -Bits 20-21: RAS_ENABLE (IU, read-write) - RAS_ENABLE_0 0x0 (default, read-write) - -Debug 0 register ----------------- - -Name: DEBUG_0 -Offset: 0x00100080 -4 bytes, read-write - -Bit 4: REFRESH (IV, read-write) - ENABLED 0x0 (default, read-write) - DISABLED 0x1 (read-write) - -Green 0 register ----------------- - -Name: GREEN_0 -Offset: 0x001000C0 -4 bytes, read-write - -Bits 0-1: LEVEL (IV, read-write) - VIDEO_ENABLED 0x0 (read-write) - VIDEO_DISABLED 0x1 (read-write) - TIMING_DISABLED 0x2 (read-write) - MEMORY_DISABLED 0x3 (default, read-write) - -Config 0 register ------------------ - -Name: CONFIG_0 -Offset: 0x00100200 -4 bytes, read-write - -Bits 0-5: RESOLUTION (IV, read-write) - 320_PIXELS 0x0a (read-write) - 400_PIXELS 0x0d (read-write) - 480_PIXELS 0x0f (read-write) - 512_PIXELS 0x10 (read-write) - 640_PIXELS 0x14 (read-write) - 800_PIXELS 0x19 (read-write) - 960_PIXELS 0x1e (read-write) - 1024_PIXELS 0x20 (read-write) - 1152_PIXELS 0x24 (read-write) - 1280_PIXELS 0x28 (read-write) - 1600_PIXELS 0x32 (read-write) - DEFAULT 0x14 (default, read-write) - -Bits 8-9: PIXEL_DEPTH (IV, read-write) - 8_BITS 0x1 (read-write) - 16_BITS 0x2 (read-write) - 32_BITS 0x3 (read-write) - DEFAULT 0x1 (default, read-write) - -Bit 12: TILING (IV, read-write) - ENABLED 0x0 (read-write) - DISABLED 0x1 (default, read-write) - - -Bits 13-23: TILING_DEBUG (IV, read-write) - DISABLED 0x0 (read-write) - -RTL(?) register ---------------- - -Name: RTL -Offset: 0x00100??? -4 bytes, read-write - -Bits 0-1: S (IU, read-write) - DEFAULT 0x2 (default, read-write) - -Bits 4-5: V (IU, read-write) - DEFAULT 0x2 (default, read-write) - -Bits 8-9: M (IU, read-write) - DEFAULT 0x2 (default, read-write) - -Bits 12-13: H (IU, read-write) - DEFAULT 0x1 (default, read-write) - -Bits 16-17: A (IU, read-write) - DEFAULT 0x1 (default, read-write) - -Bits 20-21: G (IU, read-write) - DEFAULT 0x1 (default, read-write) - -Bit 24: ARB_GR_HI_PRIOR (IU, read-write) - DEFAULT 0x0 (default, read-write) - -Bit 28: ARB_MEDIA_HI_PRIOR (IU, read-write) - DEFAULT 0x0 (default, read-write) - - - -External devices -================ - -The EXTDEV registers begin at 0x00101000 in the CTRL region. - -Boot 0 register ---------------- - -Name: BOOT_0 -Offset: 0x00101000 -4 bytes, read-write - -Bit 2: STRAP_RAM_TYPE (XV, read-write) - SGRAM_8MBIT 0x1 (read-write) - SGRAM_16MBIT 0x0 (read-write) - -Bit 11: STRAP_OVERWRITE (IV, read-write) - ENABLED 0x1 (read-write) - -Bit 4: STRAP_RAM_WIDTH (XV, read-write) - 64 0x0 (read-write) - 128 0x1 (read-write) - - - -GRAPH -===== - -The GRAPH registers begin at 0x00400000 in the CTRL region. - -Debug 0 register ----------------- - -Name: DEBUG_0 -Offset: 0x00400080 -4 bytes, read-write - -Bit 0: STATE (-V, clear(check?)-write) - NORMAL 0x0 (clear(check?)-write) - RESET 0x1 (write-only) - -Bit 4: BULK_READS (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 20: WRITE_ONLY_ROPS_2D (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 24: DRAWDIR_AUTO (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Debug 1 register ----------------- - -Name: DEBUG_1 -Offset: 0x00400084 -4 bytes, read-write - -Bit 0: VOLATILE_RESET (IV, read-write) - NOT_LAST 0x0 (default, read-write) - LAST 0x1 (read-write) - -Bit 16: INSTANCE (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 20: CTX (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Debug 2 register ----------------- - -Name: DEBUG_2 -Offset: 0x00400088 -4 bytes, read-write - -Bit 0: AVOID_RMW_BLEND (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 8: DPWR_FIFO (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Bit 28: VOLATILE_RESET (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Debug 3 register ----------------- - -Name: DEBUG_3 -Offset: 0x0040008C -4 bytes, read-write - -Bit 24: HONOR_ALPHA (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Interrupt 0 register --------------------- - -Name: INTR_0 -Offset: 0x00400100 -4 bytes, read-write - -Bit 0: RESERVED (-V, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 4: CONTEXT_SWITCH (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 8: VBLANK (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 12: RANGE (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 16: METHOD_COUNT (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 20: FORMAT (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 24: COMPLEX_CLIP (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 28: NOTIFY (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Interrupt 1 register --------------------- - -Name: INTR_1 -Offset: 0x00400104 -4 bytes, read-write - -Bit 0: METHOD (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 4: DATA (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 12: DOUBLE_NOTIFY (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 16: CTXSW_NOTIFY (IV, read-write) - NOT_PENDING 0x0 (default, read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Interrupt 0 enable register ---------------------------- - -Name: INTR_EN_0 -Offset: 0x00400140 -4 bytes, read-write - -Interrupt 1 enable register ---------------------------- - -Name: INTR_EN_1 -Offset: 0x00400144 -4 bytes, read-write - -Context switch register ------------------------ - -Name: CTX_SWITCH -Offset: 0x00400180 -4 bytes, read-write - -Context control register ------------------------- - -Name: CTX_CONTROL -Offset: 0x00400190 -4 bytes, read-write - -Bits 0-1: MINIMUM_TIME (IV, read-write) - 33US 0x0 (default, read-write) - 262US 0x1 (read-write) - 2MS 0x2 (read-write) - 17MS 0x3 (read-write) - -Bit 8: TIME (IV, read-write) - EXPIRED 0x0 (default, read-write) - NOT_EXPIRED 0x1 (read-write) - -Bit 16: CHID (IV, read-write) - INVALID 0x0 (default, read-write) - VALID 0x1 (read-write) - -Bit 20: SWITCH (-V, read-only) - UNAVAILABLE 0x0 (read-only) - AVAILABLE 0x1 (read-only) - -Bit 24: SWITCHING (IV, read-write) - IDLE 0x0 (default, read-write) - BUSY 0x1 (read-write) - -Bit 28: DEVICE (IV, read-write) - DISABLED 0x0 (default, read-write) - ENABLED 0x1 (read-write) - -Context user register ---------------------- - -Name: CTX_USER -Offset: 0x00400194 -4 bytes, read-write - -Context cache registers ------------------------ - -8 context registers for each channel (I guess). - -Name: CTX_CACHE -Offset: 0x004001a0+i*4 (0 <= i 8) -8*4 bytes, read-write - -Absolute X RAM registers ------------------------- - -Name: ABS_X_RAM -Offset: 0x00400400+i*4 (0 <= i < 32) -32*4 bytes, read-write - -Absolute Y RAM registers ------------------------- - -Name: ABS_Y_RAM -Offset: 0x00400480+i*4 (0 <= i < 32) -32*4 bytes, read-write - -X misc register ---------------- - -Name: X_MISC -Offset: 0x00400500 -4 bytes, read-write - -Y misc register ---------------- - -Name: Y_MISC -Offset: 0x00400504 -4 bytes, read-write - -Exceptions register -------------------- - -Name: EXCEPTIONS -Offset: 0x00400508 -4 bytes, read-write - -Source color register ---------------------- - -Name: SOURCE_COLOR -Offset: 0x0040050C -4 bytes, read-write - -XY logic misc 0 register ------------------------- - -Name: XY_LOGIC_MISC0 -Offset: 0x00400514 -4 bytes, read-write - -XY logic misc 1 register ------------------------- - -Name: XY_LOGIC_MISC1 -Offset: 0x00400518 -4 bytes, read-write - - DVDY_VALUE 0x0 (default, read-write) (???) - -XY logic misc 2 register ------------------------- - -Name: XY_LOGIC_MISC2 -Offset: 0x0040051C -4 bytes, read-write - -XY logic misc 3 register ------------------------- - -Name: XY_LOGIC_MISC3 -Offset: 0x00400520 -4 bytes, read-write - -Clip X 0 register ------------------ - -Name: CLIPX_0 -Offset: 0x00400524 -4 bytes, read-write - -Clip X 1 register ------------------ - -Name: CLIPX_1 -Offset: 0x00400528 -4 bytes, read-write - -Clip Y 0 register ------------------ - -Name: CLIPY_0 -Offset: 0x0040052c -4 bytes, read-write - -Clip Y 1 register ------------------ - -Name: CLIPY_1 -Offset: 0x00400530 -4 bytes, read-write - -Absolute iclip X max. register ------------------------------- - -Name: ABS_ICLIP_XMAX -Offset: 0x00400534 -4 bytes, read-write - -Absolute iclip Y max. register ------------------------------- - -Name: ABS_ICLIP_YMAX -Offset: 0x00400538 -4 bytes, read-write - -Absolute uclip X min. register ------------------------------- - -Name: ABS_UCLIP_XMIN -Offset: 0x0040053C -4 bytes, read-write - -Absolute uclip Y min. register ------------------------------- - -Name: ABS_UCLIP_YMIN -Offset: 0x00400540 -4 bytes, read-write - -Absolute uclip X max. register ------------------------------- - -Name: ABS_UCLIP_XMAX -Offset: 0x00400544 -4 bytes, read-write - -Absolute uclip Y max. register ------------------------------- - -Name: ABS_UCLIP_YMAX -Offset: 0x00400548 -4 bytes, read-write - -Absolute uclipa X min. register ------------------------------- - -Name: ABS_UCLIPA_XMIN -Offset: 0x00400560 -4 bytes, read-write - -Absolute uclipa Y min. register ------------------------------- - -Name: ABS_UCLIPA_YMIN -Offset: 0x00400564 -4 bytes, read-write - -Absolute uclipa X max. register ------------------------------- - -Name: ABS_UCLIPA_XMAX -Offset: 0x00400568 -4 bytes, read-write - -Absolute uclipa Y max. register ------------------------------- - -Name: ABS_UCLIPA_YMAX -Offset: 0x0040056C -4 bytes, read-write - -Source canvas min. register ---------------------------- - -Name: SRC_CANVAS_MIN -Offset: 0x00400550 -4 bytes, read-write - -Source canvas max. register ---------------------------- - -Name: SRC_CANVAS_MAX -Offset: 0x00400554 -4 bytes, read-write - -Destination canvas min. register --------------------------------- - -Name: DST_CANVAS_MIN -Offset: 0x00400558 -4 bytes, read-write - -Destination canvas max. register --------------------------------- - -Name: DST_CANVAS_MAX -Offset: 0x0040055C -4 bytes, read-write - -Pattern color 0 0 register --------------------------- - -Name: PATT_COLOR0_0 -Offset: 0x00400600 -4 bytes, read-write - -Pattern color 0 1 register --------------------------- - -Name: PATT_COLOR0_1 -Offset: 0x00400604 -4 bytes, read-write - -Pattern color 1 0 register --------------------------- - -Name: PATT_COLOR1_0 -Offset: 0x00400608 -4 bytes, read-write - -Pattern color 1 1 register --------------------------- - -Name: PATT_COLOR1_1 -Offset: 0x0040060C -4 bytes, read-write - -Pattern registers ------------------ - -Name: PATTERN -Offset: 0x00400610+i*4 (0 <=i < 2) -2*4 bytes, read-write - -Pattern shape register ----------------------- - -Name: PATTERN_SHAPE -Offset: 0x00400618 -4 bytes, read-write - -Bits 0-1: VALUE (XV, read-write) - 8X8 0x0 (read-write) - 64X1 0x1 (read-write) - 1X64 0x2 (read-write) - -Monochrome color 0 register ---------------------------- - -Name: MONO_COLOR0 -Offset: 0x0040061C -4 bytes, read-write - -Raster operation register -------------------------- - -Name: ROP3 -Offset: 0x00400624 -4 bytes, read-write - -Plane mask register -------------------- - -Name: PLANE_MASK -Offset: 0x00400628 -4 bytes, read-write - -Chroma register ---------------- - -Name: CHROMA -Offset: 0x0040062C -4 bytes, read-write - -B(?) offset 0 register ----------------------- - -Name: BOFFSET0 -Offset: 0x00400630 -4 bytes, read-write - -B(?) offset 1 register ----------------------- - -Name: BOFFSET1 -Offset: 0x00400634 -4 bytes, read-write - -B(?) offset 2 register ----------------------- - -Name: BOFFSET2 -Offset: 0x00400638 -4 bytes, read-write - -B(?) offset 3 register ----------------------- - -Name: BOFFSET3 -Offset: 0x0040063C -4 bytes, read-write - -Beta register -------------- - -Name: BETA -Offset: 0x00400640 -4 bytes, read-write - -Control out register --------------------- - -Name: CONTROL_OUT -Offset: 0x00400644 -4 bytes, read-write - -B(?) pitch 0 register ---------------------- - -Name: BPITCH0 -Offset: 0x00400650 -4 bytes, read-write - -B(?) pitch 1 register ---------------------- - -Name: BPITCH1 -Offset: 0x00400654 -4 bytes, read-write - -B(?) pitch 2 register ---------------------- - -Name: BPITCH2 -Offset: 0x00400658 -4 bytes, read-write - -B(?) pitch 3 register ---------------------- - -Name: BPITCH3 -Offset: 0x0040065C -4 bytes, read-write - -DMA register ------------- - -Name: DMA -Offset: 0x00400680 -4 bytes, read-write - -Notify register ---------------- - -Name: NOTIFY -Offset: 0x00400684 -4 bytes, read-write - -Bits 0-15: INST_MEM_LOC ??? - -Instance register ------------------ - -Name: INSTANCE -Offset: 0x00400688 -4 bytes, read-write - -Memory format register ----------------------- - -Name: MEMFMT -Offset: 0x0040068C -4 bytes, read-write - -Clip 0 min. register --------------------- - -Name: CLIP0_MIN -Offset: 0x00400690 -4 bytes, read-write - -Clip 0 max. register --------------------- - -Name: CLIP0_MAX -Offset: 0x00400694 -4 bytes, read-write - -Clip 1 min. register --------------------- - -Name: CLIP1_MIN -Offset: 0x00400698 -4 bytes, read-write - -Clip 1 max. register --------------------- - -Name: CLIP1_MAX -Offset: 0x0040069C -4 bytes, read-write - -Clip misc register ------------------- - -Name: CLIP_MISC -Offset: 0x004006A0 -4 bytes, read-write - -FIFO register -------------- - -Name: FIFO -Offset: 0x004006A4 -4 bytes, read-write - -Bit 0: ACCESS (IV, read-write) - DISABLED 0x0 (read-write) - ENABLED 0x1 (default, read-write) - -B(?) pixel register -------------------- - -Name: BPIXEL -Offset: 0x004006A8 -4 bytes, read-write - -Bits 0-1: DEPTH0_FMT (XV, read-write) - Y16_BITS 0x0 (read-write) - BITS_8 0x1 (read-write) - BITS_16 0x2 (read-write) - BITS_32 0x3 (read-write) - -Bit 2: DEPTH0 (XV, read-write) - NOT_VALID 0x0 (read-write) - VALID 0x1 (read-write) - -Bits 4-5: DEPTH1_FMT (XV, read-write) - Y16_BITS 0x0 (read-write) - BITS_8 0x1 (read-write) - BITS_16 0x2 (read-write) - BITS_32 0x3 (read-write) - -Bit 6: DEPTH1 (XV, read-write) - NOT_VALID 0x0 (read-write) - VALID 0x1 (read-write) - -Bits 8-9: DEPTH2_FMT (XV, read-write) - Y16_BITS 0x0 (read-write) - BITS_8 0x1 (read-write) - BITS_16 0x2 (read-write) - BITS_32 0x3 (read-write) - -Bit 10: DEPTH2 (XV, read-write) - NOT_VALID 0x0 (read-write) - VALID 0x1 (read-write) - -Bits 12-13: DEPTH3_FMT (XV, read-write) - Y16_BITS 0x0 (read-write) - BITS_8 0x1 (read-write) - BITS_16 0x2 (read-write) - BITS_32 0x3 (read-write) - -Bit 14: DEPTH3 (XV, read-write) - NOT_VALID 0x0 (read-write) - VALID 0x1 (read-write) - -Status register ---------------- - -Name: STATUS -Offset: 0x004006B0 -4 bytes, read-only - -DMA interrupt 0 register ------------------------- - -Name: DMA_INTR_0 -Offset: 0x00401100 -4 bytes, read-write - -Bit 0: INSTANCE (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 4: PRESENT (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 8: PROTECTION (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 12: LINEAR (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -Bit 16: NOTIFY (XV, read-write) - NOT_PENDING 0x0 (read-only) - PENDING 0x1 (read-only) - RESET 0x1 (write-only) - -DMA interrupt 0 enable register -------------------------------- - -Name: DMA_INTR_EN_0 -Offset: 0x00401140 -4 bytes, read-write - -DMA control register --------------------- - -Name: DMA_CONTROL -Offset: 0x00401210 -4 bytes, read-write - - - -RAMDAC -====== - -The RAMDAC registers begin at 0x00680000 in the CTRL region. - -Graphic cursor starting position register ------------------------------------------ - -Name: GRCURSOR_START_POS -Offset: 0x00680300 -4 bytes, read-write - -Bits 0-11: X (XS, read-write) - -Bits 16-27: Y (XS, read-write) - -MPLL coeff register -------------------- - -Name: MPLL_COEFF -Offset: 0x00680504 -4 bytes, read-write - -Bits 0-7: MDIV (IU, read-write) - -Bits 8-15: NDIV (IU, read-write) - -Bits 16-18: PDIV (IV, read-write) - -VPLL coeff register -------------------- - -Name: VPLL_COEFF -Offset: 0x00680508 -4 bytes, read-write - -Bits 0-7: MDIV (IU, read-write) - -Bits 8-15: NDIV (IU, read-write) - -Bits 16-18: PDIV (IV, read-write) - -PLL coeff select register -------------------------- - -Name: PLL_COEFF_SELECT -Offset: 0x0068050C -4 bytes, read-write - -Bit 4: DLL_BYPASS (IV, read-write) - FALSE 0x0 (default, read-write) - TRUE 0x1 (read-write) - -Bit 8: MPLL_SOURCE (IV, read-write) - DEFAULT 0x0 (default, read-write) - PROG 0x1 (read-write) - -Bit 12: MPLL_BYPASS (IV, read-write) - FALSE 0x0 (default, read-write) - TRUE 0x1 (read-write) - -Bit 16: VPLL_SOURCE (IV, read-write) - DEFAULT 0x0 (default, read-write) - PROG 0x1 (read-write) - -Bit 20: VPLL_BYPASS (IV, read-write) - FALSE 0x0 (default, read-write) - TRUE 0x1 (read-write) - -Bits 24-25: PCLK_SOURCE (IV, read-write) - VPLL 0x0 (default, read-write) - VIP 0x1 (read-write) - XTALOSC 0x2 (read-write) - -Bit 28: VCLK_RATIO (IV, read-write) - DB1 0x0 (default, read-write) - DB2 0x1 (read-write) - -General control register ------------------------- - -Various flags for DAC. BPC controls the width of the palette. - -Name: GENERAL_CONTROL -Offset: 0x00680600 -4 bytes, read-write - -Bits 0-1: FF_COEFF (IV, read-write) - DEF 0x0 (default, read-write) - -Bit 4: IDC_MODE (IV, read-write) - GAMMA 0x0 (default, read-write) - INDEX 0x1 (read-write) - -Bit 8: VGA_STATE (IV, read-write) - NOTSEL 0x0 (default, read-write) - SEL 0x1 (read-write) - -Bit 12: 565_MODE (IV, read-write) - NOTSEL 0x0 (default, read-write) - SEL 0x1 (read-write) - -Bit 16: BLK_PEDSTL (IV, read-write) - OFF 0x0 (default, read-write) - ON 0x1 (read-write) - -Bit 17: TERMINATION (IV, read-write) - 37OHM 0x0 (default, read-write) - 75OHM 0x1 (read-write) - -Bit 20: BPC (IV, read-write) - 6BITS 0x0 (default, read-write) - 8BITS 0x1 (read-write) - -Bit 24: DAC_SLEEP (IV, read-write) - DIS 0x0 (default, read-write) - EN 0x1 (read-write) - -Bit 28: PALETTE_CLK (IV, read-write) - EN 0x0 (default, read-write) - DIS 0x1 (read-write) - -VSERR width register --------------------- - -Name: VSERR_WIDTH -Offset: 0x00680700 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -VEQU end register ------------------ - -Name: VEQU_END -Offset: 0x00680704 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Vertical B(?) blank end register --------------------------------- - -Name: VBBLANK_END -Offset: 0x00680708 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Vertical blank end register ---------------------------- - -Name: VBLANK_END -Offset: 0x0068070C -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Vertical blank start register ------------------------------ - -Name: VBLANK_START -Offset: 0x00680710 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Vertical (B?) blank start register ----------------------------------- - -Name: VBBLANK_START -Offset: 0x00680714 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -VEQU start register -------------------- - -Name: VEQU_START -Offset: 0x00680718 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Vertical total register ------------------------ - -Name: VTOTAL -Offset: 0x0068071C -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Horizontal sync width register ------------------------------- - -Name: HSYNC_WIDTH -Offset: 0x00680720 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Horizontal burst start register -------------------------------- - -Name: HBURST_START -Offset: 0x00680724 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Horizontal burst end register ------------------------------ - -Name: HBURST_END -Offset: 0x00680728 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Horizontal blank start register -------------------------------- - -Name: HBLANK_START -Offset: 0x0068072C -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Horizontal blank end register ------------------------------ - -Name: HBLANK_END -Offset: 0x00680730 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -Horizontal total register -------------------------- - -Name: HTOTAL -Offset: 0x00680734 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -HEQU width register -------------------- - -Name: HEQU_WIDTH -Offset: 0x00680738 -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - -HSERR width register --------------------- - -Name: HSERR_WIDTH -Offset: 0x0068073C -4 bytes, read-write - -Bits 0-10: VAL (IV, read-write) - - - -'Standard' SVGA registers -========================= - -ATTR, CTRC, GRAPH, SEQ and MISC registers are available throught MMIO too. - -Name: ATTR_REG_INDEX -Offset: 0x006013c0 -1 byte, read-write - -Name: ATTR_REG_DATA -Offset: 0x006013c1 -1 byte, read-write - -Name: CRTC_REG_INDEX -Offset: 0x006013d4 -1 byte, read-write - -Name: CRTC_REG_DATA -Offset: 0x006013d5 -1 byte, read-write - -Name: GRA_REG_INDEX -Offset: 0x000C03ce -1 byte, read-write - -Name: GRA_REG_DATA -Offset: 0x000C03cf -1 byte, read-write - -Name: SEQ_REG_INDEX -Offset: 0x000C03c4 -1 byte, read-write - -Name: SEQ_REG_DATA -Offset: 0x000C03c5 -1 byte, read-write - -Name: MISC_REG -Offset: 0x000C03c2 -1 byte, read-write - - - -Extra CRTC registers -==================== - -Repaint 0 register ------------------- - -Extended offset and start address. - -Name: REPAINT0 -Index: 0x19 -1 byte - -Bits 0-4: START_ADDR_20_16 - -Bits 5-7: OFFSET_10_8 - -Repaint 1 register ------------------- - -Various flags. - -Name: REPAINT1 -Index: 0x1a -1 byte - -Bit 1: PALETTE_WIDTH - 8BITS 0x0 - 6BITS 0x1 - -Bit 2: LARGE_SCREEN - DISABLE 0x1 - ENABLE 0x0 ( >= 1280 ) - -Bit 4: COMPATIBLE_TEXT - ENABLE 0x1 - DISABLE 0x0 - -Bit 6: VSYNC - DISABLE 0x1 - ENABLE 0x0 - -Bit 7: HSYNC - DISABLE 0x1 - ENABLE 0x0 - -FIFO control register ---------------------- - -Controls how much data the refresh fifo requests. - -Name: FIFO_CONTROL -Index: 0x1b -1 byte - -Bits 0-2: BURST_LENGTH - BURST_LENGTH_8 0x0 - BURST_LENGTH_32 0x1 - BURST_LENGTH_64 0x2 - BURST_LENGTH_128 0x3 - BURST_LENGTH_256 0x4 - -Bit 7: UNDERFLOW_WARN - -FIFO register -------------- - -When the fifo occupancy falls below *twice* the watermark, -the refresh fifo will start to be refilled. If this value is -too low, you will get junk on the screen. Too high, and performance -will suffer. Watermark in units of 8 bytes. - -Name: FIFO -Index: 0x20 -1 byte - -Bits 0-5: WATERMARK - -Bit 7: RESET - -Extra register --------------- - -Assorted extra bits. - -Name: EXTRA -Index: 0x25 -1 byte - -Bit 0: VERT_TOTAL_10 - -Bit 1: VERT_DISPLAY_END_10 - -Bit 2: VERT_RETRACE_START_10 - -Bit 3: VERT_BLANK_START_10 - -Bit 4: HORIZ_BLANK_END_6 - -Bit 5: OFFSET_11 - -Pixel register --------------- - -Controls what the format of the framebuffer is. - -Name: PIXEL -Index: 0x28 -1 byte - -Bits 0-1: FORMAT - VGA 0x0 - 8BPP 0x1 - 16BPP 0x2 - 32BPP 0x3 - -Bits 3-5: TV_HORIZ_ADJUST - -Bit 6: TV_MODE - NTSC 0x0 - PAL 0x1 - -Bit 7: MODE - TV 0x1 - VGA 0x0 - -Horizontal extra register -------------------------- - -Horizonal extended bits. - -Name: HORIZ_EXTRA -Index: 0x2d -1 byte - -Bit 0: DISPLAY_TOTAL_8 - -Bit 1: DISPLAY_END_8 - -Bit 2: HORIZ_BLANK_START_8 - -Bit 3: HORIZ_RETRACE_START_8 - -Bit 4: INTER_HALF_START_8 - -Graphic cursor 0 register -------------------------- - -Name: GRCURSOR0 -Index: 0x30 -1 byte - -Bits 0-5: START_ADDR_21_16 - -Graphic cursor 1 register -------------------------- - -Name: GRCURSOR1 -Index: 0x31 -1 byte - -Bit 0: CURSOR - DISABLE 0x0 - ENABLE 0x1 - -Bit 1: SCAN_DBL - DISABLE 0x0 - ENABLE 0x1 - -Bits 3-7: START_ADDR_15_11 - -EOF diff --git a/doc/nvidia_notes/status.xlsx b/doc/nvidia_notes/status.xlsx deleted file mode 100644 index bfeeb14528f00e6aa6a6f1d9e1f055ab1399947f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 15945 zcmeHuV_+rgvUWJJIkAluO+1;2ZQHhO+qTUKCz#mQ#J26^%bt7A-TTbh=jV6-+}l68 z7rLI+tGk}6dJEEGpkSy#AAlf%fPe^r1kb&r9Dsp<*dTy_P=Fvo)cC9{?F}sLwd7r_ z4eT`NoGr`=a=}0-vVlO}&;P&efAJj{Nf@^50w4<9B|IX;G%Dz3BPgKx2;dK+mt2D` zJM+@uEL~zkd##1I6qm{(f|Qu+l4dsF>62*P1%;`S+npDe52~;pRfCD^6fnl6dxUFE zxg}~N3PM}JZJR?41o{n!y*eKNp&WinuA>6G`@xQmHUq+R^kYKO#Df;3?Gef;H#rpQ zT(iioAI1zMIXY0#5AIP)Iy41-@XGgdl`xmF{@_+=^~F$%wPYDD7}1U$u~&1xSx`8K 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nv3_pgraph_class02_rop = 0x02, - nv3_pgraph_class03_chroma_key = 0x03, - nv3_pgraph_class04_plane_mask = 0x04, - nv3_pgraph_class05_clipping_rectangle = 0x05, - nv3_pgraph_class06_pattern = 0x06, - nv3_pgraph_class07_rectangle = 0x07, - nv3_pgraph_class08_point = 0x08, - nv3_pgraph_class09_line = 0x09, - nv3_pgraph_class0a_lin = 0x0a, - nv3_pgraph_class0b_triangle = 0x0b, - nv3_pgraph_class0c_w95txt = 0x0c, - nv3_pgraph_class0d_m2mf = 0x0d, - nv3_pgraph_class0e_scaled_image_from_memory = 0x0e, - nv3_pgraph_class10_blit = 0x10, - nv3_pgraph_class11_image = 0x11, - nv3_pgraph_class12_bitmap = 0x12, - nv3_pgraph_class14_transfer2memory = 0x14, - nv3_pgraph_class15_stretched_image_from_cpu = 0x15, - nv3_pgraph_class17_d3d5tri_zeta_buffer = 0x17, - nv3_pgraph_class18_point_zeta_buffer = 0x18, - nv3_pgraph_class1c_image_in_memory = 0x1c, -} nv3_pgraph_class; - -/* - OBJECT METHODS -*/ - -// Global stuff -#define NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE 0x0 // I'm going insane at 00:48 14/02/2025 -#define NV3_SET_NOTIFY_CONTEXT_FOR_DMA 0x0100 // Set object ctx for dma...see nv3_dma_context_t structure -#define NV3_SET_NOTIFY 0x0104 - -// Crap e.g. "OS name", that sometimes gets submitted, for some reason. So we just suppress the warning messages for them -#define NV3_NVCLASS_CRAP_START 0x0310 -#define NV3_NVCLASS_CRAP_END 0x0324 - -// Render OPeration -#define NV3_ROP_SET_ROP 0x0300 // Set GDI standard rop - -// Beta Factor -#define NV3_BETA_FACTOR 0x0300 - -// Chroma Key -// Can't figure out what this is, used in 9x but certainly software, can't find anywhere... -#define NV3_CHROMA_UNKNOWN_0200 0x0200 -#define NV3_CHROMA_KEY 0x0304 - -// Clip -#define NV3_CLIP_POSITION 0x0300 // S16:S16, 0=topleft -#define NV3_CLIP_SIZE 0x0304 // U16:U16 - -// Blit Pattern -#define NV3_PATTERN_FORMAT 0x0304 -#define NV3_PATTERN_SHAPE 0x0308 -#define NV3_PATTERN_SHAPE_8X8 0 -#define NV3_PATTERN_SHAPE_64X1 1 -#define NV3_PATTERN_SHAPE_1X64 2 -#define NV3_PATTERN_SHAPE_LAST_VALID NV3_PATTERN_SHAPE_1X64 - -#define NV3_PATTERN_UNUSED_DRIVER_BUG 0x030C -#define NV3_PATTERN_COLOR0 0x0310 -#define NV3_PATTERN_COLOR1 0x0314 -#define NV3_PATTERN_BITMAP_HIGH 0x0318 -#define NV3_PATTERN_BITMAP_LOW 0x031C - -// Rect - -#define NV3_RECTANGLE_COLOR 0x0304 - -// 16 possible rectangles. 8 byte structure, first 4 bytes = position, second 2 = size. -#define NV3_RECTANGLE_START 0x0400 - -#define NV3_RECTANGLE_MAX 16 -#define NV3_RECTANGLE_END 0x0480 - -// M2MF -#define NV3_M2MF_IN_CTXDMA_OFFSET 0x030C -#define NV3_M2MF_OUT_CTXDMA_OFFSET 0x0310 -#define NV3_M2MF_IN_PITCH 0x0314 -#define NV3_M2MF_OUT_PITCH 0x0318 -#define NV3_M2MF_SCANLINE_LENGTH_IN_BYTES 0x031C -#define NV3_M2MF_NUM_SCANLINES 0x0320 -#define NV3_M2MF_FORMAT 0x0324 - -// M2MF formats (IN and OUT ORed together) -#define NV3_M2MF_FORMAT_INPUT 0 -#define NV3_M2MF_FORMAT_OUTPUT 8 - -#define NV3_M2MF_NOTIFY 0x0328 - -// blit -#define NV3_BLIT_POSITION_IN 0x0300 -#define NV3_BLIT_POSITION_OUT 0x0304 -#define NV3_BLIT_SIZE 0x0308 - -// image_from_cpu -#define NV3_IMAGE_START_POSITION 0x0304 // starting position of image from cpu -#define NV3_IMAGE_SIZE 0x0308 -#define NV3_IMAGE_SIZE_IN 0x030C -#define NV3_IMAGE_COLOR_START 0x0400 -#define NV3_IMAGE_COLOR_MAX 32 -#define NV3_IMAGE_COLOR_END 0x0480 - -#define NV3_IMAGE_IN_MEMORY_COLOR_FORMAT 0x0300 -#define NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE 0x0304 -#define NV3_IMAGE_IN_MEMORY_PITCH 0x0308 -#define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET 0x030C -#define NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END 22 - -/* GDI */ - -/* Type A: Unclipped Rectangle */ -#define NV3_W95TXT_A_COLOR 0x03FC // It's the colour of the text. This is used to submit a dummy object so the notifier can be used to sync in Win2000 DDraw6 drivers. -#define NV3_W95TXT_A_RECT_START 0x0400 -#define NV3_W95TXT_A_RECT_SIZE 64 // Number of rects -#define NV3_W95TXT_A_RECT_END 0x05FF - -/* Type B: Clipped Rectangle */ -#define NV3_W95TXT_B_CLIP_TOPLEFT 0x07F4 -#define NV3_W95TXT_B_CLIP_BOTTOMRIGHT 0x07F8 -#define NV3_W95TXT_B_COLOR 0x07FC -#define NV3_W95TXT_B_CLIP_CLIPRECT_START 0x0800 -#define NV3_W95TXT_B_CLIP_CLIPRECT_SIZE 128 // Number of rects -#define NV3_W95TXT_B_CLIP_CLIPRECT_END 0x09FF - -/* Type C: Unscaled Single-Colour Text (filled in from mono bitmap) */ -#define NV3_W95TXT_C_CLIP_TOPLEFT 0x0BEC -#define NV3_W95TXT_C_CLIP_BOTTOMRIGHT 0x0BF0 -#define NV3_W95TXT_C_CLIP_COLOR 0x0BF4 -#define NV3_W95TXT_C_CLIP_SIZE 0x0BF8 -#define NV3_W95TXT_C_CLIP_POSITION 0x0BFC /* TOP LEFT */ -#define NV3_W95TXT_C_CLIP_CLIPRECT_START 0x0C00 -#define NV3_W95TXT_C_CLIP_CLIPRECT_SIZE 64 // Number of rects -#define NV3_W95TXT_C_CLIP_CLIPRECT_END 0x0DFF - -/* Type D: Scaled Single-Colour Text (filled in from mono bitmap) */ -#define NV3_W95TXT_D_CLIP_TOPLEFT 0x0FE8 -#define NV3_W95TXT_D_CLIP_BOTTOMRIGHT 0x0FEC -#define NV3_W95TXT_D_CLIP_COLOR 0x0FF0 -#define NV3_W95TXT_D_CLIP_SIZE_IN 0x0FF4 -#define NV3_W95TXT_D_CLIP_SIZE_OUT 0x0FF8 -#define NV3_W95TXT_D_CLIP_POSITION 0x0FFC /* TOP LEFT */ -#define NV3_W95TXT_D_CLIP_CLIPRECT_START 0x1000 -#define NV3_W95TXT_D_CLIP_CLIPRECT_SIZE 128 // Number of rects -#define NV3_W95TXT_D_CLIP_CLIPRECT_END 0x11FF - -/* Type E: Scaled Pattern-type Bitmap Text (filled) */ -#define NV3_W95TXT_E_CLIP_TOPLEFT 0x13E4 -#define NV3_W95TXT_E_CLIP_BOTTOMRIGHT 0x13E8 -#define NV3_W95TXT_E_CLIP_COLOR_0 0x13EC -#define NV3_W95TXT_E_CLIP_COLOR_1 0x13F0 -#define NV3_W95TXT_E_CLIP_SIZE_IN 0x13F4 -#define NV3_W95TXT_E_CLIP_SIZE_OUT 0x13F8 -#define NV3_W95TXT_E_CLIP_POSITION 0x13FC /* TOP LEFT */ -#define NV3_W95TXT_E_CLIP_CLIPRECT_START 0x1400 -#define NV3_W95TXT_E_CLIP_CLIPRECT_SIZE 128 // Number of rects -#define NV3_W95TXT_E_CLIP_CLIPRECT_END 0x15FF - - -/* Class context switch method */ -typedef struct nv3_class_ctx_switch_method_s -{ - union - { - uint32_t data; - - uint16_t instance; - uint8_t channel : 6; - uint16_t reserved : 9; - bool reset_if_volatile; // ???? - } set_notify_ctx_dma; // Set notifier context for DMA (context switch) - -} nv3_class_ctx_switch_method_t; - -/* -enumerates color formats -there are some other colour formats that are only used in certain areas which are defined below -*/ -typedef enum nv3_pgraph_pixel_format_e -{ - nv3_pgraph_pixel_format_r5g5b5 = 0, - nv3_pgraph_pixel_format_r8g8b8 = 1, - nv3_pgraph_pixel_format_r10g10b10 = 2, - nv3_pgraph_pixel_format_y8 = 3, - nv3_pgraph_pixel_format_y16 = 4, - nv3_pgraph_pixel_format_v8y8u8y18 = 5, // "18"? NV wtf? - nv3_pgraph_pixel_format_y18v8y8u8 = 6, // "18"? NV wtf? - nv3_pgraph_pixel_format_y420 = 7, // YUV 420 -} nv3_pgraph_pixel_format; - -/* Main color format */ -typedef struct nv3_color_expanded_s -{ - uint8_t a; - - /* WARNING: The internal format is 10-bit RGB! */ - uint16_t r; - uint16_t g; - uint16_t b; - - // YUV stuff - float y; - float u; - float v; - - // Indexed colour - union - { - uint16_t i16; - - uint8_t i16_high; - uint8_t i8; - }; - - // the pixel format - nv3_pgraph_pixel_format pixel_format; -} nv3_color_expanded_t; - -/* A simple ARGB format colour */ -typedef struct nv3_color_argb_s -{ - uint8_t a; - uint8_t r; - uint8_t g; - uint8_t b; -} nv3_color_argb_t; - -/* Generic 16-bit coordinate*/ -typedef struct nv3_coord_16_s -{ - uint16_t x; - uint16_t y; -} nv3_coord_16_t; - -/* A big position format with 30:16 = y, 15:11 = nothing, 10:0 = x */ -typedef struct nv3_coord_16_bigy_s -{ - // WHOSE IDEA WAS THIS? - uint16_t x : 11; - uint8_t reserved : 5; - uint16_t y : 15; - bool reserved2 : 1; -} nv3_coord_16_bigy_t; - -/* Generic 32-bit colour + 16-bit position */ -typedef struct nv3_color_and_coord_16_s -{ - nv3_color_expanded_t color; - nv3_coord_16_t points; -} nv3_color_and_coord_16_t; - -/* "UTRI" type triangle */ -typedef struct nv3_utri_s -{ - uint32_t color; // use nv3_color_expanded_t but changed for alignment reasons - nv3_coord_16_t point0; - nv3_coord_16_t point1; - nv3_coord_16_t point2; -} nv3_utri_t; - -/* Generic 16-bit clip region */ -typedef struct nv3_clip_16_s -{ - // The bounds of the clipping area. - uint16_t left; - uint16_t top; - uint16_t right; - uint16_t bottom; -} nv3_clip_16_t; - -/* In case your positions weren't HIGH PRECISION enough */ -typedef struct nv3_coord_32_s -{ - uint32_t x; - uint32_t y; -} nv3_coord_32_t; - -// COLOUR FORMATS - -/* - Object Class 0x01 (real hardware, also 0x41) - 0x12 (drivers) - Beta factor -*/ -typedef struct nv3_object_class_001 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; - uint32_t set_beta_factor_1d31; // 31:31 (?) value, 30:21 fraction - // Put the rest of it here -} nv3_beta_factor_t; - -/* - Object class 0x02 (real hardware) - 0x14/0x43 (drivers) - Also 0x42 in context IDs - Render operation used for things like blending. Appears to be 8-bit i.e. a ROP3 with 256 possible operations. -*/ -typedef struct nv3_object_class_002 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint8_t rop; // ROP3 (ID = ????????) -} nv3_render_operation_t; - -/* - Object class 0x03 (real hardware) - 0x15 (drivers) - Also 0x43 in context IDs - A chroma/color key, like in video editing -*/ -typedef struct nv3_object_class_003 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t color; // ROP3 (ID = ????????) -} nv3_chroma_key_t; - -/* - Object class 0x04 (real hardware) - 0x15 (drivers) - Also 0x44 in context IDs - Plane mask -*/ -typedef struct nv3_object_class_004 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t color; // Plane mask -} nv3_plane_mask_t; - -/* - Object class 0x05 (real hardware) - 0x19/0x1E/0x47 (drivers) - Also 0x45 in context IDs - Clipping rectangle used for various blitting operations -*/ -typedef struct nv3_object_class_005 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - - /* 16-bit precision */ - nv3_coord_16_t position; - nv3_coord_16_t size; - -} nv3_clipping_rectangle_t; - -/* - Object Class 0x06 (real hardware) - 0x?? (drivers) - Also 0x46 in context IDs - A pattern used for blits. Wahey! -*/ -typedef struct nv3_object_class_006 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t shape; // 0 = 8x8, 1 = 64x1, 2 = 1x64 - uint32_t color0; // Some 32-bit format (argb?) - uint32_t color1; // bit0=color0, bit1=color1 - uint32_t pattern[2]; // bit0=color0, bit1=color1 -} nv3_pattern_t; - -/* - Object Class 0x07 (real hardware) - 0x1E (drivers) - Also 0x47 in context IDs - A rectangle. Wahey! -*/ -typedef struct nv3_object_class_007 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t color; // The colour of the object. - nv3_coord_16_t position[16]; // The positions of up to 16 rectangles. - nv3_coord_16_t size[16]; // The sizes of up to 16 rectangles -} nv3_rectangle_t; - - -/* In case your points weren't colourful enough */ -typedef struct nv3_object_class_008_cpoint_s -{ - nv3_color_expanded_t color; // argb-format 32-bit color - nv3_coord_16_t position; // position -} nv3_object_class_008_cpoint_t; - -/* - Object Class 0x08 (real hardware) - 0x1A (drivers) - Also 0x48 in context IDs - A point: the revolutionary 3d graphics technique... -*/ -typedef struct nv3_object_class_008 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - nv3_color_expanded_t color; // argb? - nv3_coord_16_t point[16]; // Boring points - nv3_coord_32_t point32[16]; // Allows you to have points with full 32-bit precision - nv3_object_class_008_cpoint_t cpoint[16]; // Allows you to have c o l o r f u l points! -} nv3_point_t; - -/* Normal line... */ -typedef struct nv3_object_class_009_line_s -{ - nv3_coord_16_t start; // presumably unless it's in reverse order...TODO: check the order - nv3_coord_16_t end; - -} nv3_object_class_009_line_t; - -/* THIRTY TWO BIT PRECISION line */ -typedef struct nv3_object_class_009_line32_s -{ - uint32_t x0; - uint32_t x1; - uint32_t y0; - uint32_t y1; -} nv3_object_class_009_line32_t; - -/* nv3_object_class_009_polyline_t not implemented because it's just a duplicate of nv3_object_class_009_line */ -/* nv3_object_class_009_polyline32_t not implemented because it's just a duplicate of nv3_object_class_009_line32 */ - - -/* - Object Class 0x09 (real hardware) - 0x1B (drivers) - Also 0x49 in context IDs - It's a line, but also a polygon... -*/ -typedef struct nv3_object_class_009 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - nv3_color_expanded_t color; // argb? - nv3_object_class_009_line_t line[16]; // List of line points (...) - nv3_object_class_009_line32_t line32[8]; - nv3_object_class_009_line_t polyline[32]; - nv3_object_class_009_line32_t polyline32[16]; - nv3_color_and_coord_16_t cpolyline[16]; // List of line points and colours. -} nv3_line_t; - -/* - Object Class 0x0A (real hardware) - 0x1c (drivers) - Also 0x4a in context IDs - - This one is where nvidia reinvents the line, but without the starting or ending pixel. - Seriously. -*/ -typedef struct nv3_object_class_00A -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - - uint32_t set_notify; // Set notifier - - nv3_color_expanded_t color; // argb? - nv3_object_class_009_line_t line[16]; // List of line points (...) - nv3_object_class_009_line32_t line32[8]; - nv3_object_class_009_line_t polyline[32]; - nv3_object_class_009_line32_t polyline32[16]; - nv3_color_and_coord_16_t cpolyline[16]; // List of line points and colours. - -} nv3_lin_t; - -/* - Object Class 0x0B (real hardware) - 0x?? (drivers) - Also 0x4b in context IDs. - - This is a triangle but seems to be obsolete. It's replaced with UD3D0Z / D3D5 Accelerated Triangle with Zeta Buffer. Does it even exist? -*/ -typedef struct nv3_object_class_00B -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - nv3_color_expanded_t color; // argb? - // The points of the triangle. - nv3_coord_16_t points[3]; - - // Another way of filling out the points of the triangle - uint32_t x0; - uint32_t y0; - uint32_t x1; - uint32_t y1; - uint32_t x2; - uint32_t y2; - - nv3_coord_16_t mesh[32]; // Some kind of mesh format. I guess a list of vertex positions? - nv3_coord_32_t mesh32[16]; // Mesh with 32-bit format - nv3_utri_t ctriangle[8]; // Triangles with colour - nv3_color_and_coord_16_t ctrimesh[16]; // Some kind of mesh format. I guess a list of vertex positions? with colours - -} nv3_triangle_t; - -/* - Object Class 0x0C (real hardware) - 0x0C (drivers) - Also 0x4C in context IDs. - - GDI text acceleration for Windows 95. -*/ -typedef struct nv3_object_class_00C -{ - /* Unclipped rect (basically class 0x07 )*/ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t color_a; // Color for Clip A - nv3_coord_16_t rect_a_position[64]; - nv3_coord_16_t rect_a_size[64]; - /* Clipped rect */ - nv3_clip_16_t clip_b; - uint32_t color_b; // Color for Clip B - nv3_clip_16_t clipped_rect[64]; - /* Unclipped transparent bitmap */ - nv3_clip_16_t clip_c; - uint32_t color1_c; - nv3_coord_16_t size_c; - nv3_coord_16_t point_c; - uint32_t bitmap_c[128]; - /* Clipped transparent bitmap */ - nv3_clip_16_t clip_d; - uint32_t color1_d; - nv3_coord_16_t size_in_d; - nv3_coord_16_t size_out_d; - nv3_coord_16_t point_d; - uint32_t bitmap_d[128]; - /* Clipped 1bpp bitmap */ - nv3_clip_16_t clip_e; - uint32_t color0_e; - uint32_t color1_e; - nv3_coord_16_t size_in_e; - nv3_coord_16_t size_out_e; - nv3_coord_16_t point_e; - uint32_t bitmap_e[128]; -} nv3_win95_text_t; - - -/* - Object Class 0x0D (real hardware) - 0x?? (drivers) - Also 0x4D in context IDs. - - Represents reformatting of an image in memory. -*/ -typedef struct nv3_object_class_00D -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t offset_in; - uint32_t offset_out; - uint32_t pitch_in; - uint32_t pitch_out; - uint32_t scanline_length; // Stride? - uint32_t num_scanlines; - uint8_t format; // input increment 1 2 or 4, output increment 1 2 or 4 (represented by << 8) - uint32_t buffer_notify; // Notify the Buffedr -} nv3_memory_to_memory_format_t; - -/* - Object Class 0x0E (real hardware) - 0x?? (drivers) - Also 0x4E in context IDs. - - Represents a scaled image coming from memory. -*/ -typedef struct nv3_object_class_00E -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_coord_16_t clip_0; - nv3_coord_16_t clip_1; - nv3_coord_16_t rectangle_out_0; - nv3_coord_16_t rectangle_out_1; - // Calculus in a graphics card - uint32_t delta_du_dx; - uint32_t delta_dv_dy; - nv3_coord_16_t size; // can be size_y if YUV420 - uint32_t pitch; - uint32_t offset; - uint32_t point; - // YUV420 stuff - uint32_t pitch_yuv420; - uint32_t offset_y; - uint32_t offset_u; - uint32_t offset_v; - uint32_t point_yuv420; -} nv3_scaled_image_from_memory_t; - -// (0x0F does not exist) - -/* - Object Class 0x10 (real hardware) - 0x?? (drivers) - Also 0x50 in context IDs. - - Represents a screen to screen blit. I'm still figuring it out. -*/ - -typedef struct nv3_object_class_010 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_coord_16_t point_in; - nv3_coord_16_t point_out; - nv3_coord_16_t size; -} nv3_blit_t; - -/* - Object Class 0x11 (real hardware) - 0x?? (drivers) - Also 0x51 in context IDs. - - Represents an image from the cpu (i guess from system memory) -*/ -typedef struct nv3_object_class_011 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_coord_16_t point; - nv3_coord_16_t size; - nv3_coord_16_t size_in; - nv3_color_expanded_t color[32]; // The colour to use -} nv3_image_t; - -/* - Object Class 0x12 (real hardware) - 0x?? (drivers) - Also 0x52 in context IDs. - - Bitmap from CPU. - It seems the difference is that an image is colour but a -*/ -typedef struct nv3_object_class_012 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_color_expanded_t color_0; - nv3_color_expanded_t color_1; - nv3_coord_16_t point; // Top left(?) of the bitmap - nv3_coord_16_t size; - nv3_coord_16_t size_in; - uint32_t monochrome_bitmap[32]; -} nv3_bitmap_t; - -// 0x13 doesn't exist - -/* - Object Class 0x14 (real hardware) - 0x?? (drivers) - Also 0x54 in context IDs. - - Image Transfer to Memory - It seems the difference is that an image is colour but a bitmap is b&w -*/ -typedef struct nv3_object_class_014 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_coord_16_t point; - nv3_coord_16_t size; - uint32_t image_pitch; // bytes per row - uint32_t image_start; -} nv3_image_to_memory_t; - -/* - Object Class 0x15 (real hardware) - 0x?? (drivers) - Also 0x55 in context IDs. - - Stretched Image from CPU - Seems to be, by the very large color array, the main class used in 2d acceleration. -*/ -typedef struct nv3_object_class_015 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_coord_16_t size_in; - uint32_t delta_dx_du; - uint32_t delta_dy_dv; - nv3_coord_16_t clip_0; - nv3_coord_16_t clip_1; - uint32_t point12d4; /* todo: fraction struct */ - // no reserve needed -} nv3_stretched_image_from_cpu_t; - -// 0x16 invalid - -/* - Object Class 0x17 (real hardware) - 0x?? (drivers) - Also 0x57 in context IDs. - - Direct3D 5.0 accelerated triangle with zeta buffer (combined z buffer and stencil buffer) - This is the final boss of this GPU. True horror stands below. -*/ - -// -// NV3 D3D5: TEXTURING & PIXEL FORMATS -// - -typedef enum nv3_d3d5_texture_pixel_format_e -{ - /* - 16-Bit Pixel Format - 5 bits red, 5 bits green, 5 bits alpha, "boolean" alpha - */ - nv3_d3d5_pixel_format_le_a1r5g5b5 = 0, - - /* - 15-Bit Pixel Format (represented as 16) - 1 bit irrelevant, 5 bits red, 5 bits green, 5 bits alpha - */ - nv3_d3d5_pixel_format_le_x1r5g5b5 = 1, - - /* - 16-Bit Pixel Format - 4 bits alpha, 4 bits red, 4 bits green, 4 bits blue - */ - nv3_d3d5_pixel_format_le_a4r4g4b4 = 2, - - /* - 16-Bit Pixel Format - 5 bits red, 6 bits green, 5 bits blue - (Required nv3tweak...) - */ - nv3_d3d5_pixel_format_le_r5g6b5 = 3, - -} nv3_d3d5_texture_pixel_format; - -/* Output format - - The output pixel format...I -*/ -typedef enum nv3_d3d5_output_pixel_format_e -{ - /* - 32-Bit Pixel Format - 8 bits irrelevant, 8 bits red, 8 bits green, 8 bits blue - */ - nv3_d3d5_output_pixel_format_le_x8r8g8b8 = 0, - - /* - 32-Bit Pixel Format - 8 bits irrelevant, 8 bits red, 8 bits green, 8 bits blue - Is this even used?? The riva can't even do 32 bit colour in 3d... - */ - nv3_d3d5_output_pixel_format_le_a8r8g8b8 = 1, - - -} nv3_d3d5_output_pixel_format; - - -/* Texture size - - NOTE: ONLY 256X256 OR LOWER ARE SUPPORTED! 2048X2048X16 TAKES UP ENTIRE VRAM OF RIVA 128 ZX... - I ASSUME THESE ARE INTERNALLY SCALED DOWN -*/ -typedef enum nv3_d3d5_texture_size_e -{ - nv3_d3d5_texture_size_1x1 = 0, - - nv3_d3d5_texture_size_2x2 = 1, - - nv3_d3d5_texture_size_4x4 = 2, - - nv3_d3d5_texture_size_8x8 = 3, - - nv3_d3d5_texture_size_16x16 = 4, - - nv3_d3d5_texture_size_32x32 = 5, - - nv3_d3d5_texture_size_64x64 = 6, - - nv3_d3d5_texture_size_128x128 = 7, - - nv3_d3d5_texture_size_256x256 = 8, - - nv3_d3d5_texture_size_512x512 = 9, - - nv3_d3d5_texture_size_1024x1024 = 10, - - // Kind of infeasible considering hardware VRAM size limitations - nv3_d3d5_texture_size_2048x2048 = 11, - - -} nv3_d3d5_texture_size; - -/* Texture Wrapping Mode for U/V Coordinate Overflow - -*/ -typedef enum nv3_d3d5_texture_wrap_mode_e -{ - // Map textures in a cylindrical fashion. - nv3_d3d5_texture_wrap_mode_cylindrical = 0, - - // Simply wrap back to the start. - nv3_d3d5_texture_wrap_mode_wrap = 1, - - // Mirror the texture. - nv3_d3d5_texture_wrap_mode_mirror = 2, - - // Clamp to the last border pixel. - nv3_d3d5_texture_wrap_mode_clamp = 3, -} nv3_d3d5_texture_wrap_mode; - - -/* This is blending but isn't really considered to be it in the GPU for some reason - What do we do with out input texel BEFORE processing it? - */ -typedef enum nv3_d3d5_dest_color_interpretation_e -{ - // Do nothing - nv3_d3d5_source_color_normal = 0, - - // Invert Colour - nv3_d3d5_source_color_inverse = 1, - - // Invert Alpha before Processing - nv3_d3d5_source_color_alpha_inverse = 2, - - // Take Alpha as 1 - nv3_d3d5_source_color_alpha_one = 3, - -} nv3_d3d5_dest_color_interpretation; - -// The full texture format structure -typedef struct nv3_d3d5_texture_format_s -{ - uint16_t color_key_color_mask; - bool color_key_enabled : 1; - nv3_d3d5_texture_pixel_format color_format : 2; - nv3_d3d5_texture_size size_min : 4; - nv3_d3d5_texture_size size_max : 4; -} nv3_d3d5_texture_format_t; - -// -// NV3 D3D5: INTERPOLATION -// - -/* - ?????? - Interpolating between mip levels? (or for texture blending) -*/ -typedef enum nv3_d3d5_interpolator_algorithm_e -{ - // Zero-order hold interpolation? - nv3_d3d5_interpolator_zoh = 0, - - // Zero-order hold (microsoft variant)? - nv3_d3d5_interpolator_zoh_ms = 1, - - // Full-order hold interpolation? - nv3_d3d5_interpolator_foh = 2, - -} nv3_d3d5_interpolator_algorithm; - -// -// NV3 D3D5: Z-BUFFER -// - -/* Probably the sorting algorithm */ -typedef enum nv3_d3d5_zbuffer_type_e -{ - // Sort based on linear distance - nv3_d3d5_zbuffer_linear = 0, - - // Sort based on distance from view frustum - nv3_d3d5_zbuffer_screen = 1, - -} nv3_d3d5_zbuffer_type; - -// NV3 D3D5: WRITE CONTROL (SHARED BETWEEN ZETA BUFFER AND ALPHA) -typedef enum nv3_d3d5_buffer_write_control_e -{ - // Never write. - nv3_d3d5_buffer_write_control_never = 0, - - // Only write the alpha. - nv3_d3d5_buffer_write_control_alpha = 1, - - // Write both alpha and the zeta-buffer. - nv3_d3d5_buffer_write_control_alpha_zeta = 2, - - // Write only the zeta-buffer - nv3_d3d5_buffer_write_control_zeta = 3, - - // Write everything (alpha+z+zeta?) - nv3_d3d5_buffer_write_control_always = 4, - - -} nv3_d3d5_buffer_write_control; - -// -// NV3 D3D5: BUFFER COMPARISON (SHARED BETWEEN ZETA BUFFER AND ALPHA CONTROL) -// - -// Todo: Which direction? (i.e. is less than p1 < p2 or p2 < p1!) -typedef enum nv3_d3d5_buffer_comparison_type_e -{ - // !!!ILLEGAL COMPARISON TYPE!!!! - nv3_d3d5_buffer_comparison_illegal = 0, - - // The (depth?) test always fails. - nv3_d3d5_buffer_comparison_always_false = 1, - - // True if less than fail. - nv3_d3d5_buffer_comparison_less_than = 2, - - // The test succeeds if equal. - nv3_d3d5_buffer_comparison_equal = 3, - - // The test succeeds if less or equal. - nv3_d3d5_buffer_comparison_less_or_equal = 4, - - // The test succeeds if greater. - nv3_d3d5_buffer_comparison_greater = 5, - - // The test succeeds if the two elements are equal. - nv3_d3d5_buffer_comparison_not_equal = 6, - - // The test succeeds if greater or equal - nv3_d3d5_buffer_comparison_greater_or_equal = 7, - - // The test always succeeds. - nv3_d3d5_buffer_comparison_always_true = 8, - -} nv3_d3d5_buffer_comparison_type; - -// -// NV3 D3D5: BLENDING -// - -/* Render Operation for Blending */ -typedef enum nv3_d3d5_blend_render_operation_e -{ - nv3_d3d5_blend_render_operation_and = 0, - - nv3_d3d5_blend_add_with_saturation = 1, - -} nv3_d3d5_blend_render_operation; - -typedef enum nv3_d3d5_blend_beta_factor_e -{ - nv3_d3d5_blend_beta_factor_srcalpha = 0, - - nv3_d3d5_blend_beta_factor_zero = 1, - -} nv3_d3d5_blend_beta_factor; - -typedef enum nv3_d3d5_blend_input0_e -{ - nv3_d3d5_blend_input0_srcalpha = 0, - - nv3_d3d5_blend_input0_zero = 1, - -} nv3_d3d5_blend_input0; - -typedef enum nv3_d3d5_blend_input1_e -{ - nv3_d3d5_blend_input1_destalpha = 0, - - nv3_d3d5_blend_input1_zero = 1, - -} nv3_d3d5_blend_input1; - -// -// NV3 D3D5: CULLING -// - -typedef enum nv3_d3d5_culling_algorithm_e -{ - // Don't cull - nv3_d3d5_culling_algorithm_none = 0, - - // Cull Clockwise around view frustum? - nv3_d3d5_culling_algorithm_clockwise = 1, - - // Cull counterclockwise around view frustum? - nv3_d3d5_culling_algorithm_counterclockwise = 2, - -} nv3_d3d5_culling_algorithm; - -/* Specular reflection parameters */ -typedef struct nv3_d3d5_specular_s -{ - uint8_t i0 : 4; - uint8_t i1 : 4; - uint8_t i2 : 4; - uint8_t i3 : 4; - uint8_t i4 : 4; - uint8_t i5 : 4; - uint8_t fog; //table fog emulation? -} nv3_d3d5_specular_t; - -// -// NV3 D3D5: MISC -// -typedef struct nv3_d3d5_texture_filter_s -{ - uint8_t spread_x; - uint8_t spread_y; - uint8_t mipmap; - uint8_t turbo; -} nv3_d3d5_texture_filter_t; - -// -// NV3 D3D5: OUTPUT CONTROL STRUCTURE -// - -/* Output Control for D3D5 Triangles */ -typedef struct nv3_d3d5_control_out_s -{ - nv3_d3d5_interpolator_algorithm ctrl_out_interpolator : 2; - uint8_t reserved : 2; - nv3_d3d5_texture_wrap_mode wrap_u : 2; // Controls wrapping mode of U texture coordinate - nv3_d3d5_texture_wrap_mode wrap_v : 2; // Controls wrapping move of V texture coordinate - nv3_d3d5_output_pixel_format output_pixel_format : 1; - bool reserved2 : 1; - nv3_d3d5_dest_color_interpretation dest_color_interpretation : 2; - nv3_d3d5_culling_algorithm culling_algorithm : 2; - bool reserved3 : 1; - nv3_d3d5_zbuffer_type zbuffer_type : 1; - nv3_d3d5_buffer_comparison_type zeta_buffer_compare : 4; - nv3_d3d5_buffer_write_control zeta_write : 3; - bool reserved4 : 1; - nv3_d3d5_buffer_write_control color_write : 3; - bool reserved5 : 1; - nv3_d3d5_blend_render_operation blend_rop : 1; - nv3_d3d5_blend_input0 blend_input0 : 1; - nv3_d3d5_blend_input1 blend_input1 : 1; -} nv3_d3d5_control_out_t; - -typedef struct nv3_d3d5_alpha_control_s -{ - uint8_t alpha_key; - nv3_d3d5_buffer_comparison_type zeta_buffer_compare : 4; - uint32_t reserved : 20; -} nv3_d3d5_alpha_control_t; - -// -// NV3 D3D5: Triangle Coordinates -// -typedef struct nv3_d3d5_coordinate_s -{ - nv3_d3d5_specular_t specular_reflection_parameters; - nv3_color_expanded_t color; // YOU HAVE TO FLIP THE ENDIANNESS. NVIDIA??? WHAT??? - - // Seems more plausible for these specifically to be floats. - // Also makes my life easier... - float x; // X coordinate in 3d space of the triangle - float y; // Y coordinate in 3d space of the triangle - float z; // Z coordinate in 3d space of the triangle - float m; // 1/W for projection - float u; // U coordinate within texture for the (top left?) of the triangle where sampling starts. - float v; // V coordinate within texture for the (top left?) of the triangle where sampling starts. -} nv3_d3d5_coordinate_t; - -typedef struct nv3_object_class_017 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - uint32_t texture_offset; - nv3_d3d5_texture_format_t texture_format; - nv3_d3d5_texture_filter_t texture_filter; - nv3_color_expanded_t fog_color; // Alpha is ignored here! - nv3_d3d5_control_out_t control_out; - nv3_d3d5_alpha_control_t alpha_control; - - nv3_d3d5_coordinate_t coordinate_points[128]; // The points we are rendering. - /* No placeholder needed, it really is that long. */ -} nv3_d3d5_accelerated_triangle_with_zeta_buffer_t; - - -// Color and Zeta Buffer algorithm -typedef struct nv3_zeta_buffer_s -{ - nv3_color_expanded_t color; - uint32_t zeta; // 16 bits z, 8 bits stenciul -} nv3_zeta_buffer_t; - -typedef struct nv3_object_class_018 -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; - uint32_t set_notify; - nv3_d3d5_control_out_t control_out; - nv3_d3d5_alpha_control_t alpha_control; - nv3_coord_16_t point; - nv3_zeta_buffer_t zeta[8]; -} nv3_point_with_zeta_buffer_t; - -/* 0x19, 0x1A, 0x1B don't exist */ - -/* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU? - They are making it look like a bitfield but it's hex? - - THEY ARE ALL LITTLE ENDIAN -*/ -typedef enum nv3_object_class_01C_pixel_format_e -{ - // Y8P4 - // 12-bits (Y8 - Planar YUV 8 bits (Y value only), 4 bits of indexed colour too? - nv3_image_in_memory_pixel_format_le_y8_p4 = 0x1010000, - - // Y16P2 - // 16-bits (Y16) - Planar YUV 16 bits (Y value only), 2 bits of indexed colour too? - nv3_image_in_memory_pixel_format_le_y16_p2 = 0x1010101, - - /* 1 unused bit, 555 15-bit format, p2(?) */ - nv3_image_in_memory_pixel_format_x1r5g5b5_p2 = 0x1000000, - - // X8G8B8R8, 24-bit colour (or 24-bit colour with alpha) - nv3_image_in_memory_pixel_format_x8g8b8r8 = 0x1, -} nv3_object_class_01C_pixel_format; - -typedef struct nv3_object_class_01C -{ - nv3_class_ctx_switch_method_t set_notify_ctx_dma; // Set notifier context for DMA (context switch) - uint32_t set_notify; // Set notifier - nv3_object_class_01C_pixel_format format; // Completely different from everything else - uint32_t pitch; // 16-bit - uint32_t linear_address; // 22-bit: Linear address in vram. -} nv3_image_in_memory_t; - -// See envytools. This is where we finally end up after this mess, it allows parameters to be passed to the methods. -typedef struct nv3_grobj_s -{ - uint32_t grobj_0; - uint32_t grobj_1; - uint32_t grobj_2; - uint32_t grobj_3; -} nv3_grobj_t; -// TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!! - -// PIO Subchannel info -#define NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE 0x0010 -#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START 0x0012 -#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017 \ No newline at end of file diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h deleted file mode 100644 index cca3761be..000000000 --- a/src/include/86box/nv/render/vid_nv3_render.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 headers for rendering - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#pragma once - -/* Core */ -void nv3_render_current_bpp(); -void nv3_render_current_bpp_dfb_8(uint32_t address); -void nv3_render_current_bpp_dfb_16(uint32_t address); -void nv3_render_current_bpp_dfb_32(uint32_t address); - -/* Pixel */ -void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj); -uint8_t nv3_render_read_pixel_8(nv3_coord_16_t position, nv3_grobj_t grobj); -uint16_t nv3_render_read_pixel_16(nv3_coord_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj); - -/* Address */ -uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj); -uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, uint32_t buffer); - -/* Colour Conversion */ -uint32_t nv3_render_get_palette_index(uint8_t index); // Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) -uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded); // Convert a colour to A1R10G10B10 for chroma key purposes. -nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj); // Convert a colour to full RGB10 format from the current working format. -uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color); // Convert a colour from the current working format to RGB10 format. - -/* ROP */ -uint8_t nv3_render_translate_nvrop(nv3_grobj_t grobj, uint32_t rop); - -/* Pattern */ -void nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1); - -/* Primitives */ -void nv3_render_rect(nv3_coord_16_t position, nv3_coord_16_t size, uint32_t color, nv3_grobj_t grobj); // Render an A (unclipped) GDI rect -void nv3_render_rect_clipped(nv3_clip_16_t clip, uint32_t color, nv3_grobj_t grobj); // Render a B (clipped) GDI rect. - -/* Chroma */ -bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj); - -/* Blit */ -void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj); -void nv3_render_blit_screen2screen(nv3_grobj_t grobj); - -/* GDI */ -void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitmap_data, nv3_grobj_t grobj); -void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj); /* GDI Type-E: Clipped 1bpp colour-expanded bitmap */ - -/* DMA */ -void nv3_perform_dma_m2mf(nv3_grobj_t grobj); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv.h b/src/include/86box/nv/vid_nv.h deleted file mode 100644 index 83f94c167..000000000 --- a/src/include/86box/nv/vid_nv.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * The real Nvidia driver. - * Implements components shared by all variants of the Nvidia GPUs (hopefully to be) supported by 86Box. - * - * This driver draws on collaborative work by many people over many years. - * - * Credit to: - * - * - Marcelina Kościelnicka (envytools) https://envytools.readthedocs.io/en/latest/ - * - fuel (PCBox developer) https://github.com/PCBox/PCBox - * - nouveau developers https://nouveau.freedesktop.org/ - * - Utah GLX developers https://utah-glx.sourceforge.net/ - * - XFree86 developers https://www.xfree86.org/ - * - xemu developers https://github.com/xemu-project/xemu - * - RivaTV developers https://rivatv.sourceforge.net (esp. https://rivatv.sourceforge.net/stuff/riva128.txt) - * - Nvidia for leaking their driver symbols numerous times ;^) https://nvidia.com - * - Vort (Bochs GeForce fork) https://github.com/Vort/Bochs/tree/geforce - * - People who prevented me from giving up (various) - * - * Authors: Connor Hyde / starfrost - * - * Copyright 2024-2025 Connor Hyde - */ -#ifdef EMU_DEVICE_H // what - -//TODO: split this all into nv1, nv3, nv4... -#include <86box/log.h> -#include <86box/i2c.h> -#include <86box/vid_ddc.h> -#include <86box/timer.h> -#include <86box/vid_svga.h> -#include <86box/vid_svga_render.h> -#include <86box/nv/vid_nv_rivatimer.h> - -void nv_log_set_device(void* device); -void nv_log(const char *fmt, ...); - -// Verbose logging level. -void nv_log_verbose_only(const char *fmt, ...); - -// Defines common to all NV chip architectural generations - -// PCI IDs -#define PCI_VENDOR_NV 0x10DE // NVidia PCI ID -#define PCI_VENDOR_SGS 0x104A // SGS-Thompson -#define PCI_VENDOR_SGS_NV 0x12D2 // SGS-Thompson/NVidia joint venture - -#define NV_PCI_NUM_CFG_REGS 256 // number of pci config registers - -// 0x0000 was probably the NV0 'Nvidia Hardware Simulator' -#define NV_PCI_DEVICE_NV1 0x0008 // Nvidia NV1 -#define NV_PCI_DEVICE_NV1_VGA 0x0009 // Nvidia NV1 VGA core -#define NV_PCI_DEVICE_NV2 0x0010 // Nvidia NV2 / Mutara V08 (cancelled) -#define NV_PCI_DEVICE_NV3 0x0018 // Nvidia NV3 (Riva 128) -#define NV_PCI_DEVICE_NV3T 0x0019 // Nvidia NV3T (Riva 128 ZX) -#define NV_PCI_DEVICE_NV4 0x0020 // Nvidia NV4 (RIVA TNT) - -#define NV_CHIP_REVISION_NV1_A0 0x0000 // 1994 -#define NV_CHIP_REVISION_NV1_B0 0x0010 // 1995 -#define NV_CHIP_REVISION_NV1_C0 0x0020 // 1995-96? - -#define NV_CHIP_REVISION_NV3_A0 0x0000 // January 1997 -#define NV_CHIP_REVISION_NV3_B0 0x0010 // October 1997 -#define NV_CHIP_REVISION_NV3_C0 0x0020 // 1998 - -// Architecture IDs -#define NV_ARCHITECTURE_NV1 1 // NV1/STG2000 -#define NV_ARCHITECTURE_NV2 2 // Nvidia 'Mutara V08' -#define NV_ARCHITECTURE_NV3 3 // Riva 128 -#define NV_ARCHITECTURE_NV4 4 // Riva TNT and later - -#define NV_MAX_BUF_SIZE_X 1920 // Maximum buffer size, X -#define NV_MAX_BUF_SIZE_Y 1200 // Maximum buffer size, Y - -typedef enum nv_bus_generation_e -{ - // NV1 - Prototype version - nv_bus_vlb = 0, - - // NV1 - // NV3 - nv_bus_pci = 1, - - // NV3 - nv_bus_agp_1x = 2, - - // NV3T - // NV4 - nv_bus_agp_2x = 3, - -} nv_bus_generation; - -// PCI configuration -typedef struct nv_pci_config_s -{ - uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability) - bool vbios_enabled; // is the vbios enabled? - uint8_t int_line; -} nv_pci_config_t; - -// NV Base -typedef struct nv_base_s -{ - rom_t vbios; // NVIDIA/OEm VBIOS - nv_pci_config_t pci_config; // PCI configuration - // move to nv3_cio_t? - svga_t svga; // SVGA core (separate to nv3) - Weitek licensed - uint32_t vram_amount; // The amount of VRAM - void* log; // new logging engine - // stuff that doesn't fit in the svga structure - uint32_t cio_read_bank; // SVGA read bank - uint32_t cio_write_bank; // SVGA write bank - - mem_mapping_t framebuffer_mapping; // Linear Framebuffer / NV_USER memory mapping - mem_mapping_t mmio_mapping; // mmio mapping (32MB unified MMIO) - mem_mapping_t framebuffer_mapping_mirror; // Mirror of LFB mapping - mem_mapping_t ramin_mapping; // RAM INput area mapping - mem_mapping_t ramin_mapping_mirror; // RAM INput area mapping (mirrored) - NV3 ONLY - uint8_t pci_slot; // pci slot number - uint8_t pci_irq_state; // current PCI irq state - uint32_t bar0_mmio_base; // PCI Base Address Register 0 - MMIO Base - uint32_t bar1_lfb_base; // PCI Base Address Register 1 - Linear Framebuffer (NV_BASE) - nv_bus_generation bus_generation; // current bus (see nv_bus_generation documentation) - uint32_t gpu_revision; // GPU Stepping - double pixel_clock_frequency; // Frequency used for pixel clock# - double refresh_time; // Rough estimation of refresh rate, for when we can present the screen - double refresh_clock; // Time since the last refresh - rivatimer_t* pixel_clock_timer; // Timer for measuring pixel clock - bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times - double memory_clock_frequency; // Source Frequency for PTIMER - rivatimer_t* memory_clock_timer; // Timer for measuring memory/gpu clock - - // VCLK / NVCLK do not have timers set here. - pc_timer_t* nv4_vclk_timer; // NV4+ MCLK (Video RAM) timer - - bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times - void* i2c; // I2C for monitor EDID - void* ddc; // Display Data Channel for EDID - bool agp_enabled; // AGP Enabled (for debugging) - bool agp_sba_enabled; // AGP Sideband Addressing enabled - - // - // DEBUG UI STUFF - // - bool debug_dba_enabled; // Debug DBA override - uint32_t debug_dba; // Debug DBA -} nv_base_t; - -#define NV_REG_LIST_END 0xD15EA5E - -// The NV architectures are very complex. -// There are hundreds of registers at minimum, and implementing these in a standard way would lead to -// unbelievably large switch statements and horrifically unreadable code. -// So this is used to abstract it and allow for more readable code. -// This is mostly just used for logging and stuff. -// Optionally, you can provide a function that is run when you read to and write from the register. -// You can also implement this functionality in a traditional way such as a switch statement, for simpler registers. To do this, simply set both read and write functions to NULL. -// Typically, unless they are for a special purpose (and handled specially) e.g. vga all register reads and writes are also 32-bit aligned -typedef struct nv_register_s -{ - int32_t address; // MMIO Address - char* friendly_name; // Friendly name - // reg_ptr not needed as a parameter, because we implicitly know which register si being tiwddled - uint32_t (*on_read)(void); // Optional on-read function - void (*on_write)(uint32_t value); // Optional on-write fucntion -} nv_register_t; - -nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs); - - -#endif \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv1.h b/src/include/86box/nv/vid_nv1.h deleted file mode 100644 index be6895c8b..000000000 --- a/src/include/86box/nv/vid_nv1.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Quadratic Heaven - * - * Authors: Connor Hyde - * - * Copyright 2024-2025 Connor Hyde - */ - -#pragma once - -#include -#include - -extern const device_config_t nv1_config[]; // Config for RIVA 128 (revision A/B) - -// -// PCI Bus Information -// - -#define NV1_PCI_BAR0_SIZE 0xFFFFFF - -// -// VRAM -// -#define NV1_VRAM_SIZE_1MB 0x100000 -#define NV1_VRAM_SIZE_2MB 0x200000 -#define NV1_VRAM_SIZE_4MB 0x400000 - -// Video BIOS -#define NV1_VBIOS_E3D_2X00 "roms/video/nvidia/nv1/Diamond_Edge_3D_2x00.BIN" -#define NV1_VBIOS_E3D_3X00 "roms/video/nvidia/nv1/Diamond_Edge_3D_3400_BIOS_M27C256.BIN" - -// -// PMC -// -#define NV1_PMC_BOOT_0 0x0 -#define NV1_PMC_BOOT_0_REVISION 0 - -#define NV1_PMC_BOOT_0_REVISION_A 0x0 // Prototype (1994) -#define NV1_PMC_BOOT_0_REVISION_B1 0x0 // Prototype (early 1995) -#define NV1_PMC_BOOT_0_REVISION_B2 0x0 // Prototype (mid 1995) -#define NV1_PMC_BOOT_0_REVISION_B3 0x0 // Final? -#define NV1_PMC_BOOT_0_REVISION_C 0x0 // Final? - -#define NV1_PMC_BOOT_0_IMPLEMENTATION 8 -#define NV1_PMC_BOOT_0_IMPLEMENTATION_NV0 0x1 // Nvidia Hardware Simulator (1993-1994) -#define NV1_PMC_BOOT_0_IMPLEMENTATION_NV1_D32 0x2 // NV1 + DRAM + SGS-Thomson STG-1732/1764 DAC -#define NV1_PMC_BOOT_0_IMPLEMENTATION_NV1_V32 0x3 // NV1 + VRAM + SGS-Thomson STG-1732/1764 DAC -#define NV1_PMC_BOOT_0_IMPLEMENTATION_PICASSO 0x4 // NV1 + VRAM + NV 128-bit DAC - - -// Defines the NV architecture version (NV1/NV2/...) -#define NV1_PMC_BOOT_0_ARCHITECTURE 16 -#define NV1_PMC_BOOT_0_ARCHITECTURE_NV0 0x0 // Nvidia Hardware Simulator (1993-1994) -#define NV1_PMC_BOOT_0_ARCHITECTURE_NV1 0x1 // NV1 (1995) -#define NV1_PMC_BOOT_0_ARCHITECTURE_NV2 0x2 // Mutara (1996, cancelled) - -#define NV1_PMC_DEBUG_0 0x80 - -#define NV1_PMC_INTR_0 0x100 -#define NV1_PMC_INTR_EN_0 0x140 - -#define NV1_PMC_INTR_EN_0_INTA 0 -#define NV1_PMC_INTR_EN_0_INTB 4 -#define NV1_PMC_INTR_EN_0_INTC 8 -#define NV1_PMC_INTR_EN_0_INTD 12 - -#define NV1_PMC_INTR_EN_0_DISABLED 0x0 -#define NV1_PMC_INTR_EN_0_HARDWARE 0x1 -#define NV1_PMC_INTR_EN_0_SOFTWARE 0x2 -#define NV1_PMC_INTR_EN_0_ALL 0x3 // (HARDWARE | SOFTWARE) - -#define NV1_PMC_INTR_READ 0x160 - -//TODO: DEFINE bits -#define NV1_PMC_ENABLE 0x200 - -// -// PRAMIN -// - -#define NV1_RAMIN_START 0x100000 - -// -// PAUTH -// Scary nvidia mode -// - -// Read only -#define NV1_PAUTH_DEBUG_0 0x605080 -#define NV1_PAUTH_DEBUG_0_BREACH_DETECTED 0 -#define NV1_PAUTH_DEBUG_0_EEPROM_INVALID 4 - -#define NV1_PAUTH_CHIP_TOKEN_0 0x605400 -#define NV1_PAUTH_CHIP_TOKEN_1 0x605404 -#define NV1_PAUTH_PASSWORD_0(i) 0x605800+(i*16) -#define NV1_PAUTH_PASSWORD_1(i) 0x605804+(i*16) -#define NV1_PAUTH_PASSWORD_2(i) 0x605808+(i*16) -#define NV1_PAUTH_PASSWORD_3(i) 0x60580C+(i*16) - -#define NV1_PAUTH_PASSWORD_SIZE 128 - -// -// PFB -// - -#define NV1_PFB_BOOT_0 0x600000 - -#define NV1_PFB_BOOT_0_RAM_AMOUNT 0 -#define NV1_PFB_BOOT_0_RAM_AMOUNT_1MB 0x0 -#define NV1_PFB_BOOT_0_RAM_AMOUNT_2MB 0x1 -#define NV1_PFB_BOOT_0_RAM_AMOUNT_4MB 0x2 - -// -// PEXTDEV -// - -#define NV1_STRAPS 0x608000 -#define NV1_STRAPS_STRAP_VENDOR 0 - -// -// PRAM+RAMIN -// - -#define NV1_PRAM_CONFIG 0x602200 -#define NV1_PRAM_CONFIG_SIZE 0 -#define NV1_PRAM_CONFIG_12KB 0 -#define NV1_PRAM_CONFIG_20KB 1 -#define NV1_PRAM_CONFIG_36KB 2 -#define NV1_PRAM_CONFIG_68KB 3 - -// Position of RAMPW in RAMIN -#define NV1_RAMPW_POSITION_CONFIG0 0x2c00 -#define NV1_RAMPW_POSITION_CONFIG1 0x4c00 -#define NV1_RAMPW_POSITION_CONFIG2 0x8c00 -#define NV1_RAMPW_POSITION_CONFIG3 0x10c00 - -// Static RAMPW mirror -#define NV1_PRAMPW 0x606000 -#define NV1_RAMPW_SIZE 0x400 - -// -// PROM -// -#define NV1_PROM 0x601000 -#define NV1_PROM_SIZE 32768 - -// Structures -typedef struct nv1_s -{ - nv_base_t nvbase; // Base Nvidia structure -} nv1_t; - -// Device Core -void nv1_init(); -void nv1_close(void* priv); -void nv1_speed_changed(void *priv); -void nv1_draw_cursor(svga_t* svga, int32_t drawline); -void nv1_recalc_timings(svga_t* svga); -void nv1_force_redraw(void* priv); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h deleted file mode 100644 index 3726ecc03..000000000 --- a/src/include/86box/nv/vid_nv3.h +++ /dev/null @@ -1,1764 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Welcome to what happens when a single person demands that their overly complicated "vision" of a design be implemented - * with absolutely no compromise. This is true lunacy. - * - * Explanation of what is being done here, and how this all works, hopefully posted on the 86Box blog. - * Notes specific to a subsystem in the header or c file for that subsystem - * Also check the doc folder for some more notres - * - * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 12 April 2025 (STILL WORKING ON IT!!!) - * - * Authors: Connor Hyde - * - * Copyright 2024-2025 Connor Hyde - */ - -#pragma once -#include <86box/nv/classes/vid_nv3_classes.h> -#include <86box/nv/render/vid_nv3_render.h> - -// The GPU base structure -extern const device_config_t nv3_config[]; // Config for RIVA 128 (revision A/B) -extern const device_config_t nv3t_config[]; // Config for RIVA 128 ZX (revision C) - -#define NV3_MMIO_SIZE 0x1000000 // Max MMIO size - -#define NV3_LFB_RAMIN_MIRROR_START 0x400000 // Mirror of ramin (VERIFY ON HARDWARE) -#define NV3_LFB_MIRROR_START 0x800000 // The second half of LFB(?) -#define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start -#define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN - -// THere are 64 DMA channels grouped into 8 "channels" with 8 "subchannels" each. You can only use one channel at a time. An arbitrary number of 8 objects can be submitted. -// Channel 0 is always taken up by NV drivers. - -#define NV3_DMA_CHANNELS 8 -#define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8 - -#define NV3_DMA_CHANNELS_TOTAL 0x7F // This is also used somewhere despite there only being 8*8 = 64 channels - -#define NV3_LAST_VALID_GRAPHICS_OBJECT_ID 0x1F - -// The class ids are represented with 5 bits in PGRAPH, but 7 bits in PFIFO! -// What... -#define NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID 0x40 -#define NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID 0x5F - -// Default value for the boot information register. -// Depends on the chip -#define NV3_BOOT_REG_REV_A00 0x00030100 // todo: format is wrong(?) for nv3a, fix it later -#define NV3_BOOT_REG_REV_B00 0x00030110 -#define NV3_BOOT_REG_REV_C00 0x00030120 - -// various vbioses for testing -// Coming soon: MIROmagic Premium BIOS (when I get mine dumped) -//todo: move to hash system - -// Oldest one of these - August 8, 1997 - -// This particular VBIOS is very early and has certain bugs -#define NV3_VBIOS_STB_V128_V160 "roms/video/nvidia/nv3/stb-velocity128-1.6.bin" // STB Velocity 128 3D (Riva 128) Ver.1.60 -#define NV3_VBIOS_ERAZOR_V14700 "roms/video/nvidia/nv3/OLD_0000.BIN" // ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00) -#define NV3_VBIOS_ERAZOR_V15403 "roms/video/nvidia/nv3/VCERAZOR.BIN" // ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS] -#define NV3_VBIOS_ERAZOR_V15500 "roms/video/nvidia/nv3/Ver15500.rv_" // ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS] -#define NV3_VBIOS_DIAMOND_V330_V162 "roms/video/nvidia/nv3/diamond_v330_rev-e.vbi" // Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO -#define NV3_VBIOS_ASUS_V3000_V151 "roms/video/nvidia/nv3/riva128_asus.vbi" // ASUS AGP/3DP-V3000 BIOS 1.51B -#define NV3_VBIOS_STB_V128_V182 "roms/video/nvidia/nv3/riva128_stb.vbi" // STB Velocity 128 (RIVA 128) Ver.1.82 -#define NV3T_VBIOS_DIAMOND_V330_V182B "roms/video/nvidia/nv3/nv3t182b.rom" // Diamond Multimedia Viper V330 8M BIOS - Version 1.82B -#define NV3T_VBIOS_ASUS_V170 "roms/video/nvidia/nv3/A170D03T.rom" // ASUS AGP-V3000 ZXTV BIOS - V1.70D.03 (C) 1996-98 Nvidia Corporation -#define NV3T_VBIOS_REFERENCE_CEK_V171 "roms/video/nvidia/nv3/BIOS_49_Riva 128" // Reference BIOS: RIVA 128 ZX BIOS - V1.71B-N (C) 1996-98 NVidia Corporation -#define NV3T_VBIOS_REFERENCE_CEK_V172 "roms/video/nvidia/nv3/vgasgram.rom" // Reference(?) BIOS: RIVA 128 ZX BIOS - V1.72B (C) 1996-98 NVidia Corporation - -// The default VBIOS to use -#define NV3_VBIOS_DEFAULT NV3_VBIOS_ERAZOR_V15403 - -// Temporary, will be loaded from settings -#define NV3_VRAM_SIZE_2MB 0x200000 // 2MB -#define NV3_VRAM_SIZE_4MB 0x400000 // 4MB -#define NV3_VRAM_SIZE_8MB 0x800000 // NV3T only -// There is also 1mb supported by the card but it was never used - -// PCI config -#define NV3_PCI_CFG_VENDOR_ID 0x0 -#define NV3_PCI_CFG_DEVICE_ID 0x2 -#define NV3_PCI_CFG_CAPABILITIES 0x4 - -#define NV3_PCI_COMMAND_L_IO 1 -#define NV3_PCI_COMMAND_L_IO_ENABLED 0x1 -#define NV3_PCI_COMMAND_L_MEMORY 2 -#define NV3_PCI_COMMAND_L_MEMORY_ENABLED 0x1 - -#define NV3_PCI_COMMAND_H_FAST_BACK2BACK 0x01 - -#define NV3_PCI_STATUS_L_66MHZ_CAPABLE 0x20 -#define NV3_PCI_STATUS_H_DEVSEL_TIMING 5 -#define NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING 0x00 - -#define NV3_PCI_CFG_REVISION 0x8 - -#define NV3_PCI_CFG_REVISION_A00 0x00 // nv3a January 1997 - engineering sample, had NV1 PAUDIO and other minor incompatibilities -#define NV3_PCI_CFG_REVISION_B00 0x10 // nv3b September 1997 -#define NV3_PCI_CFG_REVISION_C00 0x20 // todo: verify this - nv3c (nv3t?) / RIVA 128 ZX - -#define NV3_PCI_CFG_PROGRAMMING_INTERFACE 0x9 -#define NV3_PCI_CFG_SUBCLASS_CODE 0x0A -#define NV3_PCI_CFG_CLASS_CODE 0x0B -#define NV3_PCI_CFG_CLASS_CODE_VGA 0x03 - -#define NV3_PCI_CFG_CACHE_LINE_SIZE 0x0C -#define NV3_PCI_CFG_CACHE_LINE_SIZE_DEFAULT_FROM_VBIOS 0x40 - -#define NV3_PCI_CFG_LATENCY_TIMER 0x0D -#define NV3_PCI_CFG_HEADER_TYPE 0x0E -#define NV3_PCI_CFG_BIST 0x0F - -// PCI Bars -#define NV3_PCI_CFG_BAR_PREFETCHABLE 3 -#define NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED 0x1 - -#define NV3_PCI_CFG_BAR0_L 0x10 -#define NV3_PCI_CFG_BAR0_BYTE1 0x11 -#define NV3_PCI_CFG_BAR0_BYTE2 0x12 -#define NV3_PCI_CFG_BAR0_BASE_ADDRESS 0x13 -#define NV3_PCI_CFG_BAR1_L 0x14 -#define NV3_PCI_CFG_BAR1_BYTE1 0x15 -#define NV3_PCI_CFG_BAR1_BYTE2 0x16 -#define NV3_PCI_CFG_BAR1_BASE_ADDRESS 0x17 -#define NV3_PCI_CFG_BAR_INVALID_START 0x18 -#define NV3_PCI_CFG_BAR_INVALID_END 0x27 -#define NV3_PCI_CFG_SUBSYSTEM_ID 0x2C - -#define NV3_PCI_CFG_ENABLE_VBIOS 0x30 -#define NV3_PCI_CFG_VBIOS_BASE 0x32 ... 0x33 -#define NV3_PCI_CFG_VBIOS_BASE_L 0x32 -#define NV3_PCI_CFG_VBIOS_BASE_H 0x33 - -#define NV3_AGP_CAPABILITIES_POINTER 0x34 - -#define NV3_PCI_CFG_INT_LINE 0x3C -#define NV3_PCI_CFG_INT_PIN 0x3D - -#define NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START 0x40 -#define NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END 0x43 - -#define NV3_PCI_CFG_MIN_GRANT 0x3E -#define NV3_PCI_CFG_MIN_GRANT_DEFAULT 0x03 -#define NV3_PCI_CFG_MAX_LATENCY 0x3F -#define NV3_PCI_CFG_MAX_LATENCY_DEFAULT 0x01 - -// -// AGP configuration -// - -#define NV3_AGP_START 0x44 - -// stupid stupid pci system -#define NV3_AGP_CAPABILITIES_START 0x44 -#define NV3_AGP_CAPABILITIES_CAP_ID 0x44 -#define NV3_AGP_CAPABILITIES_CAP_ID_AGP 0x02 // "AGP" -#define NV3_AGP_CAPABILITIES_NEXT_PTR 0x45 -#define NV3_AGP_CAPABILITIES_AGP_VERSION 0x46 -#define NV3_AGP_CAPABILITIES_AGP_VERSION_MINOR 0 -#define NV3_AGP_CAPABILITIES_AGP_VERSION_MAJOR 4 -#define NV3_AGP_CAPABILITIES_H 0x47 - -#define NV3_AGP_STATUS_RATE 0x48 -#define NV3_AGP_STATUS_RATE_1X_SUPPORTED 0x1 -#define NV3_AGP_STATUS_RATE_2X_SUPPORTED 0x2 - -#define NV3_AGP_STATUS_BYTE1 0x49 -#define NV3_AGP_STATUS_BYTE1_SBA 1 -#define NV3_AGP_STATUS_SBA_SUPPORTED 0x0 -#define NV3_AGP_STATUS_SBA_UNSUPPORTED 0x1 -#define NV3_AGP_STATUS_MAX_REQUESTS 0x4B -#define NV3_AGP_STATUS_MAX_REQUESTS_AMOUNT 4 - -#define NV3_AGP_COMMAND 0x4C -#define NV3_AGP_COMMAND_DATA_RATE 0 -#define NV3_AGP_COMMAND_DATA_RATE_1X 0x1 -#define NV3_AGP_COMMAND_DATA_RATE_2X 0x2 -#define NV3_AGP_COMMAND_BYTE1 0x4D -#define NV3_AGP_COMMAND_BYTE1_ENABLE 0 -#define NV3_AGP_COMMAND_BYTE1_ENABLE_DISABLED 0x0 -#define NV3_AGP_COMMAND_BYTE1_ENABLE_ENABLED 0x1 -#define NV3_AGP_COMMAND_SBA_ENABLE 1 -#define NV3_AGP_COMMAND_SBA_ENABLE_DISABLED 0x0 -#define NV3_AGP_COMMAND_SBA_ENABLE_ENABLED 0x1 -#define NV3_AGP_COMMAND_REQUEST_DEPTH 0x4F - -#define NV3_AGP_END 0x4F - -// -// ACPI (NV3T only) -// TODO: IMPLEMENT THIS!!!!!! -// -#define NV3_POWER_CAP_ID 0x60 -#define NV3_POWER_NEXT_PTR 0x61 -#define NV3_POWER_VERSION 0x62 - -// "The RIVA128ZX does not physically change its power consumption when -// POWER_STATE is modified." -#define NV3_POWER_STATE 0x64 - -#define NV3_POWER_STATE_D0 0x0 -#define NV3_POWER_STATE_D3HOT 0x3 - -// GPU Subsystems -// These most likely correspond to functional blocks in the original design - -#define NV3_PMC_START 0x0 // Chip Master Control Subsystem - -#define NV3_PMC_BOOT 0x0 // Boot Configuration - -#define NV3_PMC_INTERRUPT_STATUS 0x100 // Interrupt Control -#define NV3_PMC_INTERRUPT_PAUDIO 0 // Unused, NV3A only -#define NV3_PMC_INTERRUPT_PAUDIO_PENDING 0x1 // Unused, NV3A only -#define NV3_PMC_INTERRUPT_PMEDIA 4 -#define NV3_PMC_INTERRUPT_PMEDIA_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PFIFO 8 -#define NV3_PMC_INTERRUPT_PFIFO_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PGRAPH0 12 -#define NV3_PMC_INTERRUPT_PGRAPH0_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PGRAPH1 13 -#define NV3_PMC_INTERRUPT_PGRAPH1_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PVIDEO 16 -#define NV3_PMC_INTERRUPT_PVIDEO_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PTIMER 20 -#define NV3_PMC_INTERRUPT_PTIMER_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PFB 24 -#define NV3_PMC_INTERRUPT_PFB_PENDING 0x1 -#define NV3_PMC_INTERRUPT_PBUS 28 -#define NV3_PMC_INTERRUPT_PBUS_PENDING 0x1 -#define NV3_PMC_INTERRUPT_SOFTWARE 31 -#define NV3_PMC_INTERRUPT_SOFTWARE_PENDING 0x1 -#define NV3_PMC_INTERRUPT_ENABLE 0x140 // Controls global interrupt enable state -#define NV3_PMC_INTERRUPT_ENABLE_HARDWARE 0x1 // Determines if hardware interrupts are enabled -#define NV3_PMC_INTERRUPT_ENABLE_SOFTWARE 0x2 // Determinse if software interrupts were enabled -#define NV3_PMC_ENABLE 0x200 // Determines which gpu subsystems were enabled -#define NV3_PMC_ENABLE_PAUDIO 0 // UNUSED - PAudio removed in NV3 Stepping B0 -#define NV3_PMC_ENABLE_PAUDIO_ENABLED 0x1 // UNUSED - PAudio removed in NV3 Stepping B0 -#define NV3_PMC_ENABLE_PMEDIA 4 -#define NV3_PMC_ENABLE_PMEDIA_ENABLED 0x1 -#define NV3_PMC_ENABLE_PFIFO 8 -#define NV3_PMC_ENABLE_PFIFO_ENABLED 0x1 -#define NV3_PMC_ENABLE_PGRAPH 12 // Determines if PGRAPH is enabled. -#define NV3_PMC_ENABLE_PGRAPH_ENABLED 0x1 -#define NV3_PMC_ENABLE_PPMI 16 -#define NV3_PMC_ENABLE_PPMI_ENABLED 0x1 -#define NV3_PMC_ENABLE_PFB 20 -#define NV3_PMC_ENABLE_PFB_ENABLED 0x1 -#define NV3_PMC_ENABLE_PCRTC 24 -#define NV3_PMC_ENABLE_PCRTC_ENABLED 0x1 -#define NV3_PMC_ENABLE_PVIDEO 28 -#define NV3_PMC_ENABLE_PVIDEO_ENABLED 0x1 - -#define NV3_PMC_END 0xfff // overlaps with CIO -#define NV3_CIO_START 0x3b0 // Legacy SVGA Emulation Subsystem -#define NV3_CIO_END 0x3df -#define NV3_PBUS_START 0x1000 // Bus Control Subsystem -#define NV3_PBUS_DEBUG_0 0x1084 // Bus Control Debug -#define NV3_PBUS_INTR 0x1100 // Bus Control - Interrupt Status - -#define NV3_PBUS_INTR_EN 0x1140 // Bus Control - Interrupt Enable -#define NV3_PBUS_PCI_START 0x1800 // PCI mirror start -#define NV3_PBUS_PCI_END 0x18FF // PCI mirror end -#define NV3_PBUS_END 0x1FFF -#define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects) - -#define NV3_PFIFO_MINIMUM_GUARANTEED_DEPTH 0x7C - -#define NV3_PFIFO_DELAY_0 0x2040 // PFIFO Config Register -#define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register -#define NV3_PFIFO_CACHE0_ERROR_PENDING 0 -#define NV3_PFIFO_CACHE1_ERROR_PENDING 4 - -#define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status -#define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable - -// PFIFO interrupts -#define NV3_PFIFO_INTR_CACHE_ERROR 0 -#define NV3_PFIFO_INTR_RUNOUT 4 -#define NV3_PFIFO_INTR_RUNOUT_OVERFLOW 8 -#define NV3_PFIFO_INTR_DMA_PUSHER 12 -#define NV3_PFIFO_INTR_DMA_PTE 16 - -#define NV3_PFIFO_CONFIG_0 0x2200 -#define NV3_PFIFO_CONFIG_0_DMA_FETCH 8 - -#define NV3_PFIFO_CONFIG_RAMHT 0x2210 // Hashtable for graphics objects config -#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 // 15:12 -#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS_DEFAULT 0x0 -#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 // 17:16 -#define NV3_PFIFO_CONFIG_RAMHT_SIZE_4K 0x0 -#define NV3_PFIFO_CONFIG_RAMHT_SIZE_8K 0x1 -#define NV3_PFIFO_CONFIG_RAMHT_SIZE_16K 0x2 -#define NV3_PFIFO_CONFIG_RAMHT_SIZE_32K 0x3 - -#define NV3_PFIFO_CONFIG_RAMFC 0x2214 -#define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS 9 -#define NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS_DEFAULT 0x1C00 // Hardcoded in silicon? -#define NV3_PFIFO_CONFIG_RAMRO 0x2218 -#define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS 9 -#define NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS_DEFAULT 0x1E00 // Hardcoded in silicon? -#define NV3_PFIFO_CONFIG_RAMRO_SIZE 16 -#define NV3_PFIFO_CONFIG_RAMRO_SIZE_512B 0x0 -#define NV3_PFIFO_CONFIG_RAMRO_SIZE_8K 0x1 - -#define NV3_PFIFO_RUNOUT_STATUS 0x2400 -#define NV3_PFIFO_RUNOUT_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty -#define NV3_PFIFO_RUNOUT_STATUS_FULL 8 -#define NV3_PFIFO_RUNOUT_PUT 0x2410 -#define NV3_PFIFO_RUNOUT_PUT_ADDRESS 3 // 9:3 if small ramfc(?) otherwise 12:3 -#define NV3_PFIFO_RUNOUT_GET 0x2420 -#define NV3_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 - -#define NV3_PFIFO_RUNOUT_RAMIN_ERR 28 // bit to or with - -#define NV3_PFIFO_CACHE0_SIZE 1 // This is for software-injected notified only! -#define NV3_PFIFO_CACHE1_SIZE_REV_AB 32 -#define NV3_PFIFO_CACHE1_SIZE_REV_C 64 -#define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C -#define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 - -#define NV3_PFIFO_CACHE0_PUSH_ENABLED 0x3000 -#define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 -#define NV3_PFIFO_CACHE0_PUT 0x3010 -#define NV3_PFIFO_CACHE0_STATUS 0x3014 -#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty -#define NV3_PFIFO_CACHE0_STATUS_FULL 8 -#define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE0_PULL0 0x3040 -#define NV3_PFIFO_CACHE0_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE0_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD 8 -#define NV3_PFIFO_CACHE0_PULLER_CTX_STATE 0x3050 -#define NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY 4 // 1=dirty 0=clean -#define NV3_PFIFO_CACHE0_GET 0x3070 -#define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit -// Current channel context - cache1 -#define NV3_PFIFO_CACHE0_CTX 0x3080 - -#define NV3_PFIFO_CACHE0_METHOD_START 0x3100 -#define NV3_PFIFO_CACHE0_METHOD_END 0x3200 -#define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 -#define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 -#define NV3_PFIFO_CACHE1_PUSH_ENABLED 0x3200 -#define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 -#define NV3_PFIFO_CACHE1_PUT 0x3210 -#define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 -#define NV3_PFIFO_CACHE1_STATUS 0x3214 -#define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up -#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty -#define NV3_PFIFO_CACHE1_STATUS_FULL 8 -#define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218 -#define NV3_PFIFO_CACHE1_DMA_STATUS_STATE 0 -#define NV3_PFIFO_CACHE1_DMA_STATUS_STATE_IDLE 0x00 -#define NV3_PFIFO_CACHE1_DMA_STATUS_STATE_RUNNING 0x01 -#define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220 -#define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224 -#define NV3_PFIFO_CACHE1_DMA_CONFIG_2 0x3228 -#define NV3_PFIFO_CACHE1_DMA_CONFIG_3 0x322C -#define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE 0 // The type of bus we are sending over -#define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_PCI 0x02 // The type of bus we are sending over -#define NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_AGP 0x03 // The type of bus we are sending over - -// Why does a gpu need its own translation lookaside buffer and pagetable format. Are they crazy -// Seems to be the same format as the notifier engine -#define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 -#define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // pagetable entry for dma -#define NV3_PFIFO_CACHE1_DMA_TLB_PTE_IS_PRESENT 1 -#define NV3_PFIFO_CACHE1_DMA_TLB_FRAME_ADDRESS 12 // 31:12 -#define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULL0 0x3240 -//todo: merge stuff -#define NV3_PFIFO_CACHE1_PULL0_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE 4 -#define NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD 8 // 0=software, 1=hardware -#define NV3_PFIFO_CACHE1_PULLER_CTX_STATE 0x3250 -#define NV3_PFIFO_CACHE1_PULLER_CTX_STATE_DIRTY 4 -#define NV3_PFIFO_CACHE1_GET 0x3270 -#define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 - -// Current channel context - cache1 -#define NV3_PFIFO_CACHE1_CTX_START 0x3280 -#define NV3_PFIFO_CACHE1_CTX_END 0x32F0 - -#define NV3_PFIFO_CACHE1_METHOD_START 0x3300 -#define NV3_PFIFO_CACHE1_METHOD_END 0x3400 -#define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2 -#define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13 - - -#define NV3_PFIFO_END 0x3FFF -#define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem -#define NV3_PRM_INTR 0x4100 -#define NV3_PRM_INTR_EN 0x4140 -#define NV3_PRM_END 0x4FFF -#define NV3_PRAM_START 0x6000 // Local ram/cache? -#define NV3_PRAM_END 0x6FFF -#define NV3_PRMIO_START 0x7000 // Real-Mode I/O Subsystem -#define NV3_PRMIO_END 0x7FFF -#define NV3_PTIMER_START 0x9000 // Programmable Interval Timer -#define NV3_PTIMER_INTR 0x9100 -#define NV3_PTIMER_INTR_ALARM 0 // Alarm interrupt -#define NV3_PTIMER_INTR_EN 0x9140 -#define NV3_PTIMER_NUMERATOR 0x9200 -#define NV3_PTIMER_DENOMINATOR 0x9210 -#define NV3_PTIMER_TIME_0_NSEC 0x9400 // nanoseconds [31:5] -#define NV3_PTIMER_TIME_1_NSEC 0x9410 // nanoseconds [28:0] -#define NV3_PTIMER_ALARM_NSEC 0x9420 // nanoseconds [31:5] -#define NV3_PTIMER_END 0x9FFF -#define NV3_VGA_VRAM_START 0xA0000 // VGA Emulation VRAM -#define NV3_VGA_VRAM_END 0xBFFFF -#define NV3_VGA_START 0xC0000 // VGA Emulation Registers -#define NV3_VGA_END 0xC7FFF -#define NV3_PRMVIO_START NV3_VGA_START // VGA stuff written from main GPU -#define NV3_PRMVIO_END 0xC0400 -#define NV3_PFB_START 0x100000 // GPU Interface to VRAM -#define NV3_PFB_BOOT 0x100000 // Boot registration -#define NV3_PFB_BOOT_RAM_AMOUNT 0 // The amount of ram -#define NV3_PFB_BOOT_RAM_AMOUNT_8MB 0x0 // 1mb in NV3A -#define NV3_PFB_BOOT_RAM_AMOUNT_2MB 0x1 -#define NV3_PFB_BOOT_RAM_AMOUNT_4MB 0x2 -#define NV3_PFB_BOOT_RAM_AMOUNT_UNDEFINED 0x3 // i assume this is used for debug -#define NV3_PFB_BOOT_RAM_WIDTH 2 // the bus width of the gpu's vram -#define NV3_PFB_BOOT_RAM_WIDTH_64 0x0 // 64bit -#define NV3_PFB_BOOT_RAM_WIDTH_128 0x1 // 128bit -#define NV3_PFB_BOOT_RAM_BANKS 3 // the number of banks -#define NV3_PFB_BOOT_RAM_BANKS_2 0x0 // 2 banks (seems to be used for 2mb) -#define NV3_PFB_BOOT_RAM_BANKS_4 0x1 // 4 banks (seems to be used for 4mb) -#define NV3_PFB_BOOT_RAM_DATA_TWIDDLE 4 -#define NV3_PFB_BOOT_RAM_DATA_TWIDDLE_OFF 0x0 -#define NV3_PFB_BOOT_RAM_DATA_TWIDDLE_ON 0x1 -#define NV3_PFB_BOOT_RAM_EXTENSION 5 -#define NV3_PFB_BOOT_RAM_EXTENSION_NONE 0x0 -#define NV3_PFB_BOOT_RAM_EXTENSION_8MB 0x1 - -#define NV3_PFB_DELAY 0x100044 -#define NV3_PFB_DEBUG_0 0x100080 // Debug register for pfb -#define NV3_PFB_GREEN_0 0x1000C0 - -#define NV3_PFB_CONFIG_0 0x100200 // Framebuffer interface config register 0 - -// What is this lol -// ??? Part of the memory timings -#define NV3_PFB_RTL 0x100300 -#define NV3_PFB_CONFIG_0_RESOLUTION 0 -// 1=40 horiz. resolution -// i assume it can be divided by some kind of divisor to produce the vertical resolution (e.g. 3/2 or multiply by 2/3) to get the final -// horiz is 32*value -// theoretically it should support resolutions from 40-2560 horiz - -// WHAT ARE THE TIMINGS: ARE THEY IN THE VBIOS? -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_320 0xA -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_400 0xD -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_480 0xF -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_512 0x10 -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_640 0x14 -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_800 0x19 -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_960 0x1E -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1024 0x20 -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1152 0x24 -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1280 0x28 -#define NV3_PFB_CONFIG_0_HORIZ_RESOLUTION_1600 0x32 - -#define NV3_PFB_CONFIG_0_PIXEL_DEPTH 8 -#define NV3_PFB_CONFIG_0_DEPTH_8BPP 0x1 -#define NV3_PFB_CONFIG_0_DEPTH_16BPP 0x2 -#define NV3_PFB_CONFIG_0_DEPTH_32BPP 0x3 - -#define NV3_PFB_CONFIG_1 0x100204 // Framebuffer interface config register 1 -#define NV3_PFB_END 0x100FFF -#define NV3_PEXTDEV_START 0x101000 // External Devices -#define NV3_PSTRAPS 0x101000 // Straps Bits -#define NV3_PSTRAPS_BUS_SPEED 0 // Configured bus speed -#define NV3_PSTRAPS_BUS_SPEED_33MHZ 0x0 -#define NV3_PSTRAPS_BUS_SPEED_66MHZ 0x1 -#define NV3_PSTRAPS_BIOS 1 // Is a VBIOS present? -#define NV3_PSTRAPS_BIOS_NOT_PRESENT 0x0 -#define NV3_PSTRAPS_BIOS_PRESENT 1 -#define NV3_PSTRAPS_RAM_TYPE 2 // Type of RAM module -#define NV3_PSTRAPS_RAM_TYPE_16MBIT 0x0 -#define NV3_PSTRAPS_RAM_TYPE_8MBIT 0x1 -#define NV3_PSTRAPS_NEC_MODE 3 // PC98? -#define NV3_PSTRAPS_NEC_MODE_DISABLED 0x0 -#define NV3_PSTRAPS_NEC_MODE_ENABLED 0x1 -#define NV3_PSTRAPS_BUS_WIDTH 4 // Bus width -#define NV3_PSTRAPS_BUS_WIDTH_64BIT 0x0 -#define NV3_PSTRAPS_BUS_WIDTH_128BIT 0x0 -#define NV3_PSTRAPS_BUS_TYPE 5 // Determines if this is a PCI or AGP card -#define NV3_PSTRAPS_BUS_TYPE_PCI 0x0 -#define NV3_PSTRAPS_BUS_TYPE_AGP 0x1 -#define NV3_PSTRAPS_CRYSTAL 6 // type of clock crystal -#define NV3_PSTRAPS_CRYSTAL_13500K 0x0 // 13.5 Mhz -#define NV3_PSTRAPS_CRYSTAL_14318180 0x1 // 14.318180 Mhz clock crystal -#define NV3_PSTRAPS_TVMODE 7 // Type of TV signal to put out -#define NV3_PSTRAPS_TVMODE_SECAM 0x0 -#define NV3_PSTRAPS_TVMODE_NTSC 0x1 -#define NV3_PSTRAPS_TVMODE_PAL 0x2 -#define NV3_PSTRAPS_TVMODE_NONE 0x3 -#define NV3_PSTRAPS_AGP2X 9 -#define NV3_PSTRAPS_AGP2X_ENABLED 0x0 -#define NV3_PSTRAPS_AGP2X_DISABLED 0x1 -#define NV3_PSTRAPS_UNUSED 10 -#define NV3_PSTRAPS_OVERWRITE 11 -#define NV3_PSTRAPS_OVERWRITE_DISABLED 0x0 -#define NV3_PSTRAPS_OVERWRITE_ENABLED 0x1 -#define NV3_PEXTDEV_END 0x101FFF -#define NV3_PROM_START 0x110000 // VBIOS? -#define NV3_PROM_END 0x11FFFF -#define NV3_PALT_START 0x120000 // ??? but it exists -#define NV3_PALT_END 0x12FFFF -#define NV3_PME_START 0x200000 // Mediaport -#define NV3_PME_INTR 0x200100 // Mediaport: Interrupt Pending? -#define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable -#define NV3_PME_END 0x200FFF - -#define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part -// PGRAPH Core - -#define NV3_PGRAPH_MAX_BUFFERS 4 - -// For these debug registers, 0=Disabled, 1=Enabled - -// Debug 0: General -#define NV3_PGRAPH_DEBUG_0 0x400080 -#define NV3_PGRAPH_DEBUG_0_STATE_IN_RESET 0 -#define NV3_PGRAPH_DEBUG_0_AP_PIPE_IN_RESET 1 -#define NV3_PGRAPH_DEBUG_0_CACHE_IN_RESET 2 -#define NV3_PGRAPH_DEBUG_0_3D_PIPE_IN_RESET 3 -#define NV3_PGRAPH_DEBUG_0_BULK_READS 4 -#define NV3_PGRAPH_DEBUG_0_TILING 16 -#define NV3_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20 -#define NV3_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D 21 -#define NV3_PGRAPH_DEBUG_0_DRAWDIR_AUT 24 -#define NV3_PGRAPH_DEBUG_0_DRAWDIR_Y 25 -#define NV3_PGRAPH_DEBUG_0_ALPHA_ABORT 28 - -// Debug 1: Registers -#define NV3_PGRAPH_DEBUG_1 0x400084 -#define NV3_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0 -#define NV3_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 4 -#define NV3_PGRAPH_DEBUG_1_TURBO3D_2X 8 -#define NV3_PGRAPH_DEBUG_1_TURBO3D_4X 9 -#define NV3_PGRAPH_DEBUG_1_TRIANGLE_OPS 12 -#define NV3_PGRAPH_DEBUG_1_TRIANGLE_CLIP_OPS 13 -#define NV3_PGRAPH_DEBUG_1_INSTANCE 16 -#define NV3_PGRAPH_DEBUG_1_CONTEXT 20 -#define NV3_PGRAPH_DEBUG_1_CACHE_FLUSH 24 -#define NV3_PGRAPH_DEBUG_1_ZCLAMP 28 - -// Debug 2: 3D Pipeline -#define NV3_PGRAPH_DEBUG_2 0x400088 -#define NV3_PGRAPH_DEBUG_2_AVOID_READMODIFYWRITE_BLEND 0 -#define NV3_PGRAPH_DEBUG_2_DPWR_FIFO 8 -#define NV3_PGRAPH_DEBUG_2_BILINEAR_FILTERING_3D 12 -#define NV3_PGRAPH_DEBUG_2_ANISOTROPIC_FILTERING_3D 13 -#define NV3_PGRAPH_DEBUG_2_FOG 14 -#define NV3_PGRAPH_DEBUG_2_LIGHTING 15 // Not sure what this does, maybe hardware t&l was planned -#define NV3_PGRAPH_DEBUG_2_BILINEAR_FILTERING_2D 16 -#define NV3_PGRAPH_DEBUG_2_ANISOTROPIC_FILTERING_2D 17 -#define NV3_PGRAPH_DEBUG_2_D3D_COALESCE 20 // coalesce reads/writes for d3d class 0x17 -#define NV3_PGRAPH_DEBUG_2_D3D_COALESCE_POINT_ZETA 22 // class 0x18 coalesce -#define NV3_PGRAPH_DEBUG_2_PREFETCH 24 -#define NV3_PGRAPH_DEBUG_2_VOLATILE_RESET 28 - -// Debug 3: Zeta & Alpha Buffer -#define NV3_PGRAPH_DEBUG_3 0x40008C -#define NV3_PGRAPH_DEBUG_3_CULLING 0 -#define NV3_PGRAPH_DEBUG_3_FAST_DATA_D3D 4 -#define NV3_PGRAPH_DEBUG_3_FAST_DATA_STRETCH 5 -#define NV3_PGRAPH_DEBUG_3_ZFLUSH 7 -#define NV3_PGRAPH_DEBUG_3_AUTOZFLUSH_POINT_ZETA 8 -#define NV3_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D 9 -#define NV3_PGRAPH_DEBUG_3_SLOT_CONFLICT_POINT_ZETA 10 // Slot conflict handling for POINT_ZETA (class 0x18) -#define NV3_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D 11 // Slot conflict handling for D3D5_TRI (class 0x17) -#define NV3_PGRAPH_DEBUG_3_EARLY_ZABORT 12 -#define NV3_PGRAPH_DEBUG_3_TRIANGLE_END_FLUSH 13 -#define NV3_PGRAPH_DEBUG_3_ZFIFO_NOOP 14 // ??? -#define NV3_PGRAPH_DEBUG_3_DITHER 15 -#define NV3_PGRAPH_DEBUG_3_FORCE_COLOR_BUFFER_READ 16 -#define NV3_PGRAPH_DEBUG_3_FORCE_ZETA_BUFFER_READ 17 -#define NV3_PGRAPH_DEBUG_3_DATA_CHECK 20 -#define NV3_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21 -#define NV3_PGRAPH_DEBUG_3_FORMAT_CHECK 22 -#define NV3_PGRAPH_DEBUG_3_ALPHA_CHECK 24 - -// Interrupt stuff -#define NV3_PGRAPH_INTR_0 0x400100 -#define NV3_PGRAPH_INTR_0_VBLANK 8 // Fired every frame -#define NV3_PGRAPH_INTR_0_VBLANK_ENABLED 0x1 // Is the vblank interrupt enabled? -#define NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY 28 // Fired on software notification - -#define NV3_PGRAPH_INTR_1 0x400104 -#define NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING 0 // Software or invalid method -#define NV3_PGRAPH_INTR_1_INVALID_DATA 4 // Invalid data. Not sure when this would be triggered. -#define NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY 12 // Tried to notify while a notify was pending. -#define NV3_PGRAPH_INTR_1_CTXSW_NOTIFY 16 // Notify fired for software context - -#define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 -//todo: add what this does -#define NV3_PGRAPH_INTR_EN_1 0x400144 // Interrupt Control for PGRAPH #2 (it can receive two at onc) -#define NV3_PGRAPH_CTX_SWITCH 0x400180 // Holds the current PGRAPH context, switched by context switching - -/* Contextual information for pgraph */ -#define NV3_PGRAPH_CTX_SWITCH_COLOR_FORMAT 0 // Holds the current color format used for drawing operations. -#define NV3_PGRAPH_CTX_SWITCH_ALPHA 3 // Holds a boolean indicating in if alpha transparency is currently enabled in drawing operations. -#define NV3_PGRAPH_CTX_SWITCH_MONO_FORMAT 8 // Holds the current color format used for monochome drawing operations. -#define NV3_PGRAPH_CTX_SWITCH_DAC_BYPASS 9 // Holds if PRAMDAC should be bypassed, and an external DAC drawn. -#define NV3_PGRAPH_CTX_SWITCH_Z_WRITE 12 // Holds if we should write back to the zbuffer. -#define NV3_PGRAPH_CTX_SWITCH_CHROMA_KEY 13 // Holds the current chroma mask used for drawing operations. -#define NV3_PGRAPH_CTX_SWITCH_PLANE_MASK 14 // Holds the current plane mask used for drawing operations. -#define NV3_PGRAPH_CTX_SWITCH_USER_CLIP 15 // Holds the user-specified clipping information used for drawing operations. -#define NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER 16 // Holds the buffer ID used for drawing operation (i.e. which bpixel/bpitch/boffset index to use) -#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER0_ENABLED 20 // Holds a boolean indicating if buffer 0 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER1_ENABLED 21 // Holds a boolean indicating if buffer 1 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER2_ENABLED 22 // Holds a boolean indicating if buffer 2 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CTX_SWITCH_DST_BUFFER3_ENABLED 23 // Holds a boolean indicating if buffer 3 can be used as the destination for a drawing operation. -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG 24 // ROP type - -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0 0x0 // Reserved -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_DST_SRC 0x1 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_DST 0x2 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_SRC 0x3 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_DST 0x4 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_SRC 0x5 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_DST 0x6 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_SRC0 0x7 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_SRC1 0x8 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_SRC_PAT 0x9 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_SRC 0xA -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_PAT 0xB -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_SRC 0xC -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_PAT 0xD -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_PAT_SRC 0xE -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD1 0xF -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_DST 0x10 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_DST_SRC 0x11 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_DST 0x12 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_PAT 0x13 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_PAT_SRC 0x14 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_PAT 0x15 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD2 0x16 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS 0x17 // Ignore -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD0 0x18 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_SRC_DST 0x19 -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_DST_SRC 0x1A -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD1 0x1B -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD2 0x1C -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_SRC 0x1D -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD3 0x1E -#define NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_BLEND_RSVD4 0x1F - -#define NV3_PGRAPH_CTX_SWITCH_VOLATILE 31 // HUH - -#define NV3_PGRAPH_CONTEXT_CONTROL 0x400190 // DMA context control -#define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename -#define NV3_PGRAPH_CONTEXT_CACHE(i) 0x4001A0+(i*4) // Context Cache -#define NV3_PGRAPH_CONTEXT_CACHE_SIZE 8 -// TODO: CLIP0/CLIP1 (8 clips min/max in 32bits) -#define NV3_PGRAPH_ABS_UCLIP_XMIN 0x40053C // Clip X minimum -#define NV3_PGRAPH_ABS_UCLIP_XMAX 0x400540 // Clip X maximum -#define NV3_PGRAPH_ABS_UCLIP_YMIN 0x400544 // Clip Y minimum -#define NV3_PGRAPH_ABS_UCLIP_YMAX 0x400548 // Clip Y maximum -#define NV3_PGRAPH_SRC_CANVAS_MIN 0x400550 // Minimum Source Canvas for Blit, Y=30:16, X=10:0 -#define NV3_PGRAPH_SRC_CANVAS_MAX 0x400554 // Maximum Source Canvas for Blit, Y=30:16, X=10:0 -#define NV3_PGRAPH_DST_CANVAS_MIN 0x400558 // Minimum Destination Canvas for Blit, Y=30:16, X=10:0 -#define NV3_PGRAPH_DST_CANVAS_MAX 0x40055C // Maximum Destination Canvas for Blit, Y=30:16, X=10:0 -#define NV3_PGRAPH_PATTERN_COLOR_0_RGB 0x400600 -#define NV3_PGRAPH_PATTERN_COLOR_0_ALPHA 0x400604 -#define NV3_PGRAPH_PATTERN_COLOR_1_RGB 0x400608 -#define NV3_PGRAPH_PATTERN_COLOR_1_ALPHA 0x40060C // pattern color -#define NV3_PGRAPH_PATTERN_BITMAP_HIGH 0x400610 // pattern bitmap [31:0] -#define NV3_PGRAPH_PATTERN_BITMAP_LOW 0x400614 // pattern bitmap [63:32] -#define NV3_PGRAPH_PATTERN_SHAPE 0x400618 -#define NV3_PGRAPH_ROP3 0x400624 // ROP3 -#define NV3_PGRAPH_PLANE_MASK 0x400628 -#define NV3_PGRAPH_CHROMA_KEY 0x40062C -#define NV3_PGRAPH_BETA 0x400640 // Beta factor (30:23 fractional, 22:0 before fraction) -#define NV3_PGRAPH_DMA 0x400680 -#define NV3_PGRAPH_INSTANCE 0x400688 // Current instance (?) - -// Current notification object for pgraph -#define NV3_PGRAPH_NOTIFY 0x400684 // Notifier for PGRAPH -#define NV3_PGRAPH_NOTIFY_INSTANCE 0 -#define NV3_PGRAPH_NOTIFY_REQUEST_PENDING 16 -#define NV3_PGRAPH_NOTIFY_REQUEST_TYPE 20 -#define NV3_PGRAPH_NOTIFY_REQUEST_TYPE_HARDWARE 0x0 // anything else is software - -#define NV3_PGRAPH_CLIP0_MIN 0x400690 // Clip for Blitting 0 Min -#define NV3_PGRAPH_CLIP0_MAX 0x400694 // Clip for Blitting 0 Max -#define NV3_PGRAPH_CLIP1_MIN 0x400698 // Clip for Blitting 1 Min -#define NV3_PGRAPH_CLIP1_MAX 0x40069C // Clip for Blitting 1 Max -#define NV3_PGRAPH_CLIP_MISC 0x4006A0 // Regions/Render/Complex mode -#define NV3_PGRAPH_FIFO_ACCESS 0x4006A4 // Is PGRAPH enabled? -#define NV3_PGRAPH_FIFO_ACCESS_DISABLED 0x0 -#define NV3_PGRAPH_FIFO_ACCESS_ENABLED 0x1 -#define NV3_PGRAPH_CLIP_MISC 0x4006A0 // Miscellaneous clipping information -#define NV3_PGRAPH_STATUS 0x4006B0 // Current PGRAPH status -#define NV3_PGRAPH_TRAPPED_ADDRESS 0x4006B4 -#define NV3_PGRAPH_TRAPPED_DATA 0x4006B8 -#define NV3_PGRAPH_TRAPPED_INSTANCE 0x4006BC - -#define NV3_PGRAPH_DMA_INTR_0 0x401100 // PGRAPH DMA Interrupt Status -#define NV3_PGRAPH_DMA_INTR_INSTANCE 0 -#define NV3_PGRAPH_DMA_INTR_PRESENT 4 -#define NV3_PGRAPH_DMA_INTR_PROTECTION 8 -#define NV3_PGRAPH_DMA_INTR_LINEAR 12 -#define NV3_PGRAPH_DMA_INTR_NOTIFY 16 -#define NV3_PGRAPH_DMA_INTR_EN_0 0x401140 // PGRAPH DMA Interrupt Enable 0 - -#define NV3_PGRAPH_DPRAM_SIZE 12288 // Size of the internal texture cache - -// not sure about the class ids -// these are NOT what each class is, just uSed to manipulate it (there isn't a one to one class->reg mapping anyway) -#define NV3_PGRAPH_CLASS01_BETA_START 0x410000 // Beta blending factor -#define NV3_PGRAPH_CLASS01_BETA_END 0x411FFF -#define NV3_PGRAPH_CLASS02_ROP_START 0x420000 // Blending render operation used at final pixel/fragment generation stage -#define NV3_PGRAPH_CLASS02_ROP_END 0x421FFF -#define NV3_PGRAPH_CLASS03_COLORKEY_START 0x430000 // Color key for image -#define NV3_PGRAPH_CLASS03_COLORKEY_END 0x431FFF -#define NV3_PGRAPH_CLASS04_PLANEMASK_START 0x440000 // Plane mask (for clipping?) -#define NV3_PGRAPH_CLASS04_PLANEMASK_END 0x441FFF -#define NV3_PGRAPH_CLASS05_CLIP_START 0x450000 // clipping, probably class 23 -#define NV3_PGRAPH_CLASS05_CLIP_END 0x451FFF -#define NV3_PGRAPH_CLASS06_PATTERN_START 0x460000 // presumably a blend pattern -#define NV3_PGRAPH_CLASS06_PATTERN_END 0x461FFF -#define NV3_PGRAPH_CLASS07_RECTANGLE_START 0x470000 // also class 25 - that's black [NV1] -#define NV3_PGRAPH_CLASS07_RECTANGLE_END 0x471FFF // also class 25 - that's black [NV1] -#define NV3_PGRAPH_CLASS08_POINT_START 0x480000 // A single point -#define NV3_PGRAPH_CLASS08_POINT_END 0x481FFF -#define NV3_PGRAPH_CLASS09_LINE_START 0x490000 // A line -#define NV3_PGRAPH_CLASS09_LINE_END 0x491FFF -#define NV3_PGRAPH_CLASS0A_LIN_START 0x4A0000 // A lin - a line without its starting or ending pixels -#define NV3_PGRAPH_CLASS0A_LIN_END 0x4A1FFF -#define NV3_PGRAPH_CLASS0B_TRIANGLE_START 0x4B0000 // A triangle [NV1 variant] - in NV1 this was converted to a quad patch -#define NV3_PGRAPH_CLASS0B_TRIANGLE_END 0x4B1FFF -#define NV3_PGRAPH_CLASS0C_GDITEXT_START 0x4C0000 // Windows 95/NT GDI text acceleration -#define NV3_PGRAPH_CLASS0C_GDITEXT_END 0x4C1FFF - -#define NV3_PGRAPH_CLASS0D_MEM2MEM_XFER_START 0x4D0000 // memory to memory transfer (not sure about which class this is) -#define NV3_PGRAPH_CLASS0D_MEM2MEM_XFER_END 0x4D1FFF -#define NV3_PGRAPH_CLASS0E_IMAGE2MEM_XFER_SCALED_START 0x4E0000 // class 55, 56 -#define NV3_PGRAPH_CLASS0F_IMAGE2MEM_XFER_SCALED_END 0x4E1FFF - -#define NV3_PGRAPH_CLASS10_BLIT_START 0x500000 // Blit 2d image from memory -#define NV3_PGRAPH_CLASS10_BLIT_END 0x501FFF - -#define NV3_PGRAPH_CLASS11_CPU2MEM_IMAGE_START 0x510000 // Used for class 33, 34, 54 -#define NV3_PGRAPH_CLASS11_CPU2MEM_IMAGE_END 0x511FFF -#define NV3_PGRAPH_CLASS12_CPU2MEM_BITMAP_START 0x520000 // not sure, might depend on format -#define NV3_PGRAPH_CLASS12_CPU2MEM_BITMAP_END 0x521FFF - -#define NV3_PGRAPH_CLASS14_IMAGE2MEM_XFER_START 0x540000 // send image to vram, not sure what class -#define NV3_PGRAPH_CLASS14_IMAGE2MEM_XFER_END 0x541FFF -#define NV3_PGRAPH_CLASS15_CPU2MEM_STRETCHED_START 0x550000 // stretched cpu->vram transfer, 54 -#define NV3_PGRAPH_CLASS15_CPU2MEM_STRETCHED_END 0x551FFF - -#define NV3_PGRAPH_CLASS17_D3D5TRI_ZETA_START 0x570000 // [NV3] Copy a direct3d 5.0 accelerated triangle to the zeta buffer -#define NV3_PGRAPH_CLASS17_D3D5TRI_ZETA_END 0x571FFF -#define NV3_PGRAPH_CLASS18_POINTZETA_START 0x580000 // possibly class 69 -#define NV3_PGRAPH_CLASS18_POINTZETA_END 0x581FFF - -#define NV3_PGRAPH_CLASS1C_MEM2IMAGE_START 0x5C0000 // class 55, 56, 62, 63? -#define NV3_PGRAPH_CLASS1C_MEM2IMAGE_END 0x5C1FFF - - -#define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers -#define NV3_PGRAPH_REAL_END 0x5C1FFF - -// PRMCIO is redirected to SVGA subsystem -#define NV3_PRMCIO_START 0x601000 - - - -#define NV3_PRMCIO_END 0x601FFF - -#define NV3_PDAC_START 0x680000 // OPTIONAL external DAC -#define NV3_PVIDEO_START 0x680000 // Video Generation / overlay configuration -#define NV3_PVIDEO_INTR 0x680100 -#define NV3_PVIDEO_INTR_EN 0x680140 -#define NV3_PVIDEO_FIFO_THRESHOLD 0x680238 -#define NV3_PVIDEO_FIFO_BURST_LENGTH 0x68023C -#define NV3_PVIDEO_OVERLAY 0x680244 -#define NV3_PVIDEO_OVERLAY_VIDEO_IS_ON 0 -#define NV3_PVIDEO_OVERLAY_KEY_ENABLED 4 -#define NV3_PVIDEO_OVERLAY_FORMAT 8 // 0 = CCIR, 1 = YUY2 - -#define NV3_PVIDEO_END 0x6802FF -#define NV3_PRAMDAC_START 0x680300 - -#define NV3_PRAMDAC_CURSOR_START 0x680300 - -#define NV3_PRAMDAC_CURSOR_SIZE_X 32 -#define NV3_PRAMDAC_CURSOR_SIZE_Y 32 - -#define NV3_PRAMDAC_CLOCK_MEMORY 0x680504 -#define NV3_PRAMDAC_CLOCK_MEMORY_VDIV 7:0 -#define NV3_PRAMDAC_CLOCK_MEMORY_NDIV 15:8 -#define NV3_PRAMDAC_CLOCK_MEMORY_PDIV 18:16 -#define NV3_PRAMDAC_CLOCK_PIXEL 0x680508 -#define NV3_PRAMDAC_COEFF_SELECT 0x68050C - -#define NV3_PRAMDAC_GENERAL_CONTROL 0x680600 -#define NV3_PRAMDAC_GENERAL_CONTROL_565_MODE 12 - -// These are all 10-bit values, but aligned to 32bits -// so treating them as 32bit should be fine -#define NV3_PRAMDAC_VSERR_WIDTH 0x680700 -#define NV3_PRAMDAC_VEQU_END 0x680704 -#define NV3_PRAMDAC_VBBLANK_END 0x680708 -#define NV3_PRAMDAC_VBLANK_END 0x68070C -#define NV3_PRAMDAC_VBLANK_START 0x680710 -#define NV3_PRAMDAC_VBBLANK_START 0x680714 -#define NV3_PRAMDAC_VEQU_START 0x680718 -#define NV3_PRAMDAC_VTOTAL 0x68071C -#define NV3_PRAMDAC_HSYNC_WIDTH 0x680720 -#define NV3_PRAMDAC_HBURST_START 0x680724 -#define NV3_PRAMDAC_HBURST_END 0x680728 -#define NV3_PRAMDAC_HBLANK_START 0x68072C -#define NV3_PRAMDAC_HBLANK_END 0x680730 -#define NV3_PRAMDAC_HTOTAL 0x680734 -#define NV3_PRAMDAC_HEQU_WIDTH 0x680738 -#define NV3_PRAMDAC_HSERR_WIDTH 0x68073C - -#define NV3_PRAMDAC_END 0x680FFF -#define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC - - -#define NV3_USER_DAC_START 0x681200 -#define NV3_USER_DAC_PALETTE_START 0x6813C6 -#define NV3_USER_DAC_PIXEL_MASK 0x6813C6 -#define NV3_USER_DAC_READ_MODE_ADDRESS 0x6813C7 //bit0=read/write mode? -#define NV3_USER_DAC_WRITE_MODE_ADDRESS 0x6813C8 -#define NV3_USER_DAC_PALETTE_DATA 0x6813C9 -#define NV3_USER_DAC_PALETTE_SIZE 768 -#define NV3_USER_DAC_PALETTE_END 0x6813C9 -#define NV3_USER_DAC_END 0x681FFF - -#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?) -#define NV3_USER_END 0xFFFFFF - -// easier name -#define NV3_OBJECT_SUBMIT_START NV3_USER_START -#define NV3_OBJECT_SUBMIT_SUBCHANNEL 13 -#define NV3_OBJECT_SUBMIT_CHANNEL 16 -#define NV3_OBJECT_SUBMIT_END NV3_USER_END - -// also PDFB (Debug Framebuffer?) -#define NV3_PNVM_START 0x1000000 // VRAM access (max 8MB) -#define NV3_PNVM_END 0x17FFFFF - -// to be less confusing - NVM = "NV Memory" -#define NV3_VRAM_START NV3_PNVM_START -#define NV3_VRAM_END NV3_PNVM_END - -// control structures for dma'd in graphics objects from pfifo -// these all have configurable sizes, define them here -#define NV3_RAMIN_START 0x1C00000 - -#define NV3_RAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects -#define NV3_RAMIN_RAMHT_END 0x1C00FFF -#define NV3_RAMIN_RAMHT_SIZE_0 0xFFF -#define NV3_RAMIN_RAMHT_SIZE_1 0x1FFF -#define NV3_RAMIN_RAMHT_SIZE_2 0x3FFF -#define NV3_RAMIN_RAMHT_SIZE_3 0x7FFF - -/* OBSOLETE AREA for AUDIO probably. DO NOT USE! */ -#define NV3_RAMIN_RAMAU_START 0x1C01000 -#define NV3_RAMIN_RAMAU_END 0x1C01BFF -#define NV3_RAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels -#define NV3_RAMIN_RAMFC_END 0x1C01DFF -#define NV3_RAMIN_RAMFC_SIZE_0 0x1FF -#define NV3_RAMIN_RAMFC_SIZE_1 0xFFF -#define NV3_RAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions -#define NV3_RAMIN_RAMRO_SIZE_0 0x1FF -#define NV3_RAMIN_RAMRO_SIZE_1 0x1FFF -#define NV3_RAMIN_RAMRO_END 0x1C01FFF -#define NV3_RAMIN_RAMRM_START 0x1C02000 -#define NV3_RAMIN_RAMRM_END 0x1C02FFF - -// I'm not sure if this can be moved. -// 4K of "PRAM" is listed at 0x6000. -#define NV3_RAMIN_OFFSET_CURSOR 0x6000 - -#define NV3_RAMIN_END 0x1FFFFFF - -// not done - -// CRTC/CIO (0x3b0-0x3df) - -#define NV3_CRTC_REGISTER_INDEX_MONO 0x3B4 -#define NV3_CRTC_REGISTER_MONO 0x3B5 // Currently Selected CRTC Register - Monochrome - -#define NV3_CRTC_DATA_OUT 0x3C0 -#define NV3_CRTC_MISCOUT 0x3C2 - -#define NV3_RMA_REGISTER_START 0x3D0 -#define NV3_RMA_REGISTER_END 0x3D3 - -#define NV3_CRTC_REGISTER_INDEX 0x3D4 -#define NV3_CRTC_REGISTER_CURRENT 0x3D5 - -#define NV3_CRTC_REGISTER_WTF 0x3D8 - -// These are standard (0-18h) -#define NV3_CRTC_REGISTER_HTOTAL 0x00 -#define NV3_CRTC_REGISTER_HDISPEND 0x01 -#define NV3_CRTC_REGISTER_HBLANKSTART 0x02 -#define NV3_CRTC_REGISTER_HBLANKEND 0x03 -#define NV3_CRTC_REGISTER_HRETRACESTART 0x04 -#define NV3_CRTC_REGISTER_HRETRACEEND 0x05 -#define NV3_CRTC_REGISTER_VTOTAL 0x06 -#define NV3_CRTC_REGISTER_OVERFLOW 0x07 -#define NV3_CRTC_REGISTER_PRESETROWSCAN 0x08 -#define NV3_CRTC_REGISTER_MAXSCAN 0x09 -#define NV3_CRTC_REGISTER_CURSOR_START 0x0A -#define NV3_CRTC_REGISTER_CURSOR_START_DISABLED 5 -#define NV3_CRTC_REGISTER_CURSOR_END 0x0B -#define NV3_CRTC_REGISTER_STARTADDR_HIGH 0x0C -#define NV3_CRTC_REGISTER_STARTADDR_LOW 0x0D -#define NV3_CRTC_REGISTER_CURSORLOCATION_HIGH 0x0E -#define NV3_CRTC_REGISTER_CURSORLOCATION_LOW 0x0F -#define NV3_CRTC_REGISTER_VRETRACESTART 0x10 -#define NV3_CRTC_REGISTER_VRETRACEEND 0x11 -#define NV3_CRTC_REGISTER_VDISPEND 0x12 -#define NV3_CRTC_REGISTER_OFFSET 0x13 -#define NV3_CRTC_REGISTER_UNDERLINELOCATION 0x14 -#define NV3_CRTC_REGISTER_STARTVBLANK 0x15 -#define NV3_CRTC_REGISTER_ENDVBLANK 0x16 -#define NV3_CRTC_REGISTER_CRTCCONTROL 0x17 -#define NV3_CRTC_REGISTER_LINECOMP 0x18 -#define NV3_CRTC_REGISTER_STANDARDVGA_END 0x18 - - -// These are nvidia, licensed from weitek (25-63) -#define NV3_CRTC_REGISTER_RPC0 0x19 // 7:5 - [10:8] of CRTC. 4:0 - [20:16] of 21-bit display buffer address -#define NV3_CRTC_REGISTER_RPC1 0x1A // bit7=hsync enabled, bit6=vsync enabled, bit4="compatible text", bit2=large screen, bit1=6bit palette width (>1280) -#define NV3_CRTC_REGISTER_READ_BANK 0x1D -#define NV3_CRTC_REGISTER_WRITE_BANK 0x1E -#define NV3_CRTC_REGISTER_FORMAT 0x25 -#define NV3_CRTC_REGISTER_FORMAT_VDT10 0 // Use 10 bit vtotal value instead of 8 bit -#define NV3_CRTC_REGISTER_FORMAT_VDE10 1 // Use 10 bit dispend value instead of 8 bit -#define NV3_CRTC_REGISTER_FORMAT_VRS10 2 // Use 10 bit vblank start value instead of 8 bit -#define NV3_CRTC_REGISTER_FORMAT_VBS10 3 // Use 10 bit vsync start value instead of 8 bit -#define NV3_CRTC_REGISTER_FORMAT_HBE6 4 // Use 6 bit hsync start value -#define NV3_CRTC_REGISTER_PIXELMODE 0x28 - -#define NV3_CRTC_REGISTER_HEB 0x2D // HRS most significant bit - -#define NV3_CRTC_REGISTER_CURSOR_ADDR0 0x30 // Cursor high 21:16 -#define NV3_CRTC_REGISTER_CURSOR_ADDR1 0x31 // Cursor low (1:0 = enable) 15:11 - -#define NV3_CRTC_REGISTER_PIXELMODE_VGA 0x00 // vga textmode -#define NV3_CRTC_REGISTER_PIXELMODE_8BPP 0x01 -#define NV3_CRTC_REGISTER_PIXELMODE_16BPP 0x02 -#define NV3_CRTC_REGISTER_PIXELMODE_32BPP 0x03 - -#define NV3_CRTC_REGISTER_RL0 0x34 -#define NV3_CRTC_REGISTER_RL1 0x35 -#define NV3_CRTC_REGISTER_RMA 0x38 // REAL MODE ACCESS! -#define NV3_CRTC_REGISTER_I2C 0x3E -#define NV3_CRTC_REGISTER_I2C_GPIO 0x3F - -#define NV3_CRTC_BANKED_128K_A0000 0x00 -#define NV3_CRTC_BANKED_64K_A0000 0x04 -#define NV3_CRTC_BANKED_32K_B0000 0x08 -#define NV3_CRTC_BANKED_32K_B8000 0x0C - -#define NV3_CRTC_REGISTER_NVIDIA_END 0x3F - -// for 86box 8bit addressing -// get rid of this asap, replace with 32->8 macros -#define NV3_RMA_SIGNATURE_MSB 0x65 -#define NV3_RMA_SIGNATURE_BYTE2 0xD0 -#define NV3_RMA_SIGNATURE_BYTE1 0x16 -#define NV3_RMA_SIGNATURE_LSB 0x2B - -#define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F - -/* - STRUCTURES FOR THE GPU START HERE - OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H -*/ - -//todo: pixel format - -// Master Control -typedef struct nv3_pmc_s -{ - /* - Holds chip manufacturing information at bootup. - Current specification (may change later): pre-packed for convenience - - Revision A: - FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?) - 31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001 - little endian 00000000 00000011 00000001 00010001 = 0x00300111# - Revision B/c: - write this later - */ - int32_t boot; - int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems. - int32_t interrupt_enable; // Determines if interrupts are actually enabled. - int32_t enable; // Determines which subsystems are enabled. - -} nv3_pmc_t; - -// add enums for eac -// Chip configuration -typedef struct nv3_straps_s -{ - uint32_t straps; -} nv3_straps_t; - -// Framebuffer -typedef struct nv3_pfb_s -{ - uint32_t boot; - uint32_t debug_0; // debug stuff - uint32_t config_0; // Framebuffer width, etc. - uint32_t config_1; - uint32_t green; - uint32_t delay; - uint32_t rtl; // Part of the memory timings -} nv3_pfb_t; - -// -// DMA & Notifier Engine -// All singing all dancing all happy happy bullshit to send dma transfers literally anywhere in your computer -// - -// Not a notification status, because it's a 16-bit enum -// C23 fixes this -#define NV3_NOTIFICATION_STATUS_DONE_OK 0x0 -#define NV3_NOTIFICATION_STATUS_IN_PROGRESS 0xFF -#define NV3_NOTIFICATION_STATUS_ERROR 0x100 - -#define NV3_NOTIFICATION_INFO_ADJUST 0 // Wut -#define NV3_NOTIFICATION_PT_PRESENT 16 // Determines if the pagetable exists. -#define NV3_NOTIFICATION_TARGET 24 // Determines where this notification goes -#define NV3_DMA_TARGET_NODE_VRAM 0 // VRAM target for DMA -#define NV3_DMA_TARGET_NODE_CART 1 // "Cartridge" target for dma, only mentioned in a few places, !!! NV2 LEFTOVER !!! -#define NV3_DMA_TARGET_NODE_PCI 2 // Send the data to the host system over PCI -#define NV3_DMA_TARGET_NODE_AGP 3 // Send the data to the host system over AGP - -#define NV3_NOTIFICATION_PAGE_IS_PRESENT 0 // Determines if the page really exists -#define NV3_NOTIFICATION_PAGE_ACCESS 1 // Determines the page access type -#define NV3_NOTIFICATION_PAGE_ACCESS_READ 0x0 // If this is set, the page is read only -#define NV3_NOTIFICATION_PAGE_ACCESS_READ_WRITE 0x1 // If this is set, the page is read/write -#define NV3_NOTIFICATION_PAGE_FRAME_ADDRESS 12 // The pageframe to use - - - -// Core notification structure -typedef struct nv3_notification_s -{ - uint64_t nanoseconds; - uint32_t info32; - uint16_t info16; - uint16_t status; -} nv3_notification_t; - -#define NV3_RMA_NUM_REGS 4 -// Access the GPU from real-mode -typedef struct nv3_pbus_rma_s -{ - uint32_t addr; // Address to RMA to - uint32_t data; // Data to send to MMIO - uint8_t mode; // the current state of the rma shifting engin - uint8_t rma_regs[NV3_RMA_NUM_REGS]; // The rma registers (saved) -} nv3_pbus_rma_t; - -// Bus Configuration -typedef struct nv3_pbus_s -{ - uint32_t debug_0; - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable - nv3_pbus_rma_t rma; -} nv3_pbus_t; - -typedef struct nv3_pfifo_cache_s -{ - bool push0; // Can we even access this cache? - uint8_t put_address; // Trigger a DMA into the value you put here. - uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. - uint8_t channel; // The DMA channel ID of this cache. - uint32_t status; - uint32_t pull0; - uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL]; // Only one of these exists for cache0 - - /* cache1 only - do we even need to emulate this? - */ - uint32_t dma_status; // 0x3218 - bool dma_enabled; // 0x3220 bit0 - bool dma_is_busy; // 0x3220 bit4 - - uint32_t dma_state; // Corresponds to PFIFO_CACHE1_DMA0 - uint32_t dma_length; // Corresponds to PFIFO_CACHE1_DMA1 - uint32_t dma_address; // Corresponds to PFIFO_CACHE1_DMA2 - uint8_t dma_target_node; // Corresponds to PFIFO_CACHE1_DMA3 depends on card bus - uint8_t dma_tlb_tag; - uint8_t dma_tlb_pte; // DMA Engine - Translation Lookaside Buffer - uint8_t dma_tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres - uint16_t method_address; // address of the method (i.e. what method it is) - uint16_t method_subchannel; // subchannel - bool context_is_dirty; - - /* TODO */ -} nv3_pfifo_cache_t; - -typedef struct nv3_pfifo_cache_entry_s -{ - uint16_t method; // method id depending on class (offset from entry channel start in ramin) - uint8_t subchannel; - uint32_t data; // is this the context - -} nv3_pfifo_cache_entry_t; - -// Command submission to PGRAPH -typedef struct nv3_pfifo_s -{ - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable - uint32_t dma_delay_retry; // DMA Delay/Retry - uint32_t debug_0; // Cache Debug register - uint32_t config_0; - uint32_t ramht_config; // RAMHT config - uint32_t ramfc_config; // RAMFC config - uint32_t ramro_config; // RAMRO config - // Runout stuff - uint32_t runout_put; // 8:3 if RAMRO=512b, otherwise 12:3 - uint32_t runout_get; // 8:3 if RAMRO=512b, otherwise 12:3 - - // Cache stuff - uint32_t cache_reassignment; // Allow context switching - nv3_pfifo_cache_t cache0_settings; - nv3_pfifo_cache_t cache1_settings; - - nv3_pfifo_cache_entry_t cache0_entry; // It only has 1 entry - nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS -} nv3_pfifo_t; - -// RAMDAC -typedef struct nv3_pramdac_s -{ - // these should be uint8_t but C math is a lot better with this - uint32_t memory_clock_m; // memory clock M-divider - uint32_t memory_clock_n; // memory clock N-divider - uint32_t memory_clock_p; // memory clock P-divider - uint32_t pixel_clock_m; // pixel clock M-divider - uint32_t pixel_clock_n; // pixel clock N-divider - uint32_t pixel_clock_p; // pixel clock P-divider - uint32_t coeff_select; // coefficient select - - uint32_t general_control; // general control register - - // this could duplicate SVGA state but I tihnk it's more readable, - // we'll just modify both - uint32_t vserr_width; // vertical sync error width - uint32_t vequ_end; // vequ end (not sure what this is) - uint32_t vbblank_end; // vbblank end (not sure what this is) - uint32_t vblank_end; // vblank end - uint32_t vblank_start; // vblank start - uint32_t vequ_start; // vequ start (not sure what this is) - uint32_t vtotal; // vertical total lines - uint32_t hsync_width; // horizontal sync width - uint32_t hburst_start; // horizontal burst signal start (in lines) - uint32_t hburst_end; // horizontal burst signal end (in lines) - uint32_t hblank_start; // horizontal blank start (in lines) - uint32_t hblank_end; // horizontal blank end (in lines) - uint32_t htotal; // horizontal total lines - uint32_t hequ_width; // horizontal equ width (not sure what this is) - uint32_t hserr_width; // horizontal sync error width - - uint8_t user_pixel_mask; // pixel mask for DAC lookup - uint32_t user_read_mode_address; // user read mode address - uint32_t user_write_mode_address; // user write mode address - uint8_t palette[NV3_USER_DAC_PALETTE_SIZE]; // Palette Info/CLUT - 256 entries, 1 byte for r,g,b = 768 bytes - - uint32_t cursor_address; // cursor address start - nv3_coord_16_t cursor_start; -} nv3_pramdac_t; - -/* Holds DMA channel context information */ -typedef struct NV3_PGRAPH_CTX_SWITCH_s -{ - /* TODO */ -} NV3_PGRAPH_CTX_SWITCH_t; - -typedef struct nv3_pgraph_context_control_s -{ - /* TODO */ -} nv3_pgraph_context_control_t; - -/* DMA object context info - Context uploaded from CACHE0/CACHE1 by DMA Puller -*/ -typedef struct nv3_pgraph_context_user_s -{ - union - { - uint32_t value; - - struct - { - bool reserved3 : 1; - uint8_t channel : 7; - uint8_t reserved2 : 3; - uint8_t class_id : 5; - uint8_t subchannel : 3; - uint16_t reserved : 13; - }; - }; -} nv3_pgraph_context_user_t; - -typedef struct nv3_pgraph_dma_settings_s -{ - /* TODO */ -} nv3_pgraph_dma_settings_t; - -typedef struct nv3_pgraph_clip_misc_settings_s -{ - /* TODO */ -} nv3_pgraph_clip_misc_settings_t; - -typedef struct nv3_pgraph_status_s -{ - bool overall_busy : 1; // Is anything busy? - uint8_t reserved : 3; - bool xy_logic_busy : 1; // Determines if the line drawing/xy/vector stuff is busy. - uint8_t reserved2 : 3; - bool port_notify_busy : 1; // Mediaport?/PIO? notifier engine busy - uint8_t reserved3 : 3; - bool port_register_busy : 1; - uint8_t reserved4 : 3; - bool port_dma_busy : 1; // Mediaport?/PIO? DMA engine busy - bool dma_engine_busy : 1; // DMA engine busy - uint8_t reserved5 : 2; - bool dma_notify_busy : 1; // Are the notifiers busy? - uint8_t reserved6 : 3; - bool engine_3d_busy : 1; // 3d engine busy? - bool engine_cache_busy : 1; // PFIFO CACHE0/CACHE1 busy? - bool engine_zfifo_busy : 1; // ZFIFO (zeta buffer? z buffer?) busy? - bool port_user_busy : 1; // User context switch? - uint8_t reserved7 : 3; - -} nv3_pgraph_status_t; - -/* All of this B* stuff is registers at 400630..40065c and 4006a8 in reality, easier to implement it like this - BPixel = Buffer Pixel Format -*/ -#define NV3_BPIXEL_FORMAT 0 -#define NV3_BPIXEL_FORMAT_IS_VALID 2 -#define NV3_BPIXEL_DEPTH 4 - -typedef enum nv3_pgraph_bpixel_format_e -{ - // Y16 - bpixel_fmt_y16 = 0, - // 8-bit colour - bpixel_fmt_8bit = 1, - // 16-bit colour - bpixel_fmt_16bit = 2, - // 32-bit colour (ARGB) - bpixel_fmt_32bit = 3, -} nv3_pgraph_bpixel_format; - -typedef enum nv3_pgraph_destination_buffer_e -{ - pgraph_dest_buffer0 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER0_ENABLED), - pgraph_dest_buffer1 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER1_ENABLED), - pgraph_dest_buffer2 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER2_ENABLED), - pgraph_dest_buffer3 = (1 << NV3_PGRAPH_CTX_SWITCH_DST_BUFFER3_ENABLED), -} nv3_pgraph_destination_buffer; - -// Graphics Subsystem -typedef struct nv3_pgraph_s -{ - uint32_t debug_0; - uint32_t debug_1; - uint32_t debug_2; - uint32_t debug_3; - uint32_t interrupt_status_0; // Interrupt status 0 - uint32_t interrupt_enable_0; // Interrupt enable 0 - uint32_t interrupt_status_1; // Interrupt status 1 - uint32_t interrupt_enable_1; // Interrupt enable 1 - uint32_t interrupt_status_dma; // Interrupt status for DMA - uint32_t interrupt_enable_dma; // Interrupt enable for DMA - - uint32_t context_switch; // TODO: Make this a struct, it's just going to be enormous lol. - nv3_pgraph_context_control_t context_control; - NV3_PGRAPH_CTX_SWITCH_t context_user_submit; - nv3_pgraph_context_user_t context_user; - uint32_t context_cache[NV3_PGRAPH_CONTEXT_CACHE_SIZE]; // DMA context cache (nv3_pgraph_context_user_t array?) - - // UCLIP stuff - uint32_t abs_uclip_xmin; - uint32_t abs_uclip_xmax; - uint32_t abs_uclip_ymin; - uint32_t abs_uclip_ymax; - // Canvas stuff - nv3_coord_16_bigy_t src_canvas_min; - nv3_coord_16_bigy_t src_canvas_max; - nv3_coord_16_bigy_t dst_canvas_min; - nv3_coord_16_bigy_t dst_canvas_max; - // Pattern stuff - nv3_color_expanded_t pattern_color_0_rgb; // ignore alpha - uint32_t pattern_color_0_alpha; // only 7:0 relevant - nv3_color_expanded_t pattern_color_1_rgb; // ignore alpha - uint32_t pattern_color_1_alpha; // only 7:0 relevant - uint64_t pattern_bitmap; // pattern bitmap for blit. it's alwaus 64 bits to simplify pixel rendering code - uint32_t pattern_shape; // may need to be an enum - 0=8x8, 1=64x1, 2=1x64 - uint32_t plane_mask; // only 7:0 relevant - uint32_t chroma_key; // color key - uint32_t beta_factor; - nv3_pgraph_dma_settings_t dma_settings; - uint8_t rop; // Current GDI Ternary Render Operation - // SURFACE STUFF - PGRAPH CAN OPERATE ON 4 SURFACES/BUFFERS AT A TIME - uint32_t boffset[NV3_PGRAPH_MAX_BUFFERS]; // 22-bit linear VRAM offset for the start of a buffer. - uint16_t bpitch[NV3_PGRAPH_MAX_BUFFERS]; // 12-bit linear VRAM offset for the pitch of a buffer - uint32_t bpixel[NV3_PGRAPH_MAX_BUFFERS]; // Pixel format for each possible surfaces. - // CLIP - nv3_pgraph_clip_misc_settings_t clip_misc_settings; - uint32_t notifier; - bool notify_pending; // Determines if a notification is pending. - /* Are these even used */ - nv3_coord_16_bigy_t clip0_min; - nv3_coord_16_bigy_t clip0_max; - nv3_coord_16_bigy_t clip1_min; - nv3_coord_16_bigy_t clip1_max; - /* idk */ - nv3_coord_16_t clip_start; // Start of the clipping region - nv3_coord_16_t clip_size; // Size of the clipping region. - bool fifo_access; // Determines if PGRAPH can access PFIFO. - nv3_pgraph_status_t status; // Current status of the 3D engine. - uint32_t trapped_address; - uint32_t trapped_data; - uint32_t instance; // no idea what this is but possibly an object context - uint32_t trapped_instance; - uint8_t dpram[NV3_PGRAPH_DPRAM_SIZE]; // Internal vertex/texturea cache. - - /* This area is used for holding universal representations of the U* registers, which are actually mapped into MMIO */ - struct nv3_object_class_001 beta_factor_class; - struct nv3_object_class_002 rop_class; - struct nv3_object_class_003 chroma_key_class; - struct nv3_object_class_004 plane_mask_class; - struct nv3_object_class_005 clipping_rectangle; - struct nv3_object_class_006 pattern; - struct nv3_object_class_007 rectangle; - struct nv3_object_class_008 point; - struct nv3_object_class_009 line; - struct nv3_object_class_00A lin; - struct nv3_object_class_00B triangle; - struct nv3_object_class_00C win95_gdi_text; - /* These are here so we can hold the current state of the image draw */ - uint32_t win95_gdi_text_bit_count; - nv3_coord_16_t win95_gdi_text_current_position; - struct nv3_object_class_00D m2mf; - struct nv3_object_class_00E scaled_image_from_memory; - struct nv3_object_class_010 blit; - struct nv3_object_class_011 image; - nv3_coord_16_t image_current_position; /* This is here so we can hold the current state of the image */ - struct nv3_object_class_012 bitmap; - struct nv3_object_class_014 transfer2memory; - struct nv3_object_class_015 stretched_image_from_cpu; - struct nv3_object_class_017 d3d5_tri; - struct nv3_object_class_018 point_zeta_buffer; - struct nv3_object_class_01C image_in_memory; -} nv3_pgraph_t; - - -// GPU Manufacturing Configuration (again) -// In the future this will be configurable -typedef struct nv3_pextdev_s -{ - /* - // Disabled 33Mhz - // Enabled 66Mhz - bool bus_speed; - - // Disabled No BIOS - // Enabled BIOS - bool bios; - - // RAM Type #1 - // Disabled 16Mbit (2MB) module size - // Enabled 8Mbit (1MB) module size - bool ram_type_1; - - // NEC Mode - bool nec_mode; - - // Disabled 64-bit - // Enabled 128-bit - bool bus_width; - - // Disabled PCI - // Enabled AGP - bool bus_type; - - // Disabled 13500 - // Enabled 14318180 - bool crystal; - - // TV Mode - // 0 - SECAM, 1 - NTSC, 2 - PAL, 3 - none - uint8_t tv_mode; - - // AGP 2X mode - // Disabled AGP 1X - // Enabled AGP 2X - bool agp_is_2x; - - bool unused; - - // Overwrite enable - bool overwrite; - - See defines in vid_nv3.h - */ - uint32_t straps; - - // more ram type stuff here but not used? -} nv3_pextdev_t; - -typedef struct nv3_ptimer_s -{ - uint32_t interrupt_status; // PTIMER Interrupt status - uint32_t interrupt_enable; // PTIMER Interrupt enable - uint32_t clock_numerator; // PTIMER (tick?) numerator - uint32_t clock_denominator; // PTIMER (tick?) denominator - uint64_t time; // time - uint32_t alarm; // The value of time when there should be an alarm -} nv3_ptimer_t; - -// Object name is just a uint32_t identifier it doesn't need a struct -// This is how the context is represented in ramin -// IN PGRAPH IT IS DIFFERENT! ONLY 5 BITS FOR THE CLASS ID! WHY? -typedef struct nv3_ramin_context_s -{ - union - { - uint32_t context; - - struct - { - uint16_t ramin_offset; - uint8_t class_id : 7; - bool is_rendering : 1; - uint8_t channel : 7; - bool reserved : 1; - }; - }; -} nv3_ramin_context_t; - -// Graphics object hashtable for specific DMA [channel, subchannel] pair -typedef struct nv3_ramin_ramht_subchannel_s -{ - uint32_t name; // must be >4096 - - // Contextual information. - // See the above union. - nv3_ramin_context_t context; -} nv3_ramin_ramht_subchannel_t; - -// Graphics object hashtable -typedef struct nv3_ramin_ramht_s -{ - nv3_ramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL]; -} nv3_ramin_ramht_t; - - -typedef enum nv3_ramin_ramro_reason_e -{ - nv3_runout_reason_illegal_access = 0, - - // PFIFO CACHE0/CACHE1 were turned off, so the graphics object could not be processed. - nv3_runout_reason_no_cache_available = 1, - - // Ran out of CACHE0 & CACHE1 space. - nv3_runout_reason_cache_ran_out = 2, - - nv3_runout_reason_free_count_overrun = 3, - - nv3_runout_reason_caught_lying = 4, - - // Access reserved by pagetable - nv3_runout_reason_reserved_access = 5, - -} nv3_ramin_ramro_reason; - -// context for unused channels -typedef struct nv3_ramin_ramfc_s -{ - -} nv3_ramin_ramfc_t; - -// RAM for AUDIO - RevisionA ONLY -typedef struct nv_ramin_ramau_s -{ - -} nv3_ramin_ramau_t; - -typedef struct nv3_ramin_s -{ - -} nv3_ramin_t; - - -typedef struct nv3_pvideo_s -{ - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable - uint32_t fifo_threshold; // FIFO threshold - uint32_t fifo_burst_size; // FIFO burst size - uint32_t overlay_settings; // Overlay settings -} nv3_pvideo_t; - -typedef struct nv3_pme_s // Mediaport -{ - uint32_t interrupt_status; - uint32_t interrupt_enable; -} nv3_pme_t; - -typedef struct nv3_s -{ - nv_base_t nvbase; // Base Nvidia structure - - // Config - nv3_straps_t straps; // OEM Configuration - - // Subsystems - nv3_pmc_t pmc; // Master Control - nv3_pfb_t pfb; // Framebuffer/VRAM - nv3_pbus_t pbus; // Bus Control - nv3_pfifo_t pfifo; // FIFO for command submission - - nv3_pramdac_t pramdac; // RAMDAC (CLUT etc) - nv3_pgraph_t pgraph; // 2D/3D Graphics - nv3_pextdev_t pextdev; // Chip configuration - nv3_ptimer_t ptimer; // programmable interval timer - nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects - // (ramro does not need a struct) - nv3_ramin_ramfc_t ramfc; // context for unused channels - nv3_ramin_ramau_t ramau; // auxillary weirdnes - nv3_ramin_t pramin; // INstance memory for graphics objects. Very important! - nv3_pvideo_t pvideo; // Video overlay - nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface - //more here - -} nv3_t; - -// device object -extern nv3_t* nv3; - -/* - *FUNCTIONS* for the GPU core start here - Functions for PGRAPH objects are in vid_nv3_classes.h -*/ - -// Device Core -void* nv3_init(const device_t *info); -void nv3_close(void* priv); -void nv3_speed_changed(void *priv); -void nv3_draw_cursor(svga_t* svga, int32_t drawline); -void nv3_recalc_timings(svga_t* svga); -void nv3_force_redraw(void* priv); - -/* BAR0 GPU MMIO read */ -void nv3_update_mappings(void); // Update memory mappings -uint8_t nv3_mmio_read8(uint32_t addr, void* priv); // Read 8-bit MMIO -uint16_t nv3_mmio_read16(uint32_t addr, void* priv); // Read 16-bit MMIO -uint32_t nv3_mmio_read32(uint32_t addr, void* priv); // Read 32-bit MMIO -void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit MMIO -void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit MMIO -void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit MMIO - -/* BAR1 Dumb Framebuffer Read */ -uint8_t nv3_dfb_read8(uint32_t addr, void* priv); // Write 8-bit DFB -uint16_t nv3_dfb_read16(uint32_t addr, void* priv); // Write 16-bit DFB -uint32_t nv3_dfb_read32(uint32_t addr, void* priv); // Write 32-bit DFB -void nv3_dfb_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit DFB -void nv3_dfb_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit DFB -void nv3_dfb_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit DFB - -uint8_t nv3_svga_read(uint16_t addr, void* priv); // Read SVGA compatibility registers -void nv3_svga_write(uint16_t addr, uint8_t val, void* priv); // Write SVGA registers -uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv); // Read PCI configuration registers -void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); // Write PCI configuration registers - -uint8_t nv3_ramin_read8(uint32_t addr, void* priv); // Read 8-bit RAMIN -uint16_t nv3_ramin_read16(uint32_t addr, void* priv); // Read 16-bit RAMIN -uint32_t nv3_ramin_read32(uint32_t addr, void* priv); // Read 32-bit RAMIN -void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv); // Write 8-bit RAMIN -void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN -void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN - -bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin -bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin - -// RAMIN functions -uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel); -bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel_id, uint8_t subchannel_id); -#ifndef RELEASE_BUILD -void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context); -#endif - -uint32_t nv3_ramfc_read(uint32_t address); -void nv3_ramfc_write(uint32_t address, uint32_t value); -uint32_t nv3_ramro_read(uint32_t address); -void nv3_ramro_write(uint32_t address, uint32_t value); -uint32_t nv3_ramht_read(uint32_t address); -void nv3_ramht_write(uint32_t address, uint32_t value); - -// MMIO Arbitration -// Determine where the hell in this mess our reads or writes are going -uint32_t nv3_mmio_arbitrate_read(uint32_t address); -void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value); - -// Read and Write functions for GPU subsystems -// Remove the ones that aren't used here eventually, have all of htem for now -uint32_t nv3_pmc_read(uint32_t address); -void nv3_pmc_write(uint32_t address, uint32_t value); -uint32_t nv3_cio_read(uint32_t address); -void nv3_cio_write(uint32_t address, uint32_t value); -uint32_t nv3_pbus_read(uint32_t address); -void nv3_pbus_write(uint32_t address, uint32_t value); -uint32_t nv3_prm_read(uint32_t address); -void nv3_prm_write(uint32_t address, uint32_t value); -uint32_t nv3_prmio_read(uint32_t address); -void nv3_prmio_write(uint32_t address, uint32_t value); -uint32_t nv3_ptimer_read(uint32_t address); -void nv3_ptimer_write(uint32_t address, uint32_t value); -uint32_t nv3_pfb_read(uint32_t address); -void nv3_pfb_write(uint32_t address, uint32_t value); -uint32_t nv3_pextdev_read(uint32_t address); -void nv3_pextdev_write(uint32_t address, uint32_t value); - -// Special consideration for straps -#define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS) -#define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x) - -// Reads from vbios are 8bit -uint8_t nv3_prom_read(uint32_t address); -void nv3_prom_write(uint32_t address, uint32_t value); -uint32_t nv3_palt_read(uint32_t address); -void nv3_palt_write(uint32_t address, uint32_t value); -uint32_t nv3_pme_read(uint32_t address); -void nv3_pme_write(uint32_t address, uint32_t value); - -// TODO: PGRAPH class registers - -uint32_t nv3_prmcio_read(uint32_t address); -void nv3_prmcio_write(uint32_t address, uint32_t value); -uint32_t nv3_pvideo_read(uint32_t address); -void nv3_pvideo_write(uint32_t address, uint32_t value); -uint32_t nv3_pramdac_read(uint32_t address); -void nv3_pramdac_write(uint32_t address, uint32_t value); - -uint32_t nv3_user_read(uint32_t address); -void nv3_user_write(uint32_t address, uint32_t value); -#define nv3_object_submit_start nv3_user_read -#define nv3_object_submit_end nv3_user_write -// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_ramin_* - -// GPU subsystems - -// NV3 PMC -void nv3_pmc_init(void); -void nv3_pmc_clear_interrupts(void); -uint32_t nv3_pmc_handle_interrupts(bool send_now); - -// NV3 PGRAPH -void nv3_pgraph_init(void); -uint32_t nv3_pgraph_read(uint32_t address); -void nv3_pgraph_write(uint32_t address, uint32_t value); -void nv3_pgraph_vblank_start(svga_t* svga); -void nv3_pgraph_interrupt_valid(uint32_t num); -void nv3_pgraph_interrupt_invalid(uint32_t num); -void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context); - -// PGRAPH class methods -// this should be in "vid_nv3_classes.h", but before that can happen, some things need to be rejigged -void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_002_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_004_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_008_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_009_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00a_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00b_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_00e_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_012_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_014_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_015_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_017_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_018_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); -void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj); - -// Notification Engine -void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context,nv3_grobj_t grobj); - -// NV3 PFIFO -void nv3_pfifo_init(void); -uint32_t nv3_pfifo_read(uint32_t address); -void nv3_pfifo_write(uint32_t address, uint32_t value); -void nv3_pfifo_interrupt(uint32_t id, bool fire_now); - -// NV3 PFIFO - Caches -//cache0_push not a thing -void nv3_pfifo_cache0_pull(void); -void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val); -void nv3_pfifo_cache1_pull(void); -uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); -uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); -uint32_t nv3_pfifo_cache1_num_free_spaces(void); - -// NV3 PFB -void nv3_pfb_init(void); - -// NV3 PEXTDEV/PSTRAPS -void nv3_pextdev_init(void); - -// NV3 PBUS -void nv3_pbus_init(void); - -// NV3 PBUS RMA - Real Mode Access for VBIOS -uint8_t nv3_pbus_rma_read(uint16_t addr); -void nv3_pbus_rma_write(uint16_t addr, uint8_t val); - -// NV3 PRAMDAC (Final presentation) -void nv3_pramdac_init(void); -void nv3_pramdac_set_vram_clock(void); -void nv3_pramdac_set_pixel_clock(void); -void nv3_pramdac_pixel_clock_poll(double real_time); -void nv3_pramdac_memory_clock_poll(double real_time); - -// NV3 PTIMER -void nv3_ptimer_init(void); -void nv3_ptimer_tick(double real_time); - -// NV3 PVIDEO -void nv3_pvideo_init(void); - -// NV3 PME (Mediaport) -void nv3_pme_init(void); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv4.h b/src/include/86box/nv/vid_nv4.h deleted file mode 100644 index 0f2aad285..000000000 --- a/src/include/86box/nv/vid_nv4.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Riva TNT hardware defines - * - * Authors: Connor Hyde - * - * Copyright 2024-2025 Connor Hyde - */ - - -#pragma once - -#include -#include -#include <86Box/nv/vid_nv4_defines.h> - -// -// Structures -// - - -// PBUS -// RMA: Access the GPU from real-mode -typedef struct nv4_pbus_rma_s -{ - uint32_t addr; // Address to RMA to - uint32_t data; // Data to send to MMIO - uint8_t mode; // the current state of the rma shifting engin - uint8_t rma_regs[NV4_RMA_NUM_REGS]; // The rma registers (saved) -} nv4_pbus_rma_t; - -// Bus Configuration -typedef struct nv4_pbus_s -{ - uint32_t debug_0; - uint32_t interrupt_status; // Interrupt status - uint32_t interrupt_enable; // Interrupt enable - nv4_pbus_rma_t rma; -} nv4_pbus_t; - - -// PTIMER -typedef struct nv4_ptimer_s -{ - uint32_t interrupt_status; // PTIMER Interrupt status - uint32_t interrupt_enable; // PTIMER Interrupt enable - uint32_t clock_numerator; // PTIMER (tick?) numerator - uint32_t clock_denominator; // PTIMER (tick?) denominator - uint64_t time; // time - uint32_t alarm; // The value of time when there should be an alarm -} nv4_ptimer_t; - -// PRAMDAC -typedef struct nv4_pramdac_s -{ - uint32_t mclk; - uint32_t vclk; - uint32_t nvclk; - uint32_t clk_coeff_select; // Clock coefficient selection - uint32_t cursor_address; -} nv4_pramdac_t; - -// Device Core -typedef struct nv4_s -{ - nv_base_t nvbase; // Base Nvidia structure - uint32_t straps; // Straps. See defines - nv4_pbus_t pbus; - nv4_ptimer_t ptimer; - nv4_pramdac_t pramdac; -} nv4_t; - -// -// Globals -// - -extern const device_config_t nv4_config[]; - -extern nv4_t* nv4; // Allocated at device startup - -#ifdef NV_LOG - -// Debug register list -extern nv_register_t nv4_registers[]; - -#endif - -// -// Functions -// - -// Device Core -bool nv4_init(); - -void* nv4_init_stb4400(const device_t* info); - -void nv4_close(void* priv); -void nv4_speed_changed(void *priv); -void nv4_draw_cursor(svga_t* svga, int32_t drawline); -void nv4_recalc_timings(svga_t* svga); -void nv4_force_redraw(void* priv); - -// I/O -uint8_t nv4_mmio_read8(uint32_t addr, void* priv); -uint16_t nv4_mmio_read16(uint32_t addr, void* priv); -uint32_t nv4_mmio_read32(uint32_t addr, void* priv); -void nv4_mmio_write8(uint32_t addr, uint8_t val, void* priv); -void nv4_mmio_write16(uint32_t addr, uint16_t val, void* priv); -void nv4_mmio_write32(uint32_t addr, uint32_t val, void* priv); -uint8_t nv4_dfb_read8(uint32_t addr, void* priv); -uint16_t nv4_dfb_read16(uint32_t addr, void* priv); -uint32_t nv4_dfb_read32(uint32_t addr, void* priv); -void nv4_dfb_write8(uint32_t addr, uint8_t val, void* priv); -void nv4_dfb_write16(uint32_t addr, uint16_t val, void* priv); -void nv4_dfb_write32(uint32_t addr, uint32_t val, void* priv); -uint8_t nv4_ramin_read8(uint32_t addr, void* priv); -uint16_t nv4_ramin_read16(uint32_t addr, void* priv); -uint32_t nv4_ramin_read32(uint32_t addr, void* priv); -void nv4_ramin_write8(uint32_t addr, uint8_t val, void* priv); -void nv4_ramin_write16(uint32_t addr, uint16_t val, void* priv); -void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv); -uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv); -void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv); - -// SVGA -uint8_t nv4_svga_read(uint16_t addr, void* priv); -void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); - -// Memory -void nv4_update_mappings(); - -// PRAMDAC -uint32_t nv4_pramdac_read(uint32_t address); -void nv4_pramdac_write(uint32_t address, uint32_t data); - -// We don't implement NVCLK/VCLK because they are too fast -void nv4_pramdac_set_vclk(); - -void nv4_vclk_tick(); - -// PTIMER -uint32_t nv4_ptimer_read(uint32_t address); -void nv4_ptimer_write(uint32_t address, uint32_t data); \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h deleted file mode 100644 index 2a959670c..000000000 --- a/src/include/86box/nv/vid_nv4_defines.h +++ /dev/null @@ -1,4291 +0,0 @@ -#pragma once - -#include -#include - -// -// General -// -#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only) -#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used) -#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB -#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB -#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only - -#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!! - -// -// VBIOS -// -#define NV4_VBIOS_STB_REVA "roms/video/nvidia/nv4/NV4_STB_velocity.rom" - -#define NV4_PRMIO_START 0x7000 -#define NV4_PRMIO_END 0x7FFF - -// NV4 Legacy I/O space -#define NV4_RMA_REGISTER_START 0x3D0 -#define NV4_RMA_REGISTER_END 0x3D3 -#define NV4_RMA_NUM_REGS 4 - -#define NV4_PRMIO_RMA_ID 0x7100 -#define NV4_PRMIO_RMA_ID_CODE 0 -#define NV4_PRMIO_RMA_ID_CODE_VALID 0x2B16D065 -#define NV4_PRMIO_RMA_PTR 0x7104 -#define NV4_PRMIO_RMA_PTR_ADDRESS 2 -#define NV4_PRMIO_RMA_DATA 0x7108 -#define NV4_PRMIO_RMA_DATA_PORT 0 -#define NV4_PRMIO_RMA_DATA32 0x710C -#define NV4_PRMIO_RMA_DATA32_BYTE2 16 -#define NV4_PRMIO_RMA_DATA32_BYTE1 8 -#define NV4_PRMIO_RMA_DATA32_BYTE0 0 -#define NV4_PRMIO_RMA_MODE_MAX 0x0F - -#define NV4_PRAMDAC_START 0x680300 -#define NV4_PRAMDAC_END 0x680FFF - -#define NV4_PRAMDAC_CU_START_POS 0x680300 -#define NV4_PRAMDAC_CU_START_POS_X 0 -#define NV4_PRAMDAC_CU_START_POS_Y 16 -#define NV4_PRAMDAC_NVPLL_COEFF 0x680500 -#define NV4_PRAMDAC_NVPLL_COEFF_MDIV 0 -#define NV4_PRAMDAC_NVPLL_COEFF_NDIV 8 -#define NV4_PRAMDAC_NVPLL_COEFF_PDIV 16 // 18:16 -#define NV4_PRAMDAC_MPLL_COEFF 0x680504 -#define NV4_PRAMDAC_MPLL_COEFF_MDIV 0 -#define NV4_PRAMDAC_MPLL_COEFF_NDIV 8 -#define NV4_PRAMDAC_MPLL_COEFF_PDIV 16 // 18:16 -#define NV4_PRAMDAC_VPLL_COEFF 0x680508 -#define NV4_PRAMDAC_VPLL_COEFF_MDIV 0 -#define NV4_PRAMDAC_VPLL_COEFF_NDIV 8 -#define NV4_PRAMDAC_VPLL_COEFF_PDIV 16 // 18:16 -#define NV4_PRAMDAC_PLL_COEFF_SELECT 0x68050C -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_XTAL 0x0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_VIP 0x1 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE 8 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_DEFAULT 0x0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL 0x1 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL 0x2 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL 0x4 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_ALL 0x7 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV 16 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_NONE 0x0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x1 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_PCLK 0x2 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_BOTH 0x3 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE 20 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE_EXT 0x0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_SOURCE_VIP 0x1 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO 24 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB1 0x0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB2 0x1 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x0 -#define NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x1 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL 0x680510 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_VALUE 0 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_VAL 0x44E -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN 12 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_ON 0x0 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_MPLL 0x1 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_VPLL 0x2 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_NVPLL 0x4 -#define NV4_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_OFF 0x7 -#define NV4_PRAMDAC_PLL_TEST_COUNTER 0x680514 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_NOOFIPCLKS 0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_VALUE 0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE 16 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE_DEASSERTED 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_ENABLE_ASSERTED 0x1 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET 20 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET_DEASSERTED 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_RESET_ASSERTED 0x1 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE 24 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_MCLK 0x2 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_VCLK 0x1 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_SOURCE_NVCLK 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIV_RST 28 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_DEASSERTED 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_ASSERTED 0x1 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK 29 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_NOTLOCKED 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCKED 0x1 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK 30 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_NOTLOCKED 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCKED 0x1 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK 31 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_NOTLOCKED 0x0 -#define NV4_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCKED 0x1 -#define NV4_PRAMDAC_PALETTE_TEST 0x680518 -#define NV4_PRAMDAC_PALETTE_TEST_BLUE_DATA 0 -#define NV4_PRAMDAC_PALETTE_TEST_GREEN_DATA 8 -#define NV4_PRAMDAC_PALETTE_TEST_RED_DATA 16 -#define NV4_PRAMDAC_PALETTE_TEST_MODE 24 -#define NV4_PRAMDAC_PALETTE_TEST_MODE_8BIT 0x0 -#define NV4_PRAMDAC_PALETTE_TEST_MODE_24BIT 0x1 -#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC 28 -#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC_READWRITE 0x0 -#define NV4_PRAMDAC_PALETTE_TEST_ADDRINC_WRITEONLY 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL 0x680600 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT 0 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_24 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_31 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX 4 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_OFF 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_POS 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_NEG 0x2 -#define NV4_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON 0x3 -#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8 -#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSEL 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_NOTSEL 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_15 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_16 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_24 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_ALT_MODE_30 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16 -#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION 17 -#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_BPC 20 -#define NV4_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24 -#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x1 -#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28 -#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x0 -#define NV4_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x1 -#define NV4_PRAMDAC_PALETTE_RECOVERY 0x680604 -#define NV4_PRAMDAC_PALETTE_RECOVERY_ACTIVE_ADDRESS 0 -#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER 8 -#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_RED 0x1 -#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_GREEN 0x2 -#define NV4_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_BLUE 0x4 -#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE 12 -#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_WRITE 0x0 -#define NV4_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_READ 0x3 -#define NV4_PRAMDAC_PALETTE_RECOVERY_RED_DATA 16 -#define NV4_PRAMDAC_PALETTE_RECOVERY_GREEN_DATA 24 -#define NV4_PRAMDAC_TEST_CONTROL 0x680608 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET 0 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET_DEASSERTED 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_RESET_ASSERTED 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE 4 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL 8 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_BLUE 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_GREEN 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_RED 0x2 -#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN 12 -#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN_DEASSERTED 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC 16 -#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_ON 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_DACTM 20 -#define NV4_PRAMDAC_TEST_CONTROL_DACTM_NORMAL 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_DACTM_TEST 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_TPATH1 24 -#define NV4_PRAMDAC_TEST_CONTROL_TPATH1_CLEAR 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_TPATH1_SET 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_TPATH31 25 -#define NV4_PRAMDAC_TEST_CONTROL_TPATH31_CLEAR 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_TPATH31_SET 0x1 -#define NV4_PRAMDAC_TEST_CONTROL_SENSEB 28 -#define NV4_PRAMDAC_TEST_CONTROL_SENSEB_SOMELO 0x0 -#define NV4_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI 0x1 -#define NV4_PRAMDAC_CHECKSUM 0x68060C -#define NV4_PRAMDAC_CHECKSUM_VALUE 0 -#define NV4_PRAMDAC_TESTPOINT_DATA 0x680610 -#define NV4_PRAMDAC_TESTPOINT_DATA_RED 0 -#define NV4_PRAMDAC_TESTPOINT_DATA_GREEN 10 -#define NV4_PRAMDAC_TESTPOINT_DATA_BLUE 20 -#define NV4_PRAMDAC_TESTPOINT_DATA_BLACK 30 -#define NV4_PRAMDAC_TESTPOINT_DATA_NOTBLANK 31 -#define NV4_PRAMDAC_TV_SETUP 0x680700 -#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE 0 -#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE_SLAVE 0x0 -#define NV4_PRAMDAC_TV_SETUP_DEV_TYPE_MASTER 0x1 -#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT 4 -#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_555 0x0 -#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_565 0x1 -#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_888 0x2 -#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_101010 0x3 -#define NV4_PRAMDAC_TV_SETUP_VS_PIXFMT_YUV 0x4 -#define NV4_PRAMDAC_TV_SETUP_DATA_SRC 8 -#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_COMP 0x0 -#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_SCALER 0x1 -#define NV4_PRAMDAC_TV_SETUP_DATA_SRC_VIP 0x2 -#define NV4_PRAMDAC_TV_SETUP_COMP_SRC 12 -#define NV4_PRAMDAC_TV_SETUP_COMP_SRC_SCALER 0x0 -#define NV4_PRAMDAC_TV_SETUP_COMP_SRC_NO_SCALER 0x1 -#define NV4_PRAMDAC_TV_SETUP_SYNC_POL 16 -#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_NONE 0x0 -#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_HSYNC 0x1 -#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_VSYNC 0x2 -#define NV4_PRAMDAC_TV_SETUP_SYNC_POL_NEG_BOTH 0x3 -#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC 20 -#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC_LEAD 0x0 -#define NV4_PRAMDAC_TV_SETUP_VIP_VSYNC_TRAIL 0x1 -#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS 24 -#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS_7_0 0x0 -#define NV4_PRAMDAC_TV_SETUP_VIP_DATAPOS_11_4 0x1 -#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD 28 -#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD_0 0x0 -#define NV4_PRAMDAC_TV_SETUP_VIP_FIELD_1 0x1 -#define NV4_PRAMDAC_TV_VBLANK_START 0x680704 -#define NV4_PRAMDAC_TV_VBLANK_START_VAL 0 -#define NV4_PRAMDAC_TV_VBLANK_END 0x680708 -#define NV4_PRAMDAC_TV_VBLANK_END_VAL 0 -#define NV4_PRAMDAC_TV_HBLANK_START 0x68070C -#define NV4_PRAMDAC_TV_HBLANK_START_VAL 0 -#define NV4_PRAMDAC_TV_HBLANK_END 0x680710 -#define NV4_PRAMDAC_TV_HBLANK_END_VAL 0 -#define NV4_PRAMDAC_BLANK_COLOR 0x680714 -#define NV4_PRAMDAC_BLANK_COLOR_VAL 0 -#define NV4_PRAMDAC_TV_CHECKSUM 0x680718 -#define NV4_PRAMDAC_TV_CHECKSUM_VAL 0 -#define NV4_PRAMDAC_TV_VSYNC 28 -#define NV4_PRAMDAC_TV_VSYNC_ACTIVE 0x0 -#define NV4_PRAMDAC_TV_VSYNC_INACTIVE 0x1 -#define NV4_PRAMDAC_TV_TEST_CONTROL 0x68071c -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET 0 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_DEASSERTED 0x0 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_ASSERTED 0x1 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE 4 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x0 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x1 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL 8 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_7_0 0x0 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_15_8 0x1 -#define NV4_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_23_16 0x2 - -#define NV4_USER_DAC_START 0x681200 -#define NV4_USER_DAC_END 0x681FFF -#define NV4_USER_DAC_PALETTE_START 0x6813C6 -#define NV4_USER_DAC_PALETTE_END 0x6813C9 - -#define NV4_USER_DAC_PIXEL_MASK 0x6813C6 -#define NV4_USER_DAC_PIXEL_MASK_VALUE 0 -#define NV4_USER_DAC_PIXEL_MASK_MASK 0xFF -#define NV4_USER_DAC_READ_MODE_ADDRESS 0x6813C7 -#define NV4_USER_DAC_READ_MODE_ADDRESS_VALUE 0 -#define NV4_USER_DAC_READ_MODE_ADDRESS_WO_VALUE 0 -#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE 0 -#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE_WRITE 0x0 -#define NV4_USER_DAC_READ_MODE_ADDRESS_RW_STATE_READ 0x3 -#define NV4_USER_DAC_WRITE_MODE_ADDRESS 0x6813C8 -#define NV4_USER_DAC_WRITE_MODE_ADDRESS_VALUE 0 -#define NV4_USER_DAC_PALETTE_DATA 0x6813C9 -#define NV4_USER_DAC_PALETTE_DATA_VALUE 0 - -#define NV4_PRMDIO_START 0x681000 -#define NV4_PRMDIO_END 0x681FFF - -#define NV4_IO_MPU_401_DATA 0x330 -#define NV4_IO_MPU_401_DATA_ALIAS_1 0x300 -#define NV4_IO_MPU_401_DATA_ALIAS_2 0x230 -#define NV4_IO_MPU_401_DATA_VALUE 0 -#define NV4_IO_MPU_401_DATA_ACK 0xFE -#define NV4_IO_MPU_401_STATUS 0x331 -#define NV4_IO_MPU_401_STATUS_ALIAS_1 0x301 -#define NV4_IO_MPU_401_STATUS_ALIAS_2 0x231 -#define NV4_IO_MPU_401_STATUS_DATA 0 -#define NV4_IO_MPU_401_STATUS_WRITE 6 -#define NV4_IO_MPU_401_STATUS_WRITE_EMPTY 0x0 -#define NV4_IO_MPU_401_STATUS_WRITE_FULL 0x1 -#define NV4_IO_MPU_401_STATUS_READ 7 -#define NV4_IO_MPU_401_STATUS_READ_FULL 0x0 -#define NV4_IO_MPU_401_STATUS_READ_EMPTY 0x1 -#define NV4_IO_MPU_401_COM 0x331 -#define NV4_IO_MPU_401_COM_ALIAS_1 0x301 -#define NV4_IO_MPU_401_COM_ALIAS_2 0x231 -#define NV4_IO_MPU_401_COM_UART_MODE 0 -#define NV4_IO_MPU_401_COM_UART_MODE_COMPLEX 0xff -#define NV4_IO_MPU_401_COM_UART_MODE_SIMPLE 0x3f - -#define NV4_PMC_START 0x0 -#define NV4_PMC_END 0xFFF - -#define NV4_PMC_BOOT_0 0x0 -#define NV4_PMC_BOOT_0_MINOR_REVISION 0 -#define NV4_PMC_BOOT_0_MINOR_REVISION_0 0x0 -#define NV4_PMC_BOOT_0_MAJOR_REVISION 4 -#define NV4_PMC_BOOT_0_MAJOR_REVISION_A 0x0 -#define NV4_PMC_BOOT_0_MAJOR_REVISION_B 0x1 -#define NV4_PMC_BOOT_0_IMPLEMENTATION 8 -#define NV4_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x0 -#define NV4_PMC_BOOT_0_ARCHITECTURE 12 -#define NV4_PMC_BOOT_0_ARCHITECTURE_NV0 0x0 -#define NV4_PMC_BOOT_0_ARCHITECTURE_NV1 0x1 -#define NV4_PMC_BOOT_0_ARCHITECTURE_NV2 0x2 -#define NV4_PMC_BOOT_0_ARCHITECTURE_NV3 0x3 -#define NV4_PMC_BOOT_0_ARCHITECTURE_NV4 0x4 -#define NV4_PMC_BOOT_0_FIB_REVISION 16 -#define NV4_PMC_BOOT_0_FIB_REVISION_0 0x0 -#define NV4_PMC_BOOT_0_MASK_REVISION 20 -#define NV4_PMC_BOOT_0_MASK_REVISION_A 0x0 -#define NV4_PMC_BOOT_0_MASK_REVISION_B 0x1 -#define NV4_PMC_BOOT_0_MASK_REVISION_C 0x2 -#define NV4_PMC_BOOT_0_MANUFACTURER 24 -#define NV4_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x0 -#define NV4_PMC_BOOT_0_FOUNDRY 28 -#define NV4_PMC_BOOT_0_FOUNDRY_SGS 0x0 -#define NV4_PMC_BOOT_0_FOUNDRY_HELIOS 0x1 -#define NV4_PMC_BOOT_0_FOUNDRY_TSMC 0x2 -#define NV4_PMC_INTR_0 0x100 -#define NV4_PMC_INTR_0_PMEDIA 4 -#define NV4_PMC_INTR_0_PMEDIA_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PMEDIA_PENDING 0x1 -#define NV4_PMC_INTR_0_PFIFO 8 -#define NV4_PMC_INTR_0_PFIFO_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PFIFO_PENDING 0x1 -#define NV4_PMC_INTR_0_PGRAPH 12 -#define NV4_PMC_INTR_0_PGRAPH_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PGRAPH_PENDING 0x1 -#define NV4_PMC_INTR_0_PVIDEO 16 -#define NV4_PMC_INTR_0_PVIDEO_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PVIDEO_PENDING 0x1 -#define NV4_PMC_INTR_0_PTIMER 20 -#define NV4_PMC_INTR_0_PTIMER_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PTIMER_PENDING 0x1 -#define NV4_PMC_INTR_0_PCRTC 24 -#define NV4_PMC_INTR_0_PCRTC_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PCRTC_PENDING 0x1 -#define NV4_PMC_INTR_0_PBUS 28 -#define NV4_PMC_INTR_0_PBUS_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_PBUS_PENDING 0x1 -#define NV4_PMC_INTR_0_SOFTWARE 31 -#define NV4_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x0 -#define NV4_PMC_INTR_0_SOFTWARE_PENDING 0x1 -#define NV4_PMC_INTR_EN_0 0x140 -#define NV4_PMC_INTR_EN_0_INTA 0 -#define NV4_PMC_INTR_EN_0_INTA_DISABLED 0x0 -#define NV4_PMC_INTR_EN_0_INTA_HARDWARE 0x1 -#define NV4_PMC_INTR_EN_0_INTA_SOFTWARE 0x2 -#define NV4_PMC_INTR_READ_0 0x160 -#define NV4_PMC_INTR_READ_0_INTA 0 -#define NV4_PMC_INTR_READ_0_INTA_LOW 0x0 -#define NV4_PMC_INTR_READ_0_INTA_HIGH 0x1 -#define NV4_PMC_ENABLE 0x200 -#define NV4_PMC_ENABLE_PMEDIA 4 -#define NV4_PMC_ENABLE_PMEDIA_ENABLED 0x1 -#define NV4_PMC_ENABLE_PFIFO 8 -#define NV4_PMC_ENABLE_PFIFO_ENABLED 0x1 -#define NV4_PMC_ENABLE_PGRAPH 12 -#define NV4_PMC_ENABLE_PGRAPH_ENABLED 0x1 -#define NV4_PMC_ENABLE_PPMI 16 -#define NV4_PMC_ENABLE_PPMI_ENABLED 0x1 -#define NV4_PMC_ENABLE_PFB 20 -#define NV4_PMC_ENABLE_PFB_ENABLED 0x1 -#define NV4_PMC_ENABLE_PCRTC 24 -#define NV4_PMC_ENABLE_PCRTC_ENABLED 0x1 -#define NV4_PMC_ENABLE_PVIDEO 28 -#define NV4_PMC_ENABLE_PVIDEO_ENABLED 0x1 - -#define NV4_PBUS_START 0x1000 -#define NV4_PBUS_END 0x1FFF - -#define NV4_PBUS_DEBUG_0 0x1080 -#define NV4_PBUS_DEBUG_0_FBIO_SCLK_DELAY 0 -#define NV4_PBUS_DEBUG_0_FBIO_SCLK_DELAY_8 0x8 -#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC 4 -#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC_NORMAL 0x0 -#define NV4_PBUS_DEBUG_0_FBIO_SCLK_PC_OVERRIDE 0x1 -#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_DELAY 8 -#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_DELAY_8 0x8 -#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC 12 -#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC_NORMAL 0x0 -#define NV4_PBUS_DEBUG_0_FBIO_FBCLK_PC_OVERRIDE 0x1 -#define NV4_PBUS_DEBUG_0_FBIO_ACLK_DELAY 16 -#define NV4_PBUS_DEBUG_0_FBIO_ACLK_DELAY_8 0x8 -#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC 20 -#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC_NORMAL 0x0 -#define NV4_PBUS_DEBUG_0_FBIO_ACLK_PC_OVERRIDE 0x1 -#define NV4_PBUS_DEBUG_0_FBIO_RCLK_DELAY 24 -#define NV4_PBUS_DEBUG_0_FBIO_RCLK_DELAY_8 0x8 -#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC 28 -#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC_NORMAL 0x0 -#define NV4_PBUS_DEBUG_0_FBIO_RCLK_PC_OVERRIDE 0x1 -#define NV4_PBUS_DEBUG_1 0x1084 -#define NV4_PBUS_DEBUG_1_PCIM_THROTTLE 0 -#define NV4_PBUS_DEBUG_1_PCIM_THROTTLE_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_PCIM_CMD 1 -#define NV4_PBUS_DEBUG_1_PCIM_CMD_SIZE_BASED 0x0 -#define NV4_PBUS_DEBUG_1_PCIM_CMD_MRL_ONLY 0x1 -#define NV4_PBUS_DEBUG_1_HASH_DECODE 2 -#define NV4_PBUS_DEBUG_1_HASH_DECODE_1FF 0x0 -#define NV4_PBUS_DEBUG_1_HASH_DECODE_2FF 0x1 -#define NV4_PBUS_DEBUG_1_AGPM_CMD 3 -#define NV4_PBUS_DEBUG_1_AGPM_CMD_HP_ON_1ST 0x0 -#define NV4_PBUS_DEBUG_1_AGPM_CMD_LP_ONLY 0x1 -#define NV4_PBUS_DEBUG_1_AGPM_CMD_HP_ONLY 0x2 -#define NV4_PBUS_DEBUG_1_PCIS_WRITE 5 -#define NV4_PBUS_DEBUG_1_PCIS_WRITE_0_CYCLE 0x0 -#define NV4_PBUS_DEBUG_1_PCIS_WRITE_1_CYCLE 0x1 -#define NV4_PBUS_DEBUG_1_PCIS_2_1 6 -#define NV4_PBUS_DEBUG_1_PCIS_2_1_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_PCIS_RETRY 7 -#define NV4_PBUS_DEBUG_1_PCIS_RETRY_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_PCIS_RD_BURST 8 -#define NV4_PBUS_DEBUG_1_PCIS_RD_BURST_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_PCIS_WR_BURST 9 -#define NV4_PBUS_DEBUG_1_PCIS_WR_BURST_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_PCIS_EARLY_RTY 10 -#define NV4_PBUS_DEBUG_1_PCIS_EARLY_RTY_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_PCIS_CPUQ 12 -#define NV4_PBUS_DEBUG_1_PCIS_CPUQ_ENABLED 0x1 -#define NV4_PBUS_DEBUG_1_DPSH_DECODE 13 -#define NV4_PBUS_DEBUG_1_DPSH_DECODE_NV4 0x0 -#define NV4_PBUS_DEBUG_1_DPSH_DECODE_NV3 0x1 -#define NV4_PBUS_DEBUG_1_SPARE1 14 -#define NV4_PBUS_DEBUG_1_SPARE2 15 -#define NV4_PBUS_DEBUG_1_SPARE3 16 -#define NV4_PBUS_DEBUG_1_SPARE4 17 -#define NV4_PBUS_DEBUG_1_SPARE5 18 -#define NV4_PBUS_DEBUG_1_SPARE6 19 -#define NV4_PBUS_DEBUG_1_SPARE7 20 -#define NV4_PBUS_DEBUG_1_SPARE8 21 -#define NV4_PBUS_DEBUG_1_SPARE9 22 -#define NV4_PBUS_DEBUG_1_SPARE10 23 -#define NV4_PBUS_DEBUG_2 0x1088 -#define NV4_PBUS_DEBUG_2_AGP_DIFFERENTIAL 0 -#define NV4_PBUS_DEBUG_2_AGP_DIFFERENTIAL_ENABLED 0x1 -#define NV4_PBUS_DEBUG_2_AGP_SB_STB_DELAY 9:4 -#define NV4_PBUS_DEBUG_2_AGP_SB_STB_DELAY_34 0x22 -#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC 12 -#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC_NORMAL 0x0 -#define NV4_PBUS_DEBUG_2_AGP_SB_STB_PC_OVERRIDE 0x1 -#define NV4_PBUS_DEBUG_3 0x108C -#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE 0 -#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_UNLIMITED 0x0 -#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_32_BYTES 0x1 -#define NV4_PBUS_DEBUG_3_AGP_MAX_SIZE_64_BYTES 0x2 -#define NV4_PBUS_DEBUG_CTL 0x1090 -#define NV4_PBUS_DEBUG_CTL_MODE 0 -#define NV4_PBUS_DEBUG_CTL_MODE_ENABLED 0x1 -#define NV4_PBUS_DEBUG_CTL_READ_SELECT 4 -#define NV4_PBUS_DEBUG_CTL_READ_SELECT_0 0x0 -#define NV4_PBUS_DEBUG_CTL_READ_SELECT_1 0x1 -#define NV4_PBUS_DEBUG_READ 0x1094 -#define NV4_PBUS_DEBUG_READ_DATA 0 -#define NV4_PBUS_DEBUG_HOST 0x109C -#define NV4_PBUS_DEBUG_HOST_SEL 0 -#define NV4_PBUS_DEBUG_SEL_0 0x10A0 -#define NV4_PBUS_DEBUG_SEL_0_X 0 -#define NV4_PBUS_DEBUG_SEL_1 0x10A4 -#define NV4_PBUS_DEBUG_SEL_1_X 0 -#define NV4_PBUS_DEBUG_SEL_2 0x10A8 -#define NV4_PBUS_DEBUG_SEL_2_X 0 -#define NV4_PBUS_DEBUG_SEL_3 0x10AC -#define NV4_PBUS_DEBUG_SEL_3_X 0 -#define NV4_PBUS_INTR_0 0x1100 -#define NV4_PBUS_INTR_0_PCI_BUS_ERROR 0 -#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_NOT_PENDING 0x0 -#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_PENDING 0x1 -#define NV4_PBUS_INTR_0_PCI_BUS_ERROR_RESET 0x1 -#define NV4_PBUS_INTR_EN_0 0x1140 -#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR 0 -#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR_ENABLED 0x1 -#define NV4_PBUS_ROM_CONFIG 0x1200 -#define NV4_PBUS_ROM_CONFIG_TW1 0 -#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF -#define NV4_PBUS_ROM_CONFIG_TW0 4 -#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3 - -// 86Box uses 8-bit PCI registers so this section was rewritten -#define NV4_PBUS_PCI_VENDOR_ID 0x1800 -#define NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA 0x10DE -#define NV4_PBUS_PCI_DEVICE_ID 0x1802 -#define NV4_PBUS_PCI_DEVICE_ID_NV4 0x0020 // Chip (19:17)= NV4, Func = VGA -#define NV4_PBUS_PCI_COMMAND 0x1804 -#define NV4_PBUS_PCI_COMMAND_H 0x1805 -#define NV4_PBUS_PCI_COMMAND_IO_SPACE 0 -#define NV4_PBUS_PCI_COMMAND_IO_SPACE_ENABLED 0x1 -#define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE 1 -#define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE_ENABLED 0x1 -#define NV4_PBUS_PCI_COMMAND_BUS_MASTER 2 -#define NV4_PBUS_PCI_COMMAND_BUS_MASTER_ENABLED 0x1 -#define NV4_PBUS_PCI_COMMAND_WRITE_AND_INVAL 4 -#define NV4_PBUS_PCI_COMMAND_WRITE_AND_INVAL_ENABLED 0x1 -#define NV4_PBUS_PCI_COMMAND_PALETTE_SNOOP 5 -#define NV4_PBUS_PCI_COMMAND_PALETTE_SNOOP_ENABLED 0x1 -#define NV4_PBUS_PCI_STATUS 0x1806 -#define NV4_PBUS_PCI_STATUS_CAPLIST 4 -#define NV4_PBUS_PCI_STATUS_CAPLIST_NOT_PRESENT 0x0 -#define NV4_PBUS_PCI_STATUS_CAPLIST_PRESENT 0x1 -#define NV4_PBUS_PCI_STATUS_66MHZ 5 -#define NV4_PBUS_PCI_STATUS_66MHZ_INCAPABLE 0x0 -#define NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE 0x1 -#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK 7 -#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK_INCAPABLE 0x0 -#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK_CAPABLE 0x1 -#define NV4_PBUS_PCI_STATUS_2 0x1807 -#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING 1 -#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST 0x0 -#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_MEDIUM 0x1 -#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_SLOW 0x2 -#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET 3 -#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_NO_ABORT 0x0 -#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_ABORT 0x1 -#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_CLEAR 0x1 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET 4 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_NO_ABORT 0x0 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_ABORT 0x1 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_CLEAR 0x1 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER 5 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_NO_ABORT 0x0 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_ABORT 0x1 -#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_CLEAR 0x1 -#define NV4_PBUS_PCI_REVISION_ID 0x1808 -#define NV4_PBUS_PCI_REVISION_ID_A01 0x0 -#define NV4_PBUS_PCI_REVISION_ID_B01 0x1 -#define NV4_PBUS_PCI_CLASS_CODE 0x180B -#define NV4_PBUS_PCI_CLASS_CODE_VGA 0x30000 -#define NV4_PBUS_PCI_LATENCY_TIMER 0x180D -// Shift left by 3 to get the real value in clocks. 0x0 = 0, 0x1 = 8, 0x1E = 240, 0x1F = 248 are values used. -#define NV4_PBUS_PCI_LATENCY_TIMER_VALUE 3 -// 0x0 = single function (only value that matters) -#define NV4_PBUS_PCI_HEADER_TYPE 0x180E -#define NV4_PBUS_PCI_BAR_SPACE_TYPE 0 -#define NV4_PBUS_PCI_BAR_SPACE_TYPE_MEMORY 0x0 -#define NV4_PBUS_PCI_BAR_SPACE_TYPE_IO 0x1 -#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE 1 -#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_32_BIT 0x0 -#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_20_BIT 0x1 -#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_64_BIT 0x2 -#define NV4_PBUS_PCI_BAR_PREFETCHABLE 3 -#define NV4_PBUS_PCI_BAR_PREFETCHABLE_NOT 0x0 -#define NV4_PBUS_PCI_BAR_PREFETCHABLE_MERGABLE 0x1 -// Bits 23:4 are resedrved -#define NV4_PBUS_PCI_BAR0_INFO 0x1810 -#define NV4_PBUS_PCI_BAR0_UNUSED1 0x1811 -#define NV4_PBUS_PCI_BAR0_UNUSED2 0x1812 -#define NV4_PBUS_PCI_BAR0_BASE_31_TO_24 0x1813 // Must align to 16MByte -#define NV4_PBUS_PCI_BAR1_INFO 0x1814 -#define NV4_PBUS_PCI_BAR1_UNUSED1 0x1815 -#define NV4_PBUS_PCI_BAR1_UNUSED2 0x1816 -#define NV4_PBUS_PCI_BAR1_BASE_31_TO_24 0x1817 // Must align to 16MByte -#define NV4_PBUS_PCI_BAR_RESERVED_START 0x1818 -#define NV4_PBUS_PCI_BAR_RESERVED_END 0x182B - -//BAR2-5 reserved -#define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID 0x182C -#define NV4_PBUS_PCI_SUBSYSTEM_ID 0x182E -#define NV4_PBUS_PCI_ROM 0x1830 -#define NV4_PBUS_PCI_ROM_DECODE 0 -#define NV4_PBUS_PCI_ROM_DECODE_ENABLED 0x1 -#define NV4_PBUS_PCI_ROM_BASE 0x1832 -#define NV4_PBUS_PCI_NEXT_PTR 0x1834 -#define NV4_PBUS_PCI_CAP_PTR_AGP 0x44 -#define NV4_PBUS_PCI_CAP_PTR_POWER_MGMT 0x60 -// 0xFF = unknown, otherwise 0x0-0xF = IRQ0-15 -#define NV4_PBUS_PCI_INTR_LINE 0x183C -#define NV4_PBUS_PCI_INTR_LINE_IRQ_NUM 0 -#define NV4_PBUS_PCI_INTR_LINE_IRQ_NUM_UNKNOWN 0xFF -#define NV4_PBUS_PCI_INTR_PIN 0x183D -#define NV4_PBUS_PCI_INTR_PIN_INTA 0x1 -#define NV4_PBUS_PCI_MIN_GNT 0x183E -#define NV4_PBUS_PCI_MIN_GNT_NO_REQUIREMENTS 0x0 -#define NV4_PBUS_PCI_MIN_GNT_750NS 0x3 -#define NV4_PBUS_PCI_MIN_GNT_1250NS 0x5 -#define NV4_PBUS_PCI_MAX_LAT 0x183F -#define NV4_PBUS_PCI_MAX_LAT_NO_REQUIREMENTS 0x0 -#define NV4_PBUS_PCI_MAX_LAT_250NS 0x1 -#define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE 0x1840 -#define NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE 0x1842 -#define NV4_PBUS_AGP 0x44 -#define NV4_PBUS_AGP_CAPABILITIES 0x1844 -#define NV4_PBUS_AGP_CAPABILITY_AGP 0x2 -// Should be null! - -#define NV4_PBUS_AGP_NEXT_PTR 0x1845 -#define NV4_PBUS_AGP_REV 0x1846 -#define NV4_PBUS_AGP_REV_MINOR 0 -#define NV4_PBUS_AGP_REV_MINOR_0 0x0 -#define NV4_PBUS_AGP_REV_MAJOR 4 -#define NV4_PBUS_AGP_REV_MAJOR_1 0x1 -#define NV4_PBUS_AGP_STATUS_RATE 0x1848 -#define NV4_PBUS_AGP_STATUS_RATE_1X 0x1 -#define NV4_PBUS_AGP_STATUS_RATE_2X 0x2 -#define NV4_PBUS_AGP_STATUS_RATE_1X_AND_2X 0x3 -#define NV4_PBUS_AGP_STATUS_RQ 0x184B -#define NV4_PBUS_AGP_STATUS_RQ_16 0xF -#define NV4_PBUS_AGP_STATUS_SBA 0x1849 -#define NV4_PBUS_AGP_STATUS_SBA_STATUS 1 -#define NV4_PBUS_AGP_STATUS_SBA_STATUS_NONE 0x0 -#define NV4_PBUS_AGP_STATUS_SBA_STATUS_CAPABLE 0x1 -#define NV4_PBUS_AGP_COMMAND 0x184C -#define NV4_PBUS_AGP_COMMAND_DATA_RATE 0 -#define NV4_PBUS_AGP_COMMAND_DATA_RATE_OFF 0x0 -#define NV4_PBUS_AGP_COMMAND_DATA_RATE_1X 0x1 -#define NV4_PBUS_AGP_COMMAND_DATA_RATE_2X 0x2 -#define NV4_PBUS_AGP_COMMAND_2 0x184D -#define NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED 0 // 1 = enabled, 0 = disabled -#define NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED 1 // 1 = enabled, 0 = disabled -#define NV4_PBUS_AGP_COMMAND_RQ_DEPTH 0x184F //DEFAUlt 0 -#define NV4_PBUS_PCI_ROM_SHADOW 0x1850 -#define NV4_PBUS_PCI_ROM_SHADOW_IS_ENABLED 0 // 1 = enabled, 0 = disabled -#define NV4_PBUS_PCI_VGA 0x1854 -#define NV4_PBUS_PCI_VGA_IS_ENABLED 0 // 1 = enabled, 0 = disabled -#define NV4_PBUS_PCI_SCRATCH 0x1858 -#define NV4_PBUS_PCI_SCRATCH_DEFAULT 0x23D6CE -#define NV4_PBUS_PCI_DT 0x185C -#define NV4_PBUS_PCI_DT_TIMEOUT 0 -#define NV4_PBUS_PCI_DT_TIMEOUT_16 0xF -//TODO: Implement -#define NV4_PBUS_PCIPOWER 0x1860 -#define NV4_PBUS_PCIPOWER_CAP_ID 0 -#define NV4_PBUS_PCIPOWER_CAP_ID_POWER_MGMT 0x1 -#define NV4_PBUS_PCIPOWER_NEXT_PTR 0x1861 // should be 0x44=AGP -#define NV4_PBUS_PCIPOWER_2 0x1862 -#define NV4_PBUS_PCIPOWER_2_VERSION 0 -#define NV4_PBUS_PCIPOWER_2_VERSION_1 0x1 -#define NV4_PBUS_PCIPOWER_2_CLOCK 3 -#define NV4_PBUS_PCIPOWER_2_CLOCK_NOT_REQUIRED 0x0 -#define NV4_PBUS_PCIPOWER_2_DSI 5 -#define NV4_PBUS_PCIPOWER_2_DSI_NOT_REQUIRED 0x0 -#define NV4_PBUS_PCIPOWER_SUPPORTED_STATES 0x1863 -#define NV4_PBUS_PCIPOWER_D1 1 -#define NV4_PBUS_PCIPOWER_D1_SUPPORTED 0x1 // 1 = supported -#define NV4_PBUS_PCIPOWER_D2 2 -#define NV4_PBUS_PCIPOWER_D2_SUPPORTED 0x1 // 0 = not supported -#define NV4_PBUS_PCIPOWER_PME_D0 3 -#define NV4_PBUS_PCIPOWER_PME_D0_SUPPORTED 0x1 -#define NV4_PBUS_PCIPOWER_PME_D1 4 -#define NV4_PBUS_PCIPOWER_PME_D1_SUPPORTED 0x1 -#define NV4_PBUS_PCIPOWER_PME_D2 5 -#define NV4_PBUS_PCIPOWER_PME_D2_SUPPORTED 0x1 -#define NV4_PBUS_PCIPOWER_PME_D3_HOT 6 -#define NV4_PBUS_PCIPOWER_PME_D3_HOT_SUPPORTED 0x1 -#define NV4_PBUS_PCIPOWER_PME_D3_COLD 7 -#define NV4_PBUS_PCIPOWER_PME_D3_COLD_SUPPORTED 0x1 -#define NV4_PBUS_PCIPOWER_STATE_CURRENT 0x1864 -#define NV4_PBUS_PCIPOWER_STATE 0 -#define NV4_PBUS_PCIPOWER_STATE_D3_HOT 0x3 -#define NV4_PBUS_PCIPOWER_STATE_D2 0x2 -#define NV4_PBUS_PCIPOWER_STATE_D1 0x1 -#define NV4_PBUS_PCIPOWER_STATE_D0 0x0 -#define NV4_PFIFO_START 0x2000 -#define NV4_PFIFO_END 0x3FFF -#define NV4_PFIFO_DELAY_0 0x2040 -#define NV4_PFIFO_DELAY_0_WAIT_RETRY 0 -#define NV4_PFIFO_DELAY_0_WAIT_RETRY_0 0x0 -#define NV4_PFIFO_DMA_TIMESLICE 0x2044 -#define NV4_PFIFO_DMA_TIMESLICE_SELECT 0 -#define NV4_PFIFO_DMA_TIMESLICE_SELECT_1 0x0 -#define NV4_PFIFO_DMA_TIMESLICE_SELECT_16K 0x3fff -#define NV4_PFIFO_DMA_TIMESLICE_SELECT_32K 0x7fff -#define NV4_PFIFO_DMA_TIMESLICE_SELECT_64K 0xffff -#define NV4_PFIFO_DMA_TIMESLICE_SELECT_128K 0x1ffff -#define NV4_PFIFO_DMA_TIMESLICE_TIMEOUT 24 -#define NV4_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x1 -#define NV4_PFIFO_PIO_TIMESLICE 0x2048 -#define NV4_PFIFO_PIO_TIMESLICE_SELECT 0 -#define NV4_PFIFO_PIO_TIMESLICE_SELECT_1 0x0 -#define NV4_PFIFO_PIO_TIMESLICE_SELECT_16K 0x3fff -#define NV4_PFIFO_PIO_TIMESLICE_SELECT_32K 0x7fff -#define NV4_PFIFO_PIO_TIMESLICE_SELECT_64K 0xffff -#define NV4_PFIFO_PIO_TIMESLICE_SELECT_128K 0x1ffff -#define NV4_PFIFO_PIO_TIMESLICE_TIMEOUT 24 -#define NV4_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x1 -#define NV4_PFIFO_TIMESLICE 0x204C -#define NV4_PFIFO_TIMESLICE_TIMER 0 -#define NV4_PFIFO_TIMESLICE_TIMER_EXPIRED 0x3FFFF -#define NV4_PFIFO_NEXT_CHANNEL 0x2050 -#define NV4_PFIFO_NEXT_CHANNEL_CHID 0 -#define NV4_PFIFO_NEXT_CHANNEL_MODE 8 -#define NV4_PFIFO_NEXT_CHANNEL_MODE_PIO 0x0 -#define NV4_PFIFO_NEXT_CHANNEL_MODE_DMA 0x1 -#define NV4_PFIFO_NEXT_CHANNEL_SWITCH 12 -#define NV4_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x0 -#define NV4_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x1 -#define NV4_PFIFO_DEBUG_0 0x2080 -#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0 0 -#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x0 -#define NV4_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x1 -#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1 4 -#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x0 -#define NV4_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x1 -#define NV4_PFIFO_INTR_0 0x2100 -#define NV4_PFIFO_INTR_0_CACHE_ERROR 0 -#define NV4_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x0 -#define NV4_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x1 -#define NV4_PFIFO_INTR_0_CACHE_ERROR_RESET 0x1 -#define NV4_PFIFO_INTR_0_RUNOUT 4 -#define NV4_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x0 -#define NV4_PFIFO_INTR_0_RUNOUT_PENDING 0x1 -#define NV4_PFIFO_INTR_0_RUNOUT_RESET 0x1 -#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW 8 -#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x0 -#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x1 -#define NV4_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x1 -#define NV4_PFIFO_INTR_0_DMA_PUSHER 12 -#define NV4_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x0 -#define NV4_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x1 -#define NV4_PFIFO_INTR_0_DMA_PUSHER_RESET 0x1 -#define NV4_PFIFO_INTR_0_DMA_PT 16 -#define NV4_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x0 -#define NV4_PFIFO_INTR_0_DMA_PT_PENDING 0x1 -#define NV4_PFIFO_INTR_0_DMA_PT_RESET 0x1 -#define NV4_PFIFO_INTR_EN_0 0x2140 -#define NV4_PFIFO_INTR_EN_0_CACHE_ERROR 0 -#define NV4_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x1 -#define NV4_PFIFO_INTR_EN_0_RUNOUT 4 -#define NV4_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x1 -#define NV4_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8 -#define NV4_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x1 -#define NV4_PFIFO_INTR_EN_0_DMA_PUSHER 12 -#define NV4_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x1 -#define NV4_PFIFO_INTR_EN_0_DMA_PT 16 -#define NV4_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x1 -#define NV4_PFIFO_RAMHT 0x2210 -#define NV4_PFIFO_RAMHT_BASE_ADDRESS 4 -#define NV4_PFIFO_RAMHT_BASE_ADDRESS_10000 0x10 -#define NV4_PFIFO_RAMHT_SIZE 16 -#define NV4_PFIFO_RAMHT_SIZE_4K 0x0 -#define NV4_PFIFO_RAMHT_SIZE_8K 0x1 -#define NV4_PFIFO_RAMHT_SIZE_16K 0x2 -#define NV4_PFIFO_RAMHT_SIZE_32K 0x3 -#define NV4_PFIFO_RAMHT_SEARCH 24 -#define NV4_PFIFO_RAMHT_SEARCH_16 0x0 -#define NV4_PFIFO_RAMHT_SEARCH_32 0x1 -#define NV4_PFIFO_RAMHT_SEARCH_64 0x2 -#define NV4_PFIFO_RAMHT_SEARCH_128 0x3 -#define NV4_PFIFO_RAMFC 0x2214 -#define NV4_PFIFO_RAMFC_BASE_ADDRESS 1 -#define NV4_PFIFO_RAMFC_BASE_ADDRESS_11000 0x88 -#define NV4_PFIFO_RAMRO 0x2218 -#define NV4_PFIFO_RAMRO_BASE_ADDRESS 1 -#define NV4_PFIFO_RAMRO_BASE_ADDRESS_11200 0x89 -#define NV4_PFIFO_RAMRO_BASE_ADDRESS_12000 0x90 -#define NV4_PFIFO_RAMRO_SIZE 16 -#define NV4_PFIFO_RAMRO_SIZE_512 0x0 -#define NV4_PFIFO_RAMRO_SIZE_8K 0x1 -#define NV4_PFIFO_CACHES 0x2500 -#define NV4_PFIFO_CACHES_REASSIGN 0 -#define NV4_PFIFO_CACHES_REASSIGN_ENABLED 0x1 -#define NV4_PFIFO_CACHES_DMA_SUSPEND 4 -#define NV4_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x0 -#define NV4_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x1 -#define NV4_PFIFO_MODE 0x2504 -// Valid for all 16 channels. Do we need thees at all? -#define NV4_PFIFO_MODE_CHANNEL_IS_PIO 0x0 -#define NV4_PFIFO_MODE_CHANNEL_IS_DMA 0x1 -#define NV4_PFIFO_MODE_CHANNEL_0 0 -#define NV4_PFIFO_MODE_CHANNEL_1 1 -#define NV4_PFIFO_MODE_CHANNEL_2 2 -#define NV4_PFIFO_MODE_CHANNEL_3 3 -#define NV4_PFIFO_MODE_CHANNEL_4 4 -#define NV4_PFIFO_MODE_CHANNEL_5 5 -#define NV4_PFIFO_MODE_CHANNEL_6 6 -#define NV4_PFIFO_MODE_CHANNEL_7 7 -#define NV4_PFIFO_MODE_CHANNEL_8 8 -#define NV4_PFIFO_MODE_CHANNEL_9 9 -#define NV4_PFIFO_MODE_CHANNEL_10 10 -#define NV4_PFIFO_MODE_CHANNEL_11 11 -#define NV4_PFIFO_MODE_CHANNEL_12 12 -#define NV4_PFIFO_MODE_CHANNEL_13 13 -#define NV4_PFIFO_MODE_CHANNEL_14 14 -#define NV4_PFIFO_MODE_CHANNEL_15 15 -#define NV4_PFIFO_DMA 0x2508 -// 0 = not pending (Valid for all channels) -#define NV4_PFIFO_DMA_CHANNEL_IS_PENDING 0x1 -#define NV4_PFIFO_DMA_CHANNEL_0 0 -#define NV4_PFIFO_DMA_CHANNEL_1 1 -#define NV4_PFIFO_DMA_CHANNEL_2 2 -#define NV4_PFIFO_DMA_CHANNEL_3 3 -#define NV4_PFIFO_DMA_CHANNEL_4 4 -#define NV4_PFIFO_DMA_CHANNEL_5 5 -#define NV4_PFIFO_DMA_CHANNEL_6 6 -#define NV4_PFIFO_DMA_CHANNEL_7 7 -#define NV4_PFIFO_DMA_CHANNEL_8 8 -#define NV4_PFIFO_DMA_CHANNEL_9 9 -#define NV4_PFIFO_DMA_CHANNEL_10 10 -#define NV4_PFIFO_DMA_CHANNEL_11 11 -#define NV4_PFIFO_DMA_CHANNEL_12 12 -#define NV4_PFIFO_DMA_CHANNEL_13 13 -#define NV4_PFIFO_DMA_CHANNEL_14 14 -#define NV4_PFIFO_DMA_CHANNEL_15 15 -#define NV4_PFIFO_SIZE 0x250C -// Valid for all channels -#define NV4_PFIFO_SIZE_CHANNEL_SIZE_IS_124_BYTES 0x0 -#define NV4_PFIFO_SIZE_CHANNEL_SIZE_IS_512_BYTES 0x1 -#define NV4_PFIFO_SIZE_CHANNEL_0 0 -#define NV4_PFIFO_SIZE_CHANNEL_1 1 -#define NV4_PFIFO_SIZE_CHANNEL_2 2 -#define NV4_PFIFO_SIZE_CHANNEL_3 3 -#define NV4_PFIFO_SIZE_CHANNEL_4 4 -#define NV4_PFIFO_SIZE_CHANNEL_5 5 -#define NV4_PFIFO_SIZE_CHANNEL_6 6 -#define NV4_PFIFO_SIZE_CHANNEL_7 7 -#define NV4_PFIFO_SIZE_CHANNEL_8 8 -#define NV4_PFIFO_SIZE_CHANNEL_9 9 -#define NV4_PFIFO_SIZE_CHANNEL_10 10 -#define NV4_PFIFO_SIZE_CHANNEL_11 11 -#define NV4_PFIFO_SIZE_CHANNEL_12 12 -#define NV4_PFIFO_SIZE_CHANNEL_13 13 -#define NV4_PFIFO_SIZE_CHANNEL_14 14 -#define NV4_PFIFO_SIZE_CHANNEL_15 15 -#define NV4_PFIFO_CACHE0_PUSH0 0x3000 -#define NV4_PFIFO_CACHE0_PUSH0_ACCESS 0 -#define NV4_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x1 -#define NV4_PFIFO_CACHE1_PUSH0 0x3200 -#define NV4_PFIFO_CACHE1_PUSH0_ACCESS 0 -#define NV4_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x1 -#define NV4_PFIFO_CACHE0_PUSH1 0x3004 -#define NV4_PFIFO_CACHE0_PUSH1_CHID 0 -#define NV4_PFIFO_CACHE1_PUSH1 0x3204 -#define NV4_PFIFO_CACHE1_PUSH1_CHID 0 -#define NV4_PFIFO_CACHE1_PUSH1_MODE 8 -#define NV4_PFIFO_CACHE1_PUSH1_MODE_PIO 0x0 -#define NV4_PFIFO_CACHE1_PUSH1_MODE_DMA 0x1 -#define NV4_PFIFO_CACHE1_DMA_PUSH 0x3220 -#define NV4_PFIFO_CACHE1_DMA_PUSH_ACCESS 0 -#define NV4_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x1 -#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE 4 -#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x0 -#define NV4_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x1 -#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER 8 -#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x0 -#define NV4_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x1 -#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS 12 -#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x0 -#define NV4_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x1 -#define NV4_PFIFO_CACHE1_DMA_FETCH 0x3224 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x0 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x1 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x2 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x3 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x4 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x5 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x6 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x7 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x8 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x9 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0xA -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0xB -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0xC -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0xD -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0xE -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0xF -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x10 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x11 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x12 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x13 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x14 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x15 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x16 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x17 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x18 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x19 -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x1A -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x1B -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x1C -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x1D -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x1E -#define NV4_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x1F -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE 13 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x0 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x1 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x2 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x3 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x4 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x5 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x6 -#define NV4_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x7 -// This is a count. 0x0-0xF = number of requests -#define NV4_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 16 -#define NV4_PFIFO_CACHE1_DMA_PUT 0x3240 -#define NV4_PFIFO_CACHE1_DMA_PUT_OFFSET 2 -#define NV4_PFIFO_CACHE1_DMA_GET 0x3244 -#define NV4_PFIFO_CACHE1_DMA_GET_OFFSET 2 -#define NV4_PFIFO_CACHE1_DMA_DCOUNT 0x32A0 -#define NV4_PFIFO_CACHE1_DMA_DCOUNT_VALUE 2 -#define NV4_PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x32A4 -#define NV4_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET 2 -#define NV4_PFIFO_CACHE1_DMA_RSVD_SHADOW 0x32A8 -#define NV4_PFIFO_CACHE1_DMA_RSVD_SHADOW_CMD 0 -#define NV4_PFIFO_CACHE1_DMA_DATA_SHADOW 0x32AC -#define NV4_PFIFO_CACHE1_DMA_DATA_SHADOW_VALUE 0 -#define NV4_PFIFO_CACHE1_DMA_STATE 0x3228 -#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD 2 -#define NV4_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 13 -#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 18 -#define NV4_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x0 -#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR 30 -#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x0 -#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x1 -#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x2 -#define NV4_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x3 -#define NV4_PFIFO_CACHE1_DMA_INSTANCE 0x322C -#define NV4_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0 -#define NV4_PFIFO_CACHE1_DMA_CTL 0x3230 -#define NV4_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 -#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12 -#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x0 -#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x1 -#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13 -#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x0 -#define NV4_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x1 -#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 16 -#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x2 -#define NV4_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x3 -#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO 31 -#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x0 -#define NV4_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x1 -#define NV4_PFIFO_CACHE1_DMA_LIMIT 0x3234 -#define NV4_PFIFO_CACHE1_DMA_LIMIT_OFFSET 2 -#define NV4_PFIFO_CACHE1_DMA_TLB_TAG 0x3238 -#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 -#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0 -#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x0 -#define NV4_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x1 -#define NV4_PFIFO_CACHE1_DMA_TLB_PTE 0x323C -#define NV4_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 12 -#define NV4_PFIFO_CACHE0_PULL0 0x3050 -#define NV4_PFIFO_CACHE0_PULL0_ACCESS 0 -#define NV4_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x1 -#define NV4_PFIFO_CACHE0_PULL0_HASH 4 -#define NV4_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x0 -#define NV4_PFIFO_CACHE0_PULL0_HASH_FAILED 0x1 -#define NV4_PFIFO_CACHE0_PULL0_DEVICE 8 -#define NV4_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x0 -#define NV4_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x1 -#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE 12 -#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x0 -#define NV4_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x1 -#define NV4_PFIFO_CACHE1_PULL0 0x3250 -#define NV4_PFIFO_CACHE1_PULL0_ACCESS 0 -#define NV4_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x1 -#define NV4_PFIFO_CACHE1_PULL0_HASH 4 -#define NV4_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x0 -#define NV4_PFIFO_CACHE1_PULL0_HASH_FAILED 0x1 -#define NV4_PFIFO_CACHE1_PULL0_DEVICE 8 -#define NV4_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x0 -#define NV4_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x1 -#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE 12 -#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x0 -#define NV4_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x1 -#define NV4_PFIFO_CACHE0_PULL1 0x3054 -#define NV4_PFIFO_CACHE0_PULL1_ENGINE 0 -#define NV4_PFIFO_CACHE0_PULL1_ENGINE_SW 0x0 -#define NV4_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x1 -#define NV4_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x2 -#define NV4_PFIFO_CACHE1_PULL1 0x3254 -#define NV4_PFIFO_CACHE1_PULL1_ENGINE 0 -#define NV4_PFIFO_CACHE1_PULL1_ENGINE_SW 0x0 -#define NV4_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x1 -#define NV4_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x2 -#define NV4_PFIFO_CACHE0_HASH 0x3058 -#define NV4_PFIFO_CACHE0_HASH_INSTANCE 0 -#define NV4_PFIFO_CACHE0_HASH_VALID 16 -#define NV4_PFIFO_CACHE1_HASH 0x3258 -#define NV4_PFIFO_CACHE1_HASH_INSTANCE 0 -#define NV4_PFIFO_CACHE1_HASH_VALID 16 -#define NV4_PFIFO_CACHE0_STATUS 0x3014 -#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK 4 -#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x0 -#define NV4_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x1 -#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK 8 -#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x0 -#define NV4_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x1 -#define NV4_PFIFO_CACHE1_STATUS 0x3214 -#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK 4 -#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x0 -#define NV4_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x1 -#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK 8 -#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x0 -#define NV4_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x1 -#define NV4_PFIFO_CACHE1_STATUS1 0x3218 -#define NV4_PFIFO_CACHE1_STATUS1_RANOUT 0 -#define NV4_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x1 -#define NV4_PFIFO_CACHE0_PUT 0x3010 -#define NV4_PFIFO_CACHE0_PUT_ADDRESS 2 -#define NV4_PFIFO_CACHE1_PUT 0x3210 -#define NV4_PFIFO_CACHE1_PUT_ADDRESS 2 -#define NV4_PFIFO_CACHE0_GET 0x3070 -#define NV4_PFIFO_CACHE0_GET_ADDRESS 2 -#define NV4_PFIFO_CACHE1_GET 0x3270 -#define NV4_PFIFO_CACHE1_GET_ADDRESS 2 -#define NV4_PFIFO_ENGINE_SW 0x0 -#define NV4_PFIFO_ENGINE_GRAPHICS 0x1 -#define NV4_PFIFO_ENGINE_DVD 0x2 -#define NV4_PFIFO_CACHE0_ENGINE 0x3080 -// For these, see above -#define NV4_PFIFO_CACHE0_SUBCHANNEL_0_ENGINE 0 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_1_ENGINE 4 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_2_ENGINE 8 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_3_ENGINE 12 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_4_ENGINE 16 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_5_ENGINE 20 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_6_ENGINE 24 -#define NV4_PFIFO_CACHE0_SUBCHANNEL_7_ENGINE 28 -#define NV4_PFIFO_CACHE1_ENGINE 0x3280 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_0_ENGINE 0 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_1_ENGINE 4 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_2_ENGINE 8 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_3_ENGINE 12 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_4_ENGINE 16 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_5_ENGINE 20 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_6_ENGINE 24 -#define NV4_PFIFO_CACHE1_SUBCHANNEL_7_ENGINE 28 -#define NV4_PFIFO_CACHE0_METHOD(i) (0x3100+(i)*8) -#define NV4_PFIFO_CACHE0_METHOD_SIZE_1 1 -#define NV4_PFIFO_CACHE0_METHOD_ADDRESS 2 -#define NV4_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 -#define NV4_PFIFO_CACHE1_METHOD(i) (0x3800+(i)*8) -#define NV4_PFIFO_CACHE1_METHOD_SIZE_1 128 -#define NV4_PFIFO_CACHE1_METHOD_ADDRESS 2 -#define NV4_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 -#define NV4_PFIFO_CACHE1_METHOD_ALIAS(i) (0x3C00+(i)*8) -#define NV4_PFIFO_CACHE1_METHOD_ALIAS_SIZE_1 128 -#define NV4_PFIFO_CACHE0_DATA(i) (0x3104+(i)*8) -#define NV4_PFIFO_CACHE0_DATA_SIZE_1 1 -#define NV4_PFIFO_CACHE0_DATA_VALUE 0 -#define NV4_PFIFO_CACHE1_DATA(i) (0x3804+(i)*8) -#define NV4_PFIFO_CACHE1_DATA_SIZE_1 128 -#define NV4_PFIFO_CACHE1_DATA_VALUE 0 -#define NV4_PFIFO_CACHE1_DATA_ALIAS(i) (0x3C04+(i)*8) -#define NV4_PFIFO_CACHE1_DATA_ALIAS_SIZE_1 128 -#define NV4_PFIFO_DEVICE(i) (0x2800+(i)*4) -#define NV4_PFIFO_DEVICE_SIZE_1 128 -#define NV4_PFIFO_DEVICE_CHID 0 -#define NV4_PFIFO_DEVICE_SWITCH 24 -#define NV4_PFIFO_DEVICE_SWITCH_AVAILABLE 0x1 -#define NV4_PFIFO_RUNOUT_STATUS 0x2400 -#define NV4_PFIFO_RUNOUT_STATUS_RANOUT 0 -#define NV4_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x1 -#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK 4 -#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x0 -#define NV4_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x1 -#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK 8 -#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x0 -#define NV4_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x1 -#define NV4_PFIFO_RUNOUT_PUT 0x2410 -#define NV4_PFIFO_RUNOUT_PUT_ADDRESS 3 // if size=0, 8:3, otherwise 12:3 -#define NV4_PFIFO_RUNOUT_GET 0x2420 -#define NV4_PFIFO_RUNOUT_GET_ADDRESS 3 // 13:3 - -#define NV4_PGRAPH_START 0x400000 -#define NV4_PGRAPH_END 0x401FFF - -#define NV4_PGRAPH_DEBUG_0 0x400080 -#define NV4_PGRAPH_DEBUG_0_STATE 0 -#define NV4_PGRAPH_DEBUG_0_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_FE_STATE 1 -#define NV4_PGRAPH_DEBUG_0_FE_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_FE_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_CACHE_STATE 2 -#define NV4_PGRAPH_DEBUG_0_CACHE_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_CACHE_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE 3 -#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_D3D_PIPE_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_PREROP_STATE 4 -#define NV4_PGRAPH_DEBUG_0_PREROP_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_PREROP_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_ROP_STATE 5 -#define NV4_PGRAPH_DEBUG_0_ROP_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_ROP_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_RSTR_STATE 6 -#define NV4_PGRAPH_DEBUG_0_RSTR_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_RSTR_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE 7 -#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_LIGHT_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_DMA_STATE 8 -#define NV4_PGRAPH_DEBUG_0_DMA_STATE_NORMAL 0x0 -#define NV4_PGRAPH_DEBUG_0_DMA_STATE_RESET 0x1 -#define NV4_PGRAPH_DEBUG_0_SPARE1 12 -#define NV4_PGRAPH_DEBUG_0_SPARE2 13 -#define NV4_PGRAPH_DEBUG_0_MINUSD5 14 -#define NV4_PGRAPH_DEBUG_0_MINUSD5_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_BLIT_DST_LIMIT 15 -#define NV4_PGRAPH_DEBUG_0_BLIT_DST_LIMIT_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_LIMIT_CHECK 16 -#define NV4_PGRAPH_DEBUG_0_LIMIT_CHECK_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_LIMIT_INT 17 -#define NV4_PGRAPH_DEBUG_0_LIMIT_INT_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_OVRFLW_INT 18 -#define NV4_PGRAPH_DEBUG_0_OVRFLW_INT_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20 -#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D 21 -#define NV4_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_DRAWDIR_AUTO 24 -#define NV4_PGRAPH_DEBUG_0_DRAWDIR_AUTO_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y 25 -#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y_DECR 0x0 -#define NV4_PGRAPH_DEBUG_0_DRAWDIR_Y_INCR 0x1 -#define NV4_PGRAPH_DEBUG_0_ALPHA_ABORT 28 -#define NV4_PGRAPH_DEBUG_0_ALPHA_ABORT_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1 0x400084 -#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET 0 -#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x0 -#define NV4_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x1 -#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY 4 -#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY_IGNORE 0x0 -#define NV4_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 0x1 -#define NV4_PGRAPH_DEBUG_1_PATCH_INV 8 -#define NV4_PGRAPH_DEBUG_1_PATCH_INV_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_ALT_RW_SEQ 10 -#define NV4_PGRAPH_DEBUG_1_ALT_RW_SEQ_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_TRI_OPTS 12 -#define NV4_PGRAPH_DEBUG_1_TRI_OPTS_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_TRICLIP_OPTS 13 -#define NV4_PGRAPH_DEBUG_1_TRICLIP_OPTS_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_INSTANCE 16 -#define NV4_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_ALOM_BURST 17 -#define NV4_PGRAPH_DEBUG_1_ALOM_BURST_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_BIDIR_DRAIN 18 -#define NV4_PGRAPH_DEBUG_1_BIDIR_DRAIN_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_EARLY_POST 19 -#define NV4_PGRAPH_DEBUG_1_EARLY_POST_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_CTX 20 -#define NV4_PGRAPH_DEBUG_1_CTX_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_FIXED_ADRS 21 -#define NV4_PGRAPH_DEBUG_1_FIXED_ADRS_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_2D 22 -#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_2D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_3D 23 -#define NV4_PGRAPH_DEBUG_1_DITHER_RANGE_ADJ_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_CACHE 24 -#define NV4_PGRAPH_DEBUG_1_CACHE_IGNORE 0x0 -#define NV4_PGRAPH_DEBUG_1_CACHE_FLUSH 0x1 -#define NV4_PGRAPH_DEBUG_1_CACHE_MODE 25 -#define NV4_PGRAPH_DEBUG_1_CACHE_MODE_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_ZCLAMP 28 -#define NV4_PGRAPH_DEBUG_1_ZCLAMP_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_UCLAMP 29 -#define NV4_PGRAPH_DEBUG_1_UCLAMP_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_RCLAMP 30 -#define NV4_PGRAPH_DEBUG_1_RCLAMP_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_1_DX6_2PIXMODE 31 -#define NV4_PGRAPH_DEBUG_1_DX6_2PIXMODE_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2 0x400088 -#define NV4_PGRAPH_DEBUG_2_HONOR_SRCFMT 0 -#define NV4_PGRAPH_DEBUG_2_HONOR_SRCFMT_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_PINGPONG 0 -#define NV4_PGRAPH_DEBUG_2_PINGPONG_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_SPARE1 4 -#define NV4_PGRAPH_DEBUG_2_SPARE2 5 -#define NV4_PGRAPH_DEBUG_2_SPARE3 6 -#define NV4_PGRAPH_DEBUG_2_SPARE4 7 -#define NV4_PGRAPH_DEBUG_2_SPARE5 8 -#define NV4_PGRAPH_DEBUG_2_SPARE6 9 -#define NV4_PGRAPH_DEBUG_2_SPARE7 10 -#define NV4_PGRAPH_DEBUG_2_MCLK_RECTS 11 -#define NV4_PGRAPH_DEBUG_2_MCLK_RECTS_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_BILINEAR_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_ANISOTROPIC_3D 13 -#define NV4_PGRAPH_DEBUG_2_ANISOTROPIC_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_FOG_3D 14 -#define NV4_PGRAPH_DEBUG_2_FOG_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_SPECULAR_3D 15 -#define NV4_PGRAPH_DEBUG_2_SPECULAR_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_ALPHA_3D 16 -#define NV4_PGRAPH_DEBUG_2_ALPHA_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ 17 -#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_CRZRWCW 0x0 -#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_ZRWCRW 0x1 -#define NV4_PGRAPH_DEBUG_2_ZBUF_SEQ_AUTO 0x2 -#define NV4_PGRAPH_DEBUG_2_COELESCE_D3D 20 -#define NV4_PGRAPH_DEBUG_2_COELESCE_D3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_COELESCE_2D 22 -#define NV4_PGRAPH_DEBUG_2_COELESCE_2D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_FAST_VERTEX_LOAD 23 -#define NV4_PGRAPH_DEBUG_2_FAST_VERTEX_LOAD_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_BLIT_MULTILINE 24 -#define NV4_PGRAPH_DEBUG_2_BLIT_MULTILINE_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_2_VOLATILE_RESET 28 -#define NV4_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3 0x40008C -#define NV4_PGRAPH_DEBUG_3_CULLING 0 -#define NV4_PGRAPH_DEBUG_3_CULLING_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE 1 -#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE_DX3 0x0 -#define NV4_PGRAPH_DEBUG_3_CULLING_TYPE_DX5 0x1 -#define NV4_PGRAPH_DEBUG_3_FAST_DATA_STRTCH 4 -#define NV4_PGRAPH_DEBUG_3_FAST_DATA_STRTCH_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_FAST_DATA_D3D 5 -#define NV4_PGRAPH_DEBUG_3_FAST_DATA_D3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_FAST_DATA_IMAGE 6 -#define NV4_PGRAPH_DEBUG_3_FAST_DATA_IMAGE_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_ZFLUSH 7 -#define NV4_PGRAPH_DEBUG_3_ZFLUSH_IGNORE 0x0 -#define NV4_PGRAPH_DEBUG_3_ZFLUSH_ACTIVATE 0x1 -#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_PTZ 8 -#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_PTZ_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D 9 -#define NV4_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_PTZ 10 -#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_PTZ_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D 11 -#define NV4_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_POSTDITHER_2D 12 -#define NV4_PGRAPH_DEBUG_3_POSTDITHER_2D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_POSTDITHER_3D 13 -#define NV4_PGRAPH_DEBUG_3_POSTDITHER_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_PREDITHER_2D 14 -#define NV4_PGRAPH_DEBUG_3_PREDITHER_2D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_PREDITHER_3D 15 -#define NV4_PGRAPH_DEBUG_3_PREDITHER_3D_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_FORCE_CREAD 16 -#define NV4_PGRAPH_DEBUG_3_FORCE_CREAD_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_FORCE_ZREAD 17 -#define NV4_PGRAPH_DEBUG_3_FORCE_ZREAD_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_EARLYZ_ABORT 18 -#define NV4_PGRAPH_DEBUG_3_EARLYZ_ABORT_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_TRIEND_FLUSH 19 -#define NV4_PGRAPH_DEBUG_3_TRIEND_FLUSH_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_DATA_CHECK 20 -#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21 -#define NV4_PGRAPH_DEBUG_3_DATA_CHECK_FAIL_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_FORMAT_CHECK 22 -#define NV4_PGRAPH_DEBUG_3_FORMAT_CHECK_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_DMA_CHECK 23 -#define NV4_PGRAPH_DEBUG_3_DMA_CHECK_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_RAMREADBACK 24 -#define NV4_PGRAPH_DEBUG_3_RAMREADBACK_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_CLIP_METHODS 25 -#define NV4_PGRAPH_DEBUG_3_CLIP_METHODS_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_EXCLUDE_ROP_IN_IDLE 27 -#define NV4_PGRAPH_DEBUG_3_EXCLUDE_ROP_IN_IDLE_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_STATE_CHECK 28 -#define NV4_PGRAPH_DEBUG_3_STATE_CHECK_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_CONTEXT_METHODS 29 -#define NV4_PGRAPH_DEBUG_3_CONTEXT_METHODS_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_OPERATION_METHOD 30 -#define NV4_PGRAPH_DEBUG_3_OPERATION_METHOD_ENABLED 0x1 -#define NV4_PGRAPH_DEBUG_3_IGNORE_PATCHVALID 31 -#define NV4_PGRAPH_DEBUG_3_IGNORE_PATCHVALID_ENABLED 0x1 -#define NV4_PGRAPH_INTR 0x400100 -#define NV4_PGRAPH_INTR_NOTIFY 0 -#define NV4_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x0 -#define NV4_PGRAPH_INTR_NOTIFY_PENDING 0x1 -#define NV4_PGRAPH_INTR_NOTIFY_RESET 0x1 -#define NV4_PGRAPH_INTR_MISSING_HW 4 -#define NV4_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x0 -#define NV4_PGRAPH_INTR_MISSING_HW_PENDING 0x1 -#define NV4_PGRAPH_INTR_MISSING_HW_RESET 0x1 -#define NV4_PGRAPH_INTR_TLB_PRESENT_A 8 -#define NV4_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x0 -#define NV4_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x1 -#define NV4_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x1 -#define NV4_PGRAPH_INTR_TLB_PRESENT_B 9 -#define NV4_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x0 -#define NV4_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x1 -#define NV4_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x1 -#define NV4_PGRAPH_INTR_CONTEXT_SWITCH 12 -#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x0 -#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x1 -#define NV4_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x1 -#define NV4_PGRAPH_INTR_BUFFER_NOTIFY 16 -#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x0 -#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x1 -#define NV4_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x1 -#define NV4_PGRAPH_NSTATUS 0x400104 -#define NV4_PGRAPH_NSTATUS_STATE_IN_USE 11 -#define NV4_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x1 -#define NV4_PGRAPH_NSTATUS_INVALID_STATE 12 -#define NV4_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x1 -#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT 13 -#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x1 -#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT 14 -#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE 0x400108 -#define NV4_PGRAPH_NSOURCE_NOTIFICATION 0 -#define NV4_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_DATA_ERROR 1 -#define NV4_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR 2 -#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION 3 -#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR 4 -#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_ 5 -#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD 6 -#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION 7 -#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION 8 -#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9 -#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION 10 -#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_STATE_INVALID 11 -#define NV4_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12 -#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE 13 -#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_METHOD_CNT 14 -#define NV4_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x1 -#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION 15 -#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x0 -#define NV4_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x1 -#define NV4_PGRAPH_INTR_EN 0x400140 -#define NV4_PGRAPH_INTR_EN_NOTIFY 0 -#define NV4_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x1 -#define NV4_PGRAPH_INTR_EN_MISSING_HW 4 -#define NV4_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x1 -#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_A 8 -#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x1 -#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_B 9 -#define NV4_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x1 -#define NV4_PGRAPH_INTR_EN_CONTEXT_SWITCH 12 -#define NV4_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x1 -#define NV4_PGRAPH_INTR_EN_BUFFER_NOTIFY 16 -#define NV4_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x1 -#define NV4_PGRAPH_CTX_SWITCH1 0x400160 -#define NV4_PGRAPH_CTX_SWITCH1_GRCLASS 0 -#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12 -#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP 13 -#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE 14 -#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x2 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x3 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x4 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x5 -#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE 20 -#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_COMPATIBILITY 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_DITHER 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_TRUNCATE 0x2 -#define NV4_PGRAPH_CTX_SWITCH1_DITHER_MODE_MS 0x3 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25 -#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x1 -#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31 -#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x0 -#define NV4_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x1 -#define NV4_PGRAPH_CTX_SWITCH2 0x400164 -#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT 0 -#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 -#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 -#define NV4_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 -#define NV4_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 -#define NV4_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 16 -#define NV4_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x00 -#define NV4_PGRAPH_CTX_SWITCH3 0x400168 -#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 0 -#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x00 -#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 16 -#define NV4_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x00 -#define NV4_PGRAPH_CTX_SWITCH4 0x40016C -#define NV4_PGRAPH_CTX_SWITCH4_USER_INSTANCE 0 -#define NV4_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x00 -#define NV4_PGRAPH_CTX_CACHE1(i) (0x400180+(i)*4) -#define NV4_PGRAPH_CTX_CACHE1_SIZE_1 8 -#define NV4_PGRAPH_CTX_CACHE1_GRCLASS 0 -#define NV4_PGRAPH_CTX_CACHE1_CHROMA_KEY 12 -#define NV4_PGRAPH_CTX_CACHE1_USER_CLIP 13 -#define NV4_PGRAPH_CTX_CACHE1_SWIZZLE 14 -#define NV4_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 -#define NV4_PGRAPH_CTX_CACHE1_SPARE1 20 -#define NV4_PGRAPH_CTX_CACHE1_PATCH_STATUS 24 -#define NV4_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25 -#define NV4_PGRAPH_CTX_CACHE2(i) (0x4001a0+(i)*4) -#define NV4_PGRAPH_CTX_CACHE2_SIZE_1 8 -#define NV4_PGRAPH_CTX_CACHE2_MONO_FORMAT 0 -#define NV4_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 -#define NV4_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 16 -#define NV4_PGRAPH_CTX_CACHE3(i) (0x4001c0+(i)*4) -#define NV4_PGRAPH_CTX_CACHE3_SIZE_1 8 -#define NV4_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 0 -#define NV4_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 16 -#define NV4_PGRAPH_CTX_CACHE4(i) (0x4001e0+(i)*4) -#define NV4_PGRAPH_CTX_CACHE4_SIZE_1 8 -#define NV4_PGRAPH_CTX_CACHE4_USER_INSTANCE 0 -#define NV4_PGRAPH_CTX_CONTROL 0x400170 -#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME 0 -#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x0 -#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x1 -#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x2 -#define NV4_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x3 -#define NV4_PGRAPH_CTX_CONTROL_TIME 8 -#define NV4_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x0 -#define NV4_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x1 -#define NV4_PGRAPH_CTX_CONTROL_CHID 16 -#define NV4_PGRAPH_CTX_CONTROL_CHID_INVALID 0x0 -#define NV4_PGRAPH_CTX_CONTROL_CHID_VALID 0x1 -#define NV4_PGRAPH_CTX_CONTROL_CHANGE 20 -#define NV4_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x0 -#define NV4_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x1 -#define NV4_PGRAPH_CTX_CONTROL_SWITCHING 24 -#define NV4_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x0 -#define NV4_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x1 -#define NV4_PGRAPH_CTX_CONTROL_DEVICE 28 -#define NV4_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x0 -#define NV4_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x1 -#define NV4_PGRAPH_CTX_USER 0x400174 -#define NV4_PGRAPH_CTX_USER_SUBCH 13 -#define NV4_PGRAPH_CTX_USER_SUBCH_0 0x0 -#define NV4_PGRAPH_CTX_USER_CHID 24 -#define NV4_PGRAPH_CTX_USER_CHID_0 0x0 -#define NV4_PGRAPH_FIFO 0x400720 -#define NV4_PGRAPH_FIFO_ACCESS 0 -#define NV4_PGRAPH_FIFO_ACCESS_DISABLED 0x0 -#define NV4_PGRAPH_FIFO_ACCESS_ENABLED 0x1 -#define NV4_PGRAPH_FFINTFC_FIFO_0(i) (0x400730+(i)*4) -#define NV4_PGRAPH_FFINTFC_FIFO_0_SIZE_1 4 -#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG 0 -#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x0 -#define NV4_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x1 -// Note: shift left by 1 (3:1). Subch number = 0-7 -#define NV4_PGRAPH_FFINTFC_FIFO_0_SUBCH 1 -#define NV4_PGRAPH_FFINTFC_FIFO_0_MTHD 4 -#define NV4_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x0 -#define NV4_PGRAPH_FFINTFC_FIFO_1(i) (0x400740+(i)*4) -#define NV4_PGRAPH_FFINTFC_FIFO_1_SIZE_1 4 -#define NV4_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 0 -#define NV4_PGRAPH_FFINTFC_FIFO_PTR 0x400750 -#define NV4_PGRAPH_FFINTFC_FIFO_PTR_WRITE 0 -#define NV4_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x0 -#define NV4_PGRAPH_FFINTFC_FIFO_PTR_READ 4 -#define NV4_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x0 -#define NV4_PGRAPH_FFINTFC_ST2 0x400754 -#define NV4_PGRAPH_FFINTFC_ST2_STATUS 0 -#define NV4_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x1 -#define NV4_PGRAPH_FFINTFC_ST2_MTHD 1 -#define NV4_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH 12 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_0 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_1 0x1 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_2 0x2 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_3 0x3 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_4 0x4 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_5 0x5 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_6 0x6 -#define NV4_PGRAPH_FFINTFC_ST2_SUBCH_7 0x7 -#define NV4_PGRAPH_FFINTFC_ST2_CHID 15 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_0 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_1 0x1 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_2 0x2 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_3 0x3 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_4 0x4 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_5 0x5 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_6 0x6 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_7 0x7 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_8 0x8 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_9 0x9 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_10 0xA -#define NV4_PGRAPH_FFINTFC_ST2_CHID_11 0xB -#define NV4_PGRAPH_FFINTFC_ST2_CHID_12 0xC -#define NV4_PGRAPH_FFINTFC_ST2_CHID_13 0xD -#define NV4_PGRAPH_FFINTFC_ST2_CHID_14 0xE -#define NV4_PGRAPH_FFINTFC_ST2_CHID_15 0xF -#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS 19 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x1 -#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT 20 -#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT_CLEAR 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_CH_SWITCH_DETECT_SET 0x1 -#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD 21 -#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD_CLEAR 0x0 -#define NV4_PGRAPH_FFINTFC_ST2_FIFO_HOLD_SET 0x1 -#define NV4_PGRAPH_FFINTFC_ST2_D 0x400758 -#define NV4_PGRAPH_FFINTFC_ST2_D_ARGUMENT 0 -#define NV4_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x0 -#define NV4_PGRAPH_STATUS 0x400700 -#define NV4_PGRAPH_STATUS_STATE 0 -#define NV4_PGRAPH_STATUS_STATE_IDLE 0x0 -#define NV4_PGRAPH_STATUS_STATE_BUSY 0x1 -#define NV4_PGRAPH_STATUS_XY_LOGIC 4 -#define NV4_PGRAPH_STATUS_XY_LOGIC_IDLE 0x0 -#define NV4_PGRAPH_STATUS_XY_LOGIC_BUSY 0x1 -#define NV4_PGRAPH_STATUS_FE 5 -#define NV4_PGRAPH_STATUS_FE_IDLE 0x0 -#define NV4_PGRAPH_STATUS_FE_BUSY 0x1 -#define NV4_PGRAPH_STATUS_RASTERIZER 6 -#define NV4_PGRAPH_STATUS_RASTERIZER_IDLE 0x0 -#define NV4_PGRAPH_STATUS_RASTERIZER_BUSY 0x1 -#define NV4_PGRAPH_STATUS_PORT_NOTIFY 8 -#define NV4_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x0 -#define NV4_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x1 -#define NV4_PGRAPH_STATUS_PORT_REGISTER 12 -#define NV4_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x0 -#define NV4_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x1 -#define NV4_PGRAPH_STATUS_PORT_DMA 16 -#define NV4_PGRAPH_STATUS_PORT_DMA_IDLE 0x0 -#define NV4_PGRAPH_STATUS_PORT_DMA_BUSY 0x1 -#define NV4_PGRAPH_STATUS_DMA_ENGINE 17 -#define NV4_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x0 -#define NV4_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x1 -#define NV4_PGRAPH_STATUS_DMA_NOTIFY 20 -#define NV4_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x0 -#define NV4_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x1 -#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21 -#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x0 -#define NV4_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x1 -#define NV4_PGRAPH_STATUS_D3D 24 -#define NV4_PGRAPH_STATUS_D3D_IDLE 0x0 -#define NV4_PGRAPH_STATUS_D3D_BUSY 0x1 -#define NV4_PGRAPH_STATUS_CACHE 25 -#define NV4_PGRAPH_STATUS_CACHE_IDLE 0x0 -#define NV4_PGRAPH_STATUS_CACHE_BUSY 0x1 -#define NV4_PGRAPH_STATUS_LIGHTING 26 -#define NV4_PGRAPH_STATUS_LIGHTING_IDLE 0x0 -#define NV4_PGRAPH_STATUS_LIGHTING_BUSY 0x1 -#define NV4_PGRAPH_STATUS_PREROP 27 -#define NV4_PGRAPH_STATUS_PREROP_IDLE 0x0 -#define NV4_PGRAPH_STATUS_PREROP_BUSY 0x1 -#define NV4_PGRAPH_STATUS_ROP 28 -#define NV4_PGRAPH_STATUS_ROP_IDLE 0x0 -#define NV4_PGRAPH_STATUS_ROP_BUSY 0x1 -#define NV4_PGRAPH_STATUS_PORT_USER 29 -#define NV4_PGRAPH_STATUS_PORT_USER_IDLE 0x0 -#define NV4_PGRAPH_STATUS_PORT_USER_BUSY 0x1 -#define NV4_PGRAPH_TRAPPED_ADDR 0x400704 -#define NV4_PGRAPH_TRAPPED_ADDR_MTHD 2 -#define NV4_PGRAPH_TRAPPED_ADDR_SUBCH 13 -#define NV4_PGRAPH_TRAPPED_ADDR_CHID 24 -#define NV4_PGRAPH_TRAPPED_DATA 0x400708 -#define NV4_PGRAPH_TRAPPED_DATA_VALUE 0 -#define NV4_PGRAPH_SURFACE 0x40070C -#define NV4_PGRAPH_SURFACE_TYPE 0 -#define NV4_PGRAPH_SURFACE_TYPE_INVALID 0x0 -#define NV4_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x1 -#define NV4_PGRAPH_SURFACE_TYPE_SWIZZLE 0x2 -#define NV4_PGRAPH_NOTIFY 0x400714 -#define NV4_PGRAPH_NOTIFY_BUFFER_REQ 0 -#define NV4_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x0 -#define NV4_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x1 -#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE 8 -#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x0 -#define NV4_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x1 -#define NV4_PGRAPH_NOTIFY_REQ 16 -#define NV4_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x0 -#define NV4_PGRAPH_NOTIFY_REQ_PENDING 0x1 -#define NV4_PGRAPH_NOTIFY_STYLE 20 -#define NV4_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x0 -#define NV4_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x1 -#define NV4_PGRAPH_BOFFSET(i) (0x400640+(i)*4) -//used for all -#define NV4_PGRAPH_BOFFSET_LINADRS_DEFAULT 0x0 -#define NV4_PGRAPH_BOFFSET_SIZE_1 6 -#define NV4_PGRAPH_BOFFSET_LINADRS 0 -#define NV4_PGRAPH_BOFFSET_LINADRS_0 0x0 -#define NV4_PGRAPH_BOFFSET0 0x400640 -#define NV4_PGRAPH_BOFFSET0_ALIAS_1 NV_PGRAPH_BOFFSET(0) -#define NV4_PGRAPH_BOFFSET0_LINADRS 0 -#define NV4_PGRAPH_BOFFSET1 0x400644 -#define NV4_PGRAPH_BOFFSET1_ALIAS_1 NV_PGRAPH_BOFFSET(1) -#define NV4_PGRAPH_BOFFSET1_LINADRS 0 -#define NV4_PGRAPH_BOFFSET2 0x400648 -#define NV4_PGRAPH_BOFFSET2_ALIAS_1 NV_PGRAPH_BOFFSET(2) -#define NV4_PGRAPH_BOFFSET2_LINADRS 0 -#define NV4_PGRAPH_BOFFSET3 0x40064C -#define NV4_PGRAPH_BOFFSET3_ALIAS_1 NV_PGRAPH_BOFFSET(3) -#define NV4_PGRAPH_BOFFSET3_LINADRS 0 -#define NV4_PGRAPH_BOFFSET4 0x400650 -#define NV4_PGRAPH_BOFFSET4_ALIAS_1 NV_PGRAPH_BOFFSET(4) -#define NV4_PGRAPH_BOFFSET4_LINADRS 0 -#define NV4_PGRAPH_BOFFSET5 0x400654 -#define NV4_PGRAPH_BOFFSET5_ALIAS_1 NV_PGRAPH_BOFFSET(5) -#define NV4_PGRAPH_BOFFSET5_LINADRS 0 -#define NV4_PGRAPH_BBASE(i) (0x400658+(i)*4) -//used for all -#define NV4_PGRAPH_BBASE_LINADRS_DEFAULT 0x0 -#define NV4_PGRAPH_BBASE_SIZE_1 6 -#define NV4_PGRAPH_BBASE_LINADRS 0 -#define NV4_PGRAPH_BBASE0 0x400658 -#define NV4_PGRAPH_BBASE0_ALIAS_1 NV_PGRAPH_BBASE(0) -#define NV4_PGRAPH_BBASE0_LINADRS 0 -#define NV4_PGRAPH_BBASE1 0x40065c -#define NV4_PGRAPH_BBASE1_ALIAS_1 NV_PGRAPH_BBASE(1) -#define NV4_PGRAPH_BBASE1_LINADRS 0 -#define NV4_PGRAPH_BBASE2 0x400660 -#define NV4_PGRAPH_BBASE2_ALIAS_1 NV_PGRAPH_BBASE(2) -#define NV4_PGRAPH_BBASE2_LINADRS 0 -#define NV4_PGRAPH_BBASE3 0x400664 -#define NV4_PGRAPH_BBASE3_ALIAS_1 NV_PGRAPH_BBASE(3) -#define NV4_PGRAPH_BBASE3_LINADRS 0 -#define NV4_PGRAPH_BBASE4 0x400668 -#define NV4_PGRAPH_BBASE4_ALIAS_1 NV_PGRAPH_BBASE(4) -#define NV4_PGRAPH_BBASE4_LINADRS 0 -#define NV4_PGRAPH_BBASE5 0x40066C -#define NV4_PGRAPH_BBASE5_ALIAS_1 NV_PGRAPH_BBASE(5) -#define NV4_PGRAPH_BBASE5_LINADRS 0 -#define NV4_PGRAPH_BPITCH(i) (0x400670+(i)*4) -//used for all -#define NV4_PGRAPH_BPITCH_LINADRS_DEFAULT 0x0 -#define NV4_PGRAPH_BPITCH_SIZE_1 5 -#define NV4_PGRAPH_BPITCH_VALUE 0 // use bit 0 for all -#define NV4_PGRAPH_BPITCH_VALUE_0 0x0 -#define NV4_PGRAPH_BPITCH0 0x400670 -#define NV4_PGRAPH_BPITCH0_ALIAS_1 NV_PGRAPH_BPITCH(0) -#define NV4_PGRAPH_BPITCH1 0x400674 -#define NV4_PGRAPH_BPITCH1_ALIAS_1 NV_PGRAPH_BPITCH(1) -#define NV4_PGRAPH_BPITCH2 0x400678 -#define NV4_PGRAPH_BPITCH2_ALIAS_1 NV_PGRAPH_BPITCH(2) -#define NV4_PGRAPH_BPITCH3 0x40067C -#define NV4_PGRAPH_BPITCH3_ALIAS_1 NV_PGRAPH_BPITCH(3) -#define NV4_PGRAPH_BPITCH4 0x400680 -#define NV4_PGRAPH_BPITCH4_ALIAS_1 NV_PGRAPH_BPITCH(4) -#define NV4_PGRAPH_BLIMIT(i) (0x400684+(i)*4) -//following two used for all -#define NV4_PGRAPH_BLIMIT_SIZE_1 6 -#define NV4_PGRAPH_BLIMIT_VALUE 0 -#define NV4_PGRAPH_BLIMIT_TYPE 31 -#define NV4_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x0 -#define NV4_PGRAPH_BLIMIT_TYPE_NULL 0x1 -#define NV4_PGRAPH_BLIMIT0 0x400684 -#define NV4_PGRAPH_BLIMIT0_ALIAS_1 NV_PGRAPH_BLIMIT(0) -#define NV4_PGRAPH_BLIMIT1 0x400688 -#define NV4_PGRAPH_BLIMIT1_ALIAS_1 NV_PGRAPH_BLIMIT(1) -#define NV4_PGRAPH_BLIMIT2 0x40068c -#define NV4_PGRAPH_BLIMIT2_ALIAS_1 NV_PGRAPH_BLIMIT(2) -#define NV4_PGRAPH_BLIMIT3 0x400690 -#define NV4_PGRAPH_BLIMIT3_ALIAS_1 NV_PGRAPH_BLIMIT(3) -#define NV4_PGRAPH_BLIMIT4 0x400694 -#define NV4_PGRAPH_BLIMIT4_ALIAS_1 NV_PGRAPH_BLIMIT(4) -#define NV4_PGRAPH_BLIMIT5 0x400698 -#define NV4_PGRAPH_BLIMIT5_ALIAS_1 NV_PGRAPH_BLIMIT(5) -#define NV4_PGRAPH_BSWIZZLE2 0x40069c -#define NV4_PGRAPH_BSWIZZLE2_WIDTH 16 -#define NV4_PGRAPH_BSWIZZLE2_WIDTH_0 0x0 -#define NV4_PGRAPH_BSWIZZLE2_HEIGHT 24 -#define NV4_PGRAPH_BSWIZZLE2_HEIGHT_0 0x0 -#define NV4_PGRAPH_BSWIZZLE5 0x4006a0 -#define NV4_PGRAPH_BSWIZZLE5_WIDTH 16 -#define NV4_PGRAPH_BSWIZZLE5_WIDTH_0 0x0 -#define NV4_PGRAPH_BSWIZZLE5_HEIGHT 24 -#define NV4_PGRAPH_BSWIZZLE5_HEIGHT_0 0x0 -#define NV4_PGRAPH_BPIXEL 0x400724 -#define NV4_PGRAPH_BPIXEL_DEPTH0 0 -#define NV4_PGRAPH_BPIXEL_DEPTH1 4 -#define NV4_PGRAPH_BPIXEL_DEPTH2 8 -#define NV4_PGRAPH_BPIXEL_DEPTH3 12 -#define NV4_PGRAPH_BPIXEL_DEPTH4 16 -#define NV4_PGRAPH_BPIXEL_DEPTH5 20 - -// valid for depth0-depth5 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_INVALID 0x0 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y8 0x1 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1R5G5B5_Z1R5G5B5 0x2 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1R5G5B5_O1R5G5B5 0x3 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_A1R5G5B5 0x4 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_R5G6B5 0x5 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y16 0x6 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_Z8R8G8B8 0x7 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_O1Z7R8G8B8 0x8 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x9 -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X1A7R8G8B8_O1A7R8G8B8 0xA -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_X8R8G8B8_O8R8G8B8 0xB -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_A8R8G8B8 0xC -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_Y32 0xD -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_V8YB8U8YA8 0xE -#define NV4_PGRAPH_BPIXEL_DEPTH_FORMAT_YB8V8YA8U8 0xF - -#define NV4_PGRAPH_LIMIT_VIOL_PIX 0x400610 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_ADRS 0 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT 29 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x1 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x1 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x1 -#define NV4_PGRAPH_LIMIT_VIOL_Z 0x400614 -#define NV4_PGRAPH_LIMIT_VIOL_Z_ADRS 0 -#define NV4_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT 30 -#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x1 -#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31 -#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x0 -#define NV4_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x1 -#define NV4_PGRAPH_STATE 0x400710 -#define NV4_PGRAPH_STATE_BUFFER_0 0 -#define NV4_PGRAPH_STATE_BUFFER_0_INVALID 0x0 -#define NV4_PGRAPH_STATE_BUFFER_0_VALID 0x1 -#define NV4_PGRAPH_STATE_BUFFER_1 1 -#define NV4_PGRAPH_STATE_BUFFER_1_INVALID 0x0 -#define NV4_PGRAPH_STATE_BUFFER_1_VALID 0x1 -#define NV4_PGRAPH_STATE_BUFFER_2 2 -#define NV4_PGRAPH_STATE_BUFFER_2_INVALID 0x0 -#define NV4_PGRAPH_STATE_BUFFER_2_VALID 0x1 -#define NV4_PGRAPH_STATE_BUFFER_3 3 -#define NV4_PGRAPH_STATE_BUFFER_3_INVALID 0x0 -#define NV4_PGRAPH_STATE_BUFFER_3_VALID 0x1 -#define NV4_PGRAPH_STATE_BUFFER_4 4 -#define NV4_PGRAPH_STATE_BUFFER_4_INVALID 0x0 -#define NV4_PGRAPH_STATE_BUFFER_4_VALID 0x1 -#define NV4_PGRAPH_STATE_BUFFER_5 5 -#define NV4_PGRAPH_STATE_BUFFER_5_INVALID 0x0 -#define NV4_PGRAPH_STATE_BUFFER_5_VALID 0x1 -#define NV4_PGRAPH_STATE_PITCH_0 8 -#define NV4_PGRAPH_STATE_PITCH_0_INVALID 0x0 -#define NV4_PGRAPH_STATE_PITCH_0_VALID 0x1 -#define NV4_PGRAPH_STATE_PITCH_1 9 -#define NV4_PGRAPH_STATE_PITCH_1_INVALID 0x0 -#define NV4_PGRAPH_STATE_PITCH_1_VALID 0x1 -#define NV4_PGRAPH_STATE_PITCH_2 10 -#define NV4_PGRAPH_STATE_PITCH_2_INVALID 0x0 -#define NV4_PGRAPH_STATE_PITCH_2_VALID 0x1 -#define NV4_PGRAPH_STATE_PITCH_3 11 -#define NV4_PGRAPH_STATE_PITCH_3_INVALID 0x0 -#define NV4_PGRAPH_STATE_PITCH_3_VALID 0x1 -#define NV4_PGRAPH_STATE_PITCH_4 12 -#define NV4_PGRAPH_STATE_PITCH_4_INVALID 0x0 -#define NV4_PGRAPH_STATE_PITCH_4_VALID 0x1 -#define NV4_PGRAPH_STATE_CHROMA_COLOR 16 -#define NV4_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x0 -#define NV4_PGRAPH_STATE_CHROMA_COLOR_VALID 0x1 -#define NV4_PGRAPH_STATE_CHROMA_COLORFMT 17 -#define NV4_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x0 -#define NV4_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x1 -#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT 20 -#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x0 -#define NV4_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x1 -#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT 21 -#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x0 -#define NV4_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x1 -#define NV4_PGRAPH_STATE_CPATTERN_SELECT 22 -#define NV4_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x0 -#define NV4_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x1 -#define NV4_PGRAPH_STATE_PATTERN_COLOR0 24 -#define NV4_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x0 -#define NV4_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x1 -#define NV4_PGRAPH_STATE_PATTERN_COLOR1 25 -#define NV4_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x0 -#define NV4_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x1 -#define NV4_PGRAPH_STATE_PATTERN_PATT0 26 -#define NV4_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x0 -#define NV4_PGRAPH_STATE_PATTERN_PATT0_VALID 0x1 -#define NV4_PGRAPH_STATE_PATTERN_PATT1 27 -#define NV4_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x0 -#define NV4_PGRAPH_STATE_PATTERN_PATT1_VALID 0x1 -#define NV4_PGRAPH_CACHE_INDEX 0x400728 -#define NV4_PGRAPH_CACHE_INDEX_BANK 2 -#define NV4_PGRAPH_CACHE_INDEX_BANK_10 0x0 -#define NV4_PGRAPH_CACHE_INDEX_BANK_32 0x1 -#define NV4_PGRAPH_CACHE_INDEX_ADRS 3 -#define NV4_PGRAPH_CACHE_INDEX_ADRS_0 0x0 -#define NV4_PGRAPH_CACHE_INDEX_ADRS_1024 0x400 -#define NV4_PGRAPH_CACHE_INDEX_OP 13 -#define NV4_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x0 -#define NV4_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x1 -#define NV4_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x2 -#define NV4_PGRAPH_CACHE_RAM 0x40072c -#define NV4_PGRAPH_CACHE_RAM_VALUE 0 -#define NV4_PGRAPH_DMA_PITCH 0x400760 -#define NV4_PGRAPH_DMA_PITCH_S0 0 -#define NV4_PGRAPH_DMA_PITCH_S1 16 -#define NV4_PGRAPH_DVD_COLORFMT 0x400764 -#define NV4_PGRAPH_DVD_COLORFMT_IMAGE 0 -#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 -#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 -#define NV4_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 -#define NV4_PGRAPH_DVD_COLORFMT_OVLY 8 -#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 -#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 -#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 -#define NV4_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 -#define NV4_PGRAPH_SCALED_FORMAT 0x400768 -#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN 16 -#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x0 -#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x1 -#define NV4_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x2 -#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24 -#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x0 -#define NV4_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x1 -#define NV4_PGRAPH_PATT_COLOR0 0x400800 -#define NV4_PGRAPH_PATT_COLOR0_VALUE 0 -#define NV4_PGRAPH_PATT_COLOR1 0x400804 -#define NV4_PGRAPH_PATT_COLOR1_VALUE 0 -#define NV4_PGRAPH_PATT_COLORRAM(i) (0x400900+(i)*4) -#define NV4_PGRAPH_PATT_COLORRAM_SIZE_1 64 -#define NV4_PGRAPH_PATT_COLORRAM_VALUE 0 -#define NV4_PGRAPH_PATTERN(i) (0x400808+(i)*4) -#define NV4_PGRAPH_PATTERN_SIZE_1 2 -#define NV4_PGRAPH_PATTERN_BITMAP 0 -#define NV4_PGRAPH_PATTERN_SHAPE 0x400810 -#define NV4_PGRAPH_PATTERN_SHAPE_VALUE 0 -#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x0 -#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x1 -#define NV4_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x2 -#define NV4_PGRAPH_PATTERN_SHAPE_SELECT 4 -#define NV4_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x0 -#define NV4_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x1 -#define NV4_PGRAPH_MONO_COLOR0 0x400600 -#define NV4_PGRAPH_MONO_COLOR0_VALUE 0 -#define NV4_PGRAPH_ROP3 0x400604 -#define NV4_PGRAPH_ROP3_VALUE 0 -#define NV4_PGRAPH_CHROMA 0x400814 -#define NV4_PGRAPH_CHROMA_VALUE 0 -#define NV4_PGRAPH_BETA_AND 0x400608 -#define NV4_PGRAPH_BETA_AND_VALUE_FRACTION 23 -#define NV4_PGRAPH_BETA_PREMULT 0x40060c -#define NV4_PGRAPH_BETA_PREMULT_VALUE 0 -#define NV4_PGRAPH_CONTROL0 0x400818 -#define NV4_PGRAPH_CONTROL0_ALPHAREF 0 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC 8 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_NEVER 0x1 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_LESS 0x2 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_EQUAL 0x3 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_LESSEQUAL 0x4 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_GREATER 0x5 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_NOTEQUAL 0x6 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_GREATEREQUAL 0x7 -#define NV4_PGRAPH_CONTROL0_ALPHAFUNC_ALWAYS 0x8 -#define NV4_PGRAPH_CONTROL0_ALPHATESTENABLE 12 -#define NV4_PGRAPH_CONTROL0_ALPHATESTENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_ZENABLE 14 -#define NV4_PGRAPH_CONTROL0_ZENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_ZENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_ZFUNC 16 -#define NV4_PGRAPH_CONTROL0_ZFUNC_NEVER 0x1 -#define NV4_PGRAPH_CONTROL0_ZFUNC_LESS 0x2 -#define NV4_PGRAPH_CONTROL0_ZFUNC_EQUAL 0x3 -#define NV4_PGRAPH_CONTROL0_ZFUNC_LESSEQUAL 0x4 -#define NV4_PGRAPH_CONTROL0_ZFUNC_GREATER 0x5 -#define NV4_PGRAPH_CONTROL0_ZFUNC_NOTEQUAL 0x6 -#define NV4_PGRAPH_CONTROL0_ZFUNC_GREATEREQUAL 0x7 -#define NV4_PGRAPH_CONTROL0_ZFUNC_ALWAYS 0x8 -#define NV4_PGRAPH_CONTROL0_CULLMODE 20 -#define NV4_PGRAPH_CONTROL0_CULLMODE_NONE 0x1 -#define NV4_PGRAPH_CONTROL0_CULLMODE_CW 0x2 -#define NV4_PGRAPH_CONTROL0_CULLMODE_CCW 0x3 -#define NV4_PGRAPH_CONTROL0_DITHERENABLE 22 -#define NV4_PGRAPH_CONTROL0_DITHERENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_DITHERENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE 23 -#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE 24 -#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_ZWRITEENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE 25 -#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE 26 -#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_ALPHA_WRITE_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE 27 -#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_RED_WRITE_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE 28 -#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_GREEN_WRITE_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE 29 -#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL0_BLUE_WRITE_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL0_Z_FORMAT 30 -#define NV4_PGRAPH_CONTROL0_Z_FORMAT_FIXED 0x1 -#define NV4_PGRAPH_CONTROL0_Z_FORMAT_FLOAT 0x2 -#define NV4_PGRAPH_CONTROL1 0x40081c -#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE 0 -#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_CONTROL1_STENCIL_TEST_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC 4 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_NEVER 0x1 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_LESS 0x2 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_EQUAL 0x3 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_LESSEQUAL 0x4 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_GREATER 0x5 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_NOTEQUAL 0x6 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_GREATEREQUAL 0x7 -#define NV4_PGRAPH_CONTROL1_STENCIL_FUNC_ALWAYS 0x8 -#define NV4_PGRAPH_CONTROL1_STENCIL_REF 8 -#define NV4_PGRAPH_CONTROL1_STENCIL_MASK_READ 16 -#define NV4_PGRAPH_CONTROL1_STENCIL_MASK_WRITE 24 -#define NV4_PGRAPH_CONTROL2 0x400820 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL 0 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_KEEP 0x1 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_ZERO 0x2 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_REPLACE 0x3 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INCRSAT 0x4 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_DECRSAT 0x5 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INVERT 0x6 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_INCR 0x7 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_FAIL_DECR 0x8 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL 4 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_KEEP 0x1 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_ZERO 0x2 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_REPLACE 0x3 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INCRSAT 0x4 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_DECRSAT 0x5 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INVERT 0x6 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_INCR 0x7 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZFAIL_DECR 0x8 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS 8 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_KEEP 0x1 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_ZERO 0x2 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_REPLACE 0x3 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INCRSAT 0x4 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_DECRSAT 0x5 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INVERT 0x6 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_INCR 0x7 -#define NV4_PGRAPH_CONTROL2_STENCIL_OP_ZPASS_DECR 0x8 -#define NV4_PGRAPH_BLEND 0x400824 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND 0 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECAL 0x1 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATE 0x2 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x3 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x4 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_DECALMASK 0x5 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x6 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_COPY 0x7 -#define NV4_PGRAPH_BLEND_TEXTUREMAPBLEND_ADD 0x8 -#define NV4_PGRAPH_BLEND_MASK_BIT 4 -#define NV4_PGRAPH_BLEND_MASK_BIT_LSB 0x1 -#define NV4_PGRAPH_BLEND_MASK_BIT_MSB 0x2 -#define NV4_PGRAPH_BLEND_SHADEMODE 6 -#define NV4_PGRAPH_BLEND_SHADEMODE_FLAT 0x1 -#define NV4_PGRAPH_BLEND_SHADEMODE_GOURAUD 0x2 -#define NV4_PGRAPH_BLEND_SHADEMODE_PHONG 0x3 -#define NV4_PGRAPH_BLEND_TEXTUREPERSPECTIVE 8 -#define NV4_PGRAPH_BLEND_TEXTUREPERSPECTIVE_TRUE 0x1 -#define NV4_PGRAPH_BLEND_SPECULARENABLE 12 -#define NV4_PGRAPH_BLEND_SPECULARENABLE_TRUE 0x1 -#define NV4_PGRAPH_BLEND_FOGENABLE 16 -#define NV4_PGRAPH_BLEND_FOGENABLE_TRUE 0x1 -#define NV4_PGRAPH_BLEND_ALPHABLENDENABLE 20 -#define NV4_PGRAPH_BLEND_ALPHABLENDENABLE_TRUE 0x1 -#define NV4_PGRAPH_BLEND_SRCBLEND 24 -#define NV4_PGRAPH_BLEND_SRCBLEND_ZERO 0x1 -#define NV4_PGRAPH_BLEND_SRCBLEND_ONE 0x2 -#define NV4_PGRAPH_BLEND_SRCBLEND_SRCCOLOR 0x3 -#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCCOLOR 0x4 -#define NV4_PGRAPH_BLEND_SRCBLEND_SRCALPHA 0x5 -#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCALPHA 0x6 -#define NV4_PGRAPH_BLEND_SRCBLEND_DESTALPHA 0x7 -#define NV4_PGRAPH_BLEND_SRCBLEND_INVDESTALPHA 0x8 -#define NV4_PGRAPH_BLEND_SRCBLEND_DESTCOLOR 0x9 -#define NV4_PGRAPH_BLEND_SRCBLEND_INVDESTCOLOR 0xA -#define NV4_PGRAPH_BLEND_SRCBLEND_SRCALPHASAT 0xB -#define NV4_PGRAPH_BLEND_SRCBLEND_INVSRCALPHASAT 0xC -#define NV4_PGRAPH_BLEND_SRCBLEND_BETA 0xD -#define NV4_PGRAPH_BLEND_DESTBLEND 28 -#define NV4_PGRAPH_BLEND_DESTBLEND_ZERO 0x1 -#define NV4_PGRAPH_BLEND_DESTBLEND_ONE 0x2 -#define NV4_PGRAPH_BLEND_DESTBLEND_SRCCOLOR 0x3 -#define NV4_PGRAPH_BLEND_DESTBLEND_INVSRCCOLOR 0x4 -#define NV4_PGRAPH_BLEND_DESTBLEND_SRCALPHA 0x5 -#define NV4_PGRAPH_BLEND_DESTBLEND_INVSRCALPHA 0x6 -#define NV4_PGRAPH_BLEND_DESTBLEND_DESTALPHA 0x7 -#define NV4_PGRAPH_BLEND_DESTBLEND_INVDESTALPHA 0x8 -#define NV4_PGRAPH_BLEND_DESTBLEND_DESTCOLOR 0x9 -#define NV4_PGRAPH_BLEND_DESTBLEND_INVDESTCOLOR 0xA -#define NV4_PGRAPH_BLEND_DESTBLEND_SRCALPHASAT 0xB -#define NV4_PGRAPH_DPRAM_INDEX 0x400828 -#define NV4_PGRAPH_DPRAM_INDEX_ADRS 0 -#define NV4_PGRAPH_DPRAM_INDEX_ADRS_0 0x0 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT 8 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x0 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x1 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x2 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x3 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x4 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x5 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x6 -#define NV4_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x7 -#define NV4_PGRAPH_DPRAM_DATA 0x40082c -#define NV4_PGRAPH_DPRAM_DATA_VALUE 0 -#define NV4_PGRAPH_DPRAM_ADRS_0 0x40082c -#define NV4_PGRAPH_DPRAM_ADRS_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_ADRS_0_VALUE 0 -#define NV4_PGRAPH_DPRAM_ADRS_1 0x40082c -#define NV4_PGRAPH_DPRAM_ADRS_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_ADRS_1_VALUE 0 -#define NV4_PGRAPH_DPRAM_DATA_0 0x40082c -#define NV4_PGRAPH_DPRAM_DATA_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_DATA_0_VALUE 0 -#define NV4_PGRAPH_DPRAM_DATA_1 0x40082c -#define NV4_PGRAPH_DPRAM_DATA_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_DATA_1_VALUE 0 -#define NV4_PGRAPH_DPRAM_WE_0 0x40082c -#define NV4_PGRAPH_DPRAM_WE_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_WE_0_VALUE 0 -#define NV4_PGRAPH_DPRAM_WE_1 0x40082c -#define NV4_PGRAPH_DPRAM_WE_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_WE_1_VALUE 0 -#define NV4_PGRAPH_DPRAM_ALPHA_0 0x40082c -#define NV4_PGRAPH_DPRAM_ALPHA_0_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_ALPHA_0_VALUE 0 -#define NV4_PGRAPH_DPRAM_ALPHA_1 0x40082c -#define NV4_PGRAPH_DPRAM_ALPHA_1_ALIAS_1 NV_PGRAPH_DPRAM_DATA -#define NV4_PGRAPH_DPRAM_ALPHA_1_VALUE 0 -#define NV4_PGRAPH_STORED_FMT 0x400830 -#define NV4_PGRAPH_STORED_FMT_MONO0 0 -#define NV4_PGRAPH_STORED_FMT_PATT0 8 -#define NV4_PGRAPH_STORED_FMT_PATT1 16 -#define NV4_PGRAPH_STORED_FMT_CHROMA 24 -#define NV4_PGRAPH_FORMATS 0x400618 -#define NV4_PGRAPH_FORMATS_ROP 0 -#define NV4_PGRAPH_FORMATS_ROP_Y8 0x0 -#define NV4_PGRAPH_FORMATS_ROP_RGB15 0x1 -#define NV4_PGRAPH_FORMATS_ROP_RGB16 0x2 -#define NV4_PGRAPH_FORMATS_ROP_Y16 0x3 -#define NV4_PGRAPH_FORMATS_ROP_INVALID 0x4 -#define NV4_PGRAPH_FORMATS_ROP_RGB24 0x5 -#define NV4_PGRAPH_FORMATS_ROP_RGB30 0x6 -#define NV4_PGRAPH_FORMATS_ROP_Y32 0x7 -#define NV4_PGRAPH_FORMATS_SRC 4 -#define NV4_PGRAPH_FORMATS_SRC_INVALID 0x0 -#define NV4_PGRAPH_FORMATS_SRC_LE_Y8 0x1 -#define NV4_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x2 -#define NV4_PGRAPH_FORMATS_SRC_LE_X24Y8 0x3 -#define NV4_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x6 -#define NV4_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x7 -#define NV4_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x8 -#define NV4_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x9 -#define NV4_PGRAPH_FORMATS_SRC_LE_R5G6B5 0xA -#define NV4_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0xB -#define NV4_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0xC -#define NV4_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0xD -#define NV4_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0xE -#define NV4_PGRAPH_FORMATS_SRC_LE_Y16 0xF -#define NV4_PGRAPH_FORMATS_SRC_LE_A16Y16 0x10 -#define NV4_PGRAPH_FORMATS_SRC_LE_X16Y16 0x11 -#define NV4_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x12 -#define NV4_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x13 -#define NV4_PGRAPH_FORMATS_SRC_LE_Y32 0x14 -#define NV4_PGRAPH_FORMATS_FB 12 -#define NV4_PGRAPH_FORMATS_FB_INVALID 0x0 -#define NV4_PGRAPH_FORMATS_FB_Y8 0x1 -#define NV4_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x2 -#define NV4_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x3 -#define NV4_PGRAPH_FORMATS_FB_A1R5G5B5 0x4 -#define NV4_PGRAPH_FORMATS_FB_R5G6B5 0x5 -#define NV4_PGRAPH_FORMATS_FB_Y16 0x6 -#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x7 -#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x8 -#define NV4_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x9 -#define NV4_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0xA -#define NV4_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0xB -#define NV4_PGRAPH_FORMATS_FB_A8R8G8B8 0xC -#define NV4_PGRAPH_FORMATS_FB_Y32 0xD -#define NV4_PGRAPH_FORMATS_FB_V8YB8U8YA8 0xE -#define NV4_PGRAPH_FORMATS_FB_YB8V8YA8U8 0xF -#define NV4_PGRAPH_ABS_X_RAM(i) (0x400400+(i)*4) -#define NV4_PGRAPH_ABS_X_RAM_SIZE_1 32 -#define NV4_PGRAPH_ABS_X_RAM_VALUE 0 -#define NV4_PGRAPH_X_RAM_BPORT(i) (0x400c00+(i)*4) -#define NV4_PGRAPH_X_RAM_BPORT_SIZE_1 32 -#define NV4_PGRAPH_X_RAM_BPORT_VALUE 0 -#define NV4_PGRAPH_ABS_Y_RAM(i) (0x400480+(i)*4) -#define NV4_PGRAPH_ABS_Y_RAM_SIZE_1 32 -#define NV4_PGRAPH_ABS_Y_RAM_VALUE 0 -#define NV4_PGRAPH_Y_RAM_BPORT(i) (0x400c80+(i)*4) -#define NV4_PGRAPH_Y_RAM_BPORT_SIZE_1 32 -#define NV4_PGRAPH_Y_RAM_BPORT_VALUE 0 -#define NV4_PGRAPH_XY_LOGIC_MISC0 0x400514 -#define NV4_PGRAPH_XY_LOGIC_MISC0_COUNTER 0 -#define NV4_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20 -#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC0_INDEX 28 -#define NV4_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1 0x400518 -#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL 0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4 -#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5 -#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC2 0x40051C -#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4 -#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5 -#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC3 0x400520 -#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0 -#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4 -#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8 -#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x1 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 16 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x0 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 24 -#define NV4_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x0 -#define NV4_PGRAPH_X_MISC 0x400500 -#define NV4_PGRAPH_X_MISC_BIT33_0 0 -#define NV4_PGRAPH_X_MISC_BIT33_0_0 0x0 -#define NV4_PGRAPH_X_MISC_BIT33_1 1 -#define NV4_PGRAPH_X_MISC_BIT33_1_0 0x0 -#define NV4_PGRAPH_X_MISC_BIT33_2 2 -#define NV4_PGRAPH_X_MISC_BIT33_2_0 0x0 -#define NV4_PGRAPH_X_MISC_BIT33_3 3 -#define NV4_PGRAPH_X_MISC_BIT33_3_0 0x0 -#define NV4_PGRAPH_X_MISC_RANGE_0 4 -#define NV4_PGRAPH_X_MISC_RANGE_0_0 0x0 -#define NV4_PGRAPH_X_MISC_RANGE_1 5 -#define NV4_PGRAPH_X_MISC_RANGE_1_0 0x0 -#define NV4_PGRAPH_X_MISC_RANGE_2 6 -#define NV4_PGRAPH_X_MISC_RANGE_2_0 0x0 -#define NV4_PGRAPH_X_MISC_RANGE_3 7 -#define NV4_PGRAPH_X_MISC_RANGE_3_0 0x0 -#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT 28 -#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x0 -#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x1 -#define NV4_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x2 -#define NV4_PGRAPH_Y_MISC 0x400504 -#define NV4_PGRAPH_Y_MISC_BIT33_0 0 -#define NV4_PGRAPH_Y_MISC_BIT33_0_0 0x0 -#define NV4_PGRAPH_Y_MISC_BIT33_1 1 -#define NV4_PGRAPH_Y_MISC_BIT33_1_0 0x0 -#define NV4_PGRAPH_Y_MISC_BIT33_2 2 -#define NV4_PGRAPH_Y_MISC_BIT33_2_0 0x0 -#define NV4_PGRAPH_Y_MISC_BIT33_3 3 -#define NV4_PGRAPH_Y_MISC_BIT33_3_0 0x0 -#define NV4_PGRAPH_Y_MISC_RANGE_0 4 -#define NV4_PGRAPH_Y_MISC_RANGE_0_0 0x0 -#define NV4_PGRAPH_Y_MISC_RANGE_1 5 -#define NV4_PGRAPH_Y_MISC_RANGE_1_0 0x0 -#define NV4_PGRAPH_Y_MISC_RANGE_2 6 -#define NV4_PGRAPH_Y_MISC_RANGE_2_0 0x0 -#define NV4_PGRAPH_Y_MISC_RANGE_3 7 -#define NV4_PGRAPH_Y_MISC_RANGE_3_0 0x0 -#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT 28 -#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x0 -#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x1 -#define NV4_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x2 -#define NV4_PGRAPH_ABS_UCLIP_XMIN 0x40053C -#define NV4_PGRAPH_ABS_UCLIP_XMIN_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIP_XMAX 0x400544 -#define NV4_PGRAPH_ABS_UCLIP_XMAX_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIP_YMIN 0x400540 -#define NV4_PGRAPH_ABS_UCLIP_YMIN_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIP_YMAX 0x400548 -#define NV4_PGRAPH_ABS_UCLIP_YMAX_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIPA_XMIN 0x400560 -#define NV4_PGRAPH_ABS_UCLIPA_XMIN_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIPA_XMAX 0x400568 -#define NV4_PGRAPH_ABS_UCLIPA_XMAX_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIPA_YMIN 0x400564 -#define NV4_PGRAPH_ABS_UCLIPA_YMIN_VALUE 0 -#define NV4_PGRAPH_ABS_UCLIPA_YMAX 0x40056C -#define NV4_PGRAPH_ABS_UCLIPA_YMAX_VALUE 0 -#define NV4_PGRAPH_SOURCE_COLOR 0x40050C -#define NV4_PGRAPH_SOURCE_COLOR_VALUE 0 -#define NV4_PGRAPH_SOURCE_COLOR_VALUE_0 0x0 -#define NV4_PGRAPH_VALID1 0x400508 -#define NV4_PGRAPH_VALID1_VLD 0 -#define NV4_PGRAPH_VALID1_VLD_0 0x0 -#define NV4_PGRAPH_VALID1_VLD_NOCLIP (0x1<<19) -#define NV4_PGRAPH_VALID1_VLD_SRCCOLOR (0x1<<16) -#define NV4_PGRAPH_VALID1_VLD_GOTMOVE (0x1<<21) -#define NV4_PGRAPH_VALID1_VLD_GOTX01 (0x3<<0) -#define NV4_PGRAPH_VALID1_VLD_GOTX02 (0x7<<0) -#define NV4_PGRAPH_VALID1_VLD_GOTX03 (0xF<<0) -#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN01 (0x3<<4) -#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN02 (0x7<<4) -#define NV4_PGRAPH_VALID1_VLD_GOTXCHAIN03 (0xF<<4) -#define NV4_PGRAPH_VALID1_VLD_GOTY01 (0x3<<8) -#define NV4_PGRAPH_VALID1_VLD_GOTY02 (0x7<<8) -#define NV4_PGRAPH_VALID1_VLD_GOTY03 (0xF<<8) -#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN01 (0x3<<12) -#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN02 (0x7<<12) -#define NV4_PGRAPH_VALID1_VLD_GOTYCHAIN03 (0xF<<12) -#define NV4_PGRAPH_VALID1_VLD_X_OFFSET (0x1<<0) -#define NV4_PGRAPH_VALID1_VLD_XCHAIN_OFFSET (0x1<<4) -#define NV4_PGRAPH_VALID1_VLD_Y_OFFSET (0x1<<8) -#define NV4_PGRAPH_VALID1_VLD_YCHAIN_OFFSET (0x1<<12) -#define NV4_PGRAPH_VALID1_VLD_GOTCOLOR0 (0x1<<17) -#define NV4_PGRAPH_VALID1_VLD_GOTCOLOR1 (0x1<<18) -#define NV4_PGRAPH_VALID1_VLD_GOTCLIP (0x1<<20) -#define NV4_PGRAPH_VALID1_VLD_GOTFONT (0x1<<22) -#define NV4_PGRAPH_VALID1_VLD_GOTOFFSET (0x1<<22) -#define NV4_PGRAPH_VALID1_VLD_GOTBPITCH (0x1<<2) -#define NV4_PGRAPH_VALID1_VLD_GOTBOFFSET (0x1<<3) -#define NV4_PGRAPH_VALID1_VLD_GOTDUDX (0x1<<4) -#define NV4_PGRAPH_VALID1_VLD_GOTDVDY (0x1<<5) -#define NV4_PGRAPH_VALID1_VLD_GOTPOINT (0x1<<8) -#define NV4_PGRAPH_VALID1_VLD_GOTSIZE (0x1<<9) -#define NV4_PGRAPH_VALID1_VLD_GOTPITCH (0x1<<10) -#define NV4_PGRAPH_VALID1_VLD_GOTSTART (0x1<<11) -#define NV4_PGRAPH_VALID1_VLD_GOTDUDX2 (0x1<<12) -#define NV4_PGRAPH_VALID1_VLD_GOTDVDY2 (0x1<<13) -#define NV4_PGRAPH_VALID1_VLD_GOTPOINT2 (0x1<<14) -#define NV4_PGRAPH_VALID1_VLD_GOTSIZE2 (0x1<<15) -#define NV4_PGRAPH_VALID1_VLD_GOTPITCH2 (0x1<<16) -#define NV4_PGRAPH_VALID1_VLD_GOTSTART2 (0x1<<17) -#define NV4_PGRAPH_VALID1_VLD_GOTOFFSIN (0x1<<0) -#define NV4_PGRAPH_VALID1_VLD_GOTOFFSOUT (0x1<<1) -#define NV4_PGRAPH_VALID1_VLD_GOTPITCHIN (0x1<<2) -#define NV4_PGRAPH_VALID1_VLD_GOTPITCHOUT (0x1<<3) -#define NV4_PGRAPH_VALID1_VLD_GOTLENGTH (0x1<<4) -#define NV4_PGRAPH_VALID1_VLD_GOTCOUNT (0x1<<5) -#define NV4_PGRAPH_VALID1_VLD_GOTFORMAT (0x1<<6) -#define NV4_PGRAPH_VALID1_VLD_GOTNOTIFY (0x1<<7) -#define NV4_PGRAPH_VALID1_CLIP_MIN 28 -#define NV4_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x0 -#define NV4_PGRAPH_VALID1_CLIP_MIN_ONLY 0x1 -#define NV4_PGRAPH_VALID1_CLIPA_MIN 29 -#define NV4_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x0 -#define NV4_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x1 -#define NV4_PGRAPH_VALID1_CLIP_MAX 30 -#define NV4_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x0 -#define NV4_PGRAPH_VALID1_CLIP_MAX_ONLY 0x1 -#define NV4_PGRAPH_VALID1_CLIPA_MAX 31 -#define NV4_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x0 -#define NV4_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x1 -#define NV4_PGRAPH_VALID2 0x400578 -#define NV4_PGRAPH_VALID2_VLD2 0 -#define NV4_PGRAPH_VALID2_VLD2_0 0x0 -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE0A (1<<28) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE0C (1<<27) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE1A (1<<26) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBINE1C (1<<25) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COMBFACTOR (1<<24) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FILTER1 (1<<23) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_OFFSET1 (1<<22) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FORMAT1 (1<<21) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_BLEND (1<<20) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL2 (1<<19) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL1 (1<<18) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_CONTROL0 (1<<17) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FILTER0 (1<<16) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FORMAT0 (1<<15) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_OFFSET0 (1<<14) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_FOGCOLOR (1<<13) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COLORKEY (1<<12) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_V1 (1<<9) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_U1 (1<<8) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_V0 (1<<7) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_U0 (1<<6) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_X (1<<5) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_Y (1<<4) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_ZETA (1<<3) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_M (1<<2) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_COLOR (1<<1) -#define NV4_PGRAPH_VALID2_VLD2_GOT3D_SPECULAR (1<<0) -#define NV4_PGRAPH_VALID2_VLD2_DX3FULLVERTEX (0x7f<<0) -#define NV4_PGRAPH_VALID2_VLD2_DX5FULLVERTEX (0x7f<<0) -#define NV4_PGRAPH_VALID2_VLD2_DX6FULLVERTEX (0x1ff<<0) -#define NV4_PGRAPH_VALID2_VLD2_DX3FULLSTATE (0x3f<<13) -#define NV4_PGRAPH_VALID2_VLD2_DX5FULLSTATE (0x1ff<<12) -#define NV4_PGRAPH_VALID2_VLD2_DX6FULLSTATE (0xFfff<<13) -#define NV4_PGRAPH_ABS_ICLIP_XMAX 0x400534 -#define NV4_PGRAPH_ABS_ICLIP_XMAX_VALUE 0 -#define NV4_PGRAPH_ABS_ICLIP_YMAX 0x400538 -#define NV4_PGRAPH_ABS_ICLIP_YMAX_VALUE 0 -#define NV4_PGRAPH_CLIPX_0 0x400524 -// Valid for all clips! -#define NV4_PGRAPH_CLIP_CONDITION_IS_GT 0x0 -#define NV4_PGRAPH_CLIP_CONDITION_IS_LT 0x1 -#define NV4_PGRAPH_CLIP_CONDITION_IS_EQ 0x2 -#define NV4_PGRAPH_CLIPX_0_CLIP0_MIN 0 -#define NV4_PGRAPH_CLIPX_0_CLIP0_MAX 2 -#define NV4_PGRAPH_CLIPX_0_CLIP1_MIN 4 -#define NV4_PGRAPH_CLIPX_0_CLIP1_MAX 6 -#define NV4_PGRAPH_CLIPX_0_CLIP2_MIN 8 -#define NV4_PGRAPH_CLIPX_0_CLIP2_MAX 10 -#define NV4_PGRAPH_CLIPX_0_CLIP3_MIN 12 -#define NV4_PGRAPH_CLIPX_0_CLIP3_MAX 14 -#define NV4_PGRAPH_CLIPX_0_CLIP4_MIN 16 -#define NV4_PGRAPH_CLIPX_0_CLIP4_MAX 18 -#define NV4_PGRAPH_CLIPX_0_CLIP5_MIN 20 -#define NV4_PGRAPH_CLIPX_0_CLIP5_MAX 22 -#define NV4_PGRAPH_CLIPX_0_CLIP6_MIN 24 -#define NV4_PGRAPH_CLIPX_0_CLIP6_MAX 26 -#define NV4_PGRAPH_CLIPX_0_CLIP7_MIN 28 -#define NV4_PGRAPH_CLIPX_0_CLIP7_MAX 30 -#define NV4_PGRAPH_CLIPX_1 0x400528 -#define NV4_PGRAPH_CLIPX_1_CLIP8_MIN 0 -#define NV4_PGRAPH_CLIPX_1_CLIP8_MAX 2 -#define NV4_PGRAPH_CLIPX_1_CLIP9_MIN 4 -#define NV4_PGRAPH_CLIPX_1_CLIP9_MAX 6 -#define NV4_PGRAPH_CLIPX_1_CLIP10_MIN 8 -#define NV4_PGRAPH_CLIPX_1_CLIP10_MAX 10 -#define NV4_PGRAPH_CLIPX_1_CLIP11_MIN 12 -#define NV4_PGRAPH_CLIPX_1_CLIP11_MAX 14 -#define NV4_PGRAPH_CLIPX_1_CLIP12_MIN 16 -#define NV4_PGRAPH_CLIPX_1_CLIP12_MAX 18 -#define NV4_PGRAPH_CLIPX_1_CLIP13_MIN 20 -#define NV4_PGRAPH_CLIPX_1_CLIP13_MAX 22 -#define NV4_PGRAPH_CLIPX_1_CLIP14_MIN 24 -#define NV4_PGRAPH_CLIPX_1_CLIP14_MAX 26 -#define NV4_PGRAPH_CLIPX_1_CLIP15_MIN 28 -#define NV4_PGRAPH_CLIPX_1_CLIP15_MAX 30 -#define NV4_PGRAPH_CLIPY_0 0x40052c -#define NV4_PGRAPH_CLIPY_0_CLIP0_MIN 0 -#define NV4_PGRAPH_CLIPY_0_CLIP0_MAX 2 -#define NV4_PGRAPH_CLIPY_0_CLIP1_MIN 4 -#define NV4_PGRAPH_CLIPY_0_CLIP1_MAX 6 -#define NV4_PGRAPH_CLIPY_0_CLIP2_MIN 8 -#define NV4_PGRAPH_CLIPY_0_CLIP2_MAX 10 -#define NV4_PGRAPH_CLIPY_0_CLIP3_MIN 12 -#define NV4_PGRAPH_CLIPY_0_CLIP3_MAX 14 -#define NV4_PGRAPH_CLIPY_0_CLIP4_MIN 16 -#define NV4_PGRAPH_CLIPY_0_CLIP4_MAX 18 -#define NV4_PGRAPH_CLIPY_0_CLIP5_MIN 20 -#define NV4_PGRAPH_CLIPY_0_CLIP5_MAX 22 -#define NV4_PGRAPH_CLIPY_0_CLIP6_MIN 24 -#define NV4_PGRAPH_CLIPY_0_CLIP6_MAX 26 -#define NV4_PGRAPH_CLIPY_0_CLIP7_MIN 28 -#define NV4_PGRAPH_CLIPY_0_CLIP7_MAX 30 -#define NV4_PGRAPH_CLIPY_1 0x400530 -#define NV4_PGRAPH_CLIPY_1_CLIP8_MIN 0 -#define NV4_PGRAPH_CLIPY_1_CLIP8_MAX 2 -#define NV4_PGRAPH_CLIPY_1_CLIP9_MIN 4 -#define NV4_PGRAPH_CLIPY_1_CLIP9_MAX 6 -#define NV4_PGRAPH_CLIPY_1_CLIP10_MIN 8 -#define NV4_PGRAPH_CLIPY_1_CLIP10_MAX 10 -#define NV4_PGRAPH_CLIPY_1_CLIP11_MIN 12 -#define NV4_PGRAPH_CLIPY_1_CLIP11_MAX 14 -#define NV4_PGRAPH_CLIPY_1_CLIP12_MIN 16 -#define NV4_PGRAPH_CLIPY_1_CLIP12_MAX 18 -#define NV4_PGRAPH_CLIPY_1_CLIP13_MIN 20 -#define NV4_PGRAPH_CLIPY_1_CLIP13_MAX 22 -#define NV4_PGRAPH_CLIPY_1_CLIP14_MIN 24 -#define NV4_PGRAPH_CLIPY_1_CLIP14_MAX 26 -#define NV4_PGRAPH_CLIPY_1_CLIP15_MIN 28 -#define NV4_PGRAPH_CLIPY_1_CLIP15_MAX 30 -#define NV4_PGRAPH_MISC24_0 0x400510 -#define NV4_PGRAPH_MISC24_0_VALUE 0 -#define NV4_PGRAPH_MISC24_1 0x400570 -#define NV4_PGRAPH_MISC24_1_VALUE 0 -#define NV4_PGRAPH_MISC24_2 0x400574 -#define NV4_PGRAPH_MISC24_2_VALUE 0 -#define NV4_PGRAPH_PASSTHRU_0 0x40057C -#define NV4_PGRAPH_PASSTHRU_0_VALUE 0 -#define NV4_PGRAPH_PASSTHRU_1 0x400580 -#define NV4_PGRAPH_PASSTHRU_1_VALUE 0 -#define NV4_PGRAPH_PASSTHRU_2 0x400584 -#define NV4_PGRAPH_PASSTHRU_2_VALUE 0 -#define NV4_PGRAPH_U_RAM(i) (0x400d00+(i)*4) -#define NV4_PGRAPH_U_RAM_SIZE_1 16 -#define NV4_PGRAPH_U_RAM_VALUE 6 -#define NV4_PGRAPH_V_RAM(i) (0x400d40+(i)*4) -#define NV4_PGRAPH_V_RAM_SIZE_1 16 -#define NV4_PGRAPH_V_RAM_VALUE 6 -#define NV4_PGRAPH_M_RAM(i) (0x400d80+(i)*4) -#define NV4_PGRAPH_M_RAM_SIZE_1 16 -#define NV4_PGRAPH_M_RAM_VALUE 6 -#define NV4_PGRAPH_D3D_XY 0x4005c0 -#define NV4_PGRAPH_D3D_XY_X_VALUE 0 -#define NV4_PGRAPH_D3D_XY_Y_VALUE 16 -#define NV4_PGRAPH_D3D_U0 0x4005c4 -#define NV4_PGRAPH_D3D_U0_VALUE 6 -#define NV4_PGRAPH_D3D_V0 0x4005c8 -#define NV4_PGRAPH_D3D_V0_VALUE 6 -#define NV4_PGRAPH_D3D_U1 0x4005cc -#define NV4_PGRAPH_D3D_U1_VALUE 6 -#define NV4_PGRAPH_D3D_V1 0x4005d0 -#define NV4_PGRAPH_D3D_V1_VALUE 6 -#define NV4_PGRAPH_D3D_ZETA 0x4005d4 -#define NV4_PGRAPH_D3D_ZETA_VALUE 0 -#define NV4_PGRAPH_D3D_RGB 0x4005d8 -#define NV4_PGRAPH_D3D_RGB_VALUE 0 -#define NV4_PGRAPH_D3D_S 0x4005dc -#define NV4_PGRAPH_D3D_S_VALUE 0 -#define NV4_PGRAPH_D3D_M 0x4005e0 -#define NV4_PGRAPH_D3D_M_VALUE 6 -#define NV4_PGRAPH_FORMAT0 0x4005A8 -#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA 1 -#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA_A 0x0 -#define NV4_PGRAPH_FORMAT0_CONTEXT_DMA_B 0x1 -#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE 2 -#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE_FALSE 0x0 -#define NV4_PGRAPH_FORMAT0_COLORKEYENABLE_TRUE 0x1 -#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH 5 -#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH_CENTER 0x0 -#define NV4_PGRAPH_FORMAT0_ORIGIN_ZOH_CORNER 0x1 -#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH 7 -#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH_CENTER 0x0 -#define NV4_PGRAPH_FORMAT0_ORIGIN_FOH_CORNER 0x1 -#define NV4_PGRAPH_FORMAT0_COLOR 8 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_Y8 0x0 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_AY8 0x1 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_A1R5G5B5 0x2 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_X1R5G5B5 0x3 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_A4R4G4B4 0x4 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_R5G6B5 0x5 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_A8R8G8B8 0x6 -#define NV4_PGRAPH_FORMAT0_COLOR_LE_X8R8G8B8 0x7 -// 0x1-0Xf used for 1-16 mipmap levels -#define NV4_PGRAPH_FORMAT0_MIPMAP_LEVELS 12 -#define NV4_PGRAPH_FORMAT0_MIPMAP_LEVELS_INVALID 0x0 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U 16 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_1 0x0 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_2 0x1 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_4 0x2 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_8 0x3 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_16 0x4 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_32 0x5 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_64 0x6 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_128 0x7 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_256 0x8 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_512 0x9 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_1024 0xA -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_U_2048 0xB -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V 20 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_1 0x0 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_2 0x1 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_4 0x2 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_8 0x3 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_16 0x4 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_32 0x5 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_64 0x6 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_128 0x7 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_256 0x8 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_512 0x9 -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_1024 0xA -#define NV4_PGRAPH_FORMAT0_BASE_SIZE_V_2048 0xB -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU 24 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_WRAP 0x1 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_MIRROR 0x2 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_CLAMP 0x3 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSU_BORDER 0x4 -#define NV4_PGRAPH_FORMAT0_WRAPU 27 -#define NV4_PGRAPH_FORMAT0_WRAPU_FALSE 0x0 -#define NV4_PGRAPH_FORMAT0_WRAPU_TRUE 0x1 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV 28 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_WRAP 0x1 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_MIRROR 0x2 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_CLAMP 0x3 -#define NV4_PGRAPH_FORMAT0_TEXTUREADDRESSV_BORDER 0x4 -#define NV4_PGRAPH_FORMAT0_WRAPV 31 -#define NV4_PGRAPH_FORMAT0_WRAPV_FALSE 0x0 -#define NV4_PGRAPH_FORMAT0_WRAPV_TRUE 0x1 -#define NV4_PGRAPH_FORMAT1 0x4005AC -#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA 1 -#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA_A 0x0 -#define NV4_PGRAPH_FORMAT1_CONTEXT_DMA_B 0x1 -#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE 2 -#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE_FALSE 0x0 -#define NV4_PGRAPH_FORMAT1_COLORKEYENABLE_TRUE 0x1 -#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH 5 -#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH_CENTER 0x0 -#define NV4_PGRAPH_FORMAT1_ORIGIN_ZOH_CORNER 0x1 -#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH 7 -#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH_CENTER 0x0 -#define NV4_PGRAPH_FORMAT1_ORIGIN_FOH_CORNER 0x1 -#define NV4_PGRAPH_FORMAT1_COLOR 8 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_Y8 0x0 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_AY8 0x1 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_A1R5G5B5 0x2 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_X1R5G5B5 0x3 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_A4R4G4B4 0x4 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_R5G6B5 0x5 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_A8R8G8B8 0x6 -#define NV4_PGRAPH_FORMAT1_COLOR_LE_X8R8G8B8 0x7 -// 15:12 = number of mipmap levels (1-15. 0 = invalid). Stupid defines removed here -#define NV4_PGRAPH_FORMAT1_MIPMAP_LEVELS 12 -#define NV4_PGRAPH_FORMAT1_MIPMAP_LEVELS_INVALID 0x0 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U 16 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_1 0x0 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_2 0x1 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_4 0x2 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_8 0x3 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_16 0x4 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_32 0x5 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_64 0x6 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_128 0x7 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_256 0x8 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_512 0x9 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_1024 0xA -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_U_2048 0xB -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V 20 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_1 0x0 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_2 0x1 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_4 0x2 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_8 0x3 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_16 0x4 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_32 0x5 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_64 0x6 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_128 0x7 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_256 0x8 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_512 0x9 -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_1024 0xA -#define NV4_PGRAPH_FORMAT1_BASE_SIZE_V_2048 0xB -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU 24 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_WRAP 0x1 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_MIRROR 0x2 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_CLAMP 0x3 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSU_BORDER 0x4 -#define NV4_PGRAPH_FORMAT1_WRAPU 27 -#define NV4_PGRAPH_FORMAT1_WRAPU_TRUE 0x1 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV 28 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_WRAP 0x1 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_MIRROR 0x2 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_CLAMP 0x3 -#define NV4_PGRAPH_FORMAT1_TEXTUREADDRESSV_BORDER 0x4 -#define NV4_PGRAPH_FORMAT1_WRAPV 31 -#define NV4_PGRAPH_FORMAT1_WRAPV_TRUE 0x1 -#define NV4_PGRAPH_FILTER0 0x4005B0 -#define NV4_PGRAPH_FILTER0_KERNEL_SIZE_X 1 -#define NV4_PGRAPH_FILTER0_KERNEL_SIZE_Y 9 -#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE 15 -#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE_FALSE 0x0 -#define NV4_PGRAPH_FILTER0_MIPMAP_DITHER_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_FILTER0_MIPMAPLODBIAS 16 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN 24 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN_NEAREST 0x1 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEAR 0x2 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN_MIPNEAREST 0x3 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN_MIPLINEAR 0x4 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEARMIPNEAREST 0x5 -#define NV4_PGRAPH_FILTER0_TEXTUREMIN_LINEARMIPLINEAR 0x6 -#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MIN_ENABLE 27 -#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MIN_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG 28 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG_NEAREST 0x1 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEAR 0x2 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG_MIPNEAREST 0x3 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG_MIPLINEAR 0x4 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEARMIPNEAREST 0x5 -#define NV4_PGRAPH_FILTER0_TEXTUREMAG_LINEARMIPLINEAR 0x6 -#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MAG_ENABLE 31 -#define NV4_PGRAPH_FILTER0_ANISOTROPIC_MAG_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_FILTER1 0x4005B4 -#define NV4_PGRAPH_FILTER1_KERNEL_SIZE_X 1 -#define NV4_PGRAPH_FILTER1_KERNEL_SIZE_Y 9 -#define NV4_PGRAPH_FILTER1_MIPMAP_DITHER_ENABLE 15 -#define NV4_PGRAPH_FILTER1_MIPMAP_DITHER_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_FILTER1_MIPMAPLODBIAS 16 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN 24 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN_NEAREST 0x1 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEAR 0x2 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN_MIPNEAREST 0x3 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN_MIPLINEAR 0x4 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEARMIPNEAREST 0x5 -#define NV4_PGRAPH_FILTER1_TEXTUREMIN_LINEARMIPLINEAR 0x6 -#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MIN_ENABLE 27 -#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MIN_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG 28 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG_NEAREST 0x1 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEAR 0x2 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG_MIPNEAREST 0x3 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG_MIPLINEAR 0x4 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEARMIPNEAREST 0x5 -#define NV4_PGRAPH_FILTER1_TEXTUREMAG_LINEARMIPLINEAR 0x6 -#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MAG_ENABLE 31 -#define NV4_PGRAPH_FILTER1_ANISOTROPIC_MAG_ENABLE_TRUE 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA 0x400590 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0 0 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_0_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0 4:2 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_0_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1 8 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_1_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1 10 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_1_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2 16 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_2_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2 18 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_2_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3 24 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0ALPHA_INVERSE_3_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3 26 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0ALPHA_ARGUMENT_3_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION 29 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD 0x1 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD2 0x2 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADD4 0x3 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDSIGNED 0x4 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_MUX 0x5 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDCOMPLEMENT 0x6 -#define NV4_PGRAPH_COMBINE0ALPHA_OPERATION_ADDSIGNED2 0x7 -#define NV4_PGRAPH_COMBINE0COLOR 0x400594 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0 0 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_0_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0 1 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_COLOR 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_0_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0 2 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_0_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1 8 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_1_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1 9 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1_COLOR 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_1_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1 10 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_1_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2 16 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_2_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2 17 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2_COLOR 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_2_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2 18 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_2_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3 24 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_INVERSE_3_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3 25 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3_COLOR 0x0 -#define NV4_PGRAPH_COMBINE0COLOR_ALPHA_3_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3 26 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_ZERO 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_INPUT 0x4 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE0COLOR_ARGUMENT_3_TEXTURELOD 0x7 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION 29 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD 0x1 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD2 0x2 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADD4 0x3 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDSIGNED 0x4 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_MUX 0x5 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDCOMPLEMENT 0x6 -#define NV4_PGRAPH_COMBINE0COLOR_OPERATION_ADDSIGNED2 0x7 -#define NV4_PGRAPH_COMBINE1ALPHA 0x400598 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0 0 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_0_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0 2 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_0_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1 8 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_1_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1 10 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_1_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2 16 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_2_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2 18 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_2_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3 24 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1ALPHA_INVERSE_3_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3 26 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1ALPHA_ARGUMENT_3_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION 29 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD 0x1 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD2 0x2 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADD4 0x3 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDSIGNED 0x4 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_MUX 0x5 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDCOMPLEMENT 0x6 -#define NV4_PGRAPH_COMBINE1ALPHA_OPERATION_ADDSIGNED2 0x7 -#define NV4_PGRAPH_COMBINE1COLOR 0x40059C -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0 0 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_0_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0 1 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0_COLOR 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_0_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0 4:2 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_0_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1 8 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_1_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1 9 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1_COLOR 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_1_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1 10 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_1_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2 16 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_2_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2 17 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2_COLOR 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_2_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2 18 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_2_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3 24 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3_NORMAL 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_INVERSE_3_INVERSE 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3 25 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3_COLOR 0x0 -#define NV4_PGRAPH_COMBINE1COLOR_ALPHA_3_ALPHA 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3 26 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_ZERO 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_FACTOR 0x2 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_DIFFUSE 0x3 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_INPUT 0x4 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_TEXTURE0 0x5 -#define NV4_PGRAPH_COMBINE1COLOR_ARGUMENT_3_TEXTURE1 0x6 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION 29 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD 0x1 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD2 0x2 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADD4 0x3 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDSIGNED 0x4 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_MUX 0x5 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDCOMPLEMENT 0x6 -#define NV4_PGRAPH_COMBINE1COLOR_OPERATION_ADDSIGNED2 0x7 -#define NV4_PGRAPH_DMA_START_0 0x401000 -#define NV4_PGRAPH_DMA_START_0_VALUE 0 -#define NV4_PGRAPH_DMA_START_1 0x401004 -#define NV4_PGRAPH_DMA_START_1_VALUE 0 -#define NV4_PGRAPH_DMA_LENGTH 0x401008 -#define NV4_PGRAPH_DMA_LENGTH_VALUE 0 -#define NV4_PGRAPH_DMA_MISC 0x40100C -#define NV4_PGRAPH_DMA_MISC_COUNT 0 -#define NV4_PGRAPH_DMA_MISC_FMT_SRC 16 -#define NV4_PGRAPH_DMA_MISC_FMT_DST 20 -#define NV4_PGRAPH_DMA_DATA_0 0x401020 -#define NV4_PGRAPH_DMA_DATA_0_VALUE 0 -#define NV4_PGRAPH_DMA_DATA_1 0x401024 -#define NV4_PGRAPH_DMA_DATA_1_VALUE 0 -#define NV4_PGRAPH_DMA_RM 0x401030 -#define NV4_PGRAPH_DMA_RM_ASSIST_A 0 -#define NV4_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x0 -#define NV4_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x1 -#define NV4_PGRAPH_DMA_RM_ASSIST_A_RESET 0x1 -#define NV4_PGRAPH_DMA_RM_ASSIST_B 1 -#define NV4_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x0 -#define NV4_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x1 -#define NV4_PGRAPH_DMA_RM_ASSIST_B_RESET 0x1 -#define NV4_PGRAPH_DMA_RM_WRITE_REQ 4 -#define NV4_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x0 -#define NV4_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x1 -#define NV4_PGRAPH_DMA_A_XLATE_INST 0x401040 -#define NV4_PGRAPH_DMA_A_XLATE_INST_VALUE 0 -#define NV4_PGRAPH_DMA_A_CONTROL 0x401044 -#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12 -#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x0 -#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x1 -#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13 -#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x0 -#define NV4_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x1 -#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE 16 -#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x0 -#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x2 -#define NV4_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x3 -#define NV4_PGRAPH_DMA_A_CONTROL_ADJUST 20 -#define NV4_PGRAPH_DMA_A_LIMIT 0x401048 -#define NV4_PGRAPH_DMA_A_LIMIT_OFFSET 0 -#define NV4_PGRAPH_DMA_A_TLB_PTE 0x40104C -#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS 1 -#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x0 -#define NV4_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x1 -#define NV4_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 12 -#define NV4_PGRAPH_DMA_A_TLB_TAG 0x401050 -#define NV4_PGRAPH_DMA_A_TLB_TAG_ADDRESS 12 -#define NV4_PGRAPH_DMA_A_ADJ_OFFSET 0x401054 -#define NV4_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 0 -#define NV4_PGRAPH_DMA_A_OFFSET 0x401058 -#define NV4_PGRAPH_DMA_A_OFFSET_VALUE 0 -#define NV4_PGRAPH_DMA_A_SIZE 0x40105C -#define NV4_PGRAPH_DMA_A_SIZE_VALUE 0 -#define NV4_PGRAPH_DMA_A_Y_SIZE 0x401060 -#define NV4_PGRAPH_DMA_A_Y_SIZE_VALUE 0 -#define NV4_PGRAPH_DMA_B_XLATE_INST 0x401080 -#define NV4_PGRAPH_DMA_B_XLATE_INST_VALUE 0 -#define NV4_PGRAPH_DMA_B_CONTROL 0x401084 -#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12 -#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x0 -#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x1 -#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13 -#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x0 -#define NV4_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x1 -#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE 16 -#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x0 -#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x2 -#define NV4_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x3 -#define NV4_PGRAPH_DMA_B_CONTROL_ADJUST 20 -#define NV4_PGRAPH_DMA_B_LIMIT 0x401088 -#define NV4_PGRAPH_DMA_B_LIMIT_OFFSET 0 -#define NV4_PGRAPH_DMA_B_TLB_PTE 0x40108C -#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS 1 -#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x0 -#define NV4_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x1 -#define NV4_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 12 -#define NV4_PGRAPH_DMA_B_TLB_TAG 0x401090 -#define NV4_PGRAPH_DMA_B_TLB_TAG_ADDRESS 12 -#define NV4_PGRAPH_DMA_B_ADJ_OFFSET 0x401094 -#define NV4_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 0 -#define NV4_PGRAPH_DMA_B_OFFSET 0x401098 -#define NV4_PGRAPH_DMA_B_OFFSET_VALUE 0 -#define NV4_PGRAPH_DMA_B_SIZE 0x40109C -#define NV4_PGRAPH_DMA_B_SIZE_VALUE 0 -#define NV4_PGRAPH_DMA_B_Y_SIZE 0x4010A0 -#define NV4_PGRAPH_DMA_B_Y_SIZE_VALUE 0 -#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR 0 -#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_ZOH_MS 0x0 -#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_ZOH 0x1 -#define NV4_PGRAPH_CONTROL_OUT_INTERPOLATOR_FOH 0x2 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_U 4 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_CYLINDRICAL 0x0 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_WRAP 0x1 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_MIRROR 0x2 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_U_CLAMP 0x3 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_V 6 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_CYLINDRICAL 0x0 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_WRAP 0x1 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_MIRROR 0x2 -#define NV4_PGRAPH_CONTROL_OUT_WRAP_V_CLAMP 0x3 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT 8 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT_LE_X8R8G8B8 0x0 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_FORMAT_LE_A8R8G8B8 0x1 -#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR 10 -#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_NORMAL 0x0 -#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_COLOR_INVERSE 0x1 -#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_ALPHA_INVERSE 0x2 -#define NV4_PGRAPH_CONTROL_OUT_SRCCOLOR_ALPHA_ONE 0x3 -#define NV4_PGRAPH_CONTROL_OUT_CULLING 12 -#define NV4_PGRAPH_CONTROL_OUT_CULLING_ILLEGAL 0x0 -#define NV4_PGRAPH_CONTROL_OUT_CULLING_NONE 0x1 -#define NV4_PGRAPH_CONTROL_OUT_CULLING_COUNTERCLOCKWISE 0x2 -#define NV4_PGRAPH_CONTROL_OUT_CULLING_CLOCKWISE 0x3 -#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER 15 -#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER_SCREEN 0x0 -#define NV4_PGRAPH_CONTROL_OUT_ZBUFFER_LINEAR 0x1 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE 16 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_ILLEGAL 0x0 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_FALSE 0x1 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_LT 0x2 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_EQ 0x3 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_LE 0x4 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_GT 0x5 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_NE 0x6 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_GE 0x7 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_COMPARE_TRUE 0x8 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE 20 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_NEVER 0x0 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALPHA 0x1 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALPHA_ZETA 0x2 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ZETA 0x3 -#define NV4_PGRAPH_CONTROL_OUT_ZETA_WRITE_ALWAYS 0x4 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE 24 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_NEVER 0x0 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ALPHA 0x1 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ALPHA_ZETA 0x2 -#define NV4_PGRAPH_CONTROL_OUT_COLOR_WRITE_ZETA 0x3 -#define NV4_PGRAPH_CONTROL_OUT_ROP 28 -#define NV4_PGRAPH_CONTROL_OUT_ROP_BLEND_AND 0x0 -#define NV4_PGRAPH_CONTROL_OUT_ROP_ADD_WITH_SATURATION 0x1 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA 29 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA_SRCALPHA 0x0 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_BETA_DESTCOLOR 0x1 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0 30 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0_DESTCOLOR 0x0 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT0_ZERO 0x1 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1 31 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1_SRCCOLOR 0x0 -#define NV4_PGRAPH_CONTROL_OUT_BLEND_INPUT1_ZERO 0x1 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_KEY 0 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE 8 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_ILLEGAL 0x0 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_FALSE 0x1 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_LT 0x2 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_EQ 0x3 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_LE 0x4 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_GT 0x5 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_NE 0x6 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_GE 0x7 -#define NV4_PGRAPH_ALPHACNTRL_ALPHA_COMPARE_TRUE 0x8 - -#define NV4_PVIDEO_START 0x680000 -#define NV4_PVIDEO_END 0x6802FF - -#define NV4_PVIDEO_INTR_0 0x680100 -#define NV4_PVIDEO_INTR_0_NOTIFY 0 -#define NV4_PVIDEO_INTR_0_NOTIFY_NOT_PENDING 0x0 -#define NV4_PVIDEO_INTR_0_NOTIFY_PENDING 0x1 -#define NV4_PVIDEO_INTR_0_NOTIFY_RESET 0x1 -#define NV4_PVIDEO_INTR_EN_0 0x680140 -#define NV4_PVIDEO_INTR_EN_0_NOTIFY 0 -#define NV4_PVIDEO_INTR_EN_0_NOTIFY_ENABLED 0x1 -#define NV4_PVIDEO_STEP_SIZE 0x680200 -#define NV4_PVIDEO_STEP_SIZE_X 0 -#define NV4_PVIDEO_STEP_SIZE_Y 16 -#define NV4_PVIDEO_CONTROL_Y 0x680204 -#define NV4_PVIDEO_CONTROL_Y_BLUR 0 -#define NV4_PVIDEO_CONTROL_Y_BLUR_OFF 0x0 -#define NV4_PVIDEO_CONTROL_Y_BLUR_ON 0x1 -#define NV4_PVIDEO_CONTROL_Y_LINE 4 -#define NV4_PVIDEO_CONTROL_Y_LINE_HALF 0x0 -#define NV4_PVIDEO_CONTROL_Y_LINE_FULL 0x1 -#define NV4_PVIDEO_CONTROL_X 0x680208 -#define NV4_PVIDEO_CONTROL_X_WEIGHT 0 -#define NV4_PVIDEO_CONTROL_X_WEIGHT_LIGHT 0x0 -#define NV4_PVIDEO_CONTROL_X_WEIGHT_HEAVY 0x1 -#define NV4_PVIDEO_CONTROL_X_SHARPENING 4 -#define NV4_PVIDEO_CONTROL_X_SHARPENING_OFF 0x0 -#define NV4_PVIDEO_CONTROL_X_SHARPENING_ON 0x1 -#define NV4_PVIDEO_CONTROL_X_SMOOTHING 8 -#define NV4_PVIDEO_CONTROL_X_SMOOTHING_OFF 0x0 -#define NV4_PVIDEO_CONTROL_X_SMOOTHING_ON 0x1 -#define NV4_PVIDEO_BUFF0_START 0x68020c -#define NV4_PVIDEO_BUFF0_START_ADDRESS 2 -#define NV4_PVIDEO_BUFF1_START 0x680210 -#define NV4_PVIDEO_BUFF1_START_ADDRESS 2 -#define NV4_PVIDEO_BUFF0_PITCH 0x680214 -#define NV4_PVIDEO_BUFF0_PITCH_LENGTH 4 -#define NV4_PVIDEO_BUFF1_PITCH 0x680218 -#define NV4_PVIDEO_BUFF1_PITCH_LENGTH 4 -#define NV4_PVIDEO_BUFF0_OFFSET 0x68021c -#define NV4_PVIDEO_BUFF0_OFFSET_X 0 -#define NV4_PVIDEO_BUFF0_OFFSET_Y 4 -#define NV4_PVIDEO_BUFF0_OFFSET_Y_OFF 0x0 -#define NV4_PVIDEO_BUFF0_OFFSET_Y_QUARTER 0x1 -#define NV4_PVIDEO_BUFF0_OFFSET_Y_HALF 0x2 -#define NV4_PVIDEO_BUFF1_OFFSET 0x680220 -#define NV4_PVIDEO_BUFF1_OFFSET_X 0 -#define NV4_PVIDEO_BUFF1_OFFSET_Y 4 -#define NV4_PVIDEO_BUFF1_OFFSET_Y_OFF 0x0 -#define NV4_PVIDEO_BUFF1_OFFSET_Y_QUARTER 0x1 -#define NV4_PVIDEO_BUFF1_OFFSET_Y_HALF 0x2 -#define NV4_PVIDEO_OE_STATE 0x680224 -#define NV4_PVIDEO_OE_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PVIDEO_OE_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PVIDEO_OE_STATE_BUFF0_ERROR 8 -#define NV4_PVIDEO_OE_STATE_BUFF1_ERROR 12 -#define NV4_PVIDEO_OE_STATE_BUFF0_IN_USE 16 -#define NV4_PVIDEO_OE_STATE_BUFF1_IN_USE 20 -#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER 24 -#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER_0 0x0 -#define NV4_PVIDEO_OE_STATE_CURRENT_BUFFER_1 0x1 -#define NV4_PVIDEO_SU_STATE 0x680228 -#define NV4_PVIDEO_SU_STATE_BUFF0_IN_USE 16 -#define NV4_PVIDEO_SU_STATE_BUFF1_IN_USE 20 -#define NV4_PVIDEO_RM_STATE 0x68022c -#define NV4_PVIDEO_RM_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PVIDEO_RM_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PVIDEO_WINDOW_START 0x680230 -#define NV4_PVIDEO_WINDOW_START_X 0 -#define NV4_PVIDEO_WINDOW_START_Y 16 -#define NV4_PVIDEO_WINDOW_SIZE 0x680234 -#define NV4_PVIDEO_WINDOW_SIZE_X 0 -#define NV4_PVIDEO_WINDOW_SIZE_Y 16 -#define NV4_PVIDEO_FIFO_THRES 0x680238 -#define NV4_PVIDEO_FIFO_THRES_SIZE 3 -#define NV4_PVIDEO_FIFO_BURST 0x68023c -#define NV4_PVIDEO_FIFO_BURST_LENGTH 0 -#define NV4_PVIDEO_FIFO_BURST_LENGTH_32 0x1 -#define NV4_PVIDEO_FIFO_BURST_LENGTH_64 0x2 -#define NV4_PVIDEO_FIFO_BURST_LENGTH_128 0x3 -#define NV4_PVIDEO_KEY 0x680240 -#define NV4_PVIDEO_KEY_INDEX 0 -#define NV4_PVIDEO_KEY_565 0 -#define NV4_PVIDEO_KEY_555 0 -#define NV4_PVIDEO_KEY_888 0 -#define NV4_PVIDEO_KEY_PACK 24 -#define NV4_PVIDEO_OVERLAY 0x680244 -#define NV4_PVIDEO_OVERLAY_VIDEO 0 -#define NV4_PVIDEO_OVERLAY_VIDEO_OFF 0x0 -#define NV4_PVIDEO_OVERLAY_VIDEO_ON 0x1 -#define NV4_PVIDEO_OVERLAY_KEY 4 -#define NV4_PVIDEO_OVERLAY_KEY_OFF 0x0 -#define NV4_PVIDEO_OVERLAY_KEY_ON 0x1 -#define NV4_PVIDEO_OVERLAY_FORMAT 8 -#define NV4_PVIDEO_OVERLAY_FORMAT_CCIR 0x0 -#define NV4_PVIDEO_OVERLAY_FORMAT_YUY2 0x1 -#define NV4_PVIDEO_RED_CSC 0x680280 -#define NV4_PVIDEO_RED_CSC_OFFSET 0 -#define NV4_PVIDEO_GREEN_CSC 0x680284 -#define NV4_PVIDEO_GREEN_CSC_OFFSET 0 -#define NV4_PVIDEO_BLUE_CSC 0x680288 -#define NV4_PVIDEO_BLUE_CSC_OFFSET 0 -#define NV4_PVIDEO_CSC_ADJUST 0x68028c -#define NV4_PVIDEO_CSC_ADJUST_B_FLAG 0 -#define NV4_PVIDEO_CSC_ADJUST_B_FLAG_OFF 0x0 -#define NV4_PVIDEO_CSC_ADJUST_B_FLAG_ON 0x1 -#define NV4_PVIDEO_CSC_ADJUST_G_FLAG 4 -#define NV4_PVIDEO_CSC_ADJUST_G_FLAG_OFF 0x0 -#define NV4_PVIDEO_CSC_ADJUST_G_FLAG_ON 0x1 -#define NV4_PVIDEO_CSC_ADJUST_R_FLAG 8 -#define NV4_PVIDEO_CSC_ADJUST_R_FLAG_OFF 0x0 -#define NV4_PVIDEO_CSC_ADJUST_R_FLAG_ON 0x1 -#define NV4_PVIDEO_CSC_ADJUST_L_FLAG 12 -#define NV4_PVIDEO_CSC_ADJUST_L_FLAG_OFF 0x0 -#define NV4_PVIDEO_CSC_ADJUST_L_FLAG_ON 0x1 -#define NV4_PVIDEO_CSC_ADJUST_CHROMA 16 -#define NV4_PVIDEO_CSC_ADJUST_CHROMA_OFF 0x0 -#define NV4_PVIDEO_CSC_ADJUST_CHROMA_ON 0x1 - -#define NV4_PRMCIO_START 0x601000 -#define NV4_PRMCIO_END 0x601FFF - -#define NV4_PRMCIO_INP0 0x6013c2 -#define NV4_PRMCIO_INP0_MONO 0x6013ba -#define NV4_PRMCIO_INP0_COLOR 0x6013da -#define NV4_PRMCIO_INP0_READ_MONO 0x6013ca -#define NV4_PRMCIO_INP0_WRITE_MONO 0x6013ba -#define NV4_PRMCIO_INP0_WRITE_COLOR 0x6013da -// DEFAULT = Palette -#define NV4_PRMCIO_ARX 0x6013c0 -#define NV4_PRMCIO_AR_WRITE 0x6013c0 // After ARX -#define NV4_PRMCIO_AR_READ 0x6013c1 -#define NV4_PRMCIO_AR_PALETTE_WRITE 0x6013c0 -#define NV4_PRMCIO_AR_PALETTE_READ 0x6013c1 -#define NV4_PRMCIO_AR_MODE_INDEX 0x10 -#define NV4_PRMCIO_AR_OSCAN_INDEX 0x11 -#define NV4_PRMCIO_AR_PLANE_INDEX 0x12 -#define NV4_PRMCIO_AR_HPP_INDEX 0x13 -#define NV4_PRMCIO_AR_CSEL_INDEX 0x14 -#define NV4_PRMCIO_CRX_MONO 0x6013b4 -#define NV4_PRMCIO_CRX_COLOR 0x6013d4 -#define NV4_PRMCIO_CR_MONO 0x6013b5 -#define NV4_PRMCIO_CR_COLOR 0x6013d5 -#define NV4_PRMCIO_CRE_MONO 0x6013b5 -#define NV4_PRMCIO_CRE_COLOR 0x6013d5 - -#define NV4_PCRTC_INTR_0 0x600100 -#define NV4_PCRTC_INTR_0_VBLANK 0 -#define NV4_PCRTC_INTR_0_VBLANK_NOT_PENDING 0x0 -#define NV4_PCRTC_INTR_0_VBLANK_PENDING 0x1 -#define NV4_PCRTC_INTR_0_VBLANK_RESET 0x1 -#define NV4_PCRTC_INTR_EN_0 0x600140 -#define NV4_PCRTC_INTR_EN_0_VBLANK 0 -#define NV4_PCRTC_INTR_EN_0_VBLANK_ENABLED 0x1 -#define NV4_PCRTC_START 0x600800 -#define NV4_PCRTC_START_ADDRESS 2 -#define NV4_PCRTC_CONFIG 0x600804 -#define NV4_PCRTC_CONFIG_START_ADDRESS 0 -#define NV4_PCRTC_CONFIG_START_ADDRESS_VGA 0x0 -#define NV4_PCRTC_CONFIG_START_ADDRESS_NON_VGA 0x1 -#define NV4_PCRTC_CONFIG_START_ADDRESS_HSYNC 0x2 -#define NV4_PCRTC_RASTER 0x600808 -#define NV4_PCRTC_RASTER_POSITION 0 -#define NV4_PCRTC_RASTER_SA_LOAD 12 -#define NV4_PCRTC_RASTER_SA_LOAD_DISPLAY 0x0 -#define NV4_PCRTC_RASTER_SA_LOAD_BEFORE 0x1 -#define NV4_PCRTC_RASTER_SA_LOAD_AFTER 0x2 -#define NV4_PCRTC_RASTER_VERT_BLANK 16 -#define NV4_PCRTC_RASTER_VERT_BLANK_ACTIVE 0x1 -#define NV4_PCRTC_RASTER_VERT_BLANK_INACTIVE 0x0 - -#define NV4_CIO_START 0x3B0 -#define NV4_CIO_END 0x3DF -#define NV4_CIO_SIZE NV4_CIO_END - NV4_CIO_START - - -#define NV4_CIO_INP0 0x3c2 -#define NV4_CIO_INP0_MONO 0x3ba -#define NV4_CIO_INP0_COLOR 0x3da -#define NV4_CIO_INP0_READ_MONO 0x3ca -#define NV4_CIO_INP0_WRITE_MONO 0x3ba -#define NV4_CIO_INP0_WRITE_COLOR 0x3da -#define NV4_CIO_ARX 0x3c0 // if index is not 0x10-0x13 write palette -#define NV4_CIO_AR_PALETTE_WRITE 0x3c0 -#define NV4_CIO_AR_PALETTE_READ 0x3c1 -#define NV4_CIO_AR_MODE_WRITE 0x3c0 -#define NV4_CIO_AR_MODE_READ 0x3c1 -#define NV4_CIO_AR_MODE_INDEX 0x10 -#define NV4_CIO_AR_OSCAN_WRITE 0x3c0 -#define NV4_CIO_AR_OSCAN_READ 0x3c1 -#define NV4_CIO_AR_OSCAN_INDEX 0x11 -#define NV4_CIO_AR_PLANE_WRITE 0x3c0 -#define NV4_CIO_AR_PLANE_READ 0x3c1 -#define NV4_CIO_AR_PLANE_INDEX 0x12 -#define NV4_CIO_AR_HPP_WRITE 0x3c0 -#define NV4_CIO_AR_HPP_READ 0x3c1 -#define NV4_CIO_AR_HPP_INDEX 0x13 -#define NV4_CIO_AR_CSEL_WRITE 0x3c0 -#define NV4_CIO_AR_CSEL_READ 0x3c1 -#define NV4_CIO_AR_CSEL_INDEX 0x14 -#define NV4_CIO_CRX_MONO 0x3b4 -#define NV4_CIO_CRX_COLOR 0x3d4 -#define NV4_CIO_CR_MONO 0x3b5 -#define NV4_CIO_CR_COLOR 0x3d5 -#define NV4_CIO_CR_HDT_INDEX 0x0 -#define NV4_CIO_CR_HDE_INDEX 0x1 -#define NV4_CIO_CR_HBS_INDEX 0x2 -#define NV4_CIO_CR_HBE_INDEX 0x3 -#define NV4_CIO_CR_HBE_4_0 0 -#define NV4_CIO_CR_HRS_INDEX 0x4 -#define NV4_CIO_CR_HRE_INDEX 0x5 -#define NV4_CIO_CR_HRE_HBE_5 7 -#define NV4_CIO_CR_HRE_4_0 0 -#define NV4_CIO_CR_VDT_INDEX 0x6 -#define NV4_CIO_CR_OVL_INDEX 0x7 -#define NV4_CIO_CR_OVL_VDE_8 1 -#define NV4_CIO_CR_OVL_VDE_9 6 -#define NV4_CIO_CR_OVL_VDT_8 0 -#define NV4_CIO_CR_OVL_VDT_9 5 -#define NV4_CIO_CR_OVL_VBS_8 3 -#define NV4_CIO_CR_OVL_VRS_8 2 -#define NV4_CIO_CR_OVL_VRS_9 7 -#define NV4_CIO_CR_RSAL_INDEX 0x8 -#define NV4_CIO_CR_RSAL_PANNING 5 -#define NV4_CIO_CR_CELL_HT_INDEX 0x9 -#define NV4_CIO_CR_CELL_HT_SCANDBL 7 -#define NV4_CIO_CR_CELL_HT_VBS_9 5 -#define NV4_CIO_CR_CURS_ST_INDEX 0xA -#define NV4_CIO_CR_CURS_END_INDEX 0xB -#define NV4_CIO_CR_SA_HI_INDEX 0xC -#define NV4_CIO_CR_SA_LO_INDEX 0xD -#define NV4_CIO_CR_TCOFF_HI_INDEX 0xE -#define NV4_CIO_CR_TCOFF_LO_INDEX 0xF -#define NV4_CIO_CR_VRS_INDEX 0x10 -#define NV4_CIO_CR_VRE_INDEX 0x11 -#define NV4_CIO_CR_VRE_3_0 0 -#define NV4_CIO_CR_VDE_INDEX 0x12 -#define NV4_CIO_CR_OFFSET_INDEX 0x13 -#define NV4_CIO_CR_ULINE_INDEX 0x14 -#define NV4_CIO_CR_VBS_INDEX 0x15 -#define NV4_CIO_CR_VBE_INDEX 0x16 -#define NV4_CIO_CR_MODE_INDEX 0x17 -#define NV4_CIO_CR_LCOMP_INDEX 0x18 -#define NV4_CIO_CR_GDATA_INDEX 0x22 -#define NV4_CIO_CR_ARFF_INDEX 0x24 -#define NV4_CIO_CR_ARX_INDEX 0x26 -#define NV4_CIO_CRE_MONO 0x3b5 -#define NV4_CIO_CRE_COLOR 0x3d5 -#define NV4_CIO_CRE_RPC0_INDEX 0x19 -#define NV4_CIO_CRE_RPC0_START 0 -#define NV4_CIO_CRE_RPC0_OFFSET_10_8 5 -#define NV4_CIO_CRE_RPC1_INDEX 0x1A -#define NV4_CIO_CRE_RPC1_LARGE 2 -#define NV4_CIO_CRE_FF_INDEX 0x1B -#define NV4_CIO_CRE_FF_BURST 0 -#define NV4_CIO_CRE_FF_BURST_8 0x0 -#define NV4_CIO_CRE_FF_BURST_32 0x1 -#define NV4_CIO_CRE_FF_BURST_64 0x2 -#define NV4_CIO_CRE_FF_BURST_128 0x3 -#define NV4_CIO_CRE_FF_BURST_256 0x4 -#define NV4_CIO_CRE_ENH_INDEX 0x1C -#define NV4_CIO_CRE_PAGE0_INDEX 0x1D -#define NV4_CIO_CRE_PAGE1_INDEX 0x1E -#define NV4_CIO_SR_LOCK_INDEX 0x1F -#define NV4_CIO_SR_UNLOCK_RW_VALUE 0x57 -#define NV4_CIO_SR_UNLOCK_RO_VALUE 0x75 -#define NV4_CIO_SR_LOCK_VALUE 0x99 -#define NV4_SR_UNLOCK_RW_VALUE 0x57 -#define NV4_SR_UNLOCK_RO_VALUE 0x75 -#define NV4_SR_LOCK_VALUE 0x99 -#define NV4_CIO_CRE_FFLWM_INDEX 0x20 -#define NV4_CIO_CRE_FFLWM_LWM 0 -#define NV4_CIO_CRE_FABID_INDEX 0x25 -#define NV4_CIO_CRE_LSR_INDEX 0x25 -#define NV4_CIO_CRE_LSR_VDE_10 1 -#define NV4_CIO_CRE_LSR_VDT_10 0 -#define NV4_CIO_CRE_LSR_HBE_6 4 -#define NV4_CIO_CRE_LSR_VBS_10 3 -#define NV4_CIO_CRE_LSR_VRS_10 2 -#define NV4_CIO_CRE_CHIP_ID_INDEX 0x27 -#define NV4_CIO_CRE_PIXEL_INDEX 0x28 -#define NV4_CIO_CRE_PIXEL_TV_ADJ 3 -#define NV4_CIO_CRE_PIXEL_FORMAT 0 -#define NV4_CIO_CRE_PIXEL_FORMAT_VGA 0x0 -#define NV4_CIO_CRE_PIXEL_FORMAT_8BPP 0x1 -#define NV4_CIO_CRE_PIXEL_FORMAT_16BPP 0x2 -#define NV4_CIO_CRE_PIXEL_FORMAT_32BPP 0x3 -#define NV4_CIO_CRE_PAGE_OVFL_INDEX 0x29 -#define NV4_CIO_CRE_OSCOL_INDEX 0x2A -#define NV4_CIO_CRE_SCRATCH0_INDEX 0x2B -#define NV4_CIO_CRE_SCRATCH1_INDEX 0x2C -#define NV4_CIO_CRE_HEB_INDEX 0x2D -#define NV4_CIO_CRE_HEB_SA_23 5 -#define NV4_CIO_CRE_HEB_ILC_8 4 -#define NV4_CIO_CRE_HEB_HRS_8 3 -#define NV4_CIO_CRE_HEB_HBS_8 2 -#define NV4_CIO_CRE_HEB_HDE_8 1 -#define NV4_CIO_CRE_HEB_HDT_8 0 -#define NV4_CIO_CRE_HCUR_ADDR2_INDEX 0x2f -#define NV4_CIO_CRE_HCUR_ADDR0_INDEX 0x30 -#define NV4_CIO_CRE_HCUR_ASI 7 -#define NV4_CIO_CRE_HCUR_ASI_FRAMEBUFFER 0x1 -#define NV4_CIO_CRE_HCUR_ASI_INSTMEM 0x0 -#define NV4_CIO_CRE_HCUR_ADDR0_ADR 0 -#define NV4_CIO_CRE_HCUR_ADDR1_INDEX 0x31 -#define NV4_CIO_CRE_HCUR_ADDR1_ADR 2 -#define NV4_CIO_CRE_HCUR_ADDR1_CUR_DBL 1 -#define NV4_CIO_CRE_HCUR_ADDR1_ENABLE 0 -#define NV4_CIO_CRE_VID_END0_INDEX 0x32 -#define NV4_CIO_CRE_VID_END_7_0 0 -#define NV4_CIO_CRE_VID_END1_INDEX 0x33 -#define NV4_CIO_CRE_VID_END_ENABLE 4 -#define NV4_CIO_CRE_VID_END_10_8 0 -#define NV4_CIO_CRE_RL0_INDEX 0x34 -#define NV4_CIO_CRE_RL1_INDEX 0x35 -#define NV4_CIO_CRE_RMA_INDEX 0x38 -#define NV4_CIO_CRE_ILACE_INDEX 0x39 -#define NV4_CIO_CRE_SCRATCH2_INDEX 0x3A -#define NV4_CIO_CRE_SCRATCH3_INDEX 0x3B -#define NV4_CIO_CRE_SCRATCH4_INDEX 0x3C -#define NV4_CIO_CRE_TREG_INDEX 0x3D -#define NV4_CIO_CRE_TREG_HCNT 6 -#define NV4_CIO_CRE_TREG_VCNT 4 -#define NV4_CIO_CRE_TREG_SHADOW 0 -#define NV4_CIO_CRE_TREG_HCNT_INDEX 0x0 -#define NV4_CIO_CRE_TREG_VCNTA_INDEX 0x6 -#define NV4_CIO_CRE_TREG_VCNTB_INDEX 0x7 -#define NV4_CIO_CRE_DDC_STATUS_INDEX 0x3E -#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F // Write to i2c for EDID/DDC -#define NV4_CIO_CRE_PCI_TO_INDEX 0x40 -#define NV4_CIO_CRE_PCI_TO_DELAY 0 - -#define NV4_VIO_MBEN 0x94 -#define NV4_VIO_ADDEN 0x46e8 -#define NV4_VIO_VSE1 0x102 -#define NV4_VIO_VSE2 0x3c3 -#define NV4_VIO_MISC_READ 0x3cc -#define NV4_VIO_MISC_WRITE 0x3c2 -#define NV4_VIO_SRX 0x3c4 -#define NV4_VIO_SR 0x3c5 -#define NV4_VIO_SR_RESET_INDEX 0x0 -#define NV4_VIO_SR_CLOCK_INDEX 0x1 -#define NV4_VIO_SR_PLANE_MASK_INDEX 0x2 -#define NV4_VIO_SR_CHAR_MAP_INDEX 0x3 -#define NV4_VIO_SR_MEM_MODE_INDEX 0x4 -#define NV4_VIO_GRX 0x3ce -#define NV4_VIO_GX_SR 0x3cf -#define NV4_VIO_GX_SR_INDEX 0x0 -#define NV4_VIO_GX_SREN_INDEX 0x1 -#define NV4_VIO_GX_CCOMP_INDEX 0x2 -#define NV4_VIO_GX_ROP_INDEX 0x3 -#define NV4_VIO_GX_READ_MAP_INDEX 0x4 -#define NV4_VIO_GX_MODE_INDEX 0x5 -#define NV4_VIO_GX_MISC_INDEX 0x6 -#define NV4_VIO_GX_DONT_CARE_INDEX 0x7 -#define NV4_VIO_GX_BIT_MASK_INDEX 0x8 - -#define NV4_PRMVIO_START 0xC0000 -#define NV4_PRMVIO_END 0xC7FFF - -#define NV4_PRMVIO_MBEN 0xC0094 -#define NV4_PRMVIO_ADDEN 0xC46e8 -#define NV4_PRMVIO_VSE1 0xC0102 -#define NV4_PRMVIO_VSE2 0xC03c3 -#define NV4_PRMVIO_MISC_READ 0xC03cc -#define NV4_PRMVIO_MISC_WRITE 0xC03c2 -#define NV4_PRMVIO_SRX 0xC03c4 -#define NV4_PRMVIO_SR_RESET 0xC03c5 -#define NV4_PRMVIO_SR_RESET_INDEX 0x0 -#define NV4_PRMVIO_SR_CLOCK_INDEX 0x1 -#define NV4_PRMVIO_SR_PLANE_MASK_INDEX 0x2 -#define NV4_PRMVIO_SR_CHAR_MAP_INDEX 0x3 -#define NV4_PRMVIO_SR_MEM_MODE_INDEX 0x4 -#define NV4_PRMVIO_GX_SR 0xC03cf -#define NV4_PRMVIO_GX_SR_INDEX 0x0 -#define NV4_PRMVIO_GX_SREN_INDEX 0x1 -#define NV4_PRMVIO_GX_CCOMP_INDEX 0x2 -#define NV4_PRMVIO_GX_ROP_INDEX 0x3 -#define NV4_PRMVIO_GX_READ_MAP_INDEX 0x4 -#define NV4_PRMVIO_GX_MODE_INDEX 0x5 -#define NV4_PRMVIO_GX_MISC_INDEX 0x6 -#define NV4_PRMVIO_GX_MISC_BANKED_128K_A0000 0x00 -#define NV4_PRMVIO_GX_MISC_BANKED_64K_A0000 0x04 -#define NV4_PRMVIO_GX_MISC_BANKED_32K_B0000 0x08 -#define NV4_PRMVIO_GX_MISC_BANKED_32K_B8000 0x0C -#define NV4_PRMVIO_GX_DONT_CARE_INDEX 0x7 -#define NV4_PRMVIO_GX_BIT_MASK_INDEX 0x8 - -#define NV4_PRMVGA 0xA0000 -#define NV4_PRMVGA_END 0xBFFFF - -#define NV4_PME 0x200FFF:0x200000 -#define NV4_PME_DEBUG_0 0x200080 -#define NV4_PME_DEBUG_0_DET_FIELD_SWITCH 0 -#define NV4_PME_DEBUG_0_DET_FIELD_SWITCH_ENABLED 0x1 -#define NV4_PME_DEBUG_0_CAPTURE_00_FF 4 -#define NV4_PME_DEBUG_0_CAPTURE_00_FF_ENABLED 0x1 -#define NV4_PME_DEBUG_1 0x200084 -#define NV4_PME_DEBUG_1_SEL 0 -#define NV4_PME_DEBUG_1_SEL_VIPCLK 0x0 -#define NV4_PME_DEBUG_1_SEL_MCLK 0x1 -#define NV4_PME_DEBUG_1_SEL_GLOB 0x2 -#define NV4_PME_DEBUG_1_VIPCLK_SEL 4 -#define NV4_PME_DEBUG_1_VIPCLK_SEL_DEFAULT 0x0 -#define NV4_PME_DEBUG_1_MCLK_SEL 8 -#define NV4_PME_DEBUG_1_MCLK_SEL_DEFAULT 0x0 -#define NV4_PME_INTR_0 0x200100 -#define NV4_PME_INTR_0_IMAGE_NOTIFY 0 -#define NV4_PME_INTR_0_IMAGE_NOTIFY_NOT_PENDING 0x0 -#define NV4_PME_INTR_0_IMAGE_NOTIFY_PENDING 0x1 -#define NV4_PME_INTR_0_IMAGE_NOTIFY_RESET 0x1 -#define NV4_PME_INTR_0_VBI_NOTIFY 4 -#define NV4_PME_INTR_0_VBI_NOTIFY_NOT_PENDING 0x0 -#define NV4_PME_INTR_0_VBI_NOTIFY_PENDING 0x1 -#define NV4_PME_INTR_0_VBI_NOTIFY_RESET 0x1 -#define NV4_PME_INTR_0_VID_NOTIFY 8 -#define NV4_PME_INTR_0_VID_NOTIFY_NOT_PENDING 0x0 -#define NV4_PME_INTR_0_VID_NOTIFY_PENDING 0x1 -#define NV4_PME_INTR_0_VID_NOTIFY_RESET 0x1 -#define NV4_PME_INTR_0_AUD_NOTIFY 12 -#define NV4_PME_INTR_0_AUD_NOTIFY_NOT_PENDING 0x0 -#define NV4_PME_INTR_0_AUD_NOTIFY_PENDING 0x1 -#define NV4_PME_INTR_0_AUD_NOTIFY_RESET 0x1 -#define NV4_PME_INTR_0_VMI 16 -#define NV4_PME_INTR_0_VMI_NOT_PENDING 0x0 -#define NV4_PME_INTR_0_VMI_PENDING 0x1 -#define NV4_PME_INTR_0_VMI_RESET 0x1 -#define NV4_PME_INTR_EN_0 0x200140 -#define NV4_PME_INTR_EN_0_IMAGE_NOTIFY 0 -#define NV4_PME_INTR_EN_0_IMAGE_NOTIFY_ENABLED 0x1 -#define NV4_PME_INTR_EN_0_VBI_NOTIFY 4 -#define NV4_PME_INTR_EN_0_VBI_NOTIFY_ENABLED 0x1 -#define NV4_PME_INTR_EN_0_VID_NOTIFY 8 -#define NV4_PME_INTR_EN_0_VID_NOTIFY_ENABLED 0x1 -#define NV4_PME_INTR_EN_0_AUD_NOTIFY 12 -#define NV4_PME_INTR_EN_0_AUD_NOTIFY_ENABLED 0x1 -#define NV4_PME_INTR_EN_0_VMI 16 -#define NV4_PME_INTR_EN_0_VMI_ENABLED 0x1 -#define NV4_PME_CONFIG_0 0x200200 -#define NV4_PME_CONFIG_0_BUS_MODE 0 -#define NV4_PME_CONFIG_0_BUS_MODE_DISABLED 0x0 -#define NV4_PME_CONFIG_0_BUS_MODE_VMI 0x1 -#define NV4_PME_CONFIG_0_BUS_MODE_CCIR656 0x2 -#define NV4_PME_CONFIG_0_IMAGE 4 -#define NV4_PME_CONFIG_0_IMAGE_ENABLED 0x1 -#define NV4_PME_CONFIG_0_VBI_MODE 8 -#define NV4_PME_CONFIG_0_VBI_MODE_DISABLED 0x0 -#define NV4_PME_CONFIG_0_VBI_MODE_1 0x1 -#define NV4_PME_CONFIG_0_VBI_MODE_2 0x2 -#define NV4_PME_CONFIG_0_VID_CD 12 -#define NV4_PME_CONFIG_0_VID_CD_ENABLED 0x1 -#define NV4_PME_CONFIG_0_AUD_CD 16 -#define NV4_PME_CONFIG_0_AUD_CD_ENABLED 0x1 -#define NV4_PME_CONFIG_1 0x200204 -#define NV4_PME_CONFIG_1_BUFFS 0 -#define NV4_PME_CONFIG_1_BUFFS_PNVM 0x0 -#define NV4_PME_CONFIG_1_BUFFS_SYS 0x1 -#define NV4_PME_CONFIG_1_HOST 4 -#define NV4_PME_CONFIG_1_HOST_PCI 0x0 -#define NV4_PME_CONFIG_1_HOST_AGP 0x1 -#define NV4_PME_NULL_DATA 0x200208 -#define NV4_PME_NULL_DATA_COMPARE 0 -#define NV4_PME_NULL_DATA_COMPARE_ENABLED 0x1 -#define NV4_PME_NULL_DATA_LINE_DETECT 4 -#define NV4_PME_NULL_DATA_LINE_DETECT_ENABLED 0x1 -#define NV4_PME_NULL_DATA_BYTE 24 -#define NV4_PME_VID_BUFF0_START_SYS 0x200300 -#define NV4_PME_VID_BUFF0_START_SYS_ADDRESS 4 -#define NV4_PME_VID_BUFF1_START_SYS 0x200304 -#define NV4_PME_VID_BUFF1_START_SYS_ADDRESS 4 -#define NV4_PME_VID_BUFF0_START_PNVM 0x200308 -#define NV4_PME_VID_BUFF0_START_PNVM_ADDRESS 4 -#define NV4_PME_VID_BUFF1_START_PNVM 0x20030c -#define NV4_PME_VID_BUFF1_START_PNVM_ADDRESS 4 -#define NV4_PME_VID_BUFF0_LENGTH 0x200310 -#define NV4_PME_VID_BUFF0_LENGTH_BITS 12 -#define NV4_PME_VID_BUFF1_LENGTH 0x200314 -#define NV4_PME_VID_BUFF1_LENGTH_BITS 12 -#define NV4_PME_VID_ME_STATE 0x200318 -#define NV4_PME_VID_ME_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_VID_ME_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_VID_ME_STATE_BUFF0_INTR_CHAINGAP 8 -#define NV4_PME_VID_ME_STATE_BUFF1_INTR_CHAINGAP 12 -#define NV4_PME_VID_ME_STATE_BUFF0_IN_USE 16 -#define NV4_PME_VID_ME_STATE_BUFF1_IN_USE 20 -#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER 24 -#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER_0 0x0 -#define NV4_PME_VID_ME_STATE_CURRENT_BUFFER_1 0x1 -#define NV4_PME_VID_SU_STATE 0x20031c -#define NV4_PME_VID_SU_STATE_BUFF0_IN_USE 16 -#define NV4_PME_VID_SU_STATE_BUFF1_IN_USE 20 -#define NV4_PME_VID_RM_STATE 0x200320 -#define NV4_PME_VID_RM_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_VID_RM_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_VID_RM_STATE_BUFF0_INTR_CHAINGAP 8 -#define NV4_PME_VID_RM_STATE_BUFF1_INTR_CHAINGAP 12 -#define NV4_PME_VID_CURRENT 0x200324 -#define NV4_PME_VID_CURRENT_POS 2 -#define NV4_PME_AUD_BUFF0_START_SYS 0x200340 -#define NV4_PME_AUD_BUFF0_START_SYS_ADDRESS 4 -#define NV4_PME_AUD_BUFF1_START_SYS 0x200344 -#define NV4_PME_AUD_BUFF1_START_SYS_ADDRESS 4 -#define NV4_PME_AUD_BUFF0_START_PNVM 0x200348 -#define NV4_PME_AUD_BUFF0_START_PNVM_ADDRESS 4 -#define NV4_PME_AUD_BUFF1_START_PNVM 0x20034c -#define NV4_PME_AUD_BUFF1_START_PNVM_ADDRESS 4 -#define NV4_PME_AUD_BUFF0_LENGTH 0x200350 -#define NV4_PME_AUD_BUFF0_LENGTH_BITS 10 -#define NV4_PME_AUD_BUFF1_LENGTH 0x200354 -#define NV4_PME_AUD_BUFF1_LENGTH_BITS 10 -#define NV4_PME_AUD_ME_STATE 0x200358 -#define NV4_PME_AUD_ME_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_AUD_ME_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_AUD_ME_STATE_BUFF0_INTR_CHAINGAP 8 -#define NV4_PME_AUD_ME_STATE_BUFF1_INTR_CHAINGAP 12 -#define NV4_PME_AUD_ME_STATE_BUFF0_IN_USE 16 -#define NV4_PME_AUD_ME_STATE_BUFF1_IN_USE 20 -#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER 24 -#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER_0 0x0 -#define NV4_PME_AUD_ME_STATE_CURRENT_BUFFER_1 0x1 -#define NV4_PME_AUD_SU_STATE 0x20035c -#define NV4_PME_AUD_SU_STATE_BUFF0_IN_USE 16 -#define NV4_PME_AUD_SU_STATE_BUFF1_IN_USE 20 -#define NV4_PME_AUD_RM_STATE 0x200360 -#define NV4_PME_AUD_RM_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_AUD_RM_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_AUD_RM_STATE_BUFF0_INTR_CHAINGAP 8 -#define NV4_PME_AUD_RM_STATE_BUFF1_INTR_CHAINGAP 12 -#define NV4_PME_AUD_CURRENT 0x200364 -#define NV4_PME_AUD_CURRENT_POS 2 -#define NV4_PME_VBI_BUFF0_START 0x200380 -#define NV4_PME_VBI_BUFF0_START_ADDRESS 4 -#define NV4_PME_VBI_BUFF1_START 0x200384 -#define NV4_PME_VBI_BUFF1_START_ADDRESS 4 -#define NV4_PME_VBI_BUFF0_PITCH 0x200388 -#define NV4_PME_VBI_BUFF0_PITCH_VALUE 4 -#define NV4_PME_VBI_BUFF1_PITCH 0x20038c -#define NV4_PME_VBI_BUFF1_PITCH_VALUE 4 -#define NV4_PME_VBI_BUFF0_LENGTH 0x200390 -#define NV4_PME_VBI_BUFF0_LENGTH_BITS 4 -#define NV4_PME_VBI_BUFF1_LENGTH 0x200394 -#define NV4_PME_VBI_BUFF1_LENGTH_BITS 4 -#define NV4_PME_VBI_ME_STATE 0x200398 -#define NV4_PME_VBI_ME_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_VBI_ME_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_VBI_ME_STATE_BUFF0_ERROR_CODE 8 -#define NV4_PME_VBI_ME_STATE_BUFF1_ERROR_CODE 12 -#define NV4_PME_VBI_ME_STATE_BUFF0_IN_USE 16 -#define NV4_PME_VBI_ME_STATE_BUFF1_IN_USE 20 -#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER 24 -#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER_0 0x0 -#define NV4_PME_VBI_ME_STATE_CURRENT_BUFFER_1 0x1 -#define NV4_PME_VBI_SU_STATE 0x20039c -#define NV4_PME_VBI_SU_STATE_BUFF0_FIELD 8 -#define NV4_PME_VBI_SU_STATE_BUFF1_FIELD 12 -#define NV4_PME_VBI_SU_STATE_BUFF0_IN_USE 16 -#define NV4_PME_VBI_SU_STATE_BUFF1_IN_USE 20 -#define NV4_PME_VBI_RM_STATE 0x2003a0 -#define NV4_PME_VBI_RM_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_VBI_RM_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_VBI 0x2003a4 -#define NV4_PME_VBI_START_LINE 0 -#define NV4_PME_VBI_NUM_LINES 16 -#define NV4_PME_IMAGE_BUFF0_START 0x200400 -#define NV4_PME_IMAGE_BUFF0_START_ADDRESS 4 -#define NV4_PME_IMAGE_BUFF1_START 0x200404 -#define NV4_PME_IMAGE_BUFF1_START_ADDRESS 4 -#define NV4_PME_IMAGE_BUFF0_PITCH 0x200408 -#define NV4_PME_IMAGE_BUFF0_PITCH_VALUE 4 -#define NV4_PME_IMAGE_BUFF1_PITCH 0x20040c -#define NV4_PME_IMAGE_BUFF1_PITCH_VALUE 4 -#define NV4_PME_IMAGE_BUFF0_LENGTH 0x200410 -#define NV4_PME_IMAGE_BUFF0_LENGTH_BITS 4 -#define NV4_PME_IMAGE_BUFF1_LENGTH 0x200414 -#define NV4_PME_IMAGE_BUFF1_LENGTH_BITS 4 -#define NV4_PME_IMAGE_ME_STATE 0x200418 -#define NV4_PME_IMAGE_ME_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_IMAGE_ME_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_IMAGE_ME_STATE_BUFF0_ERROR_CODE 8 -#define NV4_PME_IMAGE_ME_STATE_BUFF1_ERROR_CODE 12 -#define NV4_PME_IMAGE_ME_STATE_BUFF0_IN_USE 16 -#define NV4_PME_IMAGE_ME_STATE_BUFF1_IN_USE 20 -#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER 24 -#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER_0 0x0 -#define NV4_PME_IMAGE_ME_STATE_CURRENT_BUFFER_1 0x1 -#define NV4_PME_IMAGE_SU_STATE 0x20041c -#define NV4_PME_IMAGE_SU_STATE_BUFF0_FIELD 8 -#define NV4_PME_IMAGE_SU_STATE_BUFF1_FIELD 12 -#define NV4_PME_IMAGE_SU_STATE_BUFF0_IN_USE 16 -#define NV4_PME_IMAGE_SU_STATE_BUFF1_IN_USE 20 -#define NV4_PME_IMAGE_RM_STATE 0x200420 -#define NV4_PME_IMAGE_RM_STATE_BUFF0_INTR_NOTIFY 0 -#define NV4_PME_IMAGE_RM_STATE_BUFF1_INTR_NOTIFY 4 -#define NV4_PME_IMAGE_BUFF0_SCALE_INCR 0x200424 -#define NV4_PME_IMAGE_BUFF0_SCALE_INCR_Y 16 -#define NV4_PME_IMAGE_BUFF0_SCALE_INCR_X 0 -#define NV4_PME_IMAGE_BUFF1_SCALE_INCR 0x200428 -#define NV4_PME_IMAGE_BUFF1_SCALE_INCR_Y 16 -#define NV4_PME_IMAGE_BUFF1_SCALE_INCR_X 0 -#define NV4_PME_IMAGE_Y_CROP 0x20042c -#define NV4_PME_IMAGE_Y_CROP_STARTLINE 0 -#define NV4_PME_FIFO_LINE_START 0x200480 -#define NV4_PME_FIFO_LINE_START_ADDRESS 4 -#define NV4_PME_FIFO_CURRENT 0x200484 -#define NV4_PME_FIFO_CURRENT_ADDRESS 2 -#define NV4_PME_VMI_POLL 0x200488 -#define NV4_PME_VMI_POLL_UNCD 0 -#define NV4_PME_VMI_POLL_UNCD_NOT_PENDING 0x0 -#define NV4_PME_VMI_POLL_UNCD_PENDING 0x1 -#define NV4_PME_VMI_POLL_VIDCD 1 -#define NV4_PME_VMI_POLL_VIDCD_NOT_PENDING 0x0 -#define NV4_PME_VMI_POLL_VIDCD_PENDING 0x1 -#define NV4_PME_VMI_POLL_AUDCD 2 -#define NV4_PME_VMI_POLL_AUDCD_NOT_PENDING 0x0 -#define NV4_PME_VMI_POLL_AUDCD_PENDING 0x1 -#define NV4_PME_VMI_POLL_INT 3 -#define NV4_PME_VMI_POLL_INT_NOT_PENDING 0x0 -#define NV4_PME_VMI_POLL_INT_PENDING 0x1 -#define NV4_PME_VMI_POLL_CPURDREC 4 -#define NV4_PME_VMI_POLL_CPURDREC_NOT_PENDING 0x0 -#define NV4_PME_VMI_POLL_CPURDREC_PENDING 0x1 -#define NV4_PME_EXTERNAL(i) (0x200600+(i)*4) -#define NV4_PME_EXTERNAL_SIZE_1 256 -#define NV4_PME_EXTERNAL_DATA 0 - -#define NV4_PFB_START 0x100000 -#define NV4_PFB_END 0x100FFF - -#define NV4_PFB_BOOT_0 0x100000 -#define NV4_PFB_BOOT_0_RAM_AMOUNT 0 -#define NV4_PFB_BOOT_0_RAM_AMOUNT_2MB 0x0 -#define NV4_PFB_BOOT_0_RAM_AMOUNT_4MB 0x1 -#define NV4_PFB_BOOT_0_RAM_AMOUNT_8MB 0x2 -#define NV4_PFB_BOOT_0_RAM_AMOUNT_16MB 0x3 -#define NV4_PFB_BOOT_0_RAM_WIDTH_128 2 -#define NV4_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x0 -#define NV4_PFB_BOOT_0_RAM_WIDTH_128_ON 0x1 -#define NV4_PFB_BOOT_0_RAM_TYPE 3 -#define NV4_PFB_BOOT_0_RAM_TYPE_256K 0x0 -#define NV4_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x1 -#define NV4_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x2 -#define NV4_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x3 -#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x0 -#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x1 -#define NV4_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x2 -#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x3 -#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x4 -#define NV4_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x5 -#define NV4_PFB_BOOT_0_UMA 8 -#define NV4_PFB_BOOT_0_UMA_DISABLE 0x0 -#define NV4_PFB_BOOT_0_UMA_ENABLE 0x1 -#define NV4_PFB_BOOT_0_UMA_SIZE 12 -#define NV4_PFB_BOOT_0_UMA_SIZE_DEFAULT 0x7 -#define NV4_PFB_BOOT_0_UMA_SIZE_2M 0x0 -#define NV4_PFB_BOOT_0_UMA_SIZE_4M 0x1 -#define NV4_PFB_BOOT_0_UMA_SIZE_6M 0x2 -#define NV4_PFB_BOOT_0_UMA_SIZE_8M 0x3 -#define NV4_PFB_BOOT_0_UMA_SIZE_10M 0x4 -#define NV4_PFB_BOOT_0_UMA_SIZE_12M 0x5 -#define NV4_PFB_BOOT_0_UMA_SIZE_14M 0x6 -#define NV4_PFB_BOOT_0_UMA_SIZE_16M 0x7 -#define NV4_PFB_BOOT_0_UMA_SIZE_18M 0x8 -#define NV4_PFB_BOOT_0_UMA_SIZE_20M 0x9 -#define NV4_PFB_BOOT_0_UMA_SIZE_22M 0xA -#define NV4_PFB_BOOT_0_UMA_SIZE_24M 0xB -#define NV4_PFB_BOOT_0_UMA_SIZE_26M 0xC -#define NV4_PFB_BOOT_0_UMA_SIZE_28M 0xD -#define NV4_PFB_BOOT_0_UMA_SIZE_30M 0xE -#define NV4_PFB_BOOT_0_UMA_SIZE_32M 0xF -#define NV4_PFB_DEBUG_0 0x100080 -#define NV4_PFB_DEBUG_0_PAGE_MODE 0 -#define NV4_PFB_DEBUG_0_PAGE_MODE_ENABLED 0x0 -#define NV4_PFB_DEBUG_0_PAGE_MODE_DISABLED 0x1 -#define NV4_PFB_DEBUG_0_REFRESH 4 -#define NV4_PFB_DEBUG_0_REFRESH_ENABLED 0x0 -#define NV4_PFB_DEBUG_0_REFRESH_DISABLED 0x1 -#define NV4_PFB_DEBUG_0_REFRESH_COUNTX64 8 -#define NV4_PFB_DEBUG_0_REFRESH_COUNTX64_DEFAULT 0x10 -#define NV4_PFB_DEBUG_0_REFRESH_SLOW_CLK 14 -#define NV4_PFB_DEBUG_0_REFRESH_SLOW_CLK_ENABLED 0x1 -#define NV4_PFB_DEBUG_0_CASOE 20 -#define NV4_PFB_DEBUG_0_CASOE_ENABLED 0x0 -#define NV4_PFB_DEBUG_0_CASOE_DISABLED 0x1 -#define NV4_PFB_DEBUG_0_CKE_INVERT 28 -#define NV4_PFB_DEBUG_0_CKE_INVERT_OFF 0x0 -#define NV4_PFB_DEBUG_0_CKE_INVERT_ON 0x1 -#define NV4_PFB_DEBUG_0_REFINC 29 -#define NV4_PFB_DEBUG_0_REFINC_DISABLED 0x0 -#define NV4_PFB_DEBUG_0_REFINC_ENABLED 0x1 -#define NV4_PFB_DEBUG_0_SAVE_POWER 30 -#define NV4_PFB_DEBUG_0_SAVE_POWER_ON 0x0 -#define NV4_PFB_DEBUG_0_SAVE_POWER_OFF 0x1 -#define NV4_PFB_GREEN_0 0x1000C0 -#define NV4_PFB_GREEN_0_LEVEL 0 -#define NV4_PFB_GREEN_0_LEVEL_VIDEO_ENABLED 0x0 -#define NV4_PFB_GREEN_0_LEVEL_VIDEO_DISABLED 0x1 -#define NV4_PFB_GREEN_0_LEVEL_TIMING_DISABLED 0x2 -#define NV4_PFB_GREEN_0_LEVEL_MEMORY_DISABLED 0x3 -#define NV4_PFB_CONFIG_0 0x100200 -#define NV4_PFB_CONFIG_0_TYPE 0 -#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x120 -#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x220 -#define NV4_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x320 -#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x4120 -#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x4220 -#define NV4_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x4320 -#define NV4_PFB_CONFIG_0_TYPE_TETRIS 0x2000 -#define NV4_PFB_CONFIG_0_TYPE_NOTILING 0x1114 -#define NV4_PFB_CONFIG_0_TETRIS_MODE 15 -// 18:15 = tetris mode # -#define NV4_PFB_CONFIG_0_TETRIS_MODE_PASS 0x0 -// 18 = shift # -#define NV4_PFB_CONFIG_0_TETRIS_SHIFT 18 -#define NV4_PFB_CONFIG_0_BANK_SWAP 20 -#define NV4_PFB_CONFIG_0_BANK_SWAP_OFF 0x0 -#define NV4_PFB_CONFIG_0_BANK_SWAP_1M 0x1 -#define NV4_PFB_CONFIG_0_BANK_SWAP_2M 0x5 -#define NV4_PFB_CONFIG_0_BANK_SWAP_4M 0x7 -#define NV4_PFB_CONFIG_0_UNUSED 23 -#define NV4_PFB_CONFIG_0_SCRAMBLE_EN 29 -#define NV4_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x0 -#define NV4_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x1 -#define NV4_PFB_CONFIG_0_PRAMIN_WR 28 -#define NV4_PFB_CONFIG_0_PRAMIN_WR_INIT 0x0 -#define NV4_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x1 -#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK 24 -#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x0 -#define NV4_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0xF -#define NV4_PFB_CONFIG_1 0x100204 -#define NV4_PFB_CONFIG_1_CAS_LATENCY 0 -#define NV4_PFB_CONFIG_1_CAS_LATENCY_3 0x3 -#define NV4_PFB_CONFIG_1_CAS_LATENCY_2 0x2 -#define NV4_PFB_CONFIG_1_CAS_LATENCY_4 0x4 -#define NV4_PFB_CONFIG_1_RAS_RAS 4 -#define NV4_PFB_CONFIG_1_RAS_RAS_DEFAULT 0x9 -#define NV4_PFB_CONFIG_1_RAS_RAS_9CYCLES 0x8 -#define NV4_PFB_CONFIG_1_RAS_RAS_8CYCLES 0x7 -#define NV4_PFB_CONFIG_1_RAS_RAS_7CYCLES 0x6 -#define NV4_PFB_CONFIG_1_RAS_PCHG 8 -#define NV4_PFB_CONFIG_1_RAS_PCHG_DEFAULT 0x2 -#define NV4_PFB_CONFIG_1_RAS_PCHG_2CYCLES 0x1 -#define NV4_PFB_CONFIG_1_RAS_LOW 12 -#define NV4_PFB_CONFIG_1_RAS_LOW_DEFAULT 0x6 -#define NV4_PFB_CONFIG_1_RAS_LOW_7CYCLES 0x7 -#define NV4_PFB_CONFIG_1_RAS_LOW_5CYCLES 0x5 -#define NV4_PFB_CONFIG_1_RAS_LOW_4CYCLES 0x4 -#define NV4_PFB_CONFIG_1_MRS_TO_RAS 16 -#define NV4_PFB_CONFIG_1_MRS_TO_RAS_DEFAULT 0x1 -#define NV4_PFB_CONFIG_1_MRS_TO_RAS_2CYCLES 0x2 -#define NV4_PFB_CONFIG_1_MRS_TO_RAS_0CYCLES 0x0 -#define NV4_PFB_CONFIG_1_WRITE_TO_READ 20 -#define NV4_PFB_CONFIG_1_WRITE_TO_READ_DEFAULT 0x0 -#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1 24 -#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_DEFAULT 0x1 -#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_2CYCLES 0x2 -#define NV4_PFB_CONFIG_1_RAS_TO_CAS_M1_0CYCLES 0x0 -#define NV4_PFB_CONFIG_1_READ_TO_WRITE 28 -#define NV4_PFB_CONFIG_1_READ_TO_WRITE_DEFAULT 0x4 -#define NV4_PFB_CONFIG_1_READ_TO_WRITE_5CYCLES 0x5 -#define NV4_PFB_CONFIG_1_READ_TO_WRITE_3CYCLES 0x3 -#define NV4_PFB_CONFIG_1_READ_TO_WRITE_2CYCLES 0x2 -#define NV4_PFB_CONFIG_1_READ_TO_PCHG 31 -#define NV4_PFB_CONFIG_1_READ_TO_PCHG_ON 0x1 -#define NV4_PFB_CONFIG_1_READ_TO_PCHG_OFF 0x0 -#define NV4_PFB_RTL 0x100300 -#define NV4_PFB_RTL_H 0 -#define NV4_PFB_RTL_H_DEFAULT 0x0 -#define NV4_PFB_RTL_MC 1 -#define NV4_PFB_RTL_MC_DEFAULT 0x0 -#define NV4_PFB_RTL_V 2 -#define NV4_PFB_RTL_V_DEFAULT 0x0 -#define NV4_PFB_RTL_G 3 -#define NV4_PFB_RTL_G_DEFAULT 0x0 -#define NV4_PFB_RTL_GB 4 -#define NV4_PFB_RTL_GB_DEFAULT 0x0 -#define NV4_PFB_SCRAMBLE(i) (0x100400+((i)*4)) -#define NV4_PFB_SCRAMBLE_SIZE_1 8 -#define NV4_PFB_SCRAMBLE_w0 0 -#define NV4_PFB_SCRAMBLE_w1 8 -#define NV4_PFB_SCRAMBLE_w2 16 -#define NV4_PFB_SCRAMBLE_w3 24 -#define NV4_PFB_SCRAMBLE_EN 0x100420 -#define NV4_PFB_SCRAMBLE_VALUE_0 0x03020100 -#define NV4_PFB_SCRAMBLE_VALUE_1 0x07060504 -#define NV4_PFB_SCRAMBLE_VALUE_2 0x0b0a0908 -#define NV4_PFB_SCRAMBLE_VALUE_3 0x0f0e0d0c -#define NV4_PFB_SCRAMBLE_VALUE_4 0x13121110 -#define NV4_PFB_SCRAMBLE_VALUE_5 0x17161514 -#define NV4_PFB_SCRAMBLE_VALUE_6 0x1b1a1918 -#define NV4_PFB_SCRAMBLE_VALUE_7 0x1f1e1d1c -#define NV4_PFB_CONFIG_0_RESOLUTION 0 -#define NV4_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0xA -#define NV4_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0xD -#define NV4_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0xF -#define NV4_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x10 -#define NV4_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x14 -#define NV4_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x19 -#define NV4_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x1e -#define NV4_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x20 -#define NV4_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x24 -#define NV4_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x28 -#define NV4_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x32 -#define NV4_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x14 -#define NV4_PFB_CONFIG_0_PIXEL_DEPTH 8 -#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x1 -#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x2 -#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x3 -#define NV4_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x1 -#define NV4_PFB_CONFIG_0_TILING 12 -#define NV4_PFB_CONFIG_0_TILING_ENABLED 0x0 -#define NV4_PFB_CONFIG_0_TILING_DISABLED 0x1 -#define NV4_PFB_CONFIG_0_TILING_DEBUG 13 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_DISABLED 0x0 -#define NV4_PFB_CONFIG_0_TILE 12 -#define NV4_PFB_CONFIG_0_TILE_OLD1024_FIXED 0x0 -#define NV4_PFB_CONFIG_0_TILE_OLD1024_VARIABLE 0x4 -#define NV4_PFB_CONFIG_0_TILE_TETRIS_ALLOW 0x1 -#define NV4_PFB_CONFIG_0_TILE_TETRIS_REDUNDANT 0x2 -#define NV4_PFB_CONFIG_0_TILE_TETRIS_REDUNDANT2 0x3 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON 13 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON_ENABLED 0x0 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_ON_DISABLED 0x1 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE 14 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE_FIXED 0x0 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_TILESIZE_VARIABLE 0x1 -// tetris mode # = 17:15 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_MODE 15 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_MODE_PASS 0x0 -// tetris shift # = 18 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_TETRIS_SHIFT 18 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP 20 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_OFF 0x0 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_ON 0x1 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB 21 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_1M 0x0 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_2M 0x2 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_BANK_SWAP_MSB_4M 0x3 -#define NV4_PFB_CONFIG_0_TILING_DEBUG_UNUSED 23 -#define NV4_PFB_CONFIG_1_SGRAM100 3 -#define NV4_PFB_CONFIG_1_SGRAM100_ENABLED 0x0 -#define NV4_PFB_CONFIG_1_SGRAM100_DISABLED 0x1 -#define NV4_PFB_DEBUG_0_CKE_ALWAYSON 29 -#define NV4_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x0 -#define NV4_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x1 - -// WARNING! WARNING! WARNING! -// STB V4400 has shown PROM at 0x700000 instead of 0x300000 (errata), clashing with first 0x10000 of instance memory -// Nvidia never ran into this issue because they never used that area -// But this part may not work -#define NV4_PRAMIN_START 0x700000 -#define NV4_PRAMIN_END 0x7FFFFF -#define NV4_PRAMIN_SIZE 0xFFFFF - -#define NV4_PRAMIN_CONTEXT_0 ( 0*32+31):( 0*32+ 0) -#define NV4_PRAMIN_CONTEXT_1 ( 1*32+31):( 1*32+ 0) -#define NV4_PRAMIN_CONTEXT_2 ( 2*32+31):( 2*32+ 0) -#define NV4_PRAMIN_CONTEXT_3 ( 3*32+31):( 3*32+ 0) -#define NV4_PRAMIN_RAMHT_START 0x710000 -#define NV4_PRAMIN_RAMHT_END 0x710FFF -#define NV4_PRAMIN_RAMFC_START 0x711000 -#define NV4_PRAMIN_RAMFC_END 0x7111FF -#define NV4_PRAMIN_RAMRO_START 0x711200 -#define NV4_PRAMIN_RAMRO_END 0x7113FF -#define NV4_PRAMIN_CTX_0(i) (0x700000 + (i)*16) -// This is the same format as PGRAPH_CTX_SWITCH -#define NV4_PRAMIN_CTX_0_SIZE_1 0x10000 -#define NV4_PRAMIN_CTX_0_NVCLASS 0 -#define NV4_PRAMIN_CTX_0_CHROMA_KEY 12 -#define NV4_PRAMIN_CTX_0_CHROMA_KEY_ENABLE 0x1 -#define NV4_PRAMIN_CTX_0_USER_CLIP 13 -#define NV4_PRAMIN_CTX_0_USER_CLIP_ENABLE 0x1 -#define NV4_PRAMIN_CTX_0_SWIZZLE 14 -#define NV4_PRAMIN_CTX_0_SWIZZLE_ENABLE 0x1 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG 17:15 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_AND 0x0 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_ROP_AND 0x1 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_AND 0x2 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY 0x3 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_PRE 0x4 -#define NV4_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_PRE 0x5 -#define NV4_PRAMIN_CTX_0_PATCH_STATUS 24 -#define NV4_PRAMIN_CTX_0_PATCH_STATUS_INVALID 0x0 -#define NV4_PRAMIN_CTX_0_PATCH_STATUS_VALID 0x1 -#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE 25 -#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE_INVALID 0x0 -#define NV4_PRAMIN_CTX_0_CONTEXT_SURFACE_VALID 0x1 -#define NV4_PRAMIN_CTX_1(i) (0x700004 + (i)*16) -#define NV4_PRAMIN_CTX_1_SIZE_1 0x10000 -#define NV4_PRAMIN_CTX_1_MONO_FORMAT 0 -#define NV4_PRAMIN_CTX_1_MONO_FORMAT_INVALID 0x00 -#define NV4_PRAMIN_CTX_1_MONO_FORMAT_CGA6_M1 0x01 -#define NV4_PRAMIN_CTX_1_MONO_FORMAT_LE_M1 0x02 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT 8 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_INVALID 0x00 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y8 0x01 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A8Y8 0x02 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X24Y8 0x03 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A1R5G5B5 0x06 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X1R5G5B5 0x07 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X17R5G5B5 0x09 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_R5G6B5 0x0A -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16R5G6B5 0x0B -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16R5G6B5 0x0C -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A8R8G8B8 0x0D -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X8R8G8B8 0x0E -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y16 0x0F -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16Y16 0x10 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16Y16 0x11 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 -#define NV4_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y32 0x14 -#define NV4_PRAMIN_CTX_1_NOTIFY_INSTANCE 16 -#define NV4_PRAMIN_CTX_1_NOTIFY_INSTANCE_INVALID 0x00 -#define NV4_PRAMIN_CTX_2(i) (0x700008 + (i)*16) -#define NV4_PRAMIN_CTX_2_SIZE_1 0x10000 -#define NV4_PRAMIN_CTX_2_DMA_0_INSTANCE 0 -#define NV4_PRAMIN_CTX_2_DMA_0_INSTANCE_INVALID 0x00 -#define NV4_PRAMIN_CTX_2_DMA_1_INSTANCE 16 -#define NV4_PRAMIN_CTX_2_DMA_1_INSTANCE_INVALID 0x00 - -#define NV4_FIFO_DMA_OPCODE ( 0*32+31):( 0*32+29) -#define NV4_FIFO_DMA_OPCODE_METHOD 0x0 -#define NV4_FIFO_DMA_OPCODE_JUMP 0x1 -#define NV4_FIFO_DMA_METHOD_COUNT ( 0*32+28):( 0*32+18) -#define NV4_FIFO_DMA_METHOD_SUBCHANNEL ( 0*32+15):( 0*32+13) -#define NV4_FIFO_DMA_METHOD_ADDRESS ( 0*32+12):( 0*32+ 2) -#define NV4_FIFO_DMA_DATA ( 1*32+31):( 1*32+ 0) -#define NV4_FIFO_DMA_JUMP_OFFSET 2 - -// DFB is in BAR1. Access it as VRAM - -#define NV4_PEXTDEV_BOOT_0 0x101000 -#define NV4_STRAP_BUS_SPEED 0 -#define NV4_STRAP_BUS_SPEED_33MHZ 0x0 -#define NV4_STRAP_BUS_SPEED_66MHZ 0x1 -#define NV4_STRAP_SUB_VENDOR 1 -#define NV4_STRAP_SUB_VENDOR_NO_BIOS 0x0 -#define NV4_STRAP_SUB_VENDOR_BIOS 0x1 -#define NV4_STRAP_RAM_TYPE 2 -#define NV4_STRAP_RAM_TYPE_SGRAM_256K 0x0 -#define NV4_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1 -#define NV4_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2 -#define NV4_STRAP_RAM_TYPE_1024K_2BANK 0x3 -#define NV4_STRAP_RAM_WIDTH 4 -#define NV4_STRAP_RAM_WIDTH_64 0x0 -#define NV4_STRAP_RAM_WIDTH_128 0x1 -#define NV4_STRAP_BUS_TYPE 5 -#define NV4_STRAP_BUS_TYPE_PCI 0x0 -#define NV4_STRAP_BUS_TYPE_AGP 0x1 -#define NV4_STRAP_CRYSTAL 6 -#define NV4_STRAP_CRYSTAL_13500K 0x0 -#define NV4_STRAP_CRYSTAL_14318180 0x1 -#define NV4_STRAP_TVMODE 7 -#define NV4_STRAP_TVMODE_SECAM 0x0 -#define NV4_STRAP_TVMODE_NTSC 0x1 -#define NV4_STRAP_TVMODE_PAL 0x2 -#define NV4_STRAP_TVMODE_DISABLED 0x3 -#define NV4_STRAP_OVERWRITE 11 -#define NV4_STRAP_OVERWRITE_DISABLED 0x0 -#define NV4_STRAP_OVERWRITE_ENABLED 0x1 - -#define NV4_PDAC_START 0x680000 -#define NV4_PDAC_END 0x680FFF - -#define NV4_PDAC_DATA(i) (0x680000+(i)*4) -#define NV4_PDAC_DATA_SIZE_1 16 -#define NV4_PDAC_DATA_VALUE 0 - -// WARNING! -// This has shown up at 0x700000 on real NV4 -#define NV4_PROM_START 0x300000 -#define NV4_PROM_END 0x30FFFF -#define NV4_PROM_DATA(i) (NV4_PROM_START+(i)) -#define NV4_PROM_SIZE 65536 - -#define NV4_PROM_ERRATA_START 0x700000 -#define NV4_PROM_ERRATA_END 0x70FFFF -#define NV4_PROM_ERRATA_DATA(i) (NV4_PROM_ERRATA_START+(i)) - -#define NV4_PRM 0x5FFF:0x4000 -#define NV4_PRM_INTR_0 0x4100 -#define NV4_PRM_INTR_0_TRACE_MPU401 0 -#define NV4_PRM_INTR_0_TRACE_MPU401_NOT_PENDING 0x0 -#define NV4_PRM_INTR_0_TRACE_MPU401_PENDING 0x1 -#define NV4_PRM_INTR_0_TRACE_MPU401_RESET 0x1 -#define NV4_PRM_INTR_0_TRACE_FM 4 -#define NV4_PRM_INTR_0_TRACE_FM_NOT_PENDING 0x0 -#define NV4_PRM_INTR_0_TRACE_FM_PENDING 0x1 -#define NV4_PRM_INTR_0_TRACE_FM_RESET 0x1 -#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL 8 -#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_NOT_PENDING 0x0 -#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_PENDING 0x1 -#define NV4_PRM_INTR_0_TRACE_SB_DIGITAL_RESET 0x1 -#define NV4_PRM_INTR_0_TRACE_SB_MIXER 12 -#define NV4_PRM_INTR_0_TRACE_SB_MIXER_NOT_PENDING 0x0 -#define NV4_PRM_INTR_0_TRACE_SB_MIXER_PENDING 0x1 -#define NV4_PRM_INTR_0_TRACE_SB_MIXER_RESET 0x1 -#define NV4_PRM_INTR_0_TRACE_OVERFLOW 16 -#define NV4_PRM_INTR_0_TRACE_OVERFLOW_NOT_PENDING 0x0 -#define NV4_PRM_INTR_0_TRACE_OVERFLOW_PENDING 0x1 -#define NV4_PRM_INTR_0_TRACE_OVERFLOW_RESET 0x1 -#define NV4_PRM_INTR_EN_0 0x4140 -#define NV4_PRM_INTR_EN_0_TRACE_MPU401 0 -#define NV4_PRM_INTR_EN_0_TRACE_MPU401_ENABLED 0x1 -#define NV4_PRM_INTR_EN_0_TRACE_FM 4 -#define NV4_PRM_INTR_EN_0_TRACE_FM_ENABLED 0x1 -#define NV4_PRM_INTR_EN_0_TRACE_SB_DIGITAL 8 -#define NV4_PRM_INTR_EN_0_TRACE_SB_DIGITAL_ENABLED 0x1 -#define NV4_PRM_INTR_EN_0_TRACE_SB_MIXER 12 -#define NV4_PRM_INTR_EN_0_TRACE_SB_MIXER_ENABLED 0x1 -#define NV4_PRM_INTR_EN_0_TRACE_OVERFLOW 16 -#define NV4_PRM_INTR_EN_0_TRACE_OVERFLOW_ENABLED 0x1 -#define NV4_PRM_RAMRM 0x4200 -#define NV4_PRM_RAMRM_BASE_ADDRESS 12 -#define NV4_PRM_RAMRM_BASE_ADDRESS_2000 0x2000 -#define NV4_PRM_TRACE 0x4300 -#define NV4_PRM_TRACE_IO_CAPTURE 0 -#define NV4_PRM_TRACE_IO_CAPTURE_DISABLED 0x0 -#define NV4_PRM_TRACE_IO_CAPTURE_WRITES 0x1 -#define NV4_PRM_TRACE_IO_CAPTURE_READS 0x2 -#define NV4_PRM_TRACE_IO_CAPTURE_READS_WRITES 0x3 -#define NV4_PRM_TRACE_IO_WRITE 4 -#define NV4_PRM_TRACE_IO_WRITE_NONE 0x0 -#define NV4_PRM_TRACE_IO_WRITE_OCCURED 0x1 -#define NV4_PRM_TRACE_IO_WRITE_RESET 0x1 -#define NV4_PRM_TRACE_IO_READ 5 -#define NV4_PRM_TRACE_IO_READ_NONE 0x0 -#define NV4_PRM_TRACE_IO_READ_OCCURED 0x1 -#define NV4_PRM_TRACE_IO_READ_RESET 0x1 -#define NV4_PRM_TRACE_INDEX 0x4310 -#define NV4_PRM_TRACE_INDEX_ADDRESS 0 -#define NV4_PRM_TRACE_INDEX_ADDRESS_0 0x0 -#define NV4_PRM_IGNORE_0 0x4320 -#define NV4_PRM_IGNORE_0_MPU401 0 -#define NV4_PRM_IGNORE_0_MPU401_DISABLED 0x0 -#define NV4_PRM_IGNORE_0_MPU401_WRITES 0x1 -#define NV4_PRM_IGNORE_0_MPU401_READS 0x2 -#define NV4_PRM_IGNORE_0_MPU401_READS_WRITES 0x3 -#define NV4_PRM_IGNORE_0_FM 4 -#define NV4_PRM_IGNORE_0_FM_DISABLED 0x0 -#define NV4_PRM_IGNORE_0_FM_WRITES 0x1 -#define NV4_PRM_IGNORE_0_FM_READS 0x2 -#define NV4_PRM_IGNORE_0_FM_READS_WRITES 0x3 -#define NV4_PRM_IGNORE_0_SB_DIGITAL 8 -#define NV4_PRM_IGNORE_0_SB_DIGITAL_DISABLED 0x0 -#define NV4_PRM_IGNORE_0_SB_DIGITAL_WRITES 0x1 -#define NV4_PRM_IGNORE_0_SB_DIGITAL_READS 0x2 -#define NV4_PRM_IGNORE_0_SB_DIGITAL_READS_WRITES 0x3 -#define NV4_PRM_IGNORE_0_SB_MIXER 12 -#define NV4_PRM_IGNORE_0_SB_MIXER_DISABLED 0x0 -#define NV4_PRM_IGNORE_0_SB_MIXER_WRITES 0x1 -#define NV4_PRM_IGNORE_0_SB_MIXER_READS 0x2 -#define NV4_PRM_IGNORE_0_SB_MIXER_READS_WRITES 0x3 - -// -// PIO submission -// - -#define NV4_USER_START 0x800000 -#define NV4_USER_END 0xFFFFFF - -#define NV4_USER_OBJECT(i,j) (0x800000+(i)*0x10000+(j)*0x2000) -#define NV4_USER_OBJECT_SIZE_1 16 -#define NV4_USER_OBJECT_SIZE_2 8 -#define NV4_USER_OBJECT_HANDLE 0 -#define NV4_USER_FREE016(i,j) (0x800010+(i)*65536+(j)*8192) -#define NV4_USER_FREE016_SIZE_1 16 -#define NV4_USER_FREE016_SIZE_2 8 -#define NV4_USER_FREE016_COUNT_LO 0 -#define NV4_USER_FREE016_COUNT_LO_0 0x0 -#define NV4_USER_FREE016_COUNT 2 -#define NV4_USER_FREE016_COUNT_HI 10 -#define NV4_USER_FREE016_COUNT_HI_0 0x0 -#define NV4_USER_FREE032(i,j) (0x800010+(i)*65536+(j)*8192) -#define NV4_USER_FREE032_SIZE_1 16 -#define NV4_USER_FREE032_SIZE_2 8 -#define NV4_USER_FREE032_COUNT_LO 0 -#define NV4_USER_FREE032_COUNT_LO_0 0x0 -#define NV4_USER_FREE032_COUNT 2 -#define NV4_USER_FREE032_COUNT_HI 10 -#define NV4_USER_FREE032_COUNT_HI_0 0x0 -#define NV4_USER_ZERO016(i,j,k) (0x0800012+(i)*65536+(j)*8192+(k)*2) -#define NV4_USER_ZERO016_SIZE_1 16 -#define NV4_USER_ZERO016_SIZE_2 8 -#define NV4_USER_ZERO016_SIZE_3 7 -#define NV4_USER_ZERO016_COUNT 0 -#define NV4_USER_ZERO016_COUNT_0 0x0 -#define NV4_USER_ZERO032(i,j,k) (0x0800014+(i)*65536+(j)*8192+(k)*4) -#define NV4_USER_ZERO032_SIZE_1 16 -#define NV4_USER_ZERO032_SIZE_2 8 -#define NV4_USER_ZERO032_SIZE_3 3 -#define NV4_USER_ZERO032_COUNT 0 -#define NV4_USER_ZERO032_COUNT_0 0x0 -#define NV4_USER_DMA_PUT(i,j) (0x800040+(i)*0x10000+(j)*0x2000) -#define NV4_USER_DMA_PUT_OFFSET 2 -#define NV4_USER_DMA_GET(i,j) (0x800044+(i)*0x10000+(j)*0x2000) -#define NV4_USER_DMA_GET_OFFSET 2 - -#define NV4_USER_ADR_CHID 16 -#define NV4_USER_ADR_SUBCHID 13 -#define NV4_USER_ADR_METHOD 0 -#define NV4_USER_DEVICE 16 - -#define NV4_PTIMER_START 0x9000 -#define NV4_PTIMER_END 0x9FFF - -#define NV4_PTIMER_INTR 0x9100 -#define NV4_PTIMER_INTR_ALARM 0 -#define NV4_PTIMER_INTR_ALARM_NOT_PENDING 0x0 -#define NV4_PTIMER_INTR_ALARM_PENDING 0x1 -#define NV4_PTIMER_INTR_ALARM_RESET 0x1 -#define NV4_PTIMER_INTR_EN 0x9140 -#define NV4_PTIMER_INTR_EN_ALARM 0 -#define NV4_PTIMER_INTR_EN_ALARM_ENABLED 0x1 // 0 = disabled -#define NV4_PTIMER_NUMERATOR 0x9200 -#define NV4_PTIMER_NUMERATOR_VALUE 0 -#define NV4_PTIMER_NUMERATOR_VALUE_0 0x0 -#define NV4_PTIMER_DENOMINATOR 0x9210 -#define NV4_PTIMER_DENOMINATOR_VALUE 0 -#define NV4_PTIMER_DENOMINATOR_VALUE_0 0x0 -#define NV4_PTIMER_TIME_0 0x9400 -#define NV4_PTIMER_TIME_0_NSEC 5 -#define NV4_PTIMER_TIME_1 0x9410 -#define NV4_PTIMER_TIME_1_NSEC 0 -#define NV4_PTIMER_ALARM 0x9420 -#define NV4_PTIMER_ALARM_NSEC 5 - -#define NV4_TRACE 0xFFFF: 0x0 -#define NV4_TRACE_DATA ( 0*32+ 7):( 0*32+ 0) -#define NV4_TRACE_ACCESS ( 0*32+14):( 0*32+14) -#define NV4_TRACE_ACCESS_WRITE 0x0 -#define NV4_TRACE_ACCESS_READ 0x1 -#define NV4_TRACE_TYPE ( 0*32+15):( 0*32+15) -#define NV4_TRACE_TYPE_IO 0x0 -#define NV4_TRACE_TYPE_MEMORY 0x1 -#define NV4_TRACE_ADDRESS ( 0*32+31):( 0*32+16) - -#define NV4_RAMHT_SIZE_0 0xFFF -#define NV4_RAMHT_SIZE_1 0x1FFF -#define NV4_RAMHT_SIZE_2 0x3FFF -#define NV4_RAMHT_SIZE_3 0x7FFF -#define NV4_RAMHT_HANDLE ( 0*32+31):( 0*32+ 0) -#define NV4_RAMHT_INSTANCE ( 1*32+15):( 1*32+ 0) -#define NV4_RAMHT_ENGINE ( 1*32+17):( 1*32+16) -#define NV4_RAMHT_ENGINE_SW 0x0 -#define NV4_RAMHT_ENGINE_GRAPHICS 0x1 -#define NV4_RAMHT_ENGINE_DVD 0x2 -#define NV4_RAMHT_CHID ( 1*32+27):( 1*32+24) -#define NV4_RAMHT_STATUS ( 1*32+31):( 1*32+31) -#define NV4_RAMHT_STATUS_INVALID 0x0 -#define NV4_RAMHT_STATUS_VALID 0x1 - -#define NV4_RAMRO_SIZE_0 0x1FF -#define NV4_RAMRO_SIZE_1 0x1FFF -#define NV4_RAMRO_METHOD ( 0*32+12):( 0*32+ 0) -#define NV4_RAMRO_SUBCHANNEL ( 0*32+15):( 0*32+13) -#define NV4_RAMRO_CHID ( 0*32+22):( 0*32+16) -#define NV4_RAMRO_TYPE ( 0*32+23):( 0*32+23) -#define NV4_RAMRO_TYPE_WRITE 0x0 -#define NV4_RAMRO_TYPE_READ 0x1 -#define NV4_RAMRO_BYTE_ENABLES ( 0*32+27):( 0*32+24) -#define NV4_RAMRO_REASON ( 0*32+31):( 0*32+28) -#define NV4_RAMRO_REASON_ILLEGAL_ACCESS 0x0 -#define NV4_RAMRO_REASON_NO_CACHE_AVAILABLE 0x1 -#define NV4_RAMRO_REASON_CACHE_RAN_OUT 0x2 -#define NV4_RAMRO_REASON_FREE_COUNT_OVERRUN 0x3 -#define NV4_RAMRO_REASON_CAUGHT_LYING 0x4 -#define NV4_RAMRO_REASON_RESERVED_ACCESS 0x5 -#define NV4_RAMRO_DATA ( 1*32+31):( 1*32+ 0) - -#define NV4_RAMFC_SIZE_0 0x1FF -#define NV4_RAMFC_DMA_PUT ( 0*32+28):( 0*32+ 2) -#define NV4_RAMFC_DMA_GET ( 1*32+28):( 1*32+ 2) -#define NV4_RAMFC_DMA_INST ( 2*32+15):( 2*32+ 0) -#define NV4_RAMFC_DMA_METHOD ( 3*32+12):( 3*32+ 2) -#define NV4_RAMFC_DMA_SUBCHANNEL ( 3*32+15):( 3*32+13) -#define NV4_RAMFC_DMA_METHOD_COUNT ( 3*32+28):( 3*32+18) -#define NV4_RAMFC_DMA_FETCH_TRIG ( 4*32+ 7):( 4*32+ 3) -#define NV4_RAMFC_DMA_FETCH_SIZE ( 4*32+15):( 4*32+13) -#define NV4_RAMFC_DMA_FETCH_MAX_REQS ( 4*32+19):( 4*32+16) -#define NV4_RAMFC_ENGINE_SUB_0 ( 5*32+ 1):( 5*32+ 0) -#define NV4_RAMFC_ENGINE_SUB_1 ( 5*32+ 5):( 5*32+ 4) -#define NV4_RAMFC_ENGINE_SUB_2 ( 5*32+ 9):( 5*32+ 8) -#define NV4_RAMFC_ENGINE_SUB_3 ( 5*32+13):( 5*32+12) -#define NV4_RAMFC_ENGINE_SUB_4 ( 5*32+17):( 5*32+16) -#define NV4_RAMFC_ENGINE_SUB_5 ( 5*32+21):( 5*32+20) -#define NV4_RAMFC_ENGINE_SUB_6 ( 5*32+25):( 5*32+24) -#define NV4_RAMFC_ENGINE_SUB_7 ( 5*32+29):( 5*32+28) -#define NV4_RAMFC_ENGINE_SW 0x0 -#define NV4_RAMFC_ENGINE_GRAPHICS 0x1 -#define NV4_RAMFC_ENGINE_DVD 0x2 -#define NV4_RAMFC_PULL1_ENGINE ( 6*32+ 1):( 6*32+ 0) -#define NV4_RAMFC_PULL1_ENGINE_SW 0x0 -#define NV4_RAMFC_PULL1_ENGINE_GRAPHICS 0x1 -#define NV4_RAMFC_PULL1_ENGINE_DVD 0x2 - - -#define NV4_RAMDVD_CTX_TABLE (63*32+31):( 0*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT(c,s) (((c)*4+((s)/2))*32+((s)%2)*16+15):(((c)*4+((s)/2))*32+((s)%2)*16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_0 ( 0*32+15):( 0*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_1 ( 0*32+31):( 0*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_2 ( 1*32+15):( 1*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_3 ( 1*32+31):( 1*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_4 ( 2*32+15):( 2*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_5 ( 2*32+31):( 2*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_6 ( 3*32+15):( 3*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_0_7 ( 3*32+31):( 3*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_0 (60*32+15):(60*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_1 (60*32+31):(60*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_2 (61*32+15):(61*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_3 (61*32+31):(61*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_4 (62*32+15):(62*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_5 (62*32+31):(62*32+16) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_6 (63*32+15):(63*32+ 0) -#define NV4_RAMDVD_CTX_TABLE_OBJECT_15_7 (63*32+31):(63*32+16) - -#define NV4_DMA_CLASS ( 0*32+11):( 0*32+ 0) -#define NV4_DMA_PAGE_TABLE ( 0*32+12):( 0*32+12) -#define NV4_DMA_PAGE_TABLE_NOT_PRESENT 0x0 -#define NV4_DMA_PAGE_TABLE_PRESENT 0x1 -#define NV4_DMA_PAGE_ENTRY ( 0*32+13):( 0*32+13) -#define NV4_DMA_PAGE_ENTRY_NOT_LINEAR 0x0 -#define NV4_DMA_PAGE_ENTRY_LINEAR 0x1 -#define NV4_DMA_TARGET_NODE ( 0*32+17):( 0*32+16) -#define NV4_DMA_TARGET_NODE_NVM 0x0 -#define NV4_DMA_TARGET_NODE_PCI 0x2 -#define NV4_DMA_TARGET_NODE_AGP 0x3 -#define NV4_DMA_ADJUST ( 0*32+31):( 0*32+20) -#define NV4_DMA_LIMIT ( 1*32+31):( 1*32+ 0) -#define NV4_DMA_ACCESS ( 2*32+ 1):( 2*32+ 1) -#define NV4_DMA_ACCESS_READ_ONLY 0x0 -#define NV4_DMA_ACCESS_READ_AND_WRITE 0x1 -#define NV4_DMA_FRAME_ADDRESS ( 2*32+31):( 2*32+12) - -#define NV4_SUBCHAN_CTX_SWITCH ( 0*32+31):( 0*32+ 0) -#define NV4_SUBCHAN_DMA_INSTANCE ( 1*32+15):( 1*32+ 0) -#define NV4_SUBCHAN_NOTIFY_INSTANCE ( 1*32+31):( 1*32+16) -#define NV4_SUBCHAN_MEMFMT_INSTANCE ( 2*32+15):( 2*32+ 0) -#define NV4_SUBCHAN_MEMFMT_LINEAR ( 2*32+16):( 2*32+16) -#define NV4_SUBCHAN_MEMFMT_LINEAR_OUT 0x0 -#define NV4_SUBCHAN_MEMFMT_LINEAR_IN 0x1 \ No newline at end of file diff --git a/src/include/86box/utils/video_stdlib.h b/src/include/86box/utils/video_stdlib.h deleted file mode 100644 index 0d4b148d6..000000000 --- a/src/include/86box/utils/video_stdlib.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Standard library for implementation of video functionality that is duplicated across multiple cards. - * - * - * - * Authors: Connor Hyde - * - * Copyright 2025 Connor Hyde - */ - - -/* ROP */ - -#define VIDEO_ROP_SRC_COPY 0xCC - -int32_t video_rop_gdi_ternary(int32_t rop, int32_t src, int32_t dst, int32_t pattern); \ No newline at end of file diff --git a/src/include/86box/video.h b/src/include/86box/video.h index c87ef4f77..81424dbcb 100644 --- a/src/include/86box/video.h +++ b/src/include/86box/video.h @@ -630,13 +630,6 @@ extern const device_t voodoo_3_3500_se_agp_device; extern const device_t voodoo_3_3500_si_agp_device; extern const device_t velocity_100_agp_device; extern const device_t velocity_200_agp_device; -extern const device_t nv1_device_edge2k; -extern const device_t nv1_device_edge3k; -extern const device_t nv3_device_pci; -extern const device_t nv3_device_agp; -extern const device_t nv3t_device_pci; -extern const device_t nv3t_device_agp; -extern const device_t nv4_device_agp; /* Wyse 700 */ extern const device_t wy700_device; diff --git a/src/qt/CMakeLists.txt b/src/qt/CMakeLists.txt index 87ff7293a..1a004d958 100644 --- a/src/qt/CMakeLists.txt +++ b/src/qt/CMakeLists.txt @@ -171,15 +171,7 @@ add_library(ui STATIC qt_newfloppydialog.ui qt_harddiskdialog.cpp qt_harddiskdialog.hpp - qt_harddiskdialog.ui - - qt_gpudebug_vram.cpp - qt_gpudebug_vram.hpp - qt_gpudebug_vram.ui - - qt_gpudebug_visualnv.cpp - qt_gpudebug_visualnv.hpp - qt_gpudebug_visualnv.ui + qt_harddiskdialog.ui qt_harddrive_common.cpp qt_harddrive_common.hpp diff --git a/src/qt/qt_gpudebug_visualnv.cpp b/src/qt/qt_gpudebug_visualnv.cpp deleted file mode 100644 index 3b2ba8472..000000000 --- a/src/qt/qt_gpudebug_visualnv.cpp +++ /dev/null @@ -1,177 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * GPU Debugging Tools - Visual NV Debugger implementation - * - * - * - * Authors: starfrost - * - * Copyright 2025 starfrost - */ - -/* C++ includes */ -#include -#include - - -/* Qt includes*/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ui_qt_gpudebug_visualnv.h" - -/* 86Box core includes */ -extern "C" -{ - /* NOTE: DO NOT REMOVE */ - #include <86box/86box.h> - #include <86box/device.h> - #include <86box/mem.h> - #include <86box/pci.h> - #include <86box/rom.h> - #include <86box/video.h> - #include <86box/nv/vid_nv.h> - #include <86box/nv/vid_nv3.h> -} - -VisualNVDialog::VisualNVDialog(QWidget *parent) - : QDialog(parent) - , ui(new Ui::VisualNVDialog) -{ - ui->setupUi(this); - - connect(ui->btnLoadSavestate, &QPushButton::clicked, this, &VisualNVDialog::on_btnLoadSavestate_clicked); - connect(ui->fbStartAddress, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_fbStartAddress_changed); - connect(ui->bPitch0Value, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_bPitch0Value_changed); - connect(ui->bPitch1Value, &QPlainTextEdit::textChanged, this, &VisualNVDialog::on_bPitch1Value_changed); -} - -// VisualNV dialog destructor -VisualNVDialog::~VisualNVDialog() -{ - -} - -void VisualNVDialog::on_btnLoadSavestate_clicked() -{ - if (!nv3) - return; - - QString bar0_file_name = QFileDialog::getOpenFileName - ( - this, - tr("Please provide NVPlay 0.3.0.7+ NV3BAR0.BIN file"), - ".", - tr("NVPlay MMIO Dump Files (*.bin)") - ); - - QString bar1_file_name = QFileDialog::getOpenFileName - ( - this, - tr("Please provide NVPlay 0.3.0.7+ NV3BAR1.BIN file"), - ".", - tr("NVPlay VRAM/RAMIN Dump Files (*.bin)") - ); - - // - // Open both dump files - // - - QFile bar0(bar0_file_name); - QFile bar1(bar1_file_name); - - if (!bar0.open(QIODevice::ReadOnly)) - { - warning("Failed to open NV3BAR0.bin!"); - return; - } - - if (!bar1.open(QIODevice::ReadOnly)) - { - warning("Failed to open NV3BAR1.bin!"); - return; - } - - if (bar0.size() != NV3_MMIO_SIZE - || bar1.size() != NV3_MMIO_SIZE) - { - warning("NV3BAR0.bin and NV3BAR1.bin must be 16MB!"); - bar0.close(); - bar1.close(); - return; - } - - // Load VRAM contents only for now. Todo: MMIO+RAMIN - QString oldTitle = this->windowTitle(); - - this->setWindowTitle(tr("RIVA 128 Realtime Debugger: Savestate Loading...")); - - bar1.read((char*)nv3->nvbase.svga.vram, nv3->nvbase.vram_amount); - - this->setWindowTitle(oldTitle); - -} - -void VisualNVDialog::on_fbStartAddress_changed() -{ - if (nv3) - { - nv3->nvbase.debug_dba_enabled = true; - - bool ok = true; - - nv3->nvbase.debug_dba = ui->fbStartAddress->toPlainText().toInt(&ok); - - if (!ok) - nv3->nvbase.debug_dba_enabled = false; - } -} - -void VisualNVDialog::on_bPitch0Value_changed() -{ - if (nv3) - { - bool ok = true; - - uint32_t old_bpitch = nv3->pgraph.bpitch[0]; - - nv3->pgraph.bpitch[0] = ui->bPitch0Value->toPlainText().toInt(&ok); - - if (!ok) - nv3->pgraph.bpitch[0] = old_bpitch; - } - -} - -void VisualNVDialog::on_bPitch1Value_changed() -{ - if (nv3) - { - bool ok = true; - - uint32_t old_bpitch = nv3->pgraph.bpitch[1]; - - nv3->pgraph.bpitch[1] = ui->bPitch0Value->toPlainText().toInt(&ok); - - if (!ok) - nv3->pgraph.bpitch[1] = old_bpitch; - } - -} \ No newline at end of file diff --git a/src/qt/qt_gpudebug_visualnv.hpp b/src/qt/qt_gpudebug_visualnv.hpp deleted file mode 100644 index ee87dc0b3..000000000 --- a/src/qt/qt_gpudebug_visualnv.hpp +++ /dev/null @@ -1,46 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * GPU Debugging Tools - VRAM Viewer headers - * - * - * - * Authors: starfrost - * - * Copyright 2025 starfrost - */ - - -#pragma once - -#include - -namespace Ui -{ - class VisualNVDialog; -} - -class VisualNVDialog : public QDialog -{ - Q_OBJECT - - public: - explicit VisualNVDialog(QWidget *parent = nullptr); - ~VisualNVDialog(); - - void on_btnLoadSavestate_clicked(); - void on_fbStartAddress_changed(); - void on_bPitch0Value_changed(); - void on_bPitch1Value_changed(); - - protected: - private: - Ui::VisualNVDialog* ui; - - -}; \ No newline at end of file diff --git a/src/qt/qt_gpudebug_visualnv.ui b/src/qt/qt_gpudebug_visualnv.ui deleted file mode 100644 index ce45c4e44..000000000 --- a/src/qt/qt_gpudebug_visualnv.ui +++ /dev/null @@ -1,213 +0,0 @@ - - - VisualNVDialog - - - - 0 - 0 - 620 - 350 - - - - - 0 - 0 - - - - - 620 - 350 - - - - - 620 - 350 - - - - RIVA 128 Realtime Debugger - - - - - - - - 10 - 0 - 201 - 171 - - - - PFIFO State - - - - - - 220 - 0 - 361 - 171 - - - - PGRAPH State - - - - - - 10 - 180 - 571 - 141 - - - - VRAM Control - - - - - 160 - 30 - 104 - 21 - - - - - - - 10 - 30 - 151 - 21 - - - - <html><head/><body><p>VRAM Visual Aperture Start</p></body></html> - - - - - - 390 - 30 - 91 - 16 - - - - <html><head/><body><p>FB Start Address:</p></body></html> - - - - - - 480 - 30 - 81 - 16 - - - - <html><head/><body><p><span style=" font-weight:700;">PLACEHOLDER</span></p></body></html> - - - - - - 160 - 60 - 104 - 21 - - - - - - - 10 - 60 - 151 - 21 - - - - <html><head/><body><p>Pixel Depth</p></body></html> - - - - - - 10 - 110 - 231 - 24 - - - - Load nvplay savestate from real hardware - - - - - - 390 - 60 - 61 - 16 - - - - <html><head/><body><p>BPITCH[0]:</p></body></html> - - - - - - 460 - 60 - 104 - 21 - - - - - - - 460 - 90 - 104 - 21 - - - - - - - 390 - 90 - 61 - 16 - - - - <html><head/><body><p>BPITCH[1]:</p></body></html> - - - - - - - - - - diff --git a/src/qt/qt_gpudebug_vram.cpp b/src/qt/qt_gpudebug_vram.cpp deleted file mode 100644 index 000f41263..000000000 --- a/src/qt/qt_gpudebug_vram.cpp +++ /dev/null @@ -1,54 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * GPU Debugging Tools - VRAM Viewer implementation - * - * - * - * Authors: starfrost - * - * Copyright 2025 starfrost - */ - -/* C++ includes */ -#include -#include - - -/* Qt includes*/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ui_qt_gpudebug_vram.h" - -/* 86Box core includes */ -extern "C" -{ - -} - -GPUDebugVRAMDialog::GPUDebugVRAMDialog(QWidget *parent) - : QDialog(parent) - , ui(new Ui::GPUDebugVRAMDialog) -{ - ui->setupUi(this); -} - -GPUDebugVRAMDialog::~GPUDebugVRAMDialog() -{ - -} \ No newline at end of file diff --git a/src/qt/qt_gpudebug_vram.hpp b/src/qt/qt_gpudebug_vram.hpp deleted file mode 100644 index 18b2e8c96..000000000 --- a/src/qt/qt_gpudebug_vram.hpp +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * GPU Debugging Tools - VRAM Viewer headers - * - * - * - * Authors: starfrost - * - * Copyright 2025 starfrost - */ - - -#pragma once - -#include - -namespace Ui -{ - class GPUDebugVRAMDialog; -} - -class GPUDebugVRAMDialog : public QDialog -{ - Q_OBJECT - - public: - explicit GPUDebugVRAMDialog(QWidget *parent = nullptr); - ~GPUDebugVRAMDialog(); - protected: - private: - Ui::GPUDebugVRAMDialog* ui; - - -}; \ No newline at end of file diff --git a/src/qt/qt_gpudebug_vram.ui b/src/qt/qt_gpudebug_vram.ui deleted file mode 100644 index a92a60306..000000000 --- a/src/qt/qt_gpudebug_vram.ui +++ /dev/null @@ -1,42 +0,0 @@ - - - GPUDebugVRAMDialog - - - - 0 - 0 - 600 - 400 - - - - - 0 - 0 - - - - - 600 - 400 - - - - - 600 - 400 - - - - VRAM Viewer - - - - - - - - - - diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index e0900d1ef..954547078 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -24,8 +24,6 @@ #include "qt_mainwindow.hpp" #include "ui_qt_mainwindow.h" -#include "ui_qt_gpudebug_vram.h" -#include "ui_qt_gpudebug_visualnv.h" #include "qt_specifydimensions.h" #include "qt_soundgain.hpp" @@ -108,8 +106,6 @@ void qt_set_sequence_auto_mnemonic(bool b); #include "qt_mediamenu.hpp" #include "qt_util.hpp" -#include "qt_gpudebug_vram.hpp" - #if defined __unix__ && !defined __HAIKU__ # ifndef Q_OS_MACOS # include "evdev_keyboard.hpp" @@ -289,7 +285,29 @@ MainWindow::MainWindow(QWidget *parent) this->setWindowTitle(QString("%1 - %2 %3").arg(vmname, EMU_NAME, EMU_VERSION_FULL)); connect(this, &MainWindow::hardResetCompleted, this, [this]() { - onHardResetCompleted(); + ui->actionMCA_devices->setVisible(machine_has_bus(machine, MACHINE_BUS_MCA)); + num_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); + scroll_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); + caps_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); + int ext_ax_kbd = machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD) && + (keyboard_type == KEYBOARD_TYPE_AX); + int int_ax_kbd = machine_has_flags(machine, MACHINE_KEYBOARD_JIS) && + !machine_has_bus(machine, MACHINE_BUS_PS2_PORTS); + kana_label->setVisible(ext_ax_kbd || int_ax_kbd); + while (QApplication::overrideCursor()) + QApplication::restoreOverrideCursor(); +#ifdef USE_WACOM + ui->menuTablet_tool->menuAction()->setVisible(mouse_input_mode >= 1); +#else + ui->menuTablet_tool->menuAction()->setVisible(false); +#endif + + bool enable_comp_option = false; + for (int i = 0; i < MONITORS_NUM; i++) { + if (monitors[i].mon_composite) { enable_comp_option = true; break; } + } + + ui->actionCGA_composite_settings->setEnabled(enable_comp_option); }); connect(this, &MainWindow::showMessageForNonQtThread, this, &MainWindow::showMessage_, Qt::QueuedConnection); @@ -890,50 +908,6 @@ MainWindow::MainWindow(QWidget *parent) updateShortcuts(); } -void MainWindow::onHardResetCompleted() -{ - ui->actionMCA_devices->setVisible(machine_has_bus(machine, MACHINE_BUS_MCA)); - num_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); - scroll_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); - caps_label->setVisible(machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD)); - int ext_ax_kbd = machine_has_bus(machine, MACHINE_BUS_PS2_PORTS | MACHINE_BUS_AT_KBD) && - (keyboard_type == KEYBOARD_TYPE_AX); - int int_ax_kbd = machine_has_flags(machine, MACHINE_KEYBOARD_JIS) && - !machine_has_bus(machine, MACHINE_BUS_PS2_PORTS); - kana_label->setVisible(ext_ax_kbd || int_ax_kbd); - while (QApplication::overrideCursor()) - QApplication::restoreOverrideCursor(); -#ifdef USE_WACOM - ui->menuTablet_tool->menuAction()->setVisible(mouse_input_mode >= 1); -#else - ui->menuTablet_tool->menuAction()->setVisible(false); -#endif - - bool enable_comp_option = false; - for (int i = 0; i < MONITORS_NUM; i++) { - if (monitors[i].mon_composite) { enable_comp_option = true; break; } - } - - ui->actionCGA_composite_settings->setEnabled(enable_comp_option); - -#ifdef ENABLE_NV_LOG - /* - THIS CODE SUCKS AND THIS DESIGN IS TERRIBLE - EVERYTHING ABOUT IT IS BAD AND WRONG. - ENTIRE DEVICE SUBSYSTEM IDEALLY WOULD BE DECOUPLED FROM UI BUT MEH - */ - - const device_t* vid_device = video_card_getdevice(gfxcard[0]); - - bool is_nv3 = (vid_device == &nv3_device_agp - || vid_device == &nv3_device_pci - || vid_device == &nv3t_device_agp - || vid_device == &nv3t_device_pci); - - ui->actionDebug_GPUDebug_VisualNv->setVisible(is_nv3); -#endif -} - - void MainWindow::closeEvent(QCloseEvent *event) { @@ -2551,29 +2525,3 @@ void MainWindow::on_actionCGA_composite_settings_triggered() config_save(); } - -void MainWindow::on_actionDebug_GPUDebug_VRAM_triggered() -{ - debugVramDialog = new GPUDebugVRAMDialog(this); - debugVramDialog->setWindowFlag(Qt::CustomizeWindowHint, true); - debugVramDialog->setWindowFlag(Qt::WindowTitleHint, true); - debugVramDialog->setWindowFlag(Qt::WindowSystemMenuHint, false); - // If I have this as a NON-MODAL dialog, input is just eaten without doing anything - // WTF?!?!?!?!? - //debugVramDialog->show(); - debugVramDialog->exec(); - -} - - -void MainWindow::on_actionDebug_GPUDebug_VisualNv_triggered() -{ - visualNvDialog = new VisualNVDialog(this); - visualNvDialog->setWindowFlag(Qt::CustomizeWindowHint, true); - visualNvDialog->setWindowFlag(Qt::WindowTitleHint, true); - visualNvDialog->setWindowFlag(Qt::WindowSystemMenuHint, false); - // If I have this as a NON-MODAL dialog, input is just eaten without doing anything - // WTF?!?!?!?!? - //visualNvDialog->show(); - visualNvDialog->exec(); -} \ No newline at end of file diff --git a/src/qt/qt_mainwindow.hpp b/src/qt/qt_mainwindow.hpp index 6ae838896..f562c2ea9 100644 --- a/src/qt/qt_mainwindow.hpp +++ b/src/qt/qt_mainwindow.hpp @@ -17,11 +17,6 @@ extern QTimer discordupdate; -// NON-modal dialogs -#include "qt_gpudebug_vram.hpp" -#include "qt_gpudebug_visualnv.hpp" - - class MediaMenu; class RendererStack; @@ -79,8 +74,6 @@ signals: public slots: void showSettings(); void hardReset(); - void onHardResetCompleted(); - void togglePause(); void initRendererMonitorSlot(int monitor_index); void destroyRendererMonitorSlot(int monitor_index); @@ -143,9 +136,7 @@ private slots: void on_actionPreferences_triggered(); void on_actionEnable_Discord_integration_triggered(bool checked); void on_actionRenderer_options_triggered(); - void on_actionDebug_GPUDebug_VRAM_triggered(); - void on_actionDebug_GPUDebug_VisualNv_triggered(); - + void refreshMediaMenu(); void showMessage_(int flags, const QString &header, const QString &message, bool richText, std::atomic_bool* done = nullptr); void getTitle_(wchar_t *title); @@ -184,10 +175,6 @@ private slots: private: Ui::MainWindow *ui; - - // NON-modal dialogs - these use ::show() and therefore have to be maintained as objects - GPUDebugVRAMDialog *debugVramDialog; - VisualNVDialog *visualNvDialog; std::unique_ptr status; std::shared_ptr mm; diff --git a/src/qt/qt_mainwindow.ui b/src/qt/qt_mainwindow.ui index bebef8c88..ca7aca2ca 100644 --- a/src/qt/qt_mainwindow.ui +++ b/src/qt/qt_mainwindow.ui @@ -251,19 +251,11 @@ - - - &Debugging Tools - - - - - @@ -927,27 +919,7 @@ &CGA composite settings... - - - - - GPU Debug - VRAM Viewer - - - - - RIVA 128 Realtime Debugger - - - - - GPU Debug - VRAM Viewer - - - - - RIVA 128 Realtime Debugger - + @@ -1077,54 +1049,6 @@ &8x - - - true - - - &Full screen stretch - - - - - true - - - &4:3 - - - - - true - - - &Square pixels (Keep ratio) - - - - - true - - - &Integer scale - - - - - true - - - 4:&3 Integer scale - - - - - true - - - &1x - - diff --git a/src/sound/snd_emu8k.c b/src/sound/snd_emu8k.c index b806f3ccb..c3efdaaff 100644 --- a/src/sound/snd_emu8k.c +++ b/src/sound/snd_emu8k.c @@ -1525,7 +1525,7 @@ emu8k_outw(uint16_t addr, uint16_t val, void *priv) default: break; } - emu8k_log("EMU8K WRITE: : Unknown register write: %04X-%02X(%d/%d): %04X \n", addr, (emu8k->cur_reg) << 5 | emu8k->cur_voice, + emu8k_log("EMU8K WRITE: Unknown register write: %04X-%02X(%d/%d): %04X \n", addr, (emu8k->cur_reg) << 5 | emu8k->cur_voice, emu8k->cur_reg, emu8k->cur_voice, val); } diff --git a/src/sound/snd_sb.c b/src/sound/snd_sb.c index fe9be9c2d..f041ebb8c 100644 --- a/src/sound/snd_sb.c +++ b/src/sound/snd_sb.c @@ -798,7 +798,7 @@ sb_ct1335_mixer_write(uint16_t addr, uint8_t val, void *priv) break; default: - sb_log("sb_ct1335: : Unknown register write: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); + sb_log("sb_ct1335: Unknown register WRITE: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); break; } } @@ -899,7 +899,7 @@ sb_ct1345_mixer_write(uint16_t addr, uint8_t val, void *priv) break; default: - sb_log("sb_ct1345: : Unknown register write: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); + sb_log("sb_ct1345: Unknown register WRITE: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); break; } } diff --git a/src/utils/CMakeLists.txt b/src/utils/CMakeLists.txt index fab669d28..bcbc7aafd 100644 --- a/src/utils/CMakeLists.txt +++ b/src/utils/CMakeLists.txt @@ -24,7 +24,4 @@ add_library(utils OBJECT ini.c log.c random.c - - # VIDEO - video/video_rop.c ) diff --git a/src/utils/log.c b/src/utils/log.c index b8c28afab..f0eb6aa3c 100644 --- a/src/utils/log.c +++ b/src/utils/log.c @@ -44,7 +44,6 @@ typedef struct log_t { char **cyclic_buff; int32_t cyclic_last_line; int32_t log_cycles; - int32_t last_repeat_order; } log_t; /* File to log output to. */ @@ -220,18 +219,9 @@ log_out_cyclic(void* priv, const char* fmt, va_list ap) } - if (is_cycle) - { - if (log->cyclic_last_line % repeat_order == 0) - { - log->log_cycles++; - - // If the order of the log repeat changes - if (log->last_repeat_order != repeat_order - && log->last_repeat_order > 0) - { - log->log_cycles = 1; - } + if (is_cycle) { + if (log->cyclic_last_line % repeat_order == 0) { + log->log_cycles++; if (log->log_cycles == 1) { /* @@ -275,13 +265,10 @@ log_out_cyclic(void* priv, const char* fmt, va_list ap) } log->cyclic_last_line++; - - log->last_repeat_order = repeat_order; } } #endif - void log_fatal(void *priv, const char *fmt, ...) { diff --git a/src/utils/video/video_rop.c b/src/utils/video/video_rop.c deleted file mode 100644 index 146822201..000000000 --- a/src/utils/video/video_rop.c +++ /dev/null @@ -1,790 +0,0 @@ -#include -#include <86box/utils/video_stdlib.h> - -/* - Implements a standard GDI ternary rop for e.g. bitblit acceleration. - For further information on this function, refer to the documentation on Win32 GDI: - - https://learn.microsoft.com/en-us/windows/win32/gdi/binary-raster-operations - - This is currently used in the following graphics cards: Tseng Labs ET4000/32p, Cirrus Logic CL-GD54xx, 3dfx Voodoo Banshee/Voodoo 3, Trident TGUI9440, - S3 ViRGE, C&T 69000, ATI Mach64, and NVidia RIVA 128 -*/ -int32_t video_rop_gdi_ternary(int32_t rop, int32_t src, int32_t dst, int32_t pattern) -{ - uint32_t out = 0x00; - - switch (rop) - { - case 0x00: - out = 0; - break; - case 0x01: - out = ~(dst | (pattern | src)); - break; - case 0x02: - out = dst & ~(pattern | src); - break; - case 0x03: - out = ~(pattern | src); - break; - case 0x04: - out = src & ~(dst | pattern); - break; - case 0x05: - out = ~(dst | pattern); - break; - case 0x06: - out = ~(pattern | ~(dst ^ src)); - break; - case 0x07: - out = ~(pattern | (dst & src)); - break; - case 0x08: - out = src & (dst & ~pattern); - break; - case 0x09: - out = ~(pattern | (dst ^ src)); - break; - case 0x0a: - out = dst & ~pattern; - break; - case 0x0b: - out = ~(pattern | (src & ~dst)); - break; - case 0x0c: - out = src & ~pattern; - break; - case 0x0d: - out = ~(pattern | (dst & ~src)); - break; - case 0x0e: - out = ~(pattern | ~(dst | src)); - break; - case 0x0f: - out = ~pattern; - break; - case 0x10: - out = pattern & ~(dst | src); - break; - case 0x11: - out = ~(dst | src); - break; - case 0x12: - out = ~(src | ~(dst ^ pattern)); - break; - case 0x13: - out = ~(src | (dst & pattern)); - break; - case 0x14: - out = ~(dst | ~(pattern ^ src)); - break; - case 0x15: - out = ~(dst | (pattern & src)); - break; - case 0x16: - out = pattern ^ (src ^ (dst & ~(pattern & src))); - break; - case 0x17: - out = ~(src ^ ((src ^ pattern) & (dst ^ src))); - break; - case 0x18: - out = (src ^ pattern) & (pattern ^ dst); - break; - case 0x19: - out = ~(src ^ (dst & ~(pattern & src))); - break; - case 0x1a: - out = pattern ^ (dst | (src & pattern)); - break; - case 0x1b: - out = ~(src ^ (dst & (pattern ^ src))); - break; - case 0x1c: - out = pattern ^ (src | (dst & pattern)); - break; - case 0x1d: - out = ~(dst ^ (src & (pattern ^ dst))); - break; - case 0x1e: - out = pattern ^ (dst | src); - break; - case 0x1f: - out = ~(pattern & (dst | src)); - break; - case 0x20: - out = dst & (pattern & ~src); - break; - case 0x21: - out = ~(src | (dst ^ pattern)); - break; - case 0x22: - out = dst & ~src; - break; - case 0x23: - out = ~(src | (pattern & ~dst)); - break; - case 0x24: - out = (src ^ pattern) & (dst ^ src); - break; - case 0x25: - out = ~(pattern ^ (dst & ~(src & pattern))); - break; - case 0x26: - out = src ^ (dst | (pattern & src)); - break; - case 0x27: - out = src ^ (dst | ~(pattern ^ src)); - break; - case 0x28: - out = dst & (pattern ^ src); - break; - case 0x29: - out = ~(pattern ^ (src ^ (dst | (pattern & src)))); - break; - case 0x2a: - out = dst & ~(pattern & src); - break; - case 0x2b: - out = ~(src ^ ((src ^ pattern) & (pattern ^ dst))); - break; - case 0x2c: - out = src ^ (pattern & (dst | src)); - break; - case 0x2d: - out = pattern ^ (src | ~dst); - break; - case 0x2e: - out = pattern ^ (src | (dst ^ pattern)); - break; - case 0x2f: - out = ~(pattern & (src | ~dst)); - break; - case 0x30: - out = pattern & ~src; - break; - case 0x31: - out = ~(src | (dst & ~pattern)); - break; - case 0x32: - out = src ^ (dst | (pattern | src)); - break; - case 0x33: - out = ~src; - break; - case 0x34: - out = src ^ (pattern | (dst & src)); - break; - case 0x35: - out = src ^ (pattern | ~(dst ^ src)); - break; - case 0x36: - out = src ^ (dst | pattern); - break; - case 0x37: - out = ~(src & (dst | pattern)); - break; - case 0x38: - out = pattern ^ (src & (dst | pattern)); - break; - case 0x39: - out = src ^ (pattern | ~dst); - break; - case 0x3a: - out = src ^ (pattern | (dst ^ src)); - break; - case 0x3b: - out = ~(src & (pattern | ~dst)); - break; - case 0x3c: - out = pattern ^ src; - break; - case 0x3d: - out = src ^ (pattern | ~(dst | src)); - break; - case 0x3e: - out = src ^ (pattern | (dst & ~src)); - break; - case 0x3f: - out = ~(pattern & src); - break; - case 0x40: - out = pattern & (src & ~dst); - break; - case 0x41: - out = ~(dst | (pattern ^ src)); - break; - case 0x42: - out = (src ^ dst) & (pattern ^ dst); - break; - case 0x43: - out = ~(src ^ (pattern & ~(dst & src))); - break; - case 0x44: - out = src & ~dst; - break; - case 0x45: - out = ~(dst | (pattern & ~src)); - break; - case 0x46: - out = dst ^ (src | (pattern & dst)); - break; - case 0x47: - out = ~(pattern ^ (src & (dst ^ pattern))); - break; - case 0x48: - out = src & (dst ^ pattern); - break; - case 0x49: - out = ~(pattern ^ (dst ^ (src | (pattern & dst)))); - break; - case 0x4a: - out = dst ^ (pattern & (src | dst)); - break; - case 0x4b: - out = pattern ^ (dst | ~src); - break; - case 0x4c: - out = src & ~(dst & pattern); - break; - case 0x4d: - out = ~(src ^ ((src ^ pattern) | (dst ^ src))); - break; - case 0x4e: - out = pattern ^ (dst | (src ^ pattern)); - break; - case 0x4f: - out = ~(pattern & (dst | ~src)); - break; - case 0x50: - out = pattern & ~dst; - break; - case 0x51: - out = ~(dst | (src & ~pattern)); - break; - case 0x52: - out = dst ^ (pattern | (src & dst)); - break; - case 0x53: - out = ~(src ^ (pattern & (dst ^ src))); - break; - case 0x54: - out = ~(dst | ~(pattern | src)); - break; - case 0x55: - out = ~dst; - break; - case 0x56: - out = dst ^ (pattern | src); - break; - case 0x57: - out = ~(dst & (pattern | src)); - break; - case 0x58: - out = pattern ^ (dst & (src | pattern)); - break; - case 0x59: - out = dst ^ (pattern | ~src); - break; - case 0x5a: - out = dst ^ pattern; - break; - case 0x5b: - out = dst ^ (pattern | ~(src | dst)); - break; - case 0x5c: - out = dst ^ (pattern | (src ^ dst)); - break; - case 0x5d: - out = ~(dst & (pattern | ~src)); - break; - case 0x5e: - out = dst ^ (pattern | (src & ~dst)); - break; - case 0x5f: - out = ~(dst & pattern); - break; - case 0x60: - out = pattern & (dst ^ src); - break; - case 0x61: - out = ~(dst ^ (src ^ (pattern | (dst & src)))); - break; - case 0x62: - out = dst ^ (src & (pattern | dst)); - break; - case 0x63: - out = src ^ (dst | ~pattern); - break; - case 0x64: - out = src ^ (dst & (pattern | src)); - break; - case 0x65: - out = dst ^ (src | ~pattern); - break; - case 0x66: - out = dst ^ src; - break; - case 0x67: - out = src ^ (dst | ~(pattern | src)); - break; - case 0x68: - out = ~(dst ^ (src ^ (pattern | ~(dst | src)))); - break; - case 0x69: - out = ~(pattern ^ (dst ^ src)); - break; - case 0x6a: - out = dst ^ (pattern & src); - break; - case 0x6b: - out = ~(pattern ^ (src ^ (dst & (pattern | src)))); - break; - case 0x6c: - out = src ^ (dst & pattern); - break; - case 0x6d: - out = ~(pattern ^ (dst ^ (src & (pattern | dst)))); - break; - case 0x6e: - out = src ^ (dst & (pattern | ~src)); - break; - case 0x6f: - out = ~(pattern & ~(dst ^ src)); - break; - case 0x70: - out = pattern & ~(dst & src); - break; - case 0x71: - out = ~(src ^ ((src ^ dst) & (pattern ^ dst))); - break; - case 0x72: - out = src ^ (dst | (pattern ^ src)); - break; - case 0x73: - out = ~(src & (dst | ~pattern)); - break; - case 0x74: - out = dst ^ (src | (pattern ^ dst)); - break; - case 0x75: - out = ~(dst & (src | ~pattern)); - break; - case 0x76: - out = src ^ (dst | (pattern & ~src)); - break; - case 0x77: - out = ~(dst & src); - break; - case 0x78: - out = pattern ^ (dst & src); - break; - case 0x79: - out = ~(dst ^ (src ^ (pattern & (dst | src)))); - break; - case 0x7a: - out = dst ^ (pattern & (src | ~dst)); - break; - case 0x7b: - out = ~(src & ~(dst ^ pattern)); - break; - case 0x7c: - out = src ^ (pattern & (dst | ~src)); - break; - case 0x7d: - out = ~(dst & ~(pattern ^ src)); - break; - case 0x7e: - out = (src ^ pattern) | (dst ^ src); - break; - case 0x7f: - out = ~(dst & (pattern & src)); - break; - case 0x80: - out = dst & (pattern & src); - break; - case 0x81: - out = ~((src ^ pattern) | (dst ^ src)); - break; - case 0x82: - out = dst & ~(pattern ^ src); - break; - case 0x83: - out = ~(src ^ (pattern & (dst | ~src))); - break; - case 0x84: - out = src & ~(dst ^ pattern); - break; - case 0x85: - out = ~(pattern ^ (dst & (src | ~pattern))); - break; - case 0x86: - out = dst ^ (src ^ (pattern & (dst | src))); - break; - case 0x87: - out = ~(pattern ^ (dst & src)); - break; - case 0x88: - out = dst & src; - break; - case 0x89: - out = ~(src ^ (dst | (pattern & ~src))); - break; - case 0x8a: - out = dst & (src | ~pattern); - break; - case 0x8b: - out = ~(dst ^ (src | (pattern ^ dst))); - break; - case 0x8c: - out = src & (dst | ~pattern); - break; - case 0x8d: - out = ~(src ^ (dst | (pattern ^ src))); - break; - case 0x8e: - out = src ^ ((src ^ dst) & (pattern ^ dst)); - break; - case 0x8f: - out = ~(pattern & ~(dst & src)); - break; - case 0x90: - out = pattern & ~(dst ^ src); - break; - case 0x91: - out = ~(src ^ (dst & (pattern | ~src))); - break; - case 0x92: - out = dst ^ (pattern ^ (src & (dst | pattern))); - break; - case 0x93: - out = ~(src ^ (pattern & dst)); - break; - case 0x94: - out = pattern ^ (src ^ (dst & (pattern | src))); - break; - case 0x95: - out = ~(dst ^ (pattern & src)); - break; - case 0x96: - out = dst ^ (pattern ^ src); - break; - case 0x97: - out = pattern ^ (src ^ (dst | ~(pattern | src))); - break; - case 0x98: - out = ~(src ^ (dst | ~(pattern | src))); - break; - case 0x99: - out = ~(dst ^ src); - break; - case 0x9a: - out = dst ^ (pattern & ~src); - break; - case 0x9b: - out = ~(src ^ (dst & (pattern | src))); - break; - case 0x9c: - out = src ^ (pattern & ~dst); - break; - case 0x9d: - out = ~(dst ^ (src & (pattern | dst))); - break; - case 0x9e: - out = dst ^ (src ^ (pattern | (dst & src))); - break; - case 0x9f: - out = ~(pattern & (dst ^ src)); - break; - case 0xa0: - out = dst & pattern; - break; - case 0xa1: - out = ~(pattern ^ (dst | (src & ~pattern))); - break; - case 0xa2: - out = dst & (pattern | ~src); - break; - case 0xa3: - out = ~(dst ^ (pattern | (src ^ dst))); - break; - case 0xa4: - out = ~(pattern ^ (dst | ~(src | pattern))); - break; - case 0xa5: - out = ~(pattern ^ dst); - break; - case 0xa6: - out = dst ^ (src & ~pattern); - break; - case 0xa7: - out = ~(pattern ^ (dst & (src | pattern))); - break; - case 0xa8: - out = dst & (pattern | src); - break; - case 0xa9: - out = ~(dst ^ (pattern | src)); - break; - case 0xaa: - out = dst; - break; - case 0xab: - out = dst | ~(pattern | src); - break; - case 0xac: - out = src ^ (pattern & (dst ^ src)); - break; - case 0xad: - out = ~(dst ^ (pattern | (src & dst))); - break; - case 0xae: - out = dst | (src & ~pattern); - break; - case 0xaf: - out = dst | ~pattern; - break; - case 0xb0: - out = pattern & (dst | ~src); - break; - case 0xb1: - out = ~(pattern ^ (dst | (src ^ pattern))); - break; - case 0xb2: - out = src ^ ((src ^ pattern) | (dst ^ src)); - break; - case 0xb3: - out = ~(src & ~(dst & pattern)); - break; - case 0xb4: - out = pattern ^ (src & ~dst); - break; - case 0xb5: - out = ~(dst ^ (pattern & (src | dst))); - break; - case 0xb6: - out = dst ^ (pattern ^ (src | (dst & pattern))); - break; - case 0xb7: - out = ~(src & (dst ^ pattern)); - break; - case 0xb8: - out = pattern ^ (src & (dst ^ pattern)); - break; - case 0xb9: - out = ~(dst ^ (src | (pattern & dst))); - break; - case 0xba: - out = dst | (pattern & ~src); - break; - case 0xbb: - out = dst | ~src; - break; - case 0xbc: - out = src ^ (pattern & ~(dst & src)); - break; - case 0xbd: - out = ~((src ^ dst) & (pattern ^ dst)); - break; - case 0xbe: - out = dst | (pattern ^ src); - break; - case 0xbf: - out = dst | ~(pattern & src); - break; - case 0xc0: - out = pattern & src; - break; - case 0xc1: - out = ~(src ^ (pattern | (dst & ~src))); - break; - case 0xc2: - out = ~(src ^ (pattern | ~(dst | src))); - break; - case 0xc3: - out = ~(pattern ^ src); - break; - case 0xc4: - out = src & (pattern | ~dst); - break; - case 0xc5: - out = ~(src ^ (pattern | (dst ^ src))); - break; - case 0xc6: - out = src ^ (dst & ~pattern); - break; - case 0xc7: - out = ~(pattern ^ (src & (dst | pattern))); - break; - case 0xc8: - out = src & (dst | pattern); - break; - case 0xc9: - out = ~(src ^ (pattern | dst)); - break; - case 0xca: - out = dst ^ (pattern & (src ^ dst)); - break; - case 0xcb: - out = ~(src ^ (pattern | (dst & src))); - break; - case 0xcc: - out = src; - break; - case 0xcd: - out = src | ~(dst | pattern); - break; - case 0xce: - out = src | (dst & ~pattern); - break; - case 0xcf: - out = src | ~pattern; - break; - case 0xd0: - out = pattern & (src | ~dst); - break; - case 0xd1: - out = ~(pattern ^ (src | (dst ^ pattern))); - break; - case 0xd2: - out = pattern ^ (dst & ~src); - break; - case 0xd3: - out = ~(src ^ (pattern & (dst | src))); - break; - case 0xd4: - out = src ^ ((src ^ pattern) & (pattern ^ dst)); - break; - case 0xd5: - out = ~(dst & ~(pattern & src)); - break; - case 0xd6: - out = pattern ^ (src ^ (dst | (pattern & src))); - break; - case 0xd7: - out = ~(dst & (pattern ^ src)); - break; - case 0xd8: - out = pattern ^ (dst & (src ^ pattern)); - break; - case 0xd9: - out = ~(src ^ (dst | (pattern & src))); - break; - case 0xda: - out = dst ^ (pattern & ~(src & dst)); - break; - case 0xdb: - out = ~((src ^ pattern) & (dst ^ src)); - break; - case 0xdc: - out = src | (pattern & ~dst); - break; - case 0xdd: - out = src | ~dst; - break; - case 0xde: - out = src | (dst ^ pattern); - break; - case 0xdf: - out = src | ~(dst & pattern); - break; - case 0xe0: - out = pattern & (dst | src); - break; - case 0xe1: - out = ~(pattern ^ (dst | src)); - break; - case 0xe2: - out = dst ^ (src & (pattern ^ dst)); - break; - case 0xe3: - out = ~(pattern ^ (src | (dst & pattern))); - break; - case 0xe4: - out = src ^ (dst & (pattern ^ src)); - break; - case 0xe5: - out = ~(pattern ^ (dst | (src & pattern))); - break; - case 0xe6: - out = src ^ (dst & ~(pattern & src)); - break; - case 0xe7: - out = ~((src ^ pattern) & (pattern ^ dst)); - break; - case 0xe8: - out = src ^ ((src ^ pattern) & (dst ^ src)); - break; - case 0xe9: - out = ~(dst ^ (src ^ (pattern & ~(dst & src)))); - break; - case 0xea: - out = dst | (pattern & src); - break; - case 0xeb: - out = dst | ~(pattern ^ src); - break; - case 0xec: - out = src | (dst & pattern); - break; - case 0xed: - out = src | ~(dst ^ pattern); - break; - case 0xee: - out = dst | src; - break; - case 0xef: - out = src | (dst | ~pattern); - break; - case 0xf0: - out = pattern; - break; - case 0xf1: - out = pattern | ~(dst | src); - break; - case 0xf2: - out = pattern | (dst & ~src); - break; - case 0xf3: - out = pattern | ~src; - break; - case 0xf4: - out = pattern | (src & ~dst); - break; - case 0xf5: - out = pattern | ~dst; - break; - case 0xf6: - out = pattern | (dst ^ src); - break; - case 0xf7: - out = pattern | ~(dst & src); - break; - case 0xf8: - out = pattern | (dst & src); - break; - case 0xf9: - out = pattern | ~(dst ^ src); - break; - case 0xfa: - out = dst | pattern; - break; - case 0xfb: - out = dst | (pattern | ~src); - break; - case 0xfc: - out = pattern | src; - break; - case 0xfd: - out = pattern | (src | ~dst); - break; - case 0xfe: - out = dst | (pattern | src); - break; - case 0xff: - out = ~0; - break; - } - - return out; -} \ No newline at end of file diff --git a/src/video/CMakeLists.txt b/src/video/CMakeLists.txt index f1d755dba..98a9cb385 100644 --- a/src/video/CMakeLists.txt +++ b/src/video/CMakeLists.txt @@ -11,7 +11,7 @@ # Authors: David Hrdlička, # # Copyright 2020-2021 David Hrdlička. -# Copyright 2025 Connor Hyde / starfrost +# Copyright 2025 starfrost # add_library(vid OBJECT @@ -136,77 +136,12 @@ add_library(vid OBJECT # Matrox vid_mga.c - # NVidia - Core - nv/nv_base.c + # NVidia (pending) nv/nv_rivatimer.c - # NVidia NV1 - nv/nv1/nv1_core.c - nv/nv1/nv1_core_config.c - - # NVidia RIVA 128 - Subsystems - nv/nv3/nv3_core.c - nv/nv3/nv3_core_config.c - nv/nv3/nv3_core_arbiter.c - - nv/nv3/subsystems/nv3_pramdac.c - nv/nv3/subsystems/nv3_pfifo.c - nv/nv3/subsystems/nv3_pgraph.c - nv/nv3/subsystems/nv3_pmc.c - nv/nv3/subsystems/nv3_pme.c - nv/nv3/subsystems/nv3_pextdev.c - nv/nv3/subsystems/nv3_pfb.c - nv/nv3/subsystems/nv3_pbus.c - nv/nv3/subsystems/nv3_pbus_dma.c - nv/nv3/subsystems/nv3_ptimer.c - nv/nv3/subsystems/nv3_pramin.c - nv/nv3/subsystems/nv3_pramin_ramht.c - nv/nv3/subsystems/nv3_pramin_ramfc.c - nv/nv3/subsystems/nv3_pramin_ramro.c - nv/nv3/subsystems/nv3_pvideo.c - nv/nv3/subsystems/nv3_user.c - - # NVidia RIVA 128 - Object Classes - nv/nv3/classes/nv3_class_names.c - nv/nv3/classes/nv3_class_shared_methods.c - nv/nv3/classes/nv3_class_001_beta_factor.c - nv/nv3/classes/nv3_class_002_rop.c - nv/nv3/classes/nv3_class_003_chroma_key.c - nv/nv3/classes/nv3_class_004_plane_mask.c - nv/nv3/classes/nv3_class_005_clipping_rectangle.c - nv/nv3/classes/nv3_class_006_pattern.c - nv/nv3/classes/nv3_class_007_rectangle.c - nv/nv3/classes/nv3_class_008_point.c - nv/nv3/classes/nv3_class_009_line.c - nv/nv3/classes/nv3_class_00a_lin.c - nv/nv3/classes/nv3_class_00b_triangle.c - nv/nv3/classes/nv3_class_00c_win95_gdi_text.c - nv/nv3/classes/nv3_class_00d_m2mf.c - nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c - nv/nv3/classes/nv3_class_010_blit.c - nv/nv3/classes/nv3_class_011_image.c - nv/nv3/classes/nv3_class_012_bitmap.c - nv/nv3/classes/nv3_class_014_transfer2memory.c - nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c - nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c - nv/nv3/classes/nv3_class_018_point_zeta_buffer.c - nv/nv3/classes/nv3_class_01c_image_in_memory.c - - # NVidia RIVA 128 - Render - nv/nv3/render/nv3_render_core.c - nv/nv3/render/nv3_render_primitives.c - nv/nv3/render/nv3_render_blit.c - - # NVidia RIVA TNT/TNT2 - Core - nv/nv4/nv4_core.c - nv/nv4/nv4_core_io.c - nv/nv4/nv4_core_config.c - nv/nv4/nv4_debug_register_list.c - nv/nv4/subsystems/nv4_pramdac.c - nv/nv4/subsystems/nv4_ptimer.c - # Generic vid_bochs_vbe.c + ) if(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") diff --git a/src/video/nv/nv1/nv1_core.c b/src/video/nv/nv1/nv1_core.c deleted file mode 100644 index 3de528b26..000000000 --- a/src/video/nv/nv1/nv1_core.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 bringup and device emulation. - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv1.h> - - -void nv1_init() -{ - -} - -void* nv1_init_edge2k(const device_t *info) -{ - -} - -void* nv1_init_edge3k(const device_t *info) -{ - -} - -void nv1_close(void* priv) -{ - -} - -void nv1_speed_changed(void *priv) -{ - -} - -void nv1_draw_cursor(svga_t* svga, int32_t drawline) -{ - -} - -void nv1_recalc_timings(svga_t* svga) -{ - -} - -void nv1_force_redraw(void* priv) -{ - -} - -// See if the bios rom is available. -int32_t nv1_available(void) -{ - return (rom_present(NV1_VBIOS_E3D_2X00) - || rom_present(NV1_VBIOS_E3D_3X00)); -} - -// NV3 (RIVA 128) -// PCI -// 2MB or 4MB VRAM -const device_t nv1_device_edge2k = -{ - .name = "nVIDIA NV1 [Diamond Edge 3D 2x00] [Not Direct3D Compatible]", - .internal_name = "nv1_edge2k", - .flags = DEVICE_PCI, - .local = 0, - .init = nv1_init_edge2k, - .close = nv1_close, - .speed_changed = nv1_speed_changed, - .force_redraw = nv1_force_redraw, - .available = nv1_available, - .config = nv1_config, -}; - -// NV3 (RIVA 128) -// AGP -// 2MB or 4MB VRAM -const device_t nv1_device_edge3k = -{ - .name = "nVIDIA NV1 [Diamond Edge 3D 3x00] [Not Direct3D Compatible]", - .internal_name = "nv1_edge3k", - .flags = DEVICE_PCI, - .local = 0, - .init = nv1_init_edge3k, - .close = nv1_close, - .speed_changed = nv1_speed_changed, - .force_redraw = nv1_force_redraw, - .available = nv1_available, - .config = nv1_config, -}; diff --git a/src/video/nv/nv1/nv1_core_config.c b/src/video/nv/nv1/nv1_core_config.c deleted file mode 100644 index 460067f6f..000000000 --- a/src/video/nv/nv1/nv1_core_config.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Provides NV4 configuration - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv1.h> - -const device_config_t nv1_config[] = -{ - // Memory configuration - { - .name = "vram_size", - .description = "VRAM Size", - .type = CONFIG_SELECTION, - .default_int = NV1_VRAM_SIZE_4MB, - .selection = - { - // I thought this was never released, but it seems that at least one was released: - // The card was called the "NEC G7AGK" - { - .description = "1 MB", - .value = NV1_VRAM_SIZE_1MB, - }, - { - .description = "2 MB", - .value = NV1_VRAM_SIZE_2MB, - }, - { - .description = "4 MB", - .value = NV1_VRAM_SIZE_4MB, - }, - } - - }, - // Multithreading configuration - { - - .name = "pgraph_threads", -#ifndef RELEASE_BUILD - .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", -#else - .description = "Render threads", -#endif - .type = CONFIG_SELECTION, - .default_int = 1, // todo: change later - .selection = - { - { - .description = "1 thread (Only use if issues appear with more threads)", - .value = 1, - }, - { - .description = "2 threads", - .value = 2, - }, - { - .description = "4 threads", - .value = 4, - }, - { - .description = "8 threads", - .value = 8, - }, - }, - }, - { - .name = "RAMDAC Type", - .description = "SGS-Thomson RAMDAC type", - .default_int = 0x1764, - .type = CONFIG_SELECTION, - .selection = - { - { - .description = "SGS-Thomson STG-1732X", - .value = 0x1732, - }, - { - .description = "SGS-Thomson STG-1764X/NVDAC64", - .value = 0x1764, - }, - } - }, - { - .name = "Chip type", - .description = "Chip type", - .default_int = 0x1, - .type = CONFIG_SELECTION, - .selection = - { - { - .description = "SGS-Thomson STG-2000", - .value = 0x2000, - }, - { - .description = "Nvidia NV1", - .value = 0x1, - }, - } - }, -#ifndef RELEASE_BUILD - { - .name = "nv_debug_fulllog", - .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", - .type = CONFIG_BINARY, - .default_int = 0, - }, -#endif - { - .type = CONFIG_END - } -}; \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c b/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c deleted file mode 100644 index 4520a941f..000000000 --- a/src/video/nv/nv3/classes/nv3_class_001_beta_factor.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x01 (Beta factor) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_001_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - /* even if we don't do anything with this yet... */ - case NV3_BETA_FACTOR: - if (param & 0x80000000) /* bit0 */ - nv3->pgraph.beta_factor = 0; - else - nv3->pgraph.beta_factor = param & 0x7F800000; - - nv_log("Method Execution: Beta Factor = %02x", nv3->pgraph.beta_factor); - - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_002_rop.c b/src/video/nv/nv3/classes/nv3_class_002_rop.c deleted file mode 100644 index 56b135888..000000000 --- a/src/video/nv/nv3/classes/nv3_class_002_rop.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x02 (Render operation) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_002_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_ROP_SET_ROP: - nv3->pgraph.rop = param & 0xFF; - nv_log("Method Execution: ROP = %02x\n", nv3->pgraph.rop); - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c b/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c deleted file mode 100644 index f19a06932..000000000 --- a/src/video/nv/nv3/classes/nv3_class_003_chroma_key.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x02 (Chroma/color key) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_003_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_CHROMA_UNKNOWN_0200: - nv_log("Method Execution: Chroma Unknown 0x0200 0x%08x", param); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - - break; - case NV3_CHROMA_KEY: - { - nv3_color_expanded_t expanded_color = nv3_render_expand_color(param, grobj); - - nv3->pgraph.chroma_key = nv3_render_to_chroma(expanded_color); - - nv_log("Method Execution: Chroma = 0x%08x", nv3->pgraph.chroma_key); - break; - } - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c b/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c deleted file mode 100644 index d93de9bc1..000000000 --- a/src/video/nv/nv3/classes/nv3_class_004_plane_mask.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x02 (Plane mask) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_004_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c b/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c deleted file mode 100644 index c7ec3ae98..000000000 --- a/src/video/nv/nv3/classes/nv3_class_005_clipping_rectangle.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x05 (Clipping rectangle) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_005_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_CLIP_POSITION: - nv3->pgraph.clip_start.x = (param >> 16) & 0xFFFF; - nv3->pgraph.clip_start.y = (param) & 0xFFFF; - nv_log("Method Execution: Clip Position: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); - break; - case NV3_CLIP_SIZE: - nv3->pgraph.clip_size.x = (param >> 16) & 0xFFFF; - nv3->pgraph.clip_size.y = (param) & 0xFFFF; - nv_log("Method Execution: Clip Size: %d,%d\n", nv3->pgraph.clip_start.x, nv3->pgraph.clip_start.y); - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_006_pattern.c b/src/video/nv/nv3/classes/nv3_class_006_pattern.c deleted file mode 100644 index 5aa5bf0fc..000000000 --- a/src/video/nv/nv3/classes/nv3_class_006_pattern.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x06 (Pattern) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_006_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - /* Valid software method, suppress logging */ - case NV3_PATTERN_FORMAT: - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - case NV3_PATTERN_SHAPE: - /* If the shape is not valid, tell the software that it's invalid */ - - /* - Technically you are meant to do this: - - But in practice, I don't know, because it always submits 0x20 or 0x40, which are valid when param & 0x03, - and appear to be deliberate behaviour in the drivers rather than bugs. What - if (param > NV3_PATTERN_SHAPE_LAST_VALID) - { - warning("NV3 class 0x06 (Pattern) invalid shape %d (This is a bug)", param); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_INVALID_DATA); - return; - } - - */ - nv3->pgraph.pattern_shape = param & 0x03; - - break; - /* Seems to be "SetPatternSelect" on Riva TNT and later, but possibly called by accident on Riva 128. There is no hardware equivalent for this. So let's just suppress - the warnings. */ - case NV3_PATTERN_UNUSED_DRIVER_BUG: - break; - case NV3_PATTERN_COLOR0: - { - nv3_color_expanded_t expanded_colour0 = nv3_render_expand_color(param, grobj); - nv3_render_set_pattern_color(expanded_colour0, false); - break; - } - case NV3_PATTERN_COLOR1: - { - nv3_color_expanded_t expanded_colour1 = nv3_render_expand_color(param, grobj); - nv3_render_set_pattern_color(expanded_colour1, true); - break; - } - case NV3_PATTERN_BITMAP_HIGH: - nv3->pgraph.pattern_bitmap = 0; //reset - nv3->pgraph.pattern_bitmap |= ((uint64_t)param << 32); - break; - case NV3_PATTERN_BITMAP_LOW: - nv3->pgraph.pattern_bitmap |= param; - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c b/src/video/nv/nv3/classes/nv3_class_007_rectangle.c deleted file mode 100644 index d1273a84a..000000000 --- a/src/video/nv/nv3/classes/nv3_class_007_rectangle.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x07 (Rectangle) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_007_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_RECTANGLE_COLOR: - nv3->pgraph.rectangle.color = param; - break; - default: - /* Check for any rectangle point or size method. */ - if (method_id >= NV3_RECTANGLE_START && method_id <= NV3_RECTANGLE_END) - { - uint32_t index = (method_id - NV3_RECTANGLE_START) >> 3; - - // If the size is submitted, render it. - if (method_id & 0x04) - { - nv3->pgraph.rectangle.size[index].x = param & 0xFFFF; - nv3->pgraph.rectangle.size[index].y = (param >> 16) & 0xFFFF; - - nv_log("Method Execution: Rect%d Size=%d,%d Color=0x%08x\n", index, nv3->pgraph.rectangle.size[index].x, nv3->pgraph.rectangle.size[index].y, nv3->pgraph.rectangle.color); - - nv3_render_rect(nv3->pgraph.rectangle.position[index], nv3->pgraph.rectangle.size[index], nv3->pgraph.rectangle.color, grobj); - } - else // position - { - nv3->pgraph.rectangle.position[index].x = param & 0xFFFF; - nv3->pgraph.rectangle.position[index].y = (param >> 16) & 0xFFFF; - - nv_log("Method Execution: Rect%d Position=%d,%d\n", index, nv3->pgraph.rectangle.position[index].x, nv3->pgraph.rectangle.position[index].y); - } - - return; - } - - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_008_point.c b/src/video/nv/nv3/classes/nv3_class_008_point.c deleted file mode 100644 index 41002f745..000000000 --- a/src/video/nv/nv3/classes/nv3_class_008_point.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x08 (Point) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_008_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_009_line.c b/src/video/nv/nv3/classes/nv3_class_009_line.c deleted file mode 100644 index f149bb8b3..000000000 --- a/src/video/nv/nv3/classes/nv3_class_009_line.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x09 (Line) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_009_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00a_lin.c b/src/video/nv/nv3/classes/nv3_class_00a_lin.c deleted file mode 100644 index 473aaa214..000000000 --- a/src/video/nv/nv3/classes/nv3_class_00a_lin.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x0A (Lin - a line without starting or ending pixels) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_00a_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c b/src/video/nv/nv3/classes/nv3_class_00b_triangle.c deleted file mode 100644 index d08b7a72e..000000000 --- a/src/video/nv/nv3/classes/nv3_class_00b_triangle.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x0B (Basic triangle) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_00b_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c b/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c deleted file mode 100644 index 64d76c278..000000000 --- a/src/video/nv/nv3/classes/nv3_class_00c_win95_gdi_text.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x0C (Windows 95 GDI text acceleration) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_00c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - /* Type A: Unclipped Rectangle */ - - /* NOTE: This method is used by the GDI driver as part of the notification engine. */ - case NV3_W95TXT_A_COLOR: - nv3->pgraph.win95_gdi_text.color_a = param; - nv_log("Method Execution: GDI-A Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); - break; - /* Type B: Clipped Rectangle */ - case NV3_W95TXT_B_COLOR: - nv3->pgraph.win95_gdi_text.color_b = param; - nv_log("Method Execution: GDI-B Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_b); - break; - case NV3_W95TXT_B_CLIP_TOPLEFT: - nv3->pgraph.win95_gdi_text.clip_b.left = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_b.top = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-B Clip Left,Top %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.left, nv3->pgraph.win95_gdi_text.clip_b.top); - break; - case NV3_W95TXT_B_CLIP_BOTTOMRIGHT: - nv3->pgraph.win95_gdi_text.clip_b.bottom = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_b.right = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-B Clip Bottom,Right %04x,%04x", nv3->pgraph.win95_gdi_text.clip_b.right, nv3->pgraph.win95_gdi_text.clip_b.bottom); - break; - /* Type C: Unclipped Bitmap */ - case NV3_W95TXT_C_CLIP_COLOR: - nv3->pgraph.win95_gdi_text.color1_c = param; - nv_log("Method Execution: GDI-C Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color1_c); - break; - case NV3_W95TXT_C_CLIP_SIZE: - nv3->pgraph.win95_gdi_text.size_c.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_c.y = ((param >> 16) & 0xFFFF); - - nv3->pgraph.win95_gdi_text_bit_count = 0; - nv_log("Method Execution: GDI-C Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_c.x, nv3->pgraph.win95_gdi_text.size_c.y); - break; - case NV3_W95TXT_C_CLIP_POSITION: - nv3->pgraph.win95_gdi_text.point_c.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.point_c.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-C Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_c.x, nv3->pgraph.win95_gdi_text.point_c.y); - - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_c.x ; - nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_c.y; - - break; - case NV3_W95TXT_C_CLIP_TOPLEFT: - nv3->pgraph.win95_gdi_text.clip_c.left = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_c.top = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-C Clip Left,Top %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.top); - break; - case NV3_W95TXT_C_CLIP_BOTTOMRIGHT: - nv3->pgraph.win95_gdi_text.clip_c.right = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_c.bottom = ((param >> 16) & 0xFFFF); - /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ - nv_log("Method Execution: GDI-C Clip Right,Bottom %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.top); - break; - /* Type B and C not implemented YET, as they are not used by NT GDI driver */ - case NV3_W95TXT_D_CLIP_TOPLEFT: - nv3->pgraph.win95_gdi_text.clip_d.left = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_d.top = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-D Clip Left,Top %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); - break; - case NV3_W95TXT_D_CLIP_BOTTOMRIGHT: - nv3->pgraph.win95_gdi_text.clip_d.right = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_d.bottom = ((param >> 16) & 0xFFFF); - /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ - nv_log("Method Execution: GDI-D Clip Right,Bottom %04x,%04x\n", nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.top); - break; - - case NV3_W95TXT_D_CLIP_COLOR: - nv3->pgraph.win95_gdi_text.color1_d = param; - nv_log("Method Execution: GDI-D Color 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); - break; - case NV3_W95TXT_D_CLIP_SIZE_IN: - nv3->pgraph.win95_gdi_text.size_in_d.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_in_d.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-D Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_d.x, nv3->pgraph.win95_gdi_text.size_in_d.y); - break; - case NV3_W95TXT_D_CLIP_SIZE_OUT: - nv3->pgraph.win95_gdi_text.size_out_d.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_out_d.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-D Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_d.x, nv3->pgraph.win95_gdi_text.size_out_d.y); - break; - case NV3_W95TXT_D_CLIP_POSITION: - nv3->pgraph.win95_gdi_text.point_d.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.point_d.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-D Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y); - - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; - nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_d.y; - nv3->pgraph.win95_gdi_text_bit_count = 0; - - break; - /* Type E: Two-colour 1bpp */ - case NV3_W95TXT_E_CLIP_TOPLEFT: - nv3->pgraph.win95_gdi_text.clip_e.left = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_e.top = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-E Clip Left,Top 0x%08x\n", nv3->pgraph.win95_gdi_text.clip_e.left, nv3->pgraph.win95_gdi_text.clip_e.top); - break; - case NV3_W95TXT_E_CLIP_BOTTOMRIGHT: - nv3->pgraph.win95_gdi_text.clip_e.right = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clip_e.bottom = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-E Clip Bottom,Right 0x%08x\n", nv3->pgraph.win95_gdi_text.clip_e.right, nv3->pgraph.win95_gdi_text.clip_e.bottom); - /* is it "only if we are out of the top left or the bottom right or is it "all of them"*/ - break; - case NV3_W95TXT_E_CLIP_COLOR_0: - nv3->pgraph.win95_gdi_text.color0_e = param; - nv_log("Method Execution: GDI-E Color0 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); - break; - case NV3_W95TXT_E_CLIP_COLOR_1: - nv3->pgraph.win95_gdi_text.color1_e = param; - nv_log("Method Execution: GDI-E Color1 0x%08x\n", nv3->pgraph.win95_gdi_text.color_a); - break; - case NV3_W95TXT_E_CLIP_SIZE_IN: - nv3->pgraph.win95_gdi_text.size_in_e.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_in_e.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-E Size In %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_in_e.x, nv3->pgraph.win95_gdi_text.size_in_e.y); - break; - case NV3_W95TXT_E_CLIP_SIZE_OUT: - nv3->pgraph.win95_gdi_text.size_out_e.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.size_out_e.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: GDI-E Size Out %04x,%04x\n", nv3->pgraph.win95_gdi_text.size_out_e.x, nv3->pgraph.win95_gdi_text.size_out_e.y); - break; - case NV3_W95TXT_E_CLIP_POSITION: - nv3->pgraph.win95_gdi_text.point_e.x = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.point_e.y = ((param >> 16) & 0xFFFF); - - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x; - nv3->pgraph.win95_gdi_text_current_position.y = nv3->pgraph.win95_gdi_text.point_e.y; - nv3->pgraph.win95_gdi_text_bit_count = 0; - - nv_log("Method Execution: GDI-E Point %04x,%04x\n", nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y); - break; - default: - /* Type A submission: these are the same things as rectangles */ - if (method_id >= NV3_W95TXT_A_RECT_START && method_id <= NV3_W95TXT_A_RECT_END) - { - uint32_t index = (method_id - NV3_W95TXT_A_RECT_START) >> 3; - - // IN THIS ONE SPECIFIC PLACE, ****AND ONLY THIS ONE SPECIFIC PLACE****, X AND Y ARE SWAPPED???? */ - // If the size is submitted, render it. - if (method_id & 0x04) - { - nv3->pgraph.win95_gdi_text.rect_a_size[index].x = (param >> 16) & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_size[index].y = param & 0xFFFF; - - nv_log("Method Execution: Rect GDI-A%d Size=%d,%d", index, nv3->pgraph.win95_gdi_text.rect_a_size[index].x, - nv3->pgraph.win95_gdi_text.rect_a_size[index].y); - - nv3_render_rect(nv3->pgraph.win95_gdi_text.rect_a_position[index], - nv3->pgraph.win95_gdi_text.rect_a_size[index], nv3->pgraph.win95_gdi_text.color_a, grobj); - } - else // position - { - nv3->pgraph.win95_gdi_text.rect_a_position[index].x = (param >> 16) & 0xFFFF; - nv3->pgraph.win95_gdi_text.rect_a_position[index].y = param & 0xFFFF; - - nv_log("Method Execution: Rect GDI-A%d Position=%d,%d\n", index, - nv3->pgraph.win95_gdi_text.rect_a_position[index].x, nv3->pgraph.win95_gdi_text.rect_a_position[index].y); - } - - return; - } - /* Type B: Clipped Rectangle */ - else if (method_id >= NV3_W95TXT_B_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_B_CLIP_CLIPRECT_END) - { - uint32_t index = (method_id - NV3_W95TXT_B_CLIP_CLIPRECT_START) >> 3; - - /* Works slightly differently, we define the bounds of the rectangle instead. */ - if (method_id & 0x04) - { - nv3->pgraph.win95_gdi_text.clipped_rect[index].right = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clipped_rect[index].bottom = ((param >> 16) & 0xFFFF); - - nv_log("Method Execution: Rect GDI-B%d Right,Bottom=%d,%d\n", index, nv3->pgraph.win95_gdi_text.clipped_rect[index].right, - nv3->pgraph.win95_gdi_text.clipped_rect[index].bottom); - - nv3_render_rect_clipped(nv3->pgraph.win95_gdi_text.clipped_rect[index], - nv3->pgraph.win95_gdi_text.color_b, grobj); - } - else // left,top - { - nv3->pgraph.win95_gdi_text.clipped_rect[index].left = (param & 0xFFFF); - nv3->pgraph.win95_gdi_text.clipped_rect[index].top = ((param >> 16) & 0xFFFF); - - nv_log("Method Execution: Rect GDI-B%d Left,Top=%d,%d\n", index, - nv3->pgraph.win95_gdi_text.clipped_rect[index].left, nv3->pgraph.win95_gdi_text.clipped_rect[index].top); - } - - return; - } - /* Type C */ - else if (method_id >= NV3_W95TXT_C_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_C_CLIP_CLIPRECT_END) - { - /* lol */ - uint32_t index = (method_id - NV3_W95TXT_C_CLIP_CLIPRECT_START) >> 3; - - nv3->pgraph.win95_gdi_text.bitmap_c[index] = param; - - /* Mammoth logger! */ - nv_log("Method Execution: Rect GDI-C%d Data=%08x Size%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", - index, param, nv3->pgraph.win95_gdi_text.size_c.x, nv3->pgraph.win95_gdi_text.size_c.y, - nv3->pgraph.win95_gdi_text.point_c.x, nv3->pgraph.win95_gdi_text.point_c.y, - nv3->pgraph.win95_gdi_text.color1_c, - nv3->pgraph.win95_gdi_text.clip_c.left, nv3->pgraph.win95_gdi_text.clip_c.right, - nv3->pgraph.win95_gdi_text.clip_c.top, nv3->pgraph.win95_gdi_text.clip_c.bottom); - - nv3_render_gdi_transparent_bitmap(false, nv3->pgraph.win95_gdi_text.color1_c, nv3->pgraph.win95_gdi_text.bitmap_c[index], grobj); - return; - } - else if (method_id >= NV3_W95TXT_D_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_D_CLIP_CLIPRECT_END) - { - /* lol */ - uint32_t index = (method_id - NV3_W95TXT_D_CLIP_CLIPRECT_START) >> 3; - - nv3->pgraph.win95_gdi_text.bitmap_d[index] = param; - - /* Mammoth logger! */ - nv_log("Method Execution: Rect GDI-D%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", - index, param, nv3->pgraph.win95_gdi_text.size_in_d.x, nv3->pgraph.win95_gdi_text.size_in_d.y, - nv3->pgraph.win95_gdi_text.size_out_d.x, nv3->pgraph.win95_gdi_text.size_out_d.y, - nv3->pgraph.win95_gdi_text.point_d.x, nv3->pgraph.win95_gdi_text.point_d.y, - nv3->pgraph.win95_gdi_text.color1_d, - nv3->pgraph.win95_gdi_text.clip_d.left, nv3->pgraph.win95_gdi_text.clip_d.right, - nv3->pgraph.win95_gdi_text.clip_d.top, nv3->pgraph.win95_gdi_text.clip_d.bottom); - - nv3_render_gdi_transparent_bitmap(true, nv3->pgraph.win95_gdi_text.color1_d, nv3->pgraph.win95_gdi_text.bitmap_d[index], grobj); - return; - } - else if (method_id >= NV3_W95TXT_E_CLIP_CLIPRECT_START && method_id <= NV3_W95TXT_E_CLIP_CLIPRECT_END) - { - /* lol */ - uint32_t index = (method_id - NV3_W95TXT_E_CLIP_CLIPRECT_START) >> 3; - - nv3->pgraph.win95_gdi_text.bitmap_e[index] = param; - - /* Mammoth logger! */ - nv_log("Method Execution: Rect GDI-E%d Data=%08x SizeIn%04x,%04x SizeOut%04x,%04x Point%04x,%04x Color=%08x Clip Left=0x%04x Right=0x%04x Top=0x%04x Bottom=0x%04x", - index, param, nv3->pgraph.win95_gdi_text.size_in_e.x, nv3->pgraph.win95_gdi_text.size_in_e.y, - nv3->pgraph.win95_gdi_text.size_out_e.x, nv3->pgraph.win95_gdi_text.size_out_e.y, - nv3->pgraph.win95_gdi_text.point_e.x, nv3->pgraph.win95_gdi_text.point_e.y, - nv3->pgraph.win95_gdi_text.color1_e, - nv3->pgraph.win95_gdi_text.clip_e.left, nv3->pgraph.win95_gdi_text.clip_e.right, nv3->pgraph.win95_gdi_text.clip_e.top, nv3->pgraph.win95_gdi_text.clip_e.bottom); - - nv3_render_gdi_1bpp_bitmap(nv3->pgraph.win95_gdi_text.color0_e, nv3->pgraph.win95_gdi_text.color1_e, nv3->pgraph.win95_gdi_text.bitmap_e[index], grobj); - return; - } - - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c b/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c deleted file mode 100644 index f07aab737..000000000 --- a/src/video/nv/nv3/classes/nv3_class_00d_m2mf.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x0D (Reformat image in memory) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_M2MF_IN_CTXDMA_OFFSET: - nv3->pgraph.m2mf.offset_in = param; - nv_log("Method Execution: M2MF Offset In = 0x%08x", param); - break; - case NV3_M2MF_OUT_CTXDMA_OFFSET: - nv3->pgraph.m2mf.offset_out = param; - nv_log("Method Execution: M2MF Offset Out = 0x%08x", param); - break; - case NV3_M2MF_IN_PITCH: - nv3->pgraph.m2mf.pitch_in = param; - nv_log("Method Execution: M2MF Pitch In = 0x%08x", param); - break; - case NV3_M2MF_OUT_PITCH: - nv3->pgraph.m2mf.pitch_out = param; - nv_log("Method Execution: M2MF Pitch Out = 0x%08x", param); - break; - case NV3_M2MF_SCANLINE_LENGTH_IN_BYTES: - nv3->pgraph.m2mf.scanline_length = param; - nv_log("Method Execution: M2MF Scanline Length in Bytes = 0x%08x", param); - break; - case NV3_M2MF_NUM_SCANLINES: - nv3->pgraph.m2mf.num_scanlines = param; - nv_log("Method Execution: M2MF Num Scanlines = 0x%08x", param); - break; - case NV3_M2MF_FORMAT: - nv3->pgraph.m2mf.format = param; - nv_log("Method Execution: M2MF Format = 0x%08x", param); - - // Format Done - start m2mf - - nv3_perform_dma_m2mf(grobj); - - break; - case NV3_M2MF_NOTIFY: - /* This is technically its own thing, but I don't know if it's ever a problem with how we've designed it */ - if (nv3->pgraph.notify_pending) - { - nv_log("WARNING: M2MF notification with notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); - nv_log("IF THIS BUILD WAS COMPILED WITH NV_LOG_ENABLE_ULTRA, YOU SHOULD SEE A CONTEXT BELOW"); - nv3_debug_ramin_print_context_info(param, context); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - - // disable - nv3->pgraph.notify_pending = false; - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - /* may need to disable fifo in this state */ - return; - } - - nv_log("Method Execution: TODO: ACTUALLY IMPLEMENT M2MF!!!!"); - // set a notify as pending. - nv3->pgraph.notifier = param; - nv3->pgraph.notify_pending = true; - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break;; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c b/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c deleted file mode 100644 index 457c8ade1..000000000 --- a/src/video/nv/nv3/classes/nv3_class_00e_scaled_image_from_mem.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x0E (Get image from vram and scale it) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_00e_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c deleted file mode 100644 index ed1ac465b..000000000 --- a/src/video/nv/nv3/classes/nv3_class_010_blit.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x10 (Blit something) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_BLIT_POSITION_IN: - nv3->pgraph.blit.point_in.x = (param & 0xFFFF); - nv3->pgraph.blit.point_in.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB POINT_IN %d,%d\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y); - break; - case NV3_BLIT_POSITION_OUT: - nv3->pgraph.blit.point_out.x = (param & 0xFFFF); - nv3->pgraph.blit.point_out.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB POINT_OUT %d,%d\n", nv3->pgraph.blit.point_out.x, nv3->pgraph.blit.point_out.y); - - break; - case NV3_BLIT_SIZE: - /* This is the last one*/ - nv3->pgraph.blit.size.x = (param & 0xFFFF); - nv3->pgraph.blit.size.y = ((param >> 16) & 0xFFFF); - nv_log("Method Execution: S2SB Size %d,%d grobj_0=0x%08x\n", nv3->pgraph.blit.size.x, nv3->pgraph.blit.size.y, grobj.grobj_0); - - nv3_render_blit_screen2screen(grobj); - - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_011_image.c b/src/video/nv/nv3/classes/nv3_class_011_image.c deleted file mode 100644 index 1eda15df7..000000000 --- a/src/video/nv/nv3/classes/nv3_class_011_image.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x11 (Color image) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_011_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - case NV3_IMAGE_START_POSITION: - nv3->pgraph.image.point.x = (param & 0xFFFF); - nv3->pgraph.image.point.y = (param >> 16); - nv_log("Method Execution: Image Point=%d,%d\n", nv3->pgraph.image.point.x, nv3->pgraph.image.point.y); - break; - /* Seems to allow scaling of the bitblt. */ - case NV3_IMAGE_SIZE: - nv3->pgraph.image.size.x = (param & 0xFFFF); - nv3->pgraph.image.size.y = (param >> 16); - nv_log("Method Execution: Image Size (Clip)=%d,%d\n", nv3->pgraph.image.size.x, nv3->pgraph.image.size.y); - break; - case NV3_IMAGE_SIZE_IN: - nv3->pgraph.image.size_in.x = (param & 0xFFFF); - nv3->pgraph.image.size_in.y = (param >> 16); - nv3->pgraph.image_current_position = nv3->pgraph.image.point; - nv_log("Method Execution: Image SizeIn=%d,%d\n", nv3->pgraph.image.size_in.x, nv3->pgraph.image.size_in.y); - break; - default: - if (method_id >= NV3_IMAGE_COLOR_START && method_id <= NV3_IMAGE_COLOR_END) - { - uint32_t pixel_slot = (method_id - NV3_IMAGE_COLOR_START) >> 2; - nv_log("Method Execution: Image Pixel%d Colour%08x Format%x\n", pixel_slot, param, (grobj.grobj_0) & 0x07); - nv3_render_blit_image(param, grobj); - } - else - { - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - - } - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c b/src/video/nv/nv3/classes/nv3_class_012_bitmap.c deleted file mode 100644 index 2ac47f0de..000000000 --- a/src/video/nv/nv3/classes/nv3_class_012_bitmap.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x12 (Monochrome bitmap) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_012_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c b/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c deleted file mode 100644 index b49b1fc89..000000000 --- a/src/video/nv/nv3/classes/nv3_class_014_transfer2memory.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x14 (Transfer to Memory) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_014_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c b/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c deleted file mode 100644 index 3fa88ba39..000000000 --- a/src/video/nv/nv3/classes/nv3_class_015_stretched_image_from_cpu.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x15 (stretched image from cpu to memory) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_015_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c deleted file mode 100644 index 3bb8f66d7..000000000 --- a/src/video/nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c +++ /dev/null @@ -1,40 +0,0 @@ -/* -* 86Box A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* This file is part of the 86Box distribution. -* -* NV3: Methods for class 0x17 (Direct3D 5.0 accelerated triangle with zeta buffer) -* -* -* -* Authors: Connor Hyde, I need a better email address ;^) -* -* Copyright 2024-2025 Connor Hyde -*/ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_017_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c b/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c deleted file mode 100644 index 87111b70c..000000000 --- a/src/video/nv/nv3/classes/nv3_class_018_point_zeta_buffer.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x18 (Point with zeta buffer) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -struct nv3_object_class_018 nv3_d3d5_point_zeta_buffer; - -void nv3_class_018_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c deleted file mode 100644 index 12ac3fe6b..000000000 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods for class 0x1C (Image in memory) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - /* We need this for a lot of methods, so may as well store it here. */ - uint32_t src_buffer_id = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER) & 0x03; - - - switch (method_id) - { - /* Color format of the image */ - case NV3_IMAGE_IN_MEMORY_COLOR_FORMAT: - { - // convert to how the bpixel registers represent surface - uint32_t real_format = 1; - - /* TODO: THIS CODE MIGHT BE NONSENSE - Convert between different internal representations of the pixel format, because Nvidia says: I WANT TO MAKE YOUR LIFE PAIN. - */ - switch (param) - { - case nv3_image_in_memory_pixel_format_x8g8b8r8: - real_format = 3; //32bit - // no change - break; - case nv3_image_in_memory_pixel_format_x1r5g5b5_p2: - real_format = 2; - break; - case nv3_image_in_memory_pixel_format_le_y16_p2: - real_format = 0; - break; - } - - /* Set the format */ - - nv3->pgraph.bpixel[src_buffer_id] = (real_format | NV3_BPIXEL_FORMAT_IS_VALID); - - nv_log("Method Execution: Image in Memory BUF%d COLOR_FORMAT=0x%04x\n", src_buffer_id, param); - - break; - } - /* DOn't log invalid */ - case NV3_IMAGE_IN_MEMORY_IN_MEMORY_DMA_CTX_TYPE: - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - /* Pitch - length between scanlines */ - case NV3_IMAGE_IN_MEMORY_PITCH: - nv3->pgraph.image_in_memory.pitch = param & 0x1FF0; - nv3->pgraph.bpitch[src_buffer_id] = param & 0x1FF0; // 12:0 - - nv_log("Method Execution: Image in Memory BUF%d PITCH=0x%04x\n", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); - break; - /* Byte offset in GPU VRAM of top left pixel (22:0) */ - case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX - nv3->pgraph.boffset[src_buffer_id] = param & 0x7FFFFF; - else - nv3->pgraph.boffset[src_buffer_id] = param & 0x3FFFFF; - - nv_log("Method Execution: Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x\n", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]); - break; - case NV3_NVCLASS_CRAP_START ... NV3_NVCLASS_CRAP_END: - /* Suppress but don't do anything */ - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - default: - warning("%s: Invalid or unimplemented method 0x%04x\n", nv3_class_names[context.class_id & 0x1F], method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_names.c b/src/video/nv/nv3/classes/nv3_class_names.c deleted file mode 100644 index 64e35d9b3..000000000 --- a/src/video/nv/nv3/classes/nv3_class_names.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Defines core class names for debugging purposes - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -/* These are the object classes AS RECOGNISED BY THE GRAPHICS HARDWARE. */ -/* The drivers implement a COMPLETELY DIFFERENT SET OF CLASSES. */ - -/* THERE CAN ONLY BE 32 CLASSES IN NV3 BECAUSE THE CLASS ID PART OF THE CONTEXT OF A GRAPHICS OBJECT IN PFIFO RAM HASH TABLE IS ONLY 5 BITS LONG! */ - -const char* nv3_class_names[] = -{ - "NV3 INVALID class 0x00", - "NV3 class 0x01: Beta factor", - "NV3 class 0x02: Render operation", - "NV3 class 0x03: Chroma key", - "NV3 class 0x04: Plane mask", - "NV3 class 0x05: Clipping rectangle", - "NV3 class 0x06: Pattern", - "NV3 class 0x07: Rectangle", - "NV3 class 0x08: Point", - "NV3 class 0x09: Line", - "NV3 class 0x0A: Lin (line without starting or ending pixel)", - "NV3 class 0x0B: Triangle", - "NV3 class 0x0C: Windows 95 GDI text acceleration", - "NV3 class 0x0D: Memory to memory format", - "NV3 class 0x0E: Scaled image from memory", - "NV3 INVALID class 0x0F", - "NV3 class 0x10: Blit", - "NV3 class 0x11: Image", - "NV3 class 0x12: Bitmap", - "NV3 INVALID class 0x13", - "NV3 class 0x14: Transfer to Memory", - "NV3 class 0x15: Stretched image from CPU", - "NV3 INVALID class 0x16", - "NV3 class 0x17: Direct3D 5.0 accelerated textured triangle w/zeta buffer", - "NV3 class 0x18: Point with zeta buffer", - "NV3 INVALID class 0x19", - "NV3 INVALID class 0x1A", - "NV3 INVALID class 0x1B", - "NV3 class 0x1C: Image in Memory", - "NV3 INVALID class 0x1D", - "NV3 INVALID class 0x1E", - "NV3 INVALID class 0x1F", -}; \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c deleted file mode 100644 index 89473d829..000000000 --- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3: Methods shared across multiple classes - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 Connor Hyde - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/dma.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - switch (method_id) - { - /* mthdCreate in software(?)*/ - case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE: - //nv_log("mthdCreate obj_name=0x%08x\n", param); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - break; - // set up the current notification request/object - // and check for double notifiers. - case NV3_SET_NOTIFY: - if (nv3->pgraph.notify_pending) - { - nv_log("Executed method NV3_SET_NOTIFY with nv3->pgraph.notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n"); - nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW"); - nv3_debug_ramin_print_context_info(param, context); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - - // disable - nv3->pgraph.notify_pending = false; - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY); - /* may need to disable fifo in this state */ - return; - } - - // set a notify as pending. - nv3->pgraph.notifier = param; - nv3->pgraph.notify_pending = true; - break; - default: - nv_log("Shared Generic Methods: Invalid or Unimplemented method 0x%04x", method_id); - nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING); - return; - } -} diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c deleted file mode 100644 index 01af9100d..000000000 --- a/src/video/nv/nv3/nv3_core.c +++ /dev/null @@ -1,1567 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 bringup and device emulation. - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -/* Main device object pointer */ -nv3_t* nv3; - -/* These are a ****PLACEHOLDER**** and are copied from 3dfx VoodooBanshee/Voodoo3*/ -static video_timings_t timing_nv3_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; -static video_timings_t timing_nv3_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; -// Revision C -static video_timings_t timing_nv3t_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; -static video_timings_t timing_nv3t_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; - -// Prototypes for functions only used in this translation unit -void nv3_init_mappings_mmio(void); -void nv3_init_mappings_svga(void); -bool nv3_is_svga_redirect_address(uint32_t addr); - -uint8_t nv3_svga_read(uint16_t addr, void* priv); -void nv3_svga_write(uint16_t addr, uint8_t val, void* priv); - -// Determine if this address needs to be redirected to the SVGA subsystem. - -bool nv3_is_svga_redirect_address(uint32_t addr) -{ - return (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) // VGA - || (addr >= NV3_PRMCIO_START && addr <= NV3_PRMCIO_END) // CRTC - || (addr >= NV3_USER_DAC_START && addr <= NV3_USER_DAC_END); // Note: 6813c6-6813c9 are ignored somewhere else -} - -// All MMIO regs are 32-bit i believe internally -// so we have to do some munging to get this to read - -// Read 8-bit MMIO -uint8_t nv3_mmio_read8(uint32_t addr, void* priv) -{ - uint32_t ret = 0x00; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - addr &= 0xFFFFFF; - - // We need to specifically exclude this particular set of registers - // so we can write the 4/8bpp CLUT - if (addr >= NV3_USER_DAC_PALETTE_START && addr <= NV3_USER_DAC_PALETTE_END) - { - // Throw directly into PRAMDAC - return nv3_mmio_arbitrate_read(addr); - } - - if (nv3_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - ret = nv3_svga_read(real_address, nv3); - - nv_log_verbose_only("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - - return ret; - } - - // see if unaligned reads are a problem - ret = nv3_mmio_read32(addr, priv); - return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFF); -} - -// Read 16-bit MMIO -uint16_t nv3_mmio_read16(uint32_t addr, void* priv) -{ - uint32_t ret = 0x00; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - addr &= 0xFFFFFF; - - if (nv3_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - ret = nv3_svga_read(real_address, nv3) - | (nv3_svga_read(real_address + 1, nv3) << 8); - - nv_log_verbose_only("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - - return ret; - } - - ret = nv3_mmio_read32(addr, priv); - return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFFFF); -} - -// Read 32-bit MMIO -uint32_t nv3_mmio_read32(uint32_t addr, void* priv) -{ - uint32_t ret = 0x00; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - addr &= 0xFFFFFF; - - if (nv3_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - ret = nv3_svga_read(real_address, nv3) - | (nv3_svga_read(real_address + 1, nv3) << 8) - | (nv3_svga_read(real_address + 2, nv3) << 16) - | (nv3_svga_read(real_address + 3, nv3) << 24); - - nv_log_verbose_only("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - - return ret; - } - ret = nv3_mmio_arbitrate_read(addr); - return ret; - -} - -// Write 8-bit MMIO -void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv) -{ - addr &= 0xFFFFFF; - - // We need to specifically exclude this particular set of registers - // so we can write the 4/8bpp CLUT - if (addr >= NV3_USER_DAC_PALETTE_START && addr <= NV3_USER_DAC_PALETTE_END) - { - // Throw directly into PRAMDAC - nv3_mmio_arbitrate_write(addr, val); - return; - } - - // This is weitek vga stuff - // If we need to add more of these we can convert these to a switch statement - if (nv3_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - nv_log_verbose_only("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - - nv3_svga_write(real_address, val & 0xFF, nv3); - - return; - } - - // overwrite first 8bits of a 32 bit value - uint32_t new_val = nv3_mmio_read32(addr, NULL); - - new_val &= (~0xFF << (addr & 3) << 3); - new_val |= (val << ((addr & 3) << 3)); - - nv3_mmio_write32(addr, new_val, priv); -} - -// Write 16-bit MMIO -void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv) -{ - addr &= 0xFFFFFF; - - // This is weitek vga stuff - if (nv3_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - - nv3_svga_write(real_address, val & 0xFF, nv3); - nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); - - return; - } - - // overwrite first 16bits of a 32 bit value - uint32_t new_val = nv3_mmio_read32(addr, NULL); - - new_val &= (~0xFFFF << (addr & 3) << 3); - new_val |= (val << ((addr & 3) << 3)); - - nv3_mmio_write32(addr, new_val, priv); -} - -// Write 32-bit MMIO -void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv) -{ - addr &= 0xFFFFFF; - - // This is weitek vga stuff - if (nv3_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - - nv3_svga_write(real_address, val & 0xFF, nv3); - nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3); - nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3); - nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3); - - return; - } - - nv3_mmio_arbitrate_write(addr, val); -} - -// AGP read function -uint8_t nv3_agp_read(int32_t func, int32_t addr) -{ - uint8_t ret = 0x00; - - switch (addr) - { - case NV3_AGP_CAPABILITIES_CAP_ID: - ret = NV3_AGP_CAPABILITIES_CAP_ID_AGP; // AGP capable device - break; - case NV3_AGP_CAPABILITIES_NEXT_PTR: // Always off - ret = 0x00; - case NV3_AGP_CAPABILITIES_AGP_VERSION: - ret = (0x1 << NV3_AGP_CAPABILITIES_AGP_VERSION_MAJOR) | NV3_AGP_CAPABILITIES_AGP_VERSION_MINOR; - break; - case NV3_AGP_STATUS_RATE: - // NV3T = AGP 2X, NV3 = AGP 1X - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) - ret = NV3_AGP_STATUS_RATE_1X_SUPPORTED | NV3_AGP_STATUS_RATE_2X_SUPPORTED; - else - ret = NV3_AGP_STATUS_RATE_1X_SUPPORTED; - break; - case NV3_AGP_STATUS_BYTE1: - ret = 0x00; // SBA not supported - break; - case NV3_AGP_STATUS_MAX_REQUESTS: - ret = NV3_AGP_STATUS_MAX_REQUESTS_AMOUNT; - break; - // This is also used for SBA but SBA is always off so we can use a bool - case NV3_AGP_COMMAND_BYTE1: - ret = nv3->nvbase.agp_enabled; - break; - default: - ret = nv3->nvbase.pci_config.pci_regs[addr]; - break; - } - - return ret; -} - -// PCI stuff -// BAR0 Pointer to MMIO space -// BAR1 Pointer to Linear Framebuffer (NV_USER) - -uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv) -{ - uint8_t ret = 0x00; - - // sanity check - if (!nv3) - return ret; - - // figure out what size this gets read as first - // seems func does not matter at least here? - switch (addr) - { - // Get the pci vendor id.. - - case NV3_PCI_CFG_VENDOR_ID: - ret = (PCI_VENDOR_SGS_NV & 0xFF); - break; - - case NV3_PCI_CFG_VENDOR_ID + 1: // all access 8bit - ret = (PCI_VENDOR_SGS_NV >> 8); - break; - - // device id - - case NV3_PCI_CFG_DEVICE_ID: - ret = (NV_PCI_DEVICE_NV3 & 0xFF); - break; - - case NV3_PCI_CFG_DEVICE_ID + 1: - ret = (NV_PCI_DEVICE_NV3 >> 8); - break; - - // various capabilities enabled by default - // IO space enabled - // Memory space enabled - // Bus master enabled - // Write/inval enabled - // Pal snoop enabled - // Capabiliies list enabled - // 66Mhz FSB capable - - case PCI_REG_COMMAND_L: - ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L]; - break; - - case PCI_REG_COMMAND_H: - ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] & NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back - break; - - // pci status register - case PCI_REG_STATUS_L: - if (nv3->pextdev.straps - & NV3_PSTRAPS_BUS_SPEED_66MHZ) - ret = (nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE); - else - ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L]; - - break; - - case PCI_REG_STATUS_H: - ret = (nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); - break; - - case NV3_PCI_CFG_REVISION: - ret = nv3->nvbase.gpu_revision; // Commercial release - break; - - case PCI_REG_PROG_IF: - ret = 0x00; - break; - - case NV3_PCI_CFG_SUBCLASS_CODE: - ret = 0x00; // nothing - break; - - case NV3_PCI_CFG_CLASS_CODE: - ret = NV3_PCI_CFG_CLASS_CODE_VGA; // CLASS_CODE_VGA - break; - - case NV3_PCI_CFG_CACHE_LINE_SIZE: - ret = NV3_PCI_CFG_CACHE_LINE_SIZE_DEFAULT_FROM_VBIOS; - break; - - case NV3_PCI_CFG_LATENCY_TIMER: - case NV3_PCI_CFG_HEADER_TYPE: - case NV3_PCI_CFG_BIST: - ret = 0x00; - break; - - // BARs are marked as prefetchable per the datasheet - case NV3_PCI_CFG_BAR0_L: - case NV3_PCI_CFG_BAR1_L: - // only bit that matters is bit 3 (prefetch bit) - ret = (NV3_PCI_CFG_BAR_PREFETCHABLE_ENABLED << NV3_PCI_CFG_BAR_PREFETCHABLE); - break; - - // These registers are hardwired to zero per the datasheet - // Writes have no effect, we can just handle it here though - case NV3_PCI_CFG_BAR0_BYTE1 ... NV3_PCI_CFG_BAR0_BYTE2: - case NV3_PCI_CFG_BAR1_BYTE1 ... NV3_PCI_CFG_BAR1_BYTE2: - ret = 0x00; - break; - - // MMIO base address - case NV3_PCI_CFG_BAR0_BASE_ADDRESS: - ret = nv3->nvbase.bar0_mmio_base >> 24;//8bit value - break; - - case NV3_PCI_CFG_BAR1_BASE_ADDRESS: - ret = nv3->nvbase.bar1_lfb_base >> 24; //8bit value - break; - - case NV3_PCI_CFG_ENABLE_VBIOS: - ret = nv3->nvbase.pci_config.vbios_enabled; - break; - - case NV3_AGP_CAPABILITIES_POINTER: - if (nv3->nvbase.bus_generation >= nv_bus_agp_1x) - ret = NV3_AGP_CAPABILITIES_START; - else - ret = 0x00; - break; - - case NV3_PCI_CFG_INT_LINE: - ret = nv3->nvbase.pci_config.int_line; - break; - - case NV3_PCI_CFG_INT_PIN: - ret = PCI_INTA; - break; - - case NV3_PCI_CFG_MIN_GRANT: - ret = NV3_PCI_CFG_MIN_GRANT_DEFAULT; - break; - - case NV3_PCI_CFG_MAX_LATENCY: - ret = NV3_PCI_CFG_MAX_LATENCY_DEFAULT; - break; - - //bar2-5 are not used and hardwired to 0 - case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END: - ret = 0x00; - break; - - case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START: - case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END: - ret = nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)]; - break; - - case NV3_AGP_START ... NV3_AGP_END: - if (nv3->nvbase.bus_generation < nv_bus_agp_1x) - break; - - ret = nv3_agp_read(func, addr); - - break; - - - default: // by default just return pci_config.pci_regs - ret = nv3->nvbase.pci_config.pci_regs[addr]; - break; - - } - - nv_log("nv3_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr, ret); - return ret; -} - -void nv3_agp_write(int32_t func, int32_t addr, uint8_t val) -{ - nv3->nvbase.pci_config.pci_regs[addr] = val; - - switch (addr) - { - case NV3_AGP_COMMAND_BYTE1: - nv3->nvbase.agp_enabled = val; - break; - default: - break; - } -} - -void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) -{ - // sanity check - if (!nv3) - return; - - // some addresses are not writable so can't have any effect and can't be allowed to be modified using this code - // as an example, only the most significant byte of the PCI BARs can be modified - if (addr >= NV3_PCI_CFG_BAR0_L && addr <= NV3_PCI_CFG_BAR0_BYTE2 - && addr >= NV3_PCI_CFG_BAR1_L && addr <= NV3_PCI_CFG_BAR1_BYTE2) - return; - - nv_log("nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val); - - nv3->nvbase.pci_config.pci_regs[addr] = val; - - switch (addr) - { - // standard pci command stuff - case PCI_REG_COMMAND_L: - nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L] = val; - // actually update the mappings - nv3_update_mappings(); - break; - case PCI_REG_COMMAND_H: - nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] = val; - // actually update the mappings - nv3_update_mappings(); - break; - // pci status register - case PCI_REG_STATUS_L: - nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE); - break; - case PCI_REG_STATUS_H: - nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING); - break; - case NV3_PCI_CFG_BAR0_BASE_ADDRESS: - nv3->nvbase.bar0_mmio_base = val << 24; - nv3_update_mappings(); - break; - case NV3_PCI_CFG_BAR1_BASE_ADDRESS: - nv3->nvbase.bar1_lfb_base = val << 24; - nv3_update_mappings(); - break; - case NV3_PCI_CFG_ENABLE_VBIOS: - case NV3_PCI_CFG_VBIOS_BASE: - - // make sure we are actually toggling the vbios, not the rom base - if (addr == NV3_PCI_CFG_ENABLE_VBIOS) - nv3->nvbase.pci_config.vbios_enabled = (val & 0x01); - - if (nv3->nvbase.pci_config.vbios_enabled) - { - // First see if we simply wanted to change the VBIOS location - - // Enable it in case it was disabled before - mem_mapping_enable(&nv3->nvbase.vbios.mapping); - - if (addr != NV3_PCI_CFG_ENABLE_VBIOS) - { - uint32_t old_addr = nv3->nvbase.vbios.mapping.base; - // 9bit register - uint32_t new_addr = nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 | - nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16; - - // move it - mem_mapping_set_addr(&nv3->nvbase.vbios.mapping, new_addr, 0x8000); - - nv_log("...i like to move it move it (VBIOS Relocation) 0x%04x -> 0x%04x\n", old_addr, new_addr); - - } - else - { - nv_log("...VBIOS Enable\n"); - } - } - else - { - nv_log("...VBIOS Disable\n"); - mem_mapping_disable(&nv3->nvbase.vbios.mapping); - - } - break; - case NV3_PCI_CFG_INT_LINE: - nv3->nvbase.pci_config.int_line = val; - break; - //bar2-5 are not used and can't be written to - case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END: - break; - - // these are mirrored to the subsystem id and also stored in the ROMBIOS - case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START: - case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END: - nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val; - break; - - case NV3_AGP_START ... NV3_AGP_END: - if (nv3->nvbase.bus_generation < nv_bus_agp_1x) - break; - - nv3_agp_write(func, addr, val); - - break; - - default: - break; - } -} - - -// -// SVGA functions -// -void nv3_recalc_timings(svga_t* svga) -{ - // sanity check - if (!nv3) - return; - - nv3_t* nv3 = (nv3_t*)svga->priv; - uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03; - - svga->memaddr_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16; - - /* Turn off override if we are in VGA mode */ - svga->override = !(pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA); - - /* NOTE: The RIVA 128 draws in a way almost completely separate to any other 86Box GPU. - - Basically, we only blit to buffer32 when something changes and we don't even bother using a timer. We only render when there is something to actually render. - - This is because there is no linear relationship between the contents of VRAM and the contents of the display which 86box's SVGA subsystem cannot tolerate. - In fact, the position in VRAM and pitch can be changed at any time via an NV_IMAGE_IN_MEMORY object. - - Therefore, we need to completely bypass it using svga->override and draw our own rendering functions. This allows us to use a neat optimisation trick - to only ever actually draw when we need to do something. This shouldn't be a problem in games, because the drivers will read the current refresh rate from - the Windows settings, and then, just submit objects at that pace for anything that changes on the screen. - */ - - // Set the pixel mode - switch (pixel_mode) - { - case NV3_CRTC_REGISTER_PIXELMODE_8BPP: - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 1; // ????? - svga->bpp = 8; - svga->lowres = 0; - svga->map8 = svga->pallook; - break; - case NV3_CRTC_REGISTER_PIXELMODE_16BPP: - /* This is some sketchy shit that is an attempt at an educated guess - at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, - this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */ - if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01) - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2; - else - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; - - /* sometimes it really renders in 15bpp, so you need to do this */ - if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) - { - svga->bpp = 16; - svga->lowres = 0; - } - else - { - svga->bpp = 15; - svga->lowres = 0; - - } - - break; - case NV3_CRTC_REGISTER_PIXELMODE_32BPP: - svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 3; - - svga->bpp = 32; - svga->lowres = 0; - //svga->render = nv3_render_32bpp; - break; - } - - // from nv_riva128 - if (((svga->miscout >> 2) & 2) == 2) - { - // set clocks - nv3_pramdac_set_pixel_clock(); - nv3_pramdac_set_vram_clock(); - } -} - -void nv3_speed_changed(void* priv) -{ - // sanity check - if (!nv3) - return; - - nv3_recalc_timings(&nv3->nvbase.svga); -} - -// Force Redraw -// Reset etc. -void nv3_force_redraw(void* priv) -{ - // sanity check - if (!nv3) - return; - - nv3->nvbase.svga.fullchange = changeframecount; -} - -// Read from SVGA core memory -uint8_t nv3_svga_read(uint16_t addr, void* priv) -{ - - nv3_t* nv3 = (nv3_t*)priv; - - uint8_t ret = 0x00; - - // sanity check - if (!nv3) - return ret; - - // If we need to RMA from GPU MMIO, go do that - if (addr >= NV3_RMA_REGISTER_START - && addr <= NV3_RMA_REGISTER_END) - { - if (!(nv3->pbus.rma.mode & 0x01)) - return ret; - - // must be dword aligned - uint32_t real_rma_read_addr = (((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX) - 1) << 1) + (addr & 0x03); - ret = nv3_pbus_rma_read(real_rma_read_addr); - return ret; - } - - // mask off b0/d0 registers - if ((((addr & 0xFFF0) == 0x3D0 - || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) - && !(nv3->nvbase.svga.miscout & 1)) - addr ^= 0x60; - - switch (addr) - { - // Alias for "get current SVGA CRTC register ID" - case NV3_CRTC_REGISTER_INDEX: - ret = nv3->nvbase.svga.crtcreg; - break; - case NV3_CRTC_REGISTER_WTF: - ret = 0x08; // Required to not freeze in certain situations on v3.xx drivers. Even though this register doesn't actually exist lol - break; - case NV3_CRTC_REGISTER_CURRENT: - // Support the extended NVIDIA CRTC register range - switch (nv3->nvbase.svga.crtcreg) - { - case NV3_CRTC_REGISTER_RL0: - ret = nv3->nvbase.svga.displine & 0xFF; - break; - /* Is rl1?*/ - case NV3_CRTC_REGISTER_RL1: - ret = (nv3->nvbase.svga.displine >> 8) & 7; - break; - case NV3_CRTC_REGISTER_I2C: - ret = i2c_gpio_get_sda(nv3->nvbase.i2c) << 3 - | i2c_gpio_get_scl(nv3->nvbase.i2c) << 2; - - break; - default: - ret = nv3->nvbase.svga.crtc[nv3->nvbase.svga.crtcreg]; - } - break; - default: - ret = svga_in(addr, &nv3->nvbase.svga); - break; - } - - return ret; //TEMP -} - -// Write to SVGA core memory -void nv3_svga_write(uint16_t addr, uint8_t val, void* priv) -{ - // sanity check - if (!nv3) - return; - - // If we need to RMA to GPU MMIO, go do that - if (addr >= NV3_RMA_REGISTER_START - && addr <= NV3_RMA_REGISTER_END) - { - // we don't need to store these registers... - nv3->pbus.rma.rma_regs[addr & 3] = val; - - if (!(nv3->pbus.rma.mode & 0x01)) // we are halfway through sending something - return; - - uint32_t real_rma_write_addr = ((nv3->pbus.rma.mode & (NV3_CRTC_REGISTER_RMA_MODE_MAX - 1)) << 1) + (addr & 0x03); - - nv3_pbus_rma_write(real_rma_write_addr, nv3->pbus.rma.rma_regs[addr & 3]); - return; - } - - // mask off b0/d0 registers - if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) - && addr < 0x3de) - && !(nv3->nvbase.svga.miscout & 1))//miscout bit 7 controls mappping - addr ^= 0x60; - - uint8_t crtcreg = nv3->nvbase.svga.crtcreg; - uint8_t old_value = 0x00; - - // todo: - // Pixel formats (8bit vs 555 vs 565) - // VBE 3.0? - - switch (addr) - { - case NV3_CRTC_REGISTER_INDEX: - // real mode access to GPU MMIO space... - nv3->nvbase.svga.crtcreg = val; - break; - // support the extended crtc regs and debug this out - case NV3_CRTC_REGISTER_CURRENT: - - // Implements the VGA Protect register - if ((nv3->nvbase.svga.crtcreg < NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80)) - return; - - // Ignore certain bits when VGA Protect register set and we are writing to CRTC register=07h - if ((nv3->nvbase.svga.crtcreg == NV3_CRTC_REGISTER_OVERFLOW) && (nv3->nvbase.svga.crtc[0x11] & 0x80)) - val = (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_OVERFLOW] & ~0x10) | (val & 0x10); - - // set the register value... - old_value = nv3->nvbase.svga.crtc[crtcreg]; - - nv3->nvbase.svga.crtc[crtcreg] = val; - // ...now act on it - - // Handle nvidia extended Bank0/Bank1 IDs - switch (crtcreg) - { - case NV3_CRTC_REGISTER_READ_BANK: - nv3->nvbase.cio_read_bank = val; - if (nv3->nvbase.svga.chain4) // chain4 addressing (planar?) - nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 15; - else - nv3->nvbase.svga.read_bank = nv3->nvbase.cio_read_bank << 13; // extended bank numbers - break; - case NV3_CRTC_REGISTER_WRITE_BANK: - nv3->nvbase.cio_write_bank = val; - if (nv3->nvbase.svga.chain4) - nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 15; - else - nv3->nvbase.svga.write_bank = nv3->nvbase.cio_write_bank << 13; - break; - case NV3_CRTC_REGISTER_RMA: - nv3->pbus.rma.mode = val & NV3_CRTC_REGISTER_RMA_MODE_MAX; - break; - /* Handle some large screen stuff */ - case NV3_CRTC_REGISTER_PIXELMODE: - if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_VDT10)) - nv3->nvbase.svga.vtotal += 0x400; - if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_VRS10)) - nv3->nvbase.svga.vblankstart += 0x400; - if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_VBS10)) - nv3->nvbase.svga.vsyncstart += 0x400; - if (val & 1 << (NV3_CRTC_REGISTER_FORMAT_HBE6)) - nv3->nvbase.svga.hdisp += 0x400; - - /* Make sure dispend and vblankstart are right if we are displaying above 1024 vert */ - if (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_PIXELMODE] & 1 << (NV3_CRTC_REGISTER_FORMAT_VDE10)) - nv3->nvbase.svga.dispend += 0x400; - - break; - case NV3_CRTC_REGISTER_HEB: - if (val & 0x01) - nv3->nvbase.svga.hdisp += 0x100; - break; - case NV3_CRTC_REGISTER_I2C_GPIO: - { - uint8_t scl = !!(val & 0x20); - uint8_t sda = !!(val & 0x10); - // Set an I2C GPIO register - i2c_gpio_set(nv3->nvbase.i2c, scl, sda); - break; - } - /* [6:0] contains cursorAddr [22:16] */ - case NV3_CRTC_REGISTER_CURSOR_ADDR0: - nv3->pramdac.cursor_address |= ((val & 0x7F) << 12); //bit7 technically ignored, but nv don't care, so neither do we - break; - /* [7:2] contains cursorAddr [16:11] */ - case NV3_CRTC_REGISTER_CURSOR_ADDR1: - nv3->pramdac.cursor_address |= ((val & 0xF8) << 4); // bit0 and 1 aren't part of the address - break; - } - - /* Recalculate the timings if we actually changed them - Additionally only do it if the value actually changed*/ - if (old_value != val) - { - // Thx to Fuel who basically wrote most of the SVGA compatibility code already (although I fixed some issues), because VGA is boring - // and in the words of an ex-Rendition/3dfx/NVIDIA engineer, "VGA was basically an undocumented bundle of steaming you-know-what. - // And it was essential that any cores the PC 3D startups acquired had to work with all the undocumented modes and timing tweaks (mode X, etc.)" - if (nv3->nvbase.svga.crtcreg < 0xE - || nv3->nvbase.svga.crtcreg > 0x10) - { - nv3->nvbase.svga.fullchange = changeframecount; - nv3_recalc_timings(&nv3->nvbase.svga); - } - } - - break; - default: - svga_out(addr, val, &nv3->nvbase.svga); - break; - } - -} - -/* DFB, sets up a dumb framebuffer */ -uint8_t nv3_dfb_read8(uint32_t addr, void* priv) -{ - addr &= (nv3->nvbase.svga.vram_mask); - return nv3->nvbase.svga.vram[addr]; -} - -uint16_t nv3_dfb_read16(uint32_t addr, void* priv) -{ - addr &= (nv3->nvbase.svga.vram_mask); - return (nv3->nvbase.svga.vram[addr + 1] << 8) | nv3->nvbase.svga.vram[addr]; -} - -uint32_t nv3_dfb_read32(uint32_t addr, void* priv) -{ - addr &= (nv3->nvbase.svga.vram_mask); - return (nv3->nvbase.svga.vram[addr + 3] << 24) | (nv3->nvbase.svga.vram[addr + 2] << 16) + - (nv3->nvbase.svga.vram[addr + 1] << 8) | nv3->nvbase.svga.vram[addr]; -} - -void nv3_dfb_write8(uint32_t addr, uint8_t val, void* priv) -{ - addr &= (nv3->nvbase.svga.vram_mask); - nv3->nvbase.svga.vram[addr] = val; - nv3->nvbase.svga.changedvram[addr >> 12] = val; - nv3_render_current_bpp_dfb_8(addr); -} - -void nv3_dfb_write16(uint32_t addr, uint16_t val, void* priv) -{ - addr &= (nv3->nvbase.svga.vram_mask); - nv3->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; - nv3->nvbase.svga.vram[addr] = (val) & 0xFF; - nv3->nvbase.svga.changedvram[addr >> 12] = val; - nv3_render_current_bpp_dfb_16(addr); - -} - -void nv3_dfb_write32(uint32_t addr, uint32_t val, void* priv) -{ - addr &= (nv3->nvbase.svga.vram_mask); - nv3->nvbase.svga.vram[addr + 3] = (val >> 24) & 0xFF; - nv3->nvbase.svga.vram[addr + 2] = (val >> 16) & 0xFF; - nv3->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; - nv3->nvbase.svga.vram[addr] = (val) & 0xFF; - nv3->nvbase.svga.changedvram[addr >> 12] = val; - - nv3_render_current_bpp_dfb_32(addr); - -} - -/* Cursor shit */ -void nv3_draw_cursor(svga_t* svga, int32_t drawline) -{ - // sanity check - if (!nv3) - return; - - // if cursor disabled is set, return - if ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_CURSOR_START] >> NV3_CRTC_REGISTER_CURSOR_START_DISABLED) & 0x01) - return; - - // NT GDI drivers: Load cursor using NV_IMAGE_FROM_MEMORY ("NV3LCD") - // 9x GDI drivers: Use H/W cursor in RAMIN - - // Do we need to emulate it? - - // THIS IS CORRECT. BUT HOW DO WE FIND IT? - uint32_t ramin_cursor_position = NV3_RAMIN_OFFSET_CURSOR; - - /* let's just assume buffer 0 here...that code needs to be totally rewritten*/ - nv3_coord_16_t start_position = nv3->pramdac.cursor_start; - - /* refuse to draw if thge cursor is offscreen */ - if (start_position.x >= nv3->nvbase.svga.hdisp - || start_position.y >= nv3->nvbase.svga.dispend) - { - return; - } - - nv_log("nv3_draw_cursor start=0x%04x,0x%04x", start_position.x, start_position.y); - - uint32_t final_position = nv3_render_get_vram_address_for_buffer(start_position, 0); - - uint16_t* vram_16 = (uint16_t*)nv3->nvbase.svga.vram; - uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; - - /* - We have to get a 32x32, "A"1R5G5B5-format cursor - out of video memory. The alpha bit actually means - XOR with display pixel if 0, replace if 1 - - These are expanded to RGB10 only if they are XORed. We don't do this (we don't really need to + there is no grobj specified here so special casing - would be needed) so we just xor it with the current pixel format - */ - for (int32_t y = 0; y < NV3_PRAMDAC_CURSOR_SIZE_Y; y++) - { - for (int32_t x = 0; x < NV3_PRAMDAC_CURSOR_SIZE_X; x++) - { - uint16_t current_pixel = nv3_ramin_read16(ramin_cursor_position, nv3); - - // 0000 = transparent, so skip drawing - if (current_pixel) - { - bool replace_bit = (current_pixel & 0x8000); - - // use buffer 0 BPIXEL - uint32_t bpixel_format = (nv3->pgraph.bpixel[0]) & 0x03; - - switch (bpixel_format) - { - case bpixel_fmt_8bit: - if (replace_bit) - nv3->nvbase.svga.vram[final_position] = current_pixel; - else //xor - { - // not sure what to do here. we'd have to search through the palette to find the closest possible colour. - uint8_t final = current_pixel ^ nv3->nvbase.svga.vram[final_position]; - nv3->nvbase.svga.vram[final_position] = final; - } - case bpixel_fmt_16bit: // easy case (our cursor is 15bpp format) - uint32_t index_16 = final_position >> 1; - - if (replace_bit) // just replace - vram_16[index_16] = current_pixel; - else // xor - { - current_pixel &= ~0x8000; // mask off the xor bit - uint16_t final = current_pixel ^ vram_16[index_16]; - vram_16[index_16] = final; - } - case bpixel_fmt_32bit: - uint32_t index_32 = final_position >> 2; - - if (replace_bit) // just replace - vram_32[index_32] = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here - else //xor - { - current_pixel &= ~0x8000; // mask off the xor bit - uint32_t current_pixel_32 = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here - - uint32_t final = current_pixel_32 ^ vram_32[index_32]; - vram_32[index_32] = final; - } - break; - } - } - - // increment vram position - ramin_cursor_position += 2; - - // go - switch (nv3->nvbase.svga.bpp) - { - case 8: - final_position++; - case 15 ... 16: - final_position += 2; - break; - case 32: - final_position += 4; - break; - } - - start_position.x++; - } - - - start_position.y++; - start_position.x = nv3->pramdac.cursor_start.x; - - // reset at the end of each line so we "jump" to the start x - final_position = nv3_render_get_vram_address_for_buffer(start_position, 0); - } -} - -// MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. -// Note this area is 64kb and the vbios is only 32kb. See below.. - -uint8_t nv3_prom_read(uint32_t address) -{ - // prom area is 64k, so... - // first see if we even have a rom of 64kb in size - uint32_t max_rom_size = NV3_PROM_END - NV3_PROM_START; - uint32_t real_rom_size = max_rom_size; - - // set it - if (nv3->nvbase.vbios.sz < max_rom_size) - real_rom_size = nv3->nvbase.vbios.sz; - - //get our real address - uint8_t rom_address = address & max_rom_size; - - // Does this mirror on real hardware? - if (rom_address >= real_rom_size) - { - nv_log("PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); - return 0xFF; - } - else - { - uint8_t val = nv3->nvbase.vbios.rom[rom_address]; - nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); - return val; - } -} - -void nv3_prom_write(uint32_t address, uint32_t value) -{ - uint32_t real_addr = address & 0x1FFFF; - nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", real_addr, value); -} - -// Initialise the MMIO mappings -void nv3_init_mappings_mmio(void) -{ - nv_log("Initialising MMIO mapping\n"); - - // 0x0 - 1000000: regs - // 0x1000000-2000000 - - // initialize the mmio mapping - mem_mapping_add(&nv3->nvbase.mmio_mapping, 0, 0, - nv3_mmio_read8, - nv3_mmio_read16, - nv3_mmio_read32, - nv3_mmio_write8, - nv3_mmio_write16, - nv3_mmio_write32, - NULL, MEM_MAPPING_EXTERNAL, nv3); - - // initialize the mmio mapping - mem_mapping_add(&nv3->nvbase.ramin_mapping, 0, 0, - nv3_ramin_read8, - nv3_ramin_read16, - nv3_ramin_read32, - nv3_ramin_write8, - nv3_ramin_write16, - nv3_ramin_write32, - NULL, MEM_MAPPING_EXTERNAL, nv3); - - mem_mapping_add(&nv3->nvbase.ramin_mapping_mirror, 0, 0, - nv3_ramin_read8, - nv3_ramin_read16, - nv3_ramin_read32, - nv3_ramin_write8, - nv3_ramin_write16, - nv3_ramin_write32, - NULL, MEM_MAPPING_EXTERNAL, nv3); - -} - -void nv3_init_mappings_svga(void) -{ - nv_log("Initialising SVGA core memory mapping\n"); - // setup the svga mappings - mem_mapping_add(&nv3->nvbase.framebuffer_mapping, 0, 0, - nv3_dfb_read8, - nv3_dfb_read16, - nv3_dfb_read32, - nv3_dfb_write8, - nv3_dfb_write16, - nv3_dfb_write32, - nv3->nvbase.svga.vram, 0, &nv3->nvbase.svga); - - // the SVGA/LFB mapping is also mirrored - mem_mapping_add(&nv3->nvbase.framebuffer_mapping_mirror, 0, 0, - nv3_dfb_read8, - nv3_dfb_read16, - nv3_dfb_read32, - nv3_dfb_write8, - nv3_dfb_write16, - nv3_dfb_write32, - nv3->nvbase.svga.vram, 0, &nv3->nvbase.svga); - - io_sethandler(0x03c0, 0x0020, - nv3_svga_read, NULL, NULL, - nv3_svga_write, NULL, NULL, - nv3); -} - -void nv3_init_mappings(void) -{ - nv3_init_mappings_mmio(); - nv3_init_mappings_svga(); -} - -// Updates the mappings after initialisation. -void nv3_update_mappings(void) -{ - // sanity check - if (!nv3) - return; - - // setting this to 0 doesn't seem to disable it, based on the datasheet - - nv_log("\nMemory Mapping Config Change:\n"); - - (nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); - - io_removehandler(0x03c0, 0x0020, - nv3_svga_read, NULL, NULL, - nv3_svga_write, NULL, NULL, - nv3); - - if (nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) - io_sethandler(0x03c0, 0x0020, - nv3_svga_read, NULL, NULL, - nv3_svga_write, NULL, NULL, - nv3); - - if (!(nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) - { - nv_log("The memory was turned off, not much is going to happen.\n"); - return; - } - - // turn off bar0 and bar1 by defualt - mem_mapping_disable(&nv3->nvbase.mmio_mapping); - mem_mapping_disable(&nv3->nvbase.framebuffer_mapping); - mem_mapping_disable(&nv3->nvbase.framebuffer_mapping_mirror); - mem_mapping_disable(&nv3->nvbase.ramin_mapping); - mem_mapping_disable(&nv3->nvbase.ramin_mapping_mirror); - - // Setup BAR0 (MMIO) - - nv_log("BAR0 (MMIO Base) = 0x%08x\n", nv3->nvbase.bar0_mmio_base); - - - if (nv3->nvbase.bar0_mmio_base) - mem_mapping_set_addr(&nv3->nvbase.mmio_mapping, nv3->nvbase.bar0_mmio_base, NV3_MMIO_SIZE); - - // if this breaks anything, remove it - nv_log("BAR1 (Linear Framebuffer / NV_USER Base & RAMIN) = 0x%08x\n", nv3->nvbase.bar1_lfb_base); - - // this is likely mirrored - // 4x on 2mb cards - // 2x on 4mb cards - // and not at all on 8mb - - /* TODO: 2MB */ - - // 4MB VRAM memory map: - // LFB_BASE+VRAM_SIZE=RAMIN Mirror(?) 0x1400000 (VERIFY PCBOX) - // LFB_BASE+VRAM_SIZE*2=LFB Mirror(?) 0x1800000 - // LFB_BASE+VRAM_SIZE*3=Definitely RAMIN (then it ends, the total ram space is 16mb) 0x1C00000 - - // 8MB VRAM memory map: - // LFB_BASE->LFB_BASE+VRAM_SIZE=LFB - // What is in 800000-c00000? - // LFB_BASE+0xC00000 = RAMIN - - if (nv3->nvbase.bar1_lfb_base) - { - if (nv3->nvbase.vram_amount == NV3_VRAM_SIZE_4MB) - { - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_VRAM_SIZE_4MB); - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_MIRROR_START, NV3_LFB_MAPPING_SIZE); - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_MIRROR_START, NV3_VRAM_SIZE_4MB); - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_START, NV3_LFB_MAPPING_SIZE); - } - else if (nv3->nvbase.vram_amount == NV3_VRAM_SIZE_8MB) - { - // we don't need this one in the case of 8mb, because regular mapping is 8mb - mem_mapping_disable(&nv3->nvbase.ramin_mapping_mirror); - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping, nv3->nvbase.bar1_lfb_base, NV3_VRAM_SIZE_8MB); - mem_mapping_set_addr(&nv3->nvbase.framebuffer_mapping_mirror, nv3->nvbase.bar1_lfb_base + NV3_LFB_MIRROR_START, NV3_LFB_MAPPING_SIZE); - mem_mapping_set_addr(&nv3->nvbase.ramin_mapping, nv3->nvbase.bar1_lfb_base + NV3_LFB_RAMIN_START, NV3_LFB_MAPPING_SIZE); - } - else - { - fatal("NV3 2MB not implemented yet"); - } - } - - // Did we change the banked SVGA mode? - switch (nv3->nvbase.svga.gdcreg[0x06] & 0x0c) - { - case NV3_CRTC_BANKED_128K_A0000: - nv_log("SVGA Banked Mode = 128K @ A0000h\n"); - mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000 - nv3->nvbase.svga.banked_mask = 0x1FFFF; - break; - case NV3_CRTC_BANKED_64K_A0000: - nv_log("SVGA Banked Mode = 64K @ A0000h\n"); - mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000 - nv3->nvbase.svga.banked_mask = 0xFFFF; - break; - case NV3_CRTC_BANKED_32K_B0000: - nv_log("SVGA Banked Mode = 32K @ B0000h\n"); - mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000 - nv3->nvbase.svga.banked_mask = 0x7FFF; - break; - case NV3_CRTC_BANKED_32K_B8000: - nv_log("SVGA Banked Mode = 32K @ B8000h\n"); - mem_mapping_set_addr(&nv3->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000 - nv3->nvbase.svga.banked_mask = 0x7FFF; - break; - } -} - -// -// Init code -// -void* nv3_init(const device_t *info) -{ - // set the vram amount and gpu revision - - /* We don't bother looking these up if they are nonzero. On Riva 128 ZX, they are already set by the init function (always 8 MB VRAM + Revision C0) */ - if (!nv3->nvbase.vram_amount) - nv3->nvbase.vram_amount = device_get_config_int("vram_size"); - - if (!nv3->nvbase.gpu_revision) - nv3->nvbase.gpu_revision = device_get_config_int("chip_revision"); - - /* Set log device name based on card model */ - const char* log_device_name = (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) ? "NV3T" : "NV3"; - - if (device_get_config_int("nv_debug_fulllog")) - nv3->nvbase.log = log_open(log_device_name); - else - nv3->nvbase.log = log_open_cyclic(log_device_name); - -#ifdef ENABLE_NV_LOG - // Allows nv_log to be used for multiple nvidia devices - nv_log_set_device(nv3->nvbase.log); -#endif - nv_log("Initialising core\n"); - - // this will only be logged if ENABLE_NV_LOG_ULTRA is defined - nv_log_verbose_only("ULTRA LOGGING enabled"); - - // Figure out which vbios the user selected - // This depends on the bus we are using and if the gpu is rev a/b or rev c - const char* vbios_id = device_get_config_bios("vbios"); - const char* vbios_file = ""; - - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) - { - if (nv3->nvbase.bus_generation == nv_bus_pci) - vbios_file = device_get_bios_file(&nv3t_device_pci, vbios_id, 0); - else - vbios_file = device_get_bios_file(&nv3t_device_agp, vbios_id, 0); - } - else - { - if (nv3->nvbase.bus_generation == nv_bus_pci) - vbios_file = device_get_bios_file(&nv3_device_pci, vbios_id, 0); - else - vbios_file = device_get_bios_file(&nv3_device_agp, vbios_id, 0); - } - - - int32_t err = rom_init(&nv3->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); - - if (err) - { - nv_log("NV3 FATAL: failed to load VBIOS err=%d\n", err); - fatal("Nvidia NV3 init failed: Somehow selected a nonexistent VBIOS? err=%d\n", err); - return NULL; - } - else - nv_log("Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file); - - // set up the bus and start setting up SVGA core - if (nv3->nvbase.bus_generation == nv_bus_pci) - { - nv_log("Using PCI bus\n"); - - pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - - /* Initialise the right revision of the card */ - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) - { - svga_init(&nv3t_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); - - video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_pci); - } - else - { - svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); - - video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_pci); - } - - } - else if (nv3->nvbase.bus_generation == nv_bus_agp_1x - || nv3->nvbase.bus_generation == nv_bus_agp_2x) - { - nv_log("Using AGP 1X/2X bus\n"); - - pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot); - - /* Initialise the right revision of the card */ - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) - { - svga_init(&nv3t_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); - - video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_agp); - } - else - { - svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount, - nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL); - - video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_agp); - } - } - - // set vram - nv_log("VRAM=%d bytes\n", nv3->nvbase.svga.vram_max); - - // init memory mappings - nv3_init_mappings(); - - // make us actually exist - nv3->nvbase.pci_config.int_line = 0xFF; // per datasheet - nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM; - - // svga is done, so now initialise the real gpu - - nv_log("Initialising GPU core...\n"); - - nv3_pextdev_init(); // Initialise Straps - nv3_pmc_init(); // Initialise Master Control - nv3_pbus_init(); // Initialise Bus (the 128 part of riva) - nv3_pfb_init(); // Initialise Framebuffer Interface - nv3_pramdac_init(); // Initialise RAMDAC (CLUT, final pixel presentation etc) - nv3_pfifo_init(); // Initialise FIFO for graphics object submission - nv3_pgraph_init(); // Initialise accelerated graphics engine - nv3_ptimer_init(); // Initialise programmable interval timer - nv3_pvideo_init(); // Initialise video overlay engine - - nv_log("Initialising I2C..."); - nv3->nvbase.i2c = i2c_gpio_init("nv3_i2c"); - nv3->nvbase.ddc = ddc_init(i2c_gpio_get_bus(nv3->nvbase.i2c)); - - return nv3; -} - -// RIVA 128 PCI initialisation function: This function simply allocates the device struct, and sets the bus to PCI before initialising. -void* nv3_init_pci(const device_t* info) -{ - nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); - nv3->nvbase.bus_generation = nv_bus_pci; - nv3_init(info); - return nv3; -} - -// RIVA 128 AGP initialisation function: This function simply allocates the device struct, and sets the bus to AGP before initialising. -void* nv3_init_agp(const device_t* info) -{ - nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); - nv3->nvbase.bus_generation = nv_bus_agp_1x; - nv3_init(info); - return nv3; -} - -// RIVA 128 ZX PCI initialisation function: This function simply allocates the device struct, and sets the bus to PCI before initialising. -// It also sets the GPU revision to C0 because NV3T config doesn't let you configure the rev (there were multiple steppings, but it's basically irrelevant), -// and sets RAM to 8 MB (the only supported config on ZX cards) -void* nv3t_init_pci(const device_t* info) -{ - nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); - nv3->nvbase.bus_generation = nv_bus_pci; - nv3->nvbase.gpu_revision = NV3_PCI_CFG_REVISION_C00; - nv3->nvbase.vram_amount = NV3_VRAM_SIZE_8MB; - nv3_init(info); - return nv3; -} - -// RIVA 128 ZX AGP initialisation function: This function simply allocates the device struct, and sets the bus to AGP before initialising. -// It also sets the GPU revision to C0 because NV3T config doesn't let you configure the rev (there were multiple steppings, but it's basically irrelevant) -// and sets RAM to 8 MB (the only supported config on ZX cards) -void* nv3t_init_agp(const device_t* info) -{ - nv3 = (nv3_t*)calloc(1, sizeof(nv3_t)); - nv3->nvbase.bus_generation = nv_bus_agp_2x; // Riva 128 ZX is AGP2X - nv3->nvbase.gpu_revision = NV3_PCI_CFG_REVISION_C00; - nv3->nvbase.vram_amount = NV3_VRAM_SIZE_8MB; - nv3_init(info); - return nv3; -} - -void nv3_close(void* priv) -{ - // Shut down logging - log_close(nv3->nvbase.log); -#ifdef ENABLE_NV_LOG - nv_log_set_device(NULL); -#endif - - // Shut down I2C and the DDC - ddc_close(nv3->nvbase.ddc); - i2c_gpio_close(nv3->nvbase.i2c); - - // Destroy the Rivatimers. (It doesn't matter if they are running.) - rivatimer_destroy(nv3->nvbase.pixel_clock_timer); - rivatimer_destroy(nv3->nvbase.memory_clock_timer); - - // Shut down SVGA - svga_close(&nv3->nvbase.svga); - free(nv3); - nv3 = NULL; -} - -// See if the bios rom is available. -int32_t nv3_available(void) -{ - return rom_present(NV3_VBIOS_ASUS_V3000_V151) - || rom_present(NV3_VBIOS_DIAMOND_V330_V162) - || rom_present(NV3_VBIOS_ERAZOR_V14700) - || rom_present(NV3_VBIOS_ERAZOR_V15403) - || rom_present(NV3_VBIOS_ERAZOR_V15500) - || rom_present(NV3_VBIOS_STB_V128_V182) - || rom_present(NV3_VBIOS_STB_V128_V182) - || rom_present(NV3T_VBIOS_ASUS_V170) - || rom_present(NV3T_VBIOS_DIAMOND_V330_V182B) - || rom_present(NV3T_VBIOS_REFERENCE_CEK_V171) - || rom_present(NV3T_VBIOS_REFERENCE_CEK_V172); -} - -// NV3 (RIVA 128) -// PCI -// 2MB or 4MB VRAM -const device_t nv3_device_pci = -{ - .name = "nVIDIA RIVA 128 (NV3) PCI", - .internal_name = "nv3_pci", - .flags = DEVICE_PCI, - .local = 0, - .init = nv3_init_pci, - .close = nv3_close, - .speed_changed = nv3_speed_changed, - .force_redraw = nv3_force_redraw, - .available = nv3_available, - .config = nv3_config, -}; - -// NV3 (RIVA 128) -// AGP -// 2MB or 4MB VRAM -const device_t nv3_device_agp = -{ - .name = "nVIDIA RIVA 128 (NV3) AGP", - .internal_name = "nv3_agp", - .flags = DEVICE_AGP, - .local = 0, - .init = nv3_init_agp, - .close = nv3_close, - .speed_changed = nv3_speed_changed, - .force_redraw = nv3_force_redraw, - .available = nv3_available, - .config = nv3_config, -}; - -// NV3T (RIVA 128 ZX) -// PCI -// 8MB VRAM -const device_t nv3t_device_pci = -{ - .name = "nVIDIA RIVA 128 ZX (NV3T) PCI", - .internal_name = "nv3t_pci", - .flags = DEVICE_PCI, - .local = 0, - .init = nv3t_init_pci, - .close = nv3_close, - .speed_changed = nv3_speed_changed, - .force_redraw = nv3_force_redraw, - .available = nv3_available, - .config = nv3t_config, -}; - -// NV3T (RIVA 128) -// AGP -// 2MB or 4MB VRAM -const device_t nv3t_device_agp = -{ - .name = "nVIDIA RIVA 128 ZX (NV3T) AGP", - .internal_name = "nv3t_agp", - .flags = DEVICE_AGP, - .local = 0, - .init = nv3t_init_agp, - .close = nv3_close, - .speed_changed = nv3_speed_changed, - .force_redraw = nv3_force_redraw, - .available = nv3_available, - .config = nv3t_config, -}; \ No newline at end of file diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c deleted file mode 100644 index 3399ca9fe..000000000 --- a/src/video/nv/nv3/nv3_core_arbiter.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * The insane NV3 MMIO arbiter. - * Writes to ALL sections of the GPU based on the write position - * All writes are internally considered to be 32-bit! Be careful... - * - * Also handles interrupt dispatch - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -// STANDARD NV3 includes -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -// Gets a register... -// move this somewhere else when we have more models -nv_register_t* nv_get_register(uint32_t address, nv_register_t* register_list, uint32_t num_regs) -{ - for (int32_t reg_num = 0; reg_num < num_regs; reg_num++) - { - if (register_list[reg_num].address == NV_REG_LIST_END) - break; //unimplemented - - if (register_list[reg_num].address == address) - return ®ister_list[reg_num]; - } - - return NULL; -} - -// Arbitrates an MMIO read -uint32_t nv3_mmio_arbitrate_read(uint32_t address) -{ - // sanity check - if (!nv3) - return 0x00; - - uint32_t ret = 0x00; - - // Ensure the addresses are dword aligned. - // I don't know why this is needed because writepriv32 is always to dword align, but it crashes if you don't do this. - if (!(address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) - address &= 0xFFFFFC; - - // gigantic set of if statements to send the write to the right subsystem - if (address >= NV3_PMC_START && address <= NV3_PMC_END) - ret = nv3_pmc_read(address); - else if (address >= NV3_CIO_START && address <= NV3_CIO_END) - ret = nv3_cio_read(address); - else if (address >= NV3_PBUS_PCI_START && address <= NV3_PBUS_PCI_END) - ret = nv3_pci_read(0x00, address & 0xFF, NULL); - else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END) - ret = nv3_pbus_read(address); - else if (address >= NV3_PFIFO_START && address <= NV3_PFIFO_END) - ret = nv3_pfifo_read(address); - else if (address >= NV3_PFB_START && address <= NV3_PFB_END) - ret = nv3_pfb_read(address); - else if (address >= NV3_PRM_START && address <= NV3_PRM_END) - ret = nv3_prm_read(address); - else if (address >= NV3_PRMIO_START && address <= NV3_PRMIO_END) - ret = nv3_prmio_read(address); - else if (address >= NV3_PTIMER_START && address <= NV3_PTIMER_END) - ret = nv3_ptimer_read(address); - else if (address >= NV3_PFB_START && address <= NV3_PFB_END) - ret = nv3_pfb_read(address); - else if (address >= NV3_PEXTDEV_START && address <= NV3_PEXTDEV_END) - ret = nv3_pextdev_read(address); - else if (address >= NV3_PROM_START && address <= NV3_PROM_END) - ret = nv3_prom_read(address); - else if (address >= NV3_PALT_START && address <= NV3_PALT_END) - ret = nv3_palt_read(address); - else if (address >= NV3_PME_START && address <= NV3_PME_END) - ret = nv3_pme_read(address); - else if (address >= NV3_PGRAPH_START && address <= NV3_PGRAPH_REAL_END) // what we're actually doing here determined by nv3_pgraph_* func - ret = nv3_pgraph_read(address); - else if (address >= NV3_PRMCIO_START && address <= NV3_PRMCIO_END) - ret = nv3_prmcio_read(address); - else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END) - ret = nv3_pvideo_read(address); - else if ((address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) - || (address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) //clut - ret = nv3_pramdac_read(address); - else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) - ret = nv3_dfb_read32(address & nv3->nvbase.svga.vram_mask, &nv3->nvbase.svga); - else if (address >= NV3_USER_START && address <= NV3_USER_END) - ret = nv3_user_read(address); - else - { - //nvplay stuff - //#ifdef ENABLE_NV_LOG_ULTRA - //warning("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); - //#else - nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address); - //#endif - - // The real hardware returns a garbage pattern - return 0x00; - } - - return ret; -} - -void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value) -{ - // sanity check - if (!nv3) - return; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - address &= 0xFFFFFF; - - - // Ensure the addresses are dword aligned. - // I don't know why this is needed because writepriv32 is always dword aligned in Nvidia's drivers, but it crashes if you don't do this. - // Exclude the 4bpp/8bpp CLUT for this purpose - if (!(address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) - address &= 0xFFFFFC; - - // gigantic set of if statements to send the write to the right subsystem - if (address >= NV3_PMC_START && address <= NV3_PMC_END) - nv3_pmc_write(address, value); - else if (address >= NV3_CIO_START && address <= NV3_CIO_END) - nv3_cio_write(address, value); - else if (address >= NV3_PBUS_PCI_START && address <= NV3_PBUS_PCI_END) // PCI mirrored at 0x1800 in MMIO - nv3_pci_write(0x00, address & 0xFF, value, NULL); // priv does not matter - else if (address >= NV3_PBUS_START && address <= NV3_PBUS_END) - nv3_pbus_write(address, value); - else if (address >= NV3_PFIFO_START && address <= NV3_PFIFO_END) - nv3_pfifo_write(address, value); - else if (address >= NV3_PRM_START && address <= NV3_PRM_END) - nv3_prm_write(address, value); - else if (address >= NV3_PRMIO_START && address <= NV3_PRMIO_END) - nv3_prmio_write(address, value); - else if (address >= NV3_PTIMER_START && address <= NV3_PTIMER_END) - nv3_ptimer_write(address, value); - else if (address >= NV3_PFB_START && address <= NV3_PFB_END) - nv3_pfb_write(address, value); - else if (address >= NV3_PEXTDEV_START && address <= NV3_PEXTDEV_END) - nv3_pextdev_write(address, value); - else if (address >= NV3_PROM_START && address <= NV3_PROM_END) - nv3_prom_write(address, value); - else if (address >= NV3_PALT_START && address <= NV3_PALT_END) - nv3_palt_write(address, value); - else if (address >= NV3_PME_START && address <= NV3_PME_END) - nv3_pme_write(address, value); - else if (address >= NV3_PGRAPH_START && address <= NV3_PGRAPH_REAL_END) // what we're actually doing here is determined by the nv3_pgraph_* functions - nv3_pgraph_write(address, value); - else if (address >= NV3_PRMCIO_START && address <= NV3_PRMCIO_END) - nv3_prmcio_write(address, value); - else if (address >= NV3_PVIDEO_START && address <= NV3_PVIDEO_END) - nv3_pvideo_write(address, value); - else if ((address >= NV3_PRAMDAC_START && address <= NV3_PRAMDAC_END) - || (address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END)) //clut - nv3_pramdac_write(address, value); - else if (address >= NV3_VRAM_START && address <= NV3_VRAM_END) - nv3_dfb_write32(address, value, &nv3->nvbase.svga); - else if (address >= NV3_USER_START && address <= NV3_USER_END) - nv3_user_write(address, value); - //RAMIN is its own thing - else - { - //nvplay stuff - //#ifdef ENABLE_NV_LOG_ULTRA - //warning("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); - //#else - nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address); - //#endif - - return; - } -} - - -// // -// ******* DUMMY FUNCTIONS FOR UNIMPLEMENTED SUBSYSTEMS ******* // -// // - -// Read and Write functions for GPU subsystems -// Remove the ones that aren't used here eventually, have all of htem for now -uint32_t nv3_cio_read(uint32_t address) { return 0; }; -void nv3_cio_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_prm_read(uint32_t address) { return 0; }; -void nv3_prm_write(uint32_t address, uint32_t value) {}; -uint32_t nv3_prmio_read(uint32_t address) { return 0; }; -void nv3_prmio_write(uint32_t address, uint32_t value) {}; - -uint32_t nv3_palt_read(uint32_t address) { return 0; }; -void nv3_palt_write(uint32_t address, uint32_t value) {}; - -// TODO: PGRAPH class registers -uint32_t nv3_prmcio_read(uint32_t address) { return 0; }; -void nv3_prmcio_write(uint32_t address, uint32_t value) {}; diff --git a/src/video/nv/nv3/nv3_core_config.c b/src/video/nv/nv3/nv3_core_config.c deleted file mode 100644 index b039ff82b..000000000 --- a/src/video/nv/nv3/nv3_core_config.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Provides NV3 configuration - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -const device_config_t nv3_config[] = -{ - // VBIOS type configuration - { - .name = "vbios", - .description = "Model", - .type = CONFIG_BIOS, - .default_string = "NV3_VBIOS_ERAZOR_V15403", - .default_int = 0, - .bios = - { - - { - .name = "ELSA VICTORY Erazor - Version 1.47.00", .files_no = 1, - .internal_name = "NV3_VBIOS_ERAZOR_V14700", - .files = {NV3_VBIOS_ERAZOR_V14700, ""} - }, - { - .name = "ELSA VICTORY Erazor - Version 1.54.03", .files_no = 1, - .internal_name = "NV3_VBIOS_ERAZOR_V15403", - .files = {NV3_VBIOS_ERAZOR_V15403, ""} - }, - { - .name = "ELSA VICTORY Erazor - Version 1.55.00", .files_no = 1, - .internal_name = "NV3_VBIOS_ERAZOR_V15500", - .files = {NV3_VBIOS_ERAZOR_V15500, ""} - }, - { - .name = "Diamond Viper V330 - Version 1.62-CO", .files_no = 1, - .internal_name = "NV3_VBIOS_DIAMOND_V330_V162", - .files = {NV3_VBIOS_DIAMOND_V330_V162, ""}, - }, - { - .name = "ASUS AGP/3DP-V3000 - Version 1.51B", .files_no = 1, - .internal_name = "NV3_VBIOS_ASUS_V3000_V151", - .files = {NV3_VBIOS_ASUS_V3000_V151, ""}, - }, - { - .name = "STB Velocity 128 - Version 1.60 [BUGGY]", .files_no = 1, - .internal_name = "NV3_VBIOS_STB_V128_V160", - .files = {NV3_VBIOS_STB_V128_V160, ""}, - }, - { - .name = "STB Velocity 128 - Version 1.82", .files_no = 1, - .internal_name = "NV3_VBIOS_STB_V128_V182", - .files = {NV3_VBIOS_STB_V128_V182, ""}, - }, - } - }, - // Memory configuration - { - .name = "vram_size", - .description = "VRAM Size", - .type = CONFIG_SELECTION, - .default_int = NV3_VRAM_SIZE_4MB, - .selection = - { - // I thought this was never released, but it seems that at least one was released: - // The card was called the "NEC G7AGK" - { - .description = "2 MB", - .value = NV3_VRAM_SIZE_2MB, - }, - - { - .description = "4 MB", - .value = NV3_VRAM_SIZE_4MB, - }, - } - - }, - { - .name = "chip_revision", - .description = "Chip Revision", - .type = CONFIG_SELECTION, - .default_int = NV3_PCI_CFG_REVISION_B00, - .selection = - { - { - .description = "RIVA 128 Prototype (Revision A; January 1997)", - .value = NV3_PCI_CFG_REVISION_A00, - }, - { - .description = "RIVA 128 (Revision B)", - .value = NV3_PCI_CFG_REVISION_B00, - }, - } - }, - // Multithreading configuration - { - - .name = "pgraph_threads", -#ifndef RELEASE_BUILD - .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", -#else - .description = "Render threads", -#endif - .type = CONFIG_SELECTION, - .default_int = 1, // todo: change later - .selection = - { - { - .description = "1 thread (Only use if issues appear with more threads)", - .value = 1, - }, - { - .description = "2 threads", - .value = 2, - }, - { - .description = "4 threads", - .value = 4, - }, - { - .description = "8 threads", - .value = 8, - }, - }, - }, -#ifndef RELEASE_BUILD - { - .name = "nv_debug_fulllog", - .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", - .type = CONFIG_BINARY, - .default_int = 0, - }, -#endif - { - .type = CONFIG_END - } -}; - -const device_config_t nv3t_config[] = -{ - // VBIOS type configuration - { - .name = "vbios", - .description = "Model", - .type = CONFIG_BIOS, - .default_string = "NV3T_VBIOS_DIAMOND_V330_V182B", - .default_int = 0, - .bios = - { - { - - .name = "Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1, - .internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B", - .files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""}, - }, - { - .name = "ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1, - .internal_name = "NV3T_VBIOS_ASUS_V170", - .files = {NV3T_VBIOS_ASUS_V170, ""}, - }, - { - .name = "NVidia Reference BIOS - V1.71B-N", .files_no = 1, - - .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171", - .files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""}, - }, - - { - .name = "NVidia Reference BIOS - V1.72B", .files_no = 1, - .internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172", - .files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""}, - }, - } - }, - // Multithreading configuration - { - - .name = "pgraph_threads", -#ifndef RELEASE_BUILD - .description = "PFIFO/PGRAPH - Number of threads to split large object method execution into", -#else - .description = "Render threads", -#endif - .type = CONFIG_SELECTION, - .default_int = 1, // todo: change later - .selection = - { - { - .description = "1 thread (Only use if issues appear with more threads)", - .value = 1, - }, - { - .description = "2 threads", - .value = 2, - }, - { - .description = "4 threads", - .value = 4, - }, - { - .description = "8 threads", - .value = 8, - }, - }, - }, -#ifndef RELEASE_BUILD - { - .name = "nv_debug_fulllog", - .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", - .type = CONFIG_BINARY, - .default_int = 0, - }, -#endif - { - .type = CONFIG_END - } -}; \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c deleted file mode 100644 index 92b657cd0..000000000 --- a/src/video/nv/nv3/render/nv3_render_blit.c +++ /dev/null @@ -1,229 +0,0 @@ -/* -* 86Box A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* This file is part of the 86Box distribution. -* -* NV3 Core rendering code (Software version) -* -* -* -* Authors: Connor Hyde, I need a better email address ;^) -* -* Copyright 2024-2025 Connor Hyde -*/ - -#include -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/plat.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -/* Check the line bounds */ -void nv3_class_011_check_line_bounds(void) -{ - uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x; - - /* In the case of class 0x11 there is no requirement to check for relative_y because we have exceeded the size of the image */ - if (relative_x >= nv3->pgraph.image.size_in.x) - { - nv3->pgraph.image_current_position.y++; - nv3->pgraph.image_current_position.x = nv3->pgraph.image.point.x; - } -} - -/* Renders an image from cpu */ -void nv3_render_blit_image(uint32_t color, nv3_grobj_t grobj) -{ - /* todo: a lot of stuff */ - - uint32_t pixel0 = 0, pixel1 = 0, pixel2 = 0, pixel3 = 0; - - /* Some extra data is sent as padding, we need to clip it off using size_out */ - - uint16_t clip_x = nv3->pgraph.image.point.x + nv3->pgraph.image.size.x; - /* we need to unpack them - IF THIS IS USED SOMEWHERE ELSE, DO SOMETHING ELSE WITH IT */ - /* the reverse order is due to the endianness */ - switch (nv3->nvbase.svga.bpp) - { - // 4 pixels packed into one color in 8bpp - case 8: - - //pixel3 - pixel3 = color & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel3, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel2 = (color >> 8) & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel2, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel1 = (color >> 16) & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel0 = (color >> 24) & 0xFF; - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - break; - // 2 pixels packed into one color in 15/16bpp - case 15: - case 16: - pixel1 = (color) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < (clip_x)) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel1, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - pixel0 = (color >> 16) & 0xFFFF; - if (nv3->pgraph.image_current_position.x < (clip_x)) nv3_render_write_pixel(nv3->pgraph.image_current_position, pixel0, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - break; - // just one pixel in 32bpp - case 32: - if (nv3->pgraph.image_current_position.x < clip_x) nv3_render_write_pixel(nv3->pgraph.image_current_position, color, grobj); - nv3->pgraph.image_current_position.x++; - nv3_class_011_check_line_bounds(); - - break; - } -} - - -#define NV3_MAX_HORIZONTAL_SIZE 1920 -#define NV3_MAX_VERTICAL_SIZE 1200 - -/* 1920 for margin. Holds a buffer of the old screen we want to hold so we don't overwrite things we already overwtote -We only need to clear it once per blit, because the blits are always the same size, and then only for the size of our new blit - -Extremely not crazy about this...Surely a better way to do it without buffering the ENTIRE SCREEN. I only update the parts that are needed, but still... - -This is LUDICROUSLY INEFFICIENT (2*O(n^2)) and COMPLETELY TERRIBLE code, but it's currently 2:48am so I can't think of a better approach... -*/ -uint32_t nv3_s2sb_line_buffer[NV3_MAX_HORIZONTAL_SIZE*NV3_MAX_VERTICAL_SIZE] = {0}; - -void nv3_render_blit_screen2screen_for_buffer(nv3_grobj_t grobj, uint32_t dst_buffer) -{ - if (nv3->pgraph.blit.size.x < NV3_MAX_HORIZONTAL_SIZE - && nv3->pgraph.blit.size.y < NV3_MAX_VERTICAL_SIZE) - memset(&nv3_s2sb_line_buffer, 0x00, (sizeof(uint32_t) * nv3->pgraph.blit.size.y) * (sizeof(uint32_t) * nv3->pgraph.blit.size.x)); - - /* First calculate our source and destination buffer */ - uint32_t src_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER) & 0x03; - - nv3_coord_16_t in_position = nv3->pgraph.blit.point_in; - nv3_coord_16_t out_position = nv3->pgraph.blit.point_out; - - /* Coordinates for copying an entire line at a time */ - uint32_t buf_position = 0, vram_position = 0, size_x = nv3->pgraph.blit.size.x; - - /* - Read the old pixel into the line buffer - Assumption: All data is sent in an unpacked format. In the case of an NVIDIA GPU this means that all data is sent 32 bits at a time regardless of if - the actual source data is 32 bits in size or not. For pixel data, the upper bits are left as 0 in 8bpp/16bpp mode. For 86box purposes, the data is written - 8/16 bits at a time. - - TODO: CHECK FOR PACKED FORMAT!!!!! - */ - - if (nv3->nvbase.svga.bpp == 15 - || nv3->nvbase.svga.bpp == 16) - size_x <<= 1; - else if (nv3->nvbase.svga.bpp == 32) - size_x <<= 2; - - for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) - { - buf_position = (nv3->pgraph.blit.size.x * y); - /* shouldn't matter in non-wtf mode */ - vram_position = nv3_render_get_vram_address_for_buffer(in_position, src_buffer); - - memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x); - in_position.y++; - /* 32bit buffer */ - } - - /* simply write it all back to vram */ - for (int32_t y = 0; y < nv3->pgraph.blit.size.y; y++) - { - buf_position = (nv3->pgraph.blit.size.x * y); - vram_position = nv3_render_get_vram_address_for_buffer(out_position, dst_buffer); - - memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x); - out_position.y++; - } - - /* - //32bit only as a test - uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; - - if (nv3->pgraph.boffset[src_buffer] != nv3->pgraph.boffset[dst_buffer]) - { - // stretch out the position to the new one - - nv3_coord_16_t current_pos_in; - nv3_coord_16_t current_pos_out; - - current_pos_in.x = nv3->pgraph.blit.point_in.x; - current_pos_in.y = nv3->pgraph.blit.point_in.y; - current_pos_out.x = nv3->pgraph.blit.point_out.x; - current_pos_out.y = nv3->pgraph.blit.point_out.y; - - for (uint32_t y = 0; y < nv3->pgraph.blit.size.y; y++) - { - current_pos_in.y = nv3->pgraph.blit.point_in.y + y; - current_pos_out.y = nv3->pgraph.blit.point_out.y + y; - - for (uint32_t x = 0; x < nv3->pgraph.blit.size.x; x++) - { - current_pos_in.x = nv3->pgraph.blit.point_in.x + x; - current_pos_out.x = nv3->pgraph.blit.point_out.x + x; - - uint32_t index = nv3_render_get_vram_address_for_buffer(current_pos_in, dst_buffer) >> 2; - uint32_t index_dst = nv3_render_get_vram_address_for_buffer(current_pos_out, src_buffer) >> 2; - - vram_32[index_dst] = vram_32[index]; - - //nv3_render_write_pixel(current_pos, vram_32[index], grobj); - } - - current_pos_in.x = nv3->pgraph.blit.point_in.x; - current_pos_out.x = nv3->pgraph.blit.point_out.x; - - } - } - */ -} - -void nv3_render_blit_screen2screen(nv3_grobj_t grobj) -{ - uint32_t dst_buffer = (nv3_pgraph_destination_buffer)grobj.grobj_0; // 5 = just use the source buffer - - if (dst_buffer & pgraph_dest_buffer0) - nv3_render_blit_screen2screen_for_buffer(grobj, 0); - if (dst_buffer & pgraph_dest_buffer1) - nv3_render_blit_screen2screen_for_buffer(grobj, 1); - if (dst_buffer & pgraph_dest_buffer2) - nv3_render_blit_screen2screen_for_buffer(grobj, 2); - if (dst_buffer & pgraph_dest_buffer3) - nv3_render_blit_screen2screen_for_buffer(grobj, 3); - - -} \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c deleted file mode 100644 index c40fa84a9..000000000 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ /dev/null @@ -1,869 +0,0 @@ -/* -* 86Box A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* This file is part of the 86Box distribution. -* -* NV3 Core rendering code (Software version) -* -* -* -* Authors: Connor Hyde, I need a better email address ;^) -* -* Copyright 2024-2025 Connor Hyde -*/ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/plat.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> -#include <86box/utils/video_stdlib.h> - -/* Functions only used in this translation unit */ -void nv3_render_8bpp(uint32_t vram_start, nv3_coord_16_t screen_size); -void nv3_render_15bpp(uint32_t vram_start, nv3_coord_16_t screen_size); -void nv3_render_16bpp(uint32_t vram_start, nv3_coord_16_t screen_size); -void nv3_render_32bpp(uint32_t vram_start, nv3_coord_16_t screen_size); - -/* Expand a colour. - NOTE: THE GPU INTERNALLY OPERATES ON RGB10!!!!!!!!!!! -*/ -nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj) -{ - // grobj0 = seems to share the format of PGRAPH_CONTEXT_SWITCH register. - - uint8_t format = (grobj.grobj_0 & 0x07); - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_ALPHA) & 0x01; - - nv3_color_expanded_t color_final; - // set the pixel format - color_final.pixel_format = format; - - nv_log_verbose_only("Expanding Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); - - - // default to fully opaque in case alpha is disabled - color_final.a = 0xFF; - - switch (format) - { - // ALL OF THESE TYPES ARE 32 BITS IN SIZE - - // 555 - case nv3_pgraph_pixel_format_r5g5b5: - // "stretch out" the colour - - color_final.a = (color >> 15) & 0x01; // will be ignored if alpha_enabled isn't used - color_final.r = ((color >> 10) & 0x1F) << 5; - color_final.g = ((color >> 5) & 0x1F) << 5; - color_final.b = (color & 0x1F) << 5; - - break; - // 888 (standard colour + 8-bit alpha) - case nv3_pgraph_pixel_format_r8g8b8: - if (alpha_enabled) - color_final.a = ((color >> 24) & 0xFF) * 4; - - color_final.r = ((color >> 16) & 0xFF) * 4; - color_final.g = ((color >> 8) & 0xFF) * 4; - color_final.b = (color & 0xFF) * 4; - - break; - case nv3_pgraph_pixel_format_r10g10b10: - color_final.a = (color >> 31) & 0x01; - color_final.r = (color >> 30) & 0x3FF; - color_final.g = (color >> 20) & 0x1FF; - color_final.b = (color >> 10); - - break; - case nv3_pgraph_pixel_format_y8: - /* Indexed mode */ - color_final.a = (color >> 8) & 0xFF; - - // yuv - color_final.r = color_final.g = color_final.b = (color & 0xFF) * 4; // convert to rgb10 - break; - case nv3_pgraph_pixel_format_y16: - color_final.a = (color >> 16) & 0xFFFF; - - // yuv - color_final.r = color_final.g = color_final.b = (color & 0xFFFF) * 4; // convert to rgb10 - break; - case nv3_pgraph_pixel_format_y420: - warning("nv3_render_expand_color: YUV420 not implemented\n"); - break; - default: - warning("nv3_render_expand_color unknown format %d", format); - break; - - } - - // i8 is a union under i16 - color_final.i16 = (color & 0xFFFF); - - return color_final; -} - -/* Used for chroma test */ -uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t color) -{ - uint8_t format = (grobj.grobj_0 & 0x07); - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_ALPHA) & 0x01; - - nv_log_verbose_only("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled); - - uint32_t packed_color = 0x00; - - switch (format) - { - case nv3_pgraph_pixel_format_r5g5b5: - packed_color = (color.r >> 5) << 10 | - (color.g >> 5) << 5 | - (color.b >> 5); - - break; - case nv3_pgraph_pixel_format_r8g8b8: - packed_color = (color.a) << 24 | // is this a thing? - (color.r >> 2) << 16 | - (color.g >> 2) << 8 | - color.b; - break; - case nv3_pgraph_pixel_format_r10g10b10: - /* sometimes alpha isn't used but we should incorporate it anyway */ - if (color.a > 0x00) packed_color |= (1 << 31); - - packed_color |= (color.r << 30); - packed_color |= (color.g << 20); - packed_color |= (color.b << 10); - break; - case nv3_pgraph_pixel_format_y8: /* i think this is just indexed mode. since r=g=b we can just take the indexed from the r */ - packed_color = nv3_render_get_palette_index((color.r >> 2) & 0xFF); - break; - case nv3_pgraph_pixel_format_y16: - warning("nv3_render_downconvert_color: Y16 not implemented"); - break; - case nv3_pgraph_pixel_format_y420: - warning("nv3_render_downconvert_color: YUV420 not implemented\n"); - break; - default: - warning("nv3_render_downconvert_color unknown format %d", format); - break; - - } - - return packed_color; -} - -/* Runs the chroma key/color key test */ -bool nv3_render_chroma_test(uint32_t color, nv3_grobj_t grobj) -{ - bool chroma_enabled = ((grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_CHROMA_KEY) & 0x01); - - if (!chroma_enabled) - return true; - - bool alpha = ((nv3->pgraph.chroma_key >> 31) & 0x01); - - if (!alpha) - return true; - - /* this is dumb but i'm lazy, if it kills perf, fix it later - we need to do some format shuffling */ - nv3_grobj_t grobj_fake = {0}; - grobj_fake.grobj_0 = 0x02; /* we don't care about any other bits */ - - nv3_color_expanded_t chroma_expanded = nv3_render_expand_color(nv3->pgraph.chroma_key, grobj_fake); - - uint32_t chroma_downconverted = nv3_render_downconvert_color(grobj, chroma_expanded); - - return !(chroma_downconverted == color); -} - -/* Convert expanded colour format to chroma key format */ -uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded) -{ - // convert the alpha to 1 bit. then return packed rgb10 - return !!expanded.a | (expanded.r << 30) | (expanded.g << 20) | (expanded.b << 10); -} - -/* Get a colour for a palette index. (The colours are 24 bit RGB888 with a 0xFF alpha added for some purposes.) */ -uint32_t nv3_render_get_palette_index(uint8_t index) -{ - uint32_t red_index = index * 3; - uint32_t green_index = red_index + 1; - uint32_t blue_index = red_index + 2; - - uint8_t red_colour = nv3->pramdac.palette[red_index]; - uint8_t green_colour = nv3->pramdac.palette[green_index]; - uint8_t blue_colour = nv3->pramdac.palette[blue_index]; - - /* Alpha is always 0xFF */ - return (0xFF << 24) | ((red_colour) << 16) | ((green_colour) << 8) | blue_colour; -} - -/* Convert a rgb10 colour to a pattern colour */ -void nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool use_color1) -{ - /* select the right pattern colour, _rgb is already in RGB10 format, so we don't need to do any conversion */ - - if (!use_color1) - { - nv3->pgraph.pattern_color_0_alpha = (pattern_colour.a) & 0xFF; - nv3->pgraph.pattern_color_0_rgb.r = pattern_colour.r; - nv3->pgraph.pattern_color_0_rgb.g = pattern_colour.g; - nv3->pgraph.pattern_color_0_rgb.b = pattern_colour.b; - - } - else - { - nv3->pgraph.pattern_color_1_alpha = (pattern_colour.a) & 0xFF; - nv3->pgraph.pattern_color_1_rgb.r = pattern_colour.r; - nv3->pgraph.pattern_color_1_rgb.g = pattern_colour.g; - nv3->pgraph.pattern_color_1_rgb.b = pattern_colour.b; - } - -} - -/* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */ -uint32_t nv3_render_get_vram_address(nv3_coord_16_t position, nv3_grobj_t grobj) -{ - uint32_t vram_x = position.x; - uint32_t vram_y = position.y; - uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_SRC_BUFFER) & 0x03; - - uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; - - // we have to multiply the x position by the number of bytes per pixel - switch (framebuffer_bpp) - { - case 8: - break; - case 15: - case 16: - vram_x = position.x << 1; - break; - case 32: - vram_x = position.x << 2; - break; - } - - uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[current_buffer] * vram_y) + nv3->pgraph.boffset[current_buffer]; - - pixel_addr_vram &= nv3->nvbase.svga.vram_mask; - - return pixel_addr_vram; -} - - -/* Combine the current buffer with the pitch to get the address in the video ram for a specific position relative to a specific framebuffer */ -uint32_t nv3_render_get_vram_address_for_buffer(nv3_coord_16_t position, uint32_t buffer) -{ - uint32_t vram_x = position.x; - uint32_t vram_y = position.y; - - uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp; - - // we have to multiply the x position by the number of bytes per pixel - switch (framebuffer_bpp) - { - case 8: - break; - case 15: - case 16: - vram_x = position.x << 1; - break; - case 32: - vram_x = position.x << 2; - break; - } - - uint32_t pixel_addr_vram = vram_x + (nv3->pgraph.bpitch[buffer] * vram_y) + nv3->pgraph.boffset[buffer]; - - pixel_addr_vram &= nv3->nvbase.svga.vram_mask; - - return pixel_addr_vram; -} - -/* Convert a dumb framebuffer address to a position. No buffer setup or anything, but just start at 0,0 for address 0. */ -nv3_coord_16_t nv3_render_get_dfb_position(uint32_t vram_address) -{ - nv3_coord_16_t pos = {0}; - - uint32_t pitch = nv3->nvbase.svga.hdisp; - - if (nv3->nvbase.svga.bpp == 15 - || nv3->nvbase.svga.bpp == 16) - pitch <<= 1; - else if (nv3->nvbase.svga.bpp == 32) - pitch <<= 2; - - pos.y = (vram_address / pitch); - pos.x = (vram_address % pitch); - - /* Fixup our x position */ - if (nv3->nvbase.svga.bpp == 15 - || nv3->nvbase.svga.bpp == 16) - pos.x >>= 1; - else if (nv3->nvbase.svga.bpp == 32) - pos.x >>= 2; - - - /* there is some strange behaviour where it writes long past the end of the fb */ - if (pos.y >= nv3->nvbase.svga.monitor->target_buffer->h) pos.y = nv3->nvbase.svga.monitor->target_buffer->h - 1; - - return pos; -} - -/* Read an 8bpp pixel from the framebuffer. */ -uint8_t nv3_render_read_pixel_8(nv3_coord_16_t position, nv3_grobj_t grobj) -{ - // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj); - - return nv3->nvbase.svga.vram[vram_address]; -} - -/* Read an 16bpp pixel from the framebuffer. */ -uint16_t nv3_render_read_pixel_16(nv3_coord_16_t position, nv3_grobj_t grobj) -{ - // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj); - - uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); - vram_address >>= 1; //convert to 16bit pointer - - return vram_16[vram_address]; -} - -/* Read an 16bpp pixel from the framebuffer. */ -uint32_t nv3_render_read_pixel_32(nv3_coord_16_t position, nv3_grobj_t grobj) -{ - // hope you call it with the right bit - uint32_t vram_address = nv3_render_get_vram_address(position, grobj); - - uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); - vram_address >>= 2; //convert to 32bit pointer - - return vram_32[vram_address]; -} - -void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj, uint32_t buffer) -{ - bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_ALPHA) & 0x01; - - int32_t clip_end_x = nv3->pgraph.clip_start.x + nv3->pgraph.clip_size.x; - int32_t clip_end_y = nv3->pgraph.clip_start.y + nv3->pgraph.clip_size.y; - - /* First, check our current buffer. */ - /* Then do the clip. */ - if (position.x < nv3->pgraph.clip_start.x - || position.y < nv3->pgraph.clip_start.y - || position.x > clip_end_x - || position.y > clip_end_y) - { - // DO NOT DRAW THE PIXEL - return; - } - - /* TODO: Plane Mask...*/ - if (!nv3_render_chroma_test(color, grobj)) - return; - - uint32_t pixel_addr_vram = nv3_render_get_vram_address_for_buffer(position, buffer); - - uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0; - uint8_t bit = 0x00; - - /* Get our pattern data, may move to another function */ - switch (nv3->pgraph.pattern.shape) - { - - /* This logic is from NV1 envytoos docs, but seems to be same on NV3*/ - case NV3_PATTERN_SHAPE_8X8: - bit = (position.x & 7) | (position.y & 7) << 3; - break; - case NV3_PATTERN_SHAPE_1X64: - bit = (position.x & 0x3f); - break; - case NV3_PATTERN_SHAPE_64X1: - bit = (position.y & 0x3f); - break; - } - - // pull out the actual bit and see which colour we need to use - - bool use_color1 = (nv3->pgraph.pattern_bitmap >> bit) & 0x01; - - if (!use_color1) - { - if (!nv3->pgraph.pattern_color_0_alpha) - return; - - /* This is stupid */ - rop_pattern = nv3_render_downconvert_color(grobj, nv3->pgraph.pattern_color_0_rgb); - } - else - { - if (!nv3->pgraph.pattern_color_1_alpha) - return; - - rop_pattern = nv3_render_downconvert_color(grobj, nv3->pgraph.pattern_color_1_rgb); - } - - - /* Go to vram and do the final ROP for a basic bitblit. - It seems we can skip the downconversion step *for now*, since (framebuffer bits per pixel) == (object bits per pixel) - I'm not sure how games will react. But it depends on how the D3D drivers operate, we may need ro convert texture formats to the current bpp internally. - - We use the pixel format of the destination buffer to achieve this (thanks frostbite2000) - */ - - // translate the patch config to GDI rop - uint32_t final_rop = nv3_render_translate_nvrop(grobj, nv3->pgraph.rop); - - uint32_t destination_format = (nv3->pgraph.bpixel[buffer]) & 0x03; - - switch (destination_format) - { - case bpixel_fmt_8bit: - rop_src = color & 0xFF; - rop_dst = nv3->nvbase.svga.vram[pixel_addr_vram]; - nv3->nvbase.svga.vram[pixel_addr_vram] = video_rop_gdi_ternary(final_rop, rop_src, rop_dst, rop_pattern) & 0xFF; - - nv3->nvbase.svga.changedvram[pixel_addr_vram >> 12] = changeframecount; - - break; - case bpixel_fmt_16bit: - { - uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram); - pixel_addr_vram >>= 1; - - // mask to 16bit - - rop_src = color & 0xFFFF; - - /* if alpha is turned on and we aren't in 565 mode, reject transparent pixels */ - bool is_16bpp = (nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01; - - // a1r5g5b5 - if (!is_16bpp) - { - if (alpha_enabled && - !(color & 0x8000)) - return; - } - - // convert to 15bpp or 16bpp based on if we are in 16bpp mode - - rop_dst = vram_16[pixel_addr_vram]; - - vram_16[pixel_addr_vram] = video_rop_gdi_ternary(final_rop, rop_src, rop_dst, rop_pattern) & 0xFFFF; - - nv3->nvbase.svga.changedvram[pixel_addr_vram >> 11] = changeframecount; - - break; - } - case bpixel_fmt_32bit: - { - uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram); - pixel_addr_vram >>= 2; - - rop_src = color; - rop_dst = vram_32[pixel_addr_vram]; - vram_32[pixel_addr_vram] = video_rop_gdi_ternary(final_rop, rop_src, rop_dst, rop_pattern); - - nv3->nvbase.svga.changedvram[pixel_addr_vram >> 10] = changeframecount; - - break; - } - } -} - -/* Plots a pixel. */ -void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t grobj) -{ - // PFB_0 is always set to hardcoded "NO_TILING" value of 0x1114. - // It seems, you are meant to use the CRTC - - nv3_pgraph_destination_buffer dst_buffer = (nv3_pgraph_destination_buffer)grobj.grobj_0; - - if (dst_buffer & (pgraph_dest_buffer0)) - nv3_render_write_pixel_to_buffer(position, color, grobj, 0); - if (dst_buffer & (pgraph_dest_buffer1)) - nv3_render_write_pixel_to_buffer(position, color, grobj, 1); - if (dst_buffer & (pgraph_dest_buffer2)) - nv3_render_write_pixel_to_buffer(position, color, grobj, 2); - if (dst_buffer & (pgraph_dest_buffer3)) - nv3_render_write_pixel_to_buffer(position, color, grobj, 3); -} - -/* Ensure the correct monitor size */ -void nv3_render_ensure_screen_size(void) -{ - /* First check if hdisp == xsize and dispend == ysize. */ - bool changed = false; - - if (nv3->nvbase.svga.hdisp != nv3->nvbase.svga.monitor->mon_xsize) - { - changed = true; - nv3->nvbase.svga.monitor->mon_xsize = nv3->nvbase.svga.hdisp; - } - - if (nv3->nvbase.svga.dispend != nv3->nvbase.svga.monitor->mon_ysize) - { - changed = true; - nv3->nvbase.svga.monitor->mon_ysize = nv3->nvbase.svga.dispend; - } - - /* - if either changed: - -> set resolution - -> set refresh rate - this is just a rough estimation right now. we need it as we only blit what changes - */ - if (changed) - { - nv3->nvbase.refresh_time = 1 / (nv3->nvbase.pixel_clock_frequency / (double)ysize / (double)xsize); // rivatimers count in microseconds - set_screen_size(xsize, ysize); - } - -} - - -/* Blit to the monitor from DFB, 8bpp */ -void nv3_render_current_bpp_dfb_8(uint32_t address) -{ - /* Broken as fuck early vbios does this. Wtf? */ - if (!nv3->nvbase.svga.hdisp) - return; - - nv3_coord_16_t size = {0}; - size.x = size.y = 1; - - nv3_coord_16_t pos = nv3_render_get_dfb_position(address); - - uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); - - *p = nv3_render_get_palette_index(data & 0xFF); -} - -/* Blit to the monitor from DFB, 15/16bpp */ -void nv3_render_current_bpp_dfb_16(uint32_t address) -{ - /* Broken as fuck early vbios does this. Wtf? */ - if (!nv3->nvbase.svga.hdisp) - return; - - nv3_coord_16_t size = {0}; - size.x = size.y = 1; - - nv3_coord_16_t pos = nv3_render_get_dfb_position(address); - - uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); - - if ((nv3->pramdac.general_control >> NV3_PRAMDAC_GENERAL_CONTROL_565_MODE) & 0x01) - /* should just "tip over" to the next line */ - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 16); - else - /* should just "tip over" to the next line */ - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); - - /*does 8bpp packed into 16 occur/ i would be surprised*/ -} - -/* Blit to the monitor from DFB, 32bpp */ -void nv3_render_current_bpp_dfb_32(uint32_t address) -{ - /* Broken as fuck early vbios does this. Wtf? */ - if (!nv3->nvbase.svga.hdisp) - return; - - nv3_coord_16_t size = {0}; - size.x = size.y = 1; - - nv3_coord_16_t pos = nv3_render_get_dfb_position(address); - - uint32_t data = *(uint32_t*)&(nv3->nvbase.svga.vram[address]); - - uint32_t* p = &nv3->nvbase.svga.monitor->target_buffer->line[pos.y][pos.x]; - - if (nv3->nvbase.svga.bpp == 32) - { - *p = data; - } - /* Packed format */ - else if (nv3->nvbase.svga.bpp == 15 - || nv3->nvbase.svga.bpp == 16) - { - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, nv3->nvbase.svga.bpp); - *p++; - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, (data >> 16) & 0xFFFF, nv3->nvbase.svga.bpp); - } -} - - -/* Blit to the monitor from GPU, current bpp */ -void nv3_render_current_bpp() -{ - /* Figure out the Display Buffer Address from the CRTC */ - - uint32_t dba = ((nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16) - + (nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_HIGH] << 8) - + nv3->nvbase.svga.crtc[NV3_CRTC_REGISTER_STARTADDR_LOW]; - - if (nv3->nvbase.debug_dba_enabled - && nv3->nvbase.debug_dba > 0) - dba = nv3->nvbase.debug_dba; - - nv3_coord_16_t screen_size = {0}; - screen_size.x = nv3->nvbase.svga.hdisp; - screen_size.y = nv3->nvbase.svga.dispend; - - /* Ensure that we are - in the correct mode. Modified SVGA core code */ - nv3_render_ensure_screen_size(); - - /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM, so it can be used for s2sb's etc */ - - switch (nv3->nvbase.svga.bpp) - { - case 4: - /* Uh we should never be here because we're in the SVGA mode(?) */ - fatal("NV3 - 4bpp not implemented (not even sure if it's SVGA only)"); - break; - case 8: - nv3_render_8bpp(dba, screen_size); - break; - case 15: - nv3_render_15bpp(dba, screen_size); - break; - case 16: - nv3_render_16bpp(dba, screen_size); - break; - case 32: - nv3_render_32bpp(dba, screen_size); - break; - } - -} - -/* - Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, indexed 8 bits per pixel format -*/ - -void nv3_render_8bpp(uint32_t vram_start, nv3_coord_16_t screen_size) -{ - if (!nv3) - return; - - uint32_t vram_current_position = vram_start; - uint32_t* p; - uint32_t data = 0; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - - for (uint32_t y = 0; y < screen_size.y; y++) - { - for (uint32_t x = 0; x < screen_size.x; x++) - { - if (vram_current_position >= nv3->nvbase.vram_amount) - return; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; - - /* should just "tip over" to the next line */ - *p = nv3_render_get_palette_index(data & 0xFF); - - vram_current_position++; - } - } -} - -/* - Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 15 bits per pixel format -*/ - -void nv3_render_15bpp(uint32_t vram_start, nv3_coord_16_t screen_size) -{ - if (!nv3) - return; - - uint32_t vram_current_position = vram_start; - uint32_t* p; - uint32_t data = 0; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - - for (uint32_t y = 0; y < screen_size.y; y++) - { - for (uint32_t x = 0; x < screen_size.x; x++) - { - if (vram_current_position >= nv3->nvbase.vram_amount) - return; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; - - /* should just "tip over" to the next line */ - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); - - vram_current_position += 2; - } - - } -} - -/* - Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 16 bits per pixel format -*/ - -void nv3_render_16bpp(uint32_t vram_start, nv3_coord_16_t screen_size) -{ - if (!nv3) - return; - - uint32_t vram_current_position = vram_start; - uint32_t* p; - uint32_t data = 0; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - - for (uint32_t y = 0; y < screen_size.y; y++) - { - for (uint32_t x = 0; x < screen_size.x; x++) - { - if (vram_current_position >= nv3->nvbase.vram_amount) - return; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; - - /* should just "tip over" to the next line */ - *p = nv3->nvbase.svga.conv_16to32(&nv3->nvbase.svga, data & 0xFFFF, 15); - - vram_current_position += 2; - - } - - } -} - -/* - Blit a certain region from the (destination buffer base + (position in vram)) to the 86Box monitor, 32 bits per pixel format -*/ - -void nv3_render_32bpp(uint32_t vram_start, nv3_coord_16_t screen_size) -{ - if (!nv3) - return; - - uint32_t vram_current_position = vram_start; - uint32_t* p; - uint32_t data = 0; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[0][0]; - - for (uint32_t y = 0; y < screen_size.y; y++) - { - for (uint32_t x = 0; x < screen_size.x; x++) - { - if (vram_current_position >= nv3->nvbase.vram_amount) - return; - - p = &nv3->nvbase.svga.monitor->target_buffer->line[y][x]; - data = *(uint32_t*)&nv3->nvbase.svga.vram[vram_current_position]; - - /* should just "tip over" to the next line */ - *p = data; - - vram_current_position += 4; - } - } -} - -// Translate an "NV-ROP" into a GDI Ternary ROP -uint8_t nv3_render_translate_nvrop(nv3_grobj_t grobj, uint32_t rop) -{ - // Credit to envytools for this function: - // https://github.com/envytools/envytools/blob/f102b82381f3f11cee113d16374c87091db039d9/nvhw/pgraph.c - // How does one even go about reverse engineering this (I'm sure the behaviour is simpler when you don't have to translate this but...) Marcelina is a legend. - - uint32_t patch_config_rop = (grobj.grobj_0 >> NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG) & 0x1F; - - /* || patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_RSVD0*/ - - // TODO: Blending - if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_BYPASS) // 0x00 is used for "nothing here" it seems. - return VIDEO_ROP_SRC_COPY; - - uint8_t res = 0; - - int32_t swizzle[3]; - - if (patch_config_rop < 8) { - swizzle[0] = patch_config_rop >> 0 & 1; - swizzle[1] = patch_config_rop >> 1 & 1; - swizzle[2] = patch_config_rop >> 2 & 1; - } else if (patch_config_rop < 0x10) { - swizzle[0] = (patch_config_rop >> 0 & 1) + 1; - swizzle[1] = (patch_config_rop >> 1 & 1) + 1; - swizzle[2] = (patch_config_rop >> 2 & 1) + 1; - } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_SRC_DST) { - swizzle[0] = 0, swizzle[1] = 1, swizzle[2] = 2; - } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_PAT_DST_SRC) { - swizzle[0] = 1, swizzle[1] = 0, swizzle[2] = 2; - } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_PAT_DST) { - swizzle[0] = 0, swizzle[1] = 2, swizzle[2] = 1; - } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_SRC_DST_PAT) { - swizzle[0] = 2, swizzle[1] = 0, swizzle[2] = 1; - } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_PAT_SRC) { - swizzle[0] = 1, swizzle[1] = 2, swizzle[2] = 0; - } else if (patch_config_rop == NV3_PGRAPH_CTX_SWITCH_PATCH_CONFIG_DST_SRC_PAT) { - swizzle[0] = 2, swizzle[1] = 1, swizzle[2] = 0; - } else { - warning("NV3 ROP: Invalid patch configuration %02x!", rop); - } - if (patch_config_rop == 0) { - if (rop & 0x01) - res |= 0x11; - if (rop & 0x16) - res |= 0x44; - if (rop & 0x68) - res |= 0x22; - if (rop & 0x80) - res |= 0x88; - } else if (patch_config_rop == 0xf) { - if (rop & 0x01) - res |= 0x03; - if (rop & 0x16) - res |= 0x0c; - if (rop & 0x68) - res |= 0x30; - if (rop & 0x80) - res |= 0xc0; - } else { - int32_t i; - for (i = 0; i < 8; i++) { - int32_t s0 = i >> swizzle[0] & 1; - int32_t s1 = i >> swizzle[1] & 1; - int32_t s2 = i >> swizzle[2] & 1; - int32_t s = s2 << 2 | s1 << 1 | s0; - if (rop >> s & 1) - res |= 1 << i; - } - } - - return res; -} \ No newline at end of file diff --git a/src/video/nv/nv3/render/nv3_render_primitives.c b/src/video/nv/nv3/render/nv3_render_primitives.c deleted file mode 100644 index e2d088c3f..000000000 --- a/src/video/nv/nv3/render/nv3_render_primitives.c +++ /dev/null @@ -1,355 +0,0 @@ -/* -* 86Box A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* This file is part of the 86Box distribution. -* -* NV3 code to render basic objects. -* -* -* -* Authors: Connor Hyde, I need a better email address ;^) -* -* Copyright 2024-2025 Connor Hyde -*/ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> -#include <86box/utils/video_stdlib.h> - -void nv3_render_rect(nv3_coord_16_t position, nv3_coord_16_t size, uint32_t color, nv3_grobj_t grobj) -{ - nv3_coord_16_t current_pos = {0}; - - for (int32_t y = position.y; y < (position.y + size.y); y++) - { - current_pos.y = y; - - for (int32_t x = position.x; x < (position.x + size.x); x++) - { - current_pos.x = x; - - nv3_render_write_pixel(current_pos, color, grobj); - } - } -} - -/* Render GDI-B clipped rectangle */ -void nv3_render_rect_clipped(nv3_clip_16_t clip, uint32_t color, nv3_grobj_t grobj) -{ - nv3_coord_16_t current_pos = {0}; - - for (int32_t y = clip.top; y < clip.bottom; y++) - { - current_pos.y = y; - - for (int32_t x = clip.left; x < clip.right; x++) - { - current_pos.x = x; - - /* compare against the global clip too */ - if (current_pos.x >= nv3->pgraph.win95_gdi_text.clip_b.left - && current_pos.x <= nv3->pgraph.win95_gdi_text.clip_b.right - && current_pos.y >= nv3->pgraph.win95_gdi_text.clip_b.top - && current_pos.y <= nv3->pgraph.win95_gdi_text.clip_b.bottom) - { - nv3_render_write_pixel(current_pos, color, grobj); - } - } - } -} - -void nv3_render_gdi_transparent_bitmap_blit(bool bit, bool clip, uint32_t color, nv3_grobj_t grobj) -{ - /* If the bit is set, and cliping is enabled (Type D) tru and lcip */ - if (bit && clip) - { - /* Turn the bit off if we need to clip (Type D ) */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_d.left - || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_d.right - || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_d.top - || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_d.bottom) - { - bit = false; - } - - /* - Also clip if we are outside of the SIZE_OUT range - We only need to do this in one direction just to get rid of the crud sent by NV - */ - uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_d.x + (nv3->pgraph.win95_gdi_text.size_out_d.x); - uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_d.y + (nv3->pgraph.win95_gdi_text.size_out_d.y); - - if (nv3->pgraph.win95_gdi_text_current_position.x >= clip_x - || nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) - bit = false; - } - - /* We don't need to and it, because it seems the Riva only uses non-packed bpp formats for this class */ - if (bit) - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, color, grobj); - - /* - Check if we've reached the bottom - Because we check the bits in reverse, we go forward (bits 7,6,5 were set for a 1x3 bitmap) - */ - - uint32_t end_x = (clip) ? nv3->pgraph.win95_gdi_text.point_d.x + nv3->pgraph.win95_gdi_text.size_in_d.x : nv3->pgraph.win95_gdi_text.point_c.x + nv3->pgraph.win95_gdi_text.size_c.x; - - nv3->pgraph.win95_gdi_text_current_position.x++; - - if (nv3->pgraph.win95_gdi_text_current_position.x >= end_x) - { - nv3->pgraph.win95_gdi_text_current_position.y++; - - if (!clip) - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_c.x; - else - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_d.x; - } - -} - -/* Originally written 23 March 2025, but then, redone, properly, on 30 March 2025 */ -void nv3_render_gdi_transparent_bitmap(bool clip, uint32_t color, uint32_t bitmap_data, nv3_grobj_t grobj) -{ - /* - First, we need to figure out how many bits we have left. - If we have less than 32, don't process all of the bits. - - Bits are processed in the following order: [7-0] [15-8] [23-16] [31-24] - TODO: Store this somewhere, so it doesn't need to be recalculated. - - We store a global bit count for this purpose. - */ - - uint32_t bitmap_size = (clip) ? nv3->pgraph.win95_gdi_text.size_in_d.x * nv3->pgraph.win95_gdi_text.size_in_d.y : nv3->pgraph.win95_gdi_text.size_c.x * nv3->pgraph.win95_gdi_text.size_c.y; - uint32_t bits_remaining_in_bitmap = bitmap_size - nv3->pgraph.win95_gdi_text_bit_count; - - /* we have to interpret every bit in reverse bit order but in the right byte order */ - - bool current_bit = false; - - /* Start by rendering bits 7 through 0 */ - for (int32_t bit = 7; bit >= 0; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - - /* Now for 15 through 8 */ - for (int32_t bit = 15; bit >= 8; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - - /* Now for 23 through 16 */ - for (int32_t bit = 23; bit >= 16; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - - /* Now for 31 through 24 */ - for (int32_t bit = 31; bit >= 24; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_transparent_bitmap_blit(current_bit, clip, color, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - -} - -void nv3_render_gdi_1bpp_bitmap_blit(bool bit, uint32_t color0, uint32_t color1, nv3_grobj_t grobj) -{ - /* We can't force the bit off because this is a 1bpp bitmap */ - bool skip = false; - - /* For Type E, always clip */ - /* Turn the bit off if we need to clip (Type D ) */ - if (nv3->pgraph.win95_gdi_text_current_position.x < nv3->pgraph.win95_gdi_text.clip_e.left - || nv3->pgraph.win95_gdi_text_current_position.x > nv3->pgraph.win95_gdi_text.clip_e.right - || nv3->pgraph.win95_gdi_text_current_position.y < nv3->pgraph.win95_gdi_text.clip_e.top - || nv3->pgraph.win95_gdi_text_current_position.y > nv3->pgraph.win95_gdi_text.clip_e.bottom) - { - skip = true; - } - - /* - Also clip if we are outside of the SIZE_OUT range - We only need to do this in one direction just to get rid of the crud sent by NV - */ - uint32_t clip_x = nv3->pgraph.win95_gdi_text.point_e.x + (nv3->pgraph.win95_gdi_text.size_out_e.x); - uint32_t clip_y = nv3->pgraph.win95_gdi_text.point_e.y + (nv3->pgraph.win95_gdi_text.size_out_e.y); - - if (nv3->pgraph.win95_gdi_text_current_position.x >= clip_x - || nv3->pgraph.win95_gdi_text_current_position.y >= clip_y) - skip = true; - - /* We don't need to and it, because it seems the Riva only uses non-packed bpp formats for this class */ - if (!skip) - { - if (bit) - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, nv3->pgraph.win95_gdi_text.color1_e, grobj); - else - nv3_render_write_pixel(nv3->pgraph.win95_gdi_text_current_position, nv3->pgraph.win95_gdi_text.color0_e, grobj); - } - - - /* - Check if we've reached the bottom, if so, advance to the next horizontal lin - Because we check the bits in reverse, we go forward (bits 7,6,5 were set for a 1x3 bitmap) - */ - - uint32_t end_x = nv3->pgraph.win95_gdi_text.point_e.x + nv3->pgraph.win95_gdi_text.size_in_e.x; - - nv3->pgraph.win95_gdi_text_current_position.x++; - - if (nv3->pgraph.win95_gdi_text_current_position.x >= end_x) - { - nv3->pgraph.win95_gdi_text_current_position.y++; - nv3->pgraph.win95_gdi_text_current_position.x = nv3->pgraph.win95_gdi_text.point_e.x; - } -} - - -/* Originally written 23 March 2025, but then, redone, properly, on 30 March 2025 */ -void nv3_render_gdi_1bpp_bitmap(uint32_t color0, uint32_t color1, uint32_t bitmap_data, nv3_grobj_t grobj) -{ - /* - First, we need to figure out how many bits we have left. - If we have less than 32, don't process all of the bits. - - Bits are processed in the following order: [7-0] [15-8] [23-16] [31-24] - TODO: Store this somewhere, so it doesn't need to be recalculated. - - We store a global bit count for this purpose. - */ - - uint32_t bitmap_size = nv3->pgraph.win95_gdi_text.size_in_e.x * nv3->pgraph.win95_gdi_text.size_in_e.y; - uint32_t bits_remaining_in_bitmap = bitmap_size - nv3->pgraph.win95_gdi_text_bit_count; - - /* we have to interpret every bit in reverse bit order but in the right byte order */ - - bool current_bit = false; - - /* Start by rendering bits 7 through 0 */ - for (int32_t bit = 7; bit >= 0; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - - /* Now for 15 through 8 */ - for (int32_t bit = 15; bit >= 8; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - - /* Now for 23 through 16 */ - for (int32_t bit = 23; bit >= 16; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; - - /* Now for 31 through 24 */ - for (int32_t bit = 31; bit >= 24; bit--) - { - current_bit = (bitmap_data >> bit) & 0x01; - - nv3_render_gdi_1bpp_bitmap_blit(current_bit, color0, color1, grobj); - nv3->pgraph.win95_gdi_text_bit_count++; - bits_remaining_in_bitmap--; - - if (!bits_remaining_in_bitmap) - break; - } - - /* IF we're done, let's return */ - if (!bits_remaining_in_bitmap) - return; -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c deleted file mode 100644 index a2e340e85..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pbus.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PBUS: 128-bit unified bus - * - * - * - * Authors: Connor Hyde, I need a better email dataess ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -// NV3 PBUS RMA - Real Mode Access for VBIOS -// This basically works like a shifter, you write one byte at a time from [0x3d0...0x3d3] and it shifts it in to build a 32-bit MMIO address... -// Putting this in pbus because imo it makes the most sense (related to memory access/memory interface) - -nv_register_t pbus_registers[] = { - { NV3_PBUS_DEBUG_0, "PBUS - Debug Register", NULL, NULL}, - { NV3_PBUS_INTR, "PBUS - Interrupt Status", NULL, NULL}, - { NV3_PBUS_INTR_EN, "PBUS - Interrupt Enable", NULL, NULL,}, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -void nv3_pbus_init(void) -{ - nv_log("Initialising PBUS..."); - - nv_log("Done\n"); -} - -uint32_t nv3_pbus_read(uint32_t address) -{ - nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); - - uint32_t ret = 0x00; - - // todo: friendly logging - - nv_log_verbose_only("PBUS Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - switch (reg->address) - { - case NV3_PBUS_DEBUG_0: - ret = nv3->pbus.debug_0; - break; - case NV3_PBUS_INTR: - ret = nv3->pbus.interrupt_status; - break; - case NV3_PBUS_INTR_EN: - ret = nv3->pbus.interrupt_enable; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pbus_write(uint32_t address, uint32_t value) -{ - nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0])); - - nv_log_verbose_only("PBUS Write 0x%08x -> 0x%08x\n", value, address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - case NV3_PBUS_DEBUG_0: - nv3->pbus.debug_0 = value; - break; - // Interrupt registers - // Interrupt state: - // Bit 0 - PCI Bus Error - case NV3_PBUS_INTR: - nv3->pbus.interrupt_status &= ~value; - nv3_pmc_clear_interrupts(); - break; - case NV3_PBUS_INTR_EN: - nv3->pbus.interrupt_enable = value & 0x00000001; - break; - } - - } - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} - -uint8_t nv3_pbus_rma_read(uint16_t addr) -{ - addr &= 0xFF; - uint32_t real_final_address = 0x0; - uint8_t ret = 0x0; - - switch (addr) - { - // signature so you know reads work - case 0x00: - ret = NV3_RMA_SIGNATURE_MSB; - break; - case 0x01: - ret = NV3_RMA_SIGNATURE_BYTE2; - break; - case 0x02: - ret = NV3_RMA_SIGNATURE_BYTE1; - break; - case 0x03: - ret = NV3_RMA_SIGNATURE_LSB; - break; - case 0x08 ... 0x0B: - // reads must be dword aligned - real_final_address = (nv3->pbus.rma.addr + (addr & 0x03)); - - if (nv3->pbus.rma.addr < NV3_MMIO_SIZE) - ret = nv3_mmio_read8(real_final_address, NULL); - else - { - /* Do we need to read RAMIN here? */ - ret = nv3->nvbase.svga.vram[real_final_address - NV3_MMIO_SIZE] & (nv3->nvbase.svga.vram_max - 1); - } - - // log current location for vbios RE - nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", - addr, real_final_address, ret); - - break; - } - - return ret; -} - -// Implements a 32-bit write using 16 bit port number -void nv3_pbus_rma_write(uint16_t addr, uint8_t val) -{ - // addresses are in reality 8bit so just mask it to be safe - addr &= 0xFF; - - // format: - // 0x00 ID - // 0x04 Pointer to data - // 0x08 Data port(?) - // 0x0B Data - 32bit. SENT IN THE RIGHT ORDER FOR ONCE WAHOO! - // 0x10 Increment (?) data - implemented the same as data for now - - if (addr < 0x08) - { - switch (addr % 0x04) - { - case 0x00: // lowest byte - nv3->pbus.rma.addr &= ~0xff; - nv3->pbus.rma.addr |= val; - break; - case 0x01: // 2nd highest byte - nv3->pbus.rma.addr &= ~0xff00; - nv3->pbus.rma.addr |= (val << 8); - break; - case 0x02: // 3rd highest byte - nv3->pbus.rma.addr &= ~0xff0000; - nv3->pbus.rma.addr |= (val << 16); - break; - case 0x03: // 4th highest byte - nv3->pbus.rma.addr &= ~0xff000000; - nv3->pbus.rma.addr |= (val << 24); - break; - } - } - // Data to send to MMIO - else - { - switch (addr % 0x04) - { - case 0x00: // lowest byte - nv3->pbus.rma.data &= ~0xff; - nv3->pbus.rma.data |= val; - break; - case 0x01: // 2nd highest byte - nv3->pbus.rma.data &= ~0xff00; - nv3->pbus.rma.data |= (val << 8); - break; - case 0x02: // 3rd highest byte - nv3->pbus.rma.data &= ~0xff0000; - nv3->pbus.rma.data |= (val << 16); - break; - case 0x03: // 4th highest byte - nv3->pbus.rma.data &= ~0xff000000; - nv3->pbus.rma.data |= (val << 24); - - nv_log_verbose_only("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", - addr, nv3->pbus.rma.addr, nv3->pbus.rma.data); - - if (nv3->pbus.rma.addr < NV3_MMIO_SIZE) - nv3_mmio_write32(nv3->pbus.rma.addr, nv3->pbus.rma.data, NULL); - else // failsafe code, i don't think you will ever write outside of VRAM? - { - uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; - vram_32[(nv3->pbus.rma.addr - NV3_MMIO_SIZE) >> 2] = nv3->pbus.rma.data; - } - - - break; - } - } - - if (addr & 0x10) - nv3->pbus.rma.addr += 0x04; // Alignment -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c deleted file mode 100644 index 3359e9079..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PBUS DMA: DMA & Notifier Engine - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/dma.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -/* Nvidia DMA Engine */ - -void nv3_perform_dma_m2mf(nv3_grobj_t grobj) -{ - // notify object base=grobj_1 >> 12 - uint32_t notify_obj_base = grobj.grobj_1 >> 12; - - uint32_t notify_obj_info = nv3_ramin_read32(notify_obj_base, nv3); - uint32_t notify_obj_limit = nv3_ramin_read32(notify_obj_base + 0x04, nv3); - uint32_t notify_obj_page = nv3_ramin_read32(notify_obj_base + 0x08, nv3); - - /* extract some important information*/ - uint32_t info_adjust = notify_obj_info & 0xFFF; - bool info_pt_present = (notify_obj_info >> NV3_NOTIFICATION_PT_PRESENT) & 0x01; - uint8_t info_dma_target = (notify_obj_info >> NV3_NOTIFICATION_TARGET) & 0x03; - - /* paging information */ - bool page_is_present = notify_obj_page & 0x01; - bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); - uint32_t frame_base = notify_obj_page & 0xFFFFF000; - - // This code is temporary and will probably be moved somewhere else - // Print torns of debug info - #ifdef DEBUG - nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); - - nv_log_verbose_only("M2MF DMA Information:\n"); - nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust); - (info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n"); - - switch (info_dma_target) - { - case NV3_DMA_TARGET_NODE_VRAM: - nv_log_verbose_only("Notification Target: VRAM\n"); - break; - case NV3_DMA_TARGET_NODE_CART: - nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); - break; - case NV3_DMA_TARGET_NODE_PCI: - (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); - break; - case NV3_DMA_TARGET_NODE_AGP: - (nv3->nvbase.bus_generation == nv_bus_agp_1x - || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); - break; - } - - nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit); - (page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n"); - (page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n"); - nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base); - #endif - - // set up the dma transfer. we need to translate to a physical address. - - uint32_t final_address = 0; - - /* M2MF DMA only uses HW type */ - - final_address = frame_base + info_adjust; - - /* send the notification off */ - nv_log("About to send M2MF DMA to 0x%08x (Check target)\n", final_address); - - uint32_t offset_in = (nv3->pgraph.m2mf.offset_in); - uint32_t offset_out = (nv3->pgraph.m2mf.offset_out); - - uint32_t pitch_in = nv3->pgraph.m2mf.pitch_in; - uint32_t pitch_out = nv3->pgraph.m2mf.pitch_out; - - // pitch out surely can't be 0 - if (pitch_out == 0) - pitch_out = pitch_in; - - uint32_t bytes_per_scanline = nv3->pgraph.m2mf.scanline_length; - - uint8_t increment_in = (nv3->pgraph.m2mf.format) & 0x07; - uint8_t increment_out = (nv3->pgraph.m2mf.format >> NV3_M2MF_FORMAT_INPUT) & 0x07; - - for (uint32_t scanline = 0; scanline < nv3->pgraph.m2mf.num_scanlines; scanline++) - { - for (uint32_t pixel = offset_in; pixel < (offset_in + bytes_per_scanline); pixel += increment_in) - { - nv3->nvbase.svga.vram[offset_out] = nv3->nvbase.svga.vram[offset_in]; - offset_out += increment_out; - } - - offset_in += pitch_in; - offset_out += pitch_out; - } - - /* - switch (info_dma_target) - { - // for M2MF only NVM target node is used. - - case NV3_DMA_TARGET_NODE_VRAM: - - - uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; - - break; - case NV3_DMA_TARGET_NODE_PCI: - case NV3_DMA_TARGET_NODE_AGP: - // Idk how to implement increments of more than 1 but only 1 increments seem to be used with these. - uint32_t size_in = nv3->pgraph.m2mf.num_scanlines * nv3->pgraph.m2mf.pitch_in; - uint32_t size_out = nv3->pgraph.m2mf.num_scanlines * nv3->pgraph.m2mf.pitch_out; - - uint8_t* page_in = calloc(1, size_in); - - for (uint32_t scanline = 0; scanline < nv3->pgraph.m2mf.num_scanlines; scanline++) - { - - } - - dma_bm_read(offset_in, page_in, size_in, size_in); - dma_bm_write(offset_out, page_in, size_out, size_out); - - break; - } -*/ - // we're done - nv3->pgraph.notify_pending = false; -} - - -/* Sees if any notification is required after an object method is executed. If so, executes it... */ -void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) -{ - if (!nv3->pgraph.notify_pending) - return; - - uint32_t current_notification_object = nv3->pgraph.notifier; - uint32_t notification_type = ((current_notification_object >> NV3_PGRAPH_NOTIFY_REQUEST_TYPE) & 0x07); - - // check for a software method (0 = hardware, 1 = software) - if (notification_type != 0) - { - nv_log("Software Notification, firing interrupt"); - nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_SOFTWARE_NOTIFY); - //return; - } - - // set up the NvNotification structure - nv3_notification_t notify = {0}; - notify.nanoseconds = nv3->ptimer.time; - notify.status = NV3_NOTIFICATION_STATUS_DONE_OK; // it should be fine to just signal that it's ok - - // these are only nonzero when there is an error - notify.info32 = notify.info16 = 0; - - // notify object base=grobj_1 >> 12 - uint32_t notify_obj_base = grobj.grobj_1 >> 12; - - uint32_t notify_obj_info = nv3_ramin_read32(notify_obj_base, nv3); - uint32_t notify_obj_limit = nv3_ramin_read32(notify_obj_base + 0x04, nv3); - uint32_t notify_obj_page = nv3_ramin_read32(notify_obj_base + 0x08, nv3); - - /* extract some important information*/ - uint32_t info_adjust = notify_obj_info & 0xFFF; - bool info_pt_present = (notify_obj_info >> NV3_NOTIFICATION_PT_PRESENT) & 0x01; - uint8_t info_notification_target = (notify_obj_info >> NV3_NOTIFICATION_TARGET) & 0x03; - - /* paging information */ - bool page_is_present = notify_obj_page & 0x01; - bool page_is_readwrite = (notify_obj_page >> NV3_NOTIFICATION_PAGE_ACCESS); - uint32_t frame_base = notify_obj_page & 0xFFFFF000; - - // This code is temporary and will probably be moved somewhere else - // Print torns of debug info - #ifdef DEBUG - nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n"); - - nv_log_verbose_only("Notification Information:\n"); - nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust); - (info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n"); - - switch (info_notification_target) - { - case NV3_DMA_TARGET_NODE_VRAM: - nv_log_verbose_only("Notification Target: VRAM\n"); - break; - case NV3_DMA_TARGET_NODE_CART: - nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n"); - break; - case NV3_DMA_TARGET_NODE_PCI: - (nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n"); - break; - case NV3_DMA_TARGET_NODE_AGP: - (nv3->nvbase.bus_generation == nv_bus_agp_1x - || nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n"); - break; - } - - nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit); - (page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n"); - (page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n"); - nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base); - #endif - - // set up the dma transfer. we need to translate to a physical address. - - uint32_t final_address = 0; - - /* Simple case: hardware notification, we can just take the pte since it's based on the type */ - if (notification_type == 0) - { - final_address = frame_base + info_adjust; - } - else - { - // for software we have to calculate the pte index - uint32_t pte_num = ((notification_type << 4) + info_adjust) >> 12; - - /* ramin entries are sorted - 1 object for each pte entry...*/ - final_address = nv3_ramin_read32(notify_obj_base + (0x10 * pte_num) + 8, nv3); - final_address += (info_adjust & 0xFFF); - } - - /* send the notification off */ - nv_log("About to send hardware notification to 0x%08x (Check target)\n", final_address); - - switch (info_notification_target) - { - case NV3_DMA_TARGET_NODE_VRAM: - - uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram; - - // increment by 1 because each index increments by 4 - vram_32[final_address] = (notify.nanoseconds & 0xFFFFFFFF); - vram_32[final_address + 1] = (notify.nanoseconds >> 32); - vram_32[final_address + 2] = notify.info32; - vram_32[final_address + 3] = (notify.info16 | notify.status); - break; - case NV3_DMA_TARGET_NODE_PCI: - case NV3_DMA_TARGET_NODE_AGP: - dma_bm_write(final_address, (uint8_t*)¬ify, sizeof(nv3_notification_t), 4); - break; - } - - // we're done - nv3->pgraph.notify_pending = false; -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c deleted file mode 100644 index c89d540c3..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pextdev.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PEXTDEV - External Devices - * Including straps - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_pextdev_init(void) -{ - nv_log("Initialising PEXTDEV....\n"); - - // Set the chip straps - // Make these configurable in the future... - - // Current settings - // AGP2X Disabled - // TV Mode NTSC - // Crystal 13.5 Mhz - // Bus width 128-Bit (some gpus were sold as 64bit for cost reduction) - // - - nv_log("Initialising straps...\n"); - - nv3->pextdev.straps = - (NV3_PSTRAPS_AGP2X_DISABLED << NV3_PSTRAPS_AGP2X) | - (NV3_PSTRAPS_TVMODE_NTSC << NV3_PSTRAPS_TVMODE) | - (NV3_PSTRAPS_CRYSTAL_13500K << NV3_PSTRAPS_CRYSTAL); - - // figure out the bus - if (nv3->nvbase.bus_generation == nv_bus_pci) - nv3->pextdev.straps |= (NV3_PSTRAPS_BUS_TYPE_PCI << NV3_PSTRAPS_BUS_TYPE); - else - nv3->pextdev.straps |= (NV3_PSTRAPS_BUS_TYPE_AGP << NV3_PSTRAPS_BUS_TYPE); - - // now the lower bits - nv3->pextdev.straps |= - (NV3_PSTRAPS_BUS_WIDTH_128BIT << NV3_PSTRAPS_BUS_WIDTH) | - (NV3_PSTRAPS_BIOS_PRESENT << NV3_PSTRAPS_BIOS) | - (NV3_PSTRAPS_BUS_SPEED_66MHZ << NV3_PSTRAPS_BUS_SPEED); - - nv_log("Straps = 0x%04x\n", nv3->pextdev.straps); - nv_log("Initialising PEXTDEV: Done\n"); -} - -// -// ****** PEXTDEV register list START ****** -// - -nv_register_t pextdev_registers[] = { - { NV3_PSTRAPS, "Straps - Chip Configuration", NULL, NULL }, - { NV_REG_LIST_END, NULL, NULL, NULL }, // sentinel value -}; - - -// -// ****** Read/Write functions start ****** -// - -uint32_t nv3_pextdev_read(uint32_t address) -{ - nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); - - uint32_t ret = 0x00; - - // special consideration for straps - if (address == NV3_PSTRAPS) - { - nv_log_verbose_only("Straps Read (current value=0x%08x)\n", nv3->pextdev.straps); - } - else - { - nv_log_verbose_only("PEXTDEV Read from 0x%08x", address); - } - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - switch (reg->address) - { - case NV3_PSTRAPS: - ret = nv3->pextdev.straps; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pextdev_write(uint32_t address, uint32_t value) -{ - nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0])); - - nv_log_verbose_only("PEXTDEV Write 0x%08x -> 0x%08x\n", value, address); - - // special consideration for straps - if (address == NV3_PSTRAPS) - { - /* For some reason, all RIVA 128 ZX VBIOSes try to write to the straps. So only indicate this as a problem and return on Rev A/B */ - if (nv3->nvbase.gpu_revision != NV3_PCI_CFG_REVISION_C00) - { - warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps); - return; - } - } - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c deleted file mode 100644 index 7360a2c9a..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PFB: Framebuffer - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -// Functions only used in this translation unit -uint32_t nv3_pfb_config0_read(void); -void nv3_pfb_config0_write(uint32_t val); - -nv_register_t pfb_registers[] = { - { NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL}, - { NV3_PFB_DELAY, "PFB Delay", NULL, NULL}, - { NV3_PFB_DEBUG_0, "PFB Debug", NULL, NULL }, - { NV3_PFB_GREEN_0, "PFB Green / Power Saving", NULL, NULL,}, - { NV3_PFB_CONFIG_0, "PFB Framebuffer Config 0", nv3_pfb_config0_read, nv3_pfb_config0_write }, - { NV3_PFB_CONFIG_1, "PFB Framebuffer Config 1", NULL, NULL }, - { NV3_PFB_RTL, "PFB RTL (Part of memory timings)", NULL, NULL }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -void nv3_pfb_init(void) -{ - nv_log("Initialising PFB..."); - - // initial configuration: - // ram 4mb - // bus width 128bit - // extension ram none (was this ever used?) - // ram banks 4 (based on observation of physical RIVA 128 with 4mb, does 1 bank = 1chip?) - // twiddle off (check this on a real card once it's actually installed) - nv3->pfb.boot = (NV3_PFB_BOOT_RAM_EXTENSION_NONE << (NV3_PFB_BOOT_RAM_EXTENSION) - | (NV3_PFB_BOOT_RAM_DATA_TWIDDLE_OFF << NV3_PFB_BOOT_RAM_DATA_TWIDDLE) - | (NV3_PFB_BOOT_RAM_BANKS_4 << NV3_PFB_BOOT_RAM_BANKS) - | (NV3_PFB_BOOT_RAM_WIDTH_128 << NV3_PFB_BOOT_RAM_WIDTH) - ); - - if (nv3->nvbase.vram_amount == NV3_VRAM_SIZE_4MB) - nv3->pfb.boot |= (NV3_PFB_BOOT_RAM_AMOUNT_4MB << NV3_PFB_BOOT_RAM_AMOUNT); - else - nv3->pfb.boot |= (NV3_PFB_BOOT_RAM_AMOUNT_8MB << NV3_PFB_BOOT_RAM_AMOUNT); - - nv_log("Done\n"); -} - -uint32_t nv3_pfb_read(uint32_t address) -{ - nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); - - uint32_t ret = 0x00; - - // todo: friendly logging - - nv_log_verbose_only("PFB Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - switch (reg->address) - { - case NV3_PFB_BOOT: - ret = nv3->pfb.boot; - break; - case NV3_PFB_DEBUG_0: - ret = nv3->pfb.debug_0; - break; - // Config 0 has a read/write function - case NV3_PFB_CONFIG_1: - ret = nv3->pfb.config_1; - break; - case NV3_PFB_GREEN_0: - ret = nv3->pfb.green; - break; - case NV3_PFB_DELAY: - ret = nv3->pfb.delay; - break; - case NV3_PFB_RTL: - ret = nv3->pfb.rtl; - break; - - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pfb_write(uint32_t address, uint32_t value) -{ - nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0])); - - nv_log_verbose_only("PFB Write 0x%08x -> 0x%08x", value, address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - // Boot is read only - case NV3_PFB_DEBUG_0: - nv3->pfb.debug_0 = value; - break; - // Config 0 has a read/write function - case NV3_PFB_CONFIG_1: // Config Register 1 - nv3->pfb.config_1 = value; - break; - case NV3_PFB_GREEN_0: - nv3->pfb.green = value; - break; - case NV3_PFB_DELAY: - nv3->pfb.delay = value; - break; - case NV3_PFB_RTL: - nv3->pfb.rtl = value; - break; - } - } - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} - -uint32_t nv3_pfb_config0_read(void) -{ - return nv3->pfb.config_0; -} - -void nv3_pfb_config0_write(uint32_t val) -{ - nv3->pfb.config_0 = val; - - // i think the actual size and pixel depth are set in PRAMDAC - // so we don't update things here for now - - uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; - // i don't think 16:9 is supported - uint32_t new_pfb_vtotal = new_pfb_htotal * (3.0/4.0); - uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; - - - // This doesn't actually seem very useful - - nv_log_verbose_only("Framebuffer Config Change\n"); - nv_log_verbose_only("Horizontal Size=%d pixels\n", new_pfb_htotal); - nv_log_verbose_only("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); - - if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) - nv_log_verbose_only("Bit Depth=8bpp\n"); - else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP) - nv_log_verbose_only("Bit Depth=16bpp\n"); - else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_32BPP) - nv_log_verbose_only("Bit Depth=32bpp\n"); - -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c deleted file mode 100644 index 9ddcda0d3..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ /dev/null @@ -1,985 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PFIFO (FIFO for graphics object submission) - * PIO object submission - * Gray code conversion routines - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/dma.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -// -// ****** PFIFO register list START ****** -// - -nv_register_t pfifo_registers[] = { - { NV3_PFIFO_INTR, "PFIFO - Interrupt Status", NULL, NULL}, - { NV3_PFIFO_INTR_EN, "PFIFO - Interrupt Enable", NULL, NULL,}, - { NV3_PFIFO_DELAY_0, "PFIFO - DMA Delay/Retry Register", NULL, NULL}, - { NV3_PFIFO_DEBUG_0, "PFIFO - Debug 0", NULL, NULL, }, - { NV3_PFIFO_CONFIG_0, "PFIFO - Config 0", NULL, NULL, }, - { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, - { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, - { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, - { NV3_PFIFO_CACHE_REASSIGNMENT, "PFIFO - Allow Cache Channel Reassignment", NULL, NULL }, - { NV3_PFIFO_CACHE0_PULL0, "PFIFO - Cache0 Puller Control", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller Control"}, - { NV3_PFIFO_CACHE0_PULLER_CTX_STATE, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULL0, "PFIFO - Cache1 Puller State0", NULL, NULL}, - { NV3_PFIFO_CACHE1_PULLER_CTX_STATE, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - { NV3_PFIFO_CACHE0_PUSH_ENABLED, "PFIFO - Cache0 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE1_PUSH_ENABLED, "PFIFO - Cache1 Access", NULL, NULL, }, - { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 Push Channel ID", NULL, NULL, }, - { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 Push Channel ID", NULL, NULL, }, - { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, - { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, - { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, - { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get", NULL, NULL }, - { NV3_PFIFO_CACHE0_CTX, "PFIFO - Cache0 Context", NULL, NULL }, - { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get", NULL, NULL }, - { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put", NULL, NULL }, - { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put", NULL, NULL }, - //Cache1 exclusive stuff - { NV3_PFIFO_CACHE1_DMA_CONFIG_0, "PFIFO - Cache1 DMA Access (bit 0: is running, bit 4: is busy)"}, - { NV3_PFIFO_CACHE1_DMA_CONFIG_1, "PFIFO - Cache1 DMA Length"}, - { NV3_PFIFO_CACHE1_DMA_CONFIG_2, "PFIFO - Cache1 DMA Address"}, - { NV3_PFIFO_CACHE1_DMA_CONFIG_3, "PFIFO - Cache1 DMA Target Node"}, - { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status"}, - { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA TLB - Pagetable Base"}, - { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA TLB - Pagetable Entry (31:12 - Frame Address; bit 0 - Is Present)"}, - { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA TLB - Tag"}, - //Runout - { NV3_PFIFO_RUNOUT_GET, "PFIFO Runout Get Address [8:3 if 512b, otherwise 12:3]"}, - { NV3_PFIFO_RUNOUT_PUT, "PFIFO Runout Put Address [8:3 if 512b, otherwise 12:3]"}, - { NV3_PFIFO_RUNOUT_STATUS, "PFIFO Runout Status"}, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -// PFIFO init code -void nv3_pfifo_init(void) -{ - nv_log("Initialising PFIFO..."); - - nv_log("Done!\n"); -} - -uint32_t nv3_pfifo_read(uint32_t address) -{ - // before doing anything, check the subsystem enablement state - - if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO) - & NV3_PMC_ENABLE_PFIFO_ENABLED) - { - nv_log("Repressing PFIFO read. The subsystem is disabled according to pmc_enable, returning 0\n"); - return 0x00; - } - - uint32_t ret = 0x00; - - nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - - // todo: friendly logging - - nv_log_verbose_only("PFIFO Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - // Interrupt state: - // Bit 0 - Cache Error - // Bit 4 - RAMRO Triggered - // Bit 8 - RAMRO Overflow (too many invalid dma objects) - // Bit 12 - DMA Pusher - // Bit 16 - DMA Page Table Entry (pagefault?) - switch (reg->address) - { - case NV3_PFIFO_INTR: - ret = nv3->pfifo.interrupt_status; - break; - case NV3_PFIFO_INTR_EN: - ret = nv3->pfifo.interrupt_enable; - break; - case NV3_PFIFO_DELAY_0: - ret = nv3->pfifo.dma_delay_retry; - break; - // Debug - case NV3_PFIFO_DEBUG_0: - ret = nv3->pfifo.debug_0; - break; - case NV3_PFIFO_CONFIG_0: - ret = nv3->pfifo.config_0; - break; - // Some of these may need to become functions. - case NV3_PFIFO_CONFIG_RAMFC: - ret = nv3->pfifo.ramfc_config; - break; - case NV3_PFIFO_CONFIG_RAMHT: - ret = nv3->pfifo.ramht_config; - break; - case NV3_PFIFO_CONFIG_RAMRO: - ret = nv3->pfifo.ramro_config; - break; - /* These automatically trigger pulls when 1 is written */ - case NV3_PFIFO_CACHE0_PULL0: - ret = nv3->pfifo.cache0_settings.pull0; - break; - case NV3_PFIFO_CACHE1_PULL0: - ret = nv3->pfifo.cache1_settings.pull0; - break; - case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: - ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; - break; - case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: - ret = (nv3->pfifo.cache0_settings.context_is_dirty) ? (1 << NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) : 0; - break; - /* Does this automatically push? */ - case NV3_PFIFO_CACHE0_PUSH_ENABLED: - ret = nv3->pfifo.cache0_settings.push0; - break; - case NV3_PFIFO_CACHE1_PUSH_ENABLED: - ret = nv3->pfifo.cache1_settings.push0; - break; - case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: - ret = nv3->pfifo.cache0_settings.channel; - break; - case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: - ret = nv3->pfifo.cache1_settings.channel; - break; - case NV3_PFIFO_CACHE0_STATUS: - // CACHE0 has only one entry so it can only ever be empty or full - - if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache0_settings.get_address) - ret |= 1 << NV3_PFIFO_CACHE0_STATUS_EMPTY; - else - ret |= 1 << NV3_PFIFO_CACHE0_STATUS_FULL; - - break; - case NV3_PFIFO_CACHE1_STATUS: - // CACHE1 doesn't... - - if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) - ret |= 1 << NV3_PFIFO_CACHE1_STATUS_EMPTY; - - // Check if Cache1 (0x7C bytes in size depending on gpu?) is full - // Based on how the drivers do it - if (!nv3_pfifo_cache1_num_free_spaces()) - ret |= 1 << NV3_PFIFO_CACHE1_STATUS_FULL; - - if (nv3->pfifo.runout_put != nv3->pfifo.runout_get) - ret |= 1 << NV3_PFIFO_CACHE1_STATUS_RANOUT; - - break; - case NV3_PFIFO_CACHE0_PUT: - ret = nv3->pfifo.cache0_settings.put_address; - break; - case NV3_PFIFO_CACHE0_GET: - ret = nv3->pfifo.cache0_settings.get_address; - break; - case NV3_PFIFO_CACHE1_PUT: - ret = nv3->pfifo.cache1_settings.put_address; - break; - case NV3_PFIFO_CACHE1_GET: - ret = nv3->pfifo.cache1_settings.get_address; - break; - // Reassignment - case NV3_PFIFO_CACHE_REASSIGNMENT: - ret = nv3->pfifo.cache_reassignment & 0x01; //1bit meaningful - break; - // Cache1 exclusive stuff - // Control - case NV3_PFIFO_CACHE1_DMA_CONFIG_0: - ret = nv3->pfifo.cache1_settings.dma_state; - break; - case NV3_PFIFO_CACHE1_DMA_CONFIG_1: - ret = nv3->pfifo.cache1_settings.dma_length & (NV3_VRAM_SIZE_8MB) - 4; //MAX vram size - break; - case NV3_PFIFO_CACHE1_DMA_CONFIG_2: - ret = nv3->pfifo.cache1_settings.dma_address; - break; - case NV3_PFIFO_CACHE1_DMA_CONFIG_3: - if (nv3->nvbase.bus_generation == nv_bus_pci) - return NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_PCI; - else - return NV3_PFIFO_CACHE1_DMA_CONFIG_3_TARGET_NODE_AGP; - break; - case NV3_PFIFO_CACHE1_DMA_STATUS: - ret = nv3->pfifo.cache1_settings.dma_status; - break; - case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: - ret = nv3->pfifo.cache1_settings.dma_tlb_pt_base; - break; - case NV3_PFIFO_CACHE1_DMA_TLB_PTE: - ret = nv3->pfifo.cache1_settings.dma_tlb_pte; - break; - case NV3_PFIFO_CACHE1_DMA_TLB_TAG: - ret = nv3->pfifo.cache1_settings.dma_tlb_tag; - break; - // Runout - case NV3_PFIFO_RUNOUT_GET: - ret = nv3->pfifo.runout_get; - break; - case NV3_PFIFO_RUNOUT_PUT: - ret = nv3->pfifo.runout_put; - break; - case NV3_PFIFO_RUNOUT_STATUS: - if (nv3->pfifo.runout_put == nv3->pfifo.runout_get) - ret |= 1 << NV3_PFIFO_RUNOUT_STATUS_EMPTY; /* good news */ - else - ret |= 1 << NV3_PFIFO_RUNOUT_STATUS_RANOUT; /* bad news */ - - /* TODO: the following code sucks (move to a functio?) */ - - uint32_t new_size_ramro = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - - if (new_size_ramro == 0) - new_size_ramro = 0x200; - else if (new_size_ramro == 1) - new_size_ramro = 0x2000; - - // WTF? - if (nv3->pfifo.runout_put + 0x08 & (new_size_ramro - 0x08) == nv3->pfifo.runout_get) - ret |= 1 << NV3_PFIFO_RUNOUT_STATUS_FULL; /* VERY BAD news */ - - break; - - /* Cache1 is handled below - cache0 only has one entry */ - case NV3_PFIFO_CACHE0_CTX: - ret = nv3->pfifo.cache0_settings.context[0]; - break; - - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - /* Handle some special memory areas */ - else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) - { - uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; - ret = nv3->pfifo.cache1_settings.context[ctx_entry_id]; - - nv_log_verbose_only("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x\n", ctx_entry_id, ret); - } - /* Direct cache read stuff */ - else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) - { - nv_log_verbose_only("PFIFO Cache0 Read\n"); - - // See if we want the object name or the channel/subchannel information. - if (address & 4) - { - nv_log_verbose_only("Data=0x%08x\n", nv3->pfifo.cache0_entry.data); - - return nv3->pfifo.cache0_entry.data; - } - else - { - uint32_t final = nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); - - nv_log_verbose_only("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); - - - return final; - } - } - else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) - { - // Not sure if REV C changes this. It should... - uint32_t slot = 0; - - // shift right by 3, convert from address, to slot. - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) - slot = (address >> 3) & 0x3F; - else - slot = (address >> 3) & 0x1F; - - nv_log_verbose_only("PFIFO Cache1 Read slot=%d", slot); - - // See if we want the object name or the channel/subchannel information. - if (address & 4) - { - nv_log_verbose_only("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data); - return nv3->pfifo.cache1_entries[slot].data; - } - else - { - uint32_t final = nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL); - nv_log_verbose_only("Param (subchannel=15:13, method=12:2)=0x%08x\n", final); - return final; - } - - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pfifo_trigger_dma_if_required(void) -{ - // Not a thing for cache0 - - bool cache1_dma = false; - - /* Check that DMA is enabled */ - if ((nv3->pfifo.cache1_settings.dma_state & NV3_PFIFO_CACHE1_DMA_STATUS_STATE_RUNNING) - && nv3->pfifo.cache1_settings.dma_enabled) - { - uint32_t bytes_to_send = nv3->pfifo.cache1_settings.dma_length; - uint32_t where_to_send = nv3->pfifo.cache1_settings.dma_address; - uint32_t target_node = nv3->pfifo.cache1_settings.dma_target_node; //2=pci, 3=agp. - - /* Pagetable information */ - uint32_t tlb_pt_base = nv3->pfifo.cache1_settings.dma_tlb_pt_base; - uint32_t tlb_pt_entry = nv3->pfifo.cache1_settings.dma_tlb_pte; // notify_obj_page - uint32_t tlb_pt_tag = nv3->pfifo.cache1_settings.dma_tlb_tag; // 0xFFFFFFFF usually? - - /* - going to treat the format the same as notifiers - */ - if (!(tlb_pt_entry & NV3_PFIFO_CACHE1_DMA_TLB_PTE_IS_PRESENT)) - { - warning("NV3: Tried to DMA to a non-existent page! Big Problem!"); - return; - } - - uint32_t final_page_base = tlb_pt_entry & 0xFFFFF000; /* pull out 31:12 */ - - /* - page size is 0x1000 - */ - uint32_t final_address = final_page_base + (tlb_pt_entry << 10) + where_to_send; //x86 page size is 0x1000 (maybe rsh where_to_send by 2) - - nv_log_verbose_only("DMA Engine: DMA to %08x length=%08x", final_address, bytes_to_send); - - //-dma_bm_write() - } - - //we're done - nv3->pfifo.cache1_settings.dma_state &= ~NV3_PFIFO_CACHE1_DMA_STATUS_STATE_RUNNING; -} - -void nv3_pfifo_write(uint32_t address, uint32_t val) -{ - // before doing anything, check the subsystem enablement - - if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PFIFO) - & NV3_PMC_ENABLE_PFIFO_ENABLED) - { - nv_log("Repressing PFIFO write. The subsystem is disabled according to pmc_enable\n"); - return; - } - - nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0])); - - nv_log_verbose_only("PFIFO Write 0x%08x -> 0x%08x", val, address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_write) - reg->on_write(val); - else - { - switch (reg->address) - { - // Interrupt state: - // Bit 0 - Cache Error - // Bit 4 - RAMRO Triggered - // Bit 8 - RAMRO Overflow (too many invalid dma objects) - // Bit 12 - DMA Pusher - // Bit 16 - DMA Page Table Entry (pagefault?) - case NV3_PFIFO_INTR: - nv3->pfifo.interrupt_status &= ~val; - nv3_pmc_clear_interrupts(); - - // update the internal cache error state - if (!nv3->pfifo.interrupt_status & NV3_PFIFO_INTR_CACHE_ERROR) - nv3->pfifo.debug_0 &= ~NV3_PFIFO_INTR_CACHE_ERROR; - break; - case NV3_PFIFO_INTR_EN: - nv3->pfifo.interrupt_enable = val & 0x00011111; - nv3_pmc_handle_interrupts(true); - break; - case NV3_PFIFO_DELAY_0: - nv3->pfifo.dma_delay_retry = val; - break; - case NV3_PFIFO_CONFIG_0: - nv3->pfifo.config_0 = val; - break; - - case NV3_PFIFO_CONFIG_RAMHT: - nv3->pfifo.ramht_config = val; -// This code sucks a bit fix it later -#ifdef ENABLE_NV_LOG - uint32_t new_size_ramht = ((val >> 16) & 0x03); - - if (new_size_ramht == 0) - new_size_ramht = 0x1000; - else if (new_size_ramht == 1) - new_size_ramht = 0x2000; - else if (new_size_ramht == 2) - new_size_ramht = 0x4000; - else if (new_size_ramht == 3) - new_size_ramht = 0x8000; - - nv_log("RAMHT Reconfiguration\n" - "Base Address in RAMIN: %d\n" - "Size: 0x%08x bytes\n", ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12, new_size_ramht); -#endif - break; - case NV3_PFIFO_CONFIG_RAMFC: - nv3->pfifo.ramfc_config = val; - - nv_log("RAMFC Reconfiguration\n" - "Base Address in RAMIN: %d\n", ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9); - break; - case NV3_PFIFO_CONFIG_RAMRO: - nv3->pfifo.ramro_config = val; - - uint32_t new_size_ramro = ((val >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - - if (new_size_ramro == 0) - new_size_ramro = 0x200; - else if (new_size_ramro == 1) - new_size_ramro = 0x2000; - - nv_log("RAMRO Reconfiguration\n" - "Base Address in RAMIN: %d\n" - "Size: 0x%08x bytes\n", ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9, new_size_ramro); - break; - case NV3_PFIFO_DEBUG_0: - nv3->pfifo.debug_0 = val; - break; - // Reassignment - case NV3_PFIFO_CACHE_REASSIGNMENT: - nv3->pfifo.cache_reassignment = val & 0x01; //1bit meaningful - break; - // Control - these can trigger pulls - case NV3_PFIFO_CACHE0_PULL0: - nv3->pfifo.cache0_settings.pull0 = val; // 8bits meaningful - - if (nv3->pfifo.cache0_settings.pull0 & (1 >> NV3_PFIFO_CACHE0_PULL0_ENABLED)) - nv3_pfifo_cache0_pull(); - - break; - case NV3_PFIFO_CACHE1_PULL0: - nv3->pfifo.cache1_settings.pull0 = val; // 8bits meaningful - - if (nv3->pfifo.cache1_settings.pull0 & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) - nv3_pfifo_cache1_pull(); - - break; - case NV3_PFIFO_CACHE0_PULLER_CTX_STATE: - nv3->pfifo.cache0_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; - break; - case NV3_PFIFO_CACHE1_PULLER_CTX_STATE: - nv3->pfifo.cache1_settings.context_is_dirty = (val >> NV3_PFIFO_CACHE0_PULLER_CTX_STATE_DIRTY) & 0x01; - break; - case NV3_PFIFO_CACHE0_PUSH_ENABLED: - nv3->pfifo.cache0_settings.push0 = val; - break; - case NV3_PFIFO_CACHE1_PUSH_ENABLED: - nv3->pfifo.cache1_settings.push0 = val; - break; - case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: - nv3->pfifo.cache0_settings.channel = val; - break; - case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: - nv3->pfifo.cache1_settings.channel = val; - break; - // CACHE0_STATUS and CACHE1_STATUS are not writable - // DMA configuration - case NV3_PFIFO_CACHE1_DMA_CONFIG_0: - nv3->pfifo.cache1_settings.dma_state = val; - break; - case NV3_PFIFO_CACHE1_DMA_CONFIG_1: - nv3->pfifo.cache1_settings.dma_length = val; - break; - case NV3_PFIFO_CACHE1_DMA_CONFIG_2: - nv3->pfifo.cache1_settings.dma_address = val; - break; - case NV3_PFIFO_CACHE1_DMA_STATUS: - nv3->pfifo.cache1_settings.dma_status = val; - break; - case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: - nv3->pfifo.cache1_settings.dma_tlb_pt_base = val; - break; - case NV3_PFIFO_CACHE1_DMA_TLB_PTE: - nv3->pfifo.cache1_settings.dma_tlb_pte = val; - break; - case NV3_PFIFO_CACHE1_DMA_TLB_TAG: - nv3->pfifo.cache1_settings.dma_tlb_tag = val; - break; - /* Put and Get addresses */ - case NV3_PFIFO_CACHE0_PUT: - nv3->pfifo.cache0_settings.put_address = val; - break; - case NV3_PFIFO_CACHE0_GET: - nv3->pfifo.cache0_settings.get_address = val; - break; - case NV3_PFIFO_CACHE1_PUT: - nv3->pfifo.cache1_settings.put_address = val; - break; - case NV3_PFIFO_CACHE1_GET: - nv3->pfifo.cache1_settings.get_address = val; - break; - case NV3_PFIFO_RUNOUT_GET: - { - uint32_t size_get = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - - if (size_get == 0) //512b - nv3->pfifo.runout_get = val & (NV3_RAMIN_RAMRO_SIZE_0 - 0x07); - else - nv3->pfifo.runout_get = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); - break; - } - case NV3_PFIFO_RUNOUT_PUT: - { - uint32_t size_put = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - - if (size_put == 0) //512b - nv3->pfifo.runout_put = val & (NV3_RAMIN_RAMRO_SIZE_0 - 0x07); - else - nv3->pfifo.runout_put = val & (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); - - break; - } - /* Cache1 Context is handled below */ - case NV3_PFIFO_CACHE0_CTX: - nv3->pfifo.cache0_settings.context[0] = val; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END) - { - nv_log_verbose_only("PFIFO Cache0 Write\n"); - - // 3104 always written after 3100 - if (address & 4) - { - nv_log_verbose_only("Name = 0x%08x\n", val); - nv3->pfifo.cache0_entry.data = val; - nv3_pfifo_cache0_pull(); // immediately pull out - } - else - { - nv3->pfifo.cache0_entry.method = (val & 0x1FFC); - nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; - nv_log_verbose_only("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache0_entry.subchannel, nv3->pfifo.cache0_entry.method); - } - - } - else if (address >= NV3_PFIFO_CACHE1_METHOD_START && address <= NV3_PFIFO_CACHE1_METHOD_END) - { - // Not sure if REV C changes this. It should... - uint32_t slot = 0; - - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) - slot = (address >> 3) & 0x3F; - else - slot = (address >> 3) & 0x1F; - - uint32_t real_entry = nv3_pfifo_cache1_normal2gray(slot); - - nv_log_verbose_only("Cache1 Write Slot %d (Gray code)", real_entry); - - // See if we want the object name or the channel/subchannel information. - if (address & 4) - { - nv_log_verbose_only("Name = 0x%08x\n", val); - nv3->pfifo.cache1_entries[real_entry].data = val; - } - else - { - nv3->pfifo.cache1_entries[real_entry].method = (val & 0x1FFC); - nv3->pfifo.cache1_entries[real_entry].subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07; - nv_log_verbose_only("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method); - } - } - /* Handle some special memory areas */ - else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END) - { - uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8; - nv3->pfifo.cache1_settings.context[ctx_entry_id] = val; - - nv_log_verbose_only("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val); - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } - - /* Trigger DMA for notifications if we need to */ - nv3_pfifo_trigger_dma_if_required(); -} - - -/* -https://en.wikipedia.org/wiki/Gray_code -WHY?????? IT'S NOT A TELEGRAPH IT'S A GPU????? - -Convert from a normal number to a total insanity number which is only used in PFIFO CACHE1 for ungodly and totally unknowable reasons -(Possibly it just makes it easier to implement in logic) - -I decided to use a lookup table to save everyone's time, also the numbers generated from the function -that existed here before didn't make any sense -*/ - -#define NV3_GRAY_TABLE_NUM_ENTRIES 64 - -uint8_t nv3_pfifo_cache1_gray_code_table[NV3_GRAY_TABLE_NUM_ENTRIES] = { - 0b000000, 0b000001, 0b000011, 0b000010, 0b000110, 0b000111, 0b000101, 0b000100, //0x07 - 0b001100, 0b001101, 0b001111, 0b001110, 0b001010, 0b001011, 0b001001, 0b001000, //0x0F - 0b011000, 0b011001, 0b011011, 0b011010, 0b011110, 0b011111, 0b011101, 0b011100, //0x17 - 0b010100, 0b010101, 0b010111, 0b010110, 0b010010, 0b010011, 0b010001, 0b010000, //0x1F - 0b110000, 0b110001, 0b110011, 0b110010, 0b110110, 0b110111, 0b110101, 0b110100, //0x27 - 0b111100, 0b111101, 0b111111, 0b111110, 0b111010, 0b111011, 0b111001, 0b111000, //0x2F - 0b101000, 0b101001, 0b101011, 0b101010, 0b101110, 0b101111, 0b101101, 0b101100, //0x37 - 0b100100, 0b100101, 0b100111, 0b100110, 0b100010, 0b100011, 0b100001, 0b100000 //0x3F -}; - -/* The function is called up to hundreds of thousands of times per second, it's too slow to do anything else */ -uint8_t nv3_pfifo_cache1_binary_code_table[NV3_GRAY_TABLE_NUM_ENTRIES] = -{ - 0x00, 0x01, 0x03, 0x02, 0x07, 0x06, 0x04, 0x05, // 0x07 (0) - 0x0F, 0x0E, 0x0C, 0x0D, 0x08, 0x09, 0x0B, 0x0A, // 0x0F (1000) - 0x1F, 0x1E, 0x1C, 0x1D, 0x18, 0x19, 0x1B, 0x1A, // 0x17 (10000) - 0x10, 0x11, 0x13, 0x12, 0x17, 0x16, 0x14, 0x15, // 0x1F (11000) - 0x3F, 0x3E, 0x3C, 0x3D, 0x38, 0x39, 0x3B, 0x3A, // 0x27 (100000) - 0x30, 0x31, 0x33, 0x32, 0x37, 0x36, 0x34, 0x35, // 0x2F (101000) - 0x20, 0x21, 0x23, 0x22, 0x27, 0x26, 0x24, 0x25, // 0x37 (110000) - 0x2F, 0x2E, 0x2C, 0x2D, 0x28, 0x29, 0x2B, 0x2A, // 0X3f (111000) -}; - -uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val) -{ - return nv3_pfifo_cache1_gray_code_table[val]; -} - -/* -Back to sanity -*/ -uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) -{ - return nv3_pfifo_cache1_binary_code_table[val]; -} - -/* -You can't push into cache0 on the real hardware, but it's not practically done because Cache0 is meant to be reserved for software objects, -NV_USER writes always go to CACHE1 -*/ - -// Pulls graphics objects OUT of cache0 -void nv3_pfifo_cache0_pull(void) -{ - // Do nothing if PFIFO CACHE0 is disabled - if (!nv3->pfifo.cache0_settings.pull0 & (1 >> NV3_PFIFO_CACHE0_PULL0_ENABLED)) - return; - - // Do nothing if there is nothing in cache0 to pull - if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache0_settings.get_address) - return; - - // There is only one entry for cache0 - uint8_t current_channel = nv3->pfifo.cache0_settings.channel; - uint8_t current_subchannel = nv3->pfifo.cache0_entry.subchannel; - uint32_t current_param = nv3->pfifo.cache0_entry.data; - uint16_t current_method = nv3->pfifo.cache0_entry.method; - - // i.e. there is no method in cache0, so we have to find the object. - if (!current_method) - { - // flip the get address over - nv3->pfifo.cache0_settings.get_address ^= 0x04; - - if (!nv3_ramin_find_object(current_param, 0, current_channel, current_subchannel)) - return; // interrupt was fired, and we went to ramro - } - - uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries? - uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; - - // Tell the CPU if we found a software method and turn off cache pulling - if (!(current_context & 0x800000)) - { - nv_log_verbose_only("The object in CACHE0 is a software object\n"); - - nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; - nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); - return; - } - - // Is this needed? - nv3->pfifo.cache0_settings.get_address ^= 0x04; - - #ifndef RELEASE_BUILD - - nv_log_verbose_only("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n"); - - - nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; - - nv3_debug_ramin_print_context_info(current_param, context_structure); - - nv3_pgraph_submit(current_param, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); - #endif - -} - -void nv3_pfifo_context_switch(uint32_t new_channel) -{ - /* Send our contexts to RAMFC. Load the new ones from RAMFC. */ - if (new_channel >= NV3_DMA_CHANNELS) - fatal("nv3_pfifo_context_switch: Tried to switch to invalid dma channel"); - - //uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF; -} - -// NV_USER writes go here! -// Pushes graphics objects into cache1 -void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param) -{ - bool oh_shit = false; // RAMRO needed - nv3_ramin_ramro_reason oh_shit_reason = 0x00; // It's all good for now - - // bit 23 of a ramin dword means it's a write... - uint32_t new_address = 0; - - uint32_t method_offset = (addr & 0x1FFC); // size of dma object is 0x2000 and some universal methods are implemented at this point, like free - - // Up to 128 per envytools? - uint32_t channel = (addr >> NV3_OBJECT_SUBMIT_CHANNEL) & 0x7F; - uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & (NV3_DMA_CHANNELS - 1); - - // first make sure there is even any cache available - if (!nv3->pfifo.cache1_settings.push0) - { - oh_shit = true; - oh_shit_reason = nv3_runout_reason_no_cache_available; - new_address |= (nv3_runout_reason_no_cache_available << NV3_PFIFO_RUNOUT_RAMIN_ERR); - - } - - // Check if runout is full - if (nv3->pfifo.runout_get != nv3->pfifo.runout_put) - { - oh_shit = true; - oh_shit_reason = nv3_runout_reason_cache_ran_out; // ? really ? I guess this means we already ran out.. - new_address |= (nv3_runout_reason_cache_ran_out << NV3_PFIFO_RUNOUT_RAMIN_ERR); - } - - if (!nv3_pfifo_cache1_num_free_spaces()) - { - oh_shit = true; - oh_shit_reason = nv3_runout_reason_free_count_overrun; - new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR); - } - - // 0x0 is used for creating the object. - if (method_offset > 0 && method_offset < 0x100) - { - // Reserved nvidia methods - oh_shit = true; - oh_shit_reason = nv3_runout_reason_reserved_access; - new_address |= (nv3_runout_reason_reserved_access << NV3_PFIFO_RUNOUT_RAMIN_ERR); - - } - - // Now check for context switching - - if (channel != nv3->pfifo.cache1_settings.channel) - { - // Cache reassignment required - if (!nv3->pfifo.cache_reassignment - || (nv3->pfifo.cache1_settings.get_address != nv3->pfifo.cache1_settings.put_address)) - { - oh_shit = true; - oh_shit_reason = nv3_runout_reason_no_cache_available; - new_address |= (nv3_runout_reason_no_cache_available << NV3_PFIFO_RUNOUT_RAMIN_ERR); - } - - nv3_pfifo_context_switch(channel); - } - - // Did we fuck up? - if (oh_shit) - { - nv_log("OH CRAP: Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x", - oh_shit_reason, channel, subchannel, method_offset); - - nv3_ramro_write(nv3->pfifo.runout_put, new_address); - nv3_ramro_write(nv3->pfifo.runout_put + 4, param); - - nv3->pfifo.runout_put += 0x08; - - uint32_t ramro_size = (nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01; - - /* Make sure it's valid */ - switch (ramro_size) - { - case 0: - nv3->pfifo.runout_put &= (NV3_RAMIN_RAMRO_SIZE_0 - 0x07); - break; - case 1: - nv3->pfifo.runout_put &= (NV3_RAMIN_RAMRO_SIZE_1 - 0x07); - break; - } - - //Fire the interrupt. Also the very bad interrupt... - if (nv3->pfifo.runout_get == nv3->pfifo.runout_put) - nv3_pfifo_interrupt(NV3_PFIFO_INTR_RUNOUT_OVERFLOW, true); - else - nv3_pfifo_interrupt(NV3_PFIFO_INTR_RUNOUT, true); - - return; - } - - // We didn't. Let's put it in CACHE1 - uint32_t current_put_index = nv3->pfifo.cache1_settings.put_address >> 2; - nv3->pfifo.cache1_entries[current_put_index].subchannel = subchannel; - nv3->pfifo.cache1_entries[current_put_index].method = method_offset; - nv3->pfifo.cache1_entries[current_put_index].data = param; - - // now we have to recalculate the cache1 put address - uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_index); - next_put_address++; - - if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX# - next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); - else - next_put_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); - - nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2; - - nv_log_verbose_only("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n", - channel, subchannel, param, method_offset, nv3->pfifo.cache1_settings.put_address); - - // Now we're done. Phew! -} - -// Pulls graphics objects OUT of cache1 -void nv3_pfifo_cache1_pull(void) -{ - // Do nothing if PFIFO CACHE1 is disabled - if (!nv3->pfifo.cache1_settings.pull0 & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED)) - return; - - // Do nothing if there is nothing in cache1 to pull - if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address) - return; - - uint32_t get_index = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably - - uint8_t current_channel = nv3->pfifo.cache1_settings.channel; - uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_index].subchannel; - uint32_t current_param = nv3->pfifo.cache1_entries[get_index].data; - uint16_t current_method = nv3->pfifo.cache1_entries[get_index].method; - - // NV_ROOT - if (!current_method) - { - if (!nv3_ramin_find_object(current_param, 1, current_channel, current_subchannel)) - return; // interrupt was fired, and we went to ramro - } - - // should this be obtained from the grobj? Test on real nv3 h/w after drawrect.nvp works - uint32_t current_context = nv3->pfifo.cache1_settings.context[current_subchannel]; // get the current subchannel - - uint8_t class_id = ((nv3_ramin_context_t*)¤t_context)->class_id; - - - - // start by incrementing - uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1; - - if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX - next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1); - else - next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1); - - // Tell the CPU if we found a software method - //bit23 unset=software - //bit23 set=hardware - if (!(current_context & 0x800000)) - { - nv_log_verbose_only("The object in CACHE1 is a software object\n"); - - nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; - nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); - return; - } - - // Is this needed? - nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2; - - #ifndef RELEASE_BUILD - - nv_log_verbose_only("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n"); - - nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)¤t_context; - - nv3_debug_ramin_print_context_info(current_param, context_structure); - #endif - - nv3_pgraph_submit(current_param, current_method, current_channel, current_subchannel, class_id & 0x1F, context_structure); - - - //Todo: finish it -} - -// THIS IS PER SUBCHANNEL! -uint32_t nv3_pfifo_cache1_num_free_spaces(void) -{ - // get the index - - uint32_t get_index = nv3->pfifo.cache1_settings.get_address >> 2; - uint32_t put_index = nv3->pfifo.cache1_settings.put_address >> 2; - - uint32_t real_get_address = nv3_pfifo_cache1_gray2normal(get_index) << 2; - uint32_t real_put_address = nv3_pfifo_cache1_gray2normal(put_index) << 2; - - // There is no hope of being able to understand it. Nobody can understand - return (real_get_address - real_put_address - 4) & 0x7C; // there are 64 entries what -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c deleted file mode 100644 index 3ad9fa2a1..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pgraph.c +++ /dev/null @@ -1,632 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PGRAPH (Scene Graph for 2D/3D Accelerated Graphics) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -// Initialise the PGRAPH subsystem. -void nv3_pgraph_init(void) -{ - nv_log("Initialising PGRAPH..."); - // Set up the vblank interrupt - nv3->nvbase.svga.vblank_start = nv3_pgraph_vblank_start; - nv_log("Done!\n"); -} - -// -// ****** PGRAPH register list START ****** -// - -nv_register_t pgraph_registers[] = { - { NV3_PGRAPH_DEBUG_0, "PGRAPH Debug 0", NULL, NULL }, - { NV3_PGRAPH_DEBUG_1, "PGRAPH Debug 1", NULL, NULL }, - { NV3_PGRAPH_DEBUG_2, "PGRAPH Debug 2", NULL, NULL }, - { NV3_PGRAPH_DEBUG_3, "PGRAPH Debug 3", NULL, NULL }, - { NV3_PGRAPH_INTR_0, "PGRAPH Interrupt Status 0", NULL, NULL }, - { NV3_PGRAPH_INTR_EN_0, "PGRAPH Interrupt Enable 0", NULL, NULL }, - { NV3_PGRAPH_INTR_1, "PGRAPH Interrupt Status 1", NULL, NULL }, - { NV3_PGRAPH_INTR_EN_1, "PGRAPH Interrupt Enable 1", NULL, NULL }, - { NV3_PGRAPH_CTX_SWITCH, "PGRAPH DMA Context Switch", NULL, NULL }, - { NV3_PGRAPH_CONTEXT_CONTROL, "PGRAPH DMA Context Control", NULL, NULL }, - { NV3_PGRAPH_CONTEXT_USER, "PGRAPH DMA Context User", NULL, NULL }, - //{ NV3_PGRAPH_CONTEXT_CACHE(0), "PGRAPH DMA Context Cache", NULL, NULL }, - { NV3_PGRAPH_ABS_UCLIP_XMIN, "PGRAPH Absolute Clip Minimum X [17:0]", NULL, NULL }, - { NV3_PGRAPH_ABS_UCLIP_XMAX, "PGRAPH Absolute Clip Maximum X [17:0]", NULL, NULL }, - { NV3_PGRAPH_ABS_UCLIP_YMIN, "PGRAPH Absolute Clip Minimum Y [17:0]", NULL, NULL }, - { NV3_PGRAPH_ABS_UCLIP_YMAX, "PGRAPH Absolute Clip Maximum Y [17:0]", NULL, NULL }, - { NV3_PGRAPH_SRC_CANVAS_MIN, "PGRAPH Source Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_SRC_CANVAS_MAX, "PGRAPH Source Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_DST_CANVAS_MIN, "PGRAPH Destination Canvas Minimum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_DST_CANVAS_MAX, "PGRAPH Destination Canvas Maximum Coordinates (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_PATTERN_COLOR_0_RGB, "PGRAPH Pattern Color 0_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_COLOR_0_ALPHA, "PGRAPH Pattern Color 0_1 (Bits 7:0 = Alpha)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_COLOR_1_RGB, "PGRAPH Pattern Color 1_0 (Bits 29:20 = Red, Bits 19:10 = Green, Bits 9:0 = Blue)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_COLOR_1_ALPHA, "PGRAPH Pattern Color 1_1 (Bits 7:0 = Alpha)", NULL, NULL, }, - { NV3_PGRAPH_PATTERN_BITMAP_HIGH, "PGRAPH Pattern Bitmap (High 32bits)", NULL, NULL}, - { NV3_PGRAPH_PATTERN_BITMAP_LOW, "PGRAPH Pattern Bitmap (Low 32bits)", NULL, NULL}, - { NV3_PGRAPH_PATTERN_SHAPE, "PGRAPH Pattern Shape (1:0 - 0=8x8, 1=64x1, 2=1x64)", NULL, NULL}, - { NV3_PGRAPH_ROP3, "PGRAPH GDI Ternary Render Operation ROP3 (2^3 bits = 256 possible operations)", NULL, NULL}, - { NV3_PGRAPH_PLANE_MASK, "PGRAPH Current Plane Mask (7:0)", NULL, NULL}, - { NV3_PGRAPH_CHROMA_KEY, "PGRAPH Chroma Key (17:0) (Bit 30 = Alpha, 29:20 = Red, 19:10 = Green, 9:0 = Blue)", NULL, NULL}, - { NV3_PGRAPH_BETA, "PGRAPH Beta factor", NULL, NULL }, - { NV3_PGRAPH_DMA, "PGRAPH DMA", NULL, NULL }, - { NV3_PGRAPH_CLIP_MISC, "PGRAPH Clipping Miscellaneous Settings", NULL, NULL }, - { NV3_PGRAPH_NOTIFY, "PGRAPH Notifier (Wip...)", NULL, NULL }, - { NV3_PGRAPH_CLIP0_MIN, "PGRAPH Clip0 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_CLIP0_MAX, "PGRAPH Clip0 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_CLIP1_MIN, "PGRAPH Clip1 Min (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_CLIP1_MAX, "PGRAPH Clip1 Max (Bits 30:16 = Y, Bits 10:0 = X)", NULL, NULL}, - { NV3_PGRAPH_FIFO_ACCESS, "PGRAPH - Can we access PFIFO?", NULL, NULL, }, - { NV3_PGRAPH_STATUS, "PGRAPH Status", NULL, NULL }, - { NV3_PGRAPH_TRAPPED_ADDRESS, "PGRAPH Trapped Address", NULL, NULL }, - { NV3_PGRAPH_TRAPPED_DATA, "PGRAPH Trapped Data", NULL, NULL }, - { NV3_PGRAPH_INSTANCE, "PGRAPH Object Instance", NULL, NULL}, - { NV3_PGRAPH_TRAPPED_INSTANCE, "PGRAPH Trapped Object Instance", NULL, NULL }, - { NV3_PGRAPH_DMA_INTR_0, "PGRAPH DMA Interrupt Status (unimplemented)", NULL, NULL }, - { NV3_PGRAPH_DMA_INTR_EN_0, "PGRAPH DMA Interrupt Enable (unimplemented)", NULL, NULL }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -uint32_t nv3_pgraph_read(uint32_t address) -{ - // before doing anything, check that this is even enabled.. - - if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH) - & NV3_PMC_ENABLE_PGRAPH_ENABLED) - { - nv_log("Repressing PGRAPH read. The subsystem is disabled according to pmc_enable, returning 0\n"); - return 0x00; - } - - uint32_t ret = 0x00; - - nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); - - // todo: friendly logging - - nv_log_verbose_only("PGRAPH Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - switch (reg->address) - { - case NV3_PGRAPH_DEBUG_0: - ret = nv3->pgraph.debug_0; - break; - case NV3_PGRAPH_DEBUG_1: - ret = nv3->pgraph.debug_1; - break; - case NV3_PGRAPH_DEBUG_2: - ret = nv3->pgraph.debug_2; - break; - case NV3_PGRAPH_DEBUG_3: - ret = nv3->pgraph.debug_3; - break; - //interrupt status and enable regs - case NV3_PGRAPH_INTR_0: - ret = nv3->pgraph.interrupt_status_0; - nv3_pmc_clear_interrupts(); - break; - case NV3_PGRAPH_INTR_1: - ret = nv3->pgraph.interrupt_status_1; - nv3_pmc_clear_interrupts(); - break; - case NV3_PGRAPH_INTR_EN_0: - ret = nv3->pgraph.interrupt_enable_0; - nv3_pmc_handle_interrupts(true); - break; - case NV3_PGRAPH_INTR_EN_1: - ret = nv3->pgraph.interrupt_enable_1; - nv3_pmc_handle_interrupts(true); - break; - // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like - // during the driver initialisation process - - // In the future, these will most likely have their own functions... - - // Context Swithcing (THIS IS CONTROLLED BY PFIFO!) - case NV3_PGRAPH_CTX_SWITCH: - ret = nv3->pgraph.context_switch; - break; - case NV3_PGRAPH_CONTEXT_CONTROL: - ret = *(uint32_t*)&nv3->pgraph.context_control; - break; - case NV3_PGRAPH_CONTEXT_USER: - ret = *(uint32_t*)&nv3->pgraph.context_user; - break; - // Clip - case NV3_PGRAPH_ABS_UCLIP_XMIN: - ret = nv3->pgraph.abs_uclip_xmin; - break; - case NV3_PGRAPH_ABS_UCLIP_XMAX: - ret = nv3->pgraph.abs_uclip_xmax; - break; - case NV3_PGRAPH_ABS_UCLIP_YMIN: - ret = nv3->pgraph.abs_uclip_ymin; - break; - case NV3_PGRAPH_ABS_UCLIP_YMAX: - ret = nv3->pgraph.abs_uclip_ymax; - break; - // Canvas - case NV3_PGRAPH_SRC_CANVAS_MIN: - ret = *(uint32_t*)&nv3->pgraph.src_canvas_min; - break; - case NV3_PGRAPH_SRC_CANVAS_MAX: - ret = *(uint32_t*)&nv3->pgraph.src_canvas_max; - break; - // Pattern - case NV3_PGRAPH_PATTERN_COLOR_0_RGB: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_rgb; - break; - case NV3_PGRAPH_PATTERN_COLOR_0_ALPHA: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_0_alpha; - break; - case NV3_PGRAPH_PATTERN_COLOR_1_RGB: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_rgb; - break; - case NV3_PGRAPH_PATTERN_COLOR_1_ALPHA: - ret = *(uint32_t*)&nv3->pgraph.pattern_color_1_alpha; - break; - case NV3_PGRAPH_PATTERN_BITMAP_HIGH: - ret = (nv3->pgraph.pattern_bitmap >> 32) & 0xFFFFFFFF; - break; - case NV3_PGRAPH_PATTERN_BITMAP_LOW: - ret = (nv3->pgraph.pattern_bitmap & 0xFFFFFFFF); - break; - // Beta factor - case NV3_PGRAPH_BETA: - ret = nv3->pgraph.beta_factor; - break; - // Todo: Massive table of ROP IDs or at least known ones? - case NV3_PGRAPH_ROP3: - ret = nv3->pgraph.rop; - break; - case NV3_PGRAPH_CHROMA_KEY: - ret = *(uint32_t*)&nv3->pgraph.chroma_key; - break; - case NV3_PGRAPH_PLANE_MASK: - ret = nv3->pgraph.plane_mask; - break; - // DMA - case NV3_PGRAPH_DMA: - ret = *(uint32_t*)&nv3->pgraph.dma_settings; - break; - case NV3_PGRAPH_NOTIFY: - ret = *(uint32_t*)&nv3->pgraph.notifier; - break; - // More clip - case NV3_PGRAPH_CLIP0_MIN: - ret = *(uint32_t*)&nv3->pgraph.clip0_min; - break; - case NV3_PGRAPH_CLIP0_MAX: - ret = *(uint32_t*)&nv3->pgraph.clip0_max; - break; - case NV3_PGRAPH_CLIP1_MIN: - ret = *(uint32_t*)&nv3->pgraph.clip1_min; - break; - case NV3_PGRAPH_CLIP1_MAX: - ret = *(uint32_t*)&nv3->pgraph.clip1_max; - break; - case NV3_PGRAPH_CLIP_MISC: - ret = *(uint32_t*)&nv3->pgraph.clip_misc_settings; - break; - - // Overall Status - case NV3_PGRAPH_STATUS: - ret = *(uint32_t*)&nv3->pgraph.status; - break; - // Trapped Address - case NV3_PGRAPH_TRAPPED_ADDRESS: - ret = nv3->pgraph.trapped_address; - break; - case NV3_PGRAPH_TRAPPED_DATA: - ret = nv3->pgraph.trapped_data; - break; - case NV3_PGRAPH_INSTANCE: - ret = nv3->pgraph.instance; - break; - case NV3_PGRAPH_TRAPPED_INSTANCE: - ret = nv3->pgraph.trapped_instance; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - /* Special exception for memory areas */ - if (address >= NV3_PGRAPH_CONTEXT_CACHE(0) - && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE)) - { - // Addresses should be aligned to 4 bytes. - uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)); - - nv_log_verbose_only("PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]); - } - else /* Completely unknown */ - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - } - - return ret; -} - -void nv3_pgraph_write(uint32_t address, uint32_t value) -{ - if (!(nv3->pmc.enable >> NV3_PMC_ENABLE_PGRAPH) - & NV3_PMC_ENABLE_PGRAPH_ENABLED) - { - nv_log("Repressing PGRAPH write. The subsystem is disabled according to pmc_enable\n"); - return; - } - - nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0])); - - nv_log_verbose_only("PGRAPH Write 0x%08x -> 0x%08x\n", value, address); - - // if the register actually exists - if (reg) - { - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - case NV3_PGRAPH_DEBUG_0: - nv3->pgraph.debug_0 = value; - break; - case NV3_PGRAPH_DEBUG_1: - nv3->pgraph.debug_1 = value; - break; - case NV3_PGRAPH_DEBUG_2: - nv3->pgraph.debug_2 = value; - break; - case NV3_PGRAPH_DEBUG_3: - nv3->pgraph.debug_3 = value; - break; - //interrupt status and enable regs - case NV3_PGRAPH_INTR_0: - nv3->pgraph.interrupt_status_0 &= ~value; - //we changed interrupt state - nv3_pmc_clear_interrupts(); - break; - case NV3_PGRAPH_INTR_1: - nv3->pgraph.interrupt_status_1 &= ~value; - //we changed interrupt state - nv3_pmc_clear_interrupts(); - break; - // Only bits divisible by 4 matter - // and only bit0-16 is defined in intr_1 - case NV3_PGRAPH_INTR_EN_0: - nv3->pgraph.interrupt_enable_0 = value & 0x11111111; - nv3_pmc_handle_interrupts(true); - break; - case NV3_PGRAPH_INTR_EN_1: - nv3->pgraph.interrupt_enable_1 = value & 0x00011111; - nv3_pmc_handle_interrupts(true); - break; - case NV3_PGRAPH_DMA_INTR_0: - nv3->pgraph.interrupt_status_dma &= ~value; - nv3_pmc_clear_interrupts(); - break; - case NV3_PGRAPH_DMA_INTR_EN_0: - nv3->pgraph.interrupt_enable_dma = value & 0x000111111; - nv_log("Handling PGRAPH_DMA interrupts not implemented"); - nv3_pmc_handle_interrupts(true); - break; - // A lot of this is currently a temporary implementation so that we can just debug what the current state looks like - // during the driver initialisation process - - // In the future, these will most likely have their own functions... - - // Context Swithcing (THIS IS CONTROLLED BY PFIFO!) - case NV3_PGRAPH_CTX_SWITCH: - nv3->pgraph.context_switch = value; - break; - case NV3_PGRAPH_CONTEXT_CONTROL: - *(uint32_t*)&nv3->pgraph.context_control = value; - break; - case NV3_PGRAPH_CONTEXT_USER: - *(uint32_t*)&nv3->pgraph.context_user = value; - break; - // Clip - case NV3_PGRAPH_ABS_UCLIP_XMIN: - nv3->pgraph.abs_uclip_xmin = value; - break; - case NV3_PGRAPH_ABS_UCLIP_XMAX: - nv3->pgraph.abs_uclip_xmax = value; - break; - case NV3_PGRAPH_ABS_UCLIP_YMIN: - nv3->pgraph.abs_uclip_ymin = value; - break; - case NV3_PGRAPH_ABS_UCLIP_YMAX: - nv3->pgraph.abs_uclip_ymax = value; - break; - // Canvas - case NV3_PGRAPH_SRC_CANVAS_MIN: - *(uint32_t*)&nv3->pgraph.src_canvas_min = value; - break; - case NV3_PGRAPH_SRC_CANVAS_MAX: - *(uint32_t*)&nv3->pgraph.src_canvas_max = value; - break; - // Pattern - case NV3_PGRAPH_PATTERN_COLOR_0_RGB: - *(uint32_t*)&nv3->pgraph.pattern_color_0_rgb = value; - break; - case NV3_PGRAPH_PATTERN_COLOR_0_ALPHA: - *(uint32_t*)&nv3->pgraph.pattern_color_0_alpha = value; - break; - case NV3_PGRAPH_PATTERN_COLOR_1_RGB: - *(uint32_t*)&nv3->pgraph.pattern_color_1_rgb = value; - break; - case NV3_PGRAPH_PATTERN_COLOR_1_ALPHA: - *(uint32_t*)&nv3->pgraph.pattern_color_1_alpha = value; - break; - case NV3_PGRAPH_PATTERN_BITMAP_HIGH: - nv3->pgraph.pattern_bitmap |= ((uint64_t)value << 32); - break; - case NV3_PGRAPH_PATTERN_BITMAP_LOW: - nv3->pgraph.pattern_bitmap |= value; - break; - // Beta factor - case NV3_PGRAPH_BETA: - nv3->pgraph.beta_factor = value; - break; - // Todo: Massive table of ROP IDs or at least known ones? - case NV3_PGRAPH_ROP3: - nv3->pgraph.rop = value & 0xFF; - break; - case NV3_PGRAPH_CHROMA_KEY: - nv3->pgraph.chroma_key = value; - break; - case NV3_PGRAPH_PLANE_MASK: - nv3->pgraph.plane_mask = value; - break; - // DMA - case NV3_PGRAPH_DMA: - *(uint32_t*)&nv3->pgraph.dma_settings = value; - break; - case NV3_PGRAPH_NOTIFY: - *(uint32_t*)&nv3->pgraph.notifier = value; - break; - // More clip - case NV3_PGRAPH_CLIP0_MIN: - *(uint32_t*)&nv3->pgraph.clip0_min = value; - break; - case NV3_PGRAPH_CLIP0_MAX: - *(uint32_t*)&nv3->pgraph.clip0_max = value; - break; - case NV3_PGRAPH_CLIP1_MIN: - *(uint32_t*)&nv3->pgraph.clip1_min = value; - break; - case NV3_PGRAPH_CLIP1_MAX: - *(uint32_t*)&nv3->pgraph.clip1_max = value; - break; - case NV3_PGRAPH_CLIP_MISC: - *(uint32_t*)&nv3->pgraph.clip_misc_settings = value; - break; - // Overall Status - case NV3_PGRAPH_STATUS: - *(uint32_t*)&nv3->pgraph.status = value; - break; - // Trapped Address - case NV3_PGRAPH_TRAPPED_ADDRESS: - nv3->pgraph.trapped_address = value; - break; - case NV3_PGRAPH_TRAPPED_DATA: - nv3->pgraph.trapped_data = value; - break; - case NV3_PGRAPH_INSTANCE: - nv3->pgraph.instance = value; - break; - case NV3_PGRAPH_TRAPPED_INSTANCE: - nv3->pgraph.trapped_instance = value; - break; - - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - } - else - { - /* Special exception for memory areas */ - if (address >= NV3_PGRAPH_CONTEXT_CACHE(0) - && address <= NV3_PGRAPH_CONTEXT_CACHE(NV3_PGRAPH_CONTEXT_CACHE_SIZE)) - { - // Addresses should be aligned to 4 bytes. - uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0)) >> 2; - - nv_log_verbose_only("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value); - nv3->pgraph.context_cache[entry] = value; - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } - } -} - -// Fire a VALID Pgraph interrupt: num is the bit# of the interrupt in the GPU subsystem INTR_EN register. -void nv3_pgraph_interrupt_valid(uint32_t num) -{ - nv3->pgraph.interrupt_status_0 |= (1 << num); - nv3_pmc_handle_interrupts(true); -} - -// Fire an INVALID pgraph interrupt -void nv3_pgraph_interrupt_invalid(uint32_t num) -{ - nv3->pgraph.interrupt_status_1 |= (1 << num); - - // Some code in pcbox hat enables the "reserved" bit HERE if it's set in intr 0. What??? - nv3_pmc_handle_interrupts(true); -} - -// VBlank. Fired every single frame. -void nv3_pgraph_vblank_start(svga_t* svga) -{ - nv3_pgraph_interrupt_valid(NV3_PGRAPH_INTR_0_VBLANK); -} - -/* Sends off method execution to the right class */ -void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) -{ - /* Obtain the grobj information from the context in ramin */ - nv3_grobj_t grobj = {0}; - - // we need to shift left by 4 to get the real address, something to do with the 16 byte unit of reversal - uint32_t real_ramin_base = context.ramin_offset << 4; - - // readin our grobj - grobj.grobj_0 = nv3_ramin_read32(real_ramin_base, nv3); - grobj.grobj_1 = nv3_ramin_read32(real_ramin_base + 4, nv3); - grobj.grobj_2 = nv3_ramin_read32(real_ramin_base + 8, nv3); - grobj.grobj_3 = nv3_ramin_read32(real_ramin_base + 12, nv3); - - nv_log_verbose_only("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n", - method, param, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3); - - /* Methods below 0x104 are shared across all classids, so call generic_method for that*/ - if (method <= NV3_SET_NOTIFY) - { - nv3_generic_method(param, method, context, grobj); - } - else - { - // By this point, we already ANDed the class ID to 0x1F. - // Send the grobj, the context, the method and the name off to actually be acted upon. - switch (class_id) - { - case nv3_pgraph_class01_beta_factor: - nv3_class_001_method(param, method, context, grobj); - break; - case nv3_pgraph_class02_rop: - nv3_class_002_method(param, method, context, grobj); - break; - case nv3_pgraph_class03_chroma_key: - nv3_class_003_method(param, method, context, grobj); - break; - case nv3_pgraph_class04_plane_mask: - nv3_class_004_method(param, method, context, grobj); - break; - case nv3_pgraph_class05_clipping_rectangle: - nv3_class_005_method(param, method, context, grobj); - break; - case nv3_pgraph_class06_pattern: - nv3_class_006_method(param, method, context, grobj); - break; - case nv3_pgraph_class07_rectangle: - nv3_class_007_method(param, method, context, grobj); - break; - case nv3_pgraph_class08_point: - nv3_class_008_method(param, method, context, grobj); - break; - case nv3_pgraph_class09_line: - nv3_class_009_method(param, method, context, grobj); - break; - case nv3_pgraph_class0a_lin: - nv3_class_00a_method(param, method, context, grobj); - break; - case nv3_pgraph_class0b_triangle: - nv3_class_00b_method(param, method, context, grobj); - break; - case nv3_pgraph_class0c_w95txt: - nv3_class_00c_method(param, method, context, grobj); - break; - case nv3_pgraph_class0d_m2mf: - nv3_class_00d_method(param, method, context, grobj); - break; - case nv3_pgraph_class0e_scaled_image_from_memory: - nv3_class_00e_method(param, method, context, grobj); - break; - case nv3_pgraph_class10_blit: - nv3_class_010_method(param, method, context, grobj); - break; - case nv3_pgraph_class11_image: - nv3_class_011_method(param, method, context, grobj); - break; - case nv3_pgraph_class12_bitmap: - nv3_class_012_method(param, method, context, grobj); - break; - case nv3_pgraph_class14_transfer2memory: - nv3_class_014_method(param, method, context, grobj); - break; - case nv3_pgraph_class15_stretched_image_from_cpu: - nv3_class_015_method(param, method, context, grobj); - break; - case nv3_pgraph_class17_d3d5tri_zeta_buffer: - nv3_class_017_method(param, method, context, grobj); - break; - case nv3_pgraph_class18_point_zeta_buffer: - nv3_class_018_method(param, method, context, grobj); - break; - case nv3_pgraph_class1c_image_in_memory: - nv3_class_01c_method(param, method, context, grobj); - break; - default: - fatal("NV3 (nv3_pgraph_arbitrate_method): Attempted to execute method on invalid, or unimplemented, class ID %s", nv3_class_names[class_id]); - return; - } - } - - nv3_notify_if_needed(param, method, context, grobj); -} - -/* Arbitrates graphics object submission to the right object types */ -void nv3_pgraph_submit(uint32_t param, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, nv3_ramin_context_t context) -{ - // class id can be derived from the context but we debug log it before we get here - // Do we need to read grobj here? - - switch (method) - { - default: - // Object Method arbitration - nv3_pgraph_arbitrate_method(param, method, channel, subchannel, class_id, context); - break; - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c deleted file mode 100644 index b6528fe0a..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pmc.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PMC - Master control for the chip - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_pmc_init(void) -{ - nv_log("Initialising PMC....\n"); - - if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_A00) - nv3->pmc.boot = NV3_BOOT_REG_REV_A00; - else if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_B00) - nv3->pmc.boot = NV3_BOOT_REG_REV_B00; - else - nv3->pmc.boot = NV3_BOOT_REG_REV_C00; - - nv3->pmc.interrupt_enable = NV3_PMC_INTERRUPT_ENABLE_HARDWARE | NV3_PMC_INTERRUPT_ENABLE_SOFTWARE; - - nv_log("Initialising PMC: Done\n"); -} - -// -// ****** PMC register list START ****** -// - -nv_register_t pmc_registers[] = { - { NV3_PMC_BOOT, "PMC: Boot Manufacturing Information", NULL, NULL }, - { NV3_PMC_INTERRUPT_STATUS, "PMC: Current Pending Subsystem Interrupts", NULL, NULL}, - { NV3_PMC_INTERRUPT_ENABLE, "PMC: Global Interrupt Enable", NULL, NULL,}, - { NV3_PMC_ENABLE, "PMC: Global Subsystem Enable", NULL, NULL }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -void nv3_pmc_clear_interrupts(void) -{ - nv_log_verbose_only("Clearing IRQs\n"); - pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); -} - -// Handle hardware interrupts -// We only clear when we need to, in other functions... -uint32_t nv3_pmc_handle_interrupts(bool send_now) -{ - // TODO: - // PGRAPH DMA INTR_EN (there is no DMA engine yet) - // PRM Real-Mode Compatibility Interrupts - - uint32_t new_intr_value = 0x00; - - // set the new interrupt value - // PAUDIO not used - // IF NV3 REV A EMULATION IS ADDED, ADD THIS COMPONENT! - - // the registers are designed to line up so you can enable specific interrupts - - // Check Mediaport interrupts - if (nv3->pme.interrupt_status & nv3->pme.interrupt_enable) - new_intr_value |= (NV3_PMC_INTERRUPT_PMEDIA_PENDING << NV3_PMC_INTERRUPT_PMEDIA); - - // Check FIFO interrupts - if (nv3->pfifo.interrupt_status & nv3->pfifo.interrupt_enable) - new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO); - - // PFB interrupt is VBLANK PGRAPH interrupt...what nvidia... - if (nv3->pgraph.interrupt_status_0 & (1 << 8) - && nv3->pgraph.interrupt_enable_0 & (1 << 8)) - new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB); - - if (nv3->pgraph.interrupt_status_0 & ~(1 << 8) - && nv3->pgraph.interrupt_enable_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt - new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0); - - // Check second pgraph interrupt register - if (nv3->pgraph.interrupt_status_1 & nv3->pgraph.interrupt_enable_1) - new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH1_PENDING << NV3_PMC_INTERRUPT_PGRAPH1); - - // check video overlay interrupts - if (nv3->pvideo.interrupt_status & nv3->pvideo.interrupt_enable) - new_intr_value |= (NV3_PMC_INTERRUPT_PVIDEO_PENDING << NV3_PMC_INTERRUPT_PVIDEO); - - // check PIT interrupts - if (nv3->ptimer.interrupt_status & nv3->ptimer.interrupt_enable) - new_intr_value |= (NV3_PMC_INTERRUPT_PTIMER_PENDING << NV3_PMC_INTERRUPT_PTIMER); - - // check bus interrupts - if (nv3->pbus.interrupt_status & nv3->pbus.interrupt_enable) - new_intr_value |= (NV3_PMC_INTERRUPT_PBUS_PENDING << NV3_PMC_INTERRUPT_PBUS); - - // check SW interrupts - if (nv3->pmc.interrupt_status & (1 << NV3_PMC_INTERRUPT_SOFTWARE)) - new_intr_value |= (NV3_PMC_INTERRUPT_SOFTWARE_PENDING << NV3_PMC_INTERRUPT_SOFTWARE); - - nv3->pmc.interrupt_status = new_intr_value; - - // ***TODO: DOes INTR still change if INTR_EN=0???*** - // If interrupts are disabled don't bother - - if (!nv3->pmc.interrupt_enable) - { - nv3_pmc_clear_interrupts(); - return nv3->pmc.interrupt_status; - } - - - // if we actually need to send the interrupt (i.e. this is a write) send it now - if (send_now) - { - // no interrupts to send - if (!(nv3->pmc.interrupt_status) - || !(nv3->pmc.interrupt_status - 0x80000000)) - { - nv3_pmc_clear_interrupts(); - return nv3->pmc.interrupt_status; - } - - if ((nv3->pmc.interrupt_status & 0x7FFFFFFF)) - { - if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE) - { - nv_log_verbose_only("Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); - pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); - } - else - nv_log_verbose_only("NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); - } - else - { - if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_SOFTWARE) - { - nv_log_verbose_only("Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status); - pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state); - } - else - nv_log_verbose_only("NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status); - } - } - - return nv3->pmc.interrupt_status; -} - - - -// -// ****** Read/Write functions start ****** -// - -uint32_t nv3_pmc_read(uint32_t address) -{ - nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); - - uint32_t ret = 0x00; - - // todo: friendly logging - nv_log_verbose_only("PMC Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - switch (reg->address) - { - case NV3_PMC_BOOT: - ret = nv3->pmc.boot; - break; - case NV3_PMC_INTERRUPT_STATUS: - nv_log_verbose_only("\n"); // clear_interrupts logs - nv3_pmc_clear_interrupts(); - - ret = nv3_pmc_handle_interrupts(false); - break; - case NV3_PMC_INTERRUPT_ENABLE: - //TODO: ACTUALLY CHANGE THE INTERRUPT STATE - ret = nv3->pmc.interrupt_enable; - break; - case NV3_PMC_ENABLE: - ret = nv3->pmc.enable; - break; - - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pmc_write(uint32_t address, uint32_t value) -{ - nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0])); - - nv_log_verbose_only("PMC Write 0x%08x -> 0x%08x", value, address); - - // if the register actually exists... - if (reg) - { - - // ... call its on-write function - if (reg->on_write) - reg->on_write(value); - else - { - // if it doesn't have one fallback to a switch statement - switch (reg->address) - { - case NV3_PMC_INTERRUPT_STATUS: - // This can only be done by software interrupts... - if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF)) - { - warning("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger " - " an interrupt on, rather than writing to NV3_PMC_INTERRUPT_STATUS (Or this is a bug)...NV3_PMC_INTERRUPT_STATUS=0x%08x)\n", nv3->pmc.interrupt_enable); - return; - } - - nv3_pmc_handle_interrupts(true); - nv3->pmc.interrupt_status = value; - break; - case NV3_PMC_INTERRUPT_ENABLE: - nv3->pmc.interrupt_enable = value & 0x03; - nv3_pmc_handle_interrupts(value != 0); - break; - case NV3_PMC_ENABLE: - nv3->pmc.enable = value; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c deleted file mode 100644 index 1f0da2aac..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pme.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 pme: Nvidia Mediaport - External MPEG Decode Interface - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -nv_register_t pme_registers[] = { - { NV3_PME_INTR, "PME - Interrupt Status", NULL, NULL}, - { NV3_PME_INTR_EN, "PME - Interrupt Enable", NULL, NULL,}, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -void nv3_pme_init(void) -{ - nv_log("Initialising PME..."); - - nv_log("Done\n"); -} - -uint32_t nv3_pme_read(uint32_t address) -{ - nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); - - uint32_t ret = 0x00; - - // todo: friendly logging - - nv_log_verbose_only("PME Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - // Interrupt state: - // Bit 0 - Image Notifier - // Bit 4 - Vertical Blank Interval Notifier - // Bit 8 - Video Notifier - // Bit 12 - Audio Notifier - // Bit 16 - VMI Notifer - switch (reg->address) - { - case NV3_PME_INTR: - ret = nv3->pme.interrupt_status; - break; - case NV3_PME_INTR_EN: - ret = nv3->pme.interrupt_enable; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pme_write(uint32_t address, uint32_t value) -{ - nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0])); - - nv_log_verbose_only("PME Write 0x%08x -> 0x%08x\n", value, address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - // Interrupt state: - // Bit 0 - Image Notifier - // Bit 4 - Vertical Blank Interfal Notifier - // Bit 8 - Video Notifier - // Bit 12 - Audio Notifier - // Bit 16 - VMI Notifer - - case NV3_PME_INTR: - nv3->pme.interrupt_status &= ~value; - nv3_pmc_clear_interrupts(); - break; - case NV3_PME_INTR_EN: - nv3->pme.interrupt_enable = value & 0x00001111; - break; - } - } - - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } - -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c deleted file mode 100644 index 9ce5a189a..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pramdac.c +++ /dev/null @@ -1,458 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 bringup and device emulation. - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -// nv3_pramdac.c: NV3 RAMDAC -// Todo: Allow overridability using 68050C register... - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -void nv3_pramdac_init(void) -{ - nv_log("Initialising PRAMDAC\n"); - - // defaults, these come from vbios in reality - // driver defaults are nonsensical(?), or the algorithm is wrong - // munged this to 100mhz for now - nv3->pramdac.memory_clock_m = nv3->pramdac.pixel_clock_m = 0x07; - nv3->pramdac.memory_clock_n = nv3->pramdac.pixel_clock_n = 0xc8; - nv3->pramdac.memory_clock_p = nv3->pramdac.pixel_clock_p = 0x0c; - - nv3_pramdac_set_pixel_clock(); - nv3_pramdac_set_vram_clock(); - - nv_log("Initialising PRAMDAC: Done\n"); -} - -// Polls the pixel clock. -void nv3_pramdac_pixel_clock_poll(double real_time) -{ - /* Ignore in VGA mode */ - if (!nv3->nvbase.svga.override) - return; - - /* Figure out our refresh time. */ - if (!nv3->nvbase.refresh_time) - nv3->nvbase.refresh_time = (1/60.0); // rivatimers count in microseconds but present the info as seconds - - nv3->nvbase.refresh_clock += real_time; - - if (nv3->nvbase.refresh_clock > nv3->nvbase.refresh_time) - { - /* Update the screen because something changed */ - nv3_render_current_bpp(); - video_blit_memtoscreen(0, 0, xsize, ysize); - nv3->nvbase.refresh_clock = 0; - } - - // TODO: ???? -} - -// Polls the memory clock. -// This updates the 2D/3D engine PGRAPH, PTIMER and more -void nv3_pramdac_memory_clock_poll(double real_time) -{ - nv3_ptimer_tick(real_time); - - nv3_pfifo_cache0_pull(); - nv3_pfifo_cache1_pull(); - // TODO: UPDATE PGRAPH! -} - -// Gets the vram clock register. -uint32_t nv3_pramdac_get_vram_clock_register(void) -{ - // the clock format is packed into 19 bits - // M divisor [7-0] - // N divisor [16-8] - // P divisor [18-16] - return (nv3->pramdac.memory_clock_m) - + (nv3->pramdac.memory_clock_n << 8) - + (nv3->pramdac.memory_clock_p << 16); // 0-3 -} - -uint32_t nv3_pramdac_get_pixel_clock_register(void) -{ - return (nv3->pramdac.pixel_clock_m) - + (nv3->pramdac.pixel_clock_n << 8) - + (nv3->pramdac.pixel_clock_p << 16); // 0-3 -} - -void nv3_pramdac_set_vram_clock_register(uint32_t value) -{ - nv3->pramdac.memory_clock_m = value & 0xFF; - nv3->pramdac.memory_clock_n = (value >> 8) & 0xFF; - nv3->pramdac.memory_clock_p = (value >> 16) & 0x07; - - nv3_pramdac_set_vram_clock(); -} - -void nv3_pramdac_set_pixel_clock_register(uint32_t value) -{ - nv3->pramdac.pixel_clock_m = value & 0xFF; - nv3->pramdac.pixel_clock_n = (value >> 8) & 0xFF; - nv3->pramdac.pixel_clock_p = (value >> 16) & 0x07; - - nv3_pramdac_set_pixel_clock(); -} - -void nv3_pramdac_set_vram_clock(void) -{ - // from driver and vbios source - float frequency = 13500000.0f; - - // prevent division by 0 - if (nv3->pramdac.memory_clock_m == 0) - nv3->pramdac.memory_clock_m = 1; - - if (nv3->pramdac.memory_clock_n == 0) - nv3->pramdac.memory_clock_n = 1; - - // Convert to microseconds - frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p); - - double time = 1000000.0 / (double)frequency; // needs to be a double for 86box - - nv_log("Memory clock = %.2f MHz\n", frequency / 1000000.0f); - - nv3->nvbase.memory_clock_frequency = frequency; - - // Create and start if it it's not running. - if (!nv3->nvbase.memory_clock_timer) - { - nv3->nvbase.memory_clock_timer = rivatimer_create(time, nv3_pramdac_memory_clock_poll); - rivatimer_start(nv3->nvbase.memory_clock_timer); - } - - rivatimer_set_period(nv3->nvbase.memory_clock_timer, time); -} - -void nv3_pramdac_set_pixel_clock(void) -{ - // frequency divider algorithm from old varcem/86box/pcbox riva driver, - // verified by reversing NT drivers v1.50e CalcMNP [symbols] function - - // missing section - // not really needed. - // if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500) - // { - // freq = 13500000.0f; - // } - // else - // - // { - // freq = 14318000.0f; - // } - - float frequency = 13500000.0f; - - // prevent division by 0 - if (nv3->pramdac.pixel_clock_m == 0) - nv3->pramdac.pixel_clock_m = 1; - - if (nv3->pramdac.memory_clock_n == 0) - nv3->pramdac.memory_clock_n = 1; - - frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p); - - nv3->nvbase.svga.clock = cpuclock / frequency; - - double time = 1000000.0 / (double)frequency; // needs to be a double for 86box - - nv_log("Pixel clock = %.2f MHz\n", frequency / 1000000.0f); - - nv3->nvbase.pixel_clock_frequency = frequency; - - // Create and start if it it's not running. - if (!nv3->nvbase.pixel_clock_timer) - { - nv3->nvbase.pixel_clock_timer = rivatimer_create(time, nv3_pramdac_pixel_clock_poll); - rivatimer_start(nv3->nvbase.pixel_clock_timer); - } - - rivatimer_set_period(nv3->nvbase.pixel_clock_timer, time); -} - -// -// ****** PRAMDAC register list START ****** -// - -// NULL means handle in read functions -nv_register_t pramdac_registers[] = -{ - { NV3_PRAMDAC_CURSOR_START, "PRAMDAC - Cursor Start Position"}, - { NV3_PRAMDAC_CLOCK_PIXEL, "PRAMDAC - NV3 GPU Core - Pixel clock", nv3_pramdac_get_pixel_clock_register, nv3_pramdac_set_pixel_clock_register }, - { NV3_PRAMDAC_CLOCK_MEMORY, "PRAMDAC - NV3 GPU Core - Memory clock", nv3_pramdac_get_vram_clock_register, nv3_pramdac_set_vram_clock_register }, - { NV3_PRAMDAC_COEFF_SELECT, "PRAMDAC - PLL Clock Coefficient Select", NULL, NULL}, - { NV3_PRAMDAC_GENERAL_CONTROL, "PRAMDAC - General Control", NULL, NULL }, - { NV3_PRAMDAC_VSERR_WIDTH, "PRAMDAC - Vertical Sync Error Width", NULL, NULL}, - { NV3_PRAMDAC_VEQU_END, "PRAMDAC - VEqu End", NULL, NULL}, - { NV3_PRAMDAC_VBBLANK_START, "PRAMDAC - VBBlank Start", NULL, NULL}, - { NV3_PRAMDAC_VBBLANK_END, "PRAMDAC - VBBlank End", NULL, NULL}, - { NV3_PRAMDAC_HBLANK_END, "PRAMDAC - Horizontal Blanking Interval End", NULL, NULL}, - { NV3_PRAMDAC_HBLANK_START, "PRAMDAC - Horizontal Blanking Interval Start", NULL, NULL}, - { NV3_PRAMDAC_VBLANK_END, "PRAMDAC - Vertical Blanking Interval End", NULL, NULL}, - { NV3_PRAMDAC_VBLANK_START, "PRAMDAC - Vertical Blanking Interval Start", NULL, NULL}, - { NV3_PRAMDAC_VEQU_START, "PRAMDAC - VEqu Start", NULL, NULL}, - { NV3_PRAMDAC_VTOTAL, "PRAMDAC - Total Vertical Lines", NULL, NULL}, - { NV3_PRAMDAC_HSYNC_WIDTH, "PRAMDAC - Horizontal Sync Pulse Width", NULL, NULL}, - { NV3_PRAMDAC_HBURST_START, "PRAMDAC - Horizontal Burst Signal Start", NULL, NULL}, - { NV3_PRAMDAC_HBURST_END, "PRAMDAC - Horizontal Burst Signal Start", NULL, NULL}, - { NV3_PRAMDAC_HTOTAL, "PRAMDAC - Total Horizontal Lines", NULL, NULL}, - { NV3_PRAMDAC_HEQU_WIDTH, "PRAMDAC - HEqu End", NULL, NULL}, - { NV3_PRAMDAC_HSERR_WIDTH, "PRAMDAC - Horizontal Sync Error", NULL, NULL}, - { NV3_USER_DAC_PIXEL_MASK, "PRAMDAC - User DAC Pixel Mask", NULL, NULL}, - { NV3_USER_DAC_READ_MODE_ADDRESS, "PRAMDAC - User DAC Read Mode Address", NULL, NULL}, - { NV3_USER_DAC_WRITE_MODE_ADDRESS, "PRAMDAC - User DAC Write Mode Address", NULL, NULL}, - { NV3_USER_DAC_PALETTE_DATA, "PRAMDAC - User DAC Palette Data", NULL, NULL}, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -// -// ****** Read/Write functions start ****** -// - -uint32_t nv3_pramdac_read(uint32_t address) -{ - nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); - - uint32_t ret = 0x00; - - // todo: friendly logging - - nv_log_verbose_only("PRAMDAC Read from 0x%08x\n", address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - //s hould be pretty easy to understand - switch (reg->address) - { - case NV3_PRAMDAC_COEFF_SELECT: - ret = nv3->pramdac.coeff_select; - break; - case NV3_PRAMDAC_GENERAL_CONTROL: - ret = nv3->pramdac.general_control; - break; - case NV3_PRAMDAC_VSERR_WIDTH: - ret = nv3->pramdac.vserr_width; - break; - case NV3_PRAMDAC_VBBLANK_END: - ret = nv3->pramdac.vbblank_end; - break; - case NV3_PRAMDAC_VBLANK_END: - ret = nv3->pramdac.vblank_end; - break; - case NV3_PRAMDAC_VBLANK_START: - ret = nv3->pramdac.vblank_start; - break; - case NV3_PRAMDAC_VEQU_START: - ret = nv3->pramdac.vequ_start; - break; - case NV3_PRAMDAC_VTOTAL: - ret = nv3->pramdac.vtotal; - break; - case NV3_PRAMDAC_HSYNC_WIDTH: - ret = nv3->pramdac.hsync_width; - break; - case NV3_PRAMDAC_HBURST_START: - ret = nv3->pramdac.hburst_start; - break; - case NV3_PRAMDAC_HBURST_END: - ret = nv3->pramdac.hburst_end; - break; - case NV3_PRAMDAC_HBLANK_START: - ret = nv3->pramdac.hblank_start; - break; - case NV3_PRAMDAC_HBLANK_END: - ret = nv3->pramdac.hblank_end; - break; - case NV3_PRAMDAC_HTOTAL: - ret = nv3->pramdac.htotal; - break; - case NV3_PRAMDAC_HEQU_WIDTH: - ret = nv3->pramdac.hequ_width; - break; - case NV3_PRAMDAC_HSERR_WIDTH: - ret = nv3->pramdac.hserr_width; - break; - case NV3_USER_DAC_PIXEL_MASK: - ret = nv3->pramdac.user_pixel_mask; - break; - case NV3_USER_DAC_READ_MODE_ADDRESS: - ret = nv3->pramdac.user_read_mode_address; - break; - case NV3_USER_DAC_WRITE_MODE_ADDRESS: - ret = nv3->pramdac.user_write_mode_address; - break; - case NV3_USER_DAC_PALETTE_DATA: - /* I doubt NV actually read this in their drivers, but it's worth doing anyway */ - /* Bit 1 is listed as "read or write mode" and 7:0 as "Write-only address", but NV only ever set this to 0 too, so i think this should be fine for now */ - ret = nv3->pramdac.palette[nv3->pramdac.user_read_mode_address]; - nv3->pramdac.user_read_mode_address++; - break; - case NV3_PRAMDAC_CURSOR_START: - ret = (nv3->pramdac.cursor_start.y << 16) | nv3->pramdac.cursor_start.x; - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pramdac_write(uint32_t address, uint32_t value) -{ - nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0])); - - nv_log_verbose_only("PRAMDAC Write 0x%08x -> 0x%08x\n", value, address); - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - //s hould be pretty easy to understand - // we also update the SVGA state here - switch (reg->address) - { - case NV3_PRAMDAC_COEFF_SELECT: - nv3->pramdac.coeff_select = value; - break; - case NV3_PRAMDAC_GENERAL_CONTROL: - nv3->pramdac.general_control = value; - nv3_recalc_timings(&nv3->nvbase.svga); - break; - case NV3_PRAMDAC_VSERR_WIDTH: - //vslines? - nv3->pramdac.vserr_width = value; - break; - case NV3_PRAMDAC_VBBLANK_END: - nv3->pramdac.vbblank_end = value; - break; - case NV3_PRAMDAC_VBLANK_END: - nv3->pramdac.vblank_end = value; - break; - case NV3_PRAMDAC_VBLANK_START: - //nv3->nvbase.svga.vblankstart = value; - nv3->pramdac.vblank_start = value; - break; - case NV3_PRAMDAC_VEQU_START: - nv3->pramdac.vequ_start = value; - break; - case NV3_PRAMDAC_VTOTAL: - //nv3->pramdac.vtotal = value; - nv3->nvbase.svga.vtotal = value; - break; - case NV3_PRAMDAC_HSYNC_WIDTH: - nv3->pramdac.hsync_width = value; - break; - case NV3_PRAMDAC_HBURST_START: - nv3->pramdac.hburst_start = value; - break; - case NV3_PRAMDAC_HBURST_END: - nv3->pramdac.hburst_end = value; - break; - case NV3_PRAMDAC_HBLANK_START: - //nv3->nvbase.svga.hblankstart = value; - nv3->pramdac.hblank_start = value; - break; - case NV3_PRAMDAC_HBLANK_END: - //nv3->nvbase.svga.hblank_end_val = value; - nv3->pramdac.hblank_end = value; - break; - case NV3_PRAMDAC_HTOTAL: - nv3->pramdac.htotal = value; - //nv3->nvbase.svga.htotal = value; - break; - case NV3_PRAMDAC_HEQU_WIDTH: - nv3->pramdac.hequ_width = value; - break; - case NV3_PRAMDAC_HSERR_WIDTH: - nv3->pramdac.hserr_width = value; - break; - case NV3_USER_DAC_PIXEL_MASK: - nv3->pramdac.user_pixel_mask = value; - break; - case NV3_USER_DAC_READ_MODE_ADDRESS: - nv3->pramdac.user_read_mode_address = value; - break; - case NV3_USER_DAC_WRITE_MODE_ADDRESS: - /* - This seems to get reset to 0 after 256 writes, but, the palette is 768 bytes in size. - Clearly there's some mechanism here, but I'm not sure what it is. So let's just reset if we reach 768. - */ - if (nv3->pramdac.user_write_mode_address >= NV3_USER_DAC_PALETTE_SIZE) - nv3->pramdac.user_write_mode_address = value; - - break; - case NV3_USER_DAC_PALETTE_DATA: - /* I doubt NV actually read this in their drivers, but it's worth doing anyway */ - /* Bit 1 is listed as "read or write mode" and 7:0 as "Write-only address", but NV only ever set this to 0 too, so i think this should be fine for now */ - nv3->pramdac.palette[nv3->pramdac.user_write_mode_address] = value; - - nv3->pramdac.user_write_mode_address++; - - break; - /* cursor start location */ - case NV3_PRAMDAC_CURSOR_START: - // only 12 bits are used here instead of 16 for some stupid reason - nv3->pramdac.cursor_start.y = (value >> 16) & 0xFFF; - nv3->pramdac.cursor_start.x = (value) & 0xFFF; - nv3_draw_cursor(&nv3->nvbase.svga, 0);//drawline doesn't matter here - break; - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} - diff --git a/src/video/nv/nv3/subsystems/nv3_pramin.c b/src/video/nv/nv3/subsystems/nv3_pramin.c deleted file mode 100644 index 77e2d1a6a..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pramin.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PRAMIN - Basically, this is how we know what to render. - * Has a giant hashtable of all the submitted DMA objects using a pseudo-C++ class system - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> - -// Functions only used in this translation unit -#ifndef RELEASE_BUILD -void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context); -#endif - -// i believe the main loop is to walk the hashtable in RAMIN (last 0.5 MB of VRAM), -// find the objects that were submitted from DMA -// (going from software -> nvidia d3d / ogl implementation -> resource manager client -> nvapi -> nvrm -> GPU PFIFO -> GPU PBUS -> GPU PFB RAMIN -> PGRAPH) -// and then rendering each of those using PGRAPH - -// Notes for all of these functions: -// Structures in RAMIN are stored from the bottom of vram up in reverse order -// this can be explained without bitwise math like so: -// real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) -// reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) - -// Read 8-bit ramin -uint8_t nv3_ramin_read8(uint32_t addr, void* priv) -{ - if (!nv3) return 0x00; - - addr &= (nv3->nvbase.svga.vram_max - 1); - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv3->nvbase.svga.vram_max - 0x10); - - uint32_t val = 0x00; - - if (!nv3_ramin_arbitrate_read(addr, &val)) // Oh well - { - val = (uint8_t)nv3->nvbase.svga.vram[addr]; - nv_log_verbose_only("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); - } - - return (uint8_t)val; -} - -// Read 16-bit ramin -uint16_t nv3_ramin_read16(uint32_t addr, void* priv) -{ - if (!nv3) return 0x00; - - addr &= (nv3->nvbase.svga.vram_max - 1); - - // why does this not work in one line - svga_t* svga = &nv3->nvbase.svga; - uint16_t* vram_16bit = (uint16_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv3->nvbase.svga.vram_max - 0x10); - addr >>= 1; // what - - uint32_t val = 0x00; - - if (!nv3_ramin_arbitrate_read(addr, &val)) - { - val = (uint16_t)vram_16bit[addr]; - nv_log_verbose_only("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); - } - - return val; -} - -// Read 32-bit ramin -uint32_t nv3_ramin_read32(uint32_t addr, void* priv) -{ - if (!nv3) - return 0x00; - - addr &= (nv3->nvbase.svga.vram_max - 1); - - // why does this not work in one line - uint32_t* vram_32bit = (uint32_t*)nv3->nvbase.svga.vram; - uint32_t raw_addr = addr; // saved after and logged - - addr ^= (nv3->nvbase.svga.vram_max - 0x10); - addr >>= 2; // what - - uint32_t val = 0x00; - - if (!nv3_ramin_arbitrate_read(addr, &val)) - { - val = vram_32bit[addr]; - - nv_log_verbose_only("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr); - } - - return val; -} - -// Write 8-bit ramin -void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv) -{ - if (!nv3) return; - - addr &= (nv3->nvbase.svga.vram_max - 1); - uint32_t raw_addr = addr; // saved after and - - // Structures in RAMIN are stored from the bottom of vram up in reverse order - // this can be explained without bitwise math like so: - // real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) - // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv3t only and 2mb...i haven't found a 22mb card) - addr ^= (nv3->nvbase.svga.vram_max - 0x10); - - uint32_t val32 = (uint32_t)val; - - if (!nv3_ramin_arbitrate_write(addr, val32)) - { - nv3->nvbase.svga.vram[addr] = val; - nv_log_verbose_only("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); - } - - -} - -// Write 16-bit ramin -void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv) -{ - if (!nv3) return; - - addr &= (nv3->nvbase.svga.vram_max - 1); - - // why does this not work in one line - svga_t* svga = &nv3->nvbase.svga; - uint16_t* vram_16bit = (uint16_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv3->nvbase.svga.vram_max - 0x10); - addr >>= 1; // what - - uint32_t val32 = (uint32_t)val; - - if (!nv3_ramin_arbitrate_write(addr, val32)) - { - vram_16bit[addr] = val; - nv_log_verbose_only("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); - } - - -} - -// Write 32-bit ramin -void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv) -{ - if (!nv3) return; - - addr &= (nv3->nvbase.svga.vram_max - 1); - - // why does this not work in one line - svga_t* svga = &nv3->nvbase.svga; - uint32_t* vram_32bit = (uint32_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv3->nvbase.svga.vram_max - 0x10); - addr >>= 2; // what - - if (!nv3_ramin_arbitrate_write(addr, val)) - { - vram_32bit[addr] = val; - nv_log_verbose_only("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); - } - -} - -void nv3_pfifo_interrupt(uint32_t id, bool fire_now) -{ - nv3->pfifo.interrupt_status |= (1 << id); - nv3_pmc_handle_interrupts(fire_now); -} - -/* -RAMIN access arbitration functions -Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) unused audio memory (RAMAU?) -and generic RAMIN - -Takes a pointer to a result integer. This is because we need to check its result in our normal write function. -Returns true if a valid "non-generic" address was found (e.g. RAMFC/RAMRO/RAMHT). False if the specified address is a generic RAMIN address -*/ -bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value) -{ - if (!nv3) return 0x00; - - uint32_t ramht_size = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03); - uint32_t ramro_size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - - // Get the addresses of RAMHT, RAMFC, RAMRO - // They must be within first 64KB of PRAMIN! - uint32_t ramht_start = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12; // Must be 0x1000 aligned - uint32_t ramfc_start = ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned - uint32_t ramro_start = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned - - // Calculate the RAMHT and RAMRO end points. - // (RAMFC is always 0x1000 bytes on NV3.) - uint32_t ramht_end = ramht_start; - uint32_t ramfc_end = ramfc_start + 0x1000; - uint32_t ramro_end = ramro_start; - - switch (ramht_size) - { - case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_0; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_1; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_2; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_3; - break; - } - - switch (ramro_size) - { - case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B: - ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_0; - break; - case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K: - ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_1; - break; - } - - if (address >= ramht_start - && address <= ramht_end) - { - *value = nv3_ramht_read(address); - return true; - } - else if (address >= ramfc_start - && address <= ramfc_end) - { - *value = nv3_ramfc_read(address); - return true; - } - else if (address >= ramro_start - && address <= ramro_end) - { - *value = nv3_ramro_read(address); - return true; - } - - /* temp */ - return false; -} - -bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value) -{ - if (!nv3) return 0x00; - - uint32_t ramht_size = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03); - uint32_t ramro_size = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_SIZE) & 0x01); - - // Get the addresses of RAMHT, RAMFC, RAMRO - // They must be within first 64KB of PRAMIN! - uint32_t ramht_start = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << 12; // Must be 0x1000 aligned - uint32_t ramfc_start = ((nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned - uint32_t ramro_start = ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9; // Must be 0x200 aligned - - // Calculate the RAMHT and RAMRO end points. - // (RAMFC is always 0x1000 bytes on NV3.) - uint32_t ramht_end = ramht_start; - uint32_t ramfc_end = ramfc_start + 0x1000; - uint32_t ramro_end = ramro_start; - - switch (ramht_size) - { - case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_0; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_1; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_2; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: - ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_3; - break; - } - - switch (ramro_size) - { - case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B: - ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_0; - break; - case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K: - ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_1; - break; - } - - // send the addresses to the right part - if (address >= ramht_start - && address <= ramht_end) - { - nv3_ramht_write(address, value); - return true; - } - else if (address >= ramfc_start - && address <= ramfc_end) - { - nv3_ramfc_write(address, value); - return true; - } - else if (address >= ramro_start - && address <= ramro_end) - { - nv3_ramro_write(address, value); - return true; - } - - return false; -} - -// THIS IS THE MOST IMPORTANT FUNCTION! -bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, uint8_t subchannel) -{ - // TODO: WRITE IT!!! - // Set the number of entries to search based on the ramht size (2*(size+1)) - // Not a switch statement in case newer gpus have larger ramins - - uint32_t bucket_entries = 2; - uint8_t ramht_size = (nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03; - - switch (ramht_size) - { - case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K: - // stays as is - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K: - bucket_entries = 4; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K: - bucket_entries = 8; - break; - case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K: - bucket_entries = 16; - break; - - } - - // Calculate the address in the hashtable - uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS; - - // This is certainly wrong. But the objects seem to be written to 4600? So I just multiply it by 80 to multiply the final address by 10. - // Why does this work? - uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel) * bucket_entries * 8); - - nv_log_verbose_only("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n", - ramht_cur_address, name, cache_num, channel, subchannel); - - bool found_object = false; - - // set up some variables - uint32_t found_obj_name = 0x00; - nv3_ramin_context_t obj_context_struct = {0}; - - for (uint32_t bucket_entry = 0; bucket_entry < bucket_entries; bucket_entry++) - { - found_obj_name = nv3_ramin_read32(ramht_cur_address, NULL); - ramht_cur_address += 0x04; - uint32_t obj_context = nv3_ramin_read32(ramht_cur_address, NULL); - ramht_cur_address += 0x04; - obj_context_struct = *(nv3_ramin_context_t*)&obj_context; - - // see if the object is in the right channel - if (found_obj_name == name - && obj_context_struct.channel == channel) - { - found_object = true; - break; - } - } - - if (!found_object) - { - if (!cache_num) - { - nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING; - nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_HASH_FAILURE; - //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; - } - else - { - nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING; - nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; - //It turns itself off on failure, the drivers turn it back on - nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; - } - - nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); - - return false; - } - - // So we did find an object. - // Now try to read some of this... - - // Class ID is 5 bits in all other parts of the gpu but 7 bits here. A move in a direction that didn't pan out? - // Represented as 0x40-0x5f? Some other meaning - - // Perform more validation - - if (obj_context_struct.class_id < NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID - || obj_context_struct.class_id > NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID) - { - fatal("NV3: Invalid graphics object class ID name=0x%04x type=%04x, interpreted by pgraph as: %04x (Contact starfrost)", - name, obj_context_struct.class_id, obj_context_struct.class_id & 0x1F); - } - else if (obj_context_struct.channel > (NV3_DMA_CHANNELS - 1)) - fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-7", obj_context_struct.channel); - - // Illegal accesses sent to RAMRO, so ignore here - // TODO: SEND THESE TO RAMRO!!!!! - - #ifndef RELEASE_BUILD - nv3_debug_ramin_print_context_info(name, obj_context_struct); - #endif - - // By definition we can't have a cache error by here so take it off - if (!cache_num) - nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_HASH_FAILURE; - else - nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_HASH_FAILURE; - - // Caches store all the subchannels for our current dma channel and basically get stale every context switch - // Also we have to check that a osftware object didn't end up in here... - - bool is_software = false; - if (!cache_num) - is_software = (nv3->pfifo.cache0_settings.context[subchannel] & 0x800000); - else - is_software = (nv3->pfifo.cache1_settings.context[subchannel] & 0x800000); - - // This isn't an error but it's sent as an interrupt so the drivers can sync - if (is_software) - { - // handle it as an error - if (!cache_num) - { - nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED; - } - else - { - nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; - nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_ENABLED; - } - - // It's an error but it isn't lol - nv3_pfifo_interrupt(NV3_PFIFO_INTR_CACHE_ERROR, true); - - } - else - { - // obviously turn off the "is software" if it's not - if (!cache_num) - nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD; - else - nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE1_PULL0_SOFTWARE_METHOD; - } - - // Ok we found it. Lol - return true; - -} - - -// Prints out some informaiton about the object -void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context) -{ - #ifndef RELEASE_BUILD - nv_log_verbose_only("Found object:\n"); - nv_log_verbose_only("Param: 0x%04x\n", name); - - nv_log_verbose_only("Context:\n"); - nv_log_verbose_only("DMA Channel %d (0-7 valid)\n", context.channel); - nv_log_verbose_only("Class ID: 0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]); - nv_log_verbose_only("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering); - nv_log_verbose_only("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4); - #endif -} diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c deleted file mode 100644 index 59fa41e8d..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PFIFO RAMFC area: Stores context for unused DMA channels - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -uint32_t nv3_ramfc_read(uint32_t address) -{ - nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x) (UNIMPLEMENTED returning 0x00)\n", address); - return 0x00; //temp -} - -void nv3_ramfc_write(uint32_t address, uint32_t value) -{ - nv_log_verbose_only("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x)\n", value, address); -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c deleted file mode 100644 index 9f90b3434..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramht.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PFIFO hashtable (Quickly access submitted DMA objects) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -/* This implements the hash that all the objects are stored within. -It is used to get the offset within RAMHT of a graphics object. - */ - -uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel) -{ - // the official nvidia hash algorithm, tweaked for readability - uint32_t hash = ((name ^ (name >> 8) ^ (name >> 16) ^ (name >> 24)) & 0xFF) ^ (channel & NV3_DMA_CHANNELS_TOTAL); - - - // is this the right endianness? - nv_log_verbose_only("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel); - return hash; -} - - -uint32_t nv3_ramht_read(uint32_t address) -{ - nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address); - return 0x00; -} - -void nv3_ramht_write(uint32_t address, uint32_t value) -{ - nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - UNIMPLEMENTED\n", value, address); -} diff --git a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c b/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c deleted file mode 100644 index 142d746d2..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pramin_ramro.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PFIFO ram runout area (you fucked up) - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - -uint32_t nv3_ramro_read(uint32_t address) -{ - nv_log("BIG Problem: RAM Runout (invalid dma object submission) Read (0x%04x)\n", address); - return 0x00; -} - -void nv3_ramro_write(uint32_t address, uint32_t value) -{ - nv_log("BIG Problem: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x)", value, address); -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c deleted file mode 100644 index ab14be4f9..000000000 --- a/src/video/nv/nv3/subsystems/nv3_ptimer.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PTIMER - PIT emulation - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - - -nv_register_t ptimer_registers[] = { - { NV3_PTIMER_INTR, "PTIMER - Interrupt Status", NULL, NULL}, - { NV3_PTIMER_INTR_EN, "PTIMER - Interrupt Enable", NULL, NULL,}, - { NV3_PTIMER_NUMERATOR, "PTIMER - Numerator", NULL, NULL, }, - { NV3_PTIMER_DENOMINATOR, "PTIMER - Denominator", NULL, NULL, }, - { NV3_PTIMER_TIME_0_NSEC, "PTIMER - Time0", NULL, NULL, }, - { NV3_PTIMER_TIME_1_NSEC, "PTIMER - Time1", NULL, NULL, }, - { NV3_PTIMER_ALARM_NSEC, "PTIMER - Alarm", NULL, NULL, }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -// ptimer init code -void nv3_ptimer_init(void) -{ - nv_log("Initialising PTIMER..."); - - nv_log("Done!\n"); -} - -// Handles the PTIMER alarm interrupt -void nv3_ptimer_interrupt(uint32_t num) -{ - nv3->ptimer.interrupt_status |= (1 << num); - - nv3_pmc_handle_interrupts(true); -} - -// Ticks the timer. -void nv3_ptimer_tick(double real_time) -{ - // prevent a divide by zero - if (nv3->ptimer.clock_numerator == 0 - || nv3->ptimer.clock_denominator == 0) - return; - - // get the current time - - // See Envytools. We need to use the frequency as a source. - // We need to figure out how many cycles actually occurred because this counts up every cycle... - // However it seems that their formula is wrong. I can't be bothered to figure out what's going on and, based on documentation from NVIDIA, - // timer_0 is meant to roll over every 4 seconds. Multiplying by 10 basically does the job. - - // Convert to microseconds - double freq_base = (real_time / 1000000.0f) / ((double)1.0 / nv3->nvbase.memory_clock_frequency) * 10.0f; - double current_time = freq_base * ((double)nv3->ptimer.clock_numerator) / (double)nv3->ptimer.clock_denominator; // *10.0? - - // truncate it - nv3->ptimer.time += (uint64_t)current_time; - - // Check if the alarm has actually triggered.. - // Only log on ptimer alarm. Otherwise, it's too much spam. - if (nv3->ptimer.time >= nv3->ptimer.alarm) - { - nv_log_verbose_only("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm); - nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM); - } -} - -uint32_t nv3_ptimer_read(uint32_t address) -{ - // always enabled - - nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - - // Only log these when tehy actually tick - if (address != NV3_PTIMER_TIME_0_NSEC - && address != NV3_PTIMER_TIME_1_NSEC) - { - nv_log_verbose_only("PTIMER Read from 0x%08x", address); - } - - uint32_t ret = 0x00; - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - // Interrupt state: - // Bit 0: Alarm - - switch (reg->address) - { - case NV3_PTIMER_INTR: - ret = nv3->ptimer.interrupt_status; - break; - case NV3_PTIMER_INTR_EN: - ret = nv3->ptimer.interrupt_enable; - break; - case NV3_PTIMER_NUMERATOR: - ret = nv3->ptimer.clock_numerator; // 15:0 - break; - case NV3_PTIMER_DENOMINATOR: - ret = nv3->ptimer.clock_denominator ; //15:0 - break; - // 64-bit value - // High part - case NV3_PTIMER_TIME_0_NSEC: - ret = nv3->ptimer.time & 0xFFFFFFFF; //28:0 - break; - // Low part - case NV3_PTIMER_TIME_1_NSEC: - ret = nv3->ptimer.time >> 32; // 31:5 - break; - case NV3_PTIMER_ALARM_NSEC: - ret = nv3->ptimer.alarm; // 31:5 - break; - } - - } - //TIME0 and TIME1 produce too much log spam that slows everything down - if (reg->address != NV3_PTIMER_TIME_0_NSEC - && reg->address != NV3_PTIMER_TIME_1_NSEC) - { - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_ptimer_write(uint32_t address, uint32_t value) -{ - // before doing anything, check the subsystem enablement - nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - - nv_log_verbose_only("PTIMER Write 0x%08x -> 0x%08x", value, address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - // Interrupt state: - // Bit 0 - Alarm - - case NV3_PTIMER_INTR: - nv3->ptimer.interrupt_status &= ~value; - nv3_pmc_clear_interrupts(); - break; - - // Interrupt enablement state - case NV3_PTIMER_INTR_EN: - nv3->ptimer.interrupt_enable = value & 0x1; - break; - // nUMERATOR - case NV3_PTIMER_NUMERATOR: - nv3->ptimer.clock_numerator = value & 0xFFFF; // 15:0 - break; - case NV3_PTIMER_DENOMINATOR: - // prevent Div0 - if (!value) - value = 1; - - nv3->ptimer.clock_denominator = value & 0xFFFF; //15:0 - break; - // 64-bit value - // High part - case NV3_PTIMER_TIME_0_NSEC: - nv3->ptimer.time |= (value) & 0xFFFFFFE0; //28:0 - break; - // Low part - case NV3_PTIMER_TIME_1_NSEC: - nv3->ptimer.time |= ((uint64_t)(value & 0xFFFFFFE0) << 32); // 31:5 - break; - case NV3_PTIMER_ALARM_NSEC: - nv3->ptimer.alarm = value & 0xFFFFFFE0; // 31:5 - break; - } - } - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c deleted file mode 100644 index 60019b9c6..000000000 --- a/src/video/nv/nv3/subsystems/nv3_pvideo.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 PVIDEO - Video Overlay - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - - -nv_register_t pvideo_registers[] = { - { NV3_PVIDEO_INTR, "PVIDEO - Interrupt Status", NULL, NULL}, - { NV3_PVIDEO_INTR_EN, "PVIDEO - Interrupt Enable", NULL, NULL,}, - { NV3_PVIDEO_FIFO_THRESHOLD, "PVIDEO - FIFO Fill Threshold", NULL, NULL}, - { NV3_PVIDEO_FIFO_BURST_LENGTH, "PVIDEO - FIFO Burst Length (1=32, 2=64, 3=128)", NULL, NULL}, - { NV3_PVIDEO_OVERLAY, "PVIDEO - Overlay Info (Bit0 = Video On, Bit4 = Key On, Bit8 = Format, 0=CCIR, 1=YUV2)", NULL, NULL }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -// ptimer init code -void nv3_pvideo_init(void) -{ - nv_log("Initialising PVIDEO..."); - - nv_log("Done!\n"); -} - -uint32_t nv3_pvideo_read(uint32_t address) -{ - // before doing anything, check the subsystem enablement - - nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); - uint32_t ret = 0x00; - - // todo: friendly logging - - nv_log_verbose_only("PVIDEO Read from 0x%08x", address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - // Interrupt state: - // Bit 0 - Notifier - - switch (reg->address) - { - case NV3_PVIDEO_INTR: - ret = nv3->pvideo.interrupt_status; - break; - case NV3_PVIDEO_INTR_EN: - ret = nv3->pvideo.interrupt_enable; - break; - case NV3_PVIDEO_FIFO_THRESHOLD: - ret = nv3->pvideo.fifo_threshold; - break; - case NV3_PVIDEO_FIFO_BURST_LENGTH: - ret = nv3->pvideo.fifo_burst_size & 0x03; - break; - case NV3_PVIDEO_OVERLAY: - ret = nv3->pvideo.overlay_settings & 0xFF; - break; - - } - } - - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv3_pvideo_write(uint32_t address, uint32_t value) -{ - // before doing anything, check the subsystem enablement - nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0])); - - nv_log_verbose_only("PVIDEO Write 0x%08x -> 0x%08x\n", value, address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - // Interrupt state: - // Bit 0 - Notifier - - case NV3_PVIDEO_INTR: - nv3->pvideo.interrupt_status &= ~value; - nv3_pmc_clear_interrupts(); - break; - case NV3_PVIDEO_INTR_EN: - nv3->pvideo.interrupt_enable = value & 0x00000001; - break; - case NV3_PVIDEO_FIFO_THRESHOLD: - // only bits 6:3 matter - nv3->pvideo.fifo_threshold = ((value >> 3) & 0x0F) << 3; - break; - case NV3_PVIDEO_FIFO_BURST_LENGTH: - nv3->pvideo.fifo_burst_size = value & 0x03; - break; - case NV3_PVIDEO_OVERLAY: - nv3->pvideo.overlay_settings = value & 0xFF; - break; - } - } - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} \ No newline at end of file diff --git a/src/video/nv/nv3/subsystems/nv3_user.c b/src/video/nv/nv3/subsystems/nv3_user.c deleted file mode 100644 index f10e28793..000000000 --- a/src/video/nv/nv3/subsystems/nv3_user.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV3 User Submission Area (NV_USER, conceptually considered "Cache1 Pusher") - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv3.h> - - -// PIO Method Submission -// 128 channels conceptually supported - a hangover from nv1 where multiple windows all directly programming the gpu were supported? total lunacy. -uint32_t nv3_user_read(uint32_t address) -{ - // Get the address within the subchannel - //todo: print out the subchannel - uint8_t method_offset = (address & 0x1FFC); - - uint8_t channel = (address - NV3_USER_START) / 0x10000; - uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL; - - nv_log_verbose_only("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset); - - // 0x10 is free CACHE1 object - // TODO: THERE ARE OTHER STUFF! - switch (method_offset) - { - case NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE: - return nv3_pfifo_cache1_num_free_spaces(); - case NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START ... NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END: - return 0x00; - - } - - nv_log("NV_USER READ: Channel FIELD NOT IMPLEMENTED!!!! offset=0x%04x\n", method_offset); - - return 0x00; -}; - -// Although NV3 doesn't have DMA mode unlike NV4 and later, it's conceptually similar to a "pusher" that pushes graphics commands that you write into CACHE1 that are then pulled out. -// So we send the writes here. This might do other stuff, so we keep this function -void nv3_user_write(uint32_t address, uint32_t value) -{ - nv3_pfifo_cache1_push(address, value); - - // This isn't ideal, but otherwise, the dynarec causes the GPU to write so many objects into CACHE1, it starts overwriting the old objects - // This basically makes the fifo not a fifo, but oh well - nv3_pfifo_cache1_pull(); -} \ No newline at end of file diff --git a/src/video/nv/nv4/nv4_core.c b/src/video/nv/nv4/nv4_core.c deleted file mode 100644 index 5712cf7d1..000000000 --- a/src/video/nv/nv4/nv4_core.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV4 bringup and device emulation. - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv4.h> - -nv4_t* nv4; - -// Stolen from Voodoo 3 -static video_timings_t timing_nv4_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 }; - -// Initialise the MMIO mappings -void nv4_init_mappings_mmio(void) -{ - nv_log("Initialising MMIO mapping\n"); - - // 0x0 - 1000000: regs - // 0x1000000-2000000 - - // initialize the mmio mapping - mem_mapping_add(&nv4->nvbase.mmio_mapping, 0, 0, - nv4_mmio_read8, - nv4_mmio_read16, - nv4_mmio_read32, - nv4_mmio_write8, - nv4_mmio_write16, - nv4_mmio_write32, - NULL, MEM_MAPPING_EXTERNAL, nv4); - - // initialize the mmio mapping - mem_mapping_add(&nv4->nvbase.ramin_mapping, 0, 0, - nv4_ramin_read8, - nv4_ramin_read16, - nv4_ramin_read32, - nv4_ramin_write8, - nv4_ramin_write16, - nv4_ramin_write32, - NULL, MEM_MAPPING_EXTERNAL, nv4); - -} - -void nv4_init_mappings_svga(void) -{ - nv_log("Initialising SVGA core memory mapping\n"); - // setup the svga mappings - - mem_mapping_add(&nv4->nvbase.framebuffer_mapping, 0, 0, - nv4_dfb_read8, - nv4_dfb_read16, - nv4_dfb_read32, - nv4_dfb_write8, - nv4_dfb_write16, - nv4_dfb_write32, - nv4->nvbase.svga.vram, 0, &nv4->nvbase.svga); - - // the SVGA/LFB mapping is also mirrored - mem_mapping_add(&nv4->nvbase.framebuffer_mapping_mirror, 0, 0, - nv4_dfb_read8, - nv4_dfb_read16, - nv4_dfb_read32, - nv4_dfb_write8, - nv4_dfb_write16, - nv4_dfb_write32, - nv4->nvbase.svga.vram, 0, &nv4->nvbase.svga); - - io_sethandler(NV4_CIO_START, NV4_CIO_SIZE, - nv4_svga_read, NULL, NULL, - nv4_svga_write, NULL, NULL, - nv4); -} - -void nv4_init_mappings(void) -{ - nv4_init_mappings_mmio(); - nv4_init_mappings_svga(); -} - -// Updates the mappings after initialisation. -void nv4_update_mappings(void) -{ - // sanity check - if (!nv4) - return; - - // setting this to 0 doesn't seem to disable it, based on the datasheet - - nv_log("\nMemory Mapping Config Change:\n"); - - (nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n"); - - io_removehandler(NV4_CIO_START, NV4_CIO_SIZE, - nv4_svga_read, NULL, NULL, - nv4_svga_write, NULL, NULL, - nv4); - - if (nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) - io_sethandler(NV4_CIO_START, NV4_CIO_SIZE, - nv4_svga_read, NULL, NULL, - nv4_svga_write, NULL, NULL, - nv4); - - if (!(nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) - { - nv_log("The memory was turned off, not much is going to happen.\n"); - return; - } - - // turn off bar0 and bar1 by defualt - mem_mapping_disable(&nv4->nvbase.mmio_mapping); - mem_mapping_disable(&nv4->nvbase.framebuffer_mapping); - mem_mapping_disable(&nv4->nvbase.framebuffer_mapping_mirror); - mem_mapping_disable(&nv4->nvbase.ramin_mapping); - - // Setup BAR0 (MMIO) - - nv_log("BAR0 (MMIO Base) = 0x%08x\n", nv4->nvbase.bar0_mmio_base); - - if (nv4->nvbase.bar0_mmio_base) - { - mem_mapping_set_addr(&nv4->nvbase.mmio_mapping, nv4->nvbase.bar0_mmio_base, NV4_MMIO_SIZE); - mem_mapping_set_addr(&nv4->nvbase.ramin_mapping, nv4->nvbase.bar0_mmio_base + NV4_PRAMIN_START, NV4_PRAMIN_SIZE); - } - - // if this breaks anything, remove it - nv_log("BAR1 (Linear Framebuffer & VRAM) = 0x%08x\n", nv4->nvbase.bar1_lfb_base); - - if (nv4->nvbase.bar1_lfb_base) - { - if (nv4->nvbase.vram_amount == NV4_VRAM_SIZE_16MB) - { - // we don't need this one in the case of 16mb, - mem_mapping_disable(&nv4->nvbase.framebuffer_mapping_mirror); - mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping, nv4->nvbase.bar1_lfb_base, NV4_VRAM_SIZE_16MB); - } - else if (nv4->nvbase.vram_amount == NV4_VRAM_SIZE_8MB) - { - mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping, nv4->nvbase.bar1_lfb_base, NV4_VRAM_SIZE_8MB); - mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping_mirror, nv4->nvbase.bar1_lfb_base + NV4_VRAM_SIZE_8MB, NV4_VRAM_SIZE_8MB); - } - } - - // Did we change the banked SVGA mode? - switch (nv4->nvbase.svga.gdcreg[NV4_PRMVIO_GX_MISC_INDEX] & 0x0c) - { - case NV4_PRMVIO_GX_MISC_BANKED_128K_A0000: - nv_log("SVGA Banked Mode = 128K @ A0000h\n"); - mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000 - nv4->nvbase.svga.banked_mask = 0x1FFFF; - break; - case NV4_PRMVIO_GX_MISC_BANKED_64K_A0000: - nv_log("SVGA Banked Mode = 64K @ A0000h\n"); - mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000 - nv4->nvbase.svga.banked_mask = 0xFFFF; - break; - case NV4_PRMVIO_GX_MISC_BANKED_32K_B0000: - nv_log("SVGA Banked Mode = 32K @ B0000h\n"); - mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000 - nv4->nvbase.svga.banked_mask = 0x7FFF; - break; - case NV4_PRMVIO_GX_MISC_BANKED_32K_B8000: - nv_log("SVGA Banked Mode = 32K @ B8000h\n"); - mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000 - nv4->nvbase.svga.banked_mask = 0x7FFF; - break; - } -} - - -bool nv4_init() -{ - nv4 = calloc(1, sizeof(nv4_t)); - - if (!nv4->nvbase.vram_amount) - nv4->nvbase.vram_amount = device_get_config_int("vram_size"); - - /* Set log device name based on card model */ - const char* log_device_name = "NV4"; - - /* Just hardcode full logging */ - - if (device_get_config_int("nv_debug_fulllog")) - nv4->nvbase.log = log_open(log_device_name); - else - nv4->nvbase.log = log_open_cyclic(log_device_name); - - nv_log_set_device(nv4->nvbase.log); - - nv4->nvbase.bus_generation = nv_bus_agp_2x; - - // Figure out which vbios the user selected - // This depends on the bus we are using and if the gpu is rev a/b or rev c - - const char* vbios_file = NV4_VBIOS_STB_REVA; - - int32_t err = rom_init(&nv4->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); - - if (err) - { - nv_log("NV4 FATAL: failed to load VBIOS err=%d\n", err); - fatal("Nvidia NV4 init failed: Somehow selected a nonexistent VBIOS? err=%d\n", err); - return false; - } - else - nv_log("Successfully loaded VBIOS located at %s\n", vbios_file); - - pci_add_card(PCI_ADD_AGP, nv4_pci_read, nv4_pci_write, NULL, &nv4->nvbase.pci_slot); - - svga_init(&nv4_device_agp, &nv4->nvbase.svga, nv4, nv4->nvbase.vram_amount, - nv4_recalc_timings, nv4_svga_read, nv4_svga_write, nv4_draw_cursor, NULL); - - video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv4_agp); - - // Setup clock information. These values don't matter, I pulled them out of an STB BIOS, we don't need to macro them - nv4->pramdac.nvclk = 0x17809; - nv4->pramdac.mclk = 0x1a30a; - nv4->pramdac.vclk = 0x1400c; - - //timer_add(nv4->pramdac.nvclk, ) - - - - nv4_init_mappings(); - //nv4_update_mappings(); - - return true; -} - -void* nv4_init_stb4400(const device_t *info) -{ - bool successful = nv4_init(); - - if (successful) - return nv4; - else - return NULL; -} - -void nv4_nvclk_tick() -{ - -} - -void nv4_mclk_tick() -{ - -} - -void nv4_vclk_tick() -{ - -} - -void nv4_close(void* priv) -{ - free(nv4); -} - -void nv4_speed_changed(void *priv) -{ - -} - -void nv4_draw_cursor(svga_t* svga, int32_t drawline) -{ - -} - - -// -// SVGA functions -// -void nv4_recalc_timings(svga_t* svga) -{ - // sanity check - if (!nv4) - return; - - - nv4_t* nv4 = (nv4_t*)svga->priv; - - // TODO: Everything, this code sucks, incl. NV4_PRAMDAC_GENERAL_CONTROL_BPC and the offset register - uint32_t pixel_mode = svga->crtc[NV4_CIO_CRE_PIXEL_INDEX] & 0x03; - - svga->memaddr_latch += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0x1F) << 16; - - /* Turn off override if we are in VGA mode */ - svga->override = !(pixel_mode == NV4_CIO_CRE_PIXEL_FORMAT_VGA); - - /* NOTE: The RIVA 128 draws in a way almost completely separate to any other 86Box GPU. - - Basically, we only blit to buffer32 when something changes and we don't even bother using a timer. We only render when there is something to actually render. - - This is because there is no linear relationship between the contents of VRAM and the contents of the display which 86box's SVGA subsystem cannot tolerate. - In fact, the position in VRAM and pitch can be changed at any time via an NV_IMAGE_IN_MEMORY object. - - Therefore, we need to completely bypass it using svga->override and draw our own rendering functions. This allows us to use a neat optimisation trick - to only ever actually draw when we need to do something. This shouldn't be a problem in games, because the drivers will read the current refresh rate from - the Windows settings, and then, just submit objects at that pace for anything that changes on the screen. - */ - - // Set the pixel mode - switch (pixel_mode) - { - case NV4_CIO_CRE_PIXEL_FORMAT_8BPP: - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 1; // ????? - svga->bpp = 8; - svga->lowres = 0; - svga->map8 = svga->pallook; - break; - case NV4_CIO_CRE_PIXEL_FORMAT_16BPP: - /* This is some sketchy shit that is an attempt at an educated guess - at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics, - this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */ - if ((svga->crtc[NV4_CIO_CR_VRS_INDEX] >> 1) & 0x01) - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 2; - else - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; - - // 15bpp mode is removed on NV4 - // TODO: Not svga - svga->bpp = 16; - svga->lowres = 0; - - break; - case NV4_CIO_CRE_PIXEL_FORMAT_32BPP: - svga->rowoffset += (svga->crtc[NV4_CIO_CRE_RPC0_INDEX] & 0xE0) << 3; - - svga->bpp = 32; - svga->lowres = 0; - //svga->render = nv4_render_32bpp; - break; - } - - - if (((svga->miscout >> 2) & 2) == 2) - { - // set clocks - //nv4_pramdac_set_pixel_clock(); - //nv4_pramdac_set_vram_clock(); - } -} - - -// See if the bios rom is available. -int32_t nv4_available(void) -{ - return (rom_present(NV4_VBIOS_STB_REVA)); -} - -// NV4 (RIVA 128) -// AGP -// 8MB or 16MB VRAM -const device_t nv4_device_agp = -{ - .name = "nVIDIA RIVA TNT (STB Velocity 4400)", - .internal_name = "nv4_stb4400", - .flags = DEVICE_AGP, - .local = 0, - .init = nv4_init_stb4400, - .close = nv4_close, - .speed_changed = nv4_speed_changed, - .force_redraw = nv4_force_redraw, - .available = nv4_available, - .config = nv4_config, -}; diff --git a/src/video/nv/nv4/nv4_core_config.c b/src/video/nv/nv4/nv4_core_config.c deleted file mode 100644 index 2dd88eed6..000000000 --- a/src/video/nv/nv4/nv4_core_config.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Provides NV4 configuration - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv4.h> - -const device_config_t nv4_config[] = -{ - // Memory configuration - { - .name = "vram_size", - .description = "VRAM Size", - .type = CONFIG_SELECTION, - .default_int = NV4_VRAM_SIZE_16MB, - .selection = - { - // I thought this was never released, but it seems that at least one was released: - // The card was called the "NEC G7AGK" - { - .description = "8 MB", - .value = NV4_VRAM_SIZE_8MB, - }, - - { - .description = "16 MB", - .value = NV4_VRAM_SIZE_16MB, - }, - } - - }, - // Multithreading configuration - { - - .name = "pgraph_threads", - .description = "Render threads", - .type = CONFIG_SELECTION, - .default_int = 1, // todo: change later - .selection = - { - { - .description = "1 thread (Only use if issues appear with more threads)", - .value = 1, - }, - { - .description = "2 threads", - .value = 2, - }, - { - .description = "4 threads", - .value = 4, - }, - { - .description = "8 threads", - .value = 8, - }, - }, - }, -#ifndef RELEASE_BUILD - { - .name = "nv_debug_fulllog", - .description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)", - .type = CONFIG_BINARY, - .default_int = 0, - }, -#endif - { - .type = CONFIG_END - } -}; \ No newline at end of file diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c deleted file mode 100644 index 4c5aa5a40..000000000 --- a/src/video/nv/nv4/nv4_core_io.c +++ /dev/null @@ -1,1283 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV4 I/O, including Real-Mode Access (RMA), memory mapping, PCI, AGP, SVGA and MMIO via PCI BARs - * - * MMIO dumps are available at: https://nvwiki.org/misc/NVDumps/ - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - - -// Prototypes for functions only used in this translation unit - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv4.h> - - -void nv4_init_mappings_mmio(void); -void nv4_init_mappings_svga(void); -bool nv4_is_svga_redirect_address(uint32_t addr); - -uint8_t nv4_svga_read(uint16_t addr, void* priv); -void nv4_svga_write(uint16_t addr, uint8_t val, void* priv); - - -uint32_t nv4_mmio_arbitrate_read(uint32_t addr) -{ - uint32_t ret = 0x00; - - if (addr >= NV4_PTIMER_START && addr <= NV4_PTIMER_END) - ret = nv4_ptimer_read(addr); - else if (addr >= NV4_PRAMDAC_START && addr <= NV4_PRAMDAC_END) - ret = nv4_pramdac_read(addr); - - #ifdef NV_LOG - nv_register_t reg = nv_get_register(addr, &nv4_registers, sizeof(nv4_registers)/sizeof(nv4_registers[0])); - - if (reg) - { - if (reg->on_read) - ret = reg->on_read(); - - nv_log_verbose_only("Register read from 0x%08x value=%08x", addr, ret); - - } - #endif - -} - -void nv4_mmio_arbitrate_write(uint32_t addr, uint32_t val) -{ - if (addr >= NV4_PTIMER_START && addr <= NV4_PTIMER_END) - nv4_ptimer_write(addr, val); - else if (addr >= NV4_PRAMDAC_START && addr <= NV4_PRAMDAC_END) - nv4_pramdac_write(addr, val); - - #ifdef NV_LOG - nv_register_t reg = nv_get_register(addr, &nv4_registers, sizeof(nv4_registers)/sizeof(nv4_registers[0])); - - if (reg) - { - if (reg->on_write) - reg->on_write(val); - - nv_log_verbose_only("Register write from 0x%08x value=%08x", addr, val); - - } - #endif -} - -// Determine if this address needs to be redirected to the SVGA subsystem. - -bool nv4_is_svga_redirect_address(uint32_t addr) -{ - return (addr >= NV4_PRMVIO_START && addr <= NV4_PRMVIO_END) // VGA - || (addr >= NV4_PRMCIO_START && addr <= NV4_PRMCIO_END) // CRTC - || (addr >= NV4_USER_DAC_START && addr <= NV4_USER_DAC_END); // Note: 6813c6-6813c9 are ignored somewhere else -} - -uint8_t nv4_rma_read(uint16_t addr) -{ - addr &= 0xFF; - uint32_t real_final_address = 0x0; - uint8_t ret = 0x0; - - switch (addr) - { - // signature so you know reads work - case 0x00: - ret = NV4_PRMIO_RMA_ID_CODE_VALID & 0xFF; - break; - case 0x01: - ret = (NV4_PRMIO_RMA_ID_CODE_VALID >> 8) & 0xFF; - break; - case 0x02: - ret = (NV4_PRMIO_RMA_ID_CODE_VALID >> 16) & 0xFF; - break; - case 0x03: - ret = (NV4_PRMIO_RMA_ID_CODE_VALID >> 24) & 0xFF; - break; - case 0x08 ... 0x0B: - // reads must be dword aligned - real_final_address = (nv4->pbus.rma.addr + (addr & 0x03)); - - if (nv4->pbus.rma.addr < NV4_MMIO_SIZE) - ret = nv4_mmio_read8(real_final_address, NULL); - else - { - /* Do we need to read RAMIN here? */ - ret = nv4->nvbase.svga.vram[real_final_address - NV4_MMIO_SIZE] & (nv4->nvbase.svga.vram_max - 1); - } - - // log current location for vbios RE - nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%08x final RMA MMIO address=0x%08x data=0x%08x\n", - addr, real_final_address, ret); - - break; - } - - return ret; -} - -// Implements a 32-bit write using 16 bit port number -void nv4_rma_write(uint16_t addr, uint8_t val) -{ - // addresses are in reality 8bit so just mask it to be safe - addr &= 0xFF; - - // format: - // 0x00 ID - // 0x04 Pointer to data - // 0x08 Data port(?) - // 0x0B Data - 32bit. SENT IN THE RIGHT ORDER FOR ONCE WAHOO! - // 0x10 Increment (?) data - implemented the same as data for now - - if (addr < 0x08) - { - switch (addr % 0x04) - { - case 0x00: // lowest byte - nv4->pbus.rma.addr &= ~0xff; - nv4->pbus.rma.addr |= val; - break; - case 0x01: // 2nd highest byte - nv4->pbus.rma.addr &= ~0xff00; - nv4->pbus.rma.addr |= (val << 8); - break; - case 0x02: // 3rd highest byte - nv4->pbus.rma.addr &= ~0xff0000; - nv4->pbus.rma.addr |= (val << 16); - break; - case 0x03: // 4th highest byte - nv4->pbus.rma.addr &= ~0xff000000; - nv4->pbus.rma.addr |= (val << 24); - break; - } - } - // Data to send to MMIO - else - { - switch (addr % 0x04) - { - case 0x00: // lowest byte - nv4->pbus.rma.data &= ~0xff; - nv4->pbus.rma.data |= val; - break; - case 0x01: // 2nd highest byte - nv4->pbus.rma.data &= ~0xff00; - nv4->pbus.rma.data |= (val << 8); - break; - case 0x02: // 3rd highest byte - nv4->pbus.rma.data &= ~0xff0000; - nv4->pbus.rma.data |= (val << 16); - break; - case 0x03: // 4th highest byte - nv4->pbus.rma.data &= ~0xff000000; - nv4->pbus.rma.data |= (val << 24); - - nv_log_verbose_only("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n", - addr, nv4->pbus.rma.addr, nv4->pbus.rma.data); - - if (nv4->pbus.rma.addr < NV4_MMIO_SIZE) - nv4_mmio_write32(nv4->pbus.rma.addr, nv4->pbus.rma.data, NULL); - else // failsafe code, i don't think you will ever write outside of VRAM? - { - uint32_t* vram_32 = (uint32_t*)nv4->nvbase.svga.vram; - vram_32[(nv4->pbus.rma.addr - NV4_MMIO_SIZE) >> 2] = nv4->pbus.rma.data; - } - - - break; - } - } - - if (addr & 0x10) - nv4->pbus.rma.addr += 0x04; // Alignment -} - - - -// All MMIO regs are 32-bit i believe internally -// so we have to do some munging to get this to read - -// Read 8-bit MMIO -uint8_t nv4_mmio_read8(uint32_t addr, void* priv) -{ - uint32_t ret = 0x00; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - addr &= 0xFFFFFF; - - // We need to specifically exclude this particular set of registers - // so we can write the 4/8bpp CLUT - if (addr >= NV4_USER_DAC_PALETTE_START && addr <= NV4_USER_DAC_PALETTE_END) - { - // Throw directly into PRAMDAC - return nv4_mmio_arbitrate_read(addr); - } - - if (nv4_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - ret = nv4_svga_read(real_address, nv4); - - nv_log_verbose_only("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - - return ret; - } - - // see if unaligned reads are a problem - ret = nv4_mmio_read32(addr, priv); - return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFF); -} - -// Read 16-bit MMIO -uint16_t nv4_mmio_read16(uint32_t addr, void* priv) -{ - uint32_t ret = 0x00; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - addr &= 0xFFFFFF; - - if (nv4_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - ret = nv4_svga_read(real_address, nv4) - | (nv4_svga_read(real_address + 1, nv4) << 8); - - nv_log_verbose_only("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - - return ret; - } - - ret = nv4_mmio_read32(addr, priv); - return (uint8_t)(ret >> ((addr & 3) << 3) & 0xFFFF); -} - -// Read 32-bit MMIO -uint32_t nv4_mmio_read32(uint32_t addr, void* priv) -{ - uint32_t ret = 0x00; - - // Some of these addresses are Weitek VGA stuff and we need to mask it to this first because the weitek addresses are 8-bit aligned. - addr &= 0xFFFFFF; - - if (nv4_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - ret = nv4_svga_read(real_address, nv4) - | (nv4_svga_read(real_address + 1, nv4) << 8) - | (nv4_svga_read(real_address + 2, nv4) << 16) - | (nv4_svga_read(real_address + 3, nv4) << 24); - - nv_log_verbose_only("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret); - - return ret; - } - - ret = nv4_mmio_arbitrate_read(addr); - - return ret; -} - -// Write 8-bit MMIO -void nv4_mmio_write8(uint32_t addr, uint8_t val, void* priv) -{ - addr &= 0xFFFFFF; - - // We need to specifically exclude this particular set of registers - // so we can write the 4/8bpp CLUT - if (addr >= NV4_USER_DAC_PALETTE_START && addr <= NV4_USER_DAC_PALETTE_END) - { - // Throw directly into PRAMDAC - nv4_mmio_arbitrate_write(addr, val); - return; - } - - // This is weitek vga stuff - // If we need to add more of these we can convert these to a switch statement - if (nv4_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - nv_log_verbose_only("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - - nv4_svga_write(real_address, val & 0xFF, nv4); - - return; - } - - // overwrite first 8bits of a 32 bit value - uint32_t new_val = nv4_mmio_read32(addr, NULL); - - new_val &= (~0xFF << (addr & 3) << 3); - new_val |= (val << ((addr & 3) << 3)); - - nv4_mmio_write32(addr, new_val, priv); -} - -// Write 16-bit MMIO -void nv4_mmio_write16(uint32_t addr, uint16_t val, void* priv) -{ - addr &= 0xFFFFFF; - - // This is weitek vga stuff - if (nv4_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - - nv4_svga_write(real_address, val & 0xFF, nv4); - nv4_svga_write(real_address + 1, (val >> 8) & 0xFF, nv4); - - return; - } - - // overwrite first 16bits of a 32 bit value - uint32_t new_val = nv4_mmio_read32(addr, NULL); - - new_val &= (~0xFFFF << (addr & 3) << 3); - new_val |= (val << ((addr & 3) << 3)); - - nv4_mmio_write32(addr, new_val, priv); -} - -// Write 32-bit MMIO -void nv4_mmio_write32(uint32_t addr, uint32_t val, void* priv) -{ - addr &= 0xFFFFFF; - - // This is weitek vga stuff - if (nv4_is_svga_redirect_address(addr)) - { - // svga writes are not logged anyway rn - uint32_t real_address = addr & 0x3FF; - - nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val); - - nv4_svga_write(real_address, val & 0xFF, nv4); - nv4_svga_write(real_address + 1, (val >> 8) & 0xFF, nv4); - nv4_svga_write(real_address + 2, (val >> 16) & 0xFF, nv4); - nv4_svga_write(real_address + 3, (val >> 24) & 0xFF, nv4); - - return; - } - - nv4_mmio_arbitrate_write(addr, val); -} - -// PCI stuff -// BAR0 Pointer to MMIO space & RAMIN -// BAR1 Pointer to Linear Framebuffer -uint8_t nv4_pci_read(int32_t func, int32_t addr, void* priv) -{ - uint8_t ret = 0x00; - - // sanity check - if (!nv4) - return ret; - - // Convert to the MMIO addresses - if (addr <= 0xFF) - addr += 0x1800; - - // Anything not listed is 0x00 - // PCI values extracted from https://nvwiki.org/misc/NVDumps/RivaMobileNV4/Nv4win_HL/nv4bar0.bin - // STB V4400 (running Half-Life) - switch (addr) - { - // Get the pci vendor id.. - - case NV4_PBUS_PCI_VENDOR_ID: - ret = (NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA & 0xFF); - break; - - case NV4_PBUS_PCI_VENDOR_ID + 1: // all access 8bit - ret = (NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA >> 8); - break; - - // device id - - case NV4_PBUS_PCI_DEVICE_ID: - ret = (NV_PCI_DEVICE_NV4 & 0xFF); - break; - - case NV4_PBUS_PCI_DEVICE_ID + 1: - ret = (NV_PCI_DEVICE_NV4 >> 8); - break; - - // various capabilities enabled by default - // IO space enabled - // Memory space enabled - // Bus master enabled - // Write/inval enabled - // Pal snoop enabled - // Capabiliies list enabled - // 66Mhz FSB capable - - case NV4_PBUS_PCI_COMMAND: - ret = nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L]; - break; - // COMMAND_L not used - - // pci status register - case NV4_PBUS_PCI_STATUS: - if (nv4->straps - & NV4_STRAP_BUS_SPEED_66MHZ) - ret = (nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] | NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE); - else - ret = nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L]; - - break; - - case NV4_PBUS_PCI_STATUS_2: - ret = (nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST << NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING); - break; - - case NV4_PBUS_PCI_REVISION_ID: - ret = nv4->nvbase.gpu_revision; // Commercial release - break; - - case PCI_REG_PROG_IF: - ret = 0x00; - break; - - // We only need to return 0x30 since the VGA class code is 0x30000 - case NV4_PBUS_PCI_CLASS_CODE: - ret = (NV4_PBUS_PCI_CLASS_CODE_VGA) >> 16; // CLASS_CODE_VGA - break; - - - case NV4_PBUS_PCI_LATENCY_TIMER: - case NV4_PBUS_PCI_HEADER_TYPE: - ret = 0x00; - break; - - // BARs are marked as prefetchable per the datasheet - case NV4_PBUS_PCI_BAR0_INFO: - case NV4_PBUS_PCI_BAR1_INFO: - // only bit that matters is bit 3 (prefetch bit) - ret = (NV4_PBUS_PCI_BAR_PREFETCHABLE_MERGABLE << NV4_PBUS_PCI_BAR_PREFETCHABLE); - break; - - // MMIO base address - case NV4_PBUS_PCI_BAR0_BASE_31_TO_24: - ret = nv4->nvbase.bar0_mmio_base >> 24;//8bit value - break; - - case NV4_PBUS_PCI_BAR1_BASE_31_TO_24: - ret = nv4->nvbase.bar1_lfb_base >> 24; //8bit value - break; - - case NV4_PBUS_PCI_BAR_RESERVED_START ... NV4_PBUS_PCI_BAR_RESERVED_END: - case NV4_PBUS_PCI_BAR0_UNUSED1: - case NV4_PBUS_PCI_BAR0_UNUSED2: - case NV4_PBUS_PCI_BAR1_UNUSED1: - case NV4_PBUS_PCI_BAR1_UNUSED2: - - ret = 0x00; // hard lock - break; - - case NV4_PBUS_PCI_ROM: - ret = nv4->nvbase.pci_config.vbios_enabled; - break; - - case NV4_PBUS_PCI_INTR_LINE: - ret = nv4->nvbase.pci_config.int_line; - break; - - case NV4_PBUS_PCI_INTR_PIN: - ret = PCI_INTA; - break; - - // - // Capabilities pointers - // - - case NV4_PBUS_PCI_NEXT_PTR: - ret = NV4_PBUS_PCI_CAP_PTR_POWER_MGMT; - break; - - case NV4_PBUS_PCIPOWER_NEXT_PTR: - ret = NV4_PBUS_PCI_CAP_PTR_AGP; - break; - - // AGP is the end of the chain - case NV4_PBUS_AGP_NEXT_PTR: - ret = 0x00; - break; - - case NV4_PBUS_PCI_MAX_LAT: - ret = NV4_PBUS_PCI_MAX_LAT_250NS; - break; - - // these map to the subsystem - // todo: port this bugfix to NV4 - case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE: - case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE + 1: - case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE: - case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE + 1: - ret = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_SUBSYSTEM_ID + (addr & 0x03)]; - break; - - case NV4_PBUS_AGP_CAPABILITIES: - ret = NV4_PBUS_AGP_CAPABILITY_AGP; // AGP capable device - break; - case NV4_PBUS_AGP_REV: - ret = (NV4_PBUS_AGP_REV_MAJOR_1 << NV4_PBUS_AGP_REV_MAJOR) | NV4_PBUS_AGP_REV_MINOR; - break; - case NV4_PBUS_AGP_STATUS_RATE: - ret = NV4_PBUS_AGP_STATUS_RATE_1X_AND_2X; - break; - case NV4_PBUS_AGP_STATUS_SBA: - ret = (NV4_PBUS_AGP_STATUS_SBA_STATUS_CAPABLE) << NV4_PBUS_AGP_STATUS_SBA_STATUS; // Sideband is supported on NV4 - break; - case NV4_PBUS_AGP_STATUS_RQ: - ret = NV4_PBUS_AGP_STATUS_RQ_16; - break; - case NV4_PBUS_AGP_COMMAND_2: - ret = (nv4->nvbase.agp_enabled) << NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED - | (nv4->nvbase.agp_sba_enabled) << NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED; - break; - default: // by default just return pci_config.pci_regs (default value for nonwritten registers is 0x00) - ret = nv4->nvbase.pci_config.pci_regs[addr]; - break; - - } - - nv_log("nv4_pci_read func=0x%04x addr=0x%04x ret=0x%04x\n", func, addr & 0xFF, ret); - return ret; -} - - -// nv4 pci/agp write -void nv4_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv) -{ - // sanity check - if (!nv4) - return; - - // Convert to the MMIO addresses - if (addr <= 0xFF) - addr += 0x1800; - // some addresses are not writable so can't have any effect and can't be allowed to be modified using this code - // as an example, only the most significant byte of the PCI BARs can be modified - if (addr == NV4_PBUS_PCI_BAR0_UNUSED1 || addr == NV4_PBUS_PCI_BAR0_UNUSED2 - && addr == NV4_PBUS_PCI_BAR1_UNUSED1 || addr == NV4_PBUS_PCI_BAR1_UNUSED2) - return; - - nv_log("nv4_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr & 0xFF, val); - - nv4->nvbase.pci_config.pci_regs[addr] = val; - - switch (addr) - { - // standard pci command stuff - case NV4_PBUS_PCI_COMMAND: - nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L] = val; - // actually update the mappings - nv4_update_mappings(); - break; - case NV4_PBUS_PCI_COMMAND_H: - nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] = val; - // actually update the mappings - nv4_update_mappings(); - break; - // pci status register - case NV4_PBUS_PCI_STATUS: - nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE << NV4_PBUS_PCI_STATUS_66MHZ); - break; - case NV4_PBUS_PCI_STATUS_2: - nv4->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST << NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING); - break; - //TODO: ACTUALLY REMAP THE MMIO AND NV_USER - case NV4_PBUS_PCI_BAR0_BASE_31_TO_24: - nv4->nvbase.bar0_mmio_base = val << 24; - nv4_update_mappings(); - break; - case NV4_PBUS_PCI_BAR1_BASE_31_TO_24: - nv4->nvbase.bar1_lfb_base = val << 24; - nv4_update_mappings(); - break; - - case NV4_PBUS_PCI_ROM: - case NV4_PBUS_PCI_ROM_BASE: - - // make sure we are actually toggling the vbios, not the rom base - if (addr == NV4_PBUS_PCI_ROM) - nv4->nvbase.pci_config.vbios_enabled = (val & 0x01); - - if (nv4->nvbase.pci_config.vbios_enabled) - { - // First see if we simply wanted to change the VBIOS location - - // Enable it in case it was disabled before - mem_mapping_enable(&nv4->nvbase.vbios.mapping); - - if (addr != NV4_PBUS_PCI_ROM) - { - uint32_t old_addr = nv4->nvbase.vbios.mapping.base; - // 9bit register - uint32_t new_addr = nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM + 3] << 24 | - nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_ROM + 2] << 16; - - // only bits 31;22 matter - //new_addr &= 0xFFC00000; - - // move it - mem_mapping_set_addr(&nv4->nvbase.vbios.mapping, new_addr, 0x8000); - - nv_log("...i like to move it move it (VBIOS Relocation) 0x%x -> 0x%x\n", old_addr, new_addr); - - } - else - { - nv_log("...VBIOS Enable\n"); - } - } - else - { - nv_log("...VBIOS Disable\n"); - mem_mapping_disable(&nv4->nvbase.vbios.mapping); - - } - break; - case NV4_PBUS_PCI_INTR_LINE: - nv4->nvbase.pci_config.int_line = val; - break; - // these are mirrored to the subsystem id and also stored in the ROMBIOS - //todo: port to pci - case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE: - case NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE + 1: - case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE: - case NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE + 1: - nv4->nvbase.pci_config.pci_regs[NV4_PBUS_PCI_SUBSYSTEM_ID + (addr & 0x03)] = val; - break; - case NV4_PBUS_AGP_COMMAND_2: - nv4->nvbase.agp_enabled = (val >> NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED) & 0x01; - nv4->nvbase.agp_sba_enabled = (val >> NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED) & 0x01; - break; - default: - break; - } -} - - -void nv4_speed_changed(void* priv) -{ - // sanity check - if (!nv4) - return; - - nv4_recalc_timings(&nv4->nvbase.svga); -} - -// Force Redraw -// Reset etc. -void nv4_force_redraw(void* priv) -{ - // sanity check - if (!nv4) - return; - - nv4->nvbase.svga.fullchange = changeframecount; -} - -// CHECK that ramin is the smae as nv4 - -// Read 8-bit ramin -uint8_t nv4_ramin_read8(uint32_t addr, void* priv) -{ - if (!nv4) return 0x00; - - addr &= (nv4->nvbase.svga.vram_max - 1); - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv4->nvbase.svga.vram_max - 0x10); - - uint32_t val = 0x00; - - //if (!nv4_ramin_arbitrate_read(addr, &val)) // Oh well - //{ - val = (uint8_t)nv4->nvbase.svga.vram[addr]; - nv_log_verbose_only("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); - //} - - return (uint8_t)val; -} - -// Read 16-bit ramin -uint16_t nv4_ramin_read16(uint32_t addr, void* priv) -{ - if (!nv4) return 0x00; - - addr &= (nv4->nvbase.svga.vram_max - 1); - - // why does this not work in one line - svga_t* svga = &nv4->nvbase.svga; - uint16_t* vram_16bit = (uint16_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv4->nvbase.svga.vram_max - 0x10); - addr >>= 1; // what - - uint32_t val = 0x00; - - //if (!nv4_ramin_arbitrate_read(addr, &val)) - //{ - val = (uint16_t)vram_16bit[addr]; - nv_log_verbose_only("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr); - //} - - return val; -} - -// Read 32-bit ramin -uint32_t nv4_ramin_read32(uint32_t addr, void* priv) -{ - if (!nv4) - return 0x00; - - addr &= (nv4->nvbase.svga.vram_max - 1); - - // why does this not work in one line - uint32_t* vram_32bit = (uint32_t*)nv4->nvbase.svga.vram; - uint32_t raw_addr = addr; // saved after and logged - - addr ^= (nv4->nvbase.svga.vram_max - 0x10); - addr >>= 2; // what - - uint32_t val = 0x00; - - //if (!nv4_ramin_arbitrate_read(addr, &val)) - //{ - val = vram_32bit[addr]; - nv_log_verbose_only("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr); - //} - - return val; -} - -// Write 8-bit ramin -void nv4_ramin_write8(uint32_t addr, uint8_t val, void* priv) -{ - if (!nv4) return; - - addr &= (nv4->nvbase.svga.vram_max - 1); - uint32_t raw_addr = addr; // saved after and - - // Structures in RAMIN are stored from the bottom of vram up in reverse order - // this can be explained without bitwise math like so: - // real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) - // reversal unit size in this case is 16 bytes, vram size is 2-8mb (but 8mb is zx/nv4t only and 2mb...i haven't found a 22mb card) - addr ^= (nv4->nvbase.svga.vram_max - 0x10); - - uint32_t val32 = (uint32_t)val; - - //if (!nv4_ramin_arbitrate_write(addr, val32)) - //{ - nv4->nvbase.svga.vram[addr] = val; - nv_log_verbose_only("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr); - //} -} - -// Write 16-bit ramin -void nv4_ramin_write16(uint32_t addr, uint16_t val, void* priv) -{ - if (!nv4) return; - - addr &= (nv4->nvbase.svga.vram_max - 1); - - // why does this not work in one line - svga_t* svga = &nv4->nvbase.svga; - uint16_t* vram_16bit = (uint16_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv4->nvbase.svga.vram_max - 0x10); - addr >>= 1; // what - - uint32_t val32 = (uint32_t)val; - - //if (!nv4_ramin_arbitrate_write(addr, val32)) - //{ - vram_16bit[addr] = val; - nv_log_verbose_only("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr); - //} - - -} - -// Write 32-bit ramin -void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv) -{ - if (!nv4) return; - - addr &= (nv4->nvbase.svga.vram_max - 1); - - // why does this not work in one line - svga_t* svga = &nv4->nvbase.svga; - uint32_t* vram_32bit = (uint32_t*)svga->vram; - uint32_t raw_addr = addr; // saved after and - - addr ^= (nv4->nvbase.svga.vram_max - 0x10); - addr >>= 2; // what - - //if (!nv4_ramin_arbitrate_write(addr, val)) - //{ - vram_32bit[addr] = val; - nv_log_verbose_only("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr); - //} -} - -// Read from SVGA core memory -uint8_t nv4_svga_read(uint16_t addr, void* priv) -{ - // CR = CRTC Controller - // CRE = CRTC Controller Extended (weitek) - uint8_t ret = 0x00; - - // sanity check - if (!nv4) - return ret; - - // If we need to RMA from GPU MMIO, go do that - if (addr >= NV4_RMA_REGISTER_START - && addr <= NV4_RMA_REGISTER_END) - { - if (!(nv4->pbus.rma.mode & 0x01)) - return ret; - - // must be dword aligned - uint32_t real_rma_read_addr = ((nv4->pbus.rma.mode & 0x0E) << 1) + (addr & 0x03); - ret = nv4_rma_read(real_rma_read_addr); - return ret; - } - - // mask off b0/d0 registers - if ((((addr & 0xFFF0) == 0x3D0 - || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) - && !(nv4->nvbase.svga.miscout & 1)) - addr ^= 0x60; - - switch (addr) - { - // Alias for "get current SVGA CRTC register ID" - case NV4_CIO_CRX_COLOR: - ret = nv4->nvbase.svga.crtcreg; - break; - case NV4_CIO_CR_COLOR: - // Support the extended NVIDIA CRTC register range - switch (nv4->nvbase.svga.crtcreg) - { - case NV4_CIO_CRE_RL0_INDEX: - ret = nv4->nvbase.svga.displine & 0xFF; - break; - /* Is rl1?*/ - case NV4_CIO_CRE_RL1_INDEX: - ret = (nv4->nvbase.svga.displine >> 8) & 7; - break; - case NV4_CIO_CRE_DDC_STATUS_INDEX: - ret = i2c_gpio_get_sda(nv4->nvbase.i2c) << 3 - | i2c_gpio_get_scl(nv4->nvbase.i2c) << 2; - - break; - default: - ret = nv4->nvbase.svga.crtc[nv4->nvbase.svga.crtcreg]; - } - break; - default: - ret = svga_in(addr, &nv4->nvbase.svga); - break; - } - - - return ret; //TEMP -} - -// Write to SVGA core memory -void nv4_svga_write(uint16_t addr, uint8_t val, void* priv) -{ - // sanity check - if (!nv4) - return; - - // If we need to RMA to GPU MMIO, go do that - if (addr >= NV4_RMA_REGISTER_START - && addr <= NV4_RMA_REGISTER_END) - { - // we don't need to store these registers... - nv4->pbus.rma.rma_regs[addr & 3] = val; - - if (!(nv4->pbus.rma.mode & 0x01)) // we are halfway through sending something - return; - - uint32_t real_rma_write_addr = ((nv4->pbus.rma.mode & (0x0E)) << 1) + (addr & 0x03); - - nv4_rma_write(real_rma_write_addr, nv4->pbus.rma.rma_regs[addr & 0x03]); - return; - } - - // mask off b0/d0 registers - if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) - && addr < 0x3de) - && !(nv4->nvbase.svga.miscout & 1))//miscout bit 7 controls mappping - addr ^= 0x60; - - uint8_t crtcreg = nv4->nvbase.svga.crtcreg; - uint8_t old_val = 0x00; - - // todo: - // Pixel formats (8bit vs 555 vs 565) - // VBE 3.0? - - switch (addr) - { - case NV4_CIO_CRX_COLOR: - // real mode access to GPU MMIO space... - nv4->nvbase.svga.crtcreg = val; - break; - // support the extended crtc regs and debug this out - case NV4_CIO_CR_COLOR: - - // Implements the VGA Protect register - if ((nv4->nvbase.svga.crtcreg < NV4_CIO_CR_OVL_INDEX) && (nv4->nvbase.svga.crtc[NV4_CIO_CR_VRE_INDEX] & 0x80)) - return; - - // Ignore certain bits when VGA Protect register set and we are writing to CRTC register=07h - if ((nv4->nvbase.svga.crtcreg == NV4_CIO_CR_OVL_INDEX) && (nv4->nvbase.svga.crtc[NV4_CIO_CR_VRE_INDEX] & 0x80)) - val = (nv4->nvbase.svga.crtc[NV4_CIO_CR_OVL_INDEX] & ~0x10) | (val & 0x10); - - // set the register value... - old_val = nv4->nvbase.svga.crtc[crtcreg]; - - nv4->nvbase.svga.crtc[crtcreg] = val; - // ...now act on it - - // Handle nvidia extended Bank0/Bank1 IDs - switch (crtcreg) - { - case NV4_CIO_CRE_PAGE0_INDEX: - nv4->nvbase.cio_read_bank = val; - if (nv4->nvbase.svga.chain4) // chain4 addressing (planar?) - nv4->nvbase.svga.read_bank = nv4->nvbase.cio_read_bank << 15; - else - nv4->nvbase.svga.read_bank = nv4->nvbase.cio_read_bank << 13; // extended bank numbers - break; - case NV4_CIO_CRE_PAGE1_INDEX: - nv4->nvbase.cio_write_bank = val; - if (nv4->nvbase.svga.chain4) - nv4->nvbase.svga.write_bank = nv4->nvbase.cio_write_bank << 15; - else - nv4->nvbase.svga.write_bank = nv4->nvbase.cio_write_bank << 13; - break; - case NV4_CIO_CRE_RMA_INDEX: - nv4->pbus.rma.mode = val & NV4_PRMIO_RMA_MODE_MAX; - break; - /* Handle some large screen stuff */ - case NV4_CIO_CRE_PIXEL_INDEX: - if (val & 1 << (NV4_CIO_CRE_LSR_VDT_10)) - nv4->nvbase.svga.vtotal += 0x400; - if (val & 1 << (NV4_CIO_CRE_LSR_VRS_10)) - nv4->nvbase.svga.vblankstart += 0x400; - if (val & 1 << (NV4_CIO_CRE_LSR_VBS_10)) - nv4->nvbase.svga.vsyncstart += 0x400; - if (val & 1 << (NV4_CIO_CRE_LSR_HBE_6)) - nv4->nvbase.svga.hdisp += 0x400; - - /* Make sure dispend and vblankstart are right if we are displaying above 1024 vert */ - if (nv4->nvbase.svga.crtc[NV4_CIO_CRE_PIXEL_INDEX] & 1 << (NV4_CIO_CRE_LSR_VDE_10)) - nv4->nvbase.svga.dispend += 0x400; - - break; - case NV4_CIO_CRE_HEB_INDEX: // large screen bit - if (val & 0x01) - nv4->nvbase.svga.hdisp += 0x100; - break; - case NV4_CIO_CRE_DDC_WR_INDEX: - { - uint8_t scl = !!(val & 0x20); - uint8_t sda = !!(val & 0x10); - // Set an I2C GPIO register - i2c_gpio_set(nv4->nvbase.i2c, scl, sda); - break; - } - /* [6:0] contains cursorAddr [23:17] */ - case NV4_CIO_CRE_HCUR_ADDR0_INDEX: - nv4->pramdac.cursor_address |= (val & 0x7F) << 13; //bit7 technically ignored, but nv don't care, so neither do we - break; - /* [7:2] contains cursorAddr [16:11] */ - case NV4_CIO_CRE_HCUR_ADDR1_INDEX: - nv4->pramdac.cursor_address |= (val & 0xFC) << 5; // bit0 and 1 aren't part of the address - break; - - - } - - /* Recalculate the timings if we actually changed them - Additionally only do it if the value actually changed*/ - if (old_val != val) - { - // Thx to Fuel who basically wrote most of the SVGA compatibility code already (although I fixed some issues), because VGA is boring - // and in the words of an ex-Rendition/3dfx/NVIDIA engineer, "VGA was basically an undocumented bundle of steaming you-know-what. - // And it was essential that any cores the PC 3D startups acquired had to work with all the undocumented modes and timing tweaks (mode X, etc.)" - if (nv4->nvbase.svga.crtcreg < 0xE - || nv4->nvbase.svga.crtcreg > 0x10) - { - nv4->nvbase.svga.fullchange = changeframecount; - nv4_recalc_timings(&nv4->nvbase.svga); - } - } - - break; - default: - svga_out(addr, val, &nv4->nvbase.svga); - break; - } - -} - -/* DFB, sets up a dumb framebuffer */ -uint8_t nv4_dfb_read8(uint32_t addr, void* priv) -{ - addr &= (nv4->nvbase.svga.vram_mask); - return nv4->nvbase.svga.vram[addr]; -} - -uint16_t nv4_dfb_read16(uint32_t addr, void* priv) -{ - addr &= (nv4->nvbase.svga.vram_mask); - return (nv4->nvbase.svga.vram[addr + 1] << 8) | nv4->nvbase.svga.vram[addr]; -} - -uint32_t nv4_dfb_read32(uint32_t addr, void* priv) -{ - addr &= (nv4->nvbase.svga.vram_mask); - return (nv4->nvbase.svga.vram[addr + 3] << 24) | (nv4->nvbase.svga.vram[addr + 2] << 16) + - (nv4->nvbase.svga.vram[addr + 1] << 8) | nv4->nvbase.svga.vram[addr]; -} - -void nv4_dfb_write8(uint32_t addr, uint8_t val, void* priv) -{ - addr &= (nv4->nvbase.svga.vram_mask); - nv4->nvbase.svga.vram[addr] = val; - nv4->nvbase.svga.changedvram[addr >> 12] = val; - //nv4_render_current_bpp_dfb_8(addr); -} - -void nv4_dfb_write16(uint32_t addr, uint16_t val, void* priv) -{ - addr &= (nv4->nvbase.svga.vram_mask); - nv4->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; - nv4->nvbase.svga.vram[addr] = (val) & 0xFF; - nv4->nvbase.svga.changedvram[addr >> 12] = val; - - //nv4_render_current_bpp_dfb_16(addr); - -} - -void nv4_dfb_write32(uint32_t addr, uint32_t val, void* priv) -{ - addr &= (nv4->nvbase.svga.vram_mask); - nv4->nvbase.svga.vram[addr + 3] = (val >> 24) & 0xFF; - nv4->nvbase.svga.vram[addr + 2] = (val >> 16) & 0xFF; - nv4->nvbase.svga.vram[addr + 1] = (val >> 8) & 0xFF; - nv4->nvbase.svga.vram[addr] = (val) & 0xFF; - nv4->nvbase.svga.changedvram[addr >> 12] = val; - - //removed until there is a render pipeline - //nv4_render_current_bpp_dfb_32(addr); - -} - -/* Cursor shit */ -void nv4_draw_cursor(svga_t* svga, int32_t drawline) -{ - // sanity check - if (!nv4) - return; - - /* - Commented out until we have a real graphics pipeline going here - - // if cursor disabled is set, return - if ((nv4->nvbase.svga.crtc[NV4_CRTC_REGISTER_CURSOR_START] >> NV4_CRTC_REGISTER_CURSOR_START_DISABLED) & 0x01) - return; - - // NT GDI drivers: Load cursor using NV_IMAGE_FROM_MEMORY ("NV4LCD") - // 9x GDI drivers: Use H/W cursor in RAMIN - - // Do we need to emulate it? - - // THIS IS CORRECT. BUT HOW DO WE FIND IT? - uint32_t ramin_cursor_position = NV4_RAMIN_OFFSET_CURSOR; - - /* let's just assume buffer 0 here...that code needs to be totally rewritten - nv4_coord_16_t start_position = nv4->pramdac.cursor_start; - - /* refuse to draw if thge cursor is offscreen - if (start_position.x >= nv4->nvbase.svga.hdisp - || start_position.y >= nv4->nvbase.svga.dispend) - { - return; - } - - nv_log("nv4_draw_cursor start=0x%04x,0x%04x", start_position.x, start_position.y); - - uint32_t final_position = nv4_render_get_vram_address_for_buffer(start_position, 0); - - uint16_t* vram_16 = (uint16_t*)nv4->nvbase.svga.vram; - uint32_t* vram_32 = (uint32_t*)nv4->nvbase.svga.vram; - - /* - We have to get a 32x32, "A"1R5G5B5-format cursor - out of video memory. The alpha bit actually means - XOR with display pixel if 0, replace if 1 - - These are expanded to RGB10 only if they are XORed. We don't do this (we don't really need to + there is no grobj specified here so special casing - would be needed) so we just xor it with the current pixel format - - for (int32_t y = 0; y < NV4_PRAMDAC_CURSOR_SIZE_Y; y++) - { - for (int32_t x = 0; x < NV4_PRAMDAC_CURSOR_SIZE_X; x++) - { - uint16_t current_pixel = nv4_ramin_read16(ramin_cursor_position, nv4); - - // 0000 = transparent, so skip drawing - if (current_pixel) - { - bool replace_bit = (current_pixel & 0x8000); - - // use buffer 0 BPIXEL - uint32_t bpixel_format = (nv4->pgraph.bpixel[0]) & 0x03; - - switch (bpixel_format) - { - case bpixel_fmt_8bit: - if (replace_bit) - nv4->nvbase.svga.vram[final_position] = current_pixel; - else //xor - { - // not sure what to do here. we'd have to search through the palette to find the closest possible colour. - uint8_t final = current_pixel ^ nv4->nvbase.svga.vram[final_position]; - nv4->nvbase.svga.vram[final_position] = final; - } - case bpixel_fmt_16bit: // easy case (our cursor is 15bpp format) - uint32_t index_16 = final_position >> 1; - - if (replace_bit) // just replace - vram_16[index_16] = current_pixel; - else // xor - { - current_pixel &= ~0x8000; // mask off the xor bit - uint16_t final = current_pixel ^ vram_16[index_16]; - vram_16[index_16] = final; - } - case bpixel_fmt_32bit: - uint32_t index_32 = final_position >> 2; - - if (replace_bit) // just replace - vram_32[index_32] = nv4->nvbase.svga.conv_16to32(&nv4->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here - else //xor - { - current_pixel &= ~0x8000; // mask off the xor bit - uint32_t current_pixel_32 = nv4->nvbase.svga.conv_16to32(&nv4->nvbase.svga, current_pixel, 15); // 565_MODE doesn't seem to matter here - - uint32_t final = current_pixel_32 ^ vram_32[index_32]; - vram_32[index_32] = final; - } - break; - } - } - - // increment vram position - ramin_cursor_position += 2; - - // go - switch (nv4->nvbase.svga.bpp) - { - case 8: - final_position++; - case 15 ... 16: - final_position += 2; - break; - case 32: - final_position += 4; - break; - } - - start_position.x++; - } - - - start_position.y++; - start_position.x = nv4->pramdac.cursor_start.x; - - // reset at the end of each line so we "jump" to the start x - final_position = nv4_render_get_vram_address_for_buffer(start_position, 0); - }*/ -} - -// MMIO 0x110000->0x111FFF is mapped to a mirror of the VBIOS. -// Note this area is 64kb and the vbios is only 32kb. See below.. - -uint8_t nv4_prom_read(uint32_t address) -{ - // prom area is 64k, so... - // first see if we even have a rom of 64kb in size - uint32_t max_rom_size = NV4_PROM_END - NV4_PROM_START; - uint32_t real_rom_size = max_rom_size; - - // set it - if (nv4->nvbase.vbios.sz < max_rom_size) - real_rom_size = nv4->nvbase.vbios.sz; - - //get our real address - uint8_t rom_address = address & max_rom_size; - - // Does this mirror on real hardware? - if (rom_address >= real_rom_size) - { - nv_log("PROM VBIOS Read to INVALID address 0x%05x, returning 0xFF", rom_address); - return 0xFF; - } - else - { - uint8_t val = nv4->nvbase.vbios.rom[rom_address]; - nv_log("PROM VBIOS Read 0x%05x <- 0x%05x", val, rom_address); - return val; - } -} - -void nv4_prom_write(uint32_t address, uint32_t value) -{ - uint32_t real_addr = address & 0x1FFFF; - nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", real_addr, value); -} diff --git a/src/video/nv/nv4/nv4_debug_register_list.c b/src/video/nv/nv4/nv4_debug_register_list.c deleted file mode 100644 index 32516be0c..000000000 --- a/src/video/nv/nv4/nv4_debug_register_list.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * NV4 debug register list - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/pci.h> -#include <86box/rom.h> -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv4.h> - -#ifdef NV_LOG - -nv_register_t nv4_registers[] = { - { NV4_PTIMER_INTR, "NV4 PTIMER - Interrupt Status", NULL, NULL}, - { NV4_PTIMER_INTR_EN, "NV4 PTIMER - Interrupt Enable", NULL, NULL,}, - { NV4_PTIMER_NUMERATOR, "NV4 PTIMER - Numerator", NULL, NULL, }, - { NV4_PTIMER_DENOMINATOR, "NV4 PTIMER - Denominator", NULL, NULL, }, - { NV4_PTIMER_TIME_0_NSEC, "NV4 PTIMER - Time0", NULL, NULL, }, - { NV4_PTIMER_TIME_1_NSEC, "NV4 PTIMER - Time1", NULL, NULL, }, - { NV4_PTIMER_ALARM_NSEC, "NV4 PTIMER - Alarm", NULL, NULL, }, - { NV4_PRAMDAC_VPLL_COEFF, "NV4 PRAMDAC - Pixel Clock Coefficient", NULL, NULL, }, - { NV4_PRAMDAC_NVPLL_COEFF, "NV4 PRAMDAC - GPU Core Clock Coefficient", NULL, NULL, }, - { NV4_PRAMDAC_MPLL_COEFF, "NV4 PRAMDAC - VRAM Clock Coefficient", NULL, NULL, }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -#endif \ No newline at end of file diff --git a/src/video/nv/nv4/subsystems/nv4_pramdac.c b/src/video/nv/nv4/subsystems/nv4_pramdac.c deleted file mode 100644 index 0b8292796..000000000 --- a/src/video/nv/nv4/subsystems/nv4_pramdac.c +++ /dev/null @@ -1,84 +0,0 @@ -/* -* 86Box A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* This file is part of the 86Box distribution. -* -* NV4/Riva TNT - RAMDAC -* -* -* Authors: Connor Hyde, I need a better email address ;^) -* -* Copyright 2024-2025 starfrost -*/ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv4.h> - - -uint64_t nv4_pramdac_get_hz(uint32_t coeff, bool apply_divider) -{ - uint32_t m = coeff & 0xFF; - uint32_t n = (coeff >> 8) & 0xFF; - uint32_t p = (coeff >> 16) & 0x07; - - // Check clock base - uint32_t hz_base = (nv4->straps & (1 << NV4_STRAP_CRYSTAL)) ? 14318180 : 13500000; - uint32_t final_hz = (hz_base * n) / (m << p); - - // Check VCLK divider - - if (apply_divider) - { - if (nv4->pramdac.clk_coeff_select & (1 << NV4_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO)) - final_hz >>= 1; - } - - return final_hz; -} - -void nv4_pramdac_set_vclk() -{ - uint64_t final_hz = nv4_pramdac_get_hz(nv4->pramdac.nvclk, false); - - //TODO: Everything - if (nv4->nvbase.nv4_vclk_timer) - timer_set_delay_u64(nv4->nvbase.nv4_vclk_timer, final_hz / TIMER_USEC); - -} - -uint32_t nv4_pramdac_read(uint32_t address) -{ - uint32_t ret = 0x00; - - switch (address) - { - case NV4_PRAMDAC_VPLL_COEFF: // Pixel clock - ret = nv4->pramdac.vclk; - break; - case NV4_PRAMDAC_NVPLL_COEFF: // System clock - ret = nv4->pramdac.nvclk; - break; - case NV4_PRAMDAC_MPLL_COEFF: // Memory clock - ret = nv4->pramdac.mclk; - break; - - } -} - -void nv4_pramdac_write(uint32_t address, uint32_t data) -{ - -} diff --git a/src/video/nv/nv4/subsystems/nv4_ptimer.c b/src/video/nv/nv4/subsystems/nv4_ptimer.c deleted file mode 100644 index 29df0168b..000000000 --- a/src/video/nv/nv4/subsystems/nv4_ptimer.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Nvidia RIVA TNT (NV4 architecture) - Timer emulation - * - * - * - * Authors: Connor Hyde, - * - * Copyright 2024-2025 starfrost - */ - -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/device.h> -#include <86box/mem.h> -#include <86box/pci.h> -#include <86box/rom.h> // DEPENDENT!!! -#include <86box/video.h> -#include <86box/nv/vid_nv.h> -#include <86box/nv/vid_nv4.h> - -nv_register_t ptimer_registers[] = { - { NV4_PTIMER_INTR, "NV4 PTIMER - Interrupt Status", NULL, NULL}, - { NV4_PTIMER_INTR_EN, "NV4 PTIMER - Interrupt Enable", NULL, NULL,}, - { NV4_PTIMER_NUMERATOR, "NV4 PTIMER - Numerator", NULL, NULL, }, - { NV4_PTIMER_DENOMINATOR, "NV4 PTIMER - Denominator", NULL, NULL, }, - { NV4_PTIMER_TIME_0_NSEC, "NV4 PTIMER - Time0", NULL, NULL, }, - { NV4_PTIMER_TIME_1_NSEC, "NV4 PTIMER - Time1", NULL, NULL, }, - { NV4_PTIMER_ALARM_NSEC, "NV4 PTIMER - Alarm", NULL, NULL, }, - { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value -}; - -// ptimer init code -void nv4_ptimer_init(void) -{ - nv_log("Initialising PTIMER..."); - - nv_log("Done!\n"); -} - -// Handles the PTIMER alarm interrupt -void nv4_ptimer_interrupt(uint32_t num) -{ - nv4->ptimer.interrupt_status |= (1 << num); - - //todo - //nv4_pmc_handle_interrupts(true); -} - -// Ticks the timer. -void nv4_ptimer_tick(double real_time) -{ - // prevent a divide by zero - if (nv4->ptimer.clock_numerator == 0 - || nv4->ptimer.clock_denominator == 0) - return; - - // get the current time - - // See Envytools. We need to use the frequency as a source. - // We need to figure out how many cycles actually occurred because this counts up every cycle... - // However it seems that their formula is wrong. I can't be bothered to figure out what's going on and, based on documentation from NVIDIA, - // timer_0 is meant to roll over every 4 seconds. Multiplying by 10 basically does the job. - - // Convert to microseconds - double freq_base = (real_time / 1000000.0f) / ((double)1.0 / nv4->nvbase.memory_clock_frequency) * 10.0f; - double current_time = freq_base * ((double)nv4->ptimer.clock_numerator) / (double)nv4->ptimer.clock_denominator; // *10.0? - - // truncate it - nv4->ptimer.time += (uint64_t)current_time; - - // Check if the alarm has actually triggered.. - // Only log on ptimer alarm. Otherwise, it's too much spam. - if (nv4->ptimer.time >= nv4->ptimer.alarm) - { - nv_log_verbose_only("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv4->ptimer.alarm); - nv4_ptimer_interrupt(NV4_PTIMER_INTR_ALARM); - } -} - -uint32_t nv4_ptimer_read(uint32_t address) -{ - // always enabled - - nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - - // Only log these when tehy actually tick - if (address != NV4_PTIMER_TIME_0_NSEC - && address != NV4_PTIMER_TIME_1_NSEC) - { - nv_log_verbose_only("PTIMER Read from 0x%08x", address); - } - - uint32_t ret = 0x00; - - // if the register actually exists - if (reg) - { - // on-read function - if (reg->on_read) - ret = reg->on_read(); - else - { - // Interrupt state: - // Bit 0: Alarm - - switch (reg->address) - { - case NV4_PTIMER_INTR: - ret = nv4->ptimer.interrupt_status; - break; - case NV4_PTIMER_INTR_EN: - ret = nv4->ptimer.interrupt_enable; - break; - case NV4_PTIMER_NUMERATOR: - ret = nv4->ptimer.clock_numerator; // 15:0 - break; - case NV4_PTIMER_DENOMINATOR: - ret = nv4->ptimer.clock_denominator ; //15:0 - break; - // 64-bit value - // High part - case NV4_PTIMER_TIME_0: - ret = nv4->ptimer.time & 0xFFFFFFFF; //28:0 - break; - // Low part - case NV4_PTIMER_TIME_1: - ret = nv4->ptimer.time >> 32; // 31:5 - break; - case NV4_PTIMER_ALARM: - ret = nv4->ptimer.alarm; // 31:5 - break; - } - - } - //TIME0 and TIME1 produce too much log spam that slows everything down - if (reg->address != NV4_PTIMER_TIME_0_NSEC - && reg->address != NV4_PTIMER_TIME_1_NSEC) - { - if (reg->friendly_name) - nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name); - else - nv_log_verbose_only("\n"); - } - } - else - { - nv_log(": Unknown register read (address=0x%08x), returning 0x00\n", address); - } - - return ret; -} - -void nv4_ptimer_write(uint32_t address, uint32_t value) -{ - // before doing anything, check the subsystem enablement - nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0])); - - nv_log_verbose_only("PTIMER Write 0x%08x -> 0x%08x", value, address); - - // if the register actually exists - if (reg) - { - if (reg->friendly_name) - nv_log_verbose_only(": %s\n", reg->friendly_name); - else - nv_log_verbose_only("\n"); - - // on-read function - if (reg->on_write) - reg->on_write(value); - else - { - switch (reg->address) - { - // Interrupt state: - // Bit 0 - Alarm - - case NV4_PTIMER_INTR: - nv4->ptimer.interrupt_status &= ~value; - //TODO nv4_pmc_clear_interrupts(); - break; - - // Interrupt enablement state - case NV4_PTIMER_INTR_EN: - nv4->ptimer.interrupt_enable = value & 0x1; - break; - // nUMERATOR - case NV4_PTIMER_NUMERATOR: - nv4->ptimer.clock_numerator = value & 0xFFFF; // 15:0 - break; - case NV4_PTIMER_DENOMINATOR: - // prevent Div0 - if (!value) - value = 1; - - nv4->ptimer.clock_denominator = value & 0xFFFF; //15:0 - break; - // 64-bit value - // High part - case NV4_PTIMER_TIME_0: - nv4->ptimer.time |= (value) & 0xFFFFFFE0; //28:0 - break; - // Low part - case NV4_PTIMER_TIME_1: - nv4->ptimer.time |= ((uint64_t)(value & 0xFFFFFFE0) << 32); // 31:5 - break; - case NV4_PTIMER_ALARM: - nv4->ptimer.alarm = value & 0xFFFFFFE0; // 31:5 - break; - } - } - } - else /* Completely unknown */ - { - nv_log(": Unknown register write (address=0x%08x)\n", address); - } -} \ No newline at end of file diff --git a/src/video/nv/nv_base.c b/src/video/nv/nv_base.c deleted file mode 100644 index c7a83d5ad..000000000 --- a/src/video/nv/nv_base.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Base file for emulation of NVidia video cards. - * - * - * - * Authors: Connor Hyde, I need a better email address ;^) - * - * Copyright 2024-2025 starfrost - */ - -// Common NV1/3/4... init -#define HAVE_STDARG_H // wtf is this crap -#include -#include -#include -#include -#include <86box/86box.h> -#ifndef RELEASE_BUILD -#include <86box/device.h> -#endif -#include <86box/log.h> - - -// Common logging -#ifdef ENABLE_NV_LOG -int nv_do_log = ENABLE_NV_LOG; - -// A bit of kludge so that in the future we can abstract this function acorss multiple generations of Nvidia GPUs -void* nv_log_device; -bool nv_log_full = false; - -void nv_log_set_device(void* device) -{ - // in case the cyclical logger doesn't show you the full context of what went on, you can enable this debug feature - #ifndef RELEASE_BUILD - if (device - && device_get_config_int("nv_debug_fulllog")) - { - nv_log_full = true; - } - #endif - - nv_log_device = device; -} - -void nv_log_internal(const char* fmt, va_list arg) -{ - if (!nv_log_device) - return; - - // If our debug config option is configured, full log. Otherwise log with cyclical detection. - if (nv_log_full) - log_out(nv_log_device, fmt, arg); - else - log_out_cyclic(nv_log_device, fmt, arg); - -} - -void nv_log(const char *fmt, ...) -{ - va_list arg; - - if (!nv_do_log) - return; - - va_start(arg, fmt); - nv_log_internal(fmt, arg); - va_end(arg); -} - -void nv_log_verbose_only(const char *fmt, ...) -{ - #ifdef ENABLE_NV_LOG_ULTRA - va_list arg; - - if (!nv_do_log) - return; - - va_start(arg, fmt); - nv_log_internal(fmt, arg); - va_end(arg); - #endif -} - -#else -void nv_log(const char *fmt, ...) -{ - -} - -void nv_log_verbose_only(const char *fmt, ...) -{ - -} - -void nv_log_set_device(void* device) -{ - -} -#endif \ No newline at end of file diff --git a/src/video/vid_table.c b/src/video/vid_table.c index 3ea8a0358..4e76e150d 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -262,13 +262,6 @@ video_cards[] = { { .device = &compaq_voodoo_3_3500_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &voodoo_3_3500_se_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = &voodoo_3_3500_si_agp_device, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv1_device_edge2k, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv1_device_edge3k, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv3_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv3_device_pci, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv3t_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv3t_device_pci, .flags = VIDEO_FLAG_TYPE_NONE }, - { .device = &nv4_device_agp, .flags = VIDEO_FLAG_TYPE_NONE }, { .device = NULL, .flags = VIDEO_FLAG_TYPE_NONE } // clang-format on }; diff --git a/src/video/vid_voodoo.c b/src/video/vid_voodoo.c index 7ee3d9ae7..fe02b7811 100644 --- a/src/video/vid_voodoo.c +++ b/src/video/vid_voodoo.c @@ -675,7 +675,7 @@ voodoo_writel(uint32_t addr, uint32_t val, void *priv) default: if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE) { - voodoo_log(": Unknown register write in CMDFIFO mode %08x %08x\n", addr, val); + voodoo_log("Unknown register write in CMDFIFO mode %08x %08x\n", addr, val); } else { voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val); } From c1235e9ee7101d35a4259abd0a889118dfd4fa6b Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Sep 2025 01:08:51 +0200 Subject: [PATCH 246/274] RTL8019AS: Re-add the commented out CONFIG1 stuff, fixes PNPODI.COM. --- src/network/net_ne2000.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 2a9f3f551..5bb5fe7ad 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -583,11 +583,9 @@ static void nic_ioremove(nic_t *dev, uint16_t addr); static void nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) { -#if 0 uint8_t irq_map[16] = { 0x00, 0x00, 0x00, 0x10, 0x20, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x50, 0x60, 0x00, 0x00, 0x70 }; uint8_t ios = 0x00; -#endif if (ld) return; @@ -603,22 +601,18 @@ nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) nic_interrupt(dev, 0); dev->base_irq = config->irq[0].irq; -#if 0 if ((dev->base_irq >= 0x00) && (dev->base_irq <= 0x0f)) dev->config1 = (dev->config1 & 0x8f) | irq_map[dev->base_irq]; else dev->config1 = (dev->config1 & 0x8f); -#endif if (config->activate && (dev->base_address != ISAPNP_IO_DISABLED)) { nic_ioset(dev, dev->base_address); -#if 0 ios |= (dev->base_address & 0x0100) ? 0x00 : 0x04; ios |= (dev->base_address & 0x0080) ? 0x08 : 0x00; ios |= (dev->base_address & 0x0040) ? 0x02 : 0x00; ios |= (dev->base_address & 0x0020) ? 0x01 : 0x00; dev->config1 = (dev->config1 & 0xf0) | ios; -#endif } } From 58e397247d866d19b5b93990d48fc083b6fa6b1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miran=20Gr=C4=8Da?= Date: Thu, 25 Sep 2025 01:21:42 +0200 Subject: [PATCH 247/274] QT Renderer: current->setAttribute(Qt::WA_AlwaysStackOnTop); --- src/qt/qt_rendererstack.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/qt/qt_rendererstack.cpp b/src/qt/qt_rendererstack.cpp index 32b017b92..4a2e39bbe 100644 --- a/src/qt/qt_rendererstack.cpp +++ b/src/qt/qt_rendererstack.cpp @@ -441,6 +441,7 @@ RendererStack::createRenderer(Renderer renderer) current->setFocusProxy(this); current->setSizePolicy(QSizePolicy::Expanding, QSizePolicy::Expanding); current->setStyleSheet("background-color: black"); + current->setAttribute(Qt::WA_AlwaysStackOnTop); addWidget(current.get()); this->setStyleSheet("background-color: black"); From 4a84c0012c5290fa4f6914de539df42407c9aec8 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Sep 2025 03:03:58 +0200 Subject: [PATCH 248/274] ISA PnP: Improve I/O range check handling code. --- src/device/isapnp.c | 79 +++++++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 35 deletions(-) diff --git a/src/device/isapnp.c b/src/device/isapnp.c index 46cd52c24..d492957ed 100644 --- a/src/device/isapnp.c +++ b/src/device/isapnp.c @@ -465,9 +465,40 @@ isapnp_write_addr(UNUSED(uint16_t addr), uint8_t val, void *priv) } static void -isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uint8_t reg, uint8_t val) +isapnp_ld_io_remove(isapnp_device_t *ld) { uint16_t io_addr; + + for (uint8_t i = 0; i < 8; i++) { + if (!ld->io_len[i]) + continue; + + io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)]; + + io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); + } +} + +static void +isapnp_ld_io_set(isapnp_device_t *ld) +{ + uint16_t io_addr; + + for (uint8_t i = 0; i < 8; i++) { + if (!ld->io_len[i]) + continue; + + io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)]; + int ior = !(ld->regs[0x30] & 0x01) && (ld->regs[0x31] & 0x02); + + if (ior) + io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); + } +} + +static void +isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uint8_t reg, uint8_t val) +{ uint16_t reset_cards = 0; isapnp_log("ISAPnP: write_common(%02X, %02X)\n", reg, val); @@ -591,46 +622,22 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin break; case 0x30: /* Activate */ - CHECK_CURRENT_LD(); - - isapnp_log("ISAPnP: %sctivate CSN %02X device %02X\n", (val & 0x01) ? "A" : "Dea", card->csn, ld->number); - - ld->regs[reg] = val & 0x01; - isapnp_device_config_changed(card, ld); - - for (uint8_t i = 0; i < 8; i++) { - if (!ld->io_len[i]) - continue; - - io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)]; - if (val & 0x01) { - if (ld->regs[0x31] & 0x02) - io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); - } else { - if (ld->regs[0x31] & 0x02) - io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); - } - } - - break; - case 0x31: /* I/O Range Check */ CHECK_CURRENT_LD(); - for (uint8_t i = 0; i < 8; i++) { - if (!ld->io_len[i]) - continue; + isapnp_log("ISAPnP: %sctivate CSN %02X device %02X\n", (ld->regs[0x30] & 0x01) ? "A" : "Dea", + card->csn, ld->number); - io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)]; - if (ld->regs[reg] & 0x02) - io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); - if ((val & 0x02) && !(ld->regs[0x30] & 0x01)) - io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld); - } + isapnp_ld_io_remove(ld); + + if (reg == 0x30) + ld->regs[reg] = val & 0x01; + else + ld->regs[reg] = val & 0x03; + + isapnp_ld_io_set(ld); - ld->regs[reg] = val & 0x03; isapnp_device_config_changed(card, ld); - break; case 0x20 ... 0x2f: @@ -696,7 +703,9 @@ vendor_defined: break; } + isapnp_ld_io_remove(ld); ld->regs[reg] = val; + isapnp_ld_io_set(ld); isapnp_device_config_changed(card, ld); } break; From f0b20fddd5bee939cfc094269ec381a49ce70995 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Sep 2025 03:36:09 +0200 Subject: [PATCH 249/274] RTL8019AS: Fix base address when active at initialization. --- src/network/net_ne2000.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 5bb5fe7ad..25ba6a17a 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -1360,15 +1360,15 @@ nic_init(const device_t *info) if (!(dev->config3 & 0x01)) { uint8_t irq_map[8] = { 9, 3, 4, 5, 10, 11, 12, 15 }; - dev->base_address = 0x0000; - dev->base_irq = irq_map[(dev->config1 >> 4) & 0x07]; - - dev->base_address = (dev->config1 & 0x01) ? 0x0020 : 0x0000; + dev->base_address = 0x0200; + dev->base_address |= (dev->config1 & 0x01) ? 0x0020 : 0x0000; dev->base_address |= (dev->config1 & 0x02) ? 0x0040 : 0x0000; dev->base_address |= (dev->config1 & 0x04) ? 0x0000 : 0x0100; dev->base_address |= (dev->config1 & 0x08) ? 0x0080 : 0x0000; + dev->base_irq = irq_map[(dev->config1 >> 4) & 0x07]; + nic_ioset(dev, dev->base_address); isapnp_activate(dev->pnp_card, dev->base_address, dev->base_irq); From e7645e5c39135eecbf08c1440033d9c30fc2fb2a Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 25 Sep 2025 05:45:14 +0200 Subject: [PATCH 250/274] ISA PnP and RTL8019AS: More fixes - fixes I/O range check errors in jumperless mode. --- src/device/isapnp.c | 25 ++++++++++++++++++++----- src/network/net_ne2000.c | 27 +++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 9 deletions(-) diff --git a/src/device/isapnp.c b/src/device/isapnp.c index d492957ed..bc022ec43 100644 --- a/src/device/isapnp.c +++ b/src/device/isapnp.c @@ -77,6 +77,7 @@ enum { typedef struct _isapnp_device_ { uint8_t number; + uint8_t defs[256]; uint8_t regs[256]; uint8_t mem_upperlimit; uint8_t irq_types; @@ -278,6 +279,18 @@ isapnp_reset_ld_regs(isapnp_device_t *ld) /* Reset configuration registers to match the default configuration. */ isapnp_reset_ld_config(ld); + + if (ld->defs[0x30] != 0x00) + ld->regs[0x30] = ld->defs[0x30]; + + if (ld->defs[0x60] != 0x00) + ld->regs[0x60] = ld->defs[0x60]; + + if (ld->defs[0x61] != 0x00) + ld->regs[0x61] = ld->defs[0x61]; + + if (ld->defs[0x70] != 0x00) + ld->regs[0x70] = ld->defs[0x70]; } static uint8_t @@ -1251,12 +1264,14 @@ isapnp_activate(void *priv, uint16_t base, uint8_t irq) } if (ld != NULL) { - ld->regs[0x30] = 0x01; - ld->regs[0x60] = base >> 4; + ld->defs[0x30] = 0x01; + ld->defs[0x60] = base >> 8; if (!(ld->io_16bit & (1 << ((0x60 >> 1) & 0x07)))) - ld->regs[0x60] &= 0x03; - ld->regs[0x61] = base & 0x0f; - ld->regs[0x70] = irq; + ld->defs[0x60] &= 0x03; + ld->defs[0x61] = base & 0xff; + ld->defs[0x70] = irq; + + isapnp_reset_ld_regs(ld); } } diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 25ba6a17a..8f45c6dc1 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -172,6 +172,19 @@ nic_interrupt(void *priv, int set) } } +static void +nic_config_reset(void *priv) +{ + nic_t *dev = (nic_t *) priv; + uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); + + dev->config1 = (data[0x00] & 0x7f) | 0x80; + dev->config2 = (data[0x01] & 0xdf); + dev->config3 = (data[0x02] & 0xf7); + + isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); +} + /* reset - restore state to power-up, cancelling all i/o */ static void nic_reset(void *priv) @@ -181,6 +194,9 @@ nic_reset(void *priv) nelog(1, "%s: reset\n", dev->name); dp8390_reset(dev->dp8390); + + if (dev->board >= NE2K_RTL8019AS_PNP) + nic_config_reset(priv); } static void @@ -189,6 +205,9 @@ nic_soft_reset(void *priv) nic_t *dev = (nic_t *) priv; dp8390_soft_reset(dev->dp8390); + + if (dev->board >= NE2K_RTL8019AS_PNP) + nic_config_reset(priv); } /* @@ -423,7 +442,7 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) dev->config1 = (data[0x00] & 0x7f) | 0x80; dev->config2 = (data[0x01] & 0xdf); - dev->config3 = (data[0x02] & 0x77) | 0x80; + dev->config3 = (data[0x02] & 0xf7); dev->_9346cr = 0x21; isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); @@ -1957,7 +1976,7 @@ const device_t rtl8019as_pnp_device = { .local = NE2K_RTL8019AS_PNP, .init = nic_init, .close = nic_close, - .reset = NULL, + .reset = nic_config_reset, .available = rtl8019as_available, .speed_changed = NULL, .force_redraw = NULL, @@ -1971,7 +1990,7 @@ const device_t de220p_device = { .local = NE2K_DE220P, .init = nic_init, .close = nic_close, - .reset = NULL, + .reset = nic_config_reset, .available = de220p_available, .speed_changed = NULL, .force_redraw = NULL, @@ -1985,7 +2004,7 @@ const device_t rtl8029as_device = { .local = NE2K_RTL8029AS, .init = nic_init, .close = nic_close, - .reset = NULL, + .reset = nic_config_reset, .available = NULL, .speed_changed = NULL, .force_redraw = NULL, From 6cd9395d2c5277b90a146bf4961f1fb678305467 Mon Sep 17 00:00:00 2001 From: Toni Riikonen Date: Thu, 25 Sep 2025 20:23:08 +0300 Subject: [PATCH 251/274] Fixes merge problem --- src/floppy/fdd_audio.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/src/floppy/fdd_audio.c b/src/floppy/fdd_audio.c index 84fcee5a6..04ae9ba68 100644 --- a/src/floppy/fdd_audio.c +++ b/src/floppy/fdd_audio.c @@ -180,30 +180,13 @@ load_wav(const char *filename, int *sample_count) if ((filename == NULL) || (strlen(filename) == 0)) return NULL; - } if (strstr(filename, "..") != NULL) return NULL; - } f = rom_fopen(filename, "rb"); if (f == NULL) return NULL; - } - } - - path_append_filename(full_path, exe_path, "roms"); - path_append_filename(full_path, full_path, "samples"); - path_append_filename(full_path, full_path, "fdd"); - path_append_filename(full_path, full_path, filename); - f = fopen(full_path, "rb"); - if (!f) { - path_append_filename(full_path, full_path, "samples"); - path_append_filename(full_path, exe_path, filename); - f = fopen(full_path, "rb"); - if (!f) - return NULL; - } wav_header_t hdr; if (fread(&hdr, sizeof(hdr), 1, f) != 1) { From 9e1ec19860c4b93a69f8bcf51aa1719b1e15fb7d Mon Sep 17 00:00:00 2001 From: Alexander Babikov Date: Thu, 25 Sep 2025 22:54:16 +0500 Subject: [PATCH 252/274] Manager: Indicate Voodoo SLI in the details pane (#6223) --- src/qt/qt_vmmanager_system.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/qt/qt_vmmanager_system.cpp b/src/qt/qt_vmmanager_system.cpp index 988d3ed5e..dec503fce 100644 --- a/src/qt/qt_vmmanager_system.cpp +++ b/src/qt/qt_vmmanager_system.cpp @@ -654,6 +654,9 @@ VMManagerSystem::setupVars() { voodoo_name = tr("3Dfx Voodoo 2"); break; } + + if (voodoo_config["sli"].toInt() == 1) + voodoo_name.append(" (SLI)"); } display_table[VMManager::Display::Name::Voodoo] = voodoo_name; From 5ac9d65a8bc7c582d5cf098aa5eda3380938a831 Mon Sep 17 00:00:00 2001 From: OBattler Date: Fri, 26 Sep 2025 01:14:07 +0200 Subject: [PATCH 253/274] RTL8029AS: Do not call isapnp_set_normal() in nic_config_reset() on this card, fixes segmentation fault. --- src/network/net_ne2000.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 8f45c6dc1..bb3d82ad5 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -92,11 +92,12 @@ typedef struct nic_t { uint8_t csnsav; /* RTL8019AS/RTL8029AS registers */ + uint8_t _9346cr; uint8_t config0; uint8_t config1; uint8_t config2; uint8_t config3; - uint8_t _9346cr; + uint8_t res; uint8_t pci_regs[PCI_REGSIZE]; @@ -176,13 +177,15 @@ static void nic_config_reset(void *priv) { nic_t *dev = (nic_t *) priv; + uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom); dev->config1 = (data[0x00] & 0x7f) | 0x80; dev->config2 = (data[0x01] & 0xdf); dev->config3 = (data[0x02] & 0xf7); - isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); + if (dev->pnp_card != NULL) + isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); } /* reset - restore state to power-up, cancelling all i/o */ @@ -384,10 +387,20 @@ page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len)) ret = (dev->config3 & 0x46); break; + case 0x7: /* Reserved, Do not write */ + if (dev->board == NE2K_RTL8019AS_PNP) + ret = dev->res; + break; + case 0x8: /* CSNSAV */ ret = ((dev->board == NE2K_RTL8019AS_PNP) ? *dev->pnp_csnsav : 0x00); break; + case 0x9: case 0xa: + case 0xc: + ret = 0xff; + break; + case 0xb: /* INTR */ if (dev->board == NE2K_RTL8019AS_PNP) { ret = (pic2.irr & 0x02) ? 0x01 : 0x00; @@ -411,11 +424,15 @@ page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len)) case 0xe: /* 8029ASID0 */ if (dev->board == NE2K_RTL8029AS) ret = 0x29; + else + ret = 0xff; break; case 0xf: /* 8029ASID1 */ if (dev->board == NE2K_RTL8029AS) ret = 0x80; + else + ret = 0xff; break; } @@ -477,6 +494,11 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) } break; + case 0x7: /* Reserved, Do not write */ + if (dev->board == NE2K_RTL8019AS_PNP) + dev->res = val; + break; + case 0x09: /* HLTCLK */ break; From 086f955e7e468c33e210c6e901ac6d9d92a5d5fa Mon Sep 17 00:00:00 2001 From: OBattler Date: Fri, 26 Sep 2025 05:06:06 +0200 Subject: [PATCH 254/274] RTL8019AS: Implement active low IRQ mode, fixes RSET8019 IRQ detection. --- src/network/net_ne2000.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index bb3d82ad5..3b63c4db8 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -113,6 +113,7 @@ typedef struct nic_t { int is_mca; int is_8bit; int base_irq; + int irq_level; int has_bios; uint32_t base_address; @@ -154,6 +155,9 @@ nic_interrupt(void *priv, int set) nic_t *dev = (nic_t *) priv; int enabled = 1; + if (dev->irq_level) + set ^= 1; + if (dev->board == NE2K_RTL8019AS_PNP) enabled = dev->config1 & 0x80; @@ -183,6 +187,7 @@ nic_config_reset(void *priv) dev->config1 = (data[0x00] & 0x7f) | 0x80; dev->config2 = (data[0x01] & 0xdf); dev->config3 = (data[0x02] & 0xf7); + dev->irq_level = 0x02; if (dev->pnp_card != NULL) isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); @@ -200,6 +205,8 @@ nic_reset(void *priv) if (dev->board >= NE2K_RTL8019AS_PNP) nic_config_reset(priv); + else + dev->irq_level = 0x02; } static void @@ -211,6 +218,8 @@ nic_soft_reset(void *priv) if (dev->board >= NE2K_RTL8019AS_PNP) nic_config_reset(priv); + else + dev->irq_level = 0x02; } /* @@ -640,8 +649,10 @@ nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) dev->base_address = config->io[0].base; + dev->irq_level = 0x02; nic_interrupt(dev, 0); dev->base_irq = config->irq[0].irq; + dev->irq_level = config->irq[0].level; if ((dev->base_irq >= 0x00) && (dev->base_irq <= 0x0f)) dev->config1 = (dev->config1 & 0x8f) | irq_map[dev->base_irq]; else From 41809098406c5900724ffeb1124526862a00dff7 Mon Sep 17 00:00:00 2001 From: Verloren50000 <110334428+Verloren50000@users.noreply.github.com> Date: Fri, 26 Sep 2025 11:21:12 +0800 Subject: [PATCH 255/274] Add BIOS selector and the mid-1999 BIOS to the ABit AB-LX6 (#6224) * machine.h: Configuration added for ABit AB-LX6 * m_at_slot1.c: Configuration is almost there for ABit AB-LX6 * Congratulations! BIOS Selector for ABit AB-LX6 is complete. --- src/include/86box/machine.h | 3 +++ src/machine/m_at_slot1.c | 50 +++++++++++++++++++++++++++++++++---- src/machine/machine_table.c | 2 +- 3 files changed, 49 insertions(+), 6 deletions(-) diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 101ed2934..b88d8f492 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -1117,6 +1117,9 @@ extern int machine_at_p65up5_cpknd_init(const machine_t *); extern int machine_at_kn97_init(const machine_t *); /* i440LX */ +#ifdef EMU_DEVICE_H +extern const device_t lx6_device; +#endif extern int machine_at_lx6_init(const machine_t *); extern int machine_at_optiplexgxa_init(const machine_t *); extern int machine_at_spitfire_init(const machine_t *); diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c index 4c25799f6..22d6baac8 100644 --- a/src/machine/m_at_slot1.c +++ b/src/machine/m_at_slot1.c @@ -151,17 +151,57 @@ machine_at_kn97_init(const machine_t *model) } /* i440LX */ +static const device_config_t lx6_config[] = { + // clang-format off + { + .name = "bios", + .description = "BIOS Version", + .type = CONFIG_BIOS, + .default_string = "lx6", + .default_int = 0, + .file_filter = "", + .spinner = { 0 }, + .bios = { + { .name = "Award Modular BIOS v4.51PG - Revision LY", .internal_name = "lx6", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 131072, .files = { "roms/machines/lx6/LX6C_LY.BIN", "" } }, + { .name = "Award Modular BIOS v4.51PG - Revision PZ Beta", .internal_name = "lx6_beta", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 131072, .files = { "roms/machines/lx6/LX6C_PZ.B00", "" } }, + { .files_no = 0 } + }, + }, + { .name = "", .description = "", .type = CONFIG_END } + // clang-format on +}; + +const device_t lx6_device = { + .name = "ABIT AB-LX6", + .internal_name = "lx6_device", + .flags = 0, + .local = 0, + .init = NULL, + .close = NULL, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = lx6_config +}; + int machine_at_lx6_init(const machine_t *model) { - int ret; + int ret = 0; + const char* fn; - ret = bios_load_linear("roms/machines/lx6/LX6C_PZ.B00", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) + /* No ROMs available */ + if (!device_available(model->device)) return ret; + device_context(model->device); + fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0); + ret = bios_load_linear(fn, 0x000e0000, 131072, 0); + device_context_restore(); + machine_at_common_init_ex(model, 2); pci_init(PCI_CONFIG_TYPE_1); diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index cbc48db1d..8c9055c9b 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -17217,7 +17217,7 @@ const machine_t machines[] = { .kbc_p1 = 0x00000cf0, .gpio = 0xffffffff, .gpio_acpi = 0xffffffff, - .device = NULL, + .device = &lx6_device, .kbd_device = NULL, .fdc_device = NULL, .sio_device = NULL, From 60bef8bb48b37286148e910c608e9327f541cb0c Mon Sep 17 00:00:00 2001 From: OBattler Date: Fri, 26 Sep 2025 18:20:06 +0200 Subject: [PATCH 256/274] Ne2000-compatibles: Fix IRQ's (this will break RSET8019 again, I'm trying to understand now to fix it). --- src/device/isapnp.c | 10 +++++----- src/network/net_ne2000.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/device/isapnp.c b/src/device/isapnp.c index bc022ec43..34703820b 100644 --- a/src/device/isapnp.c +++ b/src/device/isapnp.c @@ -186,7 +186,7 @@ isapnp_device_config_changed(isapnp_card_t *card, isapnp_device_t *ld) for (uint8_t i = 0; i < 2; i++) { reg_base = 0x70 + (2 * i); card->config.irq[i].irq = ld->regs[reg_base]; - card->config.irq[i].level = ld->regs[reg_base + 1] & 0x02; + card->config.irq[i].level = !!(ld->regs[reg_base + 1] & 0x02); card->config.irq[i].type = ld->regs[reg_base + 1] & 0x01; } for (uint8_t i = 0; i < 2; i++) { @@ -268,13 +268,13 @@ isapnp_reset_ld_regs(isapnp_device_t *ld) /* Set the default IRQ type bits. */ for (uint8_t i = 0; i < 2; i++) { if (ld->irq_types & (0x1 << (4 * i))) - ld->regs[0x70 + (2 * i)] = 0x02; + ld->regs[0x71 + (2 * i)] = 0x02; else if (ld->irq_types & (0x2 << (4 * i))) - ld->regs[0x70 + (2 * i)] = 0x00; + ld->regs[0x71 + (2 * i)] = 0x00; else if (ld->irq_types & (0x4 << (4 * i))) - ld->regs[0x70 + (2 * i)] = 0x03; + ld->regs[0x71 + (2 * i)] = 0x03; else if (ld->irq_types & (0x8 << (4 * i))) - ld->regs[0x70 + (2 * i)] = 0x01; + ld->regs[0x71 + (2 * i)] = 0x01; } /* Reset configuration registers to match the default configuration. */ diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 3b63c4db8..c91fd9641 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -155,7 +155,7 @@ nic_interrupt(void *priv, int set) nic_t *dev = (nic_t *) priv; int enabled = 1; - if (dev->irq_level) + if (!dev->irq_level) set ^= 1; if (dev->board == NE2K_RTL8019AS_PNP) From edb7a040bca7fab126798e736a95f2a592deb421 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Fri, 26 Sep 2025 21:05:53 +0200 Subject: [PATCH 257/274] Some fixes for the AdLib Gold of the day (September 26th, 2025) (#6227) * AdLib Gold changes of the day (September 23rd, 2025) 1. Make sure the check to the Surround module is properly placed when disabled/enabled. 2. Replace local adgold_buffer with opl_buffer from its struct to improve the audio output and less clipping. * Some fixes for the AdLib Gold of the day (September 26th, 2025) 1. Revert the sampling DMA int functions back to void but with a check that monitors the DMA FIFO whenever it's within the range or not. 2. Actually clear the IRQ properly. --- src/sound/snd_adlibgold.c | 71 ++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 38 deletions(-) diff --git a/src/sound/snd_adlibgold.c b/src/sound/snd_adlibgold.c index 870e473b0..f8c89c554 100644 --- a/src/sound/snd_adlibgold.c +++ b/src/sound/snd_adlibgold.c @@ -91,6 +91,8 @@ typedef struct adgold_t { int gameport_enabled; int surround_enabled; + + int finish_dma; } adgold_t; static int attenuation[0x40]; @@ -174,33 +176,41 @@ adgold_update_irq_status(adgold_t *adgold) temp &= ~2; if ((adgold->adgold_mma_status & 0x02) && !(adgold->adgold_mma_regs[1][0xc] & 2)) temp &= ~2; + adgold->adgold_status = temp; - if ((adgold->adgold_status ^ 0xf) && !adgold->adgold_irq_status) { + if ((adgold->adgold_status ^ 0xf) && !adgold->adgold_irq_status) picint(1 << adgold->irq); - } + else if (!(adgold->adgold_status ^ 0xf) && adgold->adgold_irq_status) + picintc(1 << adgold->irq); adgold->adgold_irq_status = adgold->adgold_status ^ 0xf; } -int +void adgold_getsamp_dma(adgold_t *adgold, int channel) { - int temp; - dma_set_drq(adgold->dma, 1); + int dma_dat; - if ((adgold->adgold_mma_regs[channel][0xc] & 0x60) && (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= 127)) - return 2; + adgold->finish_dma = 0; - temp = dma_channel_read(adgold->dma); - if (temp == DMA_NODATA) { - return 1; + if ((adgold->adgold_mma_regs[channel][0xc] & 0x60) && (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= 127)) { + adgold->finish_dma = 1; + return; } - adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = temp; - adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255; + + dma_set_drq(adgold->dma, 1); + dma_dat = dma_channel_read(adgold->dma); + if (dma_dat == DMA_NODATA) + return; + + adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = dma_dat; + adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255; if (adgold->adgold_mma_regs[channel][0xc] & 0x60) { - temp = dma_channel_read(adgold->dma); - adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = temp; + dma_dat = dma_channel_read(adgold->dma); + if (dma_dat == DMA_NODATA) + return; + adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = dma_dat; adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255; } if (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= adgold->adgold_mma_intpos[channel]) { @@ -208,8 +218,6 @@ adgold_getsamp_dma(adgold_t *adgold, int channel) adgold_update_irq_status(adgold); dma_set_drq(adgold->dma, 0); } - - return 0; } void @@ -381,16 +389,10 @@ adgold_write(uint16_t addr, uint8_t val, void *priv) adgold->adgold_mma.voice_count[1] = adgold->adgold_mma.voice_latch[1]; while (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) { - if (adgold_getsamp_dma(adgold, 0)) { - adgold->adgold_mma_fifo_end[0] = 0; - adgold->adgold_mma_fifo_start[0] = 0; + adgold_getsamp_dma(adgold, 0); + adgold_getsamp_dma(adgold, 1); + if (adgold->finish_dma) break; - } - if (adgold_getsamp_dma(adgold, 1)) { - adgold->adgold_mma_fifo_end[1] = 0; - adgold->adgold_mma_fifo_start[1] = 0; - break; - } } if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) { adgold->adgold_mma_status &= ~0x01; @@ -404,11 +406,9 @@ adgold_write(uint16_t addr, uint8_t val, void *priv) } } else { while (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) { - if (adgold_getsamp_dma(adgold, 0)) { - adgold->adgold_mma_fifo_end[0] = 0; - adgold->adgold_mma_fifo_start[0] = 0; + adgold_getsamp_dma(adgold, 0); + if (adgold->finish_dma) break; - } } if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) { adgold->adgold_mma_status &= ~0x01; @@ -518,11 +518,9 @@ adgold_write(uint16_t addr, uint8_t val, void *priv) if (adgold->adgold_mma_regs[1][0xc] & 1) { while (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) < 128) { - if (adgold_getsamp_dma(adgold, 1)) { - adgold->adgold_mma_fifo_end[1] = 0; - adgold->adgold_mma_fifo_start[1] = 0; + adgold_getsamp_dma(adgold, 1); + if (adgold->finish_dma) break; - } } } } @@ -600,7 +598,6 @@ adgold_read(uint16_t addr, void *priv) temp = adgold->adgold_mma_status; adgold->adgold_mma_status &= ~0xf3; /*JUKEGOLD expects timer status flags to auto-clear*/ adgold_update_irq_status(adgold); - picintc(1 << adgold->irq); break; case 5: if (adgold->adgold_mma_addr >= 0xf) @@ -695,11 +692,9 @@ adgold_mma_poll(adgold_t *adgold, int channel) } if (adgold->adgold_mma_regs[channel][0xc] & 1) { - if (adgold_getsamp_dma(adgold, channel)) { - adgold->adgold_mma_fifo_end[channel] = 0; - adgold->adgold_mma_fifo_start[channel] = 0; + adgold_getsamp_dma(adgold, channel); + if (adgold->finish_dma) return; - } } if (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) < adgold->adgold_mma_intpos[channel] && !(adgold->adgold_mma_status & 0x01)) { adgold->adgold_mma_status |= (1 << channel); From 16c0460d61e6dc192444cd813559501422c89b33 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 26 Sep 2025 21:06:45 +0200 Subject: [PATCH 258/274] Bump SonarSource/sonarqube-scan-action from 5 to 6 in /.github/workflows (#6225) Bumps [SonarSource/sonarqube-scan-action](https://github.com/sonarsource/sonarqube-scan-action) from 5 to 6. - [Release notes](https://github.com/sonarsource/sonarqube-scan-action/releases) - [Commits](https://github.com/sonarsource/sonarqube-scan-action/compare/v5...v6) --- updated-dependencies: - dependency-name: SonarSource/sonarqube-scan-action dependency-version: '6' dependency-type: direct:production ... Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- .github/workflows/codeql_linux.yml | 4 ++-- .github/workflows/codeql_macos.yml | 4 ++-- .github/workflows/codeql_windows_msys2.yml | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/codeql_linux.yml b/.github/workflows/codeql_linux.yml index 957c7090b..855571782 100644 --- a/.github/workflows/codeql_linux.yml +++ b/.github/workflows/codeql_linux.yml @@ -121,7 +121,7 @@ jobs: fetch-depth: 0 # Shallow clones should be disabled for a better relevancy of analysis - name: Install Build Wrapper - uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v5 + uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v6 - name: Initialize CodeQL uses: github/codeql-action/init@v3 @@ -149,7 +149,7 @@ jobs: - name: SonarQube Scan if: matrix.build.preset == 'dev_debug' && matrix.dynarec.new == 'on' && matrix.ui.qt == 'on' && env.SONAR_TOKEN != '' # if: 0 - uses: SonarSource/sonarqube-scan-action@v5 + uses: SonarSource/sonarqube-scan-action@v6 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }} diff --git a/.github/workflows/codeql_macos.yml b/.github/workflows/codeql_macos.yml index 488cbfd49..74365cd56 100644 --- a/.github/workflows/codeql_macos.yml +++ b/.github/workflows/codeql_macos.yml @@ -109,7 +109,7 @@ jobs: fetch-depth: 0 # Shallow clones should be disabled for a better relevancy of analysis - name: Install Build Wrapper - uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v5 + uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v6 - name: Initialize CodeQL uses: github/codeql-action/init@v3 @@ -140,7 +140,7 @@ jobs: - name: SonarQube Scan # if: matrix.build.preset == 'dev_debug' && matrix.dynarec.new == 'on' && matrix.ui.qt == 'on' && env.SONAR_TOKEN != '' if: 0 - uses: SonarSource/sonarqube-scan-action@v5 + uses: SonarSource/sonarqube-scan-action@v6 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }} diff --git a/.github/workflows/codeql_windows_msys2.yml b/.github/workflows/codeql_windows_msys2.yml index d70c6fd5f..9673ab650 100644 --- a/.github/workflows/codeql_windows_msys2.yml +++ b/.github/workflows/codeql_windows_msys2.yml @@ -169,7 +169,7 @@ jobs: - name: SonarQube Scan # if: matrix.build.preset == 'dev_debug' && matrix.dynarec.new == 'on' && matrix.ui.qt == 'on' && env.SONAR_TOKEN != '' if: 0 - uses: SonarSource/sonarqube-scan-action@v5 + uses: SonarSource/sonarqube-scan-action@v6 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }} From ca1005817ab9f0a5614def2bbf73b42623755d86 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 27 Sep 2025 00:04:42 +0200 Subject: [PATCH 259/274] RTL8019AS: Properly fix the RSET8019 IRQ check (writing 0x00 to IMR clears IRQ, writing 0x80 to CONFIG1 sets IRQ, changing IRQ does not clear it). --- src/network/net_ne2000.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index c91fd9641..e9732fba8 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -481,8 +481,11 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len)) break; case 0x04: /* CONFIG1 */ - if (cfg_write_enable && (dev->board == NE2K_RTL8019AS_PNP)) + if (cfg_write_enable && (dev->board == NE2K_RTL8019AS_PNP)) { dev->config1 = (dev->config1 & 0x7f) | (val & 0x80); + if (val & 0x80) + nic_interrupt(dev, 1); + } break; case 0x05: /* CONFIG2 */ @@ -649,8 +652,6 @@ nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) dev->base_address = config->io[0].base; - dev->irq_level = 0x02; - nic_interrupt(dev, 0); dev->base_irq = config->irq[0].irq; dev->irq_level = config->irq[0].level; if ((dev->base_irq >= 0x00) && (dev->base_irq <= 0x0f)) From b8b8efd454d2d01d7b596cd753bb66d445bac752 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 27 Sep 2025 00:56:50 +0200 Subject: [PATCH 260/274] RTL8019AS: Inform ISA PnP of the I/O base address, configured in the EEPROM even if it's programmed to start inactive, fixes the remaining I/O range check errors in RSET8019. --- src/network/net_ne2000.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index e9732fba8..3e2e7dd38 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -1411,21 +1411,20 @@ nic_init(const device_t *info) isapnp_set_normal(dev->pnp_card, !!(dev->config3 & 0x80)); isapnp_set_single_ld(dev->pnp_card); - if (!(dev->config3 & 0x01)) { - uint8_t irq_map[8] = { 9, 3, 4, 5, 10, 11, 12, 15 }; + uint8_t irq_map[8] = { 9, 3, 4, 5, 10, 11, 12, 15 }; - dev->base_address = 0x0200; - dev->base_address |= (dev->config1 & 0x01) ? 0x0020 : 0x0000; - dev->base_address |= (dev->config1 & 0x02) ? 0x0040 : 0x0000; - dev->base_address |= (dev->config1 & 0x04) ? 0x0000 : 0x0100; - dev->base_address |= (dev->config1 & 0x08) ? 0x0080 : 0x0000; + dev->base_address = 0x0200; + dev->base_address |= (dev->config1 & 0x01) ? 0x0020 : 0x0000; + dev->base_address |= (dev->config1 & 0x02) ? 0x0040 : 0x0000; + dev->base_address |= (dev->config1 & 0x04) ? 0x0000 : 0x0100; + dev->base_address |= (dev->config1 & 0x08) ? 0x0080 : 0x0000; - dev->base_irq = irq_map[(dev->config1 >> 4) & 0x07]; + dev->base_irq = irq_map[(dev->config1 >> 4) & 0x07]; + if (!(dev->config3 & 0x01)) nic_ioset(dev, dev->base_address); - isapnp_activate(dev->pnp_card, dev->base_address, dev->base_irq); - } + isapnp_activate(dev->pnp_card, dev->base_address, dev->base_irq, !(dev->config3 & 0x01)); } } From 1dbc304b2f6c19a82d7172e09cfcde7c391417b3 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 27 Sep 2025 01:28:43 +0200 Subject: [PATCH 261/274] The forgotten isapnp.c and .h. --- src/device/isapnp.c | 4 ++-- src/include/86box/isapnp.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/device/isapnp.c b/src/device/isapnp.c index 34703820b..3129cd1c8 100644 --- a/src/device/isapnp.c +++ b/src/device/isapnp.c @@ -1252,7 +1252,7 @@ isapnp_set_normal(void *priv, uint8_t normal) } void -isapnp_activate(void *priv, uint16_t base, uint8_t irq) +isapnp_activate(void *priv, uint16_t base, uint8_t irq, int active) { isapnp_card_t *card = (isapnp_card_t *) priv; isapnp_device_t *ld = card->first_ld; @@ -1264,7 +1264,7 @@ isapnp_activate(void *priv, uint16_t base, uint8_t irq) } if (ld != NULL) { - ld->defs[0x30] = 0x01; + ld->defs[0x30] = active; ld->defs[0x60] = base >> 8; if (!(ld->io_16bit & (1 << ((0x60 >> 1) & 0x07)))) ld->defs[0x60] &= 0x03; diff --git a/src/include/86box/isapnp.h b/src/include/86box/isapnp.h index 7d730564a..9fedd656c 100644 --- a/src/include/86box/isapnp.h +++ b/src/include/86box/isapnp.h @@ -73,7 +73,7 @@ extern void isapnp_reset_card(void *priv); extern void isapnp_reset_device(void *priv, uint8_t ld); extern void isapnp_set_rt(void *priv, uint8_t is_rt); extern void isapnp_set_normal(void *priv, uint8_t normal); -extern void isapnp_activate(void *priv, uint16_t base, uint8_t irq); +extern void isapnp_activate(void *priv, uint16_t base, uint8_t irq, int active); extern void isapnp_set_single_ld(void *priv); extern uint8_t *isapnp_get_csnsav(void *priv); From 809e1f3efbb2695e9fd5d0f3107a1c32c3ee74fb Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 27 Sep 2025 04:16:01 +0200 Subject: [PATCH 262/274] Give the Jetway J-403TG with AMI BIOS the correct NVR device, fixes #6230. --- src/machine/m_at_socket3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/m_at_socket3.c b/src/machine/m_at_socket3.c index 8d460186c..d882dbd4d 100644 --- a/src/machine/m_at_socket3.c +++ b/src/machine/m_at_socket3.c @@ -216,7 +216,7 @@ machine_at_403tg_init(const machine_t *model) return ret; device_context(model->device); - int nvr_hack = !strcmp(device_get_config_bios("bios"), "403tg_d"); + int nvr_hack = !strcmp(device_get_config_bios("bios"), "403tg"); fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0); ret = bios_load_linear(fn, 0x000f0000, 65536, 0); From b1dfe5320c25cf21899d16af3d3459c64f032aa6 Mon Sep 17 00:00:00 2001 From: Toni Riikonen Date: Sat, 27 Sep 2025 09:54:41 +0300 Subject: [PATCH 263/274] Fixes #6220: OS/2 Warp 3.0 install disk issue and NT 3.1 floppy disk issues. Changed the fdc->stat bit to 0x10 which states fdc busy. Previous implementation with seek time 0, set the ready flag 0x80 immediadely - which was correct for that time, but now as the drive is busy during seek, the value should 0x10. Implemented a backup for fdd commands during fdd seek to be processes after the seek is completed. --- src/floppy/fdc.c | 1522 +++++++++++++++++++++++----------------------- src/floppy/fdd.c | 151 ++++- 2 files changed, 913 insertions(+), 760 deletions(-) diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index bcf4a1299..212bf9ce0 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -184,7 +184,7 @@ fdc_ctrl_reset(void *priv) { fdc_t *fdc = (fdc_t *) priv; - fdc->stat = 0x80; + fdc->stat = 0x10; fdc->pnum = fdc->ptot = 0; fdc->st0 = 0; fdc->head = 0; @@ -470,9 +470,9 @@ uint8_t fdc_get_shadow(fdc_t *fdc) { uint8_t ret = (fdc->rate & 0x03) | - ((fdc->pretrk & 0x07) << 2) | - (fdc->power_down ? 0x40 : 0x00) | - ((fdc_read(0x03f2, fdc) & 0x04) ? 0x80 : 0x00); + ((fdc->pretrk & 0x07) << 2) | + (fdc->power_down ? 0x40 : 0x00) | + ((fdc_read(0x03f2, fdc) & 0x04) ? 0x80 : 0x00); return ret; } @@ -532,36 +532,36 @@ fdc_update_rate(fdc_t *fdc, int drive) fdc->enh_mode && !(fdc->flags & FDC_FLAG_SMC661)) fdc->bit_rate = 500; else if ((fdc->rwc[drive] == 3) && fdc->enh_mode && - !(fdc->flags & FDC_FLAG_SMC661)) + !(fdc->flags & FDC_FLAG_SMC661)) fdc->bit_rate = 250; else switch (fdc->rate) { - default: - break; - case 0: /*High density*/ - fdc->bit_rate = 500; - break; - case 1: /*Double density (360 rpm)*/ - switch (fdc->drvrate[drive]) { - default: - break; - case 0: - fdc->bit_rate = 300; - break; - case 1: - fdc->bit_rate = 500; - break; - case 2: - fdc->bit_rate = 2000; - break; - } - break; - case 2: /*Double density*/ - fdc->bit_rate = 250; - break; - case 3: /*Extended density*/ - fdc->bit_rate = 1000; - break; - } + default: + break; + case 0: /*High density*/ + fdc->bit_rate = 500; + break; + case 1: /*Double density (360 rpm)*/ + switch (fdc->drvrate[drive]) { + default: + break; + case 0: + fdc->bit_rate = 300; + break; + case 1: + fdc->bit_rate = 500; + break; + case 2: + fdc->bit_rate = 2000; + break; + } + break; + case 2: /*Double density*/ + fdc->bit_rate = 250; + break; + case 3: /*Extended density*/ + fdc->bit_rate = 1000; + break; + } fdc->bitcell_period = (1000000 / fdc->bit_rate) * 2; /*Bitcell period in ns*/ } @@ -695,7 +695,7 @@ void fdc_seek(fdc_t *fdc, int drive, int params) { fdd_seek(real_drive(fdc, drive), params); - fdc->stat |= (1 << fdc->drive); + fdc->stat = (fdc->stat & 0x0F) | 0x10 | (1 << fdc->drive); } static void @@ -719,8 +719,10 @@ fdc_io_command_phase1(fdc_t *fdc, int out) fdc->dtl = fdc->params[7]; fdc->rw_track = fdc->params[1]; + int implied_seek = 0; if (fdc->config & 0x40) { if (fdc->rw_track != fdc->pcn[fdc->params[0] & 3]) { + implied_seek = 1; fdc_seek(fdc, fdc->drive, ((int) fdc->rw_track) - ((int) fdc->pcn[fdc->params[0] & 3])); fdc->pcn[fdc->params[0] & 3] = fdc->rw_track; } @@ -730,6 +732,12 @@ fdc_io_command_phase1(fdc_t *fdc, int out) ui_sb_update_icon_write(SB_FLOPPY | real_drive(fdc, fdc->drive), 1); else ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 1); + + if (implied_seek) { + fdc->stat = (fdc->stat & 0x0F) | 0x10 | (1 << real_drive(fdc, fdc->drive)); /* CB=1, per-drive busy */ + return; + } + fdc->stat = out ? 0x10 : 0x50; if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) { fdc->stat |= 0x20; @@ -791,7 +799,7 @@ fdc_soft_reset(fdc_t *fdc) } fdc_ctrl_reset(fdc); - } + } } static void @@ -806,565 +814,566 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) cycles -= ISA_CYCLES(8); - if (!fdc->power_down || ((addr & 7) == 2) || ((addr & 7) == 4)) switch (addr & 7) { - case 0: - return; - case 1: - return; - case 2: /*DOR*/ - if (fdc->flags & FDC_FLAG_PCJR) { - if ((fdc->dor & 0x40) && !(val & 0x40)) { - timer_set_delay_u64(&fdc->watchdog_timer, 1000 * TIMER_USEC); - fdc->watchdog_count = 1000; - picintc(1 << fdc->irq); - } - if ((val & 0x80) && !(fdc->dor & 0x80)) { - timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); - fdc->interrupt = -1; - ui_sb_update_icon(SB_FLOPPY | 0, 0); - ui_sb_update_icon_write(SB_FLOPPY | 0, 0); - fdc_ctrl_reset(fdc); - } - if (!fdd_get_flags(0)) - val &= 0xfe; - fdd_set_motor_enable(0, val & 0x01); - fdc->st0 &= ~0x07; - fdc->st0 |= (fdd_get_head(0) ? 4 : 0); - } else { - /* - Writing this bit to logic "1" will enable the DRQ, - nDACK, TC and FINTR outputs. This bit being a - logic "0" will disable the nDACK and TC inputs, and - hold the DRQ and FINTR outputs in a high - impedance state. - */ - if (!(val & 8) && (fdc->dor & 8) && !(fdc->flags & FDC_FLAG_PS2_MCA)) { - fdc->tc = 1; - fdc->fintr = 0; - picintc(1 << fdc->irq); - } - if (!(val & 4)) { - fdd_stop(real_drive(fdc, val & 3)); - fdc->stat = 0x00; - fdc->pnum = fdc->ptot = 0; - } - if ((val & 4) && !(fdc->dor & 4)) - fdc_soft_reset(fdc); - /* We can now simplify this since each motor now spins separately. */ - for (int i = 0; i < FDD_NUM; i++) { - drive_num = real_drive(fdc, i); - if ((!fdd_get_flags(drive_num)) || (drive_num >= FDD_NUM)) - val &= ~(0x10 << drive_num); - else - fdd_set_motor_enable(i, (val & (0x10 << drive_num))); - } - drive_num = real_drive(fdc, val & 0x03); - current_drive = drive_num; - fdc->st0 = (fdc->st0 & 0xf8) | (val & 0x03) | (fdd_get_head(drive_num) ? 4 : 0); - } - fdc->dor = val; - return; - case 3: /* TDR */ - if (fdc->enh_mode) { - if (fdc->flags & FDC_FLAG_SMC661) { - fdc_set_swap(fdc, !!(val & 0x20)); - fdc_update_densel_force(fdc, (val & 0x18) >> 3); + if (!fdc->power_down || ((addr & 7) == 2) || ((addr & 7) == 4)) + switch (addr & 7) { + case 0: + return; + case 1: + return; + case 2: /*DOR*/ + if (fdc->flags & FDC_FLAG_PCJR) { + if ((fdc->dor & 0x40) && !(val & 0x40)) { + timer_set_delay_u64(&fdc->watchdog_timer, 1000 * TIMER_USEC); + fdc->watchdog_count = 1000; + picintc(1 << fdc->irq); + } + if ((val & 0x80) && !(fdc->dor & 0x80)) { + timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); + fdc->interrupt = -1; + ui_sb_update_icon(SB_FLOPPY | 0, 0); + ui_sb_update_icon_write(SB_FLOPPY | 0, 0); + fdc_ctrl_reset(fdc); + } + if (!fdd_get_flags(0)) + val &= 0xfe; + fdd_set_motor_enable(0, val & 0x01); + fdc->st0 &= ~0x07; + fdc->st0 |= (fdd_get_head(0) ? 4 : 0); } else { - drive = real_drive(fdc, fdc->dor & 3); - fdc_update_rwc(fdc, drive, (val & 0x30) >> 4); + /* + Writing this bit to logic "1" will enable the DRQ, + nDACK, TC and FINTR outputs. This bit being a + logic "0" will disable the nDACK and TC inputs, and + hold the DRQ and FINTR outputs in a high + impedance state. + */ + if (!(val & 8) && (fdc->dor & 8) && !(fdc->flags & FDC_FLAG_PS2_MCA)) { + fdc->tc = 1; + fdc->fintr = 0; + picintc(1 << fdc->irq); + } + if (!(val & 4)) { + fdd_stop(real_drive(fdc, val & 3)); + fdc->stat = 0x00; + fdc->pnum = fdc->ptot = 0; + } + if ((val & 4) && !(fdc->dor & 4)) + fdc_soft_reset(fdc); + /* We can now simplify this since each motor now spins separately. */ + for (int i = 0; i < FDD_NUM; i++) { + drive_num = real_drive(fdc, i); + if ((!fdd_get_flags(drive_num)) || (drive_num >= FDD_NUM)) + val &= ~(0x10 << drive_num); + else + fdd_set_motor_enable(i, (val & (0x10 << drive_num))); + } + drive_num = real_drive(fdc, val & 0x03); + current_drive = drive_num; + fdc->st0 = (fdc->st0 & 0xf8) | (val & 0x03) | (fdd_get_head(drive_num) ? 4 : 0); } - } - /* Bit 2: FIFO test mode (PS/55 5550-S,T only. Undocumented) - The Power-on Self Test of PS/55 writes and verifies 8 bytes of FIFO buffer through I/O 3F5h. - If it fails, then floppy drives will be treated as DD drives. */ - if (fdc->flags & FDC_FLAG_PS2_MCA) { - if (val & 0x04) { - fdc->tfifo = 8; - fdc->fifointest = 1; - } else { - fdc->tfifo = 1; - fdc->fifointest = 0; + fdc->dor = val; + return; + case 3: /* TDR */ + if (fdc->enh_mode) { + if (fdc->flags & FDC_FLAG_SMC661) { + fdc_set_swap(fdc, !!(val & 0x20)); + fdc_update_densel_force(fdc, (val & 0x18) >> 3); + } else { + drive = real_drive(fdc, fdc->dor & 3); + fdc_update_rwc(fdc, drive, (val & 0x30) >> 4); + } } - fifo_reset(fdc->fifo_p); - fifo_set_len(fdc->fifo_p, fdc->tfifo + 1); - fifo_set_trigger_len(fdc->fifo_p, fdc->tfifo + 1); - } - return; - case 4: /* DSR */ - if (!(fdc->flags & FDC_FLAG_NO_DSR_RESET)) { - if (!(val & 0x80)) { - timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); - fdc->interrupt = -6; + /* Bit 2: FIFO test mode (PS/55 5550-S,T only. Undocumented) + The Power-on Self Test of PS/55 writes and verifies 8 bytes of FIFO buffer through I/O 3F5h. + If it fails, then floppy drives will be treated as DD drives. */ + if (fdc->flags & FDC_FLAG_PS2_MCA) { + if (val & 0x04) { + fdc->tfifo = 8; + fdc->fifointest = 1; + } else { + fdc->tfifo = 1; + fdc->fifointest = 0; + } + fifo_reset(fdc->fifo_p); + fifo_set_len(fdc->fifo_p, fdc->tfifo + 1); + fifo_set_trigger_len(fdc->fifo_p, fdc->tfifo + 1); } - if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) - fdc_soft_reset(fdc); - } - fdc->dsr = val; - return; - case 5: /*Command register*/ - if (fdc->fifointest) { - /* Write FIFO buffer in the test mode (PS/55) */ - fdc_log("FIFO buffer position = %X\n", ((fifo_t *) fdc->fifo_p)->end); - fifo_write(val, fdc->fifo_p); - if (fifo_get_full(fdc->fifo_p)) - fdc->stat &= ~0x80; - break; - } - if ((fdc->stat & 0xf0) == 0xb0) { - if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { - fdc->dat = val; - fdc->stat &= ~0x80; - } else { + return; + case 4: /* DSR */ + if (!(fdc->flags & FDC_FLAG_NO_DSR_RESET)) { + if (!(val & 0x80)) { + timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); + fdc->interrupt = -6; + } + if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) + fdc_soft_reset(fdc); + } + fdc->dsr = val; + return; + case 5: /*Command register*/ + if (fdc->fifointest) { + /* Write FIFO buffer in the test mode (PS/55) */ + fdc_log("FIFO buffer position = %X\n", ((fifo_t *) fdc->fifo_p)->end); fifo_write(val, fdc->fifo_p); if (fifo_get_full(fdc->fifo_p)) fdc->stat &= ~0x80; + break; } - break; - } - if (fdc->pnum == fdc->ptot) { - if ((fdc->stat & 0xf0) != 0x80) { - /* If bit 4 of the MSR is set, or the MSR is 0x00, - the fdc_t is NOT in the command phase, therefore - do NOT accept commands. */ - return; + if ((fdc->stat & 0xf0) == 0xb0) { + if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { + fdc->dat = val; + fdc->stat &= ~0x80; + } else { + fifo_write(val, fdc->fifo_p); + if (fifo_get_full(fdc->fifo_p)) + fdc->stat &= ~0x80; + } + break; } + if (fdc->pnum == fdc->ptot) { + if ((fdc->stat & 0xf0) != 0x80) { + /* If bit 4 of the MSR is set, or the MSR is 0x00, + the fdc_t is NOT in the command phase, therefore + do NOT accept commands. */ + return; + } - fdc->stat &= 0xf; + fdc->stat &= 0xf; - fdc->tc = 0; - fdc->data_ready = 0; + fdc->tc = 0; + fdc->data_ready = 0; - fdc->command = val; - fdc->stat |= 0x10; - fdc_log("Starting FDC command %02X\n", fdc->command); - fdc->error = 0; + fdc->command = val; + fdc->stat |= 0x10; + fdc_log("Starting FDC command %02X\n", fdc->command); + fdc->error = 0; - if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) || - ((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) || - ((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) || - ((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) || - ((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d)) - fdc->processed_cmd = fdc->command & 0x1f; - else - fdc->processed_cmd = fdc->command; + if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) || + ((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) || + ((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) || + ((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) || + ((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d)) + fdc->processed_cmd = fdc->command & 0x1f; + else + fdc->processed_cmd = fdc->command; - switch (fdc->processed_cmd) { - case 0x01: /*Mode*/ - if (fdc->flags & FDC_FLAG_NSC) { - fdc->pnum = 0; - fdc->ptot = 4; + switch (fdc->processed_cmd) { + case 0x01: /*Mode*/ + if (fdc->flags & FDC_FLAG_NSC) { + fdc->pnum = 0; + fdc->ptot = 4; + fdc->stat |= 0x90; + fdc->format_state = 0; + } else + fdc_bad_command(fdc); + break; + case 0x02: /*Read track*/ + fdc->satisfying_sectors = 0; + fdc->sc = 0; + fdc->wrong_am = 0; + fdc->pnum = 0; + fdc->ptot = 8; fdc->stat |= 0x90; - fdc->format_state = 0; - } else - fdc_bad_command(fdc); - break; - case 0x02: /*Read track*/ - fdc->satisfying_sectors = 0; - fdc->sc = 0; - fdc->wrong_am = 0; - fdc->pnum = 0; - fdc->ptot = 8; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x03: /*Specify*/ - fdc->pnum = 0; - fdc->ptot = 2; - fdc->stat |= 0x90; - break; - case 0x04: /*Sense drive status*/ - fdc->pnum = 0; - fdc->ptot = 1; - fdc->stat |= 0x90; - break; - case 0x05: /*Write data*/ - case 0x09: /*Write deleted data*/ - fdc->satisfying_sectors = 0; - fdc->sc = 0; - fdc->wrong_am = 0; - fdc->deleted = ((fdc->command & 0x1F) == 9) ? 1 : 0; - fdc->pnum = 0; - fdc->ptot = 8; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x06: /*Read data*/ - case 0x0c: /*Read deleted data*/ - case 0x11: /*Scan equal*/ - case 0x19: /*Scan low or equal*/ - case 0x16: /*Verify*/ - case 0x1d: /*Scan high or equal*/ - fdc->satisfying_sectors = 0; - fdc->sc = 0; - fdc->wrong_am = 0; - fdc->deleted = ((fdc->command & 0x1F) == 0xC) ? 1 : 0; - if ((fdc->command & 0x1F) == 0x16) - fdc->deleted = 2; - fdc->deleted |= (fdc->command & 0x20); - fdc->pnum = 0; - fdc->ptot = 8; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x17: /*Powerdown mode*/ - if (!(fdc->flags & FDC_FLAG_ALI)) { - fdc_bad_command(fdc); + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; break; - } - fallthrough; - case 0x07: /*Recalibrate*/ - fdc->pnum = 0; - fdc->ptot = 1; - fdc->stat |= 0x90; - break; - case 0x08: /*Sense interrupt status*/ - fdc_log("fdc->fintr = %i, fdc->reset_stat = %i\n", fdc->fintr, fdc->reset_stat); - fdc->lastdrive = fdc->drive; - fdc_sis(fdc); - break; - case 0x0a: /*Read sector ID*/ - fdc->pnum = 0; - fdc->ptot = 1; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x0d: /*Format track*/ - fdc->pnum = 0; - fdc->ptot = 5; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - fdc->format_state = 0; - break; - case 0x0e: /*Dump registers*/ - if (fdc->flags & FDC_FLAG_NEC) { - fdc_bad_command(fdc); + case 0x03: /*Specify*/ + fdc->pnum = 0; + fdc->ptot = 2; + fdc->stat |= 0x90; break; - } - fdc->lastdrive = fdc->drive; - fdc->interrupt = 0x0e; - fdc_callback(fdc); - break; - case 0x0f: /*Seek*/ - fdc->pnum = 0; - fdc->ptot = 2; - fdc->stat |= 0x90; - break; - case 0x18: /*NSC*/ - if (!(fdc->flags & FDC_FLAG_NSC)) { - fdc_bad_command(fdc); - break; - } - fallthrough; - case 0x10: /*Get version*/ - case 0x14: /*Unlock*/ - case 0x94: /*Lock*/ - if (fdc->flags & FDC_FLAG_NEC) { - fdc_bad_command(fdc); - break; - } - fdc->lastdrive = fdc->drive; - fdc->interrupt = fdc->command; - fdc_callback(fdc); - break; - case 0x12: /*Set perpendicular mode*/ - if ((fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_PCJR)) { + case 0x04: /*Sense drive status*/ fdc->pnum = 0; fdc->ptot = 1; fdc->stat |= 0x90; - } else - fdc_bad_command(fdc); - break; - case 0x13: /*Configure*/ - if (fdc->flags & FDC_FLAG_NEC) { - fdc_bad_command(fdc); break; - } - fdc->pnum = 0; - fdc->ptot = 3; - fdc->stat |= 0x90; - break; - default: - fdc_bad_command(fdc); - break; - } - } else { - fdc->stat = 0x10 | (fdc->stat & 0xf); - fdc->params[fdc->pnum++] = val; - if (fdc->pnum == 1) { - if (command_has_drivesel[fdc->command & 0x1F]) { - if (fdc->flags & FDC_FLAG_PCJR) - fdc->drive = 0; - else - fdc->drive = fdc->dor & 3; - fdc->rw_drive = fdc->params[0] & 3; - if (((fdc->command & 0x1F) == 7) || ((fdc->command & 0x1F) == 15)) - fdc->stat |= (1 << real_drive(fdc, fdc->drive)); - } - } - if (fdc->pnum == fdc->ptot) { - fdc_log("Got all params %02X\n", fdc->command); - fifo_reset(fdc->fifo_p); - fdc->interrupt = fdc->processed_cmd; - fdc->reset_stat = 0; - /* Disable timer if enabled. */ - timer_disable(&fdc->timer); - /* Start timer if needed at this point. */ - switch (fdc->interrupt & 0x1f) { - case 0x02: /* Read a track */ - case 0x03: /* Specify */ - case 0x0a: /* Read sector ID */ - case 0x05: /* Write data */ - case 0x06: /* Read data */ - case 0x09: /* Write deleted data */ - case 0x0c: /* Read deleted data */ - case 0x11: /* Scan equal */ - case 0x12: /* Perpendicular mode */ - case 0x16: /* Verify */ - case 0x19: /* Scan low or equal */ - case 0x1d: /* Scan high or equal */ - /* Do nothing. */ + case 0x05: /*Write data*/ + case 0x09: /*Write deleted data*/ + fdc->satisfying_sectors = 0; + fdc->sc = 0; + fdc->wrong_am = 0; + fdc->deleted = ((fdc->command & 0x1F) == 9) ? 1 : 0; + fdc->pnum = 0; + fdc->ptot = 8; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; break; - case 0x07: /* Recalibrate */ - case 0x0f: /* Seek */ - if (fdc->flags & FDC_FLAG_PCJR) - timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC); - else - timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); + case 0x06: /*Read data*/ + case 0x0c: /*Read deleted data*/ + case 0x11: /*Scan equal*/ + case 0x19: /*Scan low or equal*/ + case 0x16: /*Verify*/ + case 0x1d: /*Scan high or equal*/ + fdc->satisfying_sectors = 0; + fdc->sc = 0; + fdc->wrong_am = 0; + fdc->deleted = ((fdc->command & 0x1F) == 0xC) ? 1 : 0; + if ((fdc->command & 0x1F) == 0x16) + fdc->deleted = 2; + fdc->deleted |= (fdc->command & 0x20); + fdc->pnum = 0; + fdc->ptot = 8; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; break; - default: - timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); - break; - } - /* Process the firt phase of the command. */ - switch (fdc->processed_cmd) { - case 0x02: /* Read a track */ - fdc_io_command_phase1(fdc, 0); - fdc->read_track_sector.id.c = fdc->params[1]; - fdc->read_track_sector.id.h = fdc->params[2]; - fdc->read_track_sector.id.r = 1; - fdc->read_track_sector.id.n = fdc->params[4]; - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; + case 0x17: /*Powerdown mode*/ + if (!(fdc->flags & FDC_FLAG_ALI)) { + fdc_bad_command(fdc); + break; } - fdd_readsector(real_drive(fdc, fdc->drive), SECTOR_FIRST, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); - break; - case 0x03: /* Specify */ - fdc->stat = 0x80; - fdc->specify[0] = fdc->params[0]; - fdc->specify[1] = fdc->params[1]; - fdc->dma = (fdc->specify[1] & 1) ^ 1; - if (!fdc->dma) - dma_set_drq(fdc->dma_ch, 0); - break; - case 0x04: /*Sense drive status*/ - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - break; - case 0x05: /* Write data */ - case 0x09: /* Write deleted data */ - fdc_io_command_phase1(fdc, 1); - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; - } - fdd_writesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); - break; - case 0x11: /* Scan equal */ - case 0x19: /* Scan low or equal */ - case 0x1d: /* Scan high or equal */ - fdc_io_command_phase1(fdc, 1); - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; - } - fdd_comparesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); - break; - case 0x16: /* Verify */ - if (fdc->params[0] & 0x80) - fdc->sc = fdc->params[7]; fallthrough; - case 0x06: /* Read data */ - case 0x0c: /* Read deleted data */ - fdc_io_command_phase1(fdc, 0); - fdc_log("Reading sector (drive %i) (%i) (%i %i %i %i) (%i %i %i)\n", fdc->drive, fdc->params[0], fdc->params[1], fdc->params[2], fdc->params[3], fdc->params[4], fdc->params[5], fdc->params[6], fdc->params[7]); - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; - } - if (((dma_mode(2) & 0x0C) == 0x00) && !(fdc->flags & FDC_FLAG_PCJR) && fdc->dma) { - /* DMA is in verify mode, treat this like a VERIFY command. */ - fdc_log("Verify-mode read!\n"); - fdc->tc = 1; - fdc->deleted |= 2; - } - fdd_readsector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + case 0x07: /*Recalibrate*/ + fdc->pnum = 0; + fdc->ptot = 1; + fdc->stat |= 0x90; break; - - case 0x07: /* Recalibrate */ - fdc->rw_drive = fdc->params[0] & 3; - fdc->stat = (1 << real_drive(fdc, fdc->drive)); - if (!(fdc->flags & FDC_FLAG_PCJR)) - fdc->stat |= 0x80; - fdc->st0 = fdc->params[0] & 3; - fdc->st0 |= fdd_get_head(real_drive(fdc, fdc->drive)) ? 0x04 : 0x00; - fdc->st0 |= 0x80; - drive_num = real_drive(fdc, fdc->drive); - /* Three conditions under which the command should fail. */ - if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num] || fdd_track0(drive_num)) { - fdc_log("Failed recalibrate\n"); - if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num]) - fdc->st0 = 0x70 | (fdc->params[0] & 3); - else - fdc->st0 = 0x20 | (fdc->params[0] & 3); - fdc->pcn[fdc->params[0] & 3] = 0; - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } + case 0x08: /*Sense interrupt status*/ + fdc_log("fdc->fintr = %i, fdc->reset_stat = %i\n", fdc->fintr, fdc->reset_stat); + fdc->lastdrive = fdc->drive; + fdc_sis(fdc); + break; + case 0x0a: /*Read sector ID*/ + fdc->pnum = 0; + fdc->ptot = 1; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; + break; + case 0x0d: /*Format track*/ + fdc->pnum = 0; + fdc->ptot = 5; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; + fdc->format_state = 0; + break; + case 0x0e: /*Dump registers*/ + if (fdc->flags & FDC_FLAG_NEC) { + fdc_bad_command(fdc); break; } - if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) - fdc_seek(fdc, fdc->drive, -fdc->max_track); - fdc_log("Recalibrating...\n"); - fdc->seek_dir = fdc->step = 1; + fdc->lastdrive = fdc->drive; + fdc->interrupt = 0x0e; + fdc_callback(fdc); break; - case 0x0a: /* Read sector ID */ - fdc_rate(fdc, fdc->drive); - fdc->head = (fdc->params[0] & 4) ? 1 : 0; - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) { - fdd_readaddress(real_drive(fdc, fdc->drive), fdc->head, fdc->rate); - if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) - fdc->stat = 0x70; - else - fdc->stat = 0x50; + case 0x0f: /*Seek*/ + fdc->pnum = 0; + fdc->ptot = 2; + fdc->stat |= 0x90; + break; + case 0x18: /*NSC*/ + if (!(fdc->flags & FDC_FLAG_NSC)) { + fdc_bad_command(fdc); + break; + } + fallthrough; + case 0x10: /*Get version*/ + case 0x14: /*Unlock*/ + case 0x94: /*Lock*/ + if (fdc->flags & FDC_FLAG_NEC) { + fdc_bad_command(fdc); + break; + } + fdc->lastdrive = fdc->drive; + fdc->interrupt = fdc->command; + fdc_callback(fdc); + break; + case 0x12: /*Set perpendicular mode*/ + if ((fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_PCJR)) { + fdc->pnum = 0; + fdc->ptot = 1; + fdc->stat |= 0x90; } else - fdc_noidam(fdc); + fdc_bad_command(fdc); break; - case 0x0d: /* Format */ - fdc_rate(fdc, fdc->drive); - fdc->head = (fdc->params[0] & 4) ? 1 : 0; - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - fdc->gap = fdc->params[3]; - fdc->format_sectors = fdc->params[2]; - fdc->format_n = fdc->params[1]; - fdc->format_state = 1; - fdc->stat = 0x10; - break; - case 0x0f: /* Seek */ - fdc->rw_drive = fdc->params[0] & 3; - fdc->stat = (1 << fdc->drive); - if (!(fdc->flags & FDC_FLAG_PCJR)) - fdc->stat |= 0x80; - fdc->head = 0; /* TODO: See if this is correct. */ - fdc->st0 = fdc->params[0] & 0x03; - fdc->st0 |= (fdc->params[0] & 4); - fdc->st0 |= 0x80; - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - drive_num = real_drive(fdc, fdc->drive); - /* Three conditions under which the command should fail. */ - if (!fdd_get_flags(drive_num) || (drive_num >= FDD_NUM) || !motoron[drive_num]) { - /* Yes, failed SEEK's still report success, unlike failed RECALIBRATE's. */ - fdc->st0 = 0x20 | (fdc->params[0] & 3); - if (fdc->command & 0x80) { - if (fdc->command & 0x40) - fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; - else - fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; - } else - fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } + case 0x13: /*Configure*/ + if (fdc->flags & FDC_FLAG_NEC) { + fdc_bad_command(fdc); break; } - if (fdc->command & 0x80) { - if (fdc->params[1]) { - if (fdc->command & 0x40) { - /* Relative seek inwards. */ - fdc->seek_dir = 0; - fdc_seek(fdc, fdc->drive, fdc->params[1]); - fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; - } else { - /* Relative seek outwards. */ - fdc->seek_dir = 1; - fdc_seek(fdc, fdc->drive, -fdc->params[1]); - fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; - } - fdc->step = 1; - } else { - fdc->st0 = 0x20 | (fdc->params[0] & 3); - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } - break; - } - } else { - fdc_log("Seeking to track %i (PCN = %i)...\n", fdc->params[1], fdc->pcn[fdc->params[0] & 3]); - if ((fdc->params[1] - fdc->pcn[fdc->params[0] & 3]) == 0) { - fdc_log("Failed seek\n"); - fdc->st0 = 0x20 | (fdc->params[0] & 3); - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } - break; - } - if (fdc->params[1] > fdc->pcn[fdc->params[0] & 3]) - fdc->seek_dir = 0; - else - fdc->seek_dir = 1; - fdc_seek(fdc, fdc->drive, fdc->params[1] - fdc->pcn[fdc->params[0] & 3]); - fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; - fdc->step = 1; - } + fdc->pnum = 0; + fdc->ptot = 3; + fdc->stat |= 0x90; break; - case 0x12: /* Perpendicular mode */ - fdc->stat = 0x80; - if (fdc->params[0] & 0x80) - fdc->perp = fdc->params[0] & 0x3f; - else { - fdc->perp &= 0xfc; - fdc->perp |= (fdc->params[0] & 0x03); - } - return; - default: + fdc_bad_command(fdc); break; } - } else - fdc->stat = 0x90 | (fdc->stat & 0xf); - } - return; - case 7: - if (!(fdc->flags & FDC_FLAG_TOSHIBA) && !(fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_UMC)) - return; - fdc->rate = val & 0x03; - if (fdc->flags & FDC_FLAG_PS2) - fdc->noprec = !!(val & 0x04); - return; + } else { + fdc->stat = 0x10 | (fdc->stat & 0xf); + fdc->params[fdc->pnum++] = val; + if (fdc->pnum == 1) { + if (command_has_drivesel[fdc->command & 0x1F]) { + if (fdc->flags & FDC_FLAG_PCJR) + fdc->drive = 0; + else + fdc->drive = fdc->dor & 3; + fdc->rw_drive = fdc->params[0] & 3; + if (((fdc->command & 0x1F) == 7) || ((fdc->command & 0x1F) == 15)) + fdc->stat |= (1 << real_drive(fdc, fdc->drive)); + } + } + if (fdc->pnum == fdc->ptot) { + fdc_log("Got all params %02X\n", fdc->command); + fifo_reset(fdc->fifo_p); + fdc->interrupt = fdc->processed_cmd; + fdc->reset_stat = 0; + /* Disable timer if enabled. */ + timer_disable(&fdc->timer); + /* Start timer if needed at this point. */ + switch (fdc->interrupt & 0x1f) { + case 0x02: /* Read a track */ + case 0x03: /* Specify */ + case 0x0a: /* Read sector ID */ + case 0x05: /* Write data */ + case 0x06: /* Read data */ + case 0x09: /* Write deleted data */ + case 0x0c: /* Read deleted data */ + case 0x11: /* Scan equal */ + case 0x12: /* Perpendicular mode */ + case 0x16: /* Verify */ + case 0x19: /* Scan low or equal */ + case 0x1d: /* Scan high or equal */ + /* Do nothing. */ + break; + case 0x07: /* Recalibrate */ + case 0x0f: /* Seek */ + if (fdc->flags & FDC_FLAG_PCJR) + timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC); + else + timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); + break; + default: + timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); + break; + } + /* Process the firt phase of the command. */ + switch (fdc->processed_cmd) { + case 0x02: /* Read a track */ + fdc_io_command_phase1(fdc, 0); + fdc->read_track_sector.id.c = fdc->params[1]; + fdc->read_track_sector.id.h = fdc->params[2]; + fdc->read_track_sector.id.r = 1; + fdc->read_track_sector.id.n = fdc->params[4]; + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + fdd_readsector(real_drive(fdc, fdc->drive), SECTOR_FIRST, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; + case 0x03: /* Specify */ + fdc->stat = 0x80; + fdc->specify[0] = fdc->params[0]; + fdc->specify[1] = fdc->params[1]; + fdc->dma = (fdc->specify[1] & 1) ^ 1; + if (!fdc->dma) + dma_set_drq(fdc->dma_ch, 0); + break; + case 0x04: /*Sense drive status*/ + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + break; + case 0x05: /* Write data */ + case 0x09: /* Write deleted data */ + fdc_io_command_phase1(fdc, 1); + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + fdd_writesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; + case 0x11: /* Scan equal */ + case 0x19: /* Scan low or equal */ + case 0x1d: /* Scan high or equal */ + fdc_io_command_phase1(fdc, 1); + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + fdd_comparesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; + case 0x16: /* Verify */ + if (fdc->params[0] & 0x80) + fdc->sc = fdc->params[7]; + fallthrough; + case 0x06: /* Read data */ + case 0x0c: /* Read deleted data */ + fdc_io_command_phase1(fdc, 0); + fdc_log("Reading sector (drive %i) (%i) (%i %i %i %i) (%i %i %i)\n", fdc->drive, fdc->params[0], fdc->params[1], fdc->params[2], fdc->params[3], fdc->params[4], fdc->params[5], fdc->params[6], fdc->params[7]); + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + if (((dma_mode(2) & 0x0C) == 0x00) && !(fdc->flags & FDC_FLAG_PCJR) && fdc->dma) { + /* DMA is in verify mode, treat this like a VERIFY command. */ + fdc_log("Verify-mode read!\n"); + fdc->tc = 1; + fdc->deleted |= 2; + } + fdd_readsector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; - default: - break; - } + case 0x07: /* Recalibrate */ + fdc->rw_drive = fdc->params[0] & 3; + fdc->stat = 0x10 | (1 << real_drive(fdc, fdc->drive)); + if (!(fdc->flags & FDC_FLAG_PCJR)) + fdc->stat |= 0x80; + fdc->st0 = fdc->params[0] & 3; + fdc->st0 |= fdd_get_head(real_drive(fdc, fdc->drive)) ? 0x04 : 0x00; + fdc->st0 |= 0x80; + drive_num = real_drive(fdc, fdc->drive); + /* Three conditions under which the command should fail. */ + if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num] || fdd_track0(drive_num)) { + fdc_log("Failed recalibrate\n"); + if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num]) + fdc->st0 = 0x70 | (fdc->params[0] & 3); + else + fdc->st0 = 0x20 | (fdc->params[0] & 3); + fdc->pcn[fdc->params[0] & 3] = 0; + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) + fdc_seek(fdc, fdc->drive, -fdc->max_track); + fdc_log("Recalibrating...\n"); + fdc->seek_dir = fdc->step = 1; + break; + case 0x0a: /* Read sector ID */ + fdc_rate(fdc, fdc->drive); + fdc->head = (fdc->params[0] & 4) ? 1 : 0; + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) { + fdd_readaddress(real_drive(fdc, fdc->drive), fdc->head, fdc->rate); + if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) + fdc->stat = 0x70; + else + fdc->stat = 0x50; + } else + fdc_noidam(fdc); + break; + case 0x0d: /* Format */ + fdc_rate(fdc, fdc->drive); + fdc->head = (fdc->params[0] & 4) ? 1 : 0; + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + fdc->gap = fdc->params[3]; + fdc->format_sectors = fdc->params[2]; + fdc->format_n = fdc->params[1]; + fdc->format_state = 1; + fdc->stat = 0x10; + break; + case 0x0f: /* Seek */ + fdc->rw_drive = fdc->params[0] & 3; + fdc->stat = 0x10 | (1 << fdc->drive); + if (!(fdc->flags & FDC_FLAG_PCJR)) + fdc->stat |= 0x80; + fdc->head = 0; /* TODO: See if this is correct. */ + fdc->st0 = fdc->params[0] & 0x03; + fdc->st0 |= (fdc->params[0] & 4); + fdc->st0 |= 0x80; + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + drive_num = real_drive(fdc, fdc->drive); + /* Three conditions under which the command should fail. */ + if (!fdd_get_flags(drive_num) || (drive_num >= FDD_NUM) || !motoron[drive_num]) { + /* Yes, failed SEEK's still report success, unlike failed RECALIBRATE's. */ + fdc->st0 = 0x20 | (fdc->params[0] & 3); + if (fdc->command & 0x80) { + if (fdc->command & 0x40) + fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; + else + fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; + } else + fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + if (fdc->command & 0x80) { + if (fdc->params[1]) { + if (fdc->command & 0x40) { + /* Relative seek inwards. */ + fdc->seek_dir = 0; + fdc_seek(fdc, fdc->drive, fdc->params[1]); + fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; + } else { + /* Relative seek outwards. */ + fdc->seek_dir = 1; + fdc_seek(fdc, fdc->drive, -fdc->params[1]); + fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; + } + fdc->step = 1; + } else { + fdc->st0 = 0x20 | (fdc->params[0] & 3); + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + } else { + fdc_log("Seeking to track %i (PCN = %i)...\n", fdc->params[1], fdc->pcn[fdc->params[0] & 3]); + if ((fdc->params[1] - fdc->pcn[fdc->params[0] & 3]) == 0) { + fdc_log("Failed seek\n"); + fdc->st0 = 0x20 | (fdc->params[0] & 3); + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + if (fdc->params[1] > fdc->pcn[fdc->params[0] & 3]) + fdc->seek_dir = 0; + else + fdc->seek_dir = 1; + fdc_seek(fdc, fdc->drive, fdc->params[1] - fdc->pcn[fdc->params[0] & 3]); + fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; + fdc->step = 1; + } + break; + case 0x12: /* Perpendicular mode */ + fdc->stat = 0x80; + if (fdc->params[0] & 0x80) + fdc->perp = fdc->params[0] & 0x3f; + else { + fdc->perp &= 0xfc; + fdc->perp |= (fdc->params[0] & 0x03); + } + return; + + default: + break; + } + } else + fdc->stat = 0x90 | (fdc->stat & 0xf); + } + return; + case 7: + if (!(fdc->flags & FDC_FLAG_TOSHIBA) && !(fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_UMC)) + return; + fdc->rate = val & 0x03; + if (fdc->flags & FDC_FLAG_PS2) + fdc->noprec = !!(val & 0x04); + return; + + default: + break; + } } uint8_t @@ -1376,213 +1385,214 @@ fdc_read(uint16_t addr, void *priv) cycles -= ISA_CYCLES(8); - if (!fdc->power_down || ((addr & 7) == 2)) switch (addr & 7) { - case 0: /* STA */ - if (fdc->flags & FDC_FLAG_PS2) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x00; - /* TODO: - Bit 2: INDEX (best return always 0 as it goes by very fast) - */ - if (fdc->seek_dir) /* nDIRECTION */ - ret |= 0x01; - if (writeprot[drive]) /* WRITEPROT */ - ret |= 0x02; - if (!fdd_get_head(drive)) /* nHDSEL */ - ret |= 0x08; - if (fdd_track0(drive)) /* TRK0 */ - ret |= 0x10; - if (fdc->step) /* STEP */ - ret |= 0x20; - if (dma_get_drq(fdc->dma_ch)) /* DRQ */ - ret |= 0x40; - if (fdc->fintr || fdc->reset_stat) /* INTR */ - ret |= 0x80; - } else if (fdc->flags & FDC_FLAG_PS2_MCA) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x04; - /* TODO: - Bit 2: nINDEX (best return always 1 as it goes by very fast) - */ - if (!fdc->seek_dir) /* DIRECTION */ - ret |= 0x01; - if (!writeprot[drive]) /* nWRITEPROT */ - ret |= 0x02; - if (fdd_get_head(drive)) /* HDSEL */ - ret |= 0x08; - if (!fdd_track0(drive)) /* nTRK0 */ - ret |= 0x10; - if (fdc->step) /* STEP */ - ret |= 0x20; - if (!fdd_get_type(1)) /* -Drive 2 Installed */ - ret |= 0x40; - if (fdc->fintr || fdc->reset_stat) /* INTR */ - ret |= 0x80; - } else - ret = 0xff; - break; - case 1: /* STB */ - if (fdc->flags & FDC_FLAG_PS2) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x00; - if (!fdd_get_type(1)) /* -Drive 2 Installed */ - ret |= 0x80; - switch (drive) { /* -Drive Select 1,0 */ - case 0: - ret |= 0x43; - break; - case 1: - ret |= 0x23; - break; - case 2: - ret |= 0x62; - break; - case 3: - ret |= 0x61; - break; - - default: - break; - } - } else if (fdc->flags & FDC_FLAG_PS2_MCA) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0xc0; - ret |= (fdc->dor & 0x01) << 5; /* Drive Select 0 */ - ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ - } else { - if (is486 || !fdc->enable_3f1) + if (!fdc->power_down || ((addr & 7) == 2)) + switch (addr & 7) { + case 0: /* STA */ + if (fdc->flags & FDC_FLAG_PS2) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x00; + /* TODO: + Bit 2: INDEX (best return always 0 as it goes by very fast) + */ + if (fdc->seek_dir) /* nDIRECTION */ + ret |= 0x01; + if (writeprot[drive]) /* WRITEPROT */ + ret |= 0x02; + if (!fdd_get_head(drive)) /* nHDSEL */ + ret |= 0x08; + if (fdd_track0(drive)) /* TRK0 */ + ret |= 0x10; + if (fdc->step) /* STEP */ + ret |= 0x20; + if (dma_get_drq(fdc->dma_ch)) /* DRQ */ + ret |= 0x40; + if (fdc->fintr || fdc->reset_stat) /* INTR */ + ret |= 0x80; + } else if (fdc->flags & FDC_FLAG_PS2_MCA) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x04; + /* TODO: + Bit 2: nINDEX (best return always 1 as it goes by very fast) + */ + if (!fdc->seek_dir) /* DIRECTION */ + ret |= 0x01; + if (!writeprot[drive]) /* nWRITEPROT */ + ret |= 0x02; + if (fdd_get_head(drive)) /* HDSEL */ + ret |= 0x08; + if (!fdd_track0(drive)) /* nTRK0 */ + ret |= 0x10; + if (fdc->step) /* STEP */ + ret |= 0x20; + if (!fdd_get_type(1)) /* -Drive 2 Installed */ + ret |= 0x40; + if (fdc->fintr || fdc->reset_stat) /* INTR */ + ret |= 0x80; + } else ret = 0xff; - else { - if (fdc->flags & FDC_FLAG_UMC) { - drive = real_drive(fdc, fdc->dor & 1); - ret = !fdd_is_dd(drive) ? ((fdc->dor & 1) ? 2 : 1) : 0; - } else { - /* TODO: What is this and what is it used for? - It's almost identical to the PS/2 MCA mode. */ - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x70; - ret &= ~(drive ? 0x40 : 0x20); - ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ + break; + case 1: /* STB */ + if (fdc->flags & FDC_FLAG_PS2) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x00; + if (!fdd_get_type(1)) /* -Drive 2 Installed */ + ret |= 0x80; + switch (drive) { /* -Drive Select 1,0 */ + case 0: + ret |= 0x43; + break; + case 1: + ret |= 0x23; + break; + case 2: + ret |= 0x62; + break; + case 3: + ret |= 0x61; + break; + + default: + break; + } + } else if (fdc->flags & FDC_FLAG_PS2_MCA) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0xc0; + ret |= (fdc->dor & 0x01) << 5; /* Drive Select 0 */ + ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ + } else { + if (is486 || !fdc->enable_3f1) + ret = 0xff; + else { + if (fdc->flags & FDC_FLAG_UMC) { + drive = real_drive(fdc, fdc->dor & 1); + ret = !fdd_is_dd(drive) ? ((fdc->dor & 1) ? 2 : 1) : 0; + } else { + /* TODO: What is this and what is it used for? + It's almost identical to the PS/2 MCA mode. */ + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x70; + ret &= ~(drive ? 0x40 : 0x20); + ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ + } } } - } - break; - case 2: - ret = fdc->dor; - break; - case 3: - drive = real_drive(fdc, fdc->dor & 3); - /* TODO: FDC_FLAG_PS2_TDR? */ - if ((fdc->flags & FDC_FLAG_PS2) || (fdc->flags & FDC_FLAG_PS2_MCA)) { - /* PS/1 Model 2121 seems return drive type in port - * 0x3f3, despite the 82077AA fdc_t not implementing - * this. This is presumably implemented outside the - * fdc_t on one of the motherboard's support chips. - * - * Confirmed: 00=1.44M 3.5 - * 10=2.88M 3.5 - * 20=1.2M 5.25 - * 30=1.2M 5.25 - * - * as reported by Configur.exe. - */ - if (fdd_is_525(drive)) - ret = 0x20; - else if (fdd_is_ed(drive)) - ret = 0x10; - else - ret = 0x00; - /* PS/55 POST throws an error and halt if ret = 1 or 2, somehow. */ - } else if (!fdc->enh_mode) - ret = 0x20; - else if (fdc->flags & FDC_FLAG_SMC661) - ret = (fdc->densel_force << 3) | ((!!fdc->swap) << 5) | (fdc->media_id << 6); - else - ret = (fdc->rwc[drive] << 4) | (fdc->media_id << 6); - break; - case 4: /*Status*/ - ret = fdc->stat; - break; - case 5: /*Data*/ - if (fdc->fifointest) { - /* Read FIFO buffer in the test mode (PS/55) */ - ret = fifo_read(fdc->fifo_p); break; - } - if ((fdc->stat & 0xf0) == 0xf0) { - fdc->stat &= ~0x80; - if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { - fdc->data_ready = 0; - ret = fdc->dat; - } else - ret = fifo_read(fdc->fifo_p); + case 2: + ret = fdc->dor; break; - } - if (fdc->paramstogo) { - fdc->stat &= ~0x80; - fdc_log("%i parameters to go\n", fdc->paramstogo); - fdc->paramstogo--; - ret = fdc->res[10 - fdc->paramstogo]; - if (!fdc->paramstogo) - fdc->stat = 0x80; - else - fdc->stat |= 0xC0; - } else if (fdc->dma) { - ret = fdc->dat; - break; - } else { - fdc->stat &= ~0x80; - if (lastbyte) - fdc->stat = 0x80; - lastbyte = 0; - ret = fdc->dat; - fdc->data_ready = 0; - } - fdc->stat &= 0xf0; - break; - case 7: /*Disk change*/ - drive = real_drive(fdc, fdc->dor & 3); - - if (fdc->flags & FDC_FLAG_PS2) { - if (fdc->dor & (0x10 << drive)) { - ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x00 : 0x80; - ret |= (fdc->dor & 0x08); - ret |= (fdc->noprec << 2); - ret |= (fdc->rate & 0x03); - } else - ret = 0x00; - } else if (fdc->flags & FDC_FLAG_PS2_MCA) { - if (fdc->dor & (0x10 << drive)) { - ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00; - ret |= ((fdc->rate & 0x03) << 1); - ret |= fdc_get_densel(fdc, drive); - ret |= 0x78; - } else - ret = 0xf9; - } else { - if (fdc->dor & (0x10 << drive)) { - if ((drive == 1) && (fdc->flags & FDC_FLAG_TOSHIBA)) - ret = 0x00; + case 3: + drive = real_drive(fdc, fdc->dor & 3); + /* TODO: FDC_FLAG_PS2_TDR? */ + if ((fdc->flags & FDC_FLAG_PS2) || (fdc->flags & FDC_FLAG_PS2_MCA)) { + /* PS/1 Model 2121 seems return drive type in port + * 0x3f3, despite the 82077AA fdc_t not implementing + * this. This is presumably implemented outside the + * fdc_t on one of the motherboard's support chips. + * + * Confirmed: 00=1.44M 3.5 + * 10=2.88M 3.5 + * 20=1.2M 5.25 + * 30=1.2M 5.25 + * + * as reported by Configur.exe. + */ + if (fdd_is_525(drive)) + ret = 0x20; + else if (fdd_is_ed(drive)) + ret = 0x10; else + ret = 0x00; + /* PS/55 POST throws an error and halt if ret = 1 or 2, somehow. */ + } else if (!fdc->enh_mode) + ret = 0x20; + else if (fdc->flags & FDC_FLAG_SMC661) + ret = (fdc->densel_force << 3) | ((!!fdc->swap) << 5) | (fdc->media_id << 6); + else + ret = (fdc->rwc[drive] << 4) | (fdc->media_id << 6); + break; + case 4: /*Status*/ + ret = fdc->stat; + break; + case 5: /*Data*/ + if (fdc->fifointest) { + /* Read FIFO buffer in the test mode (PS/55) */ + ret = fifo_read(fdc->fifo_p); + break; + } + if ((fdc->stat & 0xf0) == 0xf0) { + fdc->stat &= ~0x80; + if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { + fdc->data_ready = 0; + ret = fdc->dat; + } else + ret = fifo_read(fdc->fifo_p); + break; + } + if (fdc->paramstogo) { + fdc->stat &= ~0x80; + fdc_log("%i parameters to go\n", fdc->paramstogo); + fdc->paramstogo--; + ret = fdc->res[10 - fdc->paramstogo]; + if (!fdc->paramstogo) + fdc->stat = 0x80; + else + fdc->stat |= 0xC0; + } else if (fdc->dma) { + ret = fdc->dat; + break; + } else { + fdc->stat &= ~0x80; + if (lastbyte) + fdc->stat = 0x80; + lastbyte = 0; + ret = fdc->dat; + fdc->data_ready = 0; + } + fdc->stat &= 0xf0; + break; + case 7: /*Disk change*/ + drive = real_drive(fdc, fdc->dor & 3); + + if (fdc->flags & FDC_FLAG_PS2) { + if (fdc->dor & (0x10 << drive)) { + ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x00 : 0x80; + ret |= (fdc->dor & 0x08); + ret |= (fdc->noprec << 2); + ret |= (fdc->rate & 0x03); + } else + ret = 0x00; + } else if (fdc->flags & FDC_FLAG_PS2_MCA) { + if (fdc->dor & (0x10 << drive)) { ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00; - } else - ret = 0x00; - if (fdc->flags & FDC_FLAG_DISKCHG_ACTLOW) /*PC2086/3086 seem to reverse this bit*/ - ret ^= 0x80; + ret |= ((fdc->rate & 0x03) << 1); + ret |= fdc_get_densel(fdc, drive); + ret |= 0x78; + } else + ret = 0xf9; + } else { + if (fdc->dor & (0x10 << drive)) { + if ((drive == 1) && (fdc->flags & FDC_FLAG_TOSHIBA)) + ret = 0x00; + else + ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00; + } else + ret = 0x00; + if (fdc->flags & FDC_FLAG_DISKCHG_ACTLOW) /*PC2086/3086 seem to reverse this bit*/ + ret ^= 0x80; - /* 0 = ????, 1 = Ext. FDD off, 2 = Ext. FDD = FDD A, 3 = Ext. FDD = FDD B */ - if (fdc->flags & FDC_FLAG_TOSHIBA) { - ret |= (3 << 5); - ret |= 0x01; - } else - ret |= 0x7F; - } + /* 0 = ????, 1 = Ext. FDD off, 2 = Ext. FDD = FDD A, 3 = Ext. FDD = FDD B */ + if (fdc->flags & FDC_FLAG_TOSHIBA) { + ret |= (3 << 5); + ret |= 0x01; + } else + ret |= 0x7F; + } - fdc->step = 0; - break; - default: - ret = 0xff; - } + fdc->step = 0; + break; + default: + ret = 0xff; + } fdc_log("[%04X:%08X] Read FDC %04X %02X [%i:%02X]\n", CS, cpu_state.pc, addr, ret, drive, fdc->dor & (0x10 << drive)); return ret; } @@ -1886,7 +1896,7 @@ fdc_callback(void *priv) } else fdc->interrupt = -3; timer_set_delay_u64(&fdc->timer, 2048 * TIMER_USEC); - fdc->stat = 0x80 | (1 << fdc->rw_drive); + fdc->stat = 0x10 | (1 << fdc->rw_drive); return; case 0x0d: /*Format track*/ if (fdc->format_state == 1) { @@ -1929,7 +1939,7 @@ fdc_callback(void *priv) return; case 0x0f: /*Seek*/ fdc->st0 = 0x20 | (fdc->params[0] & 3); - fdc->stat = 0x80 | (1 << fdc->rw_drive); + fdc->stat = 0x10 | (1 << fdc->rw_drive); // Interrupts and callbacks in the fdd callback function return; case 0x10: /*Version*/ @@ -2863,4 +2873,4 @@ const device_t fdc_ps2_mca_device = { .speed_changed = NULL, .force_redraw = NULL, .config = NULL -}; +}; \ No newline at end of file diff --git a/src/floppy/fdd.c b/src/floppy/fdd.c index a0bef7ac6..212317f49 100644 --- a/src/floppy/fdd.c +++ b/src/floppy/fdd.c @@ -79,11 +79,34 @@ typedef struct fdd_t { fdd_t fdd[FDD_NUM]; +enum { + FDD_OP_NONE = 0, + FDD_OP_READ, + FDD_OP_WRITE, + FDD_OP_COMPARE, + FDD_OP_READADDR, + FDD_OP_FORMAT +}; + +typedef struct fdd_pending_op_t { + int pending; + int op; + int sector; + int track; + int side; + int density; + int sector_size; + uint8_t fill; +} fdd_pending_op_t; + +static fdd_pending_op_t fdd_pending[FDD_NUM]; + char floppyfns[FDD_NUM][512]; char *fdd_image_history[FDD_NUM][FLOPPY_IMAGE_HISTORY]; pc_timer_t fdd_poll_time[FDD_NUM]; pc_timer_t fdd_seek_timer[FDD_NUM]; +int fdd_seek_in_progress[FDD_NUM] = { 0, 0, 0, 0 }; static int fdd_notfound = 0; static int driveloaders[FDD_NUM]; @@ -293,10 +316,49 @@ fdd_seek_complete_callback(void *priv) { DRIVE *drive = (DRIVE *) priv; + fdd_seek_in_progress[drive->id] = 0; + fdd_log("fdd_seek_complete_callback(drive=%d) - TIMER FIRED! seek_in_progress=1\n", drive->id); fdd_log("Notifying FDC of seek completion\n"); fdd_do_seek(drive->id, fdd[drive->id].track); - fdc_seek_complete_interrupt(fdd_fdc, drive->id); + + int had_pending = fdd_pending[drive->id].pending; + if (had_pending) { + fdd_pending_op_t *po = &fdd_pending[drive->id]; + fdd_log("Starting deferred op %d after seek on drive %d (trk=%d, side=%d, sec=%d)\n", + po->op, drive->id, po->track, po->side, po->sector); + + switch (po->op) { + case FDD_OP_READ: + if (drives[drive->id].readsector) + drives[drive->id].readsector(drive->id, po->sector, po->track, po->side, po->density, po->sector_size); + break; + case FDD_OP_WRITE: + if (drives[drive->id].writesector) + drives[drive->id].writesector(drive->id, po->sector, po->track, po->side, po->density, po->sector_size); + break; + case FDD_OP_COMPARE: + if (drives[drive->id].comparesector) + drives[drive->id].comparesector(drive->id, po->sector, po->track, po->side, po->density, po->sector_size); + break; + case FDD_OP_READADDR: + if (drives[drive->id].readaddress) + drives[drive->id].readaddress(drive->id, po->side, po->density); + break; + case FDD_OP_FORMAT: + if (drives[drive->id].format) + drives[drive->id].format(drive->id, po->side, po->density, po->fill); + break; + default: + break; + } + + po->pending = 0; + po->op = FDD_OP_NONE; + } + + if (!had_pending) + fdc_seek_complete_interrupt(fdd_fdc, drive->id); } void @@ -306,6 +368,11 @@ fdd_seek(int drive, int track_diff) if (!track_diff) return; + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek already in progress for drive %d, ignoring new seek request\n", drive); + return; + } + int old_track = fdd[drive].track; fdd[drive].track += track_diff; @@ -327,12 +394,14 @@ fdd_seek(int drive, int track_diff) /* Multi-track seek */ fdd_audio_play_multi_track_seek(drive, old_track, fdd[drive].track); } - + if (old_track + track_diff < 0) { fdd_do_seek(drive, fdd[drive].track); return; } + fdd_seek_in_progress[drive] = 1; + if (!fdd_seek_timer[drive].callback) { timer_add(&(fdd_seek_timer[drive]), fdd_seek_complete_callback, &drives[drive], 0); } @@ -629,7 +698,7 @@ fdd_set_motor_enable(int drive, int motor_enable) { fdd_log("fdd_set_motor_enable(%d, %d)\n", drive, motor_enable); fdd_audio_set_motor_enable(drive, motor_enable); - + if (motor_enable && !motoron[drive]) { timer_set_delay_u64(&fdd_poll_time[drive], fdd_byteperiod(drive)); } else if (!motor_enable && motoron[drive]) { @@ -700,6 +769,22 @@ void fdd_readsector(int drive, int sector, int track, int side, int density, int sector_size) { fdd_log("fdd_readsector(%d, %d, %d, %d, %d, %d)\n", drive, sector, track, side, density, sector_size); + + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring READ (trk=%d->%d, side=%d, sec=%d)\n", + drive, fdd[drive].track, track, side, sector); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_READ, + .sector = sector, + .track = track, + .side = side, + .density = density, + .sector_size = sector_size + }; + return; + } + if (drives[drive].readsector) drives[drive].readsector(drive, sector, track, side, density, sector_size); else @@ -710,6 +795,22 @@ void fdd_writesector(int drive, int sector, int track, int side, int density, int sector_size) { fdd_log("fdd_writesector(%d, %d, %d, %d, %d, %d)\n", drive, sector, track, side, density, sector_size); + + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring WRITE (trk=%d->%d, side=%d, sec=%d)\n", + drive, fdd[drive].track, track, side, sector); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_WRITE, + .sector = sector, + .track = track, + .side = side, + .density = density, + .sector_size = sector_size + }; + return; + } + if (drives[drive].writesector) drives[drive].writesector(drive, sector, track, side, density, sector_size); else @@ -719,6 +820,21 @@ fdd_writesector(int drive, int sector, int track, int side, int density, int sec void fdd_comparesector(int drive, int sector, int track, int side, int density, int sector_size) { + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring COMPARE (trk=%d->%d, side=%d, sec=%d)\n", + drive, fdd[drive].track, track, side, sector); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_COMPARE, + .sector = sector, + .track = track, + .side = side, + .density = density, + .sector_size = sector_size + }; + return; + } + if (drives[drive].comparesector) drives[drive].comparesector(drive, sector, track, side, density, sector_size); else @@ -728,6 +844,19 @@ fdd_comparesector(int drive, int sector, int track, int side, int density, int s void fdd_readaddress(int drive, int side, int density) { + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring READADDRESS (trk=%d, side=%d)\n", + drive, fdd[drive].track, side); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_READADDR, + .track = fdd[drive].track, + .side = side, + .density = density + }; + return; + } + if (drives[drive].readaddress) drives[drive].readaddress(drive, side, density); } @@ -735,6 +864,20 @@ fdd_readaddress(int drive, int side, int density) void fdd_format(int drive, int side, int density, uint8_t fill) { + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring FORMAT (trk=%d, side=%d)\n", + drive, fdd[drive].track, side); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_FORMAT, + .track = fdd[drive].track, + .side = side, + .density = density, + .fill = fill + }; + return; + } + if (drives[drive].format) drives[drive].format(drive, side, density, fill); else @@ -777,7 +920,7 @@ fdd_init(void) if (fdd_sounds_enabled) { fdd_audio_init(); - } + } } void From 836f855683bc822e113ab1b715d5579dc74c5a6a Mon Sep 17 00:00:00 2001 From: Toni Riikonen Date: Sat, 27 Sep 2025 11:51:38 +0300 Subject: [PATCH 264/274] Fixes #6220 floppy disk issues with OS/2 and NT 3.1 systems (#6232) * Initial spindle emulation working for windows atleast * Spingle motor spin-up, spin-down implemented with smooth transitions to motor-on loop. * Moved fdd audio emulation to a separate file * Multiple drives sound emulation * Single sector movement sound emulations implemented * Rename project to Immersive86Box and update details Updated README to reflect the new project name and added details about the Immersive86Box features and future plans. * Revise contribution guidelines in CONTRIBUTING.md * Update vulnerability reporting instructions * System fan-sound next feature after basic fdd sound emulation is ready * v0.5 multitrack audio seek sfx * Removed unnecessary stuff * no .vs folder for git * Added currently used fdd sound effects and readme.txt for source of the files and intallation instructions * Add audio emulation installation instructions Added instructions for audio emulation installation. * Code and audio samples merged * Simplify audio emulation installation instructions * FDC seeking fixed, not instant anymore drive is set to busy during the operation and when it's finished at call fdc to set the appropriate fdc flags. Also added time logic to fdd to calculate seek duration and a callback function for it. * FDD sound samples volume control * Menu options to enable / disable fdd sound for all drives. DISABLE_FDD_AUDIO definition added, to disable the feature via cmake/build. * Revert readme etc. changes * Revert "Revise contribution guidelines in CONTRIBUTING.md" This reverts commit 98a0478225bbf8bf0fb0e7edfd5c00636ecc0eed. * Revert "Update vulnerability reporting instructions" This reverts commit 7d32cb659b018b26bdaa4a1e06ee9c3d09278aac. * Fixed merge issue * Removed excess files * Fixed PCJr seeking not to break the FDC implementation. Now seeking will take the "correct" amount of time for each system and the seek time is based on the track count. E.g. 40 track FDD system causes 40 track seek time to be 80/40 * 6ms * 40 tracks + 50ms = 480ms + 50ms -> 530ms. 80 track system full seek is 80/80 * 6ms * 80 + 50ms = 530ms, 40 track seek would take 240 + 50 = 290ms. * Fixed PS/1, PS/2 and PS/55 FDD issues. * FDD_AUDIO: Updating samples looked in executablePath/samples and if now found there, looks in the executable directory * Updated installation instructions * Removed samples path strcat use * fdd_audio 5.25 samples and support added * FDD audio timing/volume tunings * Timing fixes for authentity and special longer timings for PCJr * Fixed second drive motor keeps running when first drive is only accessed. * Fixed PCJr random failure issue, timings * CodeQL fix for load_wav-function. Check the filename to be proper filename * Revert "Fixed second drive motor keeps running when first drive is only accessed." This reverts commit 307b173ae7d40c9efafed8d432e01cce9808b111. * Teac 5.25" drive samples added. Added per drive audio selection to FDD settings. * Fixes merge problem * Fixes #6220: OS/2 Warp 3.0 install disk issue and NT 3.1 floppy disk issues. Changed the fdc->stat bit to 0x10 which states fdc busy. Previous implementation with seek time 0, set the ready flag 0x80 immediadely - which was correct for that time, but now as the drive is busy during seek, the value should 0x10. Implemented a backup for fdd commands during fdd seek to be processes after the seek is completed. --------- Co-authored-by: Toni Riikonen --- src/floppy/fdc.c | 1522 ++++++++++++++++++++-------------------- src/floppy/fdd.c | 151 +++- src/floppy/fdd_audio.c | 1 + 3 files changed, 914 insertions(+), 760 deletions(-) diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index bcf4a1299..212bf9ce0 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -184,7 +184,7 @@ fdc_ctrl_reset(void *priv) { fdc_t *fdc = (fdc_t *) priv; - fdc->stat = 0x80; + fdc->stat = 0x10; fdc->pnum = fdc->ptot = 0; fdc->st0 = 0; fdc->head = 0; @@ -470,9 +470,9 @@ uint8_t fdc_get_shadow(fdc_t *fdc) { uint8_t ret = (fdc->rate & 0x03) | - ((fdc->pretrk & 0x07) << 2) | - (fdc->power_down ? 0x40 : 0x00) | - ((fdc_read(0x03f2, fdc) & 0x04) ? 0x80 : 0x00); + ((fdc->pretrk & 0x07) << 2) | + (fdc->power_down ? 0x40 : 0x00) | + ((fdc_read(0x03f2, fdc) & 0x04) ? 0x80 : 0x00); return ret; } @@ -532,36 +532,36 @@ fdc_update_rate(fdc_t *fdc, int drive) fdc->enh_mode && !(fdc->flags & FDC_FLAG_SMC661)) fdc->bit_rate = 500; else if ((fdc->rwc[drive] == 3) && fdc->enh_mode && - !(fdc->flags & FDC_FLAG_SMC661)) + !(fdc->flags & FDC_FLAG_SMC661)) fdc->bit_rate = 250; else switch (fdc->rate) { - default: - break; - case 0: /*High density*/ - fdc->bit_rate = 500; - break; - case 1: /*Double density (360 rpm)*/ - switch (fdc->drvrate[drive]) { - default: - break; - case 0: - fdc->bit_rate = 300; - break; - case 1: - fdc->bit_rate = 500; - break; - case 2: - fdc->bit_rate = 2000; - break; - } - break; - case 2: /*Double density*/ - fdc->bit_rate = 250; - break; - case 3: /*Extended density*/ - fdc->bit_rate = 1000; - break; - } + default: + break; + case 0: /*High density*/ + fdc->bit_rate = 500; + break; + case 1: /*Double density (360 rpm)*/ + switch (fdc->drvrate[drive]) { + default: + break; + case 0: + fdc->bit_rate = 300; + break; + case 1: + fdc->bit_rate = 500; + break; + case 2: + fdc->bit_rate = 2000; + break; + } + break; + case 2: /*Double density*/ + fdc->bit_rate = 250; + break; + case 3: /*Extended density*/ + fdc->bit_rate = 1000; + break; + } fdc->bitcell_period = (1000000 / fdc->bit_rate) * 2; /*Bitcell period in ns*/ } @@ -695,7 +695,7 @@ void fdc_seek(fdc_t *fdc, int drive, int params) { fdd_seek(real_drive(fdc, drive), params); - fdc->stat |= (1 << fdc->drive); + fdc->stat = (fdc->stat & 0x0F) | 0x10 | (1 << fdc->drive); } static void @@ -719,8 +719,10 @@ fdc_io_command_phase1(fdc_t *fdc, int out) fdc->dtl = fdc->params[7]; fdc->rw_track = fdc->params[1]; + int implied_seek = 0; if (fdc->config & 0x40) { if (fdc->rw_track != fdc->pcn[fdc->params[0] & 3]) { + implied_seek = 1; fdc_seek(fdc, fdc->drive, ((int) fdc->rw_track) - ((int) fdc->pcn[fdc->params[0] & 3])); fdc->pcn[fdc->params[0] & 3] = fdc->rw_track; } @@ -730,6 +732,12 @@ fdc_io_command_phase1(fdc_t *fdc, int out) ui_sb_update_icon_write(SB_FLOPPY | real_drive(fdc, fdc->drive), 1); else ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 1); + + if (implied_seek) { + fdc->stat = (fdc->stat & 0x0F) | 0x10 | (1 << real_drive(fdc, fdc->drive)); /* CB=1, per-drive busy */ + return; + } + fdc->stat = out ? 0x10 : 0x50; if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) { fdc->stat |= 0x20; @@ -791,7 +799,7 @@ fdc_soft_reset(fdc_t *fdc) } fdc_ctrl_reset(fdc); - } + } } static void @@ -806,565 +814,566 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) cycles -= ISA_CYCLES(8); - if (!fdc->power_down || ((addr & 7) == 2) || ((addr & 7) == 4)) switch (addr & 7) { - case 0: - return; - case 1: - return; - case 2: /*DOR*/ - if (fdc->flags & FDC_FLAG_PCJR) { - if ((fdc->dor & 0x40) && !(val & 0x40)) { - timer_set_delay_u64(&fdc->watchdog_timer, 1000 * TIMER_USEC); - fdc->watchdog_count = 1000; - picintc(1 << fdc->irq); - } - if ((val & 0x80) && !(fdc->dor & 0x80)) { - timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); - fdc->interrupt = -1; - ui_sb_update_icon(SB_FLOPPY | 0, 0); - ui_sb_update_icon_write(SB_FLOPPY | 0, 0); - fdc_ctrl_reset(fdc); - } - if (!fdd_get_flags(0)) - val &= 0xfe; - fdd_set_motor_enable(0, val & 0x01); - fdc->st0 &= ~0x07; - fdc->st0 |= (fdd_get_head(0) ? 4 : 0); - } else { - /* - Writing this bit to logic "1" will enable the DRQ, - nDACK, TC and FINTR outputs. This bit being a - logic "0" will disable the nDACK and TC inputs, and - hold the DRQ and FINTR outputs in a high - impedance state. - */ - if (!(val & 8) && (fdc->dor & 8) && !(fdc->flags & FDC_FLAG_PS2_MCA)) { - fdc->tc = 1; - fdc->fintr = 0; - picintc(1 << fdc->irq); - } - if (!(val & 4)) { - fdd_stop(real_drive(fdc, val & 3)); - fdc->stat = 0x00; - fdc->pnum = fdc->ptot = 0; - } - if ((val & 4) && !(fdc->dor & 4)) - fdc_soft_reset(fdc); - /* We can now simplify this since each motor now spins separately. */ - for (int i = 0; i < FDD_NUM; i++) { - drive_num = real_drive(fdc, i); - if ((!fdd_get_flags(drive_num)) || (drive_num >= FDD_NUM)) - val &= ~(0x10 << drive_num); - else - fdd_set_motor_enable(i, (val & (0x10 << drive_num))); - } - drive_num = real_drive(fdc, val & 0x03); - current_drive = drive_num; - fdc->st0 = (fdc->st0 & 0xf8) | (val & 0x03) | (fdd_get_head(drive_num) ? 4 : 0); - } - fdc->dor = val; - return; - case 3: /* TDR */ - if (fdc->enh_mode) { - if (fdc->flags & FDC_FLAG_SMC661) { - fdc_set_swap(fdc, !!(val & 0x20)); - fdc_update_densel_force(fdc, (val & 0x18) >> 3); + if (!fdc->power_down || ((addr & 7) == 2) || ((addr & 7) == 4)) + switch (addr & 7) { + case 0: + return; + case 1: + return; + case 2: /*DOR*/ + if (fdc->flags & FDC_FLAG_PCJR) { + if ((fdc->dor & 0x40) && !(val & 0x40)) { + timer_set_delay_u64(&fdc->watchdog_timer, 1000 * TIMER_USEC); + fdc->watchdog_count = 1000; + picintc(1 << fdc->irq); + } + if ((val & 0x80) && !(fdc->dor & 0x80)) { + timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); + fdc->interrupt = -1; + ui_sb_update_icon(SB_FLOPPY | 0, 0); + ui_sb_update_icon_write(SB_FLOPPY | 0, 0); + fdc_ctrl_reset(fdc); + } + if (!fdd_get_flags(0)) + val &= 0xfe; + fdd_set_motor_enable(0, val & 0x01); + fdc->st0 &= ~0x07; + fdc->st0 |= (fdd_get_head(0) ? 4 : 0); } else { - drive = real_drive(fdc, fdc->dor & 3); - fdc_update_rwc(fdc, drive, (val & 0x30) >> 4); + /* + Writing this bit to logic "1" will enable the DRQ, + nDACK, TC and FINTR outputs. This bit being a + logic "0" will disable the nDACK and TC inputs, and + hold the DRQ and FINTR outputs in a high + impedance state. + */ + if (!(val & 8) && (fdc->dor & 8) && !(fdc->flags & FDC_FLAG_PS2_MCA)) { + fdc->tc = 1; + fdc->fintr = 0; + picintc(1 << fdc->irq); + } + if (!(val & 4)) { + fdd_stop(real_drive(fdc, val & 3)); + fdc->stat = 0x00; + fdc->pnum = fdc->ptot = 0; + } + if ((val & 4) && !(fdc->dor & 4)) + fdc_soft_reset(fdc); + /* We can now simplify this since each motor now spins separately. */ + for (int i = 0; i < FDD_NUM; i++) { + drive_num = real_drive(fdc, i); + if ((!fdd_get_flags(drive_num)) || (drive_num >= FDD_NUM)) + val &= ~(0x10 << drive_num); + else + fdd_set_motor_enable(i, (val & (0x10 << drive_num))); + } + drive_num = real_drive(fdc, val & 0x03); + current_drive = drive_num; + fdc->st0 = (fdc->st0 & 0xf8) | (val & 0x03) | (fdd_get_head(drive_num) ? 4 : 0); } - } - /* Bit 2: FIFO test mode (PS/55 5550-S,T only. Undocumented) - The Power-on Self Test of PS/55 writes and verifies 8 bytes of FIFO buffer through I/O 3F5h. - If it fails, then floppy drives will be treated as DD drives. */ - if (fdc->flags & FDC_FLAG_PS2_MCA) { - if (val & 0x04) { - fdc->tfifo = 8; - fdc->fifointest = 1; - } else { - fdc->tfifo = 1; - fdc->fifointest = 0; + fdc->dor = val; + return; + case 3: /* TDR */ + if (fdc->enh_mode) { + if (fdc->flags & FDC_FLAG_SMC661) { + fdc_set_swap(fdc, !!(val & 0x20)); + fdc_update_densel_force(fdc, (val & 0x18) >> 3); + } else { + drive = real_drive(fdc, fdc->dor & 3); + fdc_update_rwc(fdc, drive, (val & 0x30) >> 4); + } } - fifo_reset(fdc->fifo_p); - fifo_set_len(fdc->fifo_p, fdc->tfifo + 1); - fifo_set_trigger_len(fdc->fifo_p, fdc->tfifo + 1); - } - return; - case 4: /* DSR */ - if (!(fdc->flags & FDC_FLAG_NO_DSR_RESET)) { - if (!(val & 0x80)) { - timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); - fdc->interrupt = -6; + /* Bit 2: FIFO test mode (PS/55 5550-S,T only. Undocumented) + The Power-on Self Test of PS/55 writes and verifies 8 bytes of FIFO buffer through I/O 3F5h. + If it fails, then floppy drives will be treated as DD drives. */ + if (fdc->flags & FDC_FLAG_PS2_MCA) { + if (val & 0x04) { + fdc->tfifo = 8; + fdc->fifointest = 1; + } else { + fdc->tfifo = 1; + fdc->fifointest = 0; + } + fifo_reset(fdc->fifo_p); + fifo_set_len(fdc->fifo_p, fdc->tfifo + 1); + fifo_set_trigger_len(fdc->fifo_p, fdc->tfifo + 1); } - if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) - fdc_soft_reset(fdc); - } - fdc->dsr = val; - return; - case 5: /*Command register*/ - if (fdc->fifointest) { - /* Write FIFO buffer in the test mode (PS/55) */ - fdc_log("FIFO buffer position = %X\n", ((fifo_t *) fdc->fifo_p)->end); - fifo_write(val, fdc->fifo_p); - if (fifo_get_full(fdc->fifo_p)) - fdc->stat &= ~0x80; - break; - } - if ((fdc->stat & 0xf0) == 0xb0) { - if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { - fdc->dat = val; - fdc->stat &= ~0x80; - } else { + return; + case 4: /* DSR */ + if (!(fdc->flags & FDC_FLAG_NO_DSR_RESET)) { + if (!(val & 0x80)) { + timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); + fdc->interrupt = -6; + } + if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) + fdc_soft_reset(fdc); + } + fdc->dsr = val; + return; + case 5: /*Command register*/ + if (fdc->fifointest) { + /* Write FIFO buffer in the test mode (PS/55) */ + fdc_log("FIFO buffer position = %X\n", ((fifo_t *) fdc->fifo_p)->end); fifo_write(val, fdc->fifo_p); if (fifo_get_full(fdc->fifo_p)) fdc->stat &= ~0x80; + break; } - break; - } - if (fdc->pnum == fdc->ptot) { - if ((fdc->stat & 0xf0) != 0x80) { - /* If bit 4 of the MSR is set, or the MSR is 0x00, - the fdc_t is NOT in the command phase, therefore - do NOT accept commands. */ - return; + if ((fdc->stat & 0xf0) == 0xb0) { + if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { + fdc->dat = val; + fdc->stat &= ~0x80; + } else { + fifo_write(val, fdc->fifo_p); + if (fifo_get_full(fdc->fifo_p)) + fdc->stat &= ~0x80; + } + break; } + if (fdc->pnum == fdc->ptot) { + if ((fdc->stat & 0xf0) != 0x80) { + /* If bit 4 of the MSR is set, or the MSR is 0x00, + the fdc_t is NOT in the command phase, therefore + do NOT accept commands. */ + return; + } - fdc->stat &= 0xf; + fdc->stat &= 0xf; - fdc->tc = 0; - fdc->data_ready = 0; + fdc->tc = 0; + fdc->data_ready = 0; - fdc->command = val; - fdc->stat |= 0x10; - fdc_log("Starting FDC command %02X\n", fdc->command); - fdc->error = 0; + fdc->command = val; + fdc->stat |= 0x10; + fdc_log("Starting FDC command %02X\n", fdc->command); + fdc->error = 0; - if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) || - ((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) || - ((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) || - ((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) || - ((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d)) - fdc->processed_cmd = fdc->command & 0x1f; - else - fdc->processed_cmd = fdc->command; + if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) || + ((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) || + ((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) || + ((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) || + ((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d)) + fdc->processed_cmd = fdc->command & 0x1f; + else + fdc->processed_cmd = fdc->command; - switch (fdc->processed_cmd) { - case 0x01: /*Mode*/ - if (fdc->flags & FDC_FLAG_NSC) { - fdc->pnum = 0; - fdc->ptot = 4; + switch (fdc->processed_cmd) { + case 0x01: /*Mode*/ + if (fdc->flags & FDC_FLAG_NSC) { + fdc->pnum = 0; + fdc->ptot = 4; + fdc->stat |= 0x90; + fdc->format_state = 0; + } else + fdc_bad_command(fdc); + break; + case 0x02: /*Read track*/ + fdc->satisfying_sectors = 0; + fdc->sc = 0; + fdc->wrong_am = 0; + fdc->pnum = 0; + fdc->ptot = 8; fdc->stat |= 0x90; - fdc->format_state = 0; - } else - fdc_bad_command(fdc); - break; - case 0x02: /*Read track*/ - fdc->satisfying_sectors = 0; - fdc->sc = 0; - fdc->wrong_am = 0; - fdc->pnum = 0; - fdc->ptot = 8; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x03: /*Specify*/ - fdc->pnum = 0; - fdc->ptot = 2; - fdc->stat |= 0x90; - break; - case 0x04: /*Sense drive status*/ - fdc->pnum = 0; - fdc->ptot = 1; - fdc->stat |= 0x90; - break; - case 0x05: /*Write data*/ - case 0x09: /*Write deleted data*/ - fdc->satisfying_sectors = 0; - fdc->sc = 0; - fdc->wrong_am = 0; - fdc->deleted = ((fdc->command & 0x1F) == 9) ? 1 : 0; - fdc->pnum = 0; - fdc->ptot = 8; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x06: /*Read data*/ - case 0x0c: /*Read deleted data*/ - case 0x11: /*Scan equal*/ - case 0x19: /*Scan low or equal*/ - case 0x16: /*Verify*/ - case 0x1d: /*Scan high or equal*/ - fdc->satisfying_sectors = 0; - fdc->sc = 0; - fdc->wrong_am = 0; - fdc->deleted = ((fdc->command & 0x1F) == 0xC) ? 1 : 0; - if ((fdc->command & 0x1F) == 0x16) - fdc->deleted = 2; - fdc->deleted |= (fdc->command & 0x20); - fdc->pnum = 0; - fdc->ptot = 8; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x17: /*Powerdown mode*/ - if (!(fdc->flags & FDC_FLAG_ALI)) { - fdc_bad_command(fdc); + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; break; - } - fallthrough; - case 0x07: /*Recalibrate*/ - fdc->pnum = 0; - fdc->ptot = 1; - fdc->stat |= 0x90; - break; - case 0x08: /*Sense interrupt status*/ - fdc_log("fdc->fintr = %i, fdc->reset_stat = %i\n", fdc->fintr, fdc->reset_stat); - fdc->lastdrive = fdc->drive; - fdc_sis(fdc); - break; - case 0x0a: /*Read sector ID*/ - fdc->pnum = 0; - fdc->ptot = 1; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - break; - case 0x0d: /*Format track*/ - fdc->pnum = 0; - fdc->ptot = 5; - fdc->stat |= 0x90; - fdc->mfm = (fdc->command & 0x40) ? 1 : 0; - fdc->format_state = 0; - break; - case 0x0e: /*Dump registers*/ - if (fdc->flags & FDC_FLAG_NEC) { - fdc_bad_command(fdc); + case 0x03: /*Specify*/ + fdc->pnum = 0; + fdc->ptot = 2; + fdc->stat |= 0x90; break; - } - fdc->lastdrive = fdc->drive; - fdc->interrupt = 0x0e; - fdc_callback(fdc); - break; - case 0x0f: /*Seek*/ - fdc->pnum = 0; - fdc->ptot = 2; - fdc->stat |= 0x90; - break; - case 0x18: /*NSC*/ - if (!(fdc->flags & FDC_FLAG_NSC)) { - fdc_bad_command(fdc); - break; - } - fallthrough; - case 0x10: /*Get version*/ - case 0x14: /*Unlock*/ - case 0x94: /*Lock*/ - if (fdc->flags & FDC_FLAG_NEC) { - fdc_bad_command(fdc); - break; - } - fdc->lastdrive = fdc->drive; - fdc->interrupt = fdc->command; - fdc_callback(fdc); - break; - case 0x12: /*Set perpendicular mode*/ - if ((fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_PCJR)) { + case 0x04: /*Sense drive status*/ fdc->pnum = 0; fdc->ptot = 1; fdc->stat |= 0x90; - } else - fdc_bad_command(fdc); - break; - case 0x13: /*Configure*/ - if (fdc->flags & FDC_FLAG_NEC) { - fdc_bad_command(fdc); break; - } - fdc->pnum = 0; - fdc->ptot = 3; - fdc->stat |= 0x90; - break; - default: - fdc_bad_command(fdc); - break; - } - } else { - fdc->stat = 0x10 | (fdc->stat & 0xf); - fdc->params[fdc->pnum++] = val; - if (fdc->pnum == 1) { - if (command_has_drivesel[fdc->command & 0x1F]) { - if (fdc->flags & FDC_FLAG_PCJR) - fdc->drive = 0; - else - fdc->drive = fdc->dor & 3; - fdc->rw_drive = fdc->params[0] & 3; - if (((fdc->command & 0x1F) == 7) || ((fdc->command & 0x1F) == 15)) - fdc->stat |= (1 << real_drive(fdc, fdc->drive)); - } - } - if (fdc->pnum == fdc->ptot) { - fdc_log("Got all params %02X\n", fdc->command); - fifo_reset(fdc->fifo_p); - fdc->interrupt = fdc->processed_cmd; - fdc->reset_stat = 0; - /* Disable timer if enabled. */ - timer_disable(&fdc->timer); - /* Start timer if needed at this point. */ - switch (fdc->interrupt & 0x1f) { - case 0x02: /* Read a track */ - case 0x03: /* Specify */ - case 0x0a: /* Read sector ID */ - case 0x05: /* Write data */ - case 0x06: /* Read data */ - case 0x09: /* Write deleted data */ - case 0x0c: /* Read deleted data */ - case 0x11: /* Scan equal */ - case 0x12: /* Perpendicular mode */ - case 0x16: /* Verify */ - case 0x19: /* Scan low or equal */ - case 0x1d: /* Scan high or equal */ - /* Do nothing. */ + case 0x05: /*Write data*/ + case 0x09: /*Write deleted data*/ + fdc->satisfying_sectors = 0; + fdc->sc = 0; + fdc->wrong_am = 0; + fdc->deleted = ((fdc->command & 0x1F) == 9) ? 1 : 0; + fdc->pnum = 0; + fdc->ptot = 8; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; break; - case 0x07: /* Recalibrate */ - case 0x0f: /* Seek */ - if (fdc->flags & FDC_FLAG_PCJR) - timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC); - else - timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); + case 0x06: /*Read data*/ + case 0x0c: /*Read deleted data*/ + case 0x11: /*Scan equal*/ + case 0x19: /*Scan low or equal*/ + case 0x16: /*Verify*/ + case 0x1d: /*Scan high or equal*/ + fdc->satisfying_sectors = 0; + fdc->sc = 0; + fdc->wrong_am = 0; + fdc->deleted = ((fdc->command & 0x1F) == 0xC) ? 1 : 0; + if ((fdc->command & 0x1F) == 0x16) + fdc->deleted = 2; + fdc->deleted |= (fdc->command & 0x20); + fdc->pnum = 0; + fdc->ptot = 8; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; break; - default: - timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); - break; - } - /* Process the firt phase of the command. */ - switch (fdc->processed_cmd) { - case 0x02: /* Read a track */ - fdc_io_command_phase1(fdc, 0); - fdc->read_track_sector.id.c = fdc->params[1]; - fdc->read_track_sector.id.h = fdc->params[2]; - fdc->read_track_sector.id.r = 1; - fdc->read_track_sector.id.n = fdc->params[4]; - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; + case 0x17: /*Powerdown mode*/ + if (!(fdc->flags & FDC_FLAG_ALI)) { + fdc_bad_command(fdc); + break; } - fdd_readsector(real_drive(fdc, fdc->drive), SECTOR_FIRST, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); - break; - case 0x03: /* Specify */ - fdc->stat = 0x80; - fdc->specify[0] = fdc->params[0]; - fdc->specify[1] = fdc->params[1]; - fdc->dma = (fdc->specify[1] & 1) ^ 1; - if (!fdc->dma) - dma_set_drq(fdc->dma_ch, 0); - break; - case 0x04: /*Sense drive status*/ - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - break; - case 0x05: /* Write data */ - case 0x09: /* Write deleted data */ - fdc_io_command_phase1(fdc, 1); - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; - } - fdd_writesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); - break; - case 0x11: /* Scan equal */ - case 0x19: /* Scan low or equal */ - case 0x1d: /* Scan high or equal */ - fdc_io_command_phase1(fdc, 1); - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; - } - fdd_comparesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); - break; - case 0x16: /* Verify */ - if (fdc->params[0] & 0x80) - fdc->sc = fdc->params[7]; fallthrough; - case 0x06: /* Read data */ - case 0x0c: /* Read deleted data */ - fdc_io_command_phase1(fdc, 0); - fdc_log("Reading sector (drive %i) (%i) (%i %i %i %i) (%i %i %i)\n", fdc->drive, fdc->params[0], fdc->params[1], fdc->params[2], fdc->params[3], fdc->params[4], fdc->params[5], fdc->params[6], fdc->params[7]); - if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { - fdc_noidam(fdc); - return; - } - if (((dma_mode(2) & 0x0C) == 0x00) && !(fdc->flags & FDC_FLAG_PCJR) && fdc->dma) { - /* DMA is in verify mode, treat this like a VERIFY command. */ - fdc_log("Verify-mode read!\n"); - fdc->tc = 1; - fdc->deleted |= 2; - } - fdd_readsector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + case 0x07: /*Recalibrate*/ + fdc->pnum = 0; + fdc->ptot = 1; + fdc->stat |= 0x90; break; - - case 0x07: /* Recalibrate */ - fdc->rw_drive = fdc->params[0] & 3; - fdc->stat = (1 << real_drive(fdc, fdc->drive)); - if (!(fdc->flags & FDC_FLAG_PCJR)) - fdc->stat |= 0x80; - fdc->st0 = fdc->params[0] & 3; - fdc->st0 |= fdd_get_head(real_drive(fdc, fdc->drive)) ? 0x04 : 0x00; - fdc->st0 |= 0x80; - drive_num = real_drive(fdc, fdc->drive); - /* Three conditions under which the command should fail. */ - if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num] || fdd_track0(drive_num)) { - fdc_log("Failed recalibrate\n"); - if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num]) - fdc->st0 = 0x70 | (fdc->params[0] & 3); - else - fdc->st0 = 0x20 | (fdc->params[0] & 3); - fdc->pcn[fdc->params[0] & 3] = 0; - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } + case 0x08: /*Sense interrupt status*/ + fdc_log("fdc->fintr = %i, fdc->reset_stat = %i\n", fdc->fintr, fdc->reset_stat); + fdc->lastdrive = fdc->drive; + fdc_sis(fdc); + break; + case 0x0a: /*Read sector ID*/ + fdc->pnum = 0; + fdc->ptot = 1; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; + break; + case 0x0d: /*Format track*/ + fdc->pnum = 0; + fdc->ptot = 5; + fdc->stat |= 0x90; + fdc->mfm = (fdc->command & 0x40) ? 1 : 0; + fdc->format_state = 0; + break; + case 0x0e: /*Dump registers*/ + if (fdc->flags & FDC_FLAG_NEC) { + fdc_bad_command(fdc); break; } - if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) - fdc_seek(fdc, fdc->drive, -fdc->max_track); - fdc_log("Recalibrating...\n"); - fdc->seek_dir = fdc->step = 1; + fdc->lastdrive = fdc->drive; + fdc->interrupt = 0x0e; + fdc_callback(fdc); break; - case 0x0a: /* Read sector ID */ - fdc_rate(fdc, fdc->drive); - fdc->head = (fdc->params[0] & 4) ? 1 : 0; - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) { - fdd_readaddress(real_drive(fdc, fdc->drive), fdc->head, fdc->rate); - if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) - fdc->stat = 0x70; - else - fdc->stat = 0x50; + case 0x0f: /*Seek*/ + fdc->pnum = 0; + fdc->ptot = 2; + fdc->stat |= 0x90; + break; + case 0x18: /*NSC*/ + if (!(fdc->flags & FDC_FLAG_NSC)) { + fdc_bad_command(fdc); + break; + } + fallthrough; + case 0x10: /*Get version*/ + case 0x14: /*Unlock*/ + case 0x94: /*Lock*/ + if (fdc->flags & FDC_FLAG_NEC) { + fdc_bad_command(fdc); + break; + } + fdc->lastdrive = fdc->drive; + fdc->interrupt = fdc->command; + fdc_callback(fdc); + break; + case 0x12: /*Set perpendicular mode*/ + if ((fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_PCJR)) { + fdc->pnum = 0; + fdc->ptot = 1; + fdc->stat |= 0x90; } else - fdc_noidam(fdc); + fdc_bad_command(fdc); break; - case 0x0d: /* Format */ - fdc_rate(fdc, fdc->drive); - fdc->head = (fdc->params[0] & 4) ? 1 : 0; - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - fdc->gap = fdc->params[3]; - fdc->format_sectors = fdc->params[2]; - fdc->format_n = fdc->params[1]; - fdc->format_state = 1; - fdc->stat = 0x10; - break; - case 0x0f: /* Seek */ - fdc->rw_drive = fdc->params[0] & 3; - fdc->stat = (1 << fdc->drive); - if (!(fdc->flags & FDC_FLAG_PCJR)) - fdc->stat |= 0x80; - fdc->head = 0; /* TODO: See if this is correct. */ - fdc->st0 = fdc->params[0] & 0x03; - fdc->st0 |= (fdc->params[0] & 4); - fdc->st0 |= 0x80; - fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); - drive_num = real_drive(fdc, fdc->drive); - /* Three conditions under which the command should fail. */ - if (!fdd_get_flags(drive_num) || (drive_num >= FDD_NUM) || !motoron[drive_num]) { - /* Yes, failed SEEK's still report success, unlike failed RECALIBRATE's. */ - fdc->st0 = 0x20 | (fdc->params[0] & 3); - if (fdc->command & 0x80) { - if (fdc->command & 0x40) - fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; - else - fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; - } else - fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } + case 0x13: /*Configure*/ + if (fdc->flags & FDC_FLAG_NEC) { + fdc_bad_command(fdc); break; } - if (fdc->command & 0x80) { - if (fdc->params[1]) { - if (fdc->command & 0x40) { - /* Relative seek inwards. */ - fdc->seek_dir = 0; - fdc_seek(fdc, fdc->drive, fdc->params[1]); - fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; - } else { - /* Relative seek outwards. */ - fdc->seek_dir = 1; - fdc_seek(fdc, fdc->drive, -fdc->params[1]); - fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; - } - fdc->step = 1; - } else { - fdc->st0 = 0x20 | (fdc->params[0] & 3); - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } - break; - } - } else { - fdc_log("Seeking to track %i (PCN = %i)...\n", fdc->params[1], fdc->pcn[fdc->params[0] & 3]); - if ((fdc->params[1] - fdc->pcn[fdc->params[0] & 3]) == 0) { - fdc_log("Failed seek\n"); - fdc->st0 = 0x20 | (fdc->params[0] & 3); - if (fdc->flags & FDC_FLAG_PCJR) { - fdc->fintr = 1; - fdc->interrupt = -4; - } else { - timer_disable(&fdc->timer); - fdc->interrupt = -3; - fdc_callback(fdc); - } - break; - } - if (fdc->params[1] > fdc->pcn[fdc->params[0] & 3]) - fdc->seek_dir = 0; - else - fdc->seek_dir = 1; - fdc_seek(fdc, fdc->drive, fdc->params[1] - fdc->pcn[fdc->params[0] & 3]); - fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; - fdc->step = 1; - } + fdc->pnum = 0; + fdc->ptot = 3; + fdc->stat |= 0x90; break; - case 0x12: /* Perpendicular mode */ - fdc->stat = 0x80; - if (fdc->params[0] & 0x80) - fdc->perp = fdc->params[0] & 0x3f; - else { - fdc->perp &= 0xfc; - fdc->perp |= (fdc->params[0] & 0x03); - } - return; - default: + fdc_bad_command(fdc); break; } - } else - fdc->stat = 0x90 | (fdc->stat & 0xf); - } - return; - case 7: - if (!(fdc->flags & FDC_FLAG_TOSHIBA) && !(fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_UMC)) - return; - fdc->rate = val & 0x03; - if (fdc->flags & FDC_FLAG_PS2) - fdc->noprec = !!(val & 0x04); - return; + } else { + fdc->stat = 0x10 | (fdc->stat & 0xf); + fdc->params[fdc->pnum++] = val; + if (fdc->pnum == 1) { + if (command_has_drivesel[fdc->command & 0x1F]) { + if (fdc->flags & FDC_FLAG_PCJR) + fdc->drive = 0; + else + fdc->drive = fdc->dor & 3; + fdc->rw_drive = fdc->params[0] & 3; + if (((fdc->command & 0x1F) == 7) || ((fdc->command & 0x1F) == 15)) + fdc->stat |= (1 << real_drive(fdc, fdc->drive)); + } + } + if (fdc->pnum == fdc->ptot) { + fdc_log("Got all params %02X\n", fdc->command); + fifo_reset(fdc->fifo_p); + fdc->interrupt = fdc->processed_cmd; + fdc->reset_stat = 0; + /* Disable timer if enabled. */ + timer_disable(&fdc->timer); + /* Start timer if needed at this point. */ + switch (fdc->interrupt & 0x1f) { + case 0x02: /* Read a track */ + case 0x03: /* Specify */ + case 0x0a: /* Read sector ID */ + case 0x05: /* Write data */ + case 0x06: /* Read data */ + case 0x09: /* Write deleted data */ + case 0x0c: /* Read deleted data */ + case 0x11: /* Scan equal */ + case 0x12: /* Perpendicular mode */ + case 0x16: /* Verify */ + case 0x19: /* Scan low or equal */ + case 0x1d: /* Scan high or equal */ + /* Do nothing. */ + break; + case 0x07: /* Recalibrate */ + case 0x0f: /* Seek */ + if (fdc->flags & FDC_FLAG_PCJR) + timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC); + else + timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); + break; + default: + timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC); + break; + } + /* Process the firt phase of the command. */ + switch (fdc->processed_cmd) { + case 0x02: /* Read a track */ + fdc_io_command_phase1(fdc, 0); + fdc->read_track_sector.id.c = fdc->params[1]; + fdc->read_track_sector.id.h = fdc->params[2]; + fdc->read_track_sector.id.r = 1; + fdc->read_track_sector.id.n = fdc->params[4]; + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + fdd_readsector(real_drive(fdc, fdc->drive), SECTOR_FIRST, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; + case 0x03: /* Specify */ + fdc->stat = 0x80; + fdc->specify[0] = fdc->params[0]; + fdc->specify[1] = fdc->params[1]; + fdc->dma = (fdc->specify[1] & 1) ^ 1; + if (!fdc->dma) + dma_set_drq(fdc->dma_ch, 0); + break; + case 0x04: /*Sense drive status*/ + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + break; + case 0x05: /* Write data */ + case 0x09: /* Write deleted data */ + fdc_io_command_phase1(fdc, 1); + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + fdd_writesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; + case 0x11: /* Scan equal */ + case 0x19: /* Scan low or equal */ + case 0x1d: /* Scan high or equal */ + fdc_io_command_phase1(fdc, 1); + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + fdd_comparesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; + case 0x16: /* Verify */ + if (fdc->params[0] & 0x80) + fdc->sc = fdc->params[7]; + fallthrough; + case 0x06: /* Read data */ + case 0x0c: /* Read deleted data */ + fdc_io_command_phase1(fdc, 0); + fdc_log("Reading sector (drive %i) (%i) (%i %i %i %i) (%i %i %i)\n", fdc->drive, fdc->params[0], fdc->params[1], fdc->params[2], fdc->params[3], fdc->params[4], fdc->params[5], fdc->params[6], fdc->params[7]); + if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) { + fdc_noidam(fdc); + return; + } + if (((dma_mode(2) & 0x0C) == 0x00) && !(fdc->flags & FDC_FLAG_PCJR) && fdc->dma) { + /* DMA is in verify mode, treat this like a VERIFY command. */ + fdc_log("Verify-mode read!\n"); + fdc->tc = 1; + fdc->deleted |= 2; + } + fdd_readsector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]); + break; - default: - break; - } + case 0x07: /* Recalibrate */ + fdc->rw_drive = fdc->params[0] & 3; + fdc->stat = 0x10 | (1 << real_drive(fdc, fdc->drive)); + if (!(fdc->flags & FDC_FLAG_PCJR)) + fdc->stat |= 0x80; + fdc->st0 = fdc->params[0] & 3; + fdc->st0 |= fdd_get_head(real_drive(fdc, fdc->drive)) ? 0x04 : 0x00; + fdc->st0 |= 0x80; + drive_num = real_drive(fdc, fdc->drive); + /* Three conditions under which the command should fail. */ + if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num] || fdd_track0(drive_num)) { + fdc_log("Failed recalibrate\n"); + if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num]) + fdc->st0 = 0x70 | (fdc->params[0] & 3); + else + fdc->st0 = 0x20 | (fdc->params[0] & 3); + fdc->pcn[fdc->params[0] & 3] = 0; + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) + fdc_seek(fdc, fdc->drive, -fdc->max_track); + fdc_log("Recalibrating...\n"); + fdc->seek_dir = fdc->step = 1; + break; + case 0x0a: /* Read sector ID */ + fdc_rate(fdc, fdc->drive); + fdc->head = (fdc->params[0] & 4) ? 1 : 0; + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) { + fdd_readaddress(real_drive(fdc, fdc->drive), fdc->head, fdc->rate); + if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) + fdc->stat = 0x70; + else + fdc->stat = 0x50; + } else + fdc_noidam(fdc); + break; + case 0x0d: /* Format */ + fdc_rate(fdc, fdc->drive); + fdc->head = (fdc->params[0] & 4) ? 1 : 0; + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + fdc->gap = fdc->params[3]; + fdc->format_sectors = fdc->params[2]; + fdc->format_n = fdc->params[1]; + fdc->format_state = 1; + fdc->stat = 0x10; + break; + case 0x0f: /* Seek */ + fdc->rw_drive = fdc->params[0] & 3; + fdc->stat = 0x10 | (1 << fdc->drive); + if (!(fdc->flags & FDC_FLAG_PCJR)) + fdc->stat |= 0x80; + fdc->head = 0; /* TODO: See if this is correct. */ + fdc->st0 = fdc->params[0] & 0x03; + fdc->st0 |= (fdc->params[0] & 4); + fdc->st0 |= 0x80; + fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0); + drive_num = real_drive(fdc, fdc->drive); + /* Three conditions under which the command should fail. */ + if (!fdd_get_flags(drive_num) || (drive_num >= FDD_NUM) || !motoron[drive_num]) { + /* Yes, failed SEEK's still report success, unlike failed RECALIBRATE's. */ + fdc->st0 = 0x20 | (fdc->params[0] & 3); + if (fdc->command & 0x80) { + if (fdc->command & 0x40) + fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; + else + fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; + } else + fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + if (fdc->command & 0x80) { + if (fdc->params[1]) { + if (fdc->command & 0x40) { + /* Relative seek inwards. */ + fdc->seek_dir = 0; + fdc_seek(fdc, fdc->drive, fdc->params[1]); + fdc->pcn[fdc->params[0] & 3] += fdc->params[1]; + } else { + /* Relative seek outwards. */ + fdc->seek_dir = 1; + fdc_seek(fdc, fdc->drive, -fdc->params[1]); + fdc->pcn[fdc->params[0] & 3] -= fdc->params[1]; + } + fdc->step = 1; + } else { + fdc->st0 = 0x20 | (fdc->params[0] & 3); + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + } else { + fdc_log("Seeking to track %i (PCN = %i)...\n", fdc->params[1], fdc->pcn[fdc->params[0] & 3]); + if ((fdc->params[1] - fdc->pcn[fdc->params[0] & 3]) == 0) { + fdc_log("Failed seek\n"); + fdc->st0 = 0x20 | (fdc->params[0] & 3); + if (fdc->flags & FDC_FLAG_PCJR) { + fdc->fintr = 1; + fdc->interrupt = -4; + } else { + timer_disable(&fdc->timer); + fdc->interrupt = -3; + fdc_callback(fdc); + } + break; + } + if (fdc->params[1] > fdc->pcn[fdc->params[0] & 3]) + fdc->seek_dir = 0; + else + fdc->seek_dir = 1; + fdc_seek(fdc, fdc->drive, fdc->params[1] - fdc->pcn[fdc->params[0] & 3]); + fdc->pcn[fdc->params[0] & 3] = fdc->params[1]; + fdc->step = 1; + } + break; + case 0x12: /* Perpendicular mode */ + fdc->stat = 0x80; + if (fdc->params[0] & 0x80) + fdc->perp = fdc->params[0] & 0x3f; + else { + fdc->perp &= 0xfc; + fdc->perp |= (fdc->params[0] & 0x03); + } + return; + + default: + break; + } + } else + fdc->stat = 0x90 | (fdc->stat & 0xf); + } + return; + case 7: + if (!(fdc->flags & FDC_FLAG_TOSHIBA) && !(fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_UMC)) + return; + fdc->rate = val & 0x03; + if (fdc->flags & FDC_FLAG_PS2) + fdc->noprec = !!(val & 0x04); + return; + + default: + break; + } } uint8_t @@ -1376,213 +1385,214 @@ fdc_read(uint16_t addr, void *priv) cycles -= ISA_CYCLES(8); - if (!fdc->power_down || ((addr & 7) == 2)) switch (addr & 7) { - case 0: /* STA */ - if (fdc->flags & FDC_FLAG_PS2) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x00; - /* TODO: - Bit 2: INDEX (best return always 0 as it goes by very fast) - */ - if (fdc->seek_dir) /* nDIRECTION */ - ret |= 0x01; - if (writeprot[drive]) /* WRITEPROT */ - ret |= 0x02; - if (!fdd_get_head(drive)) /* nHDSEL */ - ret |= 0x08; - if (fdd_track0(drive)) /* TRK0 */ - ret |= 0x10; - if (fdc->step) /* STEP */ - ret |= 0x20; - if (dma_get_drq(fdc->dma_ch)) /* DRQ */ - ret |= 0x40; - if (fdc->fintr || fdc->reset_stat) /* INTR */ - ret |= 0x80; - } else if (fdc->flags & FDC_FLAG_PS2_MCA) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x04; - /* TODO: - Bit 2: nINDEX (best return always 1 as it goes by very fast) - */ - if (!fdc->seek_dir) /* DIRECTION */ - ret |= 0x01; - if (!writeprot[drive]) /* nWRITEPROT */ - ret |= 0x02; - if (fdd_get_head(drive)) /* HDSEL */ - ret |= 0x08; - if (!fdd_track0(drive)) /* nTRK0 */ - ret |= 0x10; - if (fdc->step) /* STEP */ - ret |= 0x20; - if (!fdd_get_type(1)) /* -Drive 2 Installed */ - ret |= 0x40; - if (fdc->fintr || fdc->reset_stat) /* INTR */ - ret |= 0x80; - } else - ret = 0xff; - break; - case 1: /* STB */ - if (fdc->flags & FDC_FLAG_PS2) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x00; - if (!fdd_get_type(1)) /* -Drive 2 Installed */ - ret |= 0x80; - switch (drive) { /* -Drive Select 1,0 */ - case 0: - ret |= 0x43; - break; - case 1: - ret |= 0x23; - break; - case 2: - ret |= 0x62; - break; - case 3: - ret |= 0x61; - break; - - default: - break; - } - } else if (fdc->flags & FDC_FLAG_PS2_MCA) { - drive = real_drive(fdc, fdc->dor & 3); - ret = 0xc0; - ret |= (fdc->dor & 0x01) << 5; /* Drive Select 0 */ - ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ - } else { - if (is486 || !fdc->enable_3f1) + if (!fdc->power_down || ((addr & 7) == 2)) + switch (addr & 7) { + case 0: /* STA */ + if (fdc->flags & FDC_FLAG_PS2) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x00; + /* TODO: + Bit 2: INDEX (best return always 0 as it goes by very fast) + */ + if (fdc->seek_dir) /* nDIRECTION */ + ret |= 0x01; + if (writeprot[drive]) /* WRITEPROT */ + ret |= 0x02; + if (!fdd_get_head(drive)) /* nHDSEL */ + ret |= 0x08; + if (fdd_track0(drive)) /* TRK0 */ + ret |= 0x10; + if (fdc->step) /* STEP */ + ret |= 0x20; + if (dma_get_drq(fdc->dma_ch)) /* DRQ */ + ret |= 0x40; + if (fdc->fintr || fdc->reset_stat) /* INTR */ + ret |= 0x80; + } else if (fdc->flags & FDC_FLAG_PS2_MCA) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x04; + /* TODO: + Bit 2: nINDEX (best return always 1 as it goes by very fast) + */ + if (!fdc->seek_dir) /* DIRECTION */ + ret |= 0x01; + if (!writeprot[drive]) /* nWRITEPROT */ + ret |= 0x02; + if (fdd_get_head(drive)) /* HDSEL */ + ret |= 0x08; + if (!fdd_track0(drive)) /* nTRK0 */ + ret |= 0x10; + if (fdc->step) /* STEP */ + ret |= 0x20; + if (!fdd_get_type(1)) /* -Drive 2 Installed */ + ret |= 0x40; + if (fdc->fintr || fdc->reset_stat) /* INTR */ + ret |= 0x80; + } else ret = 0xff; - else { - if (fdc->flags & FDC_FLAG_UMC) { - drive = real_drive(fdc, fdc->dor & 1); - ret = !fdd_is_dd(drive) ? ((fdc->dor & 1) ? 2 : 1) : 0; - } else { - /* TODO: What is this and what is it used for? - It's almost identical to the PS/2 MCA mode. */ - drive = real_drive(fdc, fdc->dor & 3); - ret = 0x70; - ret &= ~(drive ? 0x40 : 0x20); - ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ + break; + case 1: /* STB */ + if (fdc->flags & FDC_FLAG_PS2) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x00; + if (!fdd_get_type(1)) /* -Drive 2 Installed */ + ret |= 0x80; + switch (drive) { /* -Drive Select 1,0 */ + case 0: + ret |= 0x43; + break; + case 1: + ret |= 0x23; + break; + case 2: + ret |= 0x62; + break; + case 3: + ret |= 0x61; + break; + + default: + break; + } + } else if (fdc->flags & FDC_FLAG_PS2_MCA) { + drive = real_drive(fdc, fdc->dor & 3); + ret = 0xc0; + ret |= (fdc->dor & 0x01) << 5; /* Drive Select 0 */ + ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ + } else { + if (is486 || !fdc->enable_3f1) + ret = 0xff; + else { + if (fdc->flags & FDC_FLAG_UMC) { + drive = real_drive(fdc, fdc->dor & 1); + ret = !fdd_is_dd(drive) ? ((fdc->dor & 1) ? 2 : 1) : 0; + } else { + /* TODO: What is this and what is it used for? + It's almost identical to the PS/2 MCA mode. */ + drive = real_drive(fdc, fdc->dor & 3); + ret = 0x70; + ret &= ~(drive ? 0x40 : 0x20); + ret |= (fdc->dor & 0x30) >> 4; /* Motor Select 1, 0 */ + } } } - } - break; - case 2: - ret = fdc->dor; - break; - case 3: - drive = real_drive(fdc, fdc->dor & 3); - /* TODO: FDC_FLAG_PS2_TDR? */ - if ((fdc->flags & FDC_FLAG_PS2) || (fdc->flags & FDC_FLAG_PS2_MCA)) { - /* PS/1 Model 2121 seems return drive type in port - * 0x3f3, despite the 82077AA fdc_t not implementing - * this. This is presumably implemented outside the - * fdc_t on one of the motherboard's support chips. - * - * Confirmed: 00=1.44M 3.5 - * 10=2.88M 3.5 - * 20=1.2M 5.25 - * 30=1.2M 5.25 - * - * as reported by Configur.exe. - */ - if (fdd_is_525(drive)) - ret = 0x20; - else if (fdd_is_ed(drive)) - ret = 0x10; - else - ret = 0x00; - /* PS/55 POST throws an error and halt if ret = 1 or 2, somehow. */ - } else if (!fdc->enh_mode) - ret = 0x20; - else if (fdc->flags & FDC_FLAG_SMC661) - ret = (fdc->densel_force << 3) | ((!!fdc->swap) << 5) | (fdc->media_id << 6); - else - ret = (fdc->rwc[drive] << 4) | (fdc->media_id << 6); - break; - case 4: /*Status*/ - ret = fdc->stat; - break; - case 5: /*Data*/ - if (fdc->fifointest) { - /* Read FIFO buffer in the test mode (PS/55) */ - ret = fifo_read(fdc->fifo_p); break; - } - if ((fdc->stat & 0xf0) == 0xf0) { - fdc->stat &= ~0x80; - if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { - fdc->data_ready = 0; - ret = fdc->dat; - } else - ret = fifo_read(fdc->fifo_p); + case 2: + ret = fdc->dor; break; - } - if (fdc->paramstogo) { - fdc->stat &= ~0x80; - fdc_log("%i parameters to go\n", fdc->paramstogo); - fdc->paramstogo--; - ret = fdc->res[10 - fdc->paramstogo]; - if (!fdc->paramstogo) - fdc->stat = 0x80; - else - fdc->stat |= 0xC0; - } else if (fdc->dma) { - ret = fdc->dat; - break; - } else { - fdc->stat &= ~0x80; - if (lastbyte) - fdc->stat = 0x80; - lastbyte = 0; - ret = fdc->dat; - fdc->data_ready = 0; - } - fdc->stat &= 0xf0; - break; - case 7: /*Disk change*/ - drive = real_drive(fdc, fdc->dor & 3); - - if (fdc->flags & FDC_FLAG_PS2) { - if (fdc->dor & (0x10 << drive)) { - ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x00 : 0x80; - ret |= (fdc->dor & 0x08); - ret |= (fdc->noprec << 2); - ret |= (fdc->rate & 0x03); - } else - ret = 0x00; - } else if (fdc->flags & FDC_FLAG_PS2_MCA) { - if (fdc->dor & (0x10 << drive)) { - ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00; - ret |= ((fdc->rate & 0x03) << 1); - ret |= fdc_get_densel(fdc, drive); - ret |= 0x78; - } else - ret = 0xf9; - } else { - if (fdc->dor & (0x10 << drive)) { - if ((drive == 1) && (fdc->flags & FDC_FLAG_TOSHIBA)) - ret = 0x00; + case 3: + drive = real_drive(fdc, fdc->dor & 3); + /* TODO: FDC_FLAG_PS2_TDR? */ + if ((fdc->flags & FDC_FLAG_PS2) || (fdc->flags & FDC_FLAG_PS2_MCA)) { + /* PS/1 Model 2121 seems return drive type in port + * 0x3f3, despite the 82077AA fdc_t not implementing + * this. This is presumably implemented outside the + * fdc_t on one of the motherboard's support chips. + * + * Confirmed: 00=1.44M 3.5 + * 10=2.88M 3.5 + * 20=1.2M 5.25 + * 30=1.2M 5.25 + * + * as reported by Configur.exe. + */ + if (fdd_is_525(drive)) + ret = 0x20; + else if (fdd_is_ed(drive)) + ret = 0x10; else + ret = 0x00; + /* PS/55 POST throws an error and halt if ret = 1 or 2, somehow. */ + } else if (!fdc->enh_mode) + ret = 0x20; + else if (fdc->flags & FDC_FLAG_SMC661) + ret = (fdc->densel_force << 3) | ((!!fdc->swap) << 5) | (fdc->media_id << 6); + else + ret = (fdc->rwc[drive] << 4) | (fdc->media_id << 6); + break; + case 4: /*Status*/ + ret = fdc->stat; + break; + case 5: /*Data*/ + if (fdc->fifointest) { + /* Read FIFO buffer in the test mode (PS/55) */ + ret = fifo_read(fdc->fifo_p); + break; + } + if ((fdc->stat & 0xf0) == 0xf0) { + fdc->stat &= ~0x80; + if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) { + fdc->data_ready = 0; + ret = fdc->dat; + } else + ret = fifo_read(fdc->fifo_p); + break; + } + if (fdc->paramstogo) { + fdc->stat &= ~0x80; + fdc_log("%i parameters to go\n", fdc->paramstogo); + fdc->paramstogo--; + ret = fdc->res[10 - fdc->paramstogo]; + if (!fdc->paramstogo) + fdc->stat = 0x80; + else + fdc->stat |= 0xC0; + } else if (fdc->dma) { + ret = fdc->dat; + break; + } else { + fdc->stat &= ~0x80; + if (lastbyte) + fdc->stat = 0x80; + lastbyte = 0; + ret = fdc->dat; + fdc->data_ready = 0; + } + fdc->stat &= 0xf0; + break; + case 7: /*Disk change*/ + drive = real_drive(fdc, fdc->dor & 3); + + if (fdc->flags & FDC_FLAG_PS2) { + if (fdc->dor & (0x10 << drive)) { + ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x00 : 0x80; + ret |= (fdc->dor & 0x08); + ret |= (fdc->noprec << 2); + ret |= (fdc->rate & 0x03); + } else + ret = 0x00; + } else if (fdc->flags & FDC_FLAG_PS2_MCA) { + if (fdc->dor & (0x10 << drive)) { ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00; - } else - ret = 0x00; - if (fdc->flags & FDC_FLAG_DISKCHG_ACTLOW) /*PC2086/3086 seem to reverse this bit*/ - ret ^= 0x80; + ret |= ((fdc->rate & 0x03) << 1); + ret |= fdc_get_densel(fdc, drive); + ret |= 0x78; + } else + ret = 0xf9; + } else { + if (fdc->dor & (0x10 << drive)) { + if ((drive == 1) && (fdc->flags & FDC_FLAG_TOSHIBA)) + ret = 0x00; + else + ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00; + } else + ret = 0x00; + if (fdc->flags & FDC_FLAG_DISKCHG_ACTLOW) /*PC2086/3086 seem to reverse this bit*/ + ret ^= 0x80; - /* 0 = ????, 1 = Ext. FDD off, 2 = Ext. FDD = FDD A, 3 = Ext. FDD = FDD B */ - if (fdc->flags & FDC_FLAG_TOSHIBA) { - ret |= (3 << 5); - ret |= 0x01; - } else - ret |= 0x7F; - } + /* 0 = ????, 1 = Ext. FDD off, 2 = Ext. FDD = FDD A, 3 = Ext. FDD = FDD B */ + if (fdc->flags & FDC_FLAG_TOSHIBA) { + ret |= (3 << 5); + ret |= 0x01; + } else + ret |= 0x7F; + } - fdc->step = 0; - break; - default: - ret = 0xff; - } + fdc->step = 0; + break; + default: + ret = 0xff; + } fdc_log("[%04X:%08X] Read FDC %04X %02X [%i:%02X]\n", CS, cpu_state.pc, addr, ret, drive, fdc->dor & (0x10 << drive)); return ret; } @@ -1886,7 +1896,7 @@ fdc_callback(void *priv) } else fdc->interrupt = -3; timer_set_delay_u64(&fdc->timer, 2048 * TIMER_USEC); - fdc->stat = 0x80 | (1 << fdc->rw_drive); + fdc->stat = 0x10 | (1 << fdc->rw_drive); return; case 0x0d: /*Format track*/ if (fdc->format_state == 1) { @@ -1929,7 +1939,7 @@ fdc_callback(void *priv) return; case 0x0f: /*Seek*/ fdc->st0 = 0x20 | (fdc->params[0] & 3); - fdc->stat = 0x80 | (1 << fdc->rw_drive); + fdc->stat = 0x10 | (1 << fdc->rw_drive); // Interrupts and callbacks in the fdd callback function return; case 0x10: /*Version*/ @@ -2863,4 +2873,4 @@ const device_t fdc_ps2_mca_device = { .speed_changed = NULL, .force_redraw = NULL, .config = NULL -}; +}; \ No newline at end of file diff --git a/src/floppy/fdd.c b/src/floppy/fdd.c index a0bef7ac6..212317f49 100644 --- a/src/floppy/fdd.c +++ b/src/floppy/fdd.c @@ -79,11 +79,34 @@ typedef struct fdd_t { fdd_t fdd[FDD_NUM]; +enum { + FDD_OP_NONE = 0, + FDD_OP_READ, + FDD_OP_WRITE, + FDD_OP_COMPARE, + FDD_OP_READADDR, + FDD_OP_FORMAT +}; + +typedef struct fdd_pending_op_t { + int pending; + int op; + int sector; + int track; + int side; + int density; + int sector_size; + uint8_t fill; +} fdd_pending_op_t; + +static fdd_pending_op_t fdd_pending[FDD_NUM]; + char floppyfns[FDD_NUM][512]; char *fdd_image_history[FDD_NUM][FLOPPY_IMAGE_HISTORY]; pc_timer_t fdd_poll_time[FDD_NUM]; pc_timer_t fdd_seek_timer[FDD_NUM]; +int fdd_seek_in_progress[FDD_NUM] = { 0, 0, 0, 0 }; static int fdd_notfound = 0; static int driveloaders[FDD_NUM]; @@ -293,10 +316,49 @@ fdd_seek_complete_callback(void *priv) { DRIVE *drive = (DRIVE *) priv; + fdd_seek_in_progress[drive->id] = 0; + fdd_log("fdd_seek_complete_callback(drive=%d) - TIMER FIRED! seek_in_progress=1\n", drive->id); fdd_log("Notifying FDC of seek completion\n"); fdd_do_seek(drive->id, fdd[drive->id].track); - fdc_seek_complete_interrupt(fdd_fdc, drive->id); + + int had_pending = fdd_pending[drive->id].pending; + if (had_pending) { + fdd_pending_op_t *po = &fdd_pending[drive->id]; + fdd_log("Starting deferred op %d after seek on drive %d (trk=%d, side=%d, sec=%d)\n", + po->op, drive->id, po->track, po->side, po->sector); + + switch (po->op) { + case FDD_OP_READ: + if (drives[drive->id].readsector) + drives[drive->id].readsector(drive->id, po->sector, po->track, po->side, po->density, po->sector_size); + break; + case FDD_OP_WRITE: + if (drives[drive->id].writesector) + drives[drive->id].writesector(drive->id, po->sector, po->track, po->side, po->density, po->sector_size); + break; + case FDD_OP_COMPARE: + if (drives[drive->id].comparesector) + drives[drive->id].comparesector(drive->id, po->sector, po->track, po->side, po->density, po->sector_size); + break; + case FDD_OP_READADDR: + if (drives[drive->id].readaddress) + drives[drive->id].readaddress(drive->id, po->side, po->density); + break; + case FDD_OP_FORMAT: + if (drives[drive->id].format) + drives[drive->id].format(drive->id, po->side, po->density, po->fill); + break; + default: + break; + } + + po->pending = 0; + po->op = FDD_OP_NONE; + } + + if (!had_pending) + fdc_seek_complete_interrupt(fdd_fdc, drive->id); } void @@ -306,6 +368,11 @@ fdd_seek(int drive, int track_diff) if (!track_diff) return; + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek already in progress for drive %d, ignoring new seek request\n", drive); + return; + } + int old_track = fdd[drive].track; fdd[drive].track += track_diff; @@ -327,12 +394,14 @@ fdd_seek(int drive, int track_diff) /* Multi-track seek */ fdd_audio_play_multi_track_seek(drive, old_track, fdd[drive].track); } - + if (old_track + track_diff < 0) { fdd_do_seek(drive, fdd[drive].track); return; } + fdd_seek_in_progress[drive] = 1; + if (!fdd_seek_timer[drive].callback) { timer_add(&(fdd_seek_timer[drive]), fdd_seek_complete_callback, &drives[drive], 0); } @@ -629,7 +698,7 @@ fdd_set_motor_enable(int drive, int motor_enable) { fdd_log("fdd_set_motor_enable(%d, %d)\n", drive, motor_enable); fdd_audio_set_motor_enable(drive, motor_enable); - + if (motor_enable && !motoron[drive]) { timer_set_delay_u64(&fdd_poll_time[drive], fdd_byteperiod(drive)); } else if (!motor_enable && motoron[drive]) { @@ -700,6 +769,22 @@ void fdd_readsector(int drive, int sector, int track, int side, int density, int sector_size) { fdd_log("fdd_readsector(%d, %d, %d, %d, %d, %d)\n", drive, sector, track, side, density, sector_size); + + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring READ (trk=%d->%d, side=%d, sec=%d)\n", + drive, fdd[drive].track, track, side, sector); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_READ, + .sector = sector, + .track = track, + .side = side, + .density = density, + .sector_size = sector_size + }; + return; + } + if (drives[drive].readsector) drives[drive].readsector(drive, sector, track, side, density, sector_size); else @@ -710,6 +795,22 @@ void fdd_writesector(int drive, int sector, int track, int side, int density, int sector_size) { fdd_log("fdd_writesector(%d, %d, %d, %d, %d, %d)\n", drive, sector, track, side, density, sector_size); + + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring WRITE (trk=%d->%d, side=%d, sec=%d)\n", + drive, fdd[drive].track, track, side, sector); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_WRITE, + .sector = sector, + .track = track, + .side = side, + .density = density, + .sector_size = sector_size + }; + return; + } + if (drives[drive].writesector) drives[drive].writesector(drive, sector, track, side, density, sector_size); else @@ -719,6 +820,21 @@ fdd_writesector(int drive, int sector, int track, int side, int density, int sec void fdd_comparesector(int drive, int sector, int track, int side, int density, int sector_size) { + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring COMPARE (trk=%d->%d, side=%d, sec=%d)\n", + drive, fdd[drive].track, track, side, sector); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_COMPARE, + .sector = sector, + .track = track, + .side = side, + .density = density, + .sector_size = sector_size + }; + return; + } + if (drives[drive].comparesector) drives[drive].comparesector(drive, sector, track, side, density, sector_size); else @@ -728,6 +844,19 @@ fdd_comparesector(int drive, int sector, int track, int side, int density, int s void fdd_readaddress(int drive, int side, int density) { + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring READADDRESS (trk=%d, side=%d)\n", + drive, fdd[drive].track, side); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_READADDR, + .track = fdd[drive].track, + .side = side, + .density = density + }; + return; + } + if (drives[drive].readaddress) drives[drive].readaddress(drive, side, density); } @@ -735,6 +864,20 @@ fdd_readaddress(int drive, int side, int density) void fdd_format(int drive, int side, int density, uint8_t fill) { + if (fdd_seek_in_progress[drive]) { + fdd_log("Seek in progress on drive %d, deferring FORMAT (trk=%d, side=%d)\n", + drive, fdd[drive].track, side); + fdd_pending[drive] = (fdd_pending_op_t) { + .pending = 1, + .op = FDD_OP_FORMAT, + .track = fdd[drive].track, + .side = side, + .density = density, + .fill = fill + }; + return; + } + if (drives[drive].format) drives[drive].format(drive, side, density, fill); else @@ -777,7 +920,7 @@ fdd_init(void) if (fdd_sounds_enabled) { fdd_audio_init(); - } + } } void diff --git a/src/floppy/fdd_audio.c b/src/floppy/fdd_audio.c index 409ddfe8c..04ae9ba68 100644 --- a/src/floppy/fdd_audio.c +++ b/src/floppy/fdd_audio.c @@ -176,6 +176,7 @@ static int16_t * load_wav(const char *filename, int *sample_count) { FILE *f = NULL; + char full_path[2048]; if ((filename == NULL) || (strlen(filename) == 0)) return NULL; From fe0277c03135168a0f97582ea6537e4df0c75987 Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 27 Sep 2025 13:28:23 +0200 Subject: [PATCH 265/274] FDC: Fix a warning and the incorrect status flags. --- src/floppy/fdc.c | 6 +++--- src/floppy/fdd_audio.c | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index 212bf9ce0..44adc569b 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -184,7 +184,7 @@ fdc_ctrl_reset(void *priv) { fdc_t *fdc = (fdc_t *) priv; - fdc->stat = 0x10; + fdc->stat = 0x80; fdc->pnum = fdc->ptot = 0; fdc->st0 = 0; fdc->head = 0; @@ -1211,7 +1211,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) case 0x07: /* Recalibrate */ fdc->rw_drive = fdc->params[0] & 3; - fdc->stat = 0x10 | (1 << real_drive(fdc, fdc->drive)); + fdc->stat = (1 << real_drive(fdc, fdc->drive)); if (!(fdc->flags & FDC_FLAG_PCJR)) fdc->stat |= 0x80; fdc->st0 = fdc->params[0] & 3; @@ -1266,7 +1266,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) break; case 0x0f: /* Seek */ fdc->rw_drive = fdc->params[0] & 3; - fdc->stat = 0x10 | (1 << fdc->drive); + fdc->stat = (1 << fdc->drive); if (!(fdc->flags & FDC_FLAG_PCJR)) fdc->stat |= 0x80; fdc->head = 0; /* TODO: See if this is correct. */ diff --git a/src/floppy/fdd_audio.c b/src/floppy/fdd_audio.c index 04ae9ba68..409ddfe8c 100644 --- a/src/floppy/fdd_audio.c +++ b/src/floppy/fdd_audio.c @@ -176,7 +176,6 @@ static int16_t * load_wav(const char *filename, int *sample_count) { FILE *f = NULL; - char full_path[2048]; if ((filename == NULL) || (strlen(filename) == 0)) return NULL; From bc085ac02f5481cd0d4df344340fadf2384d9636 Mon Sep 17 00:00:00 2001 From: andresdelcampo <33843515+andresdelcampo@users.noreply.github.com> Date: Sat, 27 Sep 2025 13:31:46 +0200 Subject: [PATCH 266/274] Change window resizing logic when using 4:3 aspect ratio (#6233) Change window resizing logic when using 4:3 aspect ratio to resize content only. Fixed issues in Remember size and position that are derived from the change. There is a slight flicker while resizing with force 4:3 aspect ratio. --- src/qt/qt_mainwindow.cpp | 154 +++++++++++++++++---------------------- src/qt/qt_mainwindow.hpp | 4 +- 2 files changed, 70 insertions(+), 88 deletions(-) diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index 954547078..fbc2d8a47 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -84,6 +84,7 @@ extern bool cpu_thread_running; #include #include #include +#include #include #include #include @@ -171,8 +172,6 @@ extern "C" void qt_blit(int x, int y, int w, int h, int monitor_index); extern MainWindow *main_window; -bool MainWindow::s_adjustingForce43 = false; - MainWindow::MainWindow(QWidget *parent) : QMainWindow(parent) , ui(new Ui::MainWindow) @@ -933,11 +932,15 @@ MainWindow::closeEvent(QCloseEvent *event) } } if (window_remember) { - window_w = ui->stackedWidget->width(); - window_h = ui->stackedWidget->height(); + // If maximized, persist the normal (restorable) geometry + const bool wasMax = isMaximized(); + QRect normal = wasMax ? this->normalGeometry() : this->geometry(); + // Save WINDOW size (not the content widget’s 4:3 box) + window_w = normal.width(); + window_h = normal.height(); if (!QApplication::platformName().contains("wayland")) { - window_x = this->geometry().x(); - window_y = this->geometry().y(); + window_x = normal.x(); + window_y = normal.y(); } for (int i = 1; i < MONITORS_NUM; i++) { if (renderers[i]) { @@ -1021,65 +1024,56 @@ void MainWindow::updateShortcuts() seq = QKeySequence::fromString(acc_keys[accID].seq); ui->actionMute_Unmute->setShortcut(seq); } - -void -MainWindow::adjustForForce43(const QSize &newWinSize) + +void +MainWindow::applyContentLayoutForCurrentState() { - // Only act in resizable mode with Force 4:3 enabled and not fullscreen - if (!(vid_resize == 1 && force_43 > 0) || video_fullscreen || s_adjustingForce43) - return; + auto applyFill = [this](const QRect& r){ + ui->stackedWidget->setGeometry(r); + ui->stackedWidget->onResize(r.width(), r.height()); + if (monitors[0].mon_scrnsz_x != r.width() || monitors[0].mon_scrnsz_y != r.height()) { + monitors[0].mon_scrnsz_x = r.width(); + monitors[0].mon_scrnsz_y = r.height(); + plat_resize_request(r.width(), r.height(), 0); + } + }; - s_adjustingForce43 = true; + auto apply43 = [this](const QRect& area){ + int areaW = area.width(); + int areaH = area.height(); + if (areaW <= 0 || areaH <= 0) return; - // Height consumed by menu/status/toolbars - int chromeH = menuBar()->height() - + (hide_status_bar ? 0 : statusBar()->height()) - + (hide_tool_bar ? 0 : ui->toolBar->height()); + int targetW = areaW; + int targetH = (areaW * 3) / 4; + if (targetH > areaH) { + targetH = areaH; + targetW = (areaH * 4) / 3; + } - // Compute client area size in device‑independent pixels - double dpr = (!dpi_scale ? util::screenOfWidget(this)->devicePixelRatio() : 1.0); - int winW = newWinSize.width(); - int winH = newWinSize.height(); - int clientW = static_cast(winW / dpr); - int clientH = static_cast((winH - chromeH) / dpr); + const int x = area.x() + (areaW - targetW) / 2; + const int y = area.y() + (areaH - targetH) / 2; - if (clientW <= 0 || clientH <= 0) { - s_adjustingForce43 = false; - return; - } + ui->stackedWidget->setGeometry(x, y, targetW, targetH); + ui->stackedWidget->onResize(targetW, targetH); - // Decide which dimension the user changed most – adjust the other - int curW = static_cast(width() / dpr); - int curH = static_cast((height() - chromeH) / dpr); - bool widthChanged = std::abs(clientW - curW) >= std::abs(clientH - curH); + if (monitors[0].mon_scrnsz_x != targetW || monitors[0].mon_scrnsz_y != targetH) { + monitors[0].mon_scrnsz_x = targetW; + monitors[0].mon_scrnsz_y = targetH; + plat_resize_request(targetW, targetH, 0); + } + }; - int targetW, targetH; - if (widthChanged) { - // user dragged width – compute matching height for 4:3 - targetW = clientW; - targetH = (clientW * 3) / 4; - } else { - // user dragged height – compute matching width for 4:3 - targetH = clientH; - targetW = (clientH * 4) / 3; - } + QWidget *cw = this->centralWidget(); + if (!cw) return; - // Convert back to window size including chrome and apply - int newW = static_cast(targetW * dpr); - int newH = static_cast(targetH * dpr) + chromeH; - if (newW != winW || newH != winH) - resize(newW, newH); + const QRect area = cw->contentsRect(); - // Update emulator framebuffer size and notify platform - monitors[0].mon_scrnsz_x = targetW; - monitors[0].mon_scrnsz_y = targetH; - plat_resize_request(targetW, targetH, 0); + // Fullscreen always fills (legacy behavior) + if (video_fullscreen) { applyFill(area); return; } - // Allow renderer widget to grow and recompute scaling - ui->stackedWidget->setFixedSize(QWIDGETSIZE_MAX, QWIDGETSIZE_MAX); - ui->stackedWidget->onResize(width(), height()); - - s_adjustingForce43 = false; + // Windowed: enforce 4:3 only when requested, otherwise fill + if (force_43 > 0) apply43(area); + else applyFill(area); } void @@ -1088,26 +1082,10 @@ MainWindow::resizeEvent(QResizeEvent *event) //qDebug() << pos().x() + event->size().width(); //qDebug() << pos().y() + event->size().height(); - // Enforce 4:3 aspect ratio in resizable mode when the option is set - adjustForForce43(event->size()); - - if (vid_resize == 1 || video_fullscreen) - return; + // Always let QMainWindow do its layout first + QMainWindow::resizeEvent(event); - int newX = pos().x(); - int newY = pos().y(); - - if (((frameGeometry().x() + event->size().width() + 1) > util::screenOfWidget(this)->availableGeometry().right())) { - //move(util::screenOfWidget(this)->availableGeometry().right() - size().width() - 1, pos().y()); - newX = util::screenOfWidget(this)->availableGeometry().right() - frameGeometry().width() - 1; - if (newX < 1) newX = 1; - } - - if (((frameGeometry().y() + event->size().height() + 1) > util::screenOfWidget(this)->availableGeometry().bottom())) { - newY = util::screenOfWidget(this)->availableGeometry().bottom() - frameGeometry().height() - 1; - if (newY < 1) newY = 1; - } - move(newX, newY); + applyContentLayoutForCurrentState(); } void @@ -1201,12 +1179,25 @@ MainWindow::showEvent(QShowEvent *event) monitors[0].mon_scrnsz_y = fixed_size_y; } if (window_remember && vid_resize == 1) { - ui->stackedWidget->setFixedSize(window_w, window_h); + const QSize target(window_w, window_h); + const QSize prevMin = ui->stackedWidget->minimumSize(); + const QSize prevMax = ui->stackedWidget->maximumSize(); + + ui->stackedWidget->setMinimumSize(target); + ui->stackedWidget->setMaximumSize(target); #ifndef Q_OS_MACOS QApplication::processEvents(); #endif this->adjustSize(); + + ui->stackedWidget->setMinimumSize(prevMin); + ui->stackedWidget->setMaximumSize(prevMax); + ui->stackedWidget->resize(target); } + + QTimer::singleShot(0, this, [this]{ + applyContentLayoutForCurrentState(); + }); } void @@ -1509,6 +1500,7 @@ MainWindow::on_actionFullscreen_triggered() { if (video_fullscreen > 0) { showNormal(); + QTimer::singleShot(0, this, [this]{ applyContentLayoutForCurrentState(); }); ui->menubar->show(); if (!hide_status_bar) ui->statusbar->show(); @@ -2146,16 +2138,7 @@ MainWindow::on_actionForce_4_3_display_ratio_triggered() { video_toggle_option(ui->actionForce_4_3_display_ratio, &force_43); - // When turning on Force 4:3 in resizable mode, immediately snap to 4:3 - if (vid_resize == 1 && !video_fullscreen) { - ui->stackedWidget->setFixedSize(QWIDGETSIZE_MAX, QWIDGETSIZE_MAX); - if (force_43 > 0) { - adjustForForce43(size()); - } else { - // Turning off: refresh renderer scaling - ui->stackedWidget->onResize(width(), height()); - } - } + QTimer::singleShot(0, this, [this]{ applyContentLayoutForCurrentState(); }); } void @@ -2524,4 +2507,3 @@ void MainWindow::on_actionCGA_composite_settings_triggered() isNonPause = false; config_save(); } - diff --git a/src/qt/qt_mainwindow.hpp b/src/qt/qt_mainwindow.hpp index f562c2ea9..77e8fe7c4 100644 --- a/src/qt/qt_mainwindow.hpp +++ b/src/qt/qt_mainwindow.hpp @@ -179,8 +179,8 @@ private: std::shared_ptr mm; static bool s_adjustingForce43; // guard against recursion - void adjustForForce43(const QSize &newWinSize); - + void applyContentLayoutForCurrentState(); + void updateShortcuts(); void processKeyboardInput(bool down, uint32_t keycode); #ifdef Q_OS_MACOS From 3fd58dde8f5d619c24001c7c1bf4f3cd516326d7 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Sat, 27 Sep 2025 17:32:00 +0600 Subject: [PATCH 267/274] Implement YUV aperture on Mach64 VT2 (#6234) Some GDBSTUB fixes --- src/gdbstub.c | 4 + src/video/vid_ati_mach64.c | 336 ++++++++++++++++++++++++++----------- 2 files changed, 243 insertions(+), 97 deletions(-) diff --git a/src/gdbstub.c b/src/gdbstub.c index cbbf0ede7..6e1e9af26 100644 --- a/src/gdbstub.c +++ b/src/gdbstub.c @@ -879,6 +879,7 @@ e22: /* Read by qwords, then by dwords, then by words, then by bytes. */ i = 0; + cpl_override = 1; if (is386) { for (; i < (k & ~7); i += 8) { *((uint64_t *) buf) = readmemql(j); @@ -900,6 +901,7 @@ e22: buf[0] = readmembl(j++); gdbstub_client_respond_hex(client, buf, 1); } + cpl_override = 0; break; case 'M': /* write memory */ @@ -934,6 +936,7 @@ e22: /* Write by qwords, then by dwords, then by words, then by bytes. */ p = client->packet; i = 0; + cpl_override = 1; if (is386) { for (; i < (k & ~7); i += 8) { writememql(j, *((uint64_t *) p)); @@ -955,6 +958,7 @@ e22: writemembl(j++, p[0]); p++; } + cpl_override = 0; /* Respond positively. */ goto ok; diff --git a/src/video/vid_ati_mach64.c b/src/video/vid_ati_mach64.c index 6a9b9ea34..221af0d3f 100644 --- a/src/video/vid_ati_mach64.c +++ b/src/video/vid_ati_mach64.c @@ -39,6 +39,7 @@ #include <86box/vid_svga.h> #include <86box/vid_svga_render.h> #include <86box/vid_ati_eeprom.h> +#include <86box/bswap.h> #ifdef CLAMP # undef CLAMP @@ -80,6 +81,7 @@ enum { typedef struct mach64_t { mem_mapping_t linear_mapping; mem_mapping_t mmio_mapping; + mem_mapping_t linear_mapping_big_endian; mem_mapping_t mmio_linear_mapping; mem_mapping_t mmio_linear_mapping_2; @@ -98,6 +100,8 @@ typedef struct mach64_t { uint8_t pci_slot; uint8_t irq_state; + uint8_t on_board; + uint8_t pci_regs[256]; uint8_t int_line; @@ -272,7 +276,7 @@ typedef struct mach64_t { uint32_t cur_clr0; uint32_t cur_clr1; - uint32_t overlay_dat[1024]; + uint32_t overlay_dat[2048]; uint32_t overlay_graphics_key_clr; uint32_t overlay_graphics_key_msk; uint32_t overlay_video_key_clr; @@ -286,12 +290,17 @@ typedef struct mach64_t { uint32_t scaler_height_width; int scaler_format; int scaler_update; + int scaler_yuv_aper; uint32_t buf_offset[2]; uint32_t buf_pitch[2]; int overlay_v_acc; + uint32_t overlay_uv_addr; + uint32_t overlay_cur_y; + uint32_t overlay_base; + uint8_t thread_run; void *i2c; void *ddc; @@ -381,6 +390,9 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv); void mach64_ext_writew(uint32_t addr, uint16_t val, void *priv); void mach64_ext_writel(uint32_t addr, uint32_t val, void *priv); +uint8_t mach64_readb_be(uint32_t addr, void *priv); +void mach64_writeb_be(uint32_t addr, uint8_t val, void *priv); + #ifdef ENABLE_MACH64_LOG int mach64_do_log = ENABLE_MACH64_LOG; @@ -591,6 +603,7 @@ mach64_updatemapping(mach64_t *mach64) mach64_log("Update mapping - PCI disabled\n"); mem_mapping_disable(&svga->mapping); mem_mapping_disable(&mach64->linear_mapping); + mem_mapping_disable(&mach64->linear_mapping_big_endian); mem_mapping_disable(&mach64->mmio_mapping); mem_mapping_disable(&mach64->mmio_linear_mapping); mem_mapping_disable(&mach64->mmio_linear_mapping_2); @@ -645,14 +658,16 @@ mach64_updatemapping(mach64_t *mach64) } } else { /*2*8 MB aperture*/ - mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000); - mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000); - mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x4000), 0x4000); + mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 4096); + mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 4096), 4096); + mem_mapping_set_addr(&mach64->linear_mapping_big_endian, mach64->linear_base + (8 << 20), (8 << 20) - 0x1000); + mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x1000), 0x1000); } } else { mem_mapping_disable(&mach64->linear_mapping); mem_mapping_disable(&mach64->mmio_linear_mapping); mem_mapping_disable(&mach64->mmio_linear_mapping_2); + mem_mapping_disable(&mach64->linear_mapping_big_endian); } } @@ -2310,8 +2325,11 @@ mach64_vblank_start(svga_t *svga) svga->overlay.ena = (mach64->overlay_scale_cntl & OVERLAY_EN) && (overlay_cmp_mix != 1); - mach64->overlay_v_acc = 0; - mach64->scaler_update = 1; + mach64->overlay_v_acc = 0; + mach64->scaler_update = 1; + mach64->overlay_uv_addr = svga->overlay.addr; + mach64->overlay_cur_y = 0; + mach64->overlay_base = svga->overlay.addr; } uint8_t @@ -2389,6 +2407,10 @@ mach64_ext_readb(uint32_t addr, void *priv) case 0x4a: ret = mach64->scaler_format; break; + + case 0x4b: + ret = mach64->scaler_yuv_aper; + break; default: ret = 0xff; @@ -2558,7 +2580,7 @@ mach64_ext_readb(uint32_t addr, void *priv) case 0xc7: READ8(addr, mach64->dac_cntl); - if (mach64->type == MACH64_VT2) { + if (mach64->type >= MACH64_VT2) { ret &= 0xf9; if (i2c_gpio_get_scl(mach64->i2c)) ret |= 0x04; @@ -2957,7 +2979,8 @@ mach64_ext_readw(uint32_t addr, void *priv) if (!(addr & 0x400)) { mach64_log("mach64_ext_readw: addr=%04x\n", addr); - ret = 0xffff; + ret = mach64_ext_readb(addr, priv); + ret |= mach64_ext_readb(addr + 1, priv) << 8; } else switch (addr & 0x3ff) { case 0xb4: @@ -2986,7 +3009,8 @@ mach64_ext_readl(uint32_t addr, void *priv) if (!(addr & 0x400)) { mach64_log("mach64_ext_readl: addr=%04x\n", addr); - ret = 0xffffffff; + ret = mach64_ext_readw(addr, priv); + ret |= mach64_ext_readw(addr + 2, priv) << 16; } else switch (addr & 0x3ff) { case 0x18: @@ -3087,6 +3111,10 @@ mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv) case 0x4a: mach64->scaler_format = val & 0xf; break; + + case 0x4b: + mach64->scaler_yuv_aper = val; + break; case 0x80: case 0x81: @@ -4106,76 +4134,113 @@ mach64_int_hwcursor_draw(svga_t *svga, int displine) } \ } while (0) -#define DECODE_VYUY422() \ - do { \ - for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x += 2) { \ - uint8_t y1, y2; \ - int8_t u, v; \ - int dR, dG, dB; \ - int r, g, b; \ - \ - y1 = src[0]; \ - u = src[1] - 0x80; \ - y2 = src[2]; \ - v = src[3] - 0x80; \ - src += 4; \ - \ - dR = (359 * v) >> 8; \ - dG = (88 * u + 183 * v) >> 8; \ - dB = (453 * u) >> 8; \ - \ - r = y1 + dR; \ - CLAMP(r); \ - g = y1 - dG; \ - CLAMP(g); \ - b = y1 + dB; \ - CLAMP(b); \ - mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \ - \ - r = y2 + dR; \ - CLAMP(r); \ - g = y2 - dG; \ - CLAMP(g); \ - b = y2 + dB; \ - CLAMP(b); \ - mach64->overlay_dat[x + 1] = (r << 16) | (g << 8) | b; \ - } \ +#define DECODE_VYUY422() \ + do { \ + for (x = 0; x < src_w; x += 1) { \ + uint8_t y1, y2; \ + int8_t u, v; \ + int dR, dG, dB; \ + int r, g, b; \ + \ + y1 = src[0]; \ + u = src[1] - 0x80; \ + y2 = src[2]; \ + v = src[3] - 0x80; \ + src += 4; \ + \ + dR = (359 * v) >> 8; \ + dG = (88 * u + 183 * v) >> 8; \ + dB = (453 * u) >> 8; \ + \ + r = y1 + dR; \ + CLAMP(r); \ + g = y1 - dG; \ + CLAMP(g); \ + b = y1 + dB; \ + CLAMP(b); \ + mach64->overlay_dat[x * 2] = (r << 16) | (g << 8) | b; \ + \ + r = y2 + dR; \ + CLAMP(r); \ + g = y2 - dG; \ + CLAMP(g); \ + b = y2 + dB; \ + CLAMP(b); \ + mach64->overlay_dat[(x * 2) + 1] = (r << 16) | (g << 8) | b; \ + } \ } while (0) -#define DECODE_YVYU422() \ - do { \ - for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x += 2) { \ - uint8_t y1, y2; \ - int8_t u, v; \ - int dR, dG, dB; \ - int r, g, b; \ - \ - u = src[0] - 0x80; \ - y1 = src[1]; \ - v = src[2] - 0x80; \ - y2 = src[3]; \ - src += 4; \ - \ - dR = (359 * v) >> 8; \ - dG = (88 * u + 183 * v) >> 8; \ - dB = (453 * u) >> 8; \ - \ - r = y1 + dR; \ - CLAMP(r); \ - g = y1 - dG; \ - CLAMP(g); \ - b = y1 + dB; \ - CLAMP(b); \ - mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \ - \ - r = y2 + dR; \ - CLAMP(r); \ - g = y2 - dG; \ - CLAMP(g); \ - b = y2 + dB; \ - CLAMP(b); \ - mach64->overlay_dat[x + 1] = (r << 16) | (g << 8) | b; \ - } \ +#define DECODE_YVYU422() \ + do { \ + for (x = 0; x < src_w; x += 1) { \ + uint8_t y1, y2; \ + int8_t u, v; \ + int dR, dG, dB; \ + int r, g, b; \ + \ + u = src[0] - 0x80; \ + y1 = src[1]; \ + v = src[2] - 0x80; \ + y2 = src[3]; \ + src += 4; \ + \ + dR = (359 * v) >> 8; \ + dG = (88 * u + 183 * v) >> 8; \ + dB = (453 * u) >> 8; \ + \ + r = y1 + dR; \ + CLAMP(r); \ + g = y1 - dG; \ + CLAMP(g); \ + b = y1 + dB; \ + CLAMP(b); \ + mach64->overlay_dat[x * 2] = (r << 16) | (g << 8) | b; \ + \ + r = y2 + dR; \ + CLAMP(r); \ + g = y2 - dG; \ + CLAMP(g); \ + b = y2 + dB; \ + CLAMP(b); \ + mach64->overlay_dat[(x * 2) + 1] = (r << 16) | (g << 8) | b; \ + } \ + } while (0) + +#define DECODE_YUV12_PACKED() \ + do { \ + for (x = 0; x < src_w; x += 1) { \ + uint8_t y1, y2; \ + int8_t u, v; \ + int dR, dG, dB; \ + int r, g, b; \ + \ + u = uvsrc[3] - 0x80; \ + y1 = src[0]; \ + v = uvsrc[2] - 0x80; \ + y2 = src[1]; \ + src += 4; \ + uvsrc += 4; \ + \ + dR = (359 * v) >> 8; \ + dG = (88 * u + 183 * v) >> 8; \ + dB = (453 * u) >> 8; \ + \ + r = y1 + dR; \ + CLAMP(r); \ + g = y1 - dG; \ + CLAMP(g); \ + b = y1 + dB; \ + CLAMP(b); \ + mach64->overlay_dat[x * 2] = (r << 16) | (g << 8) | b; \ + \ + r = y2 + dR; \ + CLAMP(r); \ + g = y2 - dG; \ + CLAMP(g); \ + b = y2 + dB; \ + CLAMP(b); \ + mach64->overlay_dat[(x * 2) + 1] = (r << 16) | (g << 8) | b; \ + } \ } while (0) void @@ -4185,11 +4250,13 @@ mach64_overlay_draw(svga_t *svga, int displine) int x; int h_acc = 0; int h_max = (mach64->scaler_height_width >> 16) & 0x3ff; + int src_w = h_max; int h_inc = mach64->overlay_scale_inc >> 16; int v_max = mach64->scaler_height_width & 0x3ff; int v_inc = mach64->overlay_scale_inc & 0xffff; uint32_t *p; uint8_t *src = &svga->vram[svga->overlay.addr]; + uint8_t *uvsrc = src; int old_y = mach64->overlay_v_acc; int y_diff; int video_key_fn = mach64->overlay_key_cntl & 5; @@ -4198,6 +4265,11 @@ mach64_overlay_draw(svga_t *svga, int displine) p = &buffer32->line[displine][svga->x_add + mach64->svga.overlay_latch.x]; + if (mach64->overlay_cur_y >= 2) { + /* Avoid corrupt UV data on YUV12 packed modes */ + uvsrc = &svga->vram[mach64->overlay_base + svga->overlay.pitch * 2 * (!(mach64->overlay_cur_y & 1) ? (mach64->overlay_cur_y + 1) : mach64->overlay_cur_y)]; + } + if (mach64->scaler_update) { switch (mach64->scaler_format) { case 0x3: @@ -4209,6 +4281,9 @@ mach64_overlay_draw(svga_t *svga, int displine) case 0x6: DECODE_ARGB8888(); break; + case 0xa: + DECODE_YUV12_PACKED(); + break; case 0xb: DECODE_VYUY422(); break; @@ -4217,7 +4292,7 @@ mach64_overlay_draw(svga_t *svga, int displine) break; default: - mach64_log("Unknown Mach64 scaler format %x\n", mach64->scaler_format); + pclog("Unknown Mach64 scaler format %x\n", mach64->scaler_format); /*Fill buffer with something recognisably wrong*/ for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) mach64->overlay_dat[x] = 0xff00ff; @@ -4354,6 +4429,7 @@ mach64_overlay_draw(svga_t *svga, int displine) svga->overlay.addr += svga->overlay.pitch * 2 * y_diff; mach64->scaler_update = y_diff; + mach64->overlay_cur_y += y_diff; } static void @@ -4389,7 +4465,7 @@ mach64_io_remove(mach64_t *mach64) io_removehandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64); if (mach64->block_decoded_io && mach64->block_decoded_io < 0x10000) - io_removehandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64); + io_removehandler(mach64->block_decoded_io, 0x0100, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64); } static void @@ -4429,7 +4505,7 @@ mach64_io_set(mach64_t *mach64) io_sethandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64); if (mach64->use_block_decoded_io && mach64->block_decoded_io && mach64->block_decoded_io < 0x10000) - io_sethandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64); + io_sethandler(mach64->block_decoded_io, 0x0100, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64); } static uint8_t @@ -4478,7 +4554,6 @@ static void mach64_write_linear(uint32_t addr, uint8_t val, void *priv) { svga_t *svga = (svga_t *) priv; - cycles -= svga->monitor->mon_video_timing_write_b; addr &= svga->decode_mask; @@ -4507,10 +4582,38 @@ mach64_writew_linear(uint32_t addr, uint16_t val, void *priv) static void mach64_writel_linear(uint32_t addr, uint32_t val, void *priv) { - svga_t *svga = (svga_t *) priv; + svga_t *svga = (svga_t *) priv; + mach64_t *mach64 = (mach64_t *) svga->priv; cycles -= svga->monitor->mon_video_timing_write_l; + if (((mach64->scaler_yuv_aper >> 4) & 0xc) && !!(addr & 0x800000) == !(mach64->scaler_yuv_aper & 0x20)) { + uint32_t offset_from_base = addr & 0x7FFFFF; + if (addr & 0x800000) bswap32s(&val); + if (((mach64->scaler_yuv_aper >> 4) & 0xc) == 0x4) { // Y plane + offset_from_base <<= 1; + svga->vram[offset_from_base & svga->vram_mask] = (val & 0xFF); + svga->vram[(offset_from_base + 1) & svga->vram_mask] = ((val >> 8) & 0xFF); + svga->vram[(offset_from_base + 4) & svga->vram_mask] = ((val >> 16) & 0xFF); + svga->vram[(offset_from_base + 5) & svga->vram_mask] = ((val >> 24) & 0xFF); + } + else if (((mach64->scaler_yuv_aper >> 4) & 0xc) == 0x8 || ((mach64->scaler_yuv_aper >> 4) & 0xc) == 0xc) { + offset_from_base <<= 2; + if (((mach64->scaler_yuv_aper >> 4) & 0xc) == 0x8) { // U plane + svga->vram[(offset_from_base + 3) & svga->vram_mask] = (val & 0xFF); + svga->vram[(offset_from_base + 7) & svga->vram_mask] = ((val >> 8) & 0xFF); + svga->vram[(offset_from_base + 11) & svga->vram_mask] = ((val >> 16) & 0xFF); + svga->vram[(offset_from_base + 15) & svga->vram_mask] = ((val >> 24) & 0xFF); + } else { // V plane + svga->vram[(offset_from_base + 2) & svga->vram_mask] = (val & 0xFF); + svga->vram[(offset_from_base + 6) & svga->vram_mask] = ((val >> 8) & 0xFF); + svga->vram[(offset_from_base + 10) & svga->vram_mask] = ((val >> 16) & 0xFF); + svga->vram[(offset_from_base + 14) & svga->vram_mask] = ((val >> 24) & 0xFF); + } + } + return; + } + addr &= svga->decode_mask; if (addr >= svga->vram_max) return; @@ -4519,6 +4622,42 @@ mach64_writel_linear(uint32_t addr, uint32_t val, void *priv) *(uint32_t *) &svga->vram[addr] = val; } +uint8_t +mach64_readb_be(uint32_t addr, void *priv) +{ + return mach64_read_linear(addr, priv); +} + +uint16_t +mach64_readw_be(uint32_t addr, void *priv) +{ + return bswap16(mach64_readw_linear(addr, priv)); +} + +uint32_t +mach64_readl_be(uint32_t addr, void *priv) +{ + return bswap32(mach64_readl_linear(addr, priv)); +} + +void +mach64_writeb_be(uint32_t addr, uint8_t val, void *priv) +{ + return mach64_write_linear(addr, val, priv); +} + +void +mach64_writew_be(uint32_t addr, uint16_t val, void *priv) +{ + return mach64_writew_linear(addr, bswap16(val), priv); +} + +void +mach64_writel_be(uint32_t addr, uint32_t val, void *priv) +{ + return mach64_writel_linear(addr, bswap32(val), priv); +} + uint8_t mach64_pci_read(UNUSED(int func), int addr, void *priv) { @@ -4564,30 +4703,31 @@ mach64_pci_read(UNUSED(int func), int addr, void *priv) return mach64->linear_base >> 24; case 0x14: - if (mach64->type == MACH64_VT2) + if (mach64->type >= MACH64_VT2) return 0x01; /*Block decoded IO address*/ return 0x00; case 0x15: - if (mach64->type == MACH64_VT2) + if (mach64->type >= MACH64_VT2) return mach64->block_decoded_io >> 8; return 0x00; case 0x16: - if (mach64->type == MACH64_VT2) + if (mach64->type >= MACH64_VT2) return mach64->block_decoded_io >> 16; return 0x00; case 0x17: - if (mach64->type == MACH64_VT2) + if (mach64->type >= MACH64_VT2) return mach64->block_decoded_io >> 24; return 0x00; + case 0x30: - return mach64->pci_regs[0x30] & 0x01; /*BIOS ROM address*/ + return (mach64->on_board) ? 0 : (mach64->pci_regs[0x30] & 0x01); /*BIOS ROM address*/ case 0x31: return 0x00; case 0x32: - return mach64->pci_regs[0x32]; + return (mach64->on_board) ? 0 : mach64->pci_regs[0x32]; case 0x33: - return mach64->pci_regs[0x33]; + return (mach64->on_board) ? 0 : mach64->pci_regs[0x33]; case 0x3c: return mach64->int_line; @@ -4619,7 +4759,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) break; case 0x12: - if (mach64->type == MACH64_VT2) + if (mach64->type >= MACH64_VT2) val = 0; mach64->linear_base = (mach64->linear_base & 0xff000000) | ((val & 0x80) << 16); mach64_updatemapping(mach64); @@ -4630,16 +4770,16 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) break; case 0x15: - if (mach64->type == MACH64_VT2) { + if (mach64->type >= MACH64_VT2) { if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) mach64_io_remove(mach64); - mach64->block_decoded_io = (mach64->block_decoded_io & 0xffff0000) | ((val & 0xfc) << 8); + mach64->block_decoded_io = (mach64->block_decoded_io & 0xffff0000) | ((val & 0xff) << 8); if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) mach64_io_set(mach64); } break; case 0x16: - if (mach64->type == MACH64_VT2) { + if (mach64->type >= MACH64_VT2) { if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) mach64_io_remove(mach64); mach64->block_decoded_io = (mach64->block_decoded_io & 0xff00fc00) | (val << 16); @@ -4648,7 +4788,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) } break; case 0x17: - if (mach64->type == MACH64_VT2) { + if (mach64->type >= MACH64_VT2) { if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) mach64_io_remove(mach64); mach64->block_decoded_io = (mach64->block_decoded_io & 0x00fffc00) | (val << 24); @@ -4660,6 +4800,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) case 0x30: case 0x32: case 0x33: + if (mach64->on_board) return; mach64->pci_regs[addr] = val; if (mach64->pci_regs[0x30] & 0x01) { uint32_t biosaddr = (mach64->pci_regs[0x32] << 16) | (mach64->pci_regs[0x33] << 24); @@ -4679,7 +4820,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) mach64_io_remove(mach64); mach64->io_base = val & 0x03; - if (mach64->type == MACH64_VT2) + if (mach64->type >= MACH64_VT2) mach64->use_block_decoded_io = val & 0x04; if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) mach64_io_set(mach64); @@ -4700,7 +4841,7 @@ mach64_common_init(const device_t *info) svga = &mach64->svga; mach64->type = info->local & 0xff; - mach64->vram_size = device_get_config_int("memory"); + mach64->vram_size = (info->local & (1 << 20)) ? 4 : device_get_config_int("memory"); mach64->vram_mask = (mach64->vram_size << 20) - 1; if (mach64->type > MACH64_GX) @@ -4717,9 +4858,10 @@ mach64_common_init(const device_t *info) mach64_overlay_draw); mem_mapping_add(&mach64->linear_mapping, 0, 0, mach64_read_linear, mach64_readw_linear, mach64_readl_linear, mach64_write_linear, mach64_writew_linear, mach64_writel_linear, NULL, MEM_MAPPING_EXTERNAL, svga); + mem_mapping_add(&mach64->linear_mapping_big_endian, 0, 0, mach64_readb_be, mach64_readw_be, mach64_readl_be, mach64_writeb_be, mach64_writew_be, mach64_writel_be, NULL, MEM_MAPPING_EXTERNAL, svga); mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64); mem_mapping_add(&mach64->mmio_linear_mapping_2, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64); - mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64); + mem_mapping_add(&mach64->mmio_mapping, 0xbf000, 0x1000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64); mem_mapping_disable(&mach64->mmio_mapping); mach64_io_set(mach64); From 9ef1b194867a92ba681c4e482b08ad09c79702d7 Mon Sep 17 00:00:00 2001 From: Verloren50000 <110334428+Verloren50000@users.noreply.github.com> Date: Sat, 27 Sep 2025 19:32:46 +0800 Subject: [PATCH 268/274] Add the BCM FR510 (Packard Bell/NEC OEM) ROM + update (#6231) * machine.h: FR510 added. * m_at_sockets7.c: BCM FR510 added, including the BIOS Selector. * machine_table.c: BCM FR510 is now added. * machine_table.c: fr510-generic * m_at_sockets7.c: AGP Bridge for BCM FR510 * machine_table.c: FR510 PCIOnly * m_at_socket7.c: Fixes at FR510 * m_at_sockets7.c: 510S228.BIN -> 510S128.BIN * machine_table.c: an update for FR510 --- src/include/86box/machine.h | 4 +++ src/machine/m_at_sockets7.c | 69 +++++++++++++++++++++++++++++++++++++ src/machine/machine_table.c | 48 ++++++++++++++++++++++++-- 3 files changed, 119 insertions(+), 2 deletions(-) diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index b88d8f492..4fd0e16e8 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -1069,6 +1069,10 @@ extern int machine_at_m560_init(const machine_t *); /* m_at_sockets7.c */ /* ALi ALADDiN V */ extern int machine_at_p5a_init(const machine_t *); +#ifdef EMU_DEVICE_H +extern const device_t fr510_device; +#endif +extern int machine_at_fr510_init(const machine_t *); extern int machine_at_m579_init(const machine_t *); extern int machine_at_gwlucas_init(const machine_t *); extern int machine_at_5aa_init(const machine_t *); diff --git a/src/machine/m_at_sockets7.c b/src/machine/m_at_sockets7.c index a39b2cef4..a70bccc03 100644 --- a/src/machine/m_at_sockets7.c +++ b/src/machine/m_at_sockets7.c @@ -74,6 +74,75 @@ machine_at_p5a_init(const machine_t *model) return ret; } +static const device_config_t fr510_config[] = { + // clang-format off + { + .name = "bios", + .description = "BIOS Version", + .type = CONFIG_BIOS, + .default_string = "fr510", + .default_int = 0, + .file_filter = "", + .spinner = { 0 }, + .bios = { + { .name = "Award Modular BIOS v4.51PG - Revision 1.19 (01/15/1999)", .internal_name = "fr510_1999", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/fr510/FR510119.bin", "" } }, + { .name = "Award Modular BIOS v4.51PG - Revision SCC-128 (11/27/2002)", .internal_name = "fr510", .bios_type = BIOS_NORMAL, + .files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/fr510/510S128.BIN", "" } }, + { .files_no = 0 } + }, + }, + { .name = "", .description = "", .type = CONFIG_END } + // clang-format on +}; + +const device_t fr510_device = { + .name = "BCM FR510 (Packard Bell/NEC OEM)", + .internal_name = "fr510_device", + .flags = 0, + .local = 0, + .init = NULL, + .close = NULL, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = fr510_config +}; + +int +machine_at_fr510_init(const machine_t *model) +{ + int ret = 0; + const char* fn; + + /* No ROMs available */ + if (!device_available(model->device)) + return ret; + + device_context(model->device); + fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0); + ret = bios_load_linear(fn, 0x000c0000, 262144, 0); + device_context_restore(); + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1); + device_add(&ali1541_device); + device_add(&ali1543c_device); /* +0 */ + device_add(&sst_flash_39sf020_device); + spd_register(SPD_TYPE_SDRAM, 0x7, 512); + + if ((sound_card_current[0] == SOUND_INTERNAL) && machine_get_snd_device(machine)) + device_add(machine_get_snd_device(machine)); + + return ret; +} + int machine_at_m579_init(const machine_t *model) { diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 8c9055c9b..1ae51e5c7 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -12388,7 +12388,7 @@ const machine_t machines[] = { }, /* The BIOS sends KBC command B3 which indicates an AMI (or VIA VT82C42N) KBC. */ { - .name = "[i430FX] NEC PowerMate V", + .name = "[i430FX] NEC PowerMate Vxxx", .internal_name = "powermatev", .type = MACHINE_TYPE_SOCKET5, .chipset = MACHINE_CHIPSET_INTEL_430FX, @@ -15329,7 +15329,7 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* This has the Phoenix MultiKey KBC firmware on the NSC Suepr I/O chip. */ + /* This has the Phoenix MultiKey KBC firmware on the NSC Super I/O chip. */ { .name = "[i430TX] Packard Bell PB790", .internal_name = "an430tx", @@ -16007,6 +16007,50 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, + /* OEM-only BCM FR510, has the ALi M1543C southbridge with on-chip KBC. */ + { + .name = "[ALi ALADDiN V] BCM FR510 (Packard Bell/NEC OEM)", + .internal_name = "fr510", + .type = MACHINE_TYPE_SOCKETS7, + .chipset = MACHINE_CHIPSET_ALI_ALADDIN_V, + .init = machine_at_fr510_init, + .p1_handler = machine_generic_p1_handler, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SOCKET5_7, + .block = CPU_BLOCK_NONE, + .min_bus = 50000000, + .max_bus = 66666667, + .min_voltage = 2200, + .max_voltage = 3200, + .min_multi = 1.5, + .max_multi = 5.5 + }, + .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Has internal video: ATI 3D Rage IIc AGP (Rage 2) */ + .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_SOUND | MACHINE_USB, + .ram = { + .min = 8192, + .max = 262144, + .step = 8192 + }, + .nvrmask = 255, + .jumpered_ecp_dma = 0, + .default_jumpered_ecp_dma = -1, + .kbc_device = NULL, + .kbc_params = 0x00000000, + .kbc_p1 = 0x00000cf0, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = &fr510_device, + .kbd_device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = &cs4235_onboard_device, + .net_device = NULL + }, /* M1534c kbc */ { .name = "[ALi ALADDiN V] Gateway Lucas", From f692c00c6d6ec4ae5c34c102be0b8c11875a325c Mon Sep 17 00:00:00 2001 From: OBattler Date: Sat, 27 Sep 2025 15:21:13 +0200 Subject: [PATCH 269/274] Remove the BCM FR510 because it turned out to be improperly implemented fixes #6236. --- src/include/86box/machine.h | 4 --- src/machine/m_at_sockets7.c | 69 ------------------------------------- src/machine/machine_table.c | 44 ----------------------- 3 files changed, 117 deletions(-) diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 4fd0e16e8..b88d8f492 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -1069,10 +1069,6 @@ extern int machine_at_m560_init(const machine_t *); /* m_at_sockets7.c */ /* ALi ALADDiN V */ extern int machine_at_p5a_init(const machine_t *); -#ifdef EMU_DEVICE_H -extern const device_t fr510_device; -#endif -extern int machine_at_fr510_init(const machine_t *); extern int machine_at_m579_init(const machine_t *); extern int machine_at_gwlucas_init(const machine_t *); extern int machine_at_5aa_init(const machine_t *); diff --git a/src/machine/m_at_sockets7.c b/src/machine/m_at_sockets7.c index a70bccc03..a39b2cef4 100644 --- a/src/machine/m_at_sockets7.c +++ b/src/machine/m_at_sockets7.c @@ -74,75 +74,6 @@ machine_at_p5a_init(const machine_t *model) return ret; } -static const device_config_t fr510_config[] = { - // clang-format off - { - .name = "bios", - .description = "BIOS Version", - .type = CONFIG_BIOS, - .default_string = "fr510", - .default_int = 0, - .file_filter = "", - .spinner = { 0 }, - .bios = { - { .name = "Award Modular BIOS v4.51PG - Revision 1.19 (01/15/1999)", .internal_name = "fr510_1999", .bios_type = BIOS_NORMAL, - .files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/fr510/FR510119.bin", "" } }, - { .name = "Award Modular BIOS v4.51PG - Revision SCC-128 (11/27/2002)", .internal_name = "fr510", .bios_type = BIOS_NORMAL, - .files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/fr510/510S128.BIN", "" } }, - { .files_no = 0 } - }, - }, - { .name = "", .description = "", .type = CONFIG_END } - // clang-format on -}; - -const device_t fr510_device = { - .name = "BCM FR510 (Packard Bell/NEC OEM)", - .internal_name = "fr510_device", - .flags = 0, - .local = 0, - .init = NULL, - .close = NULL, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = fr510_config -}; - -int -machine_at_fr510_init(const machine_t *model) -{ - int ret = 0; - const char* fn; - - /* No ROMs available */ - if (!device_available(model->device)) - return ret; - - device_context(model->device); - fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0); - ret = bios_load_linear(fn, 0x000c0000, 262144, 0); - device_context_restore(); - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1); - device_add(&ali1541_device); - device_add(&ali1543c_device); /* +0 */ - device_add(&sst_flash_39sf020_device); - spd_register(SPD_TYPE_SDRAM, 0x7, 512); - - if ((sound_card_current[0] == SOUND_INTERNAL) && machine_get_snd_device(machine)) - device_add(machine_get_snd_device(machine)); - - return ret; -} - int machine_at_m579_init(const machine_t *model) { diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 1ae51e5c7..cd68127e1 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -16007,50 +16007,6 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* OEM-only BCM FR510, has the ALi M1543C southbridge with on-chip KBC. */ - { - .name = "[ALi ALADDiN V] BCM FR510 (Packard Bell/NEC OEM)", - .internal_name = "fr510", - .type = MACHINE_TYPE_SOCKETS7, - .chipset = MACHINE_CHIPSET_ALI_ALADDIN_V, - .init = machine_at_fr510_init, - .p1_handler = machine_generic_p1_handler, - .gpio_handler = NULL, - .available_flag = MACHINE_AVAILABLE, - .gpio_acpi_handler = NULL, - .cpu = { - .package = CPU_PKG_SOCKET5_7, - .block = CPU_BLOCK_NONE, - .min_bus = 50000000, - .max_bus = 66666667, - .min_voltage = 2200, - .max_voltage = 3200, - .min_multi = 1.5, - .max_multi = 5.5 - }, - .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Has internal video: ATI 3D Rage IIc AGP (Rage 2) */ - .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_SOUND | MACHINE_USB, - .ram = { - .min = 8192, - .max = 262144, - .step = 8192 - }, - .nvrmask = 255, - .jumpered_ecp_dma = 0, - .default_jumpered_ecp_dma = -1, - .kbc_device = NULL, - .kbc_params = 0x00000000, - .kbc_p1 = 0x00000cf0, - .gpio = 0xffffffff, - .gpio_acpi = 0xffffffff, - .device = &fr510_device, - .kbd_device = NULL, - .fdc_device = NULL, - .sio_device = NULL, - .vid_device = NULL, - .snd_device = &cs4235_onboard_device, - .net_device = NULL - }, /* M1534c kbc */ { .name = "[ALi ALADDiN V] Gateway Lucas", From 1fc4dda73e623686ef0a7bda9b3a1aaf9676602e Mon Sep 17 00:00:00 2001 From: Maxwell Scott Date: Sat, 27 Sep 2025 20:43:45 +0700 Subject: [PATCH 270/274] Add MSI name for Gateway Lucas (#6235) * Fix bus speeds for FR510 + add MSI name for Lucas * Removed table for FR510 --- src/machine/machine_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index cd68127e1..2462ccd7a 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -16009,7 +16009,7 @@ const machine_t machines[] = { }, /* M1534c kbc */ { - .name = "[ALi ALADDiN V] Gateway Lucas", + .name = "[ALi ALADDiN V] Gateway Lucas (MSI MS-5185)", .internal_name = "gwlucas", .type = MACHINE_TYPE_SOCKETS7, .chipset = MACHINE_CHIPSET_ALI_ALADDIN_V, From c22bd0e63ce79beb81dd8e26c2c945f90538e18e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= <13226155+dhrdlicka@users.noreply.github.com> Date: Sat, 27 Sep 2025 15:55:54 +0200 Subject: [PATCH 271/274] Update pull request template [skip ci] Added a checklist item for local testing validation. --- .github/pull_request_template.md | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index e09b5636f..9e5521cf4 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -5,6 +5,7 @@ _Briefly describe what you are submitting._ Checklist ========= * [ ] Closes #xxx +* [ ] I have tested my changes locally and validated that the functionality works as intended * [ ] I have discussed this with core contributors already * [ ] This pull request requires changes to the ROM set * [ ] I have opened a roms pull request - https://github.com/86Box/roms/pull/changeme/ From 58b4af4689f364c9d4c1a9d9106e6398166e5029 Mon Sep 17 00:00:00 2001 From: Maxwell Scott Date: Sat, 27 Sep 2025 21:26:31 +0700 Subject: [PATCH 272/274] Slightly name correction to Vectra VL 5 + added codename (#6237) * Fix bus speeds for FR510 + add MSI name for Lucas * Removed table for FR510 * Name changes to Vectra VL 5 Series 4 Also added codename. --- src/machine/machine_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 2462ccd7a..8c8dc6b91 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -12973,7 +12973,7 @@ const machine_t machines[] = { /* Has a SM(S)C FDC37C932 Super I/O chip with on-chip KBC with AMI MegaKey (revision '5') KBC firmware. */ { - .name = "[i430FX] HP Vectra VL 5 Series 4", + .name = "[i430FX] HP Vectra VL 5/xxx Series 4 (Chimay)", .internal_name = "vectra54", .type = MACHINE_TYPE_SOCKET7_3V, .chipset = MACHINE_CHIPSET_INTEL_430FX, From 74aa15644d177d0b16df075885fb5ef808d55105 Mon Sep 17 00:00:00 2001 From: andresdelcampo <33843515+andresdelcampo@users.noreply.github.com> Date: Sat, 27 Sep 2025 19:53:45 +0200 Subject: [PATCH 273/274] Fix remember size and position regression in which vertical size could grow when reopening the VM (#6239) * Change window resizing logic when using 4:3 aspect ratio Change window resizing logic when using 4:3 aspect ratio to resize content only. Fixed issues in Remember size and position that are derived from the change. There is a slight flicker while resizing with force 4:3 aspect ratio. * Fix regression that adds vertical size when showing toolbar and statusbar and remembering size and po The recent rework on the force aspect 4:3 which needed to revisit the remembering of size and position introduced a regression that would save the size without considering the non-content window elements that could be showed or hidden. Now it calculates it accordingly. --- src/qt/qt_mainwindow.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/qt/qt_mainwindow.cpp b/src/qt/qt_mainwindow.cpp index fbc2d8a47..e88bedd90 100644 --- a/src/qt/qt_mainwindow.cpp +++ b/src/qt/qt_mainwindow.cpp @@ -936,8 +936,11 @@ MainWindow::closeEvent(QCloseEvent *event) const bool wasMax = isMaximized(); QRect normal = wasMax ? this->normalGeometry() : this->geometry(); // Save WINDOW size (not the content widget’s 4:3 box) + const int chromeHeight = geometry().height() - ui->stackedWidget->height(); window_w = normal.width(); - window_h = normal.height(); + window_h = normal.height() - chromeHeight; + if (window_h < 0) + window_h = 0; if (!QApplication::platformName().contains("wayland")) { window_x = normal.x(); window_y = normal.y(); From bc41f8bbb6472809a878d2233e472b8baf8f289a Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Sat, 27 Sep 2025 23:57:12 +0600 Subject: [PATCH 274/274] Fix sign position of DDA accumulator registers (#6241) --- src/video/vid_s3_virge.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c index d9e1d91ef..ac96aedef 100644 --- a/src/video/vid_s3_virge.c +++ b/src/video/vid_s3_virge.c @@ -1952,9 +1952,9 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv) break; case 0x8190: virge->streams.sec_ctrl = val; - virge->streams.dda_horiz_accumulator = val & 0xfff; - if (val & 0x1000) - virge->streams.dda_horiz_accumulator |= ~0xfff; + virge->streams.dda_horiz_accumulator = val & 0x7ff; + if (val & 0x800) + virge->streams.dda_horiz_accumulator |= ~0x7ff; virge->streams.sdif = (val >> 24) & 7; break; @@ -2030,9 +2030,9 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv) virge->streams.k2_vert_scale |= ~0x7ff; break; case 0x81e8: - virge->streams.dda_vert_accumulator = val & 0xfff; - if (val & 0x1000) - virge->streams.dda_vert_accumulator |= ~0xfff; + virge->streams.dda_vert_accumulator = val & 0x7ff; + if (val & 0x800) + virge->streams.dda_vert_accumulator |= ~0x7ff; svga_recalctimings(svga); svga->fullchange = changeframecount;

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