From e5a566014e6133a876a53f5e0864ba0c133b9fd2 Mon Sep 17 00:00:00 2001
From: starfrost013 <mario64crashed@gmail.com>
Date: Fri, 24 Jan 2025 00:33:27 +0000
Subject: [PATCH] implement prom subsystem, which i forgot existed

---
 src/include/86box/nv/vid_nv3.h           |  3 ++-
 src/video/nv/nv3/nv3_core.c              | 33 +++++++++++++++++++++---
 src/video/nv/nv3/nv3_core_arbiter.c      |  3 +--
 src/video/nv/nv3/subsystems/nv3_pfifo.c  |  4 +--
 src/video/nv/nv3/subsystems/nv3_ptimer.c |  1 -
 5 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h
index 37c4683d5..f0286e2db 100644
--- a/src/include/86box/nv/vid_nv3.h
+++ b/src/include/86box/nv/vid_nv3.h
@@ -1248,7 +1248,8 @@ void        nv3_pextdev_write(uint32_t address, uint32_t value);
 #define nv3_pstraps_read nv3_pextdev_read(NV3_PSTRAPS)
 #define nv3_pstraps_write(x) nv3_pextdev_write(NV3_PSTRAPS, x)
 
-uint32_t    nv3_prom_read(uint32_t address);
+// Reads from vbios are 8bit
+uint8_t     nv3_prom_read(uint32_t address);
 void        nv3_prom_write(uint32_t address, uint32_t value);
 uint32_t    nv3_palt_read(uint32_t address);
 void        nv3_palt_write(uint32_t address, uint32_t value);
diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c
index 499c06a92..761ca9cf9 100644
--- a/src/video/nv/nv3/nv3_core.c
+++ b/src/video/nv/nv3/nv3_core.c
@@ -22,7 +22,7 @@
 #include <86Box/86box.h>
 #include <86Box/device.h>
 #include <86Box/mem.h>
-#include <86box/io.h>
+#include <86Box/io.h>
 #include <86box/pci.h>
 #include <86Box/rom.h> // DEPENDENT!!!
 #include <86Box/video.h>
@@ -727,6 +727,35 @@ void nv3_draw_cursor(svga_t* svga, int32_t drawline)
     nv_log("nv3_draw_cursor drawline=0x%04x", drawline);
 }
 
+// MMIO 0x6000->0x7FFF is mapped to a mirror of the VBIOS.
+
+uint8_t nv3_prom_read(uint32_t address)
+{
+    // prom area is 64k, so...
+    // first see if we even have a rom of 64kb in size
+    uint32_t max_rom_size = NV3_PROM_END - NV3_PROM_START;
+    uint32_t real_rom_size = max_rom_size;
+
+    // set it
+    if (nv3->nvbase.vbios.sz < max_rom_size)
+        real_rom_size = nv3->nvbase.vbios.sz;
+
+    //get our real address
+    uint8_t rom_address = address & max_rom_size;
+
+    // Does this mirror on real hardware?
+    if (rom_address >= real_rom_size)
+        return 0xFF;
+    else
+        return nv3->nvbase.vbios.rom[rom_address];
+}
+
+void nv3_prom_write(uint32_t address, uint32_t value)
+{
+    uint32_t real_addr = address & 0x1FFFF;
+    nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=)");
+}
+
 // Initialise the MMIO mappings
 void nv3_init_mappings_mmio()
 {
@@ -906,8 +935,6 @@ void nv3_update_mappings()
     }
 }
 
-
-
 // 
 // Init code
 //
diff --git a/src/video/nv/nv3/nv3_core_arbiter.c b/src/video/nv/nv3/nv3_core_arbiter.c
index bab378b9f..88ab74fe5 100644
--- a/src/video/nv/nv3/nv3_core_arbiter.c
+++ b/src/video/nv/nv3/nv3_core_arbiter.c
@@ -189,8 +189,7 @@ uint32_t    nv3_prm_read(uint32_t address) { return 0; };
 void        nv3_prm_write(uint32_t address, uint32_t value) {};
 uint32_t    nv3_prmio_read(uint32_t address) { return 0; };
 void        nv3_prmio_write(uint32_t address, uint32_t value) {};
-uint32_t    nv3_prom_read(uint32_t address) { return 0; };
-void        nv3_prom_write(uint32_t address, uint32_t value) {};
+
 uint32_t    nv3_palt_read(uint32_t address) { return 0; };
 void        nv3_palt_write(uint32_t address, uint32_t value) {};
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c
index 3de7661e3..db657b63e 100644
--- a/src/video/nv/nv3/subsystems/nv3_pfifo.c
+++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c
@@ -125,10 +125,10 @@ uint32_t nv3_pfifo_read(uint32_t address)
                     break;
                 // Control
                 case NV3_PFIFO_CACHE0_PULLER_CONTROL:
-                    ret = nv3->pfifo.cache0_settings.control & 0xFF; // 8bits meaningful
+                    ret = nv3->pfifo.cache0_settings.control; // 8bits meaningful
                     break;
                 case NV3_PFIFO_CACHE1_PULLER_CONTROL:
-                    ret = nv3->pfifo.cache1_settings.control & 0xFF; // only 8bits are meaningful
+                    ret = nv3->pfifo.cache1_settings.control; // only 8bits are meaningful
                     break;
             }
         }
diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c
index ab19c1e61..938389054 100644
--- a/src/video/nv/nv3/subsystems/nv3_ptimer.c
+++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c
@@ -105,7 +105,6 @@ uint32_t nv3_ptimer_read(uint32_t address)
     {
         nv_log("NV3: PTIMER Read from 0x%08x", address);
     }
-    
 
     uint32_t ret = 0x00;