1. Actually place the correct clocks in the PVGA-based ICS90c64a (see sources).
2. Make sure the difference between 4bpp and 8bpp in the BT484/5 ramdac is actually seen and done.
3. Forgot the ATI panning flag for the plain Mach64GX cards.
4. Fix standard VGA graphics mode for Japanese text in the Mach32 so that it's rendered correctly (if bit 5 of ati 0xb0 and bit 0 of 0x4aee clock select are 0).
5. Normalize ET4000AX clocks.
6. ET4000W32 series: fix some hwcursor issues in win3.1/winos2 (in non-24bpp modes) as well as well as the chips' clocks. Cleanup of the modes too.
7. Video7 HT208 cards: Add the 7.04 HP OEM bios and implement the clocks according to its manual (HT208, below).
8. More fixes of the stalls caused by FIFO stuff in non-FIFO modes (S3 stuff).
9. Remove unused code in vid_svga.c (vga core layer)
1. Some fixes to the S3 refresh rates using the bt48x ramdac as well as 32bpp acceleration (actually pixtrans reads) fixes, which are actually one single dword rather than two words. (This fixes some graphical bugs in 32bpp mode using OS/2 Warp with the Elsa 928 drivers).
2. Add undocumented ports 0x82ec and 0x82ed, needed by the Elsa OS/2 928/805i cards to operate correctly and not getting stuck at a blank screen.
3. Workaround a read select register issue when reading back the accelerated height (0xbee8 index 0x0f bits 3-0 returning a non-height index, in this case, 0x0e) so that the height is not zeroed on writes after the first reads, allowing text and fonts to be displayed on OS/2 Warp 3's built-in S3 864 drivers in every bpp.
4. Don't run the mach8/32 specific clock if we're in plain VGA text mode.
5. Some cleanups to the et4000w32 chip series, including a clock (refresh rate) fix for OS/2's built-in drivers and the extended crtc parameters to be run only on graphics modes.
1. Add a variant of the ICS1494 clock generator specifically for the Radius HT209 card.
2. Add the ICD2047 clock generator to the HT216-32 card.
3. Add the previously missing 7.00 BIOS revision of the VGA 1024i HT208 card.
1. The S3 968-based Diamond Stealth 64 Video VRAM, using a 14mhz reference clock, now has its RGB528 fixed Pixel PLL reference divider set to its default value (0x07) per manual and reference clock. Fixes wrong refresh rates on said cards and others.
2. Added the ICS2494-324 clock generator to the ET4000AX. Fixes wrong refresh rates on this one too.
1. In the STG code, separated the STG1703 without its built-in clock as 1702 while keeping the one with the clock as 1703.
2. Added the ICS2494AN-324 clock generator used by the et4000w32 series.
3. Return 0x98 as the ID of the ATT498 ramdac.
4. Corrected the pixel clocks of the IBM RGB528 while keeping its current compatibility and exactness of the refresh rates of its clocks.
5. Added a variable reference clock of the SDAC/GenDAC for future use.
6. The clocks of the TVP3026 have been implemented for a while. Some corrections have been made (plus color key r/w).
7. Mach64 enhanced mode doesn't use scrollcache (bits 0-3 of attrregs 0x13), fixes some pixels being off (mainly in win3.1x)
8. Reorganized the cirrus 54xx built-in clock for proper refresh rates.
9. Proper reorganization of the et4000w32 series of chipsets and their cards supporting them, from cursor to clocks to ramdacs plus a 24bpp acceleration fix for the w32p series (about pixels being processed in bitblt).
10. Removed the PCI videomagic card as its bios doesn't have the PCIR header while making sure the plain ISA/VLB w32 and ISA only w32i (now named Axis Microdevice) support 2mb of vram properly.
11. Added the Hercules Dynamite VL Pro based on the w32i chip (and VLB).
12. Initialize the et4000w32 cards with misc bit 0 set as well as crtc31 bit 6 for rs2 connection to the ramdac.
13. Refactored the S3 Pre-ViRGE code to have proper refresh rates and clocks and added the 805I as a member of the chips (ID 0xa8).
14. Replaced the S3 805I Elsa Winner 1000 ISA bios with a more supported one for our code using the SDAC.
15. Added proper 24bpp acceleration to the Visionx68 chips.
16. Fixed wrong colors in the 911/924 15/16bpp acceleration when used for the first time.
17. Match the ViRGE mapping to the pre-ViRGE one per manual/datasheet.
18. Correct as best as possible the TGUI9400 clocks.
