mirror of
https://github.com/86Box/86Box.git
synced 2026-02-24 10:28:19 -07:00
185 lines
4.4 KiB
C
185 lines
4.4 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of Intel ICH2 GPIO
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*
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*
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*
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* Authors: Tiseno100,
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*
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* Copyright 2022 Tiseno100.
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/intel_ich2_gpio.h>
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#ifdef ENABLE_INTEL_ICH2_GPIO_LOG
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int intel_ich2_gpio_do_log = ENABLE_INTEL_ICH2_GPIO_LOG;
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static void
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intel_ich2_gpio_log(const char *fmt, ...)
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{
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va_list ap;
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if (intel_ich2_gpio_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define intel_ich2_gpio_log(fmt, ...)
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#endif
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static void
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intel_ich2_gpio_write(uint16_t addr, uint8_t val, void *priv)
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{
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intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) priv;
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addr -= dev->gpio_addr;
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intel_ich2_gpio_log("Intel ICH2 GPIO: Write 0x%02x on GPIO Register 0x%02x\n", val, addr);
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switch (addr) {
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/* GPIO Use Enable */
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case 0x00:
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dev->gpio_regs[addr] = val & 0x3f;
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break;
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case 0x01:
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dev->gpio_regs[addr] = val & 8;
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break;
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case 0x02:
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dev->gpio_regs[addr] = val & 0x20;
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break;
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/* GPIO I/O Select */
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case 0x07:
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dev->gpio_regs[addr] = val & 0x1b;
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break;
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/* GPIO Level */
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case 0x0e:
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dev->gpio_regs[addr] = val;
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break;
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case 0x0f:
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dev->gpio_regs[addr] = val & 0x1b;
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dev->gpio_regs[addr] &= dev->gpio_regs[0x1b]; // Mask out whatever change if the bits aren't programmed as outputs.
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break;
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/* GPIO Blink which is not Utilized */
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case 0x1a:
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dev->gpio_regs[addr] = val & 6;
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break;
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case 0x1b:
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dev->gpio_regs[addr] = val & 0x1a;
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break;
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/* GPIO Signal Inverter */
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case 0x2d:
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dev->gpio_regs[addr] = val & 0x39;
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break;
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}
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}
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static uint8_t
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intel_ich2_gpio_read(uint16_t addr, void *priv)
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{
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intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) priv;
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addr -= dev->gpio_addr;
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intel_ich2_gpio_log("Intel ICH2 GPIO: Reading 0x%02x from Register 0x%02x\n", dev->gpio_regs[addr], addr);
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if (addr <= 0x2f)
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return dev->gpio_regs[addr];
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else
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return 0xff;
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}
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void
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intel_ich2_gpio_base(int enable, uint16_t addr, intel_ich2_gpio_t *dev)
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{
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if (dev->gpio_addr != 0)
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io_removehandler(dev->gpio_addr, 15, intel_ich2_gpio_read, NULL, NULL, intel_ich2_gpio_write, NULL, NULL, dev);
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dev->gpio_addr = addr;
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if ((addr != 0) && enable)
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io_sethandler(addr, 15, intel_ich2_gpio_read, NULL, NULL, intel_ich2_gpio_write, NULL, NULL, dev);
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}
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static void
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intel_ich2_gpio_reset(void *priv)
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{
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intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) priv;
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dev->gpio_addr = 0;
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/* Enabled GPIO's */
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dev->gpio_regs[0x00] = 0x80;
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dev->gpio_regs[0x01] = 0x31;
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dev->gpio_regs[0x03] = 0x1a;
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/* GPIO Drives (Input or Output) */
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dev->gpio_regs[0x04] = 0xff;
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dev->gpio_regs[0x05] = 0xff;
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dev->gpio_regs[0x0e] = 0x3f;
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dev->gpio_regs[0x0f] = 0x1b;
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dev->gpio_regs[0x16] = 0x63;
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dev->gpio_regs[0x17] = 0x06;
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}
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static void
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intel_ich2_gpio_close(void *priv)
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{
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intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) priv;
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free(dev);
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}
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static void *
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intel_ich2_gpio_init(const device_t *info)
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{
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intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) malloc(sizeof(intel_ich2_gpio_t));
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memset(dev, 0, sizeof(intel_ich2_gpio_t));
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intel_ich2_gpio_reset(dev);
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return dev;
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}
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const device_t intel_ich2_gpio_device = {
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.name = "Intel ICH2 GPIO",
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.internal_name = "intel_ich2_gpio",
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.flags = 0,
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.local = 0,
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.init = intel_ich2_gpio_init,
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.close = intel_ich2_gpio_close,
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.reset = intel_ich2_gpio_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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