mirror of
https://github.com/86Box/86Box.git
synced 2026-02-24 10:28:19 -07:00
a505894a10
- 86Box's own headers go to /86box - munt's public interface goes to /mt32emu - all slirp headers go to /slirp (might want to consider using only its public inteface) - single file headers from other projects go in include root
345 lines
8.8 KiB
C
345 lines
8.8 KiB
C
/*
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86Box A hypervisor and IBM PC system emulator that specializes in
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running old operating systems and software designed for IBM
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PC systems and compatibles from 1981 through fairly recent
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system designs based on the PCI bus.
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<This file is part of the 86Box distribution.>
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VIA Apollo Pro North Bridge emulation
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VT82C691 used in the PC Partner APAS3 board
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based on the model of VIA MVP3 by mooch & Sarah
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Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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Copyright(C) 2020 Tiseno100
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Copyright(C) 2020 Melissa Goad
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Copyright(C) 2020 Miran Grca
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Note: Due to 99.9% similarities with the VP3, MVP3 but also other later Apollo chipsets. We probably should create a common Apollo tree
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just like the Intel 4x0 series.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/chipset.h>
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typedef struct via_apro_t
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{
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uint8_t pci_conf[2][256];
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} via_apro_t;
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static void
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apro_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void
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via_apro_pci_regs(via_apro_t *dev)
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{
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memset(dev, 0, sizeof(via_apro_t));
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// Host Bridge registers
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dev->pci_conf[0][0x00] = 0x06; // VIA
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dev->pci_conf[0][0x01] = 0x11;
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dev->pci_conf[0][0x02] = 0x91; // VT82C691
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dev->pci_conf[0][0x03] = 0x06;
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dev->pci_conf[0][0x04] = 6; // Command
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dev->pci_conf[0][0x05] = 0;
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// These(06h-0fh) probably aren't needed but as they're referenced by the MVP3 chipset code i added them too
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dev->pci_conf[0][0x06] = 0; // Status
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dev->pci_conf[0][0x07] = 0;
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dev->pci_conf[0][0x09] = 0; // Program Interface
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dev->pci_conf[0][0x0a] = 0; // Sub Class Code
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dev->pci_conf[0][0x0b] = 0; // Base Class Code
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dev->pci_conf[0][0x0c] = 0; // reserved
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dev->pci_conf[0][0x0d] = 0; // Latency Timer
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dev->pci_conf[0][0x0e] = 0; // Header Type
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dev->pci_conf[0][0x0f] = 0; // Built-in Self test
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dev->pci_conf[0][0x10] = 0x08; // Graphics Aperature Base
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dev->pci_conf[0][0x34] = 0xa0; // Capability Pointer
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dev->pci_conf[0][0x56] = 1; // Bank 6 Ending
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dev->pci_conf[0][0x57] = 1; // Bank 7 Ending
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dev->pci_conf[0][0x5a] = 1; // Bank 0 Ending
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dev->pci_conf[0][0x5b] = 1; // Bank 1 Ending
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dev->pci_conf[0][0x5c] = 1; // Bank 2 Ending
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dev->pci_conf[0][0x5d] = 1; // Bank 3 Ending
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dev->pci_conf[0][0x5e] = 1; // Bank 4 Ending
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dev->pci_conf[0][0x5f] = 1; // Bank 5 Ending
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dev->pci_conf[0][0x64] = 0xec; // DRAM Timing for Banks 0,1
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dev->pci_conf[0][0x65] = 0xec; // DRAM Timing for Banks 2,3
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dev->pci_conf[0][0x66] = 0xec; // DRAM Timing for Banks 4,5
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dev->pci_conf[0][0x67] = 0x01; // DRAM Timing for Banks 6,7
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dev->pci_conf[0][0x6b] = 1; // DRAM Abritration control
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dev->pci_conf[0][0xa4] = 0x03; // AGP Status
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dev->pci_conf[0][0xa5] = 0x02;
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dev->pci_conf[0][0xa6] = 0;
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dev->pci_conf[0][0xa7] = 0x07;
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// PCI-to-PCI
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dev->pci_conf[1][0x00] = 0x06; // VIA
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dev->pci_conf[1][0x01] = 0x11;
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dev->pci_conf[1][0x02] = 0x91; // VT82C691
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dev->pci_conf[1][0x03] = 0x06;
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dev->pci_conf[1][0x04] = 7; // Command
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dev->pci_conf[1][0x05] = 0;
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dev->pci_conf[1][0x06] = 0x20; // Status
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dev->pci_conf[1][0x07] = 0x02;
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dev->pci_conf[1][0x09] = 0; // Program Interface
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dev->pci_conf[1][0x0A] = 4; // Sub Class Code
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dev->pci_conf[1][0x0B] = 6; // Base Class Code
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dev->pci_conf[1][0x0C] = 0; // reserved
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dev->pci_conf[1][0x0D] = 0; // Latency Timer
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dev->pci_conf[1][0x0E] = 1; // Header Type
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dev->pci_conf[1][0x0F] = 0; // Built-in Self test
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dev->pci_conf[1][0x1c] = 0xf0; // I/O Base
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dev->pci_conf[1][0x20] = 0xf0; // Memory Base
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dev->pci_conf[1][0x21] = 0xff;
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dev->pci_conf[1][0x24] = 0xf0;
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dev->pci_conf[1][0x25] = 0xff;
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}
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static void
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host_bridge_write(int func, int addr, uint8_t val, void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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// Read-Only registers. Exact same as MVP3
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if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x12)) ||
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((addr >= 0x14) && (addr < 0x50)) || ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) ||
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((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd)))
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return;
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switch(addr){
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case 0x04: // Command
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dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40);
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case 0x07: // Status
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dev->pci_conf[0][0x07] &= ~(val & 0xb0);
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break;
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case 0x12: //Graphics Aperature Base
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dev->pci_conf[0][0x12] = (val & 0xf0);
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break;
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case 0x13:
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dev->pci_conf[0][0x13] = val;
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break;
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case 0x61: // Shadow RAM control 1
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if ((dev->pci_conf[0][0x61] ^ val) & 0x03)
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apro_map(0xc0000, 0x04000, val & 0x03);
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if ((dev->pci_conf[0][0x61] ^ val) & 0x0c)
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apro_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->pci_conf[0][0x61] ^ val) & 0x30)
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apro_map(0xc8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->pci_conf[0][0x61] ^ val) & 0xc0)
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apro_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x61] = val;
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return;
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case 0x62: // Shadow RAM Control 2
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if ((dev->pci_conf[0][0x62] ^ val) & 0x03)
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apro_map(0xd0000, 0x04000, val & 0x03);
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if ((dev->pci_conf[0][0x62] ^ val) & 0x0c)
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apro_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->pci_conf[0][0x62] ^ val) & 0x30)
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apro_map(0xd8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->pci_conf[0][0x62] ^ val) & 0xc0)
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apro_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x62] = val;
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return;
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case 0x63: // Shadow RAM Control 3
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if ((dev->pci_conf[0][0x63] ^ val) & 0x30) {
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apro_map(0xf0000, 0x10000, (val & 0x30) >> 4);
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shadowbios = (((val & 0x30) >> 4) & 0x02);
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}
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if ((dev->pci_conf[0][0x63] ^ val) & 0xc0)
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apro_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x63] = val;
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return;
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//In case we throw somewhere
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default:
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dev->pci_conf[0][addr] = val;
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break;
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}
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}
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static void
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pci_to_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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if (func != 1)
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return;
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//As with MVP3. Same deal
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if ((addr < 4) || ((addr >= 5) && (addr < 7)) ||
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((addr >= 8) && (addr < 0x18)) || (addr == 0x1b) ||
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((addr >= 0x1e) && (addr < 0x20)) || ((addr >= 0x28) && (addr < 0x3e)) ||
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(addr >= 0x43))
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return;
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switch(addr) {
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case 0x04:
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dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47);
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break;
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case 0x07:
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dev->pci_conf[1][0x07] &= ~(val & 0x30);
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break;
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case 0x20: // Memory Base
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dev->pci_conf[1][0x20] = val & 0xf0;
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break;
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case 0x22: // Memory Limit
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dev->pci_conf[1][0x22] = val & 0xf0;
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break;
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case 0x24: // Prefetchable Memory base
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dev->pci_conf[1][0x24] = val & 0xf0;
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break;
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case 0x26: // Prefetchable Memory limit
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dev->pci_conf[1][0x26] = val & 0xf0;
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break;
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default:
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dev->pci_conf[1][addr] = val;
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break;
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}
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}
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static uint8_t
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via_apro_read(int func, int addr, void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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uint8_t ret = 0xff;
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switch(func) {
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case 0:
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ret = dev->pci_conf[0][addr];
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break;
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case 1:
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ret = dev->pci_conf[1][addr];
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break;
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}
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return ret;
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}
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static void
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via_apro_write(int func, int addr, uint8_t val, void *priv)
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{
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switch(func) {
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case 0:
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host_bridge_write(func, addr, val, priv);
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break;
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case 1:
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pci_to_pci_bridge_write(func, addr, val, priv);
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break;
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}
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}
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static void
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via_apro_reset(void *priv)
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{
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via_apro_write(0, 0x63, via_apro_read(0, 0x63, priv) & 0xcf, priv);
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}
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static void *
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via_apro_init(const device_t *info)
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{
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via_apro_t *dev = (via_apro_t *) malloc(sizeof(via_apro_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, via_apro_read, via_apro_write, dev);
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via_apro_pci_regs(dev);
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return dev;
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}
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static void
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via_apro_close(void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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free(dev);
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}
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const device_t via_apro_device = {
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"VIA Apollo Pro",
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DEVICE_PCI,
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0,
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via_apro_init,
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via_apro_close,
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via_apro_reset,
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NULL,
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NULL,
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NULL,
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NULL
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}; |