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ca9eb9acb9
Only FE /0 (INC r/m8) and FE /1 (DEC r/m8) are valid instructions in INC/DEC Grp 4. All other ModR/M opcode bits are reserved and should throw #UD.
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
#define INC_DEC_OP(name, reg, inc, setflags) \
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static int op##name(UNUSED(uint32_t fetchdat)) \
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{ \
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setflags(reg, 1); \
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reg += inc; \
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CLOCK_CYCLES(timing_rr); \
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PREFETCH_RUN(timing_rr, 1, -1, 0, 0, 0, 0, 0); \
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return 0; \
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}
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INC_DEC_OP(INC_AX, AX, 1, setadd16nc)
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INC_DEC_OP(INC_BX, BX, 1, setadd16nc)
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INC_DEC_OP(INC_CX, CX, 1, setadd16nc)
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INC_DEC_OP(INC_DX, DX, 1, setadd16nc)
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INC_DEC_OP(INC_SI, SI, 1, setadd16nc)
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INC_DEC_OP(INC_DI, DI, 1, setadd16nc)
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INC_DEC_OP(INC_BP, BP, 1, setadd16nc)
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INC_DEC_OP(INC_SP, SP, 1, setadd16nc)
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INC_DEC_OP(INC_EAX, EAX, 1, setadd32nc)
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INC_DEC_OP(INC_EBX, EBX, 1, setadd32nc)
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INC_DEC_OP(INC_ECX, ECX, 1, setadd32nc)
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INC_DEC_OP(INC_EDX, EDX, 1, setadd32nc)
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INC_DEC_OP(INC_ESI, ESI, 1, setadd32nc)
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INC_DEC_OP(INC_EDI, EDI, 1, setadd32nc)
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INC_DEC_OP(INC_EBP, EBP, 1, setadd32nc)
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INC_DEC_OP(INC_ESP, ESP, 1, setadd32nc)
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INC_DEC_OP(DEC_AX, AX, -1, setsub16nc)
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INC_DEC_OP(DEC_BX, BX, -1, setsub16nc)
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INC_DEC_OP(DEC_CX, CX, -1, setsub16nc)
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INC_DEC_OP(DEC_DX, DX, -1, setsub16nc)
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INC_DEC_OP(DEC_SI, SI, -1, setsub16nc)
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INC_DEC_OP(DEC_DI, DI, -1, setsub16nc)
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INC_DEC_OP(DEC_BP, BP, -1, setsub16nc)
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INC_DEC_OP(DEC_SP, SP, -1, setsub16nc)
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INC_DEC_OP(DEC_EAX, EAX, -1, setsub32nc)
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INC_DEC_OP(DEC_EBX, EBX, -1, setsub32nc)
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INC_DEC_OP(DEC_ECX, ECX, -1, setsub32nc)
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INC_DEC_OP(DEC_EDX, EDX, -1, setsub32nc)
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INC_DEC_OP(DEC_ESI, ESI, -1, setsub32nc)
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INC_DEC_OP(DEC_EDI, EDI, -1, setsub32nc)
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INC_DEC_OP(DEC_EBP, EBP, -1, setsub32nc)
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INC_DEC_OP(DEC_ESP, ESP, -1, setsub32nc)
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static int
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opINCDEC_b_a16(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_16(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteab();
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if (cpu_state.abrt)
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return 1;
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switch (rmdat & 0x38) {
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case 0: /* INC r/m8 */
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seteab(temp + 1);
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if (cpu_state.abrt)
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return 1;
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setadd8nc(temp, 1);
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break;
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case 0x8: /* DEC r/m8 */
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seteab(temp - 1);
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if (cpu_state.abrt)
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return 1;
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setsub8nc(temp, 1);
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break;
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default:
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
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PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
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return 0;
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}
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static int
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opINCDEC_b_a32(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_32(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteab();
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if (cpu_state.abrt)
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return 1;
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switch (rmdat & 0x38) {
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case 0: /* INC r/m8 */
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seteab(temp + 1);
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if (cpu_state.abrt)
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return 1;
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setadd8nc(temp, 1);
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break;
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case 0x8: /* DEC r/m8 */
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seteab(temp - 1);
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if (cpu_state.abrt)
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return 1;
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setsub8nc(temp, 1);
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break;
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default:
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
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PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
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return 0;
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}
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