mirror of
https://github.com/86Box/86Box.git
synced 2026-02-23 18:08:20 -07:00
327 lines
8.2 KiB
C
327 lines
8.2 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* Emulation of the SiS 50x PCI chips.
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*
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* Version: @(#)sis50x.c 1.0.1 2017/08/23
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*
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* Author: Miran Grca, <mgrca8@gmail.com>
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* Copyright 2017 Miran Grca.
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*/
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#include <stdlib.h>
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#include "ibm.h"
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#include "device.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "sis50x.h"
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typedef struct sis501_t
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{
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uint8_t pci_conf[256];
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uint8_t turbo_reg;
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} sis501_t;
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sis501_t sis501;
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typedef struct sis503_t
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{
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uint8_t pci_conf[256];
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} sis503_t;
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sis503_t sis503;
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typedef struct sis50x_t
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{
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uint8_t isa_conf[12];
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uint8_t reg;
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} sis50x_isa_t;
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sis50x_isa_t sis50x_isa;
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static void sis501_recalcmapping(void)
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{
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int c, d;
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for (c = 0; c < 1; c++)
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{
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for (d = 0; d < 4; d++)
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{
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uint32_t base = 0xe0000 + (d << 14);
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if (sis501.pci_conf[0x54 + c] & (1 << (d + 4)))
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{
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switch (sis501.pci_conf[0x53] & 0x60)
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{
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case 0x00:
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mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 0x20:
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mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 0x40:
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mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 0x60:
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mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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}
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}
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else
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mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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}
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flushmmucache();
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shadowbios = 1;
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}
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static void sis501_write(int func, int addr, uint8_t val, void *p)
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{
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/* pclog("sis501_write : addr=%02x val=%02x\n", addr, val); */
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if (func)
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return;
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if ((addr >= 0x10) && (addr < 0x4f))
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return;
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0c: case 0x0e:
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return;
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case 0x04: /*Command register*/
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val &= 0x42;
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val |= 0x04;
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break;
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case 0x05:
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val &= 0x01;
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break;
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case 0x06: /*Status*/
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val = 0;
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break;
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case 0x07:
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val = 0x02;
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break;
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case 0x54: /*Shadow configure*/
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if ((sis501.pci_conf[0x54] & val) ^ 0xf0)
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{
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sis501.pci_conf[0x54] = val;
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sis501_recalcmapping();
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}
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break;
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}
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sis501.pci_conf[addr] = val;
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}
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static void sis503_write(int func, int addr, uint8_t val, void *p)
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{
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/* pclog("sis503_write : addr=%02x val=%02x\n", addr, val); */
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if (func > 0)
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return;
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if (addr >= 0x0f && addr < 0x41)
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return;
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switch(addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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case 0x04: /*Command register*/
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val &= 0x08;
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val |= 0x07;
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break;
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case 0x05:
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val = 0;
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break;
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case 0x06: /*Status*/
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val = 0;
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break;
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case 0x07:
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val = 0x02;
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break;
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case 0x41:
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pclog("Set IRQ routing: INT A -> %02X\n", val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTA, val & 0xf);
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break;
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case 0x42:
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pclog("Set IRQ routing: INT B -> %02X\n", val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTC, val & 0xf);
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break;
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case 0x43:
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pclog("Set IRQ routing: INT C -> %02X\n", val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTB, val & 0xf);
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break;
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case 0x44:
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pclog("Set IRQ routing: INT D -> %02X\n", val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTD, val & 0xf);
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break;
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}
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sis503.pci_conf[addr] = val;
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}
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static void sis50x_isa_write(uint16_t port, uint8_t val, void *priv)
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{
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if (port & 1)
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{
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if (sis50x_isa.reg <= 0xB) sis50x_isa.isa_conf[sis50x_isa.reg] = val;
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}
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else
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{
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sis50x_isa.reg = val;
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}
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}
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static uint8_t sis501_read(int func, int addr, void *p)
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{
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if (func)
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return 0xff;
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return sis501.pci_conf[addr];
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}
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static uint8_t sis503_read(int func, int addr, void *p)
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{
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if (func > 0)
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return 0xff;
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return sis503.pci_conf[addr];
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}
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static uint8_t sis50x_isa_read(uint16_t port, void *priv)
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{
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if (port & 1)
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{
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if (sis50x_isa.reg <= 0xB)
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return sis50x_isa.isa_conf[sis50x_isa.reg];
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else
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return 0xff;
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}
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else
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{
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return sis50x_isa.reg;
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}
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}
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static void sis501_reset(void)
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{
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memset(&sis501, 0, sizeof(sis501_t));
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sis501.pci_conf[0x00] = 0x39; /*SiS*/
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sis501.pci_conf[0x01] = 0x10;
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sis501.pci_conf[0x02] = 0x06; /*501/502*/
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sis501.pci_conf[0x03] = 0x04;
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sis501.pci_conf[0x04] = 7;
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sis501.pci_conf[0x05] = 0;
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sis501.pci_conf[0x06] = 0x80;
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sis501.pci_conf[0x07] = 0x02;
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sis501.pci_conf[0x08] = 0; /*Device revision*/
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sis501.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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sis501.pci_conf[0x0a] = 0x00;
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sis501.pci_conf[0x0b] = 0x06;
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sis501.pci_conf[0x0e] = 0x00; /*Single function device*/
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sis501.pci_conf[0x50] = 0xbc;
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sis501.pci_conf[0x51] = 0xfb;
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sis501.pci_conf[0x52] = 0xad;
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sis501.pci_conf[0x53] = 0xfe;
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shadowbios = 1;
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}
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void sis501_init(void)
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{
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pci_add_card(0, sis501_read, sis501_write, NULL);
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sis501_reset();
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pci_reset_handler.pci_master_reset = NULL;
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}
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void sis503_reset(void)
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{
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memset(&sis503, 0, sizeof(sis503_t));
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sis503.pci_conf[0x00] = 0x39; /*SiS*/
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sis503.pci_conf[0x01] = 0x10;
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sis503.pci_conf[0x02] = 0x08; /*503*/
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sis503.pci_conf[0x03] = 0x00;
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sis503.pci_conf[0x04] = 7;
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sis503.pci_conf[0x05] = 0;
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sis503.pci_conf[0x06] = 0x80;
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sis503.pci_conf[0x07] = 0x02;
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sis503.pci_conf[0x08] = 0; /*Device revision*/
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sis503.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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sis503.pci_conf[0x0a] = 0x01;
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sis503.pci_conf[0x0b] = 0x06;
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sis503.pci_conf[0x0e] = 0x00; /*Single function device*/
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sis503.pci_conf[0x41] = sis503.pci_conf[0x42] = sis503.pci_conf[0x43] = sis503.pci_conf[0x44] = 0x80;
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}
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void sis503_init(int card)
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{
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pci_add_card(card, sis503_read, sis503_write, NULL);
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sis503_reset();
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trc_init();
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port_92_reset();
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port_92_add();
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pci_reset_handler.pci_set_reset = sis503_reset;
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}
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void sis50x_isa_init(void)
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{
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memset(&sis50x_isa, 0, sizeof(sis50x_isa_t));
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io_sethandler(0x22, 0x0002, sis50x_isa_read, NULL, NULL, sis50x_isa_write, NULL, NULL, NULL);
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}
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