[lightning-ln882h] Add support for Lightning LN882H family (#312)
* fix mbedtls bad pointer in function call (prototype mismatch) * fix issue with weak families functions implemented in static library, it will never be linked. fixed by redefining prototypes inside families * [ln882x] add support for lightning ln882x & ln882h families * add i2c (wire) support * add analog (adc) support * add watchdog support * [ln882x] changed default uart 0/1 pins; added board wl2s * [ln882x] fix IRQ & ADC pins * [ln882x] boards cosmetic * [ln882x] wifi sta use otp mac addr by default; re-enabled wifi powersave mode * [ln882x] clang-format clean code * [ln882x] clang-format clean code * Update families.json * Apply suggestions from code review * [ln882x] reformat json board files * [ln882x] os_queue cleanup * [ln882x] removed Beken auto-download command * [ln882x] removed personal script file * [ln882x] removed unusefull pi section in debugging.md * [ln882x] removed Arduino.h and changed private I2C definition * [ln882x] updated README.md * [ln882x] changed pin naming scheme to PA/PB * [ln882x] clean code * [ln882x] clean code * [ln882x] add ota image verification * Update push-dev.yml * [ln882x] fix boards ADC missing inputs] * [ln882x] removed reg_xxx fixup files and use include guards instead * [ln882x] cleanup code * [ln882x] cleanup code * [ln882x] fix lt_init weak functions linking * [ln882x] revert lt_api.h modification, fixed with previous commit * [ln882x] setup UF2 firmware for flasher with partitions * [ln882x] update README.md * [ln882x] include ln_wifi.h and ln_serial.h to avoid including bad headers on case insensitive systems * [ln882x] Replace RingBuffer by SerialRingBuffer * [ln882x] clang-format * [ln882x] update README.md * Apply suggestions from code review * Reformat board JSON files * Add mkdocs link redirect * Update ltchiptool to v4.12.0 --------- Co-authored-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
This commit is contained in:
lamauny
GitHub
52
cores/lightning-ln882h/base/PinNames.h
Normal file
52
cores/lightning-ln882h/base/PinNames.h
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@@ -0,0 +1,52 @@
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#ifndef _PINNAMES_H_
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#define _PINNAMES_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <hal/hal_gpio.h>
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typedef enum {
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PORT_A = 0,
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PORT_B = 1,
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} ln_PinPort;
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typedef enum {
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PA_0 = 0,
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PA_1,
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PA_2,
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PA_3,
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PA_4,
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PA_5,
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PA_6,
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PA_7,
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PA_8,
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PA_9,
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PA_10,
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PA_11,
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PA_12,
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PA_13,
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PA_14,
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PA_15,
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PB_0,
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PB_1,
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PB_2,
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PB_3,
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PB_4,
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PB_5,
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PB_6,
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PB_7,
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PB_8,
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PB_9,
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// Not connected
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NC = -1
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} ln_PinName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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8
cores/lightning-ln882h/base/api/lt_cpu.c
Normal file
8
cores/lightning-ln882h/base/api/lt_cpu.c
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@@ -0,0 +1,8 @@
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/* Copyright (c) Etienne Le Cousin 2024-02-24. */
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#include <libretiny.h>
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#include <sdk_private.h>
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const char *lt_cpu_get_core_type() {
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return "ARM Cortex-M4F (ARMv7E-M)";
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}
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27
cores/lightning-ln882h/base/api/lt_device.c
Normal file
27
cores/lightning-ln882h/base/api/lt_device.c
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@@ -0,0 +1,27 @@
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/* Copyright (c) Etienne Le Cousin 2024-03-03. */
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#include <libretiny.h>
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#include <sdk_private.h>
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void lt_get_device_mac(uint8_t *mac) {
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ln_fotp_get_mac_val(mac);
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}
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void lt_reboot() {
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ln_chip_reboot();
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while (1) {}
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}
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lt_reboot_reason_t lt_get_reboot_reason() {
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chip_reboot_cause_t reason = ln_chip_get_reboot_cause();
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switch (reason) {
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case CHIP_REBOOT_POWER_ON:
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return REBOOT_REASON_POWER;
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case CHIP_REBOOT_SOFTWARE:
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return REBOOT_REASON_SOFTWARE;
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case CHIP_REBOOT_WATCHDOG:
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return REBOOT_REASON_WATCHDOG;
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default:
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return REBOOT_REASON_UNKNOWN;
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}
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}
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15
cores/lightning-ln882h/base/api/lt_flash.c
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15
cores/lightning-ln882h/base/api/lt_flash.c
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@@ -0,0 +1,15 @@
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/* Copyright (c) Etienne Le Cousin 2024-03-03. */
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#include <libretiny.h>
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#include <sdk_private.h>
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uint32_t hal_flash_read_id(void);
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lt_flash_id_t lt_flash_get_id() {
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lt_flash_id_t id;
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uint32_t fl_id = hal_flash_read_id();
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id.manufacturer_id = (uint8_t)(fl_id >> 16);
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id.chip_id = (uint8_t)(fl_id >> 8);
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id.chip_size_id = (uint8_t)(fl_id >> 0);
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return id;
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}
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58
cores/lightning-ln882h/base/api/lt_init.c
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58
cores/lightning-ln882h/base/api/lt_init.c
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@@ -0,0 +1,58 @@
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/* Copyright (c) Etienne Le Cousin 2024-02-24. */
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#include <libretiny.h>
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#include <sdk_private.h>
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extern uint8_t uart_print_port;
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extern Serial_t m_LogSerial;
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static void lt_init_log(void) {
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// default LT print port
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uart_print_port = LT_UART_DEFAULT_LOGGER;
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// default SDK print port
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serial_init(&m_LogSerial, LT_UART_DEFAULT_PORT, CFG_UART_BAUDRATE_LOG, NULL);
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}
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void lt_init_family() {
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// 0. check reboot cause
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ln_chip_get_reboot_cause();
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// 1. sys clock,interrupt
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SetSysClock();
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set_interrupt_priority();
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switch_global_interrupt(HAL_ENABLE);
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ln_runtime_measure_init();
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// 2. register os heap mem
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OS_DefineHeapRegions();
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// 3. log init
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lt_init_log();
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cm_backtrace_init("LibreTiny - LN882H", "HW_V1.0", "SW_V1.0");
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if (NVDS_ERR_OK != ln_nvds_init(FLASH_NVDS_OFFSET)) {
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LT_E("NVDS init failed!");
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}
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if (KV_ERR_NONE != ln_kv_port_init(FLASH_KV_OFFSET, (FLASH_KV_OFFSET + FLASH_KV_LENGTH))) {
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LT_E("KV init failed!");
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}
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// init system parameter
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sysparam_integrity_check_all();
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ln_pm_sleep_mode_set(ACTIVE);
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// ln_pm_always_clk_disable_select(CLK_G_I2S | CLK_G_WS2811 | CLK_G_SDIO);
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/*ln_pm_always_clk_disable_select(CLK_G_I2S | CLK_G_WS2811 | CLK_G_SDIO | CLK_G_AES);
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ln_pm_lightsleep_clk_disable_select(CLK_G_GPIOA | CLK_G_GPIOB | CLK_G_SPI0 | CLK_G_SPI1 | CLK_G_I2C0 |
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CLK_G_UART1 | CLK_G_UART2 | CLK_G_WDT | CLK_G_TIM1 | CLK_G_TIM2 | CLK_G_MAC |
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CLK_G_DMA | CLK_G_RF | CLK_G_ADV_TIMER| CLK_G_TRNG);*/
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}
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void lt_init_arduino() {
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#if LT_AUTO_DOWNLOAD_REBOOT && LT_ARD_HAS_SERIAL && LT_HW_UART0
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// initialize auto-download-reboot parser
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Serial0.begin(115200);
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#endif
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}
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8
cores/lightning-ln882h/base/api/lt_mem.c
Normal file
8
cores/lightning-ln882h/base/api/lt_mem.c
Normal file
@@ -0,0 +1,8 @@
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/* Copyright (c) Etienne Le Cousin 2024-02-24. */
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#include <libretiny.h>
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#include <sdk_private.h>
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uint32_t lt_ram_get_size() {
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return 296 * 1024;
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}
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45
cores/lightning-ln882h/base/api/lt_ota.c
Normal file
45
cores/lightning-ln882h/base/api/lt_ota.c
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@@ -0,0 +1,45 @@
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/* Copyright (c) Etienne Le Cousin 2024-12-21. */
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#include <libretiny.h>
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#include <ota_image.h>
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#include <sdk_private.h>
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lt_ota_type_t lt_ota_get_type() {
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return OTA_TYPE_SINGLE;
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}
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bool lt_ota_is_valid(uint8_t index) {
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image_hdr_t ota_header;
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if (OTA_ERR_NONE != image_header_fast_read(FLASH_OTA_OFFSET, &ota_header)) {
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return false;
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}
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if (OTA_ERR_NONE != image_header_verify(&ota_header)) {
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return false;
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}
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if (OTA_ERR_NONE != image_body_verify(FLASH_OTA_OFFSET, &ota_header)) {
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return false;
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}
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return true;
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}
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uint8_t lt_ota_dual_get_current() {
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return 0;
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}
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uint8_t lt_ota_dual_get_stored() {
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return 0;
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}
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void lt_ota_set_write_protect(uf2_ota_t *uf2) {
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LT_DM(OTA, "lt_ota_set_write_protect");
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ln_nvds_set_ota_upg_state(UPG_STATE_DOWNLOAD_ING);
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}
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bool lt_ota_switch(bool revert) {
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LT_DM(OTA, "lt_ota_switch(%d)", revert);
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ln_nvds_set_ota_upg_state(UPG_STATE_DOWNLOAD_OK);
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return true;
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}
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43
cores/lightning-ln882h/base/api/lt_wdt.c
Normal file
43
cores/lightning-ln882h/base/api/lt_wdt.c
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@@ -0,0 +1,43 @@
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/* Copyright (c) Etienne Le Cousin 2025-01-19. */
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#include <libretiny.h>
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#include <sdk_private.h>
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bool lt_wdt_enable(uint32_t timeout) {
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wdt_top_value_t wdt_top_value = 0;
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for (uint8_t i = 0; i < 15; i++) {
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if ((0x100UL << i) < (timeout * 32768 / 1000))
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wdt_top_value = i;
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}
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wdt_init_t_def wdt_init;
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memset(&wdt_init, 0, sizeof(wdt_init));
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wdt_init.wdt_rmod = WDT_RMOD_1;
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wdt_init.wdt_rpl = WDT_RPL_32_PCLK;
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wdt_init.top = wdt_top_value;
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hal_wdt_init(WDT_BASE, &wdt_init);
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/* Configure Interrupt */
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NVIC_SetPriority(WDT_IRQn, 4);
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NVIC_EnableIRQ(WDT_IRQn);
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/* Watchdog enable */
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/* Note : Watchdog cannot be disabled */
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hal_wdt_en(WDT_BASE, HAL_ENABLE);
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/* Start feeding */
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hal_wdt_cnt_restart(WDT_BASE);
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return true;
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}
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void lt_wdt_disable() {
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hal_wdt_deinit();
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hal_wdt_en(WDT_BASE, HAL_DISABLE);
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}
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void lt_wdt_feed() {
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hal_wdt_cnt_restart(WDT_BASE);
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}
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31
cores/lightning-ln882h/base/config/lwipopts.h
Normal file
31
cores/lightning-ln882h/base/config/lwipopts.h
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@@ -0,0 +1,31 @@
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/* Copyright (c) Etienne Le Cousin 2024-03-10. */
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#pragma once
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#include_next "lwipopts.h"
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#if (!defined(LWIP_IPV4) || LWIP_IPV4) && !LWIP_IPV6
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#define ip_addr ip4_addr // LwIP 2.0.x compatibility
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#define ip_addr_t ip4_addr_t // LwIP 2.0.x compatibility
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#endif
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#if !LWIP_IPV4 && LWIP_IPV6
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#define ip_addr ip6_addr // LwIP 2.0.x compatibility
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#define ip_addr_t ip6_addr_t // LwIP 2.0.x compatibility
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#endif
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#define in_addr_t u32_t
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#define IN_ADDR_T_DEFINED 1
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#ifndef INT_MAX
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#define INT_MAX 2147483647 // for RECV_BUFSIZE_DEFAULT
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#endif
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#define LWIP_NUM_NETIF_CLIENT_DATA 1
|
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#define LWIP_NETIF_EXT_STATUS_CALLBACK 1
|
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#undef MEMP_NUM_UDP_PCB
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#define MEMP_NUM_UDP_PCB 7
|
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|
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// LWIP_COMPAT_MUTEX cannot prevent priority inversion. It is recommended to implement priority-aware mutexes. (Define
|
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// LWIP_COMPAT_MUTEX_ALLOWED to disable this error.)
|
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#define LWIP_COMPAT_MUTEX_ALLOWED 1
|
||||
|
||||
#define LWIP_TCPIP_TIMEOUT 1
|
||||
82
cores/lightning-ln882h/base/config/proj_config.h
Normal file
82
cores/lightning-ln882h/base/config/proj_config.h
Normal file
@@ -0,0 +1,82 @@
|
||||
#ifndef _PROJ_CONFIG_H_
|
||||
#define _PROJ_CONFIG_H_
|
||||
|
||||
#define DISABLE (0)
|
||||
#define ENABLE (1)
|
||||
|
||||
#define __CONFIG_OS_KERNEL RTOS_FREERTOS
|
||||
|
||||
/*
|
||||
* Clock settings section
|
||||
* Note:
|
||||
*
|
||||
*/
|
||||
#define XTAL_CLOCK (40000000)
|
||||
#define RCO_CLOCK (32000)
|
||||
#define PLL_CLOCK (160000000)
|
||||
|
||||
// TODO: SystemCoreClock
|
||||
#define SYSTEM_CLOCK (160000000)
|
||||
|
||||
/*
|
||||
* Module enable/disable control
|
||||
*/
|
||||
#define FLASH_XIP ENABLE
|
||||
#define LN_ASSERT_EN ENABLE
|
||||
#define HAL_ASSERT_EN ENABLE
|
||||
#define PRINTF_OMIT DISABLE // when release software, set 1 to omit all printf logs
|
||||
#define OS_TICK_COMPENSATE
|
||||
|
||||
// Check big and endian mode
|
||||
#if defined(__CC_ARM)
|
||||
#if defined(__BIG_ENDIAN)
|
||||
#error "Please set the compiler to little-endian mode"
|
||||
#endif
|
||||
#elif defined(__GNUC__)
|
||||
#if (__BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__)
|
||||
#error "Please set the compiler to little-endian mode"
|
||||
#endif // __BYTE_ORDER__
|
||||
#else
|
||||
#error "Unsupported compiler"
|
||||
#endif
|
||||
|
||||
#ifndef LITTLE_ENDIAN
|
||||
#define LITTLE_ENDIAN 1234
|
||||
#endif
|
||||
|
||||
/*
|
||||
* flash image settings
|
||||
*/
|
||||
#define FLASH_IMAGE_VER_MAJOR 0
|
||||
#define FLASH_IMAGE_VER_MINOR 1
|
||||
#define SOC_CRP_FLAG 0
|
||||
|
||||
/*
|
||||
* Hardware config
|
||||
*/
|
||||
#define CFG_UART0_TX_BUF_SIZE 256
|
||||
#define CFG_UART0_RX_BUF_SIZE 256
|
||||
#define CFG_UART1_TX_BUF_SIZE 128
|
||||
#define CFG_UART1_RX_BUF_SIZE 256
|
||||
#define CFG_UART2_TX_BUF_SIZE 128
|
||||
#define CFG_UART2_RX_BUF_SIZE 256
|
||||
|
||||
#define CFG_UART_BAUDRATE_LOG 115200
|
||||
#define CFG_UART_BAUDRATE_CONSOLE 115200
|
||||
|
||||
/*
|
||||
* FreeRTOS config
|
||||
*/
|
||||
|
||||
#define configTOTAL_HEAP_SIZE ((size_t)(160 * 1024))
|
||||
|
||||
/*
|
||||
* log
|
||||
*/
|
||||
#ifndef __cplusplus
|
||||
#define hexdump ln_hexdump
|
||||
#endif // __cplusplus
|
||||
|
||||
#define mbedtls_platform_set_calloc_free(calloc, free)
|
||||
|
||||
#endif /* _PROJ_CONFIG_H_ */
|
||||
2
cores/lightning-ln882h/base/fixups/.clang-format
Normal file
2
cores/lightning-ln882h/base/fixups/.clang-format
Normal file
@@ -0,0 +1,2 @@
|
||||
DisableFormat: true
|
||||
SortIncludes: Never
|
||||
4
cores/lightning-ln882h/base/fixups/os_queue.h
Normal file
4
cores/lightning-ln882h/base/fixups/os_queue.h
Normal file
@@ -0,0 +1,4 @@
|
||||
#pragma once
|
||||
|
||||
#include "queue.h"
|
||||
|
||||
518
cores/lightning-ln882h/base/fixups/serial_hw.c
Normal file
518
cores/lightning-ln882h/base/fixups/serial_hw.c
Normal file
@@ -0,0 +1,518 @@
|
||||
#include "proj_config.h"
|
||||
#include "hal/hal_uart.h"
|
||||
#include "serial/ln_serial.h"
|
||||
#include "serial_hw.h"
|
||||
#include "utils/debug/ln_assert.h"
|
||||
#include "hal/hal_gpio.h"
|
||||
#include "hal/hal_misc.h"
|
||||
|
||||
#include "reg_sysc_cmp.h"//gpio fullmux
|
||||
|
||||
#define UART0_TX_BUF_SIZE CFG_UART0_TX_BUF_SIZE
|
||||
#define UART0_RX_BUF_SIZE CFG_UART0_RX_BUF_SIZE
|
||||
#define UART1_TX_BUF_SIZE CFG_UART1_TX_BUF_SIZE
|
||||
#define UART1_RX_BUF_SIZE CFG_UART1_RX_BUF_SIZE
|
||||
#define UART2_TX_BUF_SIZE CFG_UART2_TX_BUF_SIZE
|
||||
#define UART2_RX_BUF_SIZE CFG_UART2_RX_BUF_SIZE
|
||||
|
||||
/* TX and RX fifo buffer */
|
||||
uint8_t uart0_txbuf[UART0_TX_BUF_SIZE];
|
||||
uint8_t uart0_rxbuf[UART0_RX_BUF_SIZE];
|
||||
uint8_t uart1_txbuf[UART1_TX_BUF_SIZE];
|
||||
uint8_t uart1_rxbuf[UART1_RX_BUF_SIZE];
|
||||
uint8_t uart2_txbuf[UART2_TX_BUF_SIZE];
|
||||
uint8_t uart2_rxbuf[UART2_RX_BUF_SIZE];
|
||||
|
||||
/* From the high-level serial driver */
|
||||
extern Serial_t serial_handles[SER_PORT_NUM];
|
||||
|
||||
/* UART device*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t uart_base;
|
||||
uart_init_t_def init_cfg;
|
||||
} uart_dev_t;
|
||||
|
||||
static uart_dev_t g_uart0;
|
||||
static uart_dev_t g_uart1;
|
||||
static uart_dev_t g_uart2;
|
||||
|
||||
/* serial */
|
||||
typedef struct
|
||||
{
|
||||
struct SerialHardware Hardware;
|
||||
struct Serial *serial;
|
||||
} ln_serial_t;
|
||||
ln_serial_t uart_serial[SER_PORT_NUM];
|
||||
|
||||
|
||||
static void uart_io_pin_request(struct Serial *serial)
|
||||
{
|
||||
if (serial->port_id == SER_PORT_UART0)
|
||||
{
|
||||
hal_gpio_pin_afio_select(GPIOA_BASE,GPIO_PIN_2,UART0_TX);
|
||||
hal_gpio_pin_afio_select(GPIOA_BASE,GPIO_PIN_3,UART0_RX);
|
||||
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_2,HAL_ENABLE);
|
||||
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_3,HAL_ENABLE);
|
||||
}
|
||||
else if (serial->port_id == SER_PORT_UART1)
|
||||
{
|
||||
hal_gpio_pin_afio_select(GPIOB_BASE,GPIO_PIN_8,UART1_RX);
|
||||
hal_gpio_pin_afio_select(GPIOB_BASE,GPIO_PIN_9,UART1_TX);
|
||||
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_8,HAL_ENABLE);
|
||||
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_9,HAL_ENABLE);
|
||||
}
|
||||
else if (serial->port_id == SER_PORT_UART2)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
static void uart_io_pin_release(struct Serial *serial)
|
||||
{
|
||||
if (serial == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (serial->port_id == SER_PORT_UART0)
|
||||
{
|
||||
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_2,HAL_DISABLE);
|
||||
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_3,HAL_DISABLE);
|
||||
}
|
||||
else if (serial->port_id == SER_PORT_UART1)
|
||||
{
|
||||
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_8,HAL_DISABLE);
|
||||
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_9,HAL_DISABLE);
|
||||
}
|
||||
else if (serial->port_id == SER_PORT_UART2)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
static void hw_uart0_init(struct SerialHardware *_hw, struct Serial *serial, uint32_t baudrate)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
|
||||
LN_ASSERT(_hw && serial);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
hw->serial = serial;
|
||||
|
||||
g_uart0.uart_base = UART0_BASE;
|
||||
g_uart0.init_cfg.baudrate = baudrate;//115200 921600 2000000
|
||||
g_uart0.init_cfg.word_len = UART_WORD_LEN_8;
|
||||
g_uart0.init_cfg.parity = UART_PARITY_NONE;
|
||||
g_uart0.init_cfg.stop_bits = UART_STOP_BITS_1;
|
||||
g_uart0.init_cfg.over_sampl= UART_OVER_SAMPL_8;
|
||||
|
||||
hal_uart_init(g_uart0.uart_base, &g_uart0.init_cfg);
|
||||
|
||||
hal_uart_rx_mode_en(g_uart0.uart_base, HAL_ENABLE);
|
||||
hal_uart_tx_mode_en(g_uart0.uart_base, HAL_ENABLE);
|
||||
hal_uart_en(g_uart0.uart_base, HAL_ENABLE);
|
||||
|
||||
hal_uart_it_en(g_uart0.uart_base, USART_IT_RXNE);
|
||||
//uart_it_enable(g_uart0.uart_base, USART_IT_TXE);//uart_it_enable(g_uart0.uart_base, USART_IT_TXE);
|
||||
|
||||
NVIC_EnableIRQ(UART0_IRQn);
|
||||
|
||||
//request pin for uart
|
||||
uart_io_pin_request(hw->serial);
|
||||
}
|
||||
|
||||
static void hw_uart1_init(struct SerialHardware *_hw, struct Serial *serial, uint32_t baudrate)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
|
||||
LN_ASSERT(_hw && serial);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
hw->serial = serial;
|
||||
|
||||
g_uart1.uart_base = UART1_BASE;
|
||||
g_uart1.init_cfg.baudrate = baudrate;//115200 921600 2000000
|
||||
g_uart1.init_cfg.word_len = UART_WORD_LEN_8;
|
||||
g_uart1.init_cfg.parity = UART_PARITY_NONE;
|
||||
g_uart1.init_cfg.stop_bits = UART_STOP_BITS_1;
|
||||
g_uart1.init_cfg.over_sampl= UART_OVER_SAMPL_8;
|
||||
|
||||
hal_uart_init(g_uart1.uart_base, &g_uart1.init_cfg);
|
||||
|
||||
hal_uart_rx_mode_en(g_uart1.uart_base, HAL_ENABLE);
|
||||
hal_uart_tx_mode_en(g_uart1.uart_base, HAL_ENABLE);
|
||||
hal_uart_en(g_uart1.uart_base, HAL_ENABLE);
|
||||
|
||||
hal_uart_it_en(g_uart1.uart_base, USART_IT_RXNE);
|
||||
//uart_it_enable(g_uart1.uart_base, USART_IT_TXE);
|
||||
NVIC_EnableIRQ(UART1_IRQn);
|
||||
|
||||
//request pin for uart
|
||||
uart_io_pin_request(hw->serial);
|
||||
}
|
||||
|
||||
static void hw_uart2_init(struct SerialHardware *_hw, struct Serial *serial, uint32_t baudrate)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
|
||||
LN_ASSERT(_hw && serial);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
hw->serial = serial;
|
||||
|
||||
g_uart2.uart_base = UART2_BASE;
|
||||
g_uart2.init_cfg.baudrate = baudrate;//115200 921600 2000000
|
||||
g_uart2.init_cfg.word_len = UART_WORD_LEN_8;
|
||||
g_uart2.init_cfg.parity = UART_PARITY_NONE;
|
||||
g_uart2.init_cfg.stop_bits = UART_STOP_BITS_1;
|
||||
g_uart2.init_cfg.over_sampl= UART_OVER_SAMPL_8;
|
||||
|
||||
hal_uart_init(g_uart2.uart_base, &g_uart2.init_cfg);
|
||||
|
||||
hal_uart_rx_mode_en(g_uart2.uart_base, HAL_ENABLE);
|
||||
hal_uart_tx_mode_en(g_uart2.uart_base, HAL_ENABLE);
|
||||
hal_uart_en(g_uart2.uart_base, HAL_ENABLE);
|
||||
|
||||
hal_uart_it_en(g_uart2.uart_base, USART_IT_RXNE);
|
||||
//uart_it_enable(g_uart2.uart_base, USART_IT_TXE);
|
||||
NVIC_EnableIRQ(UART2_IRQn);
|
||||
|
||||
//request pin for uart
|
||||
uart_io_pin_request(hw->serial);
|
||||
}
|
||||
|
||||
static void hw_uart0_cleanup(struct SerialHardware *_hw)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
LN_ASSERT(_hw);
|
||||
|
||||
hal_misc_reset_uart0();
|
||||
NVIC_ClearPendingIRQ(UART0_IRQn);
|
||||
NVIC_DisableIRQ(UART0_IRQn);
|
||||
|
||||
hw = (ln_serial_t *)_hw;
|
||||
uart_io_pin_release(hw->serial);
|
||||
hw->serial = NULL; // must be reset to NULL
|
||||
}
|
||||
|
||||
static void hw_uart1_cleanup(struct SerialHardware *_hw)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
LN_ASSERT(_hw);
|
||||
|
||||
hal_misc_reset_uart1();
|
||||
NVIC_ClearPendingIRQ(UART1_IRQn);
|
||||
NVIC_DisableIRQ(UART1_IRQn);
|
||||
|
||||
hw = (ln_serial_t *)_hw;
|
||||
uart_io_pin_release(hw->serial);
|
||||
hw->serial = NULL; // must be reset to NULL
|
||||
}
|
||||
|
||||
static void hw_uart2_cleanup(struct SerialHardware *_hw)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
LN_ASSERT(_hw);
|
||||
|
||||
hal_misc_reset_uart2();
|
||||
NVIC_ClearPendingIRQ(UART2_IRQn);
|
||||
NVIC_DisableIRQ(UART2_IRQn);
|
||||
|
||||
hw = (ln_serial_t *)_hw;
|
||||
uart_io_pin_release(hw->serial);
|
||||
hw->serial = NULL; // must be reset to NULL
|
||||
}
|
||||
|
||||
static void hw_uart_tx_start_polling(struct SerialHardware * _hw)
|
||||
{
|
||||
uint8_t ch;
|
||||
ln_serial_t *hw = NULL;
|
||||
uart_dev_t * pdev;
|
||||
|
||||
LN_ASSERT(_hw);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
while(!fifo_isempty(&hw->serial->txfifo))
|
||||
{
|
||||
ch = fifo_pop(&hw->serial->txfifo);
|
||||
pdev = (uart_dev_t *)hw->Hardware.hw_device;
|
||||
while (hal_uart_flag_get(pdev->uart_base, USART_FLAG_TXE) != HAL_SET) {};
|
||||
//while (uart_flag_get(pdev->uart_base, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
|
||||
hal_uart_send_data(pdev->uart_base, ch);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void hw_uart_tx_start_isr(struct SerialHardware * _hw)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
LN_ASSERT(_hw);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
|
||||
if (hw->Hardware.isSending){
|
||||
return;
|
||||
}
|
||||
|
||||
if(!fifo_isempty(&hw->serial->txfifo))
|
||||
{
|
||||
hw->Hardware.isSending = LN_TRUE;
|
||||
/* Enable TX empty interrupts. */
|
||||
uart_it_enable(UART0_BASE, USART_IT_TXE);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static int8_t hw_uart_tx_is_sending(struct SerialHardware * _hw)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
|
||||
LN_ASSERT(_hw);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
return hw->Hardware.isSending;
|
||||
}
|
||||
|
||||
static int8_t hw_uart_set_baudrate(struct SerialHardware * _hw, uint32_t baudrate)
|
||||
{
|
||||
ln_serial_t *hw = NULL;
|
||||
uart_dev_t * pdev;
|
||||
|
||||
LN_ASSERT(_hw);
|
||||
hw = (ln_serial_t *)_hw;
|
||||
|
||||
pdev = (uart_dev_t *)hw->Hardware.hw_device;
|
||||
|
||||
hal_uart_baudrate_set(pdev->uart_base, baudrate);
|
||||
return LN_TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* High-level interface data structures.
|
||||
*/
|
||||
static const struct SerialHardwareVT uart0_vtable =
|
||||
{
|
||||
.init = hw_uart0_init,
|
||||
.cleanup = hw_uart0_cleanup,
|
||||
.txStart = hw_uart_tx_start_polling,//hw_uart_tx_start_polling,//hw_uart_tx_start_isr
|
||||
.txSending = hw_uart_tx_is_sending,
|
||||
.setBaudrate = hw_uart_set_baudrate,
|
||||
};
|
||||
|
||||
static const struct SerialHardwareVT uart1_vtable =
|
||||
{
|
||||
.init = hw_uart1_init,
|
||||
.cleanup = hw_uart1_cleanup,
|
||||
.txStart = hw_uart_tx_start_polling,//hw_uart_tx_start_isr
|
||||
.txSending = hw_uart_tx_is_sending,
|
||||
.setBaudrate = hw_uart_set_baudrate,
|
||||
};
|
||||
|
||||
static const struct SerialHardwareVT uart2_vtable =
|
||||
{
|
||||
.init = hw_uart2_init,
|
||||
.cleanup = hw_uart2_cleanup,
|
||||
.txStart = hw_uart_tx_start_polling,//hw_uart_tx_start_isr
|
||||
.txSending = hw_uart_tx_is_sending,
|
||||
.setBaudrate = hw_uart_set_baudrate,
|
||||
};
|
||||
|
||||
ln_serial_t uart_serial[SER_PORT_NUM] =
|
||||
{
|
||||
{
|
||||
.Hardware =
|
||||
{
|
||||
.table = &uart0_vtable,
|
||||
.txbuffer = uart0_txbuf,
|
||||
.rxbuffer = uart0_rxbuf,
|
||||
.txbuffer_size = sizeof(uart0_txbuf),
|
||||
.rxbuffer_size = sizeof(uart0_rxbuf),
|
||||
.hw_device = (void *)&g_uart0,
|
||||
.isSending = LN_FALSE,
|
||||
},
|
||||
.serial = NULL,
|
||||
},
|
||||
{
|
||||
.Hardware =
|
||||
{
|
||||
.table = &uart1_vtable,
|
||||
.txbuffer = uart1_txbuf,
|
||||
.rxbuffer = uart1_rxbuf,
|
||||
.txbuffer_size = sizeof(uart1_txbuf),
|
||||
.rxbuffer_size = sizeof(uart1_rxbuf),
|
||||
.hw_device = (void *)&g_uart1,
|
||||
.isSending = LN_FALSE,
|
||||
},
|
||||
.serial = NULL,
|
||||
},
|
||||
{
|
||||
.Hardware =
|
||||
{
|
||||
.table = &uart2_vtable,
|
||||
.txbuffer = uart2_txbuf,
|
||||
.rxbuffer = uart2_rxbuf,
|
||||
.txbuffer_size = sizeof(uart2_txbuf),
|
||||
.rxbuffer_size = sizeof(uart2_rxbuf),
|
||||
.hw_device = (void *)&g_uart2,
|
||||
.isSending = LN_FALSE,
|
||||
},
|
||||
.serial = NULL,
|
||||
},
|
||||
};
|
||||
|
||||
struct SerialHardware *serial_hw_getdesc(serial_port_id_t port_id)
|
||||
{
|
||||
LN_ASSERT(port_id < SER_PORT_NUM);
|
||||
return (struct SerialHardware *)&uart_serial[port_id].Hardware;
|
||||
}
|
||||
|
||||
///=====================UART0/1/2 IQR Handle===============================///
|
||||
static inline void uart0_send_data_isr(void)
|
||||
{
|
||||
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART0];
|
||||
uint8_t tx_char = 0;
|
||||
|
||||
if (fifo_isempty(&hw->serial->txfifo))
|
||||
{
|
||||
hal_uart_it_disable(UART0_BASE, USART_IT_TXE);
|
||||
hw->Hardware.isSending = LN_FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
tx_char = fifo_pop(&hw->serial->txfifo);
|
||||
hal_uart_send_data(UART0_BASE, tx_char);
|
||||
while (hal_uart_flag_get(UART0_BASE, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uart0_recv_data_isr(void)
|
||||
{
|
||||
uint8_t ch = 0;
|
||||
|
||||
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART0];
|
||||
|
||||
while (fifo_isfull(&hw->serial->rxfifo)){
|
||||
serial_purge_rx(hw->serial);
|
||||
}
|
||||
|
||||
ch = hal_uart_recv_data(UART0_BASE);
|
||||
|
||||
fifo_push(&hw->serial->rxfifo, ch);
|
||||
hw->serial->rx_callback();
|
||||
}
|
||||
|
||||
static inline void serial_uart0_isr_callback(void)
|
||||
{
|
||||
if (hal_uart_it_en_status_get(UART0_BASE, USART_IT_RXNE) && \
|
||||
hal_uart_flag_get(UART0_BASE, USART_FLAG_RXNE)) {
|
||||
uart0_recv_data_isr();
|
||||
}
|
||||
|
||||
if (hal_uart_it_en_status_get(UART0_BASE, USART_IT_TXE) && \
|
||||
hal_uart_flag_get(UART0_BASE, USART_FLAG_TXE)) {
|
||||
uart0_send_data_isr();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uart1_send_data_isr(void)
|
||||
{
|
||||
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART1];
|
||||
uint8_t tx_char = 0;
|
||||
|
||||
if (fifo_isempty(&hw->serial->txfifo))
|
||||
{
|
||||
hal_uart_it_disable(UART1_BASE, USART_IT_TXE);
|
||||
hw->Hardware.isSending = LN_FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
tx_char = fifo_pop(&hw->serial->txfifo);
|
||||
hal_uart_send_data(UART1_BASE, tx_char);
|
||||
while (hal_uart_flag_get(UART1_BASE, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uart1_recv_data_isr(void)
|
||||
{
|
||||
uint8_t ch = 0;
|
||||
|
||||
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART1];
|
||||
|
||||
while (fifo_isfull(&hw->serial->rxfifo)){
|
||||
serial_purge_rx(hw->serial);
|
||||
}
|
||||
|
||||
ch = hal_uart_recv_data(UART1_BASE);
|
||||
|
||||
fifo_push(&hw->serial->rxfifo, ch);
|
||||
hw->serial->rx_callback();
|
||||
}
|
||||
|
||||
static inline void serial_uart1_isr_callback(void)
|
||||
{
|
||||
if (hal_uart_it_en_status_get(UART1_BASE, USART_IT_RXNE) && \
|
||||
hal_uart_flag_get(UART1_BASE, USART_FLAG_RXNE)) {
|
||||
uart1_recv_data_isr();
|
||||
}
|
||||
|
||||
if (hal_uart_it_en_status_get(UART1_BASE, USART_IT_TXE) && \
|
||||
hal_uart_flag_get(UART1_BASE, USART_FLAG_TXE)) {
|
||||
uart1_send_data_isr();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uart2_send_data_isr(void)
|
||||
{
|
||||
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART2];
|
||||
uint8_t tx_char = 0;
|
||||
|
||||
if (fifo_isempty(&hw->serial->txfifo))
|
||||
{
|
||||
hal_uart_it_disable(UART2_BASE, USART_IT_TXE);
|
||||
hw->Hardware.isSending = LN_FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
tx_char = fifo_pop(&hw->serial->txfifo);
|
||||
hal_uart_send_data(UART2_BASE, tx_char);
|
||||
while (hal_uart_flag_get(UART2_BASE, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
|
||||
}
|
||||
}
|
||||
|
||||
static inline void uart2_recv_data_isr(void)
|
||||
{
|
||||
uint8_t ch = 0;
|
||||
|
||||
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART2];
|
||||
|
||||
while (fifo_isfull(&hw->serial->rxfifo)){
|
||||
serial_purge_rx(hw->serial);
|
||||
}
|
||||
|
||||
ch = hal_uart_recv_data(UART2_BASE);
|
||||
|
||||
fifo_push(&hw->serial->rxfifo, ch);
|
||||
hw->serial->rx_callback();
|
||||
}
|
||||
|
||||
static inline void serial_uart2_isr_callback(void)
|
||||
{
|
||||
if (hal_uart_it_en_status_get(UART2_BASE, USART_IT_RXNE) && \
|
||||
hal_uart_flag_get(UART2_BASE, USART_FLAG_RXNE)) {
|
||||
uart2_recv_data_isr();
|
||||
}
|
||||
|
||||
if (hal_uart_it_en_status_get(UART2_BASE, USART_IT_TXE) && \
|
||||
hal_uart_flag_get(UART2_BASE, USART_FLAG_TXE)) {
|
||||
uart2_send_data_isr();
|
||||
}
|
||||
}
|
||||
|
||||
void UART0_IRQHandler(void)
|
||||
{
|
||||
serial_uart0_isr_callback();
|
||||
}
|
||||
|
||||
void UART1_IRQHandler(void)
|
||||
{
|
||||
serial_uart1_isr_callback();
|
||||
}
|
||||
|
||||
void UART2_IRQHandler(void)
|
||||
{
|
||||
serial_uart2_isr_callback();
|
||||
}
|
||||
|
||||
42
cores/lightning-ln882h/base/fixups/serial_hw.h
Normal file
42
cores/lightning-ln882h/base/fixups/serial_hw.h
Normal file
@@ -0,0 +1,42 @@
|
||||
#ifndef __SERIAL_HW_H__
|
||||
#define __SERIAL_HW_H__
|
||||
|
||||
#include "hal/hal_uart.h"
|
||||
#include "ln_types.h"
|
||||
|
||||
struct SerialHardware;
|
||||
struct Serial;
|
||||
|
||||
typedef enum {
|
||||
SER_PORT_UART0 = 0,
|
||||
SER_PORT_UART1 = 1,
|
||||
SER_PORT_UART2 = 2,
|
||||
SER_PORT_NUM = 3, /**< Number of serial ports */
|
||||
SER_PORT_ID_INVALID = SER_PORT_NUM
|
||||
}serial_port_id_t;
|
||||
|
||||
struct SerialHardwareVT
|
||||
{
|
||||
void (*init )(struct SerialHardware *ctx, struct Serial *ser, uint32_t baudrate);
|
||||
void (*cleanup )(struct SerialHardware *ctx);
|
||||
void (*txStart )(struct SerialHardware *ctx);
|
||||
int8_t (*txSending )(struct SerialHardware *ctx);
|
||||
int8_t (*setBaudrate)(struct SerialHardware *ctx, uint32_t baudrate);
|
||||
};
|
||||
|
||||
struct SerialHardware
|
||||
{
|
||||
const struct SerialHardwareVT *table;
|
||||
unsigned char *txbuffer;
|
||||
unsigned char *rxbuffer;
|
||||
size_t txbuffer_size;
|
||||
size_t rxbuffer_size;
|
||||
void *hw_device;
|
||||
volatile int8_t isSending;
|
||||
};
|
||||
|
||||
struct SerialHardware *serial_hw_getdesc(serial_port_id_t port_id);
|
||||
|
||||
|
||||
|
||||
#endif /* __SERIAL_HW_H__ */
|
||||
262
cores/lightning-ln882h/base/fixups/startup_ln882h_gcc.c
Normal file
262
cores/lightning-ln882h/base/fixups/startup_ln882h_gcc.c
Normal file
@@ -0,0 +1,262 @@
|
||||
|
||||
#include "ln882h.h"
|
||||
#include "ln_compiler.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Linker generated Symbols
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __copysection_ram0_load;
|
||||
extern uint32_t __copysection_ram0_start;
|
||||
extern uint32_t __copysection_ram0_end;
|
||||
extern uint32_t __etext;
|
||||
extern uint32_t __bss_ram0_start__;
|
||||
extern uint32_t __bss_ram0_end__;
|
||||
extern uint32_t __StackTop;
|
||||
extern uint32_t __retention_start__;
|
||||
extern uint32_t __retention_end__;
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler Function Prototype
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
//extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
|
||||
extern void lt_main (void);
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler (void) ;
|
||||
__WEAK__ void NMI_Handler (void);
|
||||
__WEAK__ void HardFault_Handler (void);
|
||||
__WEAK__ void MemManage_Handler (void);
|
||||
__WEAK__ void BusFault_Handler (void);
|
||||
__WEAK__ void UsageFault_Handler (void);
|
||||
__WEAK__ void SVC_Handler (void);
|
||||
__WEAK__ void DebugMon_Handler (void);
|
||||
__WEAK__ void PendSV_Handler (void);
|
||||
__WEAK__ void SysTick_Handler (void);
|
||||
__WEAK__ void WDT_IRQHandler (void);
|
||||
__WEAK__ void EXT_IRQHandler (void);
|
||||
__WEAK__ void RTC_IRQHandler (void);
|
||||
__WEAK__ void RFSLP_IRQHandler (void);
|
||||
__WEAK__ void MAC_IRQHandler (void);
|
||||
__WEAK__ void BLE_WAKE_IRQHandler (void);
|
||||
__WEAK__ void BLE_ERR_IRQHandler (void);
|
||||
__WEAK__ void BLE_MAC_IRQHandler (void);
|
||||
__WEAK__ void DMA_IRQHandler (void);
|
||||
__WEAK__ void QSPI_IRQHandler (void);
|
||||
__WEAK__ void SDIO_F1_IRQHandler (void);
|
||||
__WEAK__ void SDIO_F2_IRQHandler (void);
|
||||
__WEAK__ void SDIO_F3_IRQHandler (void);
|
||||
__WEAK__ void CM4_FPIXC_IRQHandler (void);
|
||||
__WEAK__ void CM4_FPOFC_IRQHandler (void);
|
||||
__WEAK__ void CM4_FPUFC_IRQHandler (void);
|
||||
__WEAK__ void CM4_FPIOC_IRQHandler (void);
|
||||
__WEAK__ void CM4_FPDZC_IRQHandler (void);
|
||||
__WEAK__ void CM4_FPIDC_IRQHandler (void);
|
||||
__WEAK__ void I2C_IRQHandler (void);
|
||||
__WEAK__ void SPI0_IRQHandler (void);
|
||||
__WEAK__ void SPI1_IRQHandler (void);
|
||||
__WEAK__ void UART0_IRQHandler (void);
|
||||
__WEAK__ void UART1_IRQHandler (void);
|
||||
__WEAK__ void UART2_IRQHandler (void);
|
||||
__WEAK__ void ADC_IRQHandler (void);
|
||||
__WEAK__ void WS_IRQHandler (void);
|
||||
__WEAK__ void I2S_IRQHandler (void);
|
||||
__WEAK__ void GPIOA_IRQHandler (void);
|
||||
__WEAK__ void GPIOB_IRQHandler (void);
|
||||
__WEAK__ void TIMER0_IRQHandler (void);
|
||||
__WEAK__ void TIMER1_IRQHandler (void);
|
||||
__WEAK__ void TIMER2_IRQHandler (void);
|
||||
__WEAK__ void TIMER3_IRQHandler (void);
|
||||
__WEAK__ void ADV_TIMER_IRQHandler (void);
|
||||
__WEAK__ void AES_IRQHandler (void);
|
||||
__WEAK__ void TRNG_IRQHandler (void);
|
||||
__WEAK__ void PAOTD_IRQHandler (void);
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Initial Stack & Heap
|
||||
*----------------------------------------------------------------------------*/
|
||||
//<h> Stack Configuration
|
||||
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
//</h>
|
||||
#define __STACK_SIZE 0x00000600
|
||||
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
|
||||
|
||||
#if 0
|
||||
//<h> Heap Configuration
|
||||
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
//</h>
|
||||
#define __HEAP_SIZE 0x00004000
|
||||
#if __HEAP_SIZE > 0
|
||||
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
__WEAK__ void NMI_Handler (void) { while(1); }
|
||||
__WEAK__ void HardFault_Handler (void) { while(1); }
|
||||
__WEAK__ void MemManage_Handler (void) { while(1); }
|
||||
__WEAK__ void BusFault_Handler (void) { while(1); }
|
||||
__WEAK__ void UsageFault_Handler (void) { while(1); }
|
||||
__WEAK__ void SVC_Handler (void) { while(1); }
|
||||
__WEAK__ void DebugMon_Handler (void) { while(1); }
|
||||
__WEAK__ void PendSV_Handler (void) { while(1); }
|
||||
__WEAK__ void SysTick_Handler (void) { while(1); }
|
||||
__WEAK__ void WDT_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void EXT_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void RTC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void RFSLP_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void MAC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void BLE_WAKE_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void BLE_ERR_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void BLE_MAC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void DMA_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void QSPI_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void SDIO_F1_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void SDIO_F2_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void SDIO_F3_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void CM4_FPIXC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void CM4_FPOFC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void CM4_FPUFC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void CM4_FPIOC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void CM4_FPDZC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void CM4_FPIDC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void I2C_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void SPI0_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void SPI1_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void UART0_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void UART1_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void UART2_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void ADC_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void WS_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void I2S_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void GPIOA_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void GPIOB_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void TIMER0_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void TIMER1_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void TIMER2_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void TIMER3_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void ADV_TIMER_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void AES_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void TRNG_IRQHandler (void) { while(1); }
|
||||
__WEAK__ void PAOTD_IRQHandler (void) { while(1); }
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const pFunc __Vectors[240];
|
||||
const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
|
||||
(pFunc)(&__StackTop), /* (0x00)Top of Stack */
|
||||
Reset_Handler, /* (0x04)IRQ -15 Reset Handler */
|
||||
NMI_Handler, /* (0x08)IRQ -14 NMI Handler */
|
||||
HardFault_Handler, /* (0x0C)IRQ -13 Hard Fault Handler */
|
||||
MemManage_Handler, /* (0x10)IRQ -12 MPU Fault Handler */
|
||||
BusFault_Handler, /* (0x14)IRQ -11 Bus Fault Handler */
|
||||
UsageFault_Handler, /* (0x18)IRQ -10 Usage Fault Handler */
|
||||
0, /* (0x1C)IRQ -9 Reserved */
|
||||
0, /* (0x20)IRQ -8 Reserved */
|
||||
0, /* (0x24)IRQ -7 Reserved */
|
||||
0, /* (0x28)IRQ -6 Reserved */
|
||||
SVC_Handler, /* (0x2C)IRQ -5 SVCall Handler */
|
||||
DebugMon_Handler, /* (0x30)IRQ -4 Debug Monitor Handler */
|
||||
0, /* (0x34)IRQ -3 Reserved */
|
||||
PendSV_Handler, /* (0x38)IRQ -2 PendSV Handler */
|
||||
SysTick_Handler, /* (0x3C)IRQ -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
WDT_IRQHandler, /* (0x40)IRQ0 */
|
||||
EXT_IRQHandler, /* (0x44)IRQ1 */
|
||||
RTC_IRQHandler, /* (0x48)IRQ2 */
|
||||
RFSLP_IRQHandler, /* (0x4C)IRQ3 */
|
||||
MAC_IRQHandler, /* (0x50)IRQ4 */
|
||||
BLE_WAKE_IRQHandler, /* (0x54)IRQ5 */
|
||||
BLE_ERR_IRQHandler, /* (0x58)IRQ6 */
|
||||
BLE_MAC_IRQHandler, /* (0x5C)IRQ7 */
|
||||
DMA_IRQHandler, /* (0x60)IRQ8 */
|
||||
QSPI_IRQHandler, /* (0x64)IRQ9 */
|
||||
SDIO_F1_IRQHandler, /* (0x68)IRQ10 */
|
||||
SDIO_F2_IRQHandler, /* (0x6C)IRQ11 */
|
||||
SDIO_F3_IRQHandler, /* (0x70)IRQ12 */
|
||||
CM4_FPIXC_IRQHandler, /* (0x74)IRQ13 */
|
||||
CM4_FPOFC_IRQHandler, /* (0x78)IRQ14 */
|
||||
CM4_FPUFC_IRQHandler, /* (0x7C)IRQ15 */
|
||||
CM4_FPIOC_IRQHandler, /* (0x80)IRQ16 */
|
||||
CM4_FPDZC_IRQHandler, /* (0x84)IRQ17 */
|
||||
CM4_FPIDC_IRQHandler, /* (0x88)IRQ18 */
|
||||
I2C_IRQHandler, /* (0x8C)IRQ19 */
|
||||
SPI0_IRQHandler, /* (0x90)IRQ20 */
|
||||
SPI1_IRQHandler, /* (0x94)IRQ21 */
|
||||
UART0_IRQHandler, /* (0x98)IRQ22 */
|
||||
UART1_IRQHandler, /* (0x9C)IRQ23 */
|
||||
UART2_IRQHandler, /* (0xA0)IRQ24 */
|
||||
ADC_IRQHandler, /* (0xA4)IRQ25 */
|
||||
WS_IRQHandler, /* (0xA8)IRQ26 */
|
||||
I2S_IRQHandler, /* (0xAC)IRQ27 */
|
||||
GPIOA_IRQHandler, /* (0xB0)IRQ28 */
|
||||
GPIOB_IRQHandler, /* (0xB4)IRQ29 */
|
||||
TIMER0_IRQHandler, /* (0xB8)IRQ30 */
|
||||
TIMER1_IRQHandler, /* (0xBC)IRQ31 */
|
||||
TIMER2_IRQHandler, /* (0xC0)IRQ32 */
|
||||
TIMER3_IRQHandler, /* (0xC4)IRQ33 */
|
||||
ADV_TIMER_IRQHandler, /* (0xC8)IRQ34 */
|
||||
AES_IRQHandler, /* (0xCC)IRQ35 */
|
||||
TRNG_IRQHandler, /* (0xD0)IRQ36 */
|
||||
PAOTD_IRQHandler, /* (0xD4)IRQ37 */
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void) {
|
||||
uint32_t *pSrc, *pDest;
|
||||
uint32_t *pTable __attribute__((unused));
|
||||
|
||||
/* Firstly it copies data from read only memory to RAM.
|
||||
* There are two schemes to copy. One can copy more than one sections.
|
||||
* Another can copy only one section. The former scheme needs more
|
||||
* instructions and read-only data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
|
||||
*/
|
||||
pSrc = &__copysection_ram0_load;
|
||||
pDest = &__copysection_ram0_start;
|
||||
|
||||
for ( ; (pDest < &__copysection_ram0_end); ) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
pDest = &__bss_ram0_start__;
|
||||
for ( ; pDest < &__bss_ram0_end__ ; ) {
|
||||
*pDest++ = 0UL;
|
||||
}
|
||||
|
||||
pDest = &__retention_start__;
|
||||
for ( ; pDest < &__retention_end__ ; ) {
|
||||
*pDest++ = 0UL;
|
||||
}
|
||||
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
lt_main();
|
||||
}
|
||||
16
cores/lightning-ln882h/base/fixups/utils/debug/log.h
Normal file
16
cores/lightning-ln882h/base/fixups/utils/debug/log.h
Normal file
@@ -0,0 +1,16 @@
|
||||
#ifndef __cplusplus
|
||||
|
||||
#undef log_printf
|
||||
#define __wrap_sprintf __wrap_ln_sprintf
|
||||
#include_next "utils/debug/log.h"
|
||||
#undef __wrap_sprintf
|
||||
#undef log_printf
|
||||
#define log_printf(...) __wrap_ln_printf(__VA_ARGS__)
|
||||
#define __sprintf(tag, fct, ...) __wrap_ln_printf(tag);__wrap_ln_vprintf(__VA_ARGS__)
|
||||
|
||||
// Redefine LOG_LVL_CTRL
|
||||
#undef LOG_LVL_CTRL
|
||||
#define LOG_LVL_CTRL LOG_LVL_DEBUG
|
||||
|
||||
#endif //__cplusplus */
|
||||
|
||||
19
cores/lightning-ln882h/base/lt_defs.h
Normal file
19
cores/lightning-ln882h/base/lt_defs.h
Normal file
@@ -0,0 +1,19 @@
|
||||
#pragma once
|
||||
|
||||
#error "Don't include this file directly"
|
||||
|
||||
#define LT_HAS_FLASH 1
|
||||
#define LT_HAS_FREERTOS 1
|
||||
#define LT_HAS_LWIP 1
|
||||
#define LT_HAS_LWIP2 1
|
||||
#define LT_HAS_MBEDTLS 1
|
||||
#define LT_HAS_OTA 1
|
||||
#define LT_HAS_PRINTF 1
|
||||
#define LT_HW_DEEP_SLEEP 0
|
||||
#define LT_HW_WATCHDOG 1
|
||||
#define LT_HW_WIFI 1
|
||||
|
||||
#define LT_REMALLOC 1
|
||||
|
||||
#define LT_HEAP_FUNC xPortGetFreeHeapSize
|
||||
#define LT_REALLOC_FUNC pvPortReAlloc
|
||||
18
cores/lightning-ln882h/base/lt_family.h
Normal file
18
cores/lightning-ln882h/base/lt_family.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/* Copyright (c) Etienne Le Cousin 2024-02-10. */
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <lt_pins.h>
|
||||
|
||||
// Choose the main UART output port
|
||||
#ifndef LT_UART_DEFAULT_PORT
|
||||
#if LT_HW_UART0
|
||||
#define LT_UART_DEFAULT_PORT 0
|
||||
#elif LT_HW_UART1
|
||||
#define LT_UART_DEFAULT_PORT 1
|
||||
#elif LT_HW_UART2
|
||||
#define LT_UART_DEFAULT_PORT 2
|
||||
#else
|
||||
#error "No serial port is available"
|
||||
#endif
|
||||
#endif
|
||||
39
cores/lightning-ln882h/base/port/fal_flash_ln882h_port.c
Normal file
39
cores/lightning-ln882h/base/port/fal_flash_ln882h_port.c
Normal file
@@ -0,0 +1,39 @@
|
||||
/* Copyright (c) Etienne Le Cousin 2024-02-10. */
|
||||
|
||||
#include <libretiny.h>
|
||||
#include <sdk_private.h>
|
||||
|
||||
#include <fal.h>
|
||||
#include <hal/hal_flash.h>
|
||||
|
||||
#define FLASH_ERASE_MIN_SIZE (4 * 1024)
|
||||
|
||||
static int init() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read(long offset, uint8_t *buf, size_t size) {
|
||||
hal_flash_read(offset, size, buf);
|
||||
return size;
|
||||
}
|
||||
|
||||
static int write(long offset, const uint8_t *buf, size_t size) {
|
||||
hal_flash_program(offset, size, (uint8_t *)buf);
|
||||
return size;
|
||||
}
|
||||
|
||||
static int erase(long offset, size_t size) {
|
||||
offset &= ~(FLASH_ERASE_MIN_SIZE - 1);
|
||||
size = ((size - 1) / FLASH_ERASE_MIN_SIZE) + 1;
|
||||
hal_flash_erase(offset, size * FLASH_ERASE_MIN_SIZE);
|
||||
return size * FLASH_ERASE_MIN_SIZE;
|
||||
}
|
||||
|
||||
const struct fal_flash_dev flash0 = {
|
||||
.name = FAL_FLASH_DEV_NAME,
|
||||
.addr = 0x0,
|
||||
.len = FLASH_LENGTH,
|
||||
.blk_size = FLASH_ERASE_MIN_SIZE,
|
||||
.ops = {init, read, write, erase},
|
||||
.write_gran = 1,
|
||||
};
|
||||
21
cores/lightning-ln882h/base/port/printf.c
Normal file
21
cores/lightning-ln882h/base/port/printf.c
Normal file
@@ -0,0 +1,21 @@
|
||||
/* Copyright (c) Etienne Le Cousin 2024-02-19. */
|
||||
|
||||
#include <libretiny.h>
|
||||
#include <sdk_private.h>
|
||||
|
||||
#include <printf/printf.h>
|
||||
|
||||
extern Serial_t *serial_handles[SER_PORT_NUM];
|
||||
|
||||
uint8_t uart_print_port = LT_UART_DEFAULT_LOGGER;
|
||||
|
||||
void putchar_(char c) {
|
||||
putchar_p(c, uart_print_port);
|
||||
}
|
||||
|
||||
void putchar_p(char c, unsigned long port) {
|
||||
serial_putchar(serial_handles[port], c);
|
||||
}
|
||||
|
||||
WRAP_PRINTF(ln_printf);
|
||||
WRAP_VPRINTF(ln_vprintf);
|
||||
15
cores/lightning-ln882h/base/port/printf_port.h
Normal file
15
cores/lightning-ln882h/base/port/printf_port.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* Copyright (c) Etienne Le Cousin 2024-02-10. */
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <printf_config.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif // __cplusplus
|
||||
|
||||
WRAP_DISABLE_DEF(ln_printf);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
87
cores/lightning-ln882h/base/sdk_private.h
Normal file
87
cores/lightning-ln882h/base/sdk_private.h
Normal file
@@ -0,0 +1,87 @@
|
||||
/* Copyright (c) Etienne Le Cousin 2024-02-10. */
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
// Fix to not include SDK reg_xx.h files in C++
|
||||
// These files declare inline functions with unallowed volatile assignments in C++
|
||||
#define __REG_CACHE_H__
|
||||
#define __REG_GPIO_H__
|
||||
#define __REG_I2C_H__
|
||||
#define __REG_LN_UART_H__
|
||||
#define __REG_QSPI_H__
|
||||
#define __REG_WDT_H__
|
||||
#define __REG_SYSC_AWO_H__
|
||||
#define __REG_SYSC_CMP_H__
|
||||
extern "C" {
|
||||
#endif // __cplusplus
|
||||
|
||||
// PinNames
|
||||
#include "PinNames.h"
|
||||
|
||||
// undefine ROM stdio in favor of printf() library (wrappers)
|
||||
#undef printf
|
||||
#undef sprintf
|
||||
#undef vsprintf
|
||||
#undef snprintf
|
||||
#undef vsnprintf
|
||||
#undef vprintf
|
||||
#include <stdio.h>
|
||||
|
||||
// Conflicting types
|
||||
#define WIFI_MODE_STATION LN_WIFI_MODE_STATION
|
||||
#define WIFI_MODE_AP LN_WIFI_MODE_AP
|
||||
#define WIFI_MODE_AP_STATION LN_WIFI_MODE_AP_STATION
|
||||
#define WIFI_MODE_MAX LN_WIFI_MODE_MAX
|
||||
#define WIFI_AUTH_OPEN LN_WIFI_AUTH_OPEN
|
||||
#define WIFI_AUTH_WEP LN_WIFI_AUTH_WEP
|
||||
#define WIFI_AUTH_WPA_PSK LN_WIFI_AUTH_WPA_PSK
|
||||
#define WIFI_AUTH_WPA2_PSK LN_WIFI_AUTH_WPA2_PSK
|
||||
#define WIFI_AUTH_WPA_WPA2_PSK LN_WIFI_AUTH_WPA_WPA2_PSK
|
||||
#define WIFI_AUTH_WPA2_ENTERPRISE LN_WIFI_AUTH_WPA2_ENTERPRISE
|
||||
#define WIFI_AUTH_WPA3_SAE LN_WIFI_AUTH_WPA3_SAE
|
||||
#define WIFI_AUTH_WPA2_PSK_WPA3_SAE LN_WIFI_AUTH_WPA2_PSK_WPA3_SAE
|
||||
#define WIFI_AUTH_MAX LN_WIFI_AUTH_MAX
|
||||
#define wifi_mode_t ln_wifi_mode_t
|
||||
#define wifi_auth_mode_t ln_wifi_auth_mode_t
|
||||
|
||||
// SDK
|
||||
#include "ln_kv_api.h"
|
||||
#include "ln_nvds.h"
|
||||
#include "utils/debug/CmBacktrace/cm_backtrace.h"
|
||||
#include "utils/ln_psk_calc.h"
|
||||
#include "utils/power_mgmt/ln_pm.h"
|
||||
#include "utils/reboot_trace/reboot_trace.h"
|
||||
#include "utils/runtime/runtime.h"
|
||||
#include "utils/system_parameter.h"
|
||||
#include <hal/hal_adc.h>
|
||||
#include <hal/hal_gpio.h>
|
||||
#include <hal/hal_i2c.h>
|
||||
#include <hal/hal_interrupt.h>
|
||||
#include <hal/hal_wdt.h>
|
||||
#include <ln_wifi.h>
|
||||
#include <osal/osal.h>
|
||||
#include <serial/ln_serial.h>
|
||||
#include <wifi_manager.h>
|
||||
|
||||
#ifndef LN882H_SDK
|
||||
#undef WIFI_MODE_STATION
|
||||
#undef WIFI_MODE_AP
|
||||
#undef WIFI_MODE_AP_STATION
|
||||
#undef WIFI_MODE_MAX
|
||||
#undef WIFI_AUTH_OPEN
|
||||
#undef WIFI_AUTH_WEP
|
||||
#undef WIFI_AUTH_WPA_PSK
|
||||
#undef WIFI_AUTH_WPA2_PSK
|
||||
#undef WIFI_AUTH_WPA_WPA2_PSK
|
||||
#undef WIFI_AUTH_WPA2_ENTERPRISE
|
||||
#undef WIFI_AUTH_WPA3_SAE
|
||||
#undef WIFI_AUTH_WPA2_PSK_WPA3_SAE
|
||||
#undef WIFI_AUTH_MAX
|
||||
#undef wifi_mode_t
|
||||
#undef wifi_auth_mode_t
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
Reference in New Issue
Block a user