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[lightning-ln882h] Add support for Lightning LN882H family (#312)

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* fix mbedtls bad pointer in function call (prototype mismatch)

* fix issue with weak families functions implemented in static library, it will never be linked. fixed by redefining prototypes inside families

* [ln882x] add support for lightning ln882x & ln882h families

* add i2c (wire) support

* add analog (adc) support

* add watchdog support

* [ln882x] changed default uart 0/1 pins; added board wl2s

* [ln882x] fix IRQ & ADC pins

* [ln882x] boards cosmetic

* [ln882x] wifi sta use otp mac addr by default; re-enabled wifi powersave mode

* [ln882x] clang-format clean code

* [ln882x] clang-format clean code

* Update families.json

* Apply suggestions from code review

* [ln882x] reformat json board files

* [ln882x] os_queue cleanup

* [ln882x] removed Beken auto-download command

* [ln882x] removed personal script file

* [ln882x] removed unusefull pi section in debugging.md

* [ln882x] removed Arduino.h and changed private I2C definition

* [ln882x] updated README.md

* [ln882x] changed pin naming scheme to PA/PB

* [ln882x] clean code

* [ln882x] clean code

* [ln882x] add ota image verification

* Update push-dev.yml

* [ln882x] fix boards ADC missing inputs]

* [ln882x] removed reg_xxx fixup files and use include guards instead

* [ln882x] cleanup code

* [ln882x] cleanup code

* [ln882x] fix lt_init weak functions linking

* [ln882x] revert lt_api.h modification, fixed with previous commit

* [ln882x] setup UF2 firmware for flasher with partitions

* [ln882x] update README.md

* [ln882x] include ln_wifi.h and ln_serial.h to avoid including bad headers on case insensitive systems

* [ln882x] Replace RingBuffer by SerialRingBuffer

* [ln882x] clang-format

* [ln882x] update README.md

* Apply suggestions from code review

* Reformat board JSON files

* Add mkdocs link redirect

* Update ltchiptool to v4.12.0

---------

Co-authored-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
This commit is contained in:
lamauny
2025-03-25 17:26:53 +01:00
committed by GitHub
parent 6083cca72e
commit 69e7e2debe
73 changed files with 4856 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
cores/lightning-ln882h/base/fixups/.clang-format Normal file
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DisableFormat: true
SortIncludes: Never

4
cores/lightning-ln882h/base/fixups/os_queue.h Normal file
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#pragma once
#include "queue.h"

518
cores/lightning-ln882h/base/fixups/serial_hw.c Normal file
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#include "proj_config.h"
#include "hal/hal_uart.h"
#include "serial/ln_serial.h"
#include "serial_hw.h"
#include "utils/debug/ln_assert.h"
#include "hal/hal_gpio.h"
#include "hal/hal_misc.h"
#include "reg_sysc_cmp.h"//gpio fullmux
#define UART0_TX_BUF_SIZE CFG_UART0_TX_BUF_SIZE
#define UART0_RX_BUF_SIZE CFG_UART0_RX_BUF_SIZE
#define UART1_TX_BUF_SIZE CFG_UART1_TX_BUF_SIZE
#define UART1_RX_BUF_SIZE CFG_UART1_RX_BUF_SIZE
#define UART2_TX_BUF_SIZE CFG_UART2_TX_BUF_SIZE
#define UART2_RX_BUF_SIZE CFG_UART2_RX_BUF_SIZE
/* TX and RX fifo buffer */
uint8_t uart0_txbuf[UART0_TX_BUF_SIZE];
uint8_t uart0_rxbuf[UART0_RX_BUF_SIZE];
uint8_t uart1_txbuf[UART1_TX_BUF_SIZE];
uint8_t uart1_rxbuf[UART1_RX_BUF_SIZE];
uint8_t uart2_txbuf[UART2_TX_BUF_SIZE];
uint8_t uart2_rxbuf[UART2_RX_BUF_SIZE];
/* From the high-level serial driver */
extern Serial_t serial_handles[SER_PORT_NUM];
/* UART device*/
typedef struct
{
uint32_t uart_base;
uart_init_t_def init_cfg;
} uart_dev_t;
static uart_dev_t g_uart0;
static uart_dev_t g_uart1;
static uart_dev_t g_uart2;
/* serial */
typedef struct
{
struct SerialHardware Hardware;
struct Serial *serial;
} ln_serial_t;
ln_serial_t uart_serial[SER_PORT_NUM];
static void uart_io_pin_request(struct Serial *serial)
{
if (serial->port_id == SER_PORT_UART0)
{
hal_gpio_pin_afio_select(GPIOA_BASE,GPIO_PIN_2,UART0_TX);
hal_gpio_pin_afio_select(GPIOA_BASE,GPIO_PIN_3,UART0_RX);
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_2,HAL_ENABLE);
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_3,HAL_ENABLE);
}
else if (serial->port_id == SER_PORT_UART1)
{
hal_gpio_pin_afio_select(GPIOB_BASE,GPIO_PIN_8,UART1_RX);
hal_gpio_pin_afio_select(GPIOB_BASE,GPIO_PIN_9,UART1_TX);
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_8,HAL_ENABLE);
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_9,HAL_ENABLE);
}
else if (serial->port_id == SER_PORT_UART2)
{
}
}
static void uart_io_pin_release(struct Serial *serial)
{
if (serial == NULL)
{
return;
}
if (serial->port_id == SER_PORT_UART0)
{
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_2,HAL_DISABLE);
hal_gpio_pin_afio_en(GPIOA_BASE,GPIO_PIN_3,HAL_DISABLE);
}
else if (serial->port_id == SER_PORT_UART1)
{
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_8,HAL_DISABLE);
hal_gpio_pin_afio_en(GPIOB_BASE,GPIO_PIN_9,HAL_DISABLE);
}
else if (serial->port_id == SER_PORT_UART2)
{
}
}
static void hw_uart0_init(struct SerialHardware *_hw, struct Serial *serial, uint32_t baudrate)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw && serial);
hw = (ln_serial_t *)_hw;
hw->serial = serial;
g_uart0.uart_base = UART0_BASE;
g_uart0.init_cfg.baudrate = baudrate;//115200 921600 2000000
g_uart0.init_cfg.word_len = UART_WORD_LEN_8;
g_uart0.init_cfg.parity = UART_PARITY_NONE;
g_uart0.init_cfg.stop_bits = UART_STOP_BITS_1;
g_uart0.init_cfg.over_sampl= UART_OVER_SAMPL_8;
hal_uart_init(g_uart0.uart_base, &g_uart0.init_cfg);
hal_uart_rx_mode_en(g_uart0.uart_base, HAL_ENABLE);
hal_uart_tx_mode_en(g_uart0.uart_base, HAL_ENABLE);
hal_uart_en(g_uart0.uart_base, HAL_ENABLE);
hal_uart_it_en(g_uart0.uart_base, USART_IT_RXNE);
//uart_it_enable(g_uart0.uart_base, USART_IT_TXE);//uart_it_enable(g_uart0.uart_base, USART_IT_TXE);
NVIC_EnableIRQ(UART0_IRQn);
//request pin for uart
uart_io_pin_request(hw->serial);
}
static void hw_uart1_init(struct SerialHardware *_hw, struct Serial *serial, uint32_t baudrate)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw && serial);
hw = (ln_serial_t *)_hw;
hw->serial = serial;
g_uart1.uart_base = UART1_BASE;
g_uart1.init_cfg.baudrate = baudrate;//115200 921600 2000000
g_uart1.init_cfg.word_len = UART_WORD_LEN_8;
g_uart1.init_cfg.parity = UART_PARITY_NONE;
g_uart1.init_cfg.stop_bits = UART_STOP_BITS_1;
g_uart1.init_cfg.over_sampl= UART_OVER_SAMPL_8;
hal_uart_init(g_uart1.uart_base, &g_uart1.init_cfg);
hal_uart_rx_mode_en(g_uart1.uart_base, HAL_ENABLE);
hal_uart_tx_mode_en(g_uart1.uart_base, HAL_ENABLE);
hal_uart_en(g_uart1.uart_base, HAL_ENABLE);
hal_uart_it_en(g_uart1.uart_base, USART_IT_RXNE);
//uart_it_enable(g_uart1.uart_base, USART_IT_TXE);
NVIC_EnableIRQ(UART1_IRQn);
//request pin for uart
uart_io_pin_request(hw->serial);
}
static void hw_uart2_init(struct SerialHardware *_hw, struct Serial *serial, uint32_t baudrate)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw && serial);
hw = (ln_serial_t *)_hw;
hw->serial = serial;
g_uart2.uart_base = UART2_BASE;
g_uart2.init_cfg.baudrate = baudrate;//115200 921600 2000000
g_uart2.init_cfg.word_len = UART_WORD_LEN_8;
g_uart2.init_cfg.parity = UART_PARITY_NONE;
g_uart2.init_cfg.stop_bits = UART_STOP_BITS_1;
g_uart2.init_cfg.over_sampl= UART_OVER_SAMPL_8;
hal_uart_init(g_uart2.uart_base, &g_uart2.init_cfg);
hal_uart_rx_mode_en(g_uart2.uart_base, HAL_ENABLE);
hal_uart_tx_mode_en(g_uart2.uart_base, HAL_ENABLE);
hal_uart_en(g_uart2.uart_base, HAL_ENABLE);
hal_uart_it_en(g_uart2.uart_base, USART_IT_RXNE);
//uart_it_enable(g_uart2.uart_base, USART_IT_TXE);
NVIC_EnableIRQ(UART2_IRQn);
//request pin for uart
uart_io_pin_request(hw->serial);
}
static void hw_uart0_cleanup(struct SerialHardware *_hw)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw);
hal_misc_reset_uart0();
NVIC_ClearPendingIRQ(UART0_IRQn);
NVIC_DisableIRQ(UART0_IRQn);
hw = (ln_serial_t *)_hw;
uart_io_pin_release(hw->serial);
hw->serial = NULL; // must be reset to NULL
}
static void hw_uart1_cleanup(struct SerialHardware *_hw)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw);
hal_misc_reset_uart1();
NVIC_ClearPendingIRQ(UART1_IRQn);
NVIC_DisableIRQ(UART1_IRQn);
hw = (ln_serial_t *)_hw;
uart_io_pin_release(hw->serial);
hw->serial = NULL; // must be reset to NULL
}
static void hw_uart2_cleanup(struct SerialHardware *_hw)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw);
hal_misc_reset_uart2();
NVIC_ClearPendingIRQ(UART2_IRQn);
NVIC_DisableIRQ(UART2_IRQn);
hw = (ln_serial_t *)_hw;
uart_io_pin_release(hw->serial);
hw->serial = NULL; // must be reset to NULL
}
static void hw_uart_tx_start_polling(struct SerialHardware * _hw)
{
uint8_t ch;
ln_serial_t *hw = NULL;
uart_dev_t * pdev;
LN_ASSERT(_hw);
hw = (ln_serial_t *)_hw;
while(!fifo_isempty(&hw->serial->txfifo))
{
ch = fifo_pop(&hw->serial->txfifo);
pdev = (uart_dev_t *)hw->Hardware.hw_device;
while (hal_uart_flag_get(pdev->uart_base, USART_FLAG_TXE) != HAL_SET) {};
//while (uart_flag_get(pdev->uart_base, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
hal_uart_send_data(pdev->uart_base, ch);
}
}
#if 0
static void hw_uart_tx_start_isr(struct SerialHardware * _hw)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw);
hw = (ln_serial_t *)_hw;
if (hw->Hardware.isSending){
return;
}
if(!fifo_isempty(&hw->serial->txfifo))
{
hw->Hardware.isSending = LN_TRUE;
/* Enable TX empty interrupts. */
uart_it_enable(UART0_BASE, USART_IT_TXE);
}
}
#endif
static int8_t hw_uart_tx_is_sending(struct SerialHardware * _hw)
{
ln_serial_t *hw = NULL;
LN_ASSERT(_hw);
hw = (ln_serial_t *)_hw;
return hw->Hardware.isSending;
}
static int8_t hw_uart_set_baudrate(struct SerialHardware * _hw, uint32_t baudrate)
{
ln_serial_t *hw = NULL;
uart_dev_t * pdev;
LN_ASSERT(_hw);
hw = (ln_serial_t *)_hw;
pdev = (uart_dev_t *)hw->Hardware.hw_device;
hal_uart_baudrate_set(pdev->uart_base, baudrate);
return LN_TRUE;
}
/*
* High-level interface data structures.
*/
static const struct SerialHardwareVT uart0_vtable =
{
.init = hw_uart0_init,
.cleanup = hw_uart0_cleanup,
.txStart = hw_uart_tx_start_polling,//hw_uart_tx_start_polling,//hw_uart_tx_start_isr
.txSending = hw_uart_tx_is_sending,
.setBaudrate = hw_uart_set_baudrate,
};
static const struct SerialHardwareVT uart1_vtable =
{
.init = hw_uart1_init,
.cleanup = hw_uart1_cleanup,
.txStart = hw_uart_tx_start_polling,//hw_uart_tx_start_isr
.txSending = hw_uart_tx_is_sending,
.setBaudrate = hw_uart_set_baudrate,
};
static const struct SerialHardwareVT uart2_vtable =
{
.init = hw_uart2_init,
.cleanup = hw_uart2_cleanup,
.txStart = hw_uart_tx_start_polling,//hw_uart_tx_start_isr
.txSending = hw_uart_tx_is_sending,
.setBaudrate = hw_uart_set_baudrate,
};
ln_serial_t uart_serial[SER_PORT_NUM] =
{
{
.Hardware =
{
.table = &uart0_vtable,
.txbuffer = uart0_txbuf,
.rxbuffer = uart0_rxbuf,
.txbuffer_size = sizeof(uart0_txbuf),
.rxbuffer_size = sizeof(uart0_rxbuf),
.hw_device = (void *)&g_uart0,
.isSending = LN_FALSE,
},
.serial = NULL,
},
{
.Hardware =
{
.table = &uart1_vtable,
.txbuffer = uart1_txbuf,
.rxbuffer = uart1_rxbuf,
.txbuffer_size = sizeof(uart1_txbuf),
.rxbuffer_size = sizeof(uart1_rxbuf),
.hw_device = (void *)&g_uart1,
.isSending = LN_FALSE,
},
.serial = NULL,
},
{
.Hardware =
{
.table = &uart2_vtable,
.txbuffer = uart2_txbuf,
.rxbuffer = uart2_rxbuf,
.txbuffer_size = sizeof(uart2_txbuf),
.rxbuffer_size = sizeof(uart2_rxbuf),
.hw_device = (void *)&g_uart2,
.isSending = LN_FALSE,
},
.serial = NULL,
},
};
struct SerialHardware *serial_hw_getdesc(serial_port_id_t port_id)
{
LN_ASSERT(port_id < SER_PORT_NUM);
return (struct SerialHardware *)&uart_serial[port_id].Hardware;
}
///=====================UART0/1/2 IQR Handle===============================///
static inline void uart0_send_data_isr(void)
{
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART0];
uint8_t tx_char = 0;
if (fifo_isempty(&hw->serial->txfifo))
{
hal_uart_it_disable(UART0_BASE, USART_IT_TXE);
hw->Hardware.isSending = LN_FALSE;
}
else
{
tx_char = fifo_pop(&hw->serial->txfifo);
hal_uart_send_data(UART0_BASE, tx_char);
while (hal_uart_flag_get(UART0_BASE, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
}
}
static inline void uart0_recv_data_isr(void)
{
uint8_t ch = 0;
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART0];
while (fifo_isfull(&hw->serial->rxfifo)){
serial_purge_rx(hw->serial);
}
ch = hal_uart_recv_data(UART0_BASE);
fifo_push(&hw->serial->rxfifo, ch);
hw->serial->rx_callback();
}
static inline void serial_uart0_isr_callback(void)
{
if (hal_uart_it_en_status_get(UART0_BASE, USART_IT_RXNE) && \
hal_uart_flag_get(UART0_BASE, USART_FLAG_RXNE)) {
uart0_recv_data_isr();
}
if (hal_uart_it_en_status_get(UART0_BASE, USART_IT_TXE) && \
hal_uart_flag_get(UART0_BASE, USART_FLAG_TXE)) {
uart0_send_data_isr();
}
}
static inline void uart1_send_data_isr(void)
{
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART1];
uint8_t tx_char = 0;
if (fifo_isempty(&hw->serial->txfifo))
{
hal_uart_it_disable(UART1_BASE, USART_IT_TXE);
hw->Hardware.isSending = LN_FALSE;
}
else
{
tx_char = fifo_pop(&hw->serial->txfifo);
hal_uart_send_data(UART1_BASE, tx_char);
while (hal_uart_flag_get(UART1_BASE, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
}
}
static inline void uart1_recv_data_isr(void)
{
uint8_t ch = 0;
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART1];
while (fifo_isfull(&hw->serial->rxfifo)){
serial_purge_rx(hw->serial);
}
ch = hal_uart_recv_data(UART1_BASE);
fifo_push(&hw->serial->rxfifo, ch);
hw->serial->rx_callback();
}
static inline void serial_uart1_isr_callback(void)
{
if (hal_uart_it_en_status_get(UART1_BASE, USART_IT_RXNE) && \
hal_uart_flag_get(UART1_BASE, USART_FLAG_RXNE)) {
uart1_recv_data_isr();
}
if (hal_uart_it_en_status_get(UART1_BASE, USART_IT_TXE) && \
hal_uart_flag_get(UART1_BASE, USART_FLAG_TXE)) {
uart1_send_data_isr();
}
}
static inline void uart2_send_data_isr(void)
{
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART2];
uint8_t tx_char = 0;
if (fifo_isempty(&hw->serial->txfifo))
{
hal_uart_it_disable(UART2_BASE, USART_IT_TXE);
hw->Hardware.isSending = LN_FALSE;
}
else
{
tx_char = fifo_pop(&hw->serial->txfifo);
hal_uart_send_data(UART2_BASE, tx_char);
while (hal_uart_flag_get(UART2_BASE, USART_FLAG_TX_FIFO_FULL) == HAL_SET) {};
}
}
static inline void uart2_recv_data_isr(void)
{
uint8_t ch = 0;
ln_serial_t *hw = (ln_serial_t *)&uart_serial[SER_PORT_UART2];
while (fifo_isfull(&hw->serial->rxfifo)){
serial_purge_rx(hw->serial);
}
ch = hal_uart_recv_data(UART2_BASE);
fifo_push(&hw->serial->rxfifo, ch);
hw->serial->rx_callback();
}
static inline void serial_uart2_isr_callback(void)
{
if (hal_uart_it_en_status_get(UART2_BASE, USART_IT_RXNE) && \
hal_uart_flag_get(UART2_BASE, USART_FLAG_RXNE)) {
uart2_recv_data_isr();
}
if (hal_uart_it_en_status_get(UART2_BASE, USART_IT_TXE) && \
hal_uart_flag_get(UART2_BASE, USART_FLAG_TXE)) {
uart2_send_data_isr();
}
}
void UART0_IRQHandler(void)
{
serial_uart0_isr_callback();
}
void UART1_IRQHandler(void)
{
serial_uart1_isr_callback();
}
void UART2_IRQHandler(void)
{
serial_uart2_isr_callback();
}

42
cores/lightning-ln882h/base/fixups/serial_hw.h Normal file
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#ifndef __SERIAL_HW_H__
#define __SERIAL_HW_H__
#include "hal/hal_uart.h"
#include "ln_types.h"
struct SerialHardware;
struct Serial;
typedef enum {
SER_PORT_UART0 = 0,
SER_PORT_UART1 = 1,
SER_PORT_UART2 = 2,
SER_PORT_NUM = 3, /**< Number of serial ports */
SER_PORT_ID_INVALID = SER_PORT_NUM
}serial_port_id_t;
struct SerialHardwareVT
{
void (*init )(struct SerialHardware *ctx, struct Serial *ser, uint32_t baudrate);
void (*cleanup )(struct SerialHardware *ctx);
void (*txStart )(struct SerialHardware *ctx);
int8_t (*txSending )(struct SerialHardware *ctx);
int8_t (*setBaudrate)(struct SerialHardware *ctx, uint32_t baudrate);
};
struct SerialHardware
{
const struct SerialHardwareVT *table;
unsigned char *txbuffer;
unsigned char *rxbuffer;
size_t txbuffer_size;
size_t rxbuffer_size;
void *hw_device;
volatile int8_t isSending;
};
struct SerialHardware *serial_hw_getdesc(serial_port_id_t port_id);
#endif /* __SERIAL_HW_H__ */

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cores/lightning-ln882h/base/fixups/startup_ln882h_gcc.c Normal file
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#include "ln882h.h"
#include "ln_compiler.h"
/*----------------------------------------------------------------------------
Linker generated Symbols
*----------------------------------------------------------------------------*/
extern uint32_t __copysection_ram0_load;
extern uint32_t __copysection_ram0_start;
extern uint32_t __copysection_ram0_end;
extern uint32_t __etext;
extern uint32_t __bss_ram0_start__;
extern uint32_t __bss_ram0_end__;
extern uint32_t __StackTop;
extern uint32_t __retention_start__;
extern uint32_t __retention_end__;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
//extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
extern void lt_main (void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Reset_Handler (void) ;
__WEAK__ void NMI_Handler (void);
__WEAK__ void HardFault_Handler (void);
__WEAK__ void MemManage_Handler (void);
__WEAK__ void BusFault_Handler (void);
__WEAK__ void UsageFault_Handler (void);
__WEAK__ void SVC_Handler (void);
__WEAK__ void DebugMon_Handler (void);
__WEAK__ void PendSV_Handler (void);
__WEAK__ void SysTick_Handler (void);
__WEAK__ void WDT_IRQHandler (void);
__WEAK__ void EXT_IRQHandler (void);
__WEAK__ void RTC_IRQHandler (void);
__WEAK__ void RFSLP_IRQHandler (void);
__WEAK__ void MAC_IRQHandler (void);
__WEAK__ void BLE_WAKE_IRQHandler (void);
__WEAK__ void BLE_ERR_IRQHandler (void);
__WEAK__ void BLE_MAC_IRQHandler (void);
__WEAK__ void DMA_IRQHandler (void);
__WEAK__ void QSPI_IRQHandler (void);
__WEAK__ void SDIO_F1_IRQHandler (void);
__WEAK__ void SDIO_F2_IRQHandler (void);
__WEAK__ void SDIO_F3_IRQHandler (void);
__WEAK__ void CM4_FPIXC_IRQHandler (void);
__WEAK__ void CM4_FPOFC_IRQHandler (void);
__WEAK__ void CM4_FPUFC_IRQHandler (void);
__WEAK__ void CM4_FPIOC_IRQHandler (void);
__WEAK__ void CM4_FPDZC_IRQHandler (void);
__WEAK__ void CM4_FPIDC_IRQHandler (void);
__WEAK__ void I2C_IRQHandler (void);
__WEAK__ void SPI0_IRQHandler (void);
__WEAK__ void SPI1_IRQHandler (void);
__WEAK__ void UART0_IRQHandler (void);
__WEAK__ void UART1_IRQHandler (void);
__WEAK__ void UART2_IRQHandler (void);
__WEAK__ void ADC_IRQHandler (void);
__WEAK__ void WS_IRQHandler (void);
__WEAK__ void I2S_IRQHandler (void);
__WEAK__ void GPIOA_IRQHandler (void);
__WEAK__ void GPIOB_IRQHandler (void);
__WEAK__ void TIMER0_IRQHandler (void);
__WEAK__ void TIMER1_IRQHandler (void);
__WEAK__ void TIMER2_IRQHandler (void);
__WEAK__ void TIMER3_IRQHandler (void);
__WEAK__ void ADV_TIMER_IRQHandler (void);
__WEAK__ void AES_IRQHandler (void);
__WEAK__ void TRNG_IRQHandler (void);
__WEAK__ void PAOTD_IRQHandler (void);
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
//<h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
//</h>
#define __STACK_SIZE 0x00000600
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
#if 0
//<h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
//</h>
#define __HEAP_SIZE 0x00004000
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
#endif
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
__WEAK__ void NMI_Handler (void) { while(1); }
__WEAK__ void HardFault_Handler (void) { while(1); }
__WEAK__ void MemManage_Handler (void) { while(1); }
__WEAK__ void BusFault_Handler (void) { while(1); }
__WEAK__ void UsageFault_Handler (void) { while(1); }
__WEAK__ void SVC_Handler (void) { while(1); }
__WEAK__ void DebugMon_Handler (void) { while(1); }
__WEAK__ void PendSV_Handler (void) { while(1); }
__WEAK__ void SysTick_Handler (void) { while(1); }
__WEAK__ void WDT_IRQHandler (void) { while(1); }
__WEAK__ void EXT_IRQHandler (void) { while(1); }
__WEAK__ void RTC_IRQHandler (void) { while(1); }
__WEAK__ void RFSLP_IRQHandler (void) { while(1); }
__WEAK__ void MAC_IRQHandler (void) { while(1); }
__WEAK__ void BLE_WAKE_IRQHandler (void) { while(1); }
__WEAK__ void BLE_ERR_IRQHandler (void) { while(1); }
__WEAK__ void BLE_MAC_IRQHandler (void) { while(1); }
__WEAK__ void DMA_IRQHandler (void) { while(1); }
__WEAK__ void QSPI_IRQHandler (void) { while(1); }
__WEAK__ void SDIO_F1_IRQHandler (void) { while(1); }
__WEAK__ void SDIO_F2_IRQHandler (void) { while(1); }
__WEAK__ void SDIO_F3_IRQHandler (void) { while(1); }
__WEAK__ void CM4_FPIXC_IRQHandler (void) { while(1); }
__WEAK__ void CM4_FPOFC_IRQHandler (void) { while(1); }
__WEAK__ void CM4_FPUFC_IRQHandler (void) { while(1); }
__WEAK__ void CM4_FPIOC_IRQHandler (void) { while(1); }
__WEAK__ void CM4_FPDZC_IRQHandler (void) { while(1); }
__WEAK__ void CM4_FPIDC_IRQHandler (void) { while(1); }
__WEAK__ void I2C_IRQHandler (void) { while(1); }
__WEAK__ void SPI0_IRQHandler (void) { while(1); }
__WEAK__ void SPI1_IRQHandler (void) { while(1); }
__WEAK__ void UART0_IRQHandler (void) { while(1); }
__WEAK__ void UART1_IRQHandler (void) { while(1); }
__WEAK__ void UART2_IRQHandler (void) { while(1); }
__WEAK__ void ADC_IRQHandler (void) { while(1); }
__WEAK__ void WS_IRQHandler (void) { while(1); }
__WEAK__ void I2S_IRQHandler (void) { while(1); }
__WEAK__ void GPIOA_IRQHandler (void) { while(1); }
__WEAK__ void GPIOB_IRQHandler (void) { while(1); }
__WEAK__ void TIMER0_IRQHandler (void) { while(1); }
__WEAK__ void TIMER1_IRQHandler (void) { while(1); }
__WEAK__ void TIMER2_IRQHandler (void) { while(1); }
__WEAK__ void TIMER3_IRQHandler (void) { while(1); }
__WEAK__ void ADV_TIMER_IRQHandler (void) { while(1); }
__WEAK__ void AES_IRQHandler (void) { while(1); }
__WEAK__ void TRNG_IRQHandler (void) { while(1); }
__WEAK__ void PAOTD_IRQHandler (void) { while(1); }
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const pFunc __Vectors[240];
const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
(pFunc)(&__StackTop), /* (0x00)Top of Stack */
Reset_Handler, /* (0x04)IRQ -15 Reset Handler */
NMI_Handler, /* (0x08)IRQ -14 NMI Handler */
HardFault_Handler, /* (0x0C)IRQ -13 Hard Fault Handler */
MemManage_Handler, /* (0x10)IRQ -12 MPU Fault Handler */
BusFault_Handler, /* (0x14)IRQ -11 Bus Fault Handler */
UsageFault_Handler, /* (0x18)IRQ -10 Usage Fault Handler */
0, /* (0x1C)IRQ -9 Reserved */
0, /* (0x20)IRQ -8 Reserved */
0, /* (0x24)IRQ -7 Reserved */
0, /* (0x28)IRQ -6 Reserved */
SVC_Handler, /* (0x2C)IRQ -5 SVCall Handler */
DebugMon_Handler, /* (0x30)IRQ -4 Debug Monitor Handler */
0, /* (0x34)IRQ -3 Reserved */
PendSV_Handler, /* (0x38)IRQ -2 PendSV Handler */
SysTick_Handler, /* (0x3C)IRQ -1 SysTick Handler */
/* Interrupts */
WDT_IRQHandler, /* (0x40)IRQ0 */
EXT_IRQHandler, /* (0x44)IRQ1 */
RTC_IRQHandler, /* (0x48)IRQ2 */
RFSLP_IRQHandler, /* (0x4C)IRQ3 */
MAC_IRQHandler, /* (0x50)IRQ4 */
BLE_WAKE_IRQHandler, /* (0x54)IRQ5 */
BLE_ERR_IRQHandler, /* (0x58)IRQ6 */
BLE_MAC_IRQHandler, /* (0x5C)IRQ7 */
DMA_IRQHandler, /* (0x60)IRQ8 */
QSPI_IRQHandler, /* (0x64)IRQ9 */
SDIO_F1_IRQHandler, /* (0x68)IRQ10 */
SDIO_F2_IRQHandler, /* (0x6C)IRQ11 */
SDIO_F3_IRQHandler, /* (0x70)IRQ12 */
CM4_FPIXC_IRQHandler, /* (0x74)IRQ13 */
CM4_FPOFC_IRQHandler, /* (0x78)IRQ14 */
CM4_FPUFC_IRQHandler, /* (0x7C)IRQ15 */
CM4_FPIOC_IRQHandler, /* (0x80)IRQ16 */
CM4_FPDZC_IRQHandler, /* (0x84)IRQ17 */
CM4_FPIDC_IRQHandler, /* (0x88)IRQ18 */
I2C_IRQHandler, /* (0x8C)IRQ19 */
SPI0_IRQHandler, /* (0x90)IRQ20 */
SPI1_IRQHandler, /* (0x94)IRQ21 */
UART0_IRQHandler, /* (0x98)IRQ22 */
UART1_IRQHandler, /* (0x9C)IRQ23 */
UART2_IRQHandler, /* (0xA0)IRQ24 */
ADC_IRQHandler, /* (0xA4)IRQ25 */
WS_IRQHandler, /* (0xA8)IRQ26 */
I2S_IRQHandler, /* (0xAC)IRQ27 */
GPIOA_IRQHandler, /* (0xB0)IRQ28 */
GPIOB_IRQHandler, /* (0xB4)IRQ29 */
TIMER0_IRQHandler, /* (0xB8)IRQ30 */
TIMER1_IRQHandler, /* (0xBC)IRQ31 */
TIMER2_IRQHandler, /* (0xC0)IRQ32 */
TIMER3_IRQHandler, /* (0xC4)IRQ33 */
ADV_TIMER_IRQHandler, /* (0xC8)IRQ34 */
AES_IRQHandler, /* (0xCC)IRQ35 */
TRNG_IRQHandler, /* (0xD0)IRQ36 */
PAOTD_IRQHandler, /* (0xD4)IRQ37 */
};
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void) {
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
/* Firstly it copies data from read only memory to RAM.
* There are two schemes to copy. One can copy more than one sections.
* Another can copy only one section. The former scheme needs more
* instructions and read-only data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
*/
pSrc = &__copysection_ram0_load;
pDest = &__copysection_ram0_start;
for ( ; (pDest < &__copysection_ram0_end); ) {
*pDest++ = *pSrc++;
}
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_ram0_start__;
for ( ; pDest < &__bss_ram0_end__ ; ) {
*pDest++ = 0UL;
}
pDest = &__retention_start__;
for ( ; pDest < &__retention_end__ ; ) {
*pDest++ = 0UL;
}
SystemInit(); /* CMSIS System Initialization */
lt_main();
}

16
cores/lightning-ln882h/base/fixups/utils/debug/log.h Normal file
View File

@@ -0,0 +1,16 @@
#ifndef __cplusplus
#undef log_printf
#define __wrap_sprintf __wrap_ln_sprintf
#include_next "utils/debug/log.h"
#undef __wrap_sprintf
#undef log_printf
#define log_printf(...) __wrap_ln_printf(__VA_ARGS__)
#define __sprintf(tag, fct, ...) __wrap_ln_printf(tag);__wrap_ln_vprintf(__VA_ARGS__)
// Redefine LOG_LVL_CTRL
#undef LOG_LVL_CTRL
#define LOG_LVL_CTRL LOG_LVL_DEBUG
#endif //__cplusplus */