diff --git a/boards/wr3.json b/boards/wr3.json index 0f90f24..89ba24f 100644 --- a/boards/wr3.json +++ b/boards/wr3.json @@ -1,9 +1,13 @@ { "build": { "mcu": "rtl8710bn", + "family": "rtl8710", + "variant": "wr3", + "ldscript_sdk": "rlx8711B-symbol-v02-img2_xip1_2M.ld", "f_cpu": "125000000L", "amb_ota1_offset": "0x0800B000", - "amb_ota2_offset": "0x080D0000" + "amb_ota2_offset": "0x080D0000", + "amb_boot_all": "boot_all.bin" }, "frameworks": [ "realtek-ambz-sdk" diff --git a/boards/wr3/bin/boot_all.bin b/boards/wr3/bin/boot_all.bin new file mode 100644 index 0000000..5160f91 Binary files /dev/null and b/boards/wr3/bin/boot_all.bin differ diff --git a/boards/wr3/bin/descript.ion b/boards/wr3/bin/descript.ion new file mode 100644 index 0000000..983e07d --- /dev/null +++ b/boards/wr3/bin/descript.ion @@ -0,0 +1 @@ +boot_all.bin tysdk_for_rtl8710bn diff --git a/boards/wr3/ld/export-rom_symbol_v01.txt b/boards/wr3/ld/export-rom_symbol_v01.txt new file mode 100644 index 0000000..5ab1c0c --- /dev/null +++ b/boards/wr3/ld/export-rom_symbol_v01.txt @@ -0,0 +1,1427 @@ +SECTIONS +{ + __vectors_table = 0x0; + Reset_Handler = 0x101; + NMI_Handler = 0x115; + HardFault_Handler = 0x119; + MemManage_Handler = 0x12d; + BusFault_Handler = 0x131; + UsageFault_Handler = 0x135; + VSprintf = 0x201; + DiagPrintf = 0x4dd; + DiagSPrintf = 0x509; + DiagSnPrintf = 0x535; + prvDiagPrintf = 0x7ed; + prvDiagSPrintf = 0x821; + UARTIMG_Write = 0x855; + UARTIMG_Download = 0x901; + _memcmp = 0x991; + _memcpy = 0x9c5; + _memset = 0xa7d; + DumpForOneBytes = 0xae9; + CmdRomHelp = 0xc69; + CmdDumpWord = 0xccd; + CmdWriteWord = 0xd7d; + CmdFlash = 0xdd1; + CmdEfuse = 0x12c1; + CmdDumpByte = 0x1775; + CmdDumpHalfWord = 0x17c9; + CmdWriteByte = 0x1881; + SramReadWriteCpy = 0x18c1; + SramReadWriteTest = 0x19f9; + CmdSRamTest = 0x1ac9; + GetRomCmdNum = 0x1b59; + Rand = 0x1b5d; + Rand_Arc4 = 0x1bdd; + RandBytes_Get = 0x1c0d; + Isspace = 0x1c59; + Strtoul = 0x1c6d; + ArrayInitialize = 0x1d15; + GetArgc = 0x1d29; + GetArgv = 0x1d55; + UartLogCmdExecute = 0x1db1; + UartLogShowBackSpace = 0x1e49; + UartLogRecallOldCmd = 0x1e7d; + UartLogHistoryCmd = 0x1eb1; + UartLogCmdChk = 0x1f2d; + UartLogIrqHandle = 0x2035; + RtlConsolInit = 0x2101; + RtlConsolTaskRom = 0x218d; + RtlExitConsol = 0x21b9; + RtlConsolRom = 0x2205; + BKUP_Write = 0x2249; + BKUP_Read = 0x226d; + BKUP_Set = 0x228d; + BKUP_Clear = 0x22b9; + NCO32K_Init = 0x22e9; + EXT32K_Cmd = 0x2349; + NCO8M_Init = 0x2365; + NCO8M_Cmd = 0x23bd; + ISO_Set = 0x23d9; + PLL0_Set = 0x23f1; + PLL1_Set = 0x2409; + PLL2_Set = 0x2421; + PLL3_Set = 0x2439; + XTAL0_Set = 0x2451; + XTAL1_Set = 0x2469; + XTAL2_Set = 0x2481; + XTAL_ClkGet = 0x2499; + CPU_ClkSet = 0x24b1; + CPU_ClkGet = 0x24c5; + OSC32K_Calibration = 0x24e5; + OSC32K_Cmd = 0x25f9; + OSC8M_Get = 0x2631; + rtl_cryptoEngine_SrcDesc_Show = 0x2641; + rtl_cryptoEngine_info = 0x27f1; + rtl_cryptoEngine_init = 0x2949; + rtl_crypto_md5_init = 0x2975; + rtl_crypto_md5_process = 0x29b1; + rtl_crypto_md5 = 0x2a09; + rtl_crypto_sha1_init = 0x2a2d; + rtl_crypto_sha1_process = 0x2a69; + rtl_crypto_sha1 = 0x2a9d; + rtl_crypto_sha2_init = 0x2ac1; + rtl_crypto_sha2_process = 0x2b15; + rtl_crypto_sha2 = 0x2b4d; + rtl_crypto_hmac_md5_init = 0x2b71; + rtl_crypto_hmac_md5_process = 0x2bd1; + rtl_crypto_hmac_md5 = 0x2c0d; + rtl_crypto_hmac_sha1_init = 0x2c31; + rtl_crypto_hmac_sha1_process = 0x2c91; + rtl_crypto_hmac_sha1 = 0x2cc9; + rtl_crypto_hmac_sha2_init = 0x2ced; + rtl_crypto_hmac_sha2_process = 0x2d65; + rtl_crypto_hmac_sha2 = 0x2da1; + rtl_crypto_aes_cbc_init = 0x2dc5; + rtl_crypto_aes_cbc_encrypt = 0x2dfd; + rtl_crypto_aes_cbc_decrypt = 0x2e45; + rtl_crypto_aes_ecb_init = 0x2e8d; + rtl_crypto_aes_ecb_encrypt = 0x2ec5; + rtl_crypto_aes_ecb_decrypt = 0x2ef5; + rtl_crypto_aes_ctr_init = 0x2f25; + rtl_crypto_aes_ctr_encrypt = 0x2f5d; + rtl_crypto_aes_ctr_decrypt = 0x2f99; + rtl_crypto_3des_cbc_init = 0x2fd5; + rtl_crypto_3des_cbc_encrypt = 0x300d; + rtl_crypto_3des_cbc_decrypt = 0x3055; + rtl_crypto_3des_ecb_init = 0x309d; + rtl_crypto_3des_ecb_encrypt = 0x30d5; + rtl_crypto_3des_ecb_decrypt = 0x311d; + rtl_crypto_des_cbc_init = 0x3165; + rtl_crypto_des_cbc_encrypt = 0x319d; + rtl_crypto_des_cbc_decrypt = 0x31f5; + rtl_crypto_des_ecb_init = 0x324d; + rtl_crypto_des_ecb_encrypt = 0x3285; + rtl_crypto_des_ecb_decrypt = 0x32dd; + SYSTIMER_Init = 0x3335; + SYSTIMER_TickGet = 0x33a1; + SYSTIMER_GetPassTime = 0x33c1; + DelayNop = 0x3401; + DelayUs = 0x3411; + DelayMs = 0x346d; + USOC_DongleSpecialCmd = 0x3481; + USOC_DongleCmd = 0x35d9; + USOC_DongleIsr = 0x35f9; + USOC_SIE_INTConfig = 0x3621; + USOC_SIE_INTClear = 0x3639; + USOC_PHY_Write = 0x3645; + USOC_PHY_Read = 0x3679; + USOC_PHY_Autoload = 0x36c1; + USOC_DongleInit = 0x37a5; + EFUSE_USER_Read = 0x386d; + EFUSE_USER1_Read = 0x3971; + EFUSE_USER2_Read = 0x397d; + EFUSE_USER3_Read = 0x3989; + EFUSE_RemainLength = 0x3995; + EFUSE_USER_Write = 0x3a21; + EFUSE_USER1_Write = 0x3bb1; + EFUSE_USER2_Write = 0x3bc1; + EFUSE_USER3_Write = 0x3bd1; + EFUSE_OTP_Read1B = 0x3be1; + EFUSE_OTP_Write1B = 0x3c01; + EFUSE_OTP_Read32B = 0x3c21; + EFUSE_OTP_Write32B = 0x3c4d; + EFUSE_RDP_EN = 0x3cad; + EFUSE_RDP_KEY = 0x3ccd; + EFUSE_OTF_KEY = 0x3cf9; + EFUSE_JTAG_OFF = 0x3d25; + PAD_DrvStrength = 0x3d45; + PAD_PullCtrl = 0x3d75; + Pinmux_Config = 0x3dc5; + Pinmux_ConfigGet = 0x3dfd; + Pinmux_Deinit = 0x3e19; + PINMUX_UART0_Ctrl = 0x3e39; + PINMUX_UART1_Ctrl = 0x3e81; + PINMUX_UARTLOG_Ctrl = 0x3ea9; + PINMUX_SPI0_Ctrl = 0x3ef9; + PINMUX_SPI1_Ctrl = 0x3f8d; + PINMUX_SPIF_Ctrl = 0x400d; + PINMUX_I2C0_Ctrl = 0x406d; + PINMUX_I2C1_Ctrl = 0x40e1; + PINMUX_SDIOD_Ctrl = 0x4151; + PINMUX_I2S0_Ctrl = 0x41e5; + PINMUX_SWD_Ctrl = 0x4265; + PINMUX_SWD_OFF = 0x42b5; + PINMUX_SWD_REG = 0x42d9; + PINMUX_Ctrl = 0x42fd; + SOCPS_BackupCPUClk = 0x4391; + SOCPS_RestoreCPUClk = 0x43b1; + SOCPS_BootFromPS = 0x43d1; + SOCPS_TrapPin = 0x43f1; + SOCPS_ANACKSel = 0x4411; + SOCPS_CLKCal = 0x442d; + SOCPS_SetWakeEvent = 0x4485; + SOCPS_ClearWakeEvent = 0x449d; + SOCPS_WakePinsCtrl = 0x44a9; + SOCPS_WakePinCtrl = 0x44d9; + SOCPS_WakePinClear = 0x4529; + SOCPS_GetANATimerParam = 0x4539; + SOCPS_SetANATimer = 0x4575; + SOCPS_SetReguWakepin = 0x45dd; + SOCPS_SetReguTimer = 0x4605; + SOCPS_PWROption = 0x46d9; + SOCPS_PWROptionExt = 0x46e5; + SOCPS_PWRMode = 0x46f9; + SOCPS_SNZMode = 0x4721; + SOCPS_DeepStandby = 0x473d; + SOCPS_DeepSleep = 0x4791; + SDIO_StructInit = 0x47d5; + SDIO_Init = 0x47f1; + SDIO_INTClear = 0x486d; + SDIO_INTConfig = 0x487d; + SDIO_RPWM1_Get = 0x4895; + SDIO_RPWM2_Get = 0x48a1; + SDIO_CPWM1_Set = 0x48ad; + SDIO_CPWM2_Set = 0x48c1; + SDIO_RXBD_RPTR_Get = 0x48dd; + SDIO_RXBD_WPTR_Set = 0x48e9; + SDIO_TXBD_WPTR_Get = 0x48f5; + SDIO_TXBD_RPTR_Set = 0x4901; + SDIO_DMA_Reset = 0x490d; + BOOT_ROM_Simulation = 0x4919; + USOC_BOOT_TXBD_Proc = 0x491d; + USOC_BOOT_Init = 0x4a3d; + USB_Boot_ROM = 0x4aa9; + USOC_CH_Cmd = 0x4b59; + USOC_Cmd = 0x4bb1; + USOC_PHY_Cmd = 0x4bf5; + USOC_MODE_Cfg = 0x4c09; + USOC_TXBD_SWIDX_Cfg = 0x4c25; + USOC_TXBD_SWIDX_Get = 0x4c2d; + USOC_TXBD_HWIDX_Get = 0x4c35; + USOC_RXBD_HWIDX_Get = 0x4c3d; + USOC_RXBD_SWIDX_Cfg = 0x4c45; + USOC_RXBD_SWIDX_Get = 0x4c4d; + USOC_StructInit = 0x4c55; + USOC_Init = 0x4c85; + USOC_SW_RST = 0x4d7d; + USOC_INTCfg = 0x4d91; + USOC_INTClr = 0x4d95; + USOC_INTGet = 0x4d9d; + USOC_MIT_Cfg = 0x4da1; + USOC_TXSTUCK_Cfg = 0x4dc5; + USOC_RXSTUCK_Cfg = 0x4de9; + USOC_POWER_On = 0x4e0d; + ADC_RXGDMA_Init = 0x4e9d; + ADC_SetAudio = 0x4f45; + ADC_SetAnalog = 0x4f61; + ADC_Cmd = 0x4fbd; + ADC_INTConfig = 0x5031; + ADC_SetOneShot = 0x5049; + ADC_SetComp = 0x50fd; + ADC_INTClear = 0x517d; + ADC_INTClearPendingBits = 0x5189; + ADC_GetISR = 0x5195; + ADC_Read = 0x51a1; + ADC_ReceiveBuf = 0x51ad; + ADC_InitStruct = 0x5205; + ADC_Init = 0x524d; + BOOT_ROM_ShowBuildInfo = 0x52ed; + BOOT_ROM_OTFCheck = 0x5335; + BOOT_ROM_InitFlash = 0x5345; + BOOT_ROM_FromFlash = 0x5405; + BOOT_ROM_InitUsb = 0x5511; + BOOT_ROM_Process = 0x553d; + BOOT_ROM_InitDebugFlg = 0x5605; + HalResetVsr = 0x5639; + Cache_Enable = 0x5811; + Cache_Flush = 0x5831; + Cache_Debug = 0x5851; + CRYPTO_AlignToBe32 = 0x58bd; + CRYPTO_MemDump = 0x58d5; + CRYPTO_GetAESKey = 0x599d; + CRYPTO_SetAESKey = 0x5cb5; + CRYPTO_SetSecurityMode = 0x5d29; + CRYPTO_Init = 0x5f5d; + CRYPTO_DeInit = 0x60b9; + CRYPTO_Reset = 0x6101; + CRYPTO_Process = 0x6129; + CRYPTO_CipherInit = 0x6a11; + CRYPTO_CipherEncrypt = 0x6a35; + CRYPTO_CipherDecrypt = 0x6a61; + CRYPTO_SetCheckSumEn = 0x6a95; + CRYPTO_GetCheckSumData = 0x6ab1; + LOGUART_StructInit = 0x6abd; + LOGUART_Init = 0x6ad5; + LOGUART_PutChar = 0x6b15; + LOGUART_GetChar = 0x6b49; + LOGUART_GetIMR = 0x6b65; + LOGUART_SetIMR = 0x6b71; + LOGUART_WaitBusy = 0x6b7d; + DIAG_UartInit = 0x6b9d; + DIAG_UartReInit = 0x6c25; + EFUSE_PowerSwitchROM = 0x6c49; + EFUSE_OneByteReadROM = 0x6d65; + EFUSE_OneByteWriteROM = 0x6e0d; + EFUSE_PG_Packet = 0x6e29; + EFUSE_LogicalMap_Read = 0x7091; + EFUSE_LogicalMap_Write = 0x71f5; + FLASH_SetSpiMode = 0x73dd; + FLASH_RxCmd = 0x7465; + FLASH_WaitBusy = 0x74cd; + FLASH_RxData = 0x754d; + FLASH_TxCmd = 0x75cd; + FLASH_WriteEn = 0x763d; + FLASH_TxData12B = 0x7661; + FLASH_SetStatus = 0x7735; + FLASH_Erase = 0x7755; + FLASH_DeepPowerDown = 0x77f5; + FLASH_SetStatusBits = 0x784d; + FLASH_Calibration = 0x791d; + FLASH_StructInit_Micron = 0x7a65; + FLASH_StructInit_MXIC = 0x7af5; + FLASH_StructInit_GD = 0x7b81; + FLASH_StructInit = 0x7c11; + FLASH_Init = 0x7ca1; + FLASH_ClockDiv = 0x7d15; + FLASH_CalibrationInit = 0x7d99; + FLASH_Calibration500MPSCmd = 0x7db1; + FLASH_CalibrationPhase = 0x7dcd; + FLASH_CalibrationPhaseIdx = 0x7e59; + FLASH_CalibrationNewCmd = 0x7e6d; + FLASH_CalibrationNew = 0x7ea9; + GDMA_StructInit = 0x80dd; + GDMA_SetLLP = 0x80f9; + GDMA_ClearINTPendingBit = 0x8191; + GDMA_ClearINT = 0x81d5; + GDMA_INTConfig = 0x8211; + GDMA_Cmd = 0x8259; + GDMA_Init = 0x828d; + GDMA_ChCleanAutoReload = 0x83c1; + GDMA_SetSrcAddr = 0x83f9; + GDMA_GetSrcAddr = 0x8411; + GDMA_GetDstAddr = 0x8429; + GDMA_SetDstAddr = 0x843d; + GDMA_SetBlkSize = 0x8459; + GDMA_GetBlkSize = 0x8489; + GDMA_ChnlRegister = 0x84a1; + GDMA_ChnlUnRegister = 0x8529; + GDMA_ChnlAlloc = 0x8591; + GDMA_ChnlFree = 0x8615; + GPIO_INTMode = 0x864d; + GPIO_INTConfig = 0x86e5; + GPIO_INTHandler = 0x8725; + GPIO_Direction = 0x8771; + GPIO_Init = 0x87a1; + GPIO_DeInit = 0x886d; + GPIO_ReadDataBit = 0x88c9; + GPIO_WriteBit = 0x88ed; + GPIO_PortDirection = 0x891d; + GPIO_PortRead = 0x893d; + GPIO_PortWrite = 0x894d; + GPIO_UserRegIrq = 0x8969; + I2C_StructInit = 0x899d; + I2C_SetSpeed = 0x89e5; + I2C_SetSlaveAddress = 0x8b3d; + I2C_CheckFlagState = 0x8b79; + I2C_INTConfig = 0x8bad; + I2C_ClearINT = 0x8be5; + I2C_ClearAllINT = 0x8c85; + I2C_Init = 0x8cad; + I2C_GetRawINT = 0x8dc9; + I2C_GetINT = 0x8df1; + I2C_MasterSendNullData = 0x8e19; + I2C_MasterSend = 0x8e65; + I2C_SlaveSend = 0x8ead; + I2C_ReceiveData = 0x8ed9; + I2C_MasterWrite = 0x8f05; + I2C_MasterReadDW = 0x8f89; + I2C_MasterRead = 0x9019; + I2C_SlaveWrite = 0x9089; + I2C_SlaveRead = 0x90f1; + I2C_MasterRepeatRead = 0x9141; + I2C_Cmd = 0x91c1; + I2C_PinMuxInit = 0x91fd; + I2C_PinMuxDeInit = 0x9255; + I2C_DMAControl = 0x92ad; + I2C_DmaMode1Config = 0x92e9; + I2C_DmaMode2Config = 0x9331; + I2C_TXGDMA_Init = 0x9375; + I2C_RXGDMA_Init = 0x9459; + I2C_Sleep_Cmd = 0x9521; + I2C_WakeUp = 0x95a1; + I2S_StructInit = 0x95e9; + I2S_Cmd = 0x9611; + I2S_TxDmaCmd = 0x962d; + I2S_RxDmaCmd = 0x9641; + I2S_INTConfig = 0x9655; + I2S_INTClear = 0x965d; + I2S_INTClearAll = 0x9665; + I2S_Init = 0x9671; + I2S_ISRGet = 0x97a9; + I2S_SetRate = 0x97b5; + I2S_SetWordLen = 0x9811; + I2S_SetChNum = 0x9839; + I2S_SetPageNum = 0x9861; + I2S_SetPageSize = 0x9895; + I2S_GetPageSize = 0x98a9; + I2S_SetDirection = 0x98b5; + I2S_SetDMABuf = 0x98dd; + I2S_TxPageBusy = 0x9905; + I2S_GetTxPage = 0x9911; + I2S_GetRxPage = 0x991d; + I2S_SetTxPageAddr = 0x9929; + I2S_GetTxPageAddr = 0x9939; + I2S_SetRxPageAddr = 0x9949; + I2S_GetRxPageAddr = 0x9959; + I2S_TxPageDMA_EN = 0x9969; + I2S_RxPageDMA_EN = 0x998d; + io_assert_failed = 0x99d9; + OTF_init = 0x99fd; + OTF_Cmd = 0x9a79; + OTF_Mask = 0x9a8d; + KEY_Request = 0x9add; + RDP_EN_Request = 0x9b21; + RCC_PeriphClockCmd = 0x9b65; + FUNC_HCI_COM = 0x9c95; + RTC_ByteToBcd2 = 0x9cad; + RTC_Bcd2ToByte = 0x9cc9; + RTC_ClokSource = 0x9cdd; + RTC_EnterInitMode = 0x9d19; + RTC_ExitInitMode = 0x9d51; + RTC_WaitForSynchro = 0x9d61; + RTC_BypassShadowCmd = 0x9da9; + RTC_StructInit = 0x9dd9; + RTC_Init = 0x9de5; + RTC_TimeStructInit = 0x9e7d; + RTC_SetTime = 0x9e8d; + RTC_GetTime = 0x9ff9; + RTC_SetAlarm = 0xa051; + RTC_AlarmStructInit = 0xa211; + RTC_GetAlarm = 0xa231; + RTC_AlarmCmd = 0xa2a1; + RTC_AlarmClear = 0xa2f5; + RTC_DayLightSavingConfig = 0xa305; + RTC_GetStoreOperation = 0xa355; + RTC_OutputConfig = 0xa365; + RTC_SmoothCalibConfig = 0xa39d; + SDIO_IsTimeout = 0xa459; + SDIOB_Init = 0xa481; + SDIOB_INTConfig = 0xa575; + SDIOB_DeInit = 0xa591; + SDIOB_H2C_WriteMem = 0xa5d9; + SDIOB_H2C_SetMem = 0xa605; + SDIOB_H2C_DataHandle = 0xa631; + SDIOB_H2C_DataReady = 0xa73d; + SDIOB_IRQ_Handler_BH = 0xa80d; + SDIOB_H2C_Task = 0xa8c9; + SDIO_Boot_Up = 0xa8e5; + SPI_DmaInit = 0xa91d; + SPI_DataHandle = 0xa9d1; + SPI_Boot_DmaRxIrqHandle = 0xaa01; + SPI_Boot_ROM = 0xaa5d; + SSI_StructInit = 0xabbd; + SSI_Cmd = 0xabf5; + SSI_INTConfig = 0xac09; + SSI_SetSclkPolarity = 0xac19; + SSI_SetSclkPhase = 0xac3d; + SSI_SetDataFrameSize = 0xac61; + SSI_SetReadLen = 0xac81; + SSI_SetBaudDiv = 0xacb1; + SSI_SetBaud = 0xaccd; + SSI_SetDmaEnable = 0xad2d; + SSI_SetDmaLevel = 0xad41; + SSI_SetIsrClean = 0xad49; + SSI_WriteData = 0xad65; + SSI_SetRxFifoLevel = 0xad6d; + SSI_SetTxFifoLevel = 0xad71; + SSI_ReadData = 0xad75; + SSI_GetRxCount = 0xad79; + SSI_GetTxCount = 0xad81; + SSI_GetStatus = 0xad89; + SSI_Writeable = 0xad8d; + SSI_Readable = 0xad9d; + SSI_GetDataFrameSize = 0xadad; + SSI_TXGDMA_Init = 0xadb9; + SSI_RXGDMA_Init = 0xaef9; + SSI_ReceiveData = 0xb021; + SSI_SendData = 0xb0b9; + SSI_Busy = 0xb165; + SSI_SetSlaveEnable = 0xb175; + SSI_Init = 0xb1ad; + SSI_GetIsr = 0xb235; + SSI_GetRawIsr = 0xb239; + SSI_GetSlaveEnable = 0xb23d; + SSI_PinmuxInit = 0xb241; + SSI_PinmuxDeInit = 0xb2a9; + SYSCFG0_Get = 0xb311; + SYSCFG0_CUTVersion = 0xb31d; + SYSCFG0_BDOption = 0xb32d; + SYSCFG1_Get = 0xb33d; + SYSCFG1_AutoLoadDone = 0xb349; + SYSCFG1_TRP_LDOMode = 0xb359; + SYSCFG1_TRP_UARTImage = 0xb369; + SYSCFG1_TRP_ICFG = 0xb37d; + SYSCFG2_Get = 0xb389; + SYSCFG2_ROMINFO_Get = 0xb395; + SYSCFG2_ROMINFO_Set = 0xb3a1; + RTIM_TimeBaseStructInit = 0xb3b5; + RTIM_Cmd = 0xb3cd; + RTIM_GetCount = 0xb42d; + RTIM_UpdateDisableConfig = 0xb475; + RTIM_ARRPreloadConfig = 0xb4c5; + RTIM_UpdateRequestConfig = 0xb515; + RTIM_PrescalerConfig = 0xb575; + RTIM_GenerateEvent = 0xb5a1; + RTIM_ChangePeriod = 0xb5f9; + RTIM_Reset = 0xb64d; + RTIM_CCStructInit = 0xb68d; + RTIM_CCxInit = 0xb6a1; + RTIM_CCRxMode = 0xb749; + RTIM_CCRxSet = 0xb785; + RTIM_CCRxGet = 0xb7dd; + RTIM_OCxPreloadConfig = 0xb80d; + RTIM_CCxPolarityConfig = 0xb85d; + RTIM_CCxCmd = 0xb8ad; + RTIM_SetOnePulseOutputMode = 0xb901; + RTIM_DMACmd = 0xb959; + RTIM_TXGDMA_Init = 0xb9a9; + RTIM_RXGDMA_Init = 0xba5d; + RTIM_INTConfig = 0xbb3d; + RTIM_INTClear = 0xbba9; + RTIM_TimeBaseInit = 0xbbed; + RTIM_DeInit = 0xbced; + RTIM_INTClearPendingBit = 0xbd41; + RTIM_GetFlagStatus = 0xbd81; + RTIM_GetINTStatus = 0xbded; + UART_DeInit = 0xbe61; + UART_StructInit = 0xbe69; + UART_BaudParaGet = 0xbe81; + UART_BaudParaGetFull = 0xbec9; + UART_SetBaud = 0xbf01; + UART_SetBaudExt = 0xbf71; + UART_SetRxLevel = 0xbfc1; + UART_RxCmd = 0xbfe9; + UART_Writable = 0xbffd; + UART_Readable = 0xc005; + UART_CharPut = 0xc00d; + UART_CharGet = 0xc011; + UART_ReceiveData = 0xc019; + UART_SendData = 0xc041; + UART_ReceiveDataTO = 0xc069; + UART_SendDataTO = 0xc0a9; + UART_RxByteCntClear = 0xc0e9; + UART_RxByteCntGet = 0xc0f5; + UART_BreakCtl = 0xc0fd; + UART_ClearRxFifo = 0xc111; + UART_Init = 0xc135; + UART_ClearTxFifo = 0xc1d1; + UART_INTConfig = 0xc1dd; + UART_IntStatus = 0xc1ed; + UART_ModemStatusGet = 0xc1f1; + UART_LineStatusGet = 0xc1f5; + UART_WaitBusy = 0xc1f9; + UART_PinMuxInit = 0xc221; + UART_PinMuxDeinit = 0xc289; + UART_TXDMAConfig = 0xc2f1; + UART_RXDMAConfig = 0xc301; + UART_TXDMACmd = 0xc315; + UART_RXDMACmd = 0xc329; + UART_TXGDMA_Init = 0xc33d; + UART_RXGDMA_Init = 0xc425; + UART_LPRxStructInit = 0xc501; + UART_LPRxInit = 0xc50d; + UART_LPRxBaudSet = 0xc575; + UART_LPRxMonitorCmd = 0xc5f1; + UART_LPRxpathSet = 0xc62d; + UART_LPRxIPClockSet = 0xc641; + UART_LPRxCmd = 0xc6b1; + UART_LPRxMonBaudCtrlRegGet = 0xc6c5; + UART_LPRxMonitorSatusGet = 0xc6c9; + UART_IrDAStructInit = 0xc6cd; + UART_IrDAInit = 0xc6e5; + UART_IrDACmd = 0xc7bd; + INT_SysOn = 0xc7d1; + INT_Wdg = 0xc811; + INT_Timer0 = 0xc855; + INT_Timer1 = 0xc899; + INT_Timer2 = 0xc8dd; + INT_Timer3 = 0xc921; + INT_SPI0 = 0xc965; + INT_GPIO = 0xc9a9; + INT_Uart0 = 0xc9ed; + INT_SPIFlash = 0xca31; + INT_Uart1 = 0xca75; + INT_Timer4 = 0xcab9; + INT_I2S0 = 0xcafd; + INT_Timer5 = 0xcb41; + INT_WlDma = 0xcb85; + INT_WlProtocol = 0xcbc9; + INT_IPSEC = 0xcc0d; + INT_SPI1 = 0xcc51; + INT_Peripheral = 0xcc95; + INT_Gdma0Ch0 = 0xccd9; + INT_Gdma0Ch1 = 0xcd1d; + INT_Gdma0Ch2 = 0xcd61; + INT_Gdma0Ch3 = 0xcda5; + INT_Gdma0Ch4 = 0xcde9; + INT_Gdma0Ch5 = 0xce2d; + INT_I2C0 = 0xce71; + INT_I2C1 = 0xceb5; + INT_Uartlog = 0xcef9; + INT_ADC = 0xcf3d; + INT_RDP = 0xcf81; + INT_RTC = 0xcfc5; + INT_Gdma1Ch0 = 0xd009; + INT_Gdma1Ch1 = 0xd051; + INT_Gdma1Ch2 = 0xd099; + INT_Gdma1Ch3 = 0xd0e1; + INT_Gdma1Ch4 = 0xd129; + INT_Gdma1Ch5 = 0xd171; + INT_USB = 0xd1b9; + INT_RXI300 = 0xd201; + INT_USB_SIE = 0xd249; + INT_SdioD = 0xd291; + INT_NMI = 0xd2d1; + INT_HardFault = 0xd305; + INT_MemManage = 0xd4b5; + INT_BusFault = 0xd4d5; + INT_UsageFault = 0xd4f5; + VECTOR_TableInit = 0xd515; + VECTOR_TableInitForOS = 0xd6c5; + VECTOR_IrqRegister = 0xd6d5; + VECTOR_IrqUnRegister = 0xd6f9; + VECTOR_IrqEn = 0xd715; + VECTOR_IrqDis = 0xd765; + WDG_Scalar = 0xd7a1; + WDG_Init = 0xd7e1; + WDG_IrqClear = 0xd7fd; + WDG_IrqInit = 0xd80d; + WDG_Cmd = 0xd83d; + WDG_Refresh = 0xd85d; + _strncpy = 0xd86d; + _strcpy = 0xd889; + prvStrCpy = 0xd899; + _strlen = 0xd8b1; + _strnlen = 0xd8c9; + prvStrLen = 0xd8fd; + _strcmp = 0xd919; + _strncmp = 0xd939; + prvStrCmp = 0xd985; + StrUpr = 0xd9b5; + prvAtoi = 0xd9d1; + prvStrtok = 0xda29; + prvStrStr = 0xda81; + _strsep = 0xdab9; + skip_spaces = 0xdaf5; + skip_atoi = 0xdb11; + _parse_integer_fixup_radix = 0xdb49; + _parse_integer = 0xdb9d; + simple_strtoull = 0xdc01; + simple_strtoll = 0xdc21; + simple_strtoul = 0xdc41; + simple_strtol = 0xdc49; + _vsscanf = 0xdc61; + _sscanf = 0xe1c9; + div_u64 = 0xe1e5; + div_s64 = 0xe1ed; + div_u64_rem = 0xe1f5; + div_s64_rem = 0xe205; + _strpbrk = 0xe215; + _strchr = 0xe241; + COMMPORT_GET_T = 0xe259; + COMMPORT_CLEAN_RX = 0xe289; + xModemDebugInit = 0xe2a5; + xModemDebug = 0xe2dd; + xModemInquiry = 0xe315; + xModemGetFirst = 0xe339; + xModemGetOthers = 0xe45d; + xModemRxFrame = 0xe691; + xModemHandshake = 0xe6d5; + xModemRxBuffer = 0xe945; + xmodem_log_close = 0xe9f5; + xmodem_log_open = 0xea01; + xmodem_uart_init = 0xea39; + xmodem_uart_deinit = 0xeb25; + xmodem_uart_port_init = 0xeb35; + xmodem_uart_port_deinit = 0xeb99; + xmodem_uart_readable = 0xebdd; + xmodem_uart_writable = 0xebf5; + xmodem_uart_getc = 0xec0d; + xmodem_uart_putc = 0xec35; + xmodem_uart_putdata = 0xec49; + aes_set_key = 0xec65; + aes_encrypt = 0xf021; + aes_decrypt = 0x10171; + AES_WRAP = 0x112b1; + AES_UnWRAP = 0x113fd; + crc32_get = 0x11549; + arc4_byte = 0x1157d; + rt_arc4_init = 0x115a5; + rt_arc4_crypt = 0x115e9; + rt_md5_init = 0x11df5; + rt_md5_append = 0x11e25; + rt_md5_final = 0x11ec9; + rt_md5_hmac = 0x11f21; + RC4 = 0x12061; + RC4_set_key = 0x1238d; + ROM_WIFI_ReadPowerValue = 0x1246d; + ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d; + ROM_WIFI_8051Reset = 0x125c5; + ROM_WIFI_FWDownloadEnable = 0x125dd; + ROM_WIFI_BlockWrite = 0x12619; + ROM_WIFI_PageWrite = 0x12661; + ROM_WIFI_FillDummy = 0x12685; + ROM_WIFI_WriteFW = 0x126b1; + ROM_WIFI_FWFreeToGo = 0x1275d; + ROM_WIFI_InitLLTTable = 0x127f9; + ROM_WIFI_GetChnlGroup = 0x12879; + ROM_WIFI_BWMapping = 0x129f1; + ROM_WIFI_SCMapping = 0x12a19; + ROM_WIFI_FillTxdescSectype = 0x12a99; + ROM_WIFI_FillFakeTxdesc = 0x12ab9; + ROM_WIFI_32K_Cmd = 0x12b91; + ROM_WIFI_DISCONNECT = 0x12bc1; + ROM_WIFI_SET_TSF = 0x12bfd; + ROM_WIFI_BCN_FUNC = 0x12ca5; + ROM_WIFI_BSSID_SET = 0x12ccd; + ROM_WIFI_MACADDR_SET = 0x12d09; + ROM_WIFI_EnableInterrupt = 0x12d39; + ROM_WIFI_DisableInterrupt = 0x12d4d; + ROM_WIFI_RESUME_TxBeacon = 0x12d61; + ROM_WIFI_STOP_TXBeacon = 0x12d91; + ROM_WIFI_BCN_Interval = 0x12dc1; + ROM_WIFI_BCN_FUNC_Enable = 0x12dcd; + ROM_WIFI_INIT_BeaconParameters = 0x12de5; + ROM_WIFI_MEDIA_STATUS1 = 0x12e35; + ROM_WIFI_MEDIA_STATUS = 0x12e4d; + ROM_WIFI_SetBrateCfg = 0x12e61; + ROM_WIFI_BASIC_RATE = 0x12f69; + ROM_WIFI_CHECK_BSSID = 0x12fc9; + ROM_WIFI_RESP_SIFS = 0x12fe9; + ROM_WIFI_CAM_WRITE = 0x13001; + ROM_WIFI_ACM_CTRL = 0x13021; + ROM_WIFI_FIFO_CLEARN_UP = 0x13051; + ROM_WIFI_CHECK_TXBUF = 0x130b9; + ROM_WIFI_BCN_VALID = 0x130fd; + ROM_WIFI_PROMISC_Cmd = 0x13119; + ROM_WIFI_SetOpmodeAP = 0x13189; + ROM_WIFI_ReadChipVersion = 0x132a9; + ROM_WIFI_DumpChipInfo = 0x1330d; + ROM_WIFI_InitLxDma = 0x135b1; + ROM_WIFI_InitQueueReservedPage = 0x13671; + ROM_WIFI_InitTxBufferBoundary = 0x136f1; + ROM_WIFI_InitNormalChipRegPriority = 0x1373d; + ROM_WIFI_InitPageBoundary = 0x13789; + ROM_WIFI_InitTransferPageSize = 0x13795; + ROM_WIFI_InitDriverInfoSize = 0x137a1; + ROM_WIFI_InitNetworkType = 0x137ad; + ROM_WIFI_InitRCR = 0x137c5; + ROM_WIFI_InitAdaptiveCtrl = 0x13805; + ROM_WIFI_InitSIFS = 0x1383d; + ROM_WIFI_InitEDCA = 0x13865; + ROM_WIFI_InitRateFallback = 0x138a1; + ROM_WIFI_InitRetryFunction = 0x138c9; + ROM_WIFI_InitOperationMode = 0x138e5; + ROM_WIFI_InitBurstPktLen = 0x138f9; + phy_CalculateBitShift = 0x13905; + PHY_SetBBReg_8711B = 0x1391d; + PHY_QueryBBReg_8711B = 0x13921; + ROM_odm_QueryRxPwrPercentage = 0x13925; + ROM_odm_EVMdbToPercentage = 0x13931; + ROM_odm_SignalScaleMapping_8711B = 0x13935; + ROM_odm_FalseAlarmCounterStatistics = 0x13a11; + ROM_odm_SetEDCCAThreshold = 0x13d39; + ROM_odm_SetTRxMux = 0x13d61; + ROM_odm_SetCrystalCap = 0x13d89; + ROM_odm_GetDefaultCrytaltalCap = 0x13ded; + ROM_ODM_CfoTrackingReset = 0x13dfd; + ROM_odm_CfoTrackingFlow = 0x13e21; + rtw_get_bit_value_from_ieee_value = 0x14045; + rtw_is_cckrates_included = 0x14071; + rtw_is_cckratesonly_included = 0x140a5; + rtw_check_network_type = 0x140cd; + rtw_set_fixed_ie = 0x14155; + rtw_set_ie = 0x14175; + rtw_get_ie = 0x141a1; + rtw_set_supported_rate = 0x141b5; + rtw_get_rateset_len = 0x14229; + rtw_get_wpa_ie = 0x14245; + rtw_get_wpa2_ie = 0x142d1; + rtw_get_wpa_cipher_suite = 0x142e5; + rtw_get_wpa2_cipher_suite = 0x1434d; + rtw_parse_wpa_ie = 0x143b5; + rtw_parse_wpa2_ie = 0x14481; + rtw_get_sec_ie = 0x14535; + rtw_get_wps_ie = 0x145e5; + rtw_get_wps_attr = 0x14659; + rtw_get_wps_attr_content = 0x146f1; + rtw_ieee802_11_parse_elems = 0x14739; + str_2char2num = 0x14909; + key_2char2num = 0x14925; + convert_ip_addr = 0x1493d; + rom_psk_PasswordHash = 0x14a21; + rom_psk_CalcGTK = 0x14a59; + rom_psk_CalcPTK = 0x14ae9; + _htons_rom = 0x14bdd; + _ntohs_rom = 0x14be5; + _htonl_rom = 0x14bed; + _ntohl_rom = 0x14bf1; + Message_ReplayCounter_OC2LI = 0x14bf5; + Message_EqualReplayCounter = 0x14c35; + Message_SmallerEqualReplayCounter = 0x14c6d; + Message_LargerReplayCounter = 0x14cad; + Message_setReplayCounter = 0x14ce5; + INCLargeInteger = 0x14d15; + INCOctet16_INTEGER = 0x14d25; + INCOctet32_INTEGER = 0x14d8d; + SetEAPOL_KEYIV = 0x14df5; + CheckMIC = 0x14e89; + CalcMIC = 0x14f29; + DecWPA2KeyData_rom = 0x14f9d; + DecGTK = 0x15055; + GetRandomBuffer = 0x15119; + GenNonce = 0x15181; + ClientConstructEAPOL_2Of4Way = 0x151c5; + ClientConstructEAPOL_4Of4Way = 0x152cd; + ClientConstructEAPOL_2Of2Way = 0x1537d; + ClientConstructEAPOL_MICOf2Way = 0x15459; + psk_strip_rsn_pairwise = 0x1552d; + psk_strip_wpa_pairwise = 0x155c1; + wep_80211_encrypt = 0x1587d; + wep_80211_decrypt = 0x158e1; + tkip_micappendbyte = 0x15975; + rtw_secmicsetkey = 0x159b9; + rtw_secmicappend = 0x159f9; + rtw_secgetmic = 0x15a15; + rtw_seccalctkipmic = 0x15a89; + tkip_phase1 = 0x15b7d; + tkip_phase2 = 0x15ce5; + tkip_80211_encrypt = 0x15f01; + tkip_80211_decrypt = 0x15f91; + aes1_encrypt = 0x16055; + aesccmp_construct_mic_iv = 0x1625d; + aesccmp_construct_mic_header1 = 0x162b1; + aesccmp_construct_mic_header2 = 0x16321; + aesccmp_construct_ctr_preload = 0x163a5; + aes_80211_encrypt = 0x16429; + aes_80211_decrypt = 0x167f9; + cckrates_included = 0x16c39; + cckratesonly_included = 0x16c7d; + networktype_to_raid_ex_rom = 0x16ca9; + judge_network_type_rom = 0x16cf5; + ratetbl_val_2wifirate = 0x16d89; + is_basicrate_rom = 0x16d9d; + ratetbl2rateset_rom = 0x16dd5; + get_rate_set_rom = 0x16e3d; + UpdateBrateTbl_rom = 0x16e71; + UpdateBrateTblForSoftAP = 0x16ec9; + write_cam_rom = 0x16f0d; + HT_caps_handler_rom = 0x16fc1; + wifirate2_ratetbl_inx = 0x17015; + update_basic_rate = 0x170bd; + update_supported_rate = 0x170f5; + update_MCS_rate = 0x17125; + get_highest_rate_idx = 0x17131; + _sha1_process_message_block = 0x1714d; + _sha1_pad_message = 0x172d1; + rt_sha1_init = 0x1736d; + rt_sha1_update = 0x173b1; + rt_sha1_finish = 0x17429; + rt_hmac_sha1 = 0x17489; + rom_aes_128_cbc_encrypt = 0x175e5; + rom_aes_128_cbc_decrypt = 0x17669; + rom_rijndaelKeySetupEnc = 0x176ed; + rom_aes_decrypt_init = 0x177c1; + rom_aes_internal_decrypt = 0x17899; + rom_aes_decrypt_deinit = 0x17bdd; + rom_aes_encrypt_init = 0x17be9; + rom_aes_internal_encrypt = 0x17c01; + rom_aes_encrypt_deinit = 0x17f81; + bignum_init = 0x1963d; + bignum_deinit = 0x19665; + bignum_get_unsigned_bin_len = 0x19685; + bignum_get_unsigned_bin = 0x19689; + bignum_set_unsigned_bin = 0x19741; + bignum_cmp = 0x197f9; + bignum_cmp_d = 0x197fd; + bignum_add = 0x19825; + bignum_sub = 0x19835; + bignum_mul = 0x19845; + bignum_exptmod = 0x19855; + WPS_realloc = 0x19879; + os_zalloc = 0x198bd; + rom_hmac_sha256_vector = 0x198e1; + rom_hmac_sha256 = 0x199e1; + rom_sha256_vector = 0x19b3d; + CRYPTO_chacha_20 = 0x19d45; + rom_ed25519_gen_keypair = 0x1a1bd; + rom_ed25519_gen_signature = 0x1a1c1; + rom_ed25519_verify_signature = 0x1a1d9; + rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9; + rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1; + rom_ed25519_ge_p3_tobytes = 0x1d43d; + rom_ed25519_ge_scalarmult_base = 0x1d489; + rom_ed25519_ge_tobytes = 0x1d64d; + rom_ed25519_crypto_sign_seed_keypair = 0x1d699; + rom_ed25519_crypto_sign_verify_detached = 0x1d6f1; + rom_ed25519_sc_muladd = 0x1d9e5; + rom_ed25519_sc_reduce = 0x24175; + rom_ed25519_crypto_sign_detached = 0x26c25; + CRYPTO_poly1305_init = 0x270dd; + CRYPTO_poly1305_update = 0x271b5; + CRYPTO_poly1305_finish = 0x27245; + rom_sha512_starts = 0x28511; + rom_sha512_update = 0x28659; + rom_sha512_finish = 0x28661; + rom_sha512 = 0x288a9; + rom_sha512_hmac_starts = 0x288e1; + rom_sha512_hmac_update = 0x289a5; + rom_sha512_hmac_finish = 0x289ad; + rom_sha512_hmac_reset = 0x289fd; + rom_sha512_hmac = 0x28a19; + rom_sha512_hkdf = 0x28a51; + aes_test_alignment_detection = 0x28b59; + aes_mode_reset = 0x28bbd; + aes_ecb_encrypt = 0x28bc9; + aes_ecb_decrypt = 0x28c05; + aes_cbc_encrypt = 0x28c41; + aes_cbc_decrypt = 0x28dad; + aes_cfb_encrypt = 0x28f49; + aes_cfb_decrypt = 0x2920d; + aes_ofb_crypt = 0x294d5; + aes_ctr_crypt = 0x29769; + aes_encrypt_key128 = 0x29a79; + aes_encrypt_key192 = 0x29a95; + aes_encrypt_key256 = 0x29ab1; + aes_encrypt_key = 0x29ad1; + aes_decrypt_key128 = 0x29b41; + aes_decrypt_key192 = 0x29b5d; + aes_decrypt_key256 = 0x29b79; + aes_decrypt_key = 0x29b99; + aes_init = 0x29c09; + curve25519_donna = 0x2a939; + __rtl_dtoa_r_v1_00 = 0x2b7f1; + __rtl_ltoa_v1_00 = 0x2c7f9; + __rtl_ultoa_v1_00 = 0x2c885; + __rtl_dtoi_v1_00 = 0x2c8ed; + __rtl_dtoi64_v1_00 = 0x2c96d; + __rtl_dtoui_v1_00 = 0x2ca09; + __rtl_ftol_v1_00 = 0x2ca11; + __rtl_itof_v1_00 = 0x2ca75; + __rtl_itod_v1_00 = 0x2cb05; + __rtl_i64tod_v1_00 = 0x2cb71; + __rtl_uitod_v1_00 = 0x2cc4d; + __rtl_ftod_v1_00 = 0x2cd29; + __rtl_dtof_v1_00 = 0x2cde1; + __rtl_uitof_v1_00 = 0x2ce75; + __rtl_fadd_v1_00 = 0x2cf59; + __rtl_fsub_v1_00 = 0x2d259; + __rtl_fmul_v1_00 = 0x2d565; + __rtl_fdiv_v1_00 = 0x2d695; + __rtl_dadd_v1_00 = 0x2d809; + __rtl_dsub_v1_00 = 0x2de49; + __rtl_dmul_v1_00 = 0x2e4a1; + __rtl_ddiv_v1_00 = 0x2e7dd; + __rtl_dcmpeq_v1_00 = 0x2ed71; + __rtl_dcmplt_v1_00 = 0x2eded; + __rtl_dcmpgt_v1_00 = 0x2ee85; + __rtl_dcmple_v1_00 = 0x2ef95; + __rtl_fcmplt_v1_00 = 0x2f0a9; + __rtl_fcmpgt_v1_00 = 0x2f105; + __rtl_fpclassifyd = 0x2f1ad; + __rtl_close_v1_00 = 0x2f205; + __rtl_fstat_v1_00 = 0x2f219; + __rtl_isatty_v1_00 = 0x2f22d; + __rtl_lseek_v1_00 = 0x2f23d; + __rtl_open_v1_00 = 0x2f251; + __rtl_read_v1_00 = 0x2f265; + __rtl_write_v1_00 = 0x2f279; + __rtl_sbrk_v1_00 = 0x2f28d; + __rom_mallocr_init_v1_00 = 0x2f29d; + __rtl_free_r_v1_00 = 0x2f309; + __rtl_malloc_r_v1_00 = 0x2f521; + __rtl_realloc_r_v1_00 = 0x2f9f5; + __rtl_memalign_r_v1_00 = 0x2fdb5; + __rtl_valloc_r_v1_00 = 0x2fe81; + __rtl_pvalloc_r_v1_00 = 0x2fe8d; + __rtl_calloc_r_v1_00 = 0x2fea1; + __rtl_cfree_r_v1_00 = 0x2ff05; + __rtl_cos_f32_v1_00 = 0x2ff15; + __rtl_sin_f32_v1_00 = 0x300e9; + __rtl_fabs_v1_00 = 0x302ad; + __rtl_fabsf_v1_00 = 0x302b5; + __rtl_memchr_v1_00 = 0x302bd; + __rtl_memcmp_v1_00 = 0x30351; + __rtl_memcpy_v1_00 = 0x303b5; + __rtl_memmove_v1_00 = 0x3045d; + __rtl_memset_v1_00 = 0x30525; + __rtl_Balloc_v1_00 = 0x3061d; + __rtl_Bfree_v1_00 = 0x3066d; + __rtl_i2b_v1_00 = 0x30681; + __rtl_multadd_v1_00 = 0x30695; + __rtl_mult_v1_00 = 0x30721; + __rtl_pow5mult_v1_00 = 0x30855; + __rtl_hi0bits_v1_00 = 0x308f5; + __rtl_d2b_v1_00 = 0x30935; + __rtl_lshift_v1_00 = 0x309ed; + __rtl_cmp_v1_00 = 0x30a99; + __rtl_diff_v1_00 = 0x30ae1; + __rtl_sread_v1_00 = 0x30bb5; + __rtl_seofread_v1_00 = 0x30c01; + __rtl_swrite_v1_00 = 0x30c05; + __rtl_sseek_v1_00 = 0x30c75; + __rtl_sclose_v1_00 = 0x30cc1; + __rtl_sbrk_r_v1_00 = 0x30ced; + __rtl_strcat_v1_00 = 0x30d15; + __rtl_strchr_v1_00 = 0x30d59; + __rtl_strcmp_v1_00 = 0x30e25; + __rtl_strcpy_v1_00 = 0x30e99; + __rtl_strlen_v1_00 = 0x30ee5; + __rtl_strncat_v1_00 = 0x30f39; + __rtl_strncmp_v1_00 = 0x30f95; + __rtl_strncpy_v1_00 = 0x3102d; + __rtl_strsep_v1_00 = 0x31095; + __rtl_strstr_v1_00 = 0x3136d; + __rtl_strtok_v1_00 = 0x315a5; + __rtl__strtok_r_v1_00 = 0x315b5; + __rtl_strtok_r_v1_00 = 0x31619; + __rtl_fflush_r_v1_00 = 0x31ae9; + __rtl_vfprintf_r_v1_00 = 0x31f99; + polarssl_aes_init = 0x335b9; + aes_free = 0x335c9; + aes_setkey_enc = 0x335dd; + aes_setkey_dec = 0x33829; + aes_crypt_ecb = 0x339a1; + aes_crypt_cbc = 0x343d1; + aes_crypt_cfb128 = 0x34649; + aes_crypt_cfb8 = 0x346c9; + aes_crypt_ctr = 0x3474d; + arc4_init = 0x347b1; + arc4_free = 0x347bd; + arc4_setup = 0x347d1; + arc4_crypt = 0x3481d; + asn1_get_len = 0x34861; + asn1_get_tag = 0x34901; + asn1_get_bool = 0x34929; + asn1_get_int = 0x3495d; + asn1_get_mpi = 0x349a9; + asn1_get_bitstring = 0x349d1; + asn1_get_bitstring_null = 0x34a19; + asn1_get_sequence_of = 0x34a4d; + asn1_get_alg = 0x34ad1; + asn1_get_alg_null = 0x34b65; + asn1_free_named_data = 0x34ba5; + asn1_free_named_data_list = 0x34bcd; + asn1_find_named_data = 0x34bf5; + asn1_write_len = 0x34c25; + asn1_write_tag = 0x34c8d; + asn1_write_raw_buffer = 0x34ca9; + asn1_write_mpi = 0x34ccd; + asn1_write_null = 0x34d41; + asn1_write_oid = 0x34d6d; + asn1_write_algorithm_identifier = 0x34dc5; + asn1_write_bool = 0x34e21; + asn1_write_int = 0x34e65; + asn1_write_printable_string = 0x34ecd; + asn1_write_ia5_string = 0x34f25; + asn1_write_bitstring = 0x34f7d; + asn1_write_octet_string = 0x34fe5; + asn1_store_named_data = 0x3503d; + base64_encode = 0x35111; + base64_decode = 0x3523d; + mpi_init = 0x35e09; + mpi_free = 0x35e19; + mpi_grow = 0x35e55; + mpi_shrink = 0x35e79; + mpi_copy = 0x35f21; + mpi_swap = 0x35fa1; + mpi_safe_cond_assign = 0x35fcd; + mpi_safe_cond_swap = 0x36069; + mpi_lset = 0x3610d; + mpi_get_bit = 0x3614d; + mpi_set_bit = 0x3616d; + mpi_lsb = 0x361d5; + mpi_msb = 0x36215; + mpi_size = 0x36261; + mpi_read_binary = 0x3626d; + mpi_write_binary = 0x362f9; + mpi_shift_l = 0x36341; + mpi_shift_r = 0x363f1; + mpi_cmp_abs = 0x36475; + mpi_cmp_mpi = 0x36619; + mpi_cmp_int = 0x366f1; + mpi_add_abs = 0x3671d; + mpi_sub_abs = 0x3680d; + mpi_add_mpi = 0x3689d; + mpi_sub_mpi = 0x368ed; + mpi_add_int = 0x3693d; + mpi_sub_int = 0x36969; + mpi_mul_mpi = 0x36995; + mpi_read_string = 0x36ac5; + mpi_mul_int = 0x36c45; + mpi_div_mpi = 0x36c61; + mpi_div_int = 0x370ed; + mpi_mod_mpi = 0x37119; + mpi_mod_int = 0x3717d; + mpi_write_string = 0x3722d; + mpi_exp_mod = 0x37395; + mpi_gcd = 0x37915; + mpi_fill_random = 0x37a39; + mpi_inv_mod = 0x37c4d; + mpi_is_prime = 0x37f15; + mpi_gen_prime = 0x37f71; + ctr_drbg_free = 0x38285; + ctr_drbg_set_prediction_resistance = 0x382a1; + ctr_drbg_set_entropy_len = 0x382a5; + ctr_drbg_set_reseed_interval = 0x382a9; + ctr_drbg_update = 0x382ad; + ctr_drbg_reseed = 0x382c9; + ctr_drbg_init_entropy_len = 0x38341; + ctr_drbg_init = 0x38399; + ctr_drbg_random_with_add = 0x383ad; + ctr_drbg_random = 0x38469; + des_init = 0x388a5; + des_free = 0x388b1; + des3_init = 0x388c5; + des3_free = 0x388d5; + des_key_set_parity = 0x388e9; + des_key_check_key_parity = 0x38909; + des_key_check_weak = 0x38939; + des_setkey_enc = 0x38965; + des_setkey_dec = 0x3898d; + des3_set2key_enc = 0x389d9; + des3_set2key_dec = 0x38a25; + des3_set3key_enc = 0x38a71; + des3_set3key_dec = 0x38ab1; + des_crypt_ecb = 0x38af1; + des_crypt_cbc = 0x38d09; + des3_crypt_ecb = 0x38f99; + des3_crypt_cbc = 0x39401; + dhm_init = 0x39729; + dhm_read_params = 0x39731; + dhm_make_params = 0x3978d; + dhm_read_public = 0x398c1; + dhm_make_public = 0x398e9; + dhm_calc_secret = 0x399ad; + dhm_free = 0x39ba1; + dhm_parse_dhm = 0x39c01; + ecdh_gen_public = 0x39cc5; + ecdh_compute_shared = 0x39cc9; + ecdh_init = 0x39d2d; + ecdh_free = 0x39d39; + ecdh_make_params = 0x39d81; + ecdh_read_params = 0x39e05; + ecdh_get_params = 0x39e2d; + ecdh_make_public = 0x39e79; + ecdh_read_public = 0x39ed1; + ecdh_calc_secret = 0x39f01; + ecdsa_sign = 0x3a041; + ecdsa_sign_det = 0x3a1c5; + ecdsa_verify = 0x3a2a9; + ecdsa_write_signature = 0x3a431; + ecdsa_write_signature_det = 0x3a46d; + ecdsa_read_signature = 0x3a4a5; + ecdsa_genkey = 0x3a531; + ecdsa_init = 0x3a565; + ecdsa_free = 0x3a591; + ecdsa_from_keypair = 0x3a5bd; + ecp_curve_list = 0x3aee5; + ecp_curve_info_from_grp_id = 0x3aeed; + ecp_curve_info_from_tls_id = 0x3af0d; + ecp_curve_info_from_name = 0x3af31; + ecp_point_init = 0x3af61; + ecp_group_init = 0x3af81; + ecp_keypair_init = 0x3af8d; + ecp_point_free = 0x3afb1; + ecp_group_free = 0x3afd1; + ecp_keypair_free = 0x3b03d; + ecp_copy = 0x3b05d; + ecp_group_copy = 0x3b08d; + ecp_set_zero = 0x3b095; + ecp_is_zero = 0x3ba61; + ecp_point_read_string = 0x3ba75; + ecp_point_write_binary = 0x3baa5; + ecp_point_read_binary = 0x3bb4d; + ecp_tls_read_point = 0x3bbc1; + ecp_tls_write_point = 0x3bbf5; + ecp_group_read_string = 0x3bc25; + ecp_tls_read_group = 0x3bc95; + ecp_tls_write_group = 0x3bcf1; + ecp_add = 0x3bd39; + ecp_sub = 0x3bd65; + ecp_check_pubkey = 0x3bddd; + ecp_check_privkey = 0x3bf8d; + ecp_mul = 0x3bff5; + ecp_gen_keypair = 0x3c565; + ecp_gen_key = 0x3c669; + ecp_use_known_dp = 0x3d741; + hmac_drbg_update = 0x3daa9; + hmac_drbg_init_buf = 0x3db41; + hmac_drbg_reseed = 0x3db91; + hmac_drbg_init = 0x3dc09; + hmac_drbg_set_prediction_resistance = 0x3dc81; + hmac_drbg_set_entropy_len = 0x3dc85; + hmac_drbg_set_reseed_interval = 0x3dc89; + hmac_drbg_random_with_add = 0x3dc8d; + hmac_drbg_random = 0x3dd4d; + hmac_drbg_free = 0x3dd61; + md_list = 0x3dd7d; + md_info_from_string = 0x3dd85; + md_info_from_type = 0x3de59; + md_init = 0x3de9d; + md_free = 0x3dea5; + md_init_ctx = 0x3dec5; + md_free_ctx = 0x3defd; + md_starts = 0x3df09; + md_update = 0x3df29; + md_finish = 0x3df49; + md = 0x3df69; + md_file = 0x3df89; + md_hmac_starts = 0x3dfa1; + md_hmac_update = 0x3dfc1; + md_hmac_finish = 0x3dfe1; + md_hmac_reset = 0x3e001; + md_hmac = 0x3e021; + md_process = 0x3e049; + md5_init = 0x3e301; + md5_free = 0x3e309; + md5_starts = 0x3e31d; + md5_process = 0x3e34d; + md5_update = 0x3ed51; + md5_finish = 0x3ed59; + md5 = 0x3ee11; + md5_hmac_starts = 0x3ee75; + md5_hmac_update = 0x3ef51; + md5_hmac_finish = 0x3ef59; + md5_hmac_reset = 0x3efbd; + md5_hmac = 0x3eff1; + oid_get_attr_short_name = 0x3f071; + oid_get_x509_ext_type = 0x3f0b1; + oid_get_extended_key_usage = 0x3f0f1; + oid_get_sig_alg_desc = 0x3f131; + oid_get_sig_alg = 0x3f149; + oid_get_oid_by_sig_alg = 0x3f169; + oid_get_pk_alg = 0x3f1a1; + oid_get_oid_by_pk_alg = 0x3f1e1; + oid_get_ec_grp = 0x3f219; + oid_get_oid_by_ec_grp = 0x3f259; + oid_get_cipher_alg = 0x3f291; + oid_get_md_alg = 0x3f2d1; + oid_get_oid_by_md = 0x3f311; + oid_get_pkcs12_pbe_alg = 0x3f349; + oid_get_numeric_string = 0x3f391; + pem_init = 0x3f649; + pem_read_buffer = 0x3f651; + pem_free = 0x3f955; + pem_write_buffer = 0x3f97d; + pk_init = 0x3fa81; + pk_free = 0x3fa8d; + pk_info_from_type = 0x3faad; + pk_init_ctx = 0x3fae1; + pk_init_ctx_rsa_alt = 0x3fb11; + pk_can_do = 0x3fb69; + pk_verify = 0x3fb79; + pk_verify_ext = 0x3fbc9; + pk_sign = 0x3fc8d; + pk_decrypt = 0x3fce9; + pk_encrypt = 0x3fd15; + pk_get_size = 0x3fd41; + pk_debug = 0x3fd51; + pk_get_name = 0x3fd79; + pk_get_type = 0x3fd8d; + pk_write_pubkey = 0x40181; + pk_write_pubkey_der = 0x40201; + pk_write_key_der = 0x402dd; + pk_write_pubkey_pem = 0x404f5; + pk_write_key_pem = 0x40545; + rsa_init = 0x4065d; + rsa_set_padding = 0x40679; + rsa_check_pubkey = 0x40685; + rsa_check_privkey = 0x406e1; + rsa_public = 0x409a5; + rsa_private = 0x40a25; + rsa_rsaes_oaep_encrypt = 0x40c29; + rsa_rsaes_pkcs1_v15_encrypt = 0x40d31; + rsa_pkcs1_encrypt = 0x40e19; + rsa_rsaes_oaep_decrypt = 0x40e59; + rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd; + rsa_pkcs1_decrypt = 0x410c1; + rsa_rsassa_pss_sign = 0x4110d; + rsa_rsassa_pkcs1_v15_sign = 0x41271; + rsa_pkcs1_sign = 0x41389; + rsa_rsassa_pss_verify_ext = 0x413c9; + rsa_rsassa_pss_verify = 0x41575; + rsa_rsassa_pkcs1_v15_verify = 0x415a5; + rsa_pkcs1_verify = 0x41709; + rsa_free = 0x41765; + rsa_gen_key = 0x417d5; + rsa_copy = 0x4198d; + sha1_init = 0x41a9d; + sha1_free = 0x41aa5; + sha1_starts = 0x41ab9; + sha1_process = 0x41aed; + sha1_update = 0x42e15; + sha1_finish = 0x42e1d; + sha1 = 0x42ee5; + sha1_hmac_starts = 0x42f51; + sha1_hmac_update = 0x43039; + sha1_hmac_finish = 0x43041; + sha1_hmac_reset = 0x430b5; + sha1_hmac = 0x430f1; + sha256_init = 0x43139; + sha256_free = 0x43141; + sha256_starts = 0x43155; + sha256_process = 0x431e5; + sha256_update = 0x4513d; + sha256_finish = 0x45145; + sha256 = 0x4524d; + sha256_hmac_starts = 0x45325; + sha256_hmac_update = 0x45475; + sha256_hmac_finish = 0x4547d; + sha256_hmac_reset = 0x45569; + sha256_hmac = 0x45601; + sha512_init = 0x45651; + sha512_free = 0x4565d; + sha512_starts = 0x45671; + sha512_process = 0x457b9; + sha512_update = 0x46879; + sha512_finish = 0x46881; + sha512 = 0x46ac9; + sha512_hmac_starts = 0x46b11; + sha512_hmac_update = 0x46bd9; + sha512_hmac_finish = 0x46be1; + sha512_hmac_reset = 0x46c35; + sha512_hmac = 0x46c51; + UartLogRomCmdTable = 0x46ca0; + XTAL_CLK = 0x46e10; + CpkClkTbl_FPAG = 0x46e50; + CpkClkTbl_ASIC = 0x46e68; + ROM_IMG1_VALID_PATTEN = 0x46e90; + __AES_rcon = 0x46e98; + __AES_Te4 = 0x46ec0; + SpicCalibrationPattern = 0x472c0; + NEW_CALIBREATION_DIV = 0x472c8; + NEW_CALIBREATION_DATA = 0x472e4; + GDMA_IrqNum = 0x47344; + I2C_DEV_TABLE = 0x47350; + spi_clk_pin = 0x47370; + SPI_DEV_TABLE = 0x47374; + PWM_GDMA_HSx = 0x47394; + TIM_DMA_CCx = 0x473ac; + TIM_IT_CCx = 0x473c4; + TIMx = 0x473dc; + TIMx_irq = 0x473f4; + BAUDRATE_TABLE_40M = 0x4740c; + UART_DEV_TABLE = 0x475bc; + RTW_WPA_OUI_TYPE = 0x4b270; + WPA_CIPHER_SUITE_NONE = 0x4b274; + WPA_CIPHER_SUITE_WEP40 = 0x4b278; + WPA_CIPHER_SUITE_TKIP = 0x4b27c; + WPA_CIPHER_SUITE_CCMP = 0x4b280; + WPA_CIPHER_SUITE_WEP104 = 0x4b284; + RSN_CIPHER_SUITE_NONE = 0x4b288; + RSN_CIPHER_SUITE_WEP40 = 0x4b28c; + RSN_CIPHER_SUITE_TKIP = 0x4b290; + RSN_CIPHER_SUITE_CCMP = 0x4b294; + RSN_CIPHER_SUITE_WEP104 = 0x4b298; + RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8; + RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac; + RSN_VERSION_BSD = 0x4b2b0; + rom_e_rtw_msgp_str_ = 0x4b2b4; + rtw_basic_rate_mix = 0x4b9a8; + rtw_basic_rate_ofdm = 0x4b9b0; + rtw_basic_rate_cck = 0x4b9b4; + REALTEK_96B_IE = 0x4b9b8; + AIRGOCAP_OUI = 0x4b9c0; + REALTEK_OUI = 0x4b9c4; + RALINK_OUI = 0x4b9c8; + MARVELL_OUI = 0x4b9cc; + CISCO_OUI = 0x4b9d0; + BROADCOM_OUI3 = 0x4b9d4; + BROADCOM_OUI2 = 0x4b9d8; + BROADCOM_OUI1 = 0x4b9dc; + ARTHEROS_OUI2 = 0x4b9e0; + ARTHEROS_OUI1 = 0x4b9e4; + rom_wps_rcons = 0x4b9e8; + rom_wps_Te0 = 0x4b9f4; + rom_wps_Td4s = 0x4bdf4; + rom_wps_Td0 = 0x4bef4; + sha512_info = 0x5850c; + sha384_info = 0x5854c; + sha256_info = 0x5858c; + sha224_info = 0x585cc; + sha1_info = 0x5860c; + md5_info = 0x5864c; + rsa_alt_info = 0x58d28; + ecdsa_info = 0x58d54; + eckeydh_info = 0x58d80; + eckey_info = 0x58dac; + rsa_info = 0x58dd8; + __rom_bss_start__ = 0x10000000; + NewVectorTable = 0x10000000; + UserIrqFunTable = 0x10000100; + UserIrqDataTable = 0x10000200; + ConfigDebugClose = 0x10000300; + CfgSysDebugWarn = 0x10000304; + CfgSysDebugInfo = 0x10000308; + CfgSysDebugErr = 0x1000030c; + ConfigDebugWarn = 0x10000310; + ConfigDebugInfo = 0x10000314; + ConfigDebugErr = 0x10000318; + sector_addr = 0x1000031c; + _rtl_impure_ptr = 0x10000338; + ArgvArray = 0x1000033c; + pUartLogCtl = 0x10000364; + UartLogBuf = 0x10000368; + UartLogCtl = 0x100003e8; + UartLogHistoryBuf = 0x10000408; + NCO32K_Enable = 0x10000684; + g_rtl_cipherEngine = 0x100006a0; + DONGLE_InitStruct = 0x10000ba0; + EFUSE_MAP = 0x10000ba4; + USOC_BOOT_TXBD = 0x10000da4; + USOC_BOOT_RXBD = 0x10000db4; + USB_RXBuff = 0x10000dc4; + USB_TXBuff = 0x10000dcc; + ADC_AnaparAd = 0x10000dd4; + flash_init_para = 0x10000dec; + NEW_CALIBREATION_END = 0x10000e44; + GDMA_Reg = 0x10000e4c; + PortA_IrqHandler = 0x10000e50; + PortA_IrqData = 0x10000ed0; + IC_FS_SCL_HCNT_TRIM = 0x10000f50; + IC_FS_SCL_LCNT_TRIM = 0x10000f54; + I2C_SLAVEWRITE_PATCH = 0x10000f58; + i2s_cur_tx_page = 0x10000f5c; + i2s_cur_rx_page = 0x10000f60; + i2s_page_num = 0x10000f64; + i2s_txpage_entry = 0x10000f68; + i2s_rxpage_entry = 0x10000f78; + TXBDAddrAligned = 0x10000f88; + H2C_Buff = 0x10000f90; + SPI_RECV_Buff = 0x10000f94; + spi_boot_recv_done = 0x10000f98; + UART_StateRx = 0x10000f9c; + UART_StateTx = 0x10000fa8; + xMCtrl = 0x10000fb8; + XComUARTx = 0x10000fc4; + FalseAlmCnt = 0x10000fc8; + ROMInfo = 0x10001008; + DM_CfoTrack = 0x10001020; + rom_wlan_ram_map = 0x10001048; + rom_libgloss_ram_map = 0x10001050; + __rtl_errno = 0x100014b4; + rom_ssl_ram_map = 0x100014b8; + __rom_bss_end__ = 0x100014f8; +} \ No newline at end of file diff --git a/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip1.ld b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip1.ld new file mode 100644 index 0000000..bbd3930 --- /dev/null +++ b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip1.ld @@ -0,0 +1,157 @@ + + +ENTRY(Reset_Handler) + +INCLUDE "export-rom_symbol_v01.txt" + +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ + ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ + BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ + BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */ + MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ + RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ + + XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ + XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ + XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ + XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */ + XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */ +} + + + +SECTIONS +{ + .rom.text : { } > ROM + .rom.rodata : { } > ROM + .hal.rom.bss : { } > ROMBSS_RAM + + /* image1 entry, this section should in RAM and fixed address for ROM */ + .ram_image1.entry : + { + __ram_image1_text_start__ = .; + __ram_start_table_start__ = .; + KEEP(*(SORT(.image1.entry.data*))) + __ram_start_table_end__ = .; + + __image1_validate_code__ = .; + KEEP(*(.image1.validate.rodata*)) + KEEP(*(.image1.export.symb*)) + } > BOOTLOADER_RAM + + /* Add . to assign the start address of the section */ + /* to prevent the change of the start address by ld doing section alignment */ + .ram_image1.text . : + { + /* image1 text */ + *(.boot.ram.text*) + *(.boot.rodata*) + } > BOOTLOADER_RAM + + .ram_image1.data . : + { + __ram_image1_data_start__ = .; + KEEP(*(.boot.ram.data*)) + __ram_image1_data_end__ = .; + + __ram_image1_text_end__ = .; + } > BOOTLOADER_RAM + + .ram_image1.bss . : + { + __image1_bss_start__ = .; + KEEP(*(.boot.ram.bss*)) + KEEP(*(.boot.ram.end.bss*)) + __image1_bss_end__ = .; + } > BOOTLOADER_RAM + + .ram_image2.entry : + { + __ram_image2_text_start__ = .; + __image2_entry_func__ = .; + KEEP(*(SORT(.image2.entry.data*))) + + __image2_validate_code__ = .; + KEEP(*(.image2.validate.rodata*)) + + } > BD_RAM + + .ram_image2.text : + { + KEEP(*(.image2.ram.text*)) + } > BD_RAM + + .ram_image2.data : + { + __data_start__ = .; + *(.data*) + __data_end__ = .; + __ram_image2_text_end__ = .; + . = ALIGN(16); + } > BD_RAM + + .ram_image2.bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + } > BD_RAM + + .ram_image2.skb.bss : + { + *(.bdsram.data*) + __bss_end__ = .; + } > BD_RAM + + .ram_heap.data : + { + *(.bfsram.data*) + *(.heap.stdlib*) + + } > BD_RAM + + .ram_rdp.text : + { + __rom_top_4k_start_ = .; + __rdp_text_start__ = .; + KEEP(*(.rdp.ram.text*)) + KEEP(*(.rdp.ram.data*)) + __rdp_text_end__ = .; + . = ALIGN(16); + + } > RDP_RAM + + .xip_image1.text : + { + __flash_boot_text_start__ = .; + + *(.flashboot.text*) + + __flash_boot_text_end__ = .; + + . = ALIGN(16); + } > XIPBOOT + + .xip_image2.text : + { + __flash_text_start__ = .; + + *(.img2_custom_signature*) + + *(.text*) + *(.rodata*) + *(.debug_trace*) + + __flash_text_end__ = .; + + . = ALIGN (16); + } > XIP1 +} + +SECTIONS +{ + /* Bootloader symbol list */ + boot_export_symbol = 0x10002020; +} diff --git a/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip1_2M.ld b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip1_2M.ld new file mode 100644 index 0000000..c95cd66 --- /dev/null +++ b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip1_2M.ld @@ -0,0 +1,157 @@ + + +ENTRY(Reset_Handler) + +INCLUDE "export-rom_symbol_v01.txt" + +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ + ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ + BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ + BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x39000 /* MAIN RAM: 228 */ + MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ + RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ + + XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ + XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ + XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ + XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 2*468k, 32 Bytes resvd for header */ + XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 2*468k, 32 Bytes resvd for header */ +} + + + +SECTIONS +{ + .rom.text : { } > ROM + .rom.rodata : { } > ROM + .hal.rom.bss : { } > ROMBSS_RAM + + /* image1 entry, this section should in RAM and fixed address for ROM */ + .ram_image1.entry : + { + __ram_image1_text_start__ = .; + __ram_start_table_start__ = .; + KEEP(*(SORT(.image1.entry.data*))) + __ram_start_table_end__ = .; + + __image1_validate_code__ = .; + KEEP(*(.image1.validate.rodata*)) + KEEP(*(.image1.export.symb*)) + } > BOOTLOADER_RAM + + /* Add . to assign the start address of the section */ + /* to prevent the change of the start address by ld doing section alignment */ + .ram_image1.text . : + { + /* image1 text */ + *(.boot.ram.text*) + *(.boot.rodata*) + } > BOOTLOADER_RAM + + .ram_image1.data . : + { + __ram_image1_data_start__ = .; + KEEP(*(.boot.ram.data*)) + __ram_image1_data_end__ = .; + + __ram_image1_text_end__ = .; + } > BOOTLOADER_RAM + + .ram_image1.bss . : + { + __image1_bss_start__ = .; + KEEP(*(.boot.ram.bss*)) + KEEP(*(.boot.ram.end.bss*)) + __image1_bss_end__ = .; + } > BOOTLOADER_RAM + + .ram_image2.entry : + { + __ram_image2_text_start__ = .; + __image2_entry_func__ = .; + KEEP(*(SORT(.image2.entry.data*))) + + __image2_validate_code__ = .; + KEEP(*(.image2.validate.rodata*)) + + } > BD_RAM + + .ram_image2.text : + { + KEEP(*(.image2.ram.text*)) + } > BD_RAM + + .ram_image2.data : + { + __data_start__ = .; + *(.data*) + __data_end__ = .; + __ram_image2_text_end__ = .; + . = ALIGN(16); + } > BD_RAM + + .ram_image2.bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + } > BD_RAM + + .ram_image2.skb.bss : + { + *(.bdsram.data*) + __bss_end__ = .; + } > BD_RAM + + .ram_heap.data : + { + *(.bfsram.data*) + *(.heap.stdlib*) + + } > BD_RAM + + .ram_rdp.text : + { + __rom_top_4k_start_ = .; + __rdp_text_start__ = .; + KEEP(*(.rdp.ram.text*)) + KEEP(*(.rdp.ram.data*)) + __rdp_text_end__ = .; + . = ALIGN(16); + + } > RDP_RAM + + .xip_image1.text : + { + __flash_boot_text_start__ = .; + + *(.flashboot.text*) + + __flash_boot_text_end__ = .; + + . = ALIGN(16); + } > XIPBOOT + + .xip_image2.text : + { + __flash_text_start__ = .; + + *(.img2_custom_signature*) + + *(.text*) + *(.rodata*) + *(.debug_trace*) + + __flash_text_end__ = .; + + . = ALIGN (16); + } > XIP1 +} + +SECTIONS +{ + /* Bootloader symbol list */ + boot_export_symbol = 0x10002020; +} diff --git a/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip2.ld b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip2.ld new file mode 100644 index 0000000..18395ae --- /dev/null +++ b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip2.ld @@ -0,0 +1,157 @@ + + +ENTRY(Reset_Handler) + +INCLUDE "export-rom_symbol_v01.txt" + +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ + ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ + BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ + BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */ + MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ + RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ + + XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ + XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ + XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ + XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */ + XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */ +} + + + +SECTIONS +{ + .rom.text : { } > ROM + .rom.rodata : { } > ROM + .hal.rom.bss : { } > ROMBSS_RAM + + /* image1 entry, this section should in RAM and fixed address for ROM */ + .ram_image1.entry : + { + __ram_image1_text_start__ = .; + __ram_start_table_start__ = .; + KEEP(*(SORT(.image1.entry.data*))) + __ram_start_table_end__ = .; + + __image1_validate_code__ = .; + KEEP(*(.image1.validate.rodata*)) + KEEP(*(.image1.export.symb*)) + } > BOOTLOADER_RAM + + /* Add . to assign the start address of the section */ + /* to prevent the change of the start address by ld doing section alignment */ + .ram_image1.text . : + { + /* image1 text */ + *(.boot.ram.text*) + *(.boot.rodata*) + } > BOOTLOADER_RAM + + .ram_image1.data . : + { + __ram_image1_data_start__ = .; + KEEP(*(.boot.ram.data*)) + __ram_image1_data_end__ = .; + + __ram_image1_text_end__ = .; + } > BOOTLOADER_RAM + + .ram_image1.bss . : + { + __image1_bss_start__ = .; + KEEP(*(.boot.ram.bss*)) + KEEP(*(.boot.ram.end.bss*)) + __image1_bss_end__ = .; + } > BOOTLOADER_RAM + + .ram_image2.entry : + { + __ram_image2_text_start__ = .; + __image2_entry_func__ = .; + KEEP(*(SORT(.image2.entry.data*))) + + __image2_validate_code__ = .; + KEEP(*(.image2.validate.rodata*)) + + } > BD_RAM + + .ram_image2.text : + { + KEEP(*(.image2.ram.text*)) + } > BD_RAM + + .ram_image2.data : + { + __data_start__ = .; + *(.data*) + __data_end__ = .; + __ram_image2_text_end__ = .; + . = ALIGN(16); + } > BD_RAM + + .ram_image2.bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + } > BD_RAM + + .ram_image2.skb.bss : + { + *(.bdsram.data*) + __bss_end__ = .; + } > BD_RAM + + .ram_heap.data : + { + *(.bfsram.data*) + *(.heap.stdlib*) + + } > BD_RAM + + .ram_rdp.text : + { + __rom_top_4k_start_ = .; + __rdp_text_start__ = .; + KEEP(*(.rdp.ram.text*)) + KEEP(*(.rdp.ram.data*)) + __rdp_text_end__ = .; + . = ALIGN(16); + + } > RDP_RAM + + .xip_image1.text : + { + __flash_boot_text_start__ = .; + + *(.flashboot.text*) + + __flash_boot_text_end__ = .; + + . = ALIGN(16); + } > XIPBOOT + + .xip_image2.text : + { + __flash_text_start__ = .; + + *(.img2_custom_signature*) + + *(.text*) + *(.rodata*) + *(.debug_trace*) + + __flash_text_end__ = .; + + . = ALIGN (16); + } > XIP2 +} + +SECTIONS +{ + /* Bootloader symbol list */ + boot_export_symbol = 0x10002020; +} diff --git a/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip2_2M.ld b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip2_2M.ld new file mode 100644 index 0000000..8968224 --- /dev/null +++ b/boards/wr3/ld/rlx8711B-symbol-v02-img2_xip2_2M.ld @@ -0,0 +1,157 @@ + + +ENTRY(Reset_Handler) + +INCLUDE "export-rom_symbol_v01.txt" + +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ + ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ + BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ + BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x39000 /* MAIN RAM: 228 */ + MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ + RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ + + XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ + XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ + XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ + XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 2*468k, 32 Bytes resvd for header */ + XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 2*468k, 32 Bytes resvd for header */ +} + + + +SECTIONS +{ + .rom.text : { } > ROM + .rom.rodata : { } > ROM + .hal.rom.bss : { } > ROMBSS_RAM + + /* image1 entry, this section should in RAM and fixed address for ROM */ + .ram_image1.entry : + { + __ram_image1_text_start__ = .; + __ram_start_table_start__ = .; + KEEP(*(SORT(.image1.entry.data*))) + __ram_start_table_end__ = .; + + __image1_validate_code__ = .; + KEEP(*(.image1.validate.rodata*)) + KEEP(*(.image1.export.symb*)) + } > BOOTLOADER_RAM + + /* Add . to assign the start address of the section */ + /* to prevent the change of the start address by ld doing section alignment */ + .ram_image1.text . : + { + /* image1 text */ + *(.boot.ram.text*) + *(.boot.rodata*) + } > BOOTLOADER_RAM + + .ram_image1.data . : + { + __ram_image1_data_start__ = .; + KEEP(*(.boot.ram.data*)) + __ram_image1_data_end__ = .; + + __ram_image1_text_end__ = .; + } > BOOTLOADER_RAM + + .ram_image1.bss . : + { + __image1_bss_start__ = .; + KEEP(*(.boot.ram.bss*)) + KEEP(*(.boot.ram.end.bss*)) + __image1_bss_end__ = .; + } > BOOTLOADER_RAM + + .ram_image2.entry : + { + __ram_image2_text_start__ = .; + __image2_entry_func__ = .; + KEEP(*(SORT(.image2.entry.data*))) + + __image2_validate_code__ = .; + KEEP(*(.image2.validate.rodata*)) + + } > BD_RAM + + .ram_image2.text : + { + KEEP(*(.image2.ram.text*)) + } > BD_RAM + + .ram_image2.data : + { + __data_start__ = .; + *(.data*) + __data_end__ = .; + __ram_image2_text_end__ = .; + . = ALIGN(16); + } > BD_RAM + + .ram_image2.bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + } > BD_RAM + + .ram_image2.skb.bss : + { + *(.bdsram.data*) + __bss_end__ = .; + } > BD_RAM + + .ram_heap.data : + { + *(.bfsram.data*) + *(.heap.stdlib*) + + } > BD_RAM + + .ram_rdp.text : + { + __rom_top_4k_start_ = .; + __rdp_text_start__ = .; + KEEP(*(.rdp.ram.text*)) + KEEP(*(.rdp.ram.data*)) + __rdp_text_end__ = .; + . = ALIGN(16); + + } > RDP_RAM + + .xip_image1.text : + { + __flash_boot_text_start__ = .; + + *(.flashboot.text*) + + __flash_boot_text_end__ = .; + + . = ALIGN(16); + } > XIPBOOT + + .xip_image2.text : + { + __flash_text_start__ = .; + + *(.img2_custom_signature*) + + *(.text*) + *(.rodata*) + *(.debug_trace*) + + __flash_text_end__ = .; + + . = ALIGN (16); + } > XIP2 +} + +SECTIONS +{ + /* Bootloader symbol list */ + boot_export_symbol = 0x10002020; +} diff --git a/builder/frameworks/realtek-ambz-sdk.py b/builder/frameworks/realtek-ambz-sdk.py index 4f206e6..5d2534c 100644 --- a/builder/frameworks/realtek-ambz-sdk.py +++ b/builder/frameworks/realtek-ambz-sdk.py @@ -5,18 +5,21 @@ env = DefaultEnvironment() platform = env.PioPlatform() board = env.BoardConfig() +mcu = board.get("build.mcu").upper() +family = board.get("build.family").upper() +variant = board.get("build.variant") +ldscript = board.get("build.ldscript_sdk") + SDK_DIR = platform.get_package_dir("framework-realtek-amb1") +BOARD_DIR = join(platform.get_dir(), "boards", variant) +FIXUPS_DIR = join(platform.get_dir(), "fixups", "realtek-ambz") assert isdir(SDK_DIR) +assert isdir(env.subst(BOARD_DIR)) +assert isdir(env.subst(FIXUPS_DIR)) ota1_offset = board.get("build.amb_ota1_offset") ota2_offset = board.get("build.amb_ota2_offset") - -# Firmware name -if env.get("PROGNAME", "program") == "program": - env.Replace(PROGNAME="firmware") -env.Replace( - PROGSUFFIX=".elf", -) +boot_all = board.get("build.amb_boot_all") # Outputs env.Replace( @@ -38,7 +41,8 @@ env.Replace( # Flags env.Replace( - CCFLAGS=[ + CFLAGS=[ + "-std=gnu99", "-mcpu=cortex-m4", "-mthumb", "-mfloat-abi=hard", @@ -47,19 +51,19 @@ env.Replace( "-w", "-O2", "-Wno-pointer-sign", - "-fno-common", - "-fmessage-length=0", - "-ffunction-sections", "-fdata-sections", - "-fomit-frame-pointer", + "-ffunction-sections", + "-fmessage-length=0", + "-fno-common", "-fno-short-enums", - "-std=gnu99", + "-fomit-frame-pointer", "-fsigned-char", ], CPPDEFINES=[ "M3", "CONFIG_PLATFORM_8711B", ("F_CPU", "166000000L"), + ("LWIP_TIMEVAL_PRIVATE", "0"), ], LINKFLAGS=[ "-mcpu=cortex-m4", @@ -169,18 +173,12 @@ sources = [ # app uart_adapter "+<" + SDK_DIR +"/component/common/application/uart_adapter/uart_adapter.c>", # cmsis - "+<" + SDK_DIR +"/component/soc/realtek/8711b/cmsis/device/app_start.c>", + # NOTE: a fixup is used instead, to remove default main() + # "+<" + SDK_DIR +"/component/soc/realtek/8711b/cmsis/device/app_start.c>", "+<" + SDK_DIR +"/component/soc/realtek/8711b/fwlib/ram_lib/startup.c>", "+<" + SDK_DIR +"/component/soc/realtek/8711b/cmsis/device/system_8195a.c>", # console - # "+<" + SDK_DIR +"/component/common/api/at_cmd/atcmd_lwip.c>", - # "+<" + SDK_DIR +"/component/common/api/at_cmd/atcmd_sys.c>", - # "+<" + SDK_DIR +"/component/common/api/at_cmd/atcmd_wifi.c>", - # "+<" + SDK_DIR +"/component/common/api/at_cmd/log_service.c>", - # "+<" + SDK_DIR +"/component/soc/realtek/8711b/app/monitor/ram/low_level_io.c>", - # "+<" + SDK_DIR +"/component/soc/realtek/8711b/app/monitor/ram/monitor.c>", - "+<" + SDK_DIR +"/component/soc/realtek/8711b/app/monitor/ram/rtl_consol.c>", - # "+<" + SDK_DIR +"/component/soc/realtek/8711b/app/monitor/ram/rtl_trace.c>", + "+<" + SDK_DIR +"/component/soc/realtek/8711b/app/monitor/ram/rtl_trace.c>", # network api wifi rtw_wpa_supplicant "+<" + SDK_DIR +"/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_eap_config.c>", "+<" + SDK_DIR +"/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_p2p_config.c>", @@ -349,36 +347,6 @@ sources = [ "+<" + SDK_DIR +"/component/soc/realtek/8711b/misc/rtl8710b_ota.c>", "+<" + SDK_DIR +"/component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_pinmapcfg.c>", "+<" + SDK_DIR +"/component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_sleepcfg.c>", - # utilities example - # "+<" + SDK_DIR +"/component/common/example/bcast/example_bcast.c>", - # "+<" + SDK_DIR +"/component/common/example/dct/example_dct.c>", - # "+<" + SDK_DIR +"/component/common/example/eap/example_eap.c>", - # "+<" + SDK_DIR +"/component/common/example/example_entry.c>", - # "+<" + SDK_DIR +"/component/common/example/get_beacon_frame/example_get_beacon_frame.c>", - # "+<" + SDK_DIR +"/component/common/example/high_load_memory_use/example_high_load_memory_use.c>", - # "+<" + SDK_DIR +"/component/common/example/http_client/example_http_client.c>", - # "+<" + SDK_DIR +"/component/common/example/httpc/example_httpc.c>", - # "+<" + SDK_DIR +"/component/common/example/httpd/example_httpd.c>", - # "+<" + SDK_DIR +"/component/common/example/http_download/example_http_download.c>", - # "+<" + SDK_DIR +"/component/common/example/mcast/example_mcast.c>", - # "+<" + SDK_DIR +"/component/common/example/mdns/example_mdns.c>", - # "+<" + SDK_DIR +"/component/common/example/mqtt/example_mqtt.c>", - # "+<" + SDK_DIR +"/component/common/example/nonblock_connect/example_nonblock_connect.c>", - # "+<" + SDK_DIR +"/component/common/example/rarp/example_rarp.c>", - # "+<" + SDK_DIR +"/component/common/example/sntp_showtime/example_sntp_showtime.c>", - # "+<" + SDK_DIR +"/component/common/example/socket_select/example_socket_select.c>", - # "+<" + SDK_DIR +"/component/common/example/socket_tcp_trx/example_socket_tcp_trx_1.c>", - # "+<" + SDK_DIR +"/component/common/example/socket_tcp_trx/example_socket_tcp_trx_2.c>", - # "+<" + SDK_DIR +"/component/common/example/ssl_download/example_ssl_download.c>", - # "+<" + SDK_DIR +"/component/common/example/ssl_server/example_ssl_server.c>", - # "+<" + SDK_DIR +"/component/common/example/tcp_keepalive/example_tcp_keepalive.c>", - # "+<" + SDK_DIR +"/component/common/example/uart_atcmd/example_uart_atcmd.c>", - # "+<" + SDK_DIR +"/component/common/example/wifi_mac_monitor/example_wifi_mac_monitor.c>", - # "+<" + SDK_DIR +"/component/common/example/wlan_fast_connect/example_wlan_fast_connect.c>", - # "+<" + SDK_DIR +"/component/common/example/wlan_scenario/example_wlan_scenario.c>", - # "+<" + SDK_DIR +"/component/common/example/websocket/example_wsclient.c>", - # "+<" + SDK_DIR +"/component/common/example/xml/example_xml.c>", - # "+<" + SDK_DIR +"/component/common/example/uart_firmware_update/example_uart_update.c>", # network - httpc "+<" + SDK_DIR +"/component/common/network/httpc/httpc_tls.c>", # network - httpd @@ -391,14 +359,22 @@ sources = [ # fmt: on ] +# Fixups +sources += [ + "+<" + FIXUPS_DIR + "/app_start_patch.c>", + "+<" + FIXUPS_DIR + "/cmsis_ipsr.c>", + "+<" + FIXUPS_DIR + "/log_uart.c>", + "+<" + FIXUPS_DIR + "/wifi_mode.c>", +] + # Libs & linker config env.Append( LIBPATH=[ # fmt: off join(SDK_DIR, "component", "soc", "realtek", "8711b", "misc", "bsp", "lib", "common", "GCC"), - # linker script path - join(SDK_DIR, "project", "realtek_amebaz_va0_example", "GCC-RELEASE"), # fmt: on + # linker script path + join(BOARD_DIR, "ld"), ], LIBS=[ "_platform", @@ -418,9 +394,7 @@ env.Append( ) env.Replace( LDSCRIPT_PATH=[ - # fmt: off - join(SDK_DIR, "project", "realtek_amebaz_va0_example", "GCC-RELEASE", "rlx8711B-symbol-v02-img2_xip1.ld"), - # fmt: on + join(BOARD_DIR, "ld", ldscript), ], ) @@ -565,15 +539,20 @@ actions.append(env.VerboseAction(package_ota, "Packaging OTA image - $IMG_OTA")) actions.append(env.VerboseAction("true", f"- OTA1 flash offset: {ota1_offset}")) actions.append(env.VerboseAction("true", f"- OTA2 flash offset: {ota2_offset}")) +# Clone env to ignore options from child projects +envsdk = env.Clone() + # SDK library target -target_sdk = env.BuildLibrary(join("$BUILD_DIR", "SDK"), SDK_DIR, sources) +target_sdk = envsdk.BuildLibrary( + join("$BUILD_DIR", "ambz_sdk"), + SDK_DIR, + sources, +) target_boot = env.StaticLibrary( join("$BUILD_DIR", "boot_all"), env.BinToObj( join("$BUILD_DIR", "boot_all.o"), - # fmt: off - join(SDK_DIR, "component", "soc", "realtek", "8711b", "misc", "bsp", "image", "boot_all.bin"), - # fmt: on + join(BOARD_DIR, "bin", boot_all), ), ) env.Prepend(LIBS=[target_sdk, target_boot]) diff --git a/builder/main.py b/builder/main.py index 2bc8e09..a1217b1 100644 --- a/builder/main.py +++ b/builder/main.py @@ -2,17 +2,22 @@ from SCons.Script import Default, DefaultEnvironment env = DefaultEnvironment() +# Firmware name +if env.get("PROGNAME", "program") == "program": + env.Replace(PROGNAME="firmware") +env.Replace(PROGSUFFIX=".elf") + env.Replace( - AR="arm-none-eabi-ar", + AR="arm-none-eabi-gcc-ar", AS="arm-none-eabi-gcc", CC="arm-none-eabi-gcc", CXX="arm-none-eabi-g++", - NM="arm-none-eabi-nm", + NM="arm-none-eabi-gcc-nm", LINK="arm-none-eabi-gcc", LD="arm-none-eabi-gcc", OBJCOPY="arm-none-eabi-objcopy", OBJDUMP="arm-none-eabi-objdump", - RANLIB="arm-none-eabi-ranlib", + # RANLIB="arm-none-eabi-gcc-ranlib", SIZETOOL="arm-none-eabi-size", ) diff --git a/fixups/realtek-ambz/app_start_patch.c b/fixups/realtek-ambz/app_start_patch.c new file mode 100644 index 0000000..7d12206 --- /dev/null +++ b/fixups/realtek-ambz/app_start_patch.c @@ -0,0 +1,118 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +// NOTE: this file has the default main() function removed. + +#include "ameba_soc.h" +#include "build_info.h" + +#if (defined(CONFIG_POST_SIM)) +void Simulation_Init(void); +#endif + +#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK) +extern void init_rom_wlan_ram_map(void); +extern VOID wlan_network(VOID); +#endif + +#ifdef CONFIG_MBED_ENABLED +extern void __libc_fini_array (void); +extern void __libc_init_array (void); +extern void SVC_Handler (void); +extern void PendSV_Handler (void); +extern void SysTick_Handler (void); + +void APP_StartMbed(void) +{ + InterruptForOSInit((VOID*)SVC_Handler, + (VOID*)PendSV_Handler, + (VOID*)SysTick_Handler); + __asm ( + "ldr r0, =SystemInit\n" + "blx r0\n" + "ldr r0, =_start\n" + "bx r0\n" + ); + + for(;;); + +} +#endif + +void APP_InitTrace(void) +{ + u32 debug[4]; + +#if (defined(CONFIG_POST_SIM) || defined(CONFIG_CP)) + return; +#endif + + debug[LEVEL_ERROR] = BIT(MODULE_BOOT); + debug[LEVEL_WARN] = 0x0; + debug[LEVEL_INFO] = BIT(MODULE_BOOT); + debug[LEVEL_TRACE] = 0x0; + +#ifdef CONFIG_DEBUG_ERR_MSG + debug[LEVEL_ERROR] = 0xFFFFFFFF; +#endif +#ifdef CONFIG_DEBUG_WARN_MSG + debug[LEVEL_WARN] = 0xFFFFFFFF; +#endif +#ifdef CONFIG_DEBUG_INFO_MSG + debug[LEVEL_INFO] = 0xFFFFFFFF; +#endif + + LOG_MASK(debug); + + DBG_PRINTF(MODULE_BOOT, LEVEL_INFO, "APP_InitTrace: %x:%x:%x:%x\n",debug[0], debug[1], debug[2], debug[3]); + DBG_PRINTF(MODULE_BOOT, LEVEL_ERROR, "APP_InitTrace: %x:%x:%x:%x\n",debug[0], debug[1], debug[2], debug[3]); + +} + +extern void main(void); + +// The Main App entry point +void APP_Start(void) +{ +#if CONFIG_SOC_PS_MODULE + SOCPS_InitSYSIRQ(); +#endif + +#ifdef CONFIG_KERNEL +#ifdef PLATFORM_FREERTOS + InterruptForOSInit((VOID*)vPortSVCHandler, + (VOID*)xPortPendSVHandler, + (VOID*)xPortSysTickHandler); +#endif +#endif + +#ifdef CONFIG_MBED_ENABLED + APP_StartMbed(); +#else + +#if 0//def CONFIG_APP_DEMO +#ifdef PLATFORM_FREERTOS + xTaskCreate( (TaskFunction_t)main, "MAIN_APP__TASK", (2048 /4), (void *)NULL, (tskIDLE_PRIORITY + 1), NULL); + vTaskStartScheduler(); +#endif +#else +#if defined ( __ICCARM__ ) + __iar_cstart_call_ctors(NULL); +#endif + // force SP align to 8 byte not 4 byte (initial SP is 4 byte align) + __asm( + "mov r0, sp\n" + "bic r0, r0, #7\n" + "mov sp, r0\n" + ); + + main(); +#endif // end of #if CONFIG_APP_DEMO +#endif // end of else of "#ifdef CONFIG_MBED_ENABLED" +} diff --git a/fixups/realtek-ambz/cmsis_ipsr.c b/fixups/realtek-ambz/cmsis_ipsr.c new file mode 100644 index 0000000..a464e50 --- /dev/null +++ b/fixups/realtek-ambz/cmsis_ipsr.c @@ -0,0 +1,9 @@ +#include + +// for some reason, cmsis_os.c does not link properly when this method is inlined in core_cmFunc.h +// (or I am too stupid to understand this) +__attribute__((weak)) uint32_t __get_IPSR() +{ + uint32_t result; + asm volatile ("MRS %0, ipsr" : "=r" (result) ); +} diff --git a/fixups/realtek-ambz/log_uart.c b/fixups/realtek-ambz/log_uart.c new file mode 100644 index 0000000..1bdf5bd --- /dev/null +++ b/fixups/realtek-ambz/log_uart.c @@ -0,0 +1,28 @@ +#include "ameba_soc.h" +#include "osdep_service.h" + +// usage: +// extern int LOGUART_SetBaud(uint32_t BaudRate); + +int LOGUART_SetBaud(uint32_t BaudRate) +{ + UART_INTConfig(UART2_DEV, RUART_IER_ERBI | RUART_IER_ELSI, DISABLE); + UART_RxCmd(UART2_DEV, DISABLE); + + UART_SetBaud(UART2_DEV, BaudRate); + + UART_INTConfig(UART2_DEV, RUART_IER_ERBI | RUART_IER_ELSI, ENABLE); + UART_RxCmd(UART2_DEV, ENABLE); + + return 1; +} + +void LOGUART_SetBaud_FromFlash(void) +{ + // useless, nop +} + +void ReRegisterPlatformLogUart(void) +{ + // useless, nop +} diff --git a/fixups/realtek-ambz/wifi_mode.c b/fixups/realtek-ambz/wifi_mode.c new file mode 100644 index 0000000..56da3e1 --- /dev/null +++ b/fixups/realtek-ambz/wifi_mode.c @@ -0,0 +1,4 @@ +#include + +// wifi_mode is declared in atcmd_wifi.c, which is a part of the built-in trash console +rtw_mode_t wifi_mode = RTW_MODE_STA; diff --git a/platform.json b/platform.json index 09d36bc..4f1dadb 100644 --- a/platform.json +++ b/platform.json @@ -23,7 +23,10 @@ "toolchain-gccarmnoneeabi": { "type": "toolchain", "optionalVersions": [ - "~1.40804.0" + "~1.40804.0", + "~1.50401.0", + "~1.90301.0", + "~1.100301.0" ] } } diff --git a/platform.py b/platform.py index f9bdac0..1f4328b 100644 --- a/platform.py +++ b/platform.py @@ -5,5 +5,5 @@ class LibretuyaPlatform(PlatformBase): def configure_default_packages(self, options, targets): framework = options.get("pioframework")[0] if framework.startswith("realtek-ambz"): - self.packages["toolchain-gccarmnoneeabi"]["version"] = "~1.40804.0" + self.packages["toolchain-gccarmnoneeabi"]["version"] = "~1.50401.0" return super().configure_default_packages(options, targets)