[core] Specify flash layout in board.json

This commit is contained in:
Kuba Szczodrzyński
2022-04-24 17:48:11 +02:00
parent e8b72561b2
commit a4eabf863e
8 changed files with 40 additions and 26 deletions

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@@ -20,9 +20,12 @@ assert isdir(env.subst(BOARD_DIR))
assert isdir(env.subst(FIXUPS_DIR)) assert isdir(env.subst(FIXUPS_DIR))
assert isdir(env.subst(PLATFORM_DIR)) assert isdir(env.subst(PLATFORM_DIR))
ota1_offset = board.get("build.amb_ota1_offset") flash_addr = board.get("build.amb_flash_addr")
ota2_offset = board.get("build.amb_ota2_offset") flash_ota1_offset = env.subst("$FLASH_OTA1_OFFSET")
flash_ota2_offset = env.subst("$FLASH_OTA2_OFFSET")
boot_all = board.get("build.amb_boot_all") boot_all = board.get("build.amb_boot_all")
ota1_offset = hex(int(flash_addr, 16) + int(flash_ota1_offset, 16))
ota2_offset = hex(int(flash_addr, 16) + int(flash_ota2_offset, 16))
# Outputs # Outputs
env.Replace( env.Replace(
@@ -543,8 +546,8 @@ actions.append(env.VerboseAction(pick_tool, "Wrapping binary images"))
actions.append(env.VerboseAction(concat_xip_ram, "Packaging firmware image - $IMG_FW")) actions.append(env.VerboseAction(concat_xip_ram, "Packaging firmware image - $IMG_FW"))
# actions.append(env.VerboseAction(checksum_img, "Generating checksum")) # actions.append(env.VerboseAction(checksum_img, "Generating checksum"))
actions.append(env.VerboseAction(package_ota, "Packaging OTA image - $IMG_OTA")) actions.append(env.VerboseAction(package_ota, "Packaging OTA image - $IMG_OTA"))
actions.append(env.VerboseAction("true", f"- OTA1 flash offset: {ota1_offset}")) actions.append(env.VerboseAction("true", f"- OTA1 flash offset: {flash_ota1_offset}"))
actions.append(env.VerboseAction("true", f"- OTA2 flash offset: {ota2_offset}")) actions.append(env.VerboseAction("true", f"- OTA2 flash offset: {flash_ota2_offset}"))
# Clone env to ignore options from child projects # Clone env to ignore options from child projects
envsdk = env.Clone() envsdk = env.Clone()

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@@ -1,12 +1,14 @@
from SCons.Script import Default, DefaultEnvironment from SCons.Script import Default, DefaultEnvironment
env = DefaultEnvironment() env = DefaultEnvironment()
board = env.BoardConfig()
# Firmware name # Firmware name
if env.get("PROGNAME", "program") == "program": if env.get("PROGNAME", "program") == "program":
env.Replace(PROGNAME="firmware") env.Replace(PROGNAME="firmware")
env.Replace(PROGSUFFIX=".elf") env.Replace(PROGSUFFIX=".elf")
# Toolchain config - TODO multiple arch, specified in board.json
env.Replace( env.Replace(
AR="arm-none-eabi-gcc-ar", AR="arm-none-eabi-gcc-ar",
AS="arm-none-eabi-gcc", AS="arm-none-eabi-gcc",
@@ -21,8 +23,17 @@ env.Replace(
SIZETOOL="arm-none-eabi-size", SIZETOOL="arm-none-eabi-size",
) )
# I have no idea how does PlatformIO work # Flash layout defines
# env.SConscript("frameworks/realtek-ambz-sdk.py") flash_layout: dict = board.get("flash")
if flash_layout:
defines = {}
for name, layout in flash_layout.items():
name = name.upper()
(offset, _, length) = layout.partition("+")
defines[f"FLASH_{name}_OFFSET"] = offset
defines[f"FLASH_{name}_LENGTH"] = length
env.Append(CPPDEFINES=defines.items())
env.Replace(**defines)
target_elf = env.BuildProgram() target_elf = env.BuildProgram()
target_fw = env.DumpFirmwareBinary("firmware.bin", target_elf) target_fw = env.DumpFirmwareBinary("firmware.bin", target_elf)

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@@ -9,11 +9,11 @@ MEMORY
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */ BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 172k */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */ XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */

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@@ -9,15 +9,15 @@ MEMORY
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x39000 /* MAIN RAM: 228 */ BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x39000 /* MAIN RAM: 228k */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 2*468k, 32 Bytes resvd for header */ XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 2*468k, 32 Bytes resvd for header */ XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
} }

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@@ -17,16 +17,16 @@ MEMORY
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 228 */ BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */ ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 2*468k, 32 Bytes resvd for header */ XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 2*468k, 32 Bytes resvd for header */ XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
} }

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@@ -9,11 +9,11 @@ MEMORY
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */ BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 172k */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */ XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */

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@@ -9,15 +9,15 @@ MEMORY
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x39000 /* MAIN RAM: 228 */ BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x39000 /* MAIN RAM: 228k */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 2*468k, 32 Bytes resvd for header */ XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 2*468k, 32 Bytes resvd for header */ XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
} }

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@@ -17,16 +17,16 @@ MEMORY
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */ ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */ BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 228 */ BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */ ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */ MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */ RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/ XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */ XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 2*468k, 32 Bytes resvd for header */ XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 2*468k, 32 Bytes resvd for header */ XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
} }