[core] Split boards as base files

This commit is contained in:
Kuba Szczodrzyński
2022-05-10 17:48:41 +02:00
parent 1477649a50
commit e4cd2ddec8
6 changed files with 119 additions and 67 deletions

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@@ -0,0 +1,21 @@
{
"build": {
"ldscript_sdk": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
"ldscript_arduino": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
"amb_boot_all": "boot_all_77F7.bin"
},
"flash": {
"boot_xip": "0x000000+0x4000",
"boot_ram": "0x004000+0x4000",
"system": "0x009000+0x1000",
"calibration": "0x00A000+0x1000",
"ota1": "0x00B000+0xC5000",
"ota2": "0x0D0000+0xC5000",
"userdata": "0x195000+0x6A000",
"rdp": "0x1FF000+0x1000"
},
"upload": {
"flash_size": 2097152,
"maximum_size": 806912
}
}

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@@ -0,0 +1,42 @@
{
"build": {
"f_cpu": "125000000L",
"amb_flash_addr": "0x08000000"
},
"connectivity": [
"wifi"
],
"debug": {
"protocol": "openocd",
"protocols": [
"openocd"
],
"openocd_config": "amebaz.cfg",
"gdb_init": [
"mem 0x8000000 0x8200000 ro"
]
},
"frameworks": [
"realtek-ambz-sdk",
"realtek-ambz-arduino"
],
"upload": {
"maximum_ram_size": 262144,
"require_upload_port": true,
"speed": 1500000,
"protocol": "uart",
"protocols": [
"uart"
]
},
"doc": {
"params": {
"manufacturer": "Realtek",
"series": "AmebaZ",
"voltage": "3.0V - 3.6V",
"extra": {
"Wi-Fi": "802.11 b/g/n"
}
}
}
}

View File

@@ -1,51 +1,12 @@
{
"_base": [
"realtek-ambz",
"realtek-ambz-2mb"
],
"build": {
"mcu": "rtl8710bn",
"family": "rtl8710",
"variant": "wr3",
"ldscript_sdk": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
"ldscript_arduino": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
"f_cpu": "125000000L",
"amb_flash_addr": "0x08000000",
"amb_boot_all": "boot_all_77F7.bin"
},
"connectivity": [
"wifi"
],
"debug": {
"protocol": "openocd",
"protocols": [
"openocd"
],
"openocd_config": "amebaz.cfg",
"gdb_init": [
"mem 0x8000000 0x8200000 ro"
]
},
"flash": {
"boot_xip": "0x000000+0x4000",
"boot_ram": "0x004000+0x4000",
"system": "0x009000+0x1000",
"calibration": "0x00A000+0x1000",
"ota1": "0x00B000+0xC5000",
"ota2": "0x0D0000+0xC5000",
"userdata": "0x195000+0x6A000",
"rdp": "0x1FF000+0x1000"
},
"frameworks": [
"realtek-ambz-sdk",
"realtek-ambz-arduino"
],
"upload": {
"flash_size": "2MB",
"maximum_size": 806912,
"maximum_ram_size": 262144,
"require_upload_port": true,
"speed": 1500000,
"protocol": "uart",
"protocols": [
"uart"
]
"variant": "wr3"
},
"name": "WR3 Wi-Fi Module",
"url": "https://developer.tuya.com/en/docs/iot/wr3-module-datasheet?id=K9g3ainzbj9z1",

View File

@@ -19,8 +19,6 @@ PinDescription g_APinDescription[PINS_COUNT] = {
{PA_15, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
// D4: PWM2, ext_32K
{PA_0, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
// D5: SD_CMD, I2S_SD_RX, ADC3
{PA_20, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ, NOT_INITIAL},
// D6: UART2_log_RXD, I2C0_SCL, PWM4
{PA_29, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
// D7: UART2_log_TXD, I2C0_SDA, PWM3, RTC_OUT
@@ -33,6 +31,8 @@ PinDescription g_APinDescription[PINS_COUNT] = {
{PA_18, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ, NOT_INITIAL},
// D11: UART0_TXD, SPI1_MOSI, SPI0_MOSI, I2C1_SDA, SD_D1, PWM0, WAKEUP_3
{PA_23, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
// A1: VBAT_MEAS, ADC2
{AD_2, NOT_INITIAL, PIO_ADC, NOT_INITIAL},
};
// clang-format on

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@@ -8,10 +8,10 @@
// ----
// Number of pins defined in PinDescription array
#define PINS_COUNT (12u)
#define NUM_DIGITAL_PINS (12u)
#define NUM_ANALOG_INPUTS (2u)
#define NUM_ANALOG_OUTPUTS (0u)
#define PINS_COUNT 12
#define NUM_DIGITAL_PINS 11
#define NUM_ANALOG_INPUTS 2
#define NUM_ANALOG_OUTPUTS 0
// Low-level pin register query macros
// -----------------------------------
@@ -21,14 +21,14 @@
// LEDs
// ----
#define PIN_LED (4u)
#define LED_BUILTIN PIN_LED
#define PIN_LED 4u // PA_0
#define LED_BUILTIN PIN_LED // PA_0
// Analog pins
// -----------
#define PIN_A0 (1u) // PA_19
#define PIN_A1 (0u) // dummy, this is NOT usable
#define PIN_A2 (5u) // PA_20
#define PIN_A0 1u // PA_19
#define PIN_A1 11u // VBAT_MEAS
#define PIN_A2 0u // dummy, this is NOT usable
static const uint8_t A0 = PIN_A0;
static const uint8_t A1 = PIN_A1;
@@ -44,18 +44,19 @@ static const uint8_t A2 = PIN_A2;
// Serial ports
// ------------
#ifdef __cplusplus
#include "LOGUARTClass.h"
extern LOGUARTClass Serial;
// LOGUARTClass
#define PIN_SERIAL2_RX PA_29
#define PIN_SERIAL2_TX PA_30
#define PIN_SERIAL2_RX 5u // PA_29
#define PIN_SERIAL2_TX 6u // PA_30
// UARTClassOne
#define PIN_SERIAL0_RX PA_18
#define PIN_SERIAL0_TX PA_23
#endif // __cplusplus
#define PIN_SERIAL0_RX 9u // PA_18
#define PIN_SERIAL0_TX 10u // PA_23
#define SERIAL_PORT_USBVIRTUAL Serial
#define SERIAL_PORT_MONITOR Serial
#define SERIAL_PORT_HARDWARE Serial
#define SERIAL_PORT_HARDWARE_OPEN Serial
#ifdef __cplusplus
#include "LOGUARTClass.h"
extern LOGUARTClass Serial;
#endif // __cplusplus

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@@ -1,7 +1,10 @@
# Copyright (c) Kuba Szczodrzyński 2022-04-20.
from os.path import dirname
import json
from os.path import dirname, join
from typing import Dict
from platformio import util
from platformio.debug.config.base import DebugConfigBase
from platformio.debug.exception import DebugInvalidOptionsError
from platformio.managers.platform import PlatformBase
@@ -67,6 +70,8 @@ def find_pkg_root(self, path: str, spec: PackageSpec):
class LibretuyaPlatform(PlatformBase):
boards_base: Dict[str, dict] = {}
def configure_default_packages(self, options, targets):
framework = options.get("pioframework")[0]
# patch find_pkg root to ignore missing manifests and save PackageSpec
@@ -97,13 +102,35 @@ class LibretuyaPlatform(PlatformBase):
if not result:
return result
if id_:
return self._add_default_debug_tools(result)
return self.update_board(result)
else:
for key, value in result.items():
result[key] = self._add_default_debug_tools(value)
result[key] = self.update_board(value)
return result
def _add_default_debug_tools(self, board: PlatformBoardConfig):
def update_board(self, board: PlatformBoardConfig):
if "_base" in board:
base = board.get("_base")
if not isinstance(base, list):
base = [base]
result = None
for base_name in base:
if base_name not in self.boards_base:
file = join(
dirname(__file__), "boards", "_base", f"{base_name}.json"
)
with open(file, encoding="utf-8") as f:
self.boards_base[base_name] = json.load(f)
if not result:
result = self.boards_base[base_name]
else:
util.merge_dicts(result, self.boards_base[base_name])
util.merge_dicts(result, board._manifest)
board._manifest = result
# inspired by platform-ststm32/platform.py
debug = board.manifest.get("debug", {})
if not debug: