[core] Split boards as base files
This commit is contained in:
21
boards/_base/realtek-ambz-2mb.json
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21
boards/_base/realtek-ambz-2mb.json
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@@ -0,0 +1,21 @@
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{
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"build": {
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"ldscript_sdk": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
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"ldscript_arduino": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
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"amb_boot_all": "boot_all_77F7.bin"
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},
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"flash": {
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"boot_xip": "0x000000+0x4000",
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"boot_ram": "0x004000+0x4000",
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"system": "0x009000+0x1000",
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"calibration": "0x00A000+0x1000",
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"ota1": "0x00B000+0xC5000",
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"ota2": "0x0D0000+0xC5000",
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"userdata": "0x195000+0x6A000",
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"rdp": "0x1FF000+0x1000"
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},
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"upload": {
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"flash_size": 2097152,
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"maximum_size": 806912
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}
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}
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42
boards/_base/realtek-ambz.json
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42
boards/_base/realtek-ambz.json
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@@ -0,0 +1,42 @@
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{
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"build": {
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"f_cpu": "125000000L",
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"amb_flash_addr": "0x08000000"
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},
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"connectivity": [
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"wifi"
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],
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"debug": {
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"protocol": "openocd",
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"protocols": [
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"openocd"
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],
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"openocd_config": "amebaz.cfg",
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"gdb_init": [
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"mem 0x8000000 0x8200000 ro"
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]
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},
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"frameworks": [
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"realtek-ambz-sdk",
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"realtek-ambz-arduino"
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],
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"upload": {
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"maximum_ram_size": 262144,
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"require_upload_port": true,
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"speed": 1500000,
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"protocol": "uart",
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"protocols": [
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"uart"
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]
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},
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"doc": {
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"params": {
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"manufacturer": "Realtek",
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"series": "AmebaZ",
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"voltage": "3.0V - 3.6V",
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"extra": {
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"Wi-Fi": "802.11 b/g/n"
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}
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}
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}
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}
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@@ -1,51 +1,12 @@
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{
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"_base": [
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"realtek-ambz",
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"realtek-ambz-2mb"
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],
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"build": {
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"mcu": "rtl8710bn",
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"family": "rtl8710",
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"variant": "wr3",
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"ldscript_sdk": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
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"ldscript_arduino": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
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"f_cpu": "125000000L",
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"amb_flash_addr": "0x08000000",
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"amb_boot_all": "boot_all_77F7.bin"
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},
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"connectivity": [
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"wifi"
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],
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"debug": {
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"protocol": "openocd",
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"protocols": [
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"openocd"
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],
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"openocd_config": "amebaz.cfg",
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"gdb_init": [
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"mem 0x8000000 0x8200000 ro"
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]
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},
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"flash": {
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"boot_xip": "0x000000+0x4000",
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"boot_ram": "0x004000+0x4000",
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"system": "0x009000+0x1000",
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"calibration": "0x00A000+0x1000",
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"ota1": "0x00B000+0xC5000",
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"ota2": "0x0D0000+0xC5000",
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"userdata": "0x195000+0x6A000",
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"rdp": "0x1FF000+0x1000"
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},
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"frameworks": [
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"realtek-ambz-sdk",
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"realtek-ambz-arduino"
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],
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"upload": {
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"flash_size": "2MB",
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"maximum_size": 806912,
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"maximum_ram_size": 262144,
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"require_upload_port": true,
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"speed": 1500000,
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"protocol": "uart",
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"protocols": [
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"uart"
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]
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"variant": "wr3"
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},
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"name": "WR3 Wi-Fi Module",
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"url": "https://developer.tuya.com/en/docs/iot/wr3-module-datasheet?id=K9g3ainzbj9z1",
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@@ -19,8 +19,6 @@ PinDescription g_APinDescription[PINS_COUNT] = {
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{PA_15, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
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// D4: PWM2, ext_32K
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{PA_0, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
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// D5: SD_CMD, I2S_SD_RX, ADC3
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{PA_20, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ, NOT_INITIAL},
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// D6: UART2_log_RXD, I2C0_SCL, PWM4
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{PA_29, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
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// D7: UART2_log_TXD, I2C0_SDA, PWM3, RTC_OUT
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@@ -33,6 +31,8 @@ PinDescription g_APinDescription[PINS_COUNT] = {
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{PA_18, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ, NOT_INITIAL},
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// D11: UART0_TXD, SPI1_MOSI, SPI0_MOSI, I2C1_SDA, SD_D1, PWM0, WAKEUP_3
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{PA_23, NOT_INITIAL, PIO_GPIO | PIO_GPIO_IRQ | PIO_PWM, NOT_INITIAL},
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// A1: VBAT_MEAS, ADC2
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{AD_2, NOT_INITIAL, PIO_ADC, NOT_INITIAL},
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};
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// clang-format on
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@@ -8,10 +8,10 @@
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// ----
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// Number of pins defined in PinDescription array
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#define PINS_COUNT (12u)
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#define NUM_DIGITAL_PINS (12u)
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#define NUM_ANALOG_INPUTS (2u)
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#define NUM_ANALOG_OUTPUTS (0u)
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#define PINS_COUNT 12
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#define NUM_DIGITAL_PINS 11
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#define NUM_ANALOG_INPUTS 2
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#define NUM_ANALOG_OUTPUTS 0
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// Low-level pin register query macros
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// -----------------------------------
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@@ -21,14 +21,14 @@
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// LEDs
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// ----
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#define PIN_LED (4u)
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#define LED_BUILTIN PIN_LED
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#define PIN_LED 4u // PA_0
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#define LED_BUILTIN PIN_LED // PA_0
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// Analog pins
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// -----------
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#define PIN_A0 (1u) // PA_19
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#define PIN_A1 (0u) // dummy, this is NOT usable
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#define PIN_A2 (5u) // PA_20
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#define PIN_A0 1u // PA_19
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#define PIN_A1 11u // VBAT_MEAS
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#define PIN_A2 0u // dummy, this is NOT usable
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static const uint8_t A0 = PIN_A0;
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static const uint8_t A1 = PIN_A1;
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@@ -44,18 +44,19 @@ static const uint8_t A2 = PIN_A2;
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// Serial ports
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// ------------
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#ifdef __cplusplus
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#include "LOGUARTClass.h"
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extern LOGUARTClass Serial;
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// LOGUARTClass
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#define PIN_SERIAL2_RX PA_29
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#define PIN_SERIAL2_TX PA_30
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#define PIN_SERIAL2_RX 5u // PA_29
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#define PIN_SERIAL2_TX 6u // PA_30
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// UARTClassOne
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#define PIN_SERIAL0_RX PA_18
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#define PIN_SERIAL0_TX PA_23
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#endif // __cplusplus
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#define PIN_SERIAL0_RX 9u // PA_18
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#define PIN_SERIAL0_TX 10u // PA_23
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#define SERIAL_PORT_USBVIRTUAL Serial
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#define SERIAL_PORT_MONITOR Serial
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#define SERIAL_PORT_HARDWARE Serial
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#define SERIAL_PORT_HARDWARE_OPEN Serial
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#ifdef __cplusplus
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#include "LOGUARTClass.h"
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extern LOGUARTClass Serial;
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#endif // __cplusplus
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35
platform.py
35
platform.py
@@ -1,7 +1,10 @@
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# Copyright (c) Kuba Szczodrzyński 2022-04-20.
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from os.path import dirname
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import json
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from os.path import dirname, join
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from typing import Dict
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from platformio import util
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from platformio.debug.config.base import DebugConfigBase
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from platformio.debug.exception import DebugInvalidOptionsError
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from platformio.managers.platform import PlatformBase
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@@ -67,6 +70,8 @@ def find_pkg_root(self, path: str, spec: PackageSpec):
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class LibretuyaPlatform(PlatformBase):
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boards_base: Dict[str, dict] = {}
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def configure_default_packages(self, options, targets):
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framework = options.get("pioframework")[0]
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# patch find_pkg root to ignore missing manifests and save PackageSpec
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@@ -97,13 +102,35 @@ class LibretuyaPlatform(PlatformBase):
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if not result:
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return result
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if id_:
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return self._add_default_debug_tools(result)
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return self.update_board(result)
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else:
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for key, value in result.items():
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result[key] = self._add_default_debug_tools(value)
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result[key] = self.update_board(value)
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return result
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def _add_default_debug_tools(self, board: PlatformBoardConfig):
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def update_board(self, board: PlatformBoardConfig):
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if "_base" in board:
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base = board.get("_base")
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if not isinstance(base, list):
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base = [base]
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result = None
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for base_name in base:
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if base_name not in self.boards_base:
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file = join(
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dirname(__file__), "boards", "_base", f"{base_name}.json"
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)
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with open(file, encoding="utf-8") as f:
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self.boards_base[base_name] = json.load(f)
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if not result:
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result = self.boards_base[base_name]
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else:
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util.merge_dicts(result, self.boards_base[base_name])
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util.merge_dicts(result, board._manifest)
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board._manifest = result
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# inspired by platform-ststm32/platform.py
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debug = board.manifest.get("debug", {})
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if not debug:
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