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[core] Move platform/ files to cores/

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This commit is contained in:
Kuba Szczodrzyński
2023-02-25 15:24:04 +01:00
parent 3407891e9c
commit f1ecb312c7
68 changed files with 0 additions and 20 deletions
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134
cores/beken-7231n/base/config/sys_config.h Normal file
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#pragma once
#define ASSERT_HALT 1
#define ASSERT_IGNORE 2
#define ASSERT_REBOOT 3
#define AT_SERVICE_CFG 0
#define BLE_DEFAULT_WIFI_REQUEST 2
#define BLE_VERSION_4_2 1
#define BLE_VERSION_5_x 2
#define BLE_WIFI_CO_REQUEST 3
#define CFG_AIRKISS_TEST 0
#define CFG_AP_MONITOR_COEXIST 0
#define CFG_AP_SUPPORT_HT_IE 0
#define CFG_ASSERT_OPTION ASSERT_IGNORE
#define CFG_BACKGROUND_PRINT 0
#define CFG_BK_AWARE 0
#define CFG_BK_AWARE_OUI "\xC8\x47\x8C"
#define CFG_BLE_ADV_NUM 1
#define CFG_BLE_CONN_NUM 1
#define CFG_BLE_INIT_NUM 0
#define CFG_BLE_SCAN_NUM 1
#define CFG_BLE_VERSION BLE_VERSION_5_x
#define CFG_EASY_FLASH 0
#define CFG_ENABLE_BUTTON 0
#define CFG_ENABLE_DEMO_TEST 0
#define CFG_ENABLE_WPA_LOG 0
#define CFG_GENERAL_DMA 1
#define CFG_IEEE80211N 1
#define CFG_IEEE80211W 0
#define CFG_INT_WDG_ENABLED 0
#define CFG_INT_WDG_PERIOD_MS 10000
#define CFG_IPERF_TEST 0
#define CFG_JTAG_ENABLE 0
#define CFG_LESS_MEMERY_IN_RWNX 0
#define CFG_LWIP_MEM_POLICY LWIP_REDUCE_THE_PLAN
#define CFG_MAC_PHY_BAPASS 1
#define CFG_MSDU_RESV_HEAD_LEN 96
#define CFG_MSDU_RESV_TAIL_LEN 16
#define CFG_PERIPHERAL_TEST 0
#define CFG_REAL_SDIO 0
#define CFG_RELEASE_FIRMWARE 0
#define CFG_ROLE_LAUNCH 0
#define CFG_RUNNING_PLATFORM SOC_PLATFORM
#define CFG_RWNX_QOS_MSDU 1
#define CFG_RX_SENSITIVITY_TEST 1
#define CFG_SARADC_CALIBRATE 0
#define CFG_SDIO 0
#define CFG_SDIO_TRANS 0
#define CFG_SOC_NAME SOC_BK7231N
#define CFG_SUPPOET_BSSID_CONNECT 0
#define CFG_SUPPORT_BKREG 1
#define CFG_SUPPORT_BLE 1
#define CFG_SUPPORT_BLE_MESH 0
#define CFG_SUPPORT_BSSID_CONNECT 0
#define CFG_SUPPORT_CALIBRATION 1
#define CFG_SUPPORT_MANUAL_CALI 1
#define CFG_SUPPORT_OTA_HTTP 1
#define CFG_SUPPORT_OTA_TFTP 0
#define CFG_SUPPORT_SPI_TEST 0
#define CFG_SUPPORT_TIANZHIHENG_DRONE 0
#define CFG_SUPPORT_TPC_PA_MAP 1
#define CFG_SYS_REDUCE_NORMAL_POWER 0
#define CFG_TASK_WDG_ENABLED 0
#define CFG_TASK_WDG_PERIOD_MS 60000
#define CFG_TCP_SERVER_TEST 0
#define CFG_TX_EVM_TEST 1
#define CFG_UART_DEBUG 0
#define CFG_UART_DEBUG_COMMAND_LINE 1
#define CFG_UDISK_MP3 0
#define CFG_USB 0
#define CFG_USE_AP_IDLE 0
#define CFG_USE_AP_PS 0
#define CFG_USE_AUD_ADC 0
#define CFG_USE_AUD_DAC 0
#define CFG_USE_AUDIO 0
#define CFG_USE_BLE_PS 1
#define CFG_USE_CAMERA_INTF 0
#define CFG_USE_DEEP_PS 1
#define CFG_USE_DHCP 1
#define CFG_USE_FAKERTC_PS 0
#define CFG_USE_FTPD_UPGRADE 0
#define CFG_USE_I2C1 0
#define CFG_USE_I2C2 1
#define CFG_USE_LWIP_NETSTACK 1
#define CFG_USE_MCU_PS 1
#define CFG_USE_PTA 0
#define CFG_USE_SDCARD_HOST 0
#define CFG_USE_SPI_DMA 1
#define CFG_USE_SPI_MASTER 1
#define CFG_USE_SPI_SLAVE 1
#define CFG_USE_SPIDMA 0
#define CFG_USE_STA_PS 1
#define CFG_USE_TEMPERATURE_DETECT 0
#define CFG_USE_TICK_CAL 1
#define CFG_USE_UART1 1
#define CFG_USE_USB_CHARGE 0
#define CFG_USE_USB_HOST 0
#define CFG_USE_WPA_29 1
#define CFG_WFA_CERT 0
#define CFG_WIFI_RAW_TX_CMD 0
#define CFG_WIFI_SENSOR 0
#define CFG_WLAN_FAST_CONNECT 0
#define CFG_WPA_CTRL_IFACE 1
#define CFG_WPA3 0
#define CFG_XTAL_FREQUENCE CFG_XTAL_FREQUENCE_26M
#define CFG_XTAL_FREQUENCE_26M 26000000
#define CFG_XTAL_FREQUENCE_40M 40000000
#define CONFIG_APP_MP3PLAYER 0
#define FPGA_PLATFORM 0
#define LWIP_DEFAULT_MEM_POLICY 1
#define LWIP_REDUCE_THE_PLAN 2
#define OSMALLOC_STATISTICAL 0
#define RF_USE_POLICY WIFI_DEFAULT_BLE_REQUEST
#define SOC_BK7221U 3
#define SOC_BK7231 1
#define SOC_BK7231N 5
#define SOC_BK7231U 2
#define SOC_BK7271 4
#define SOC_PLATFORM 1
#define THD_APPLICATION_PRIORITY 3
#define THD_CORE_PRIORITY 2
#define THD_EXTENDED_APP_PRIORITY 5
#define THD_HOSTAPD_PRIORITY 5
#define THD_INIT_PRIORITY 4
#define THD_LWIP_PRIORITY 4
#define THD_MEDIA_PRIORITY 4
#define THD_RECONNECT_PRIORITY 4
#define THD_UBG_PRIORITY 5
#define THD_UMP3_PRIORITY 4
#define THD_WPAS_PRIORITY 5
#define THDD_KEY_SCAN_PRIORITY 7
#define UART1_USE_FIFO_REC 0
#define UART2_USE_FIFO_REC 0
#define WIFI_DEFAULT_BLE_REQUEST 1

6
cores/beken-7231n/base/src/fixups/temp_detect.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-07-07. */
// Fix for compiling on BK7231N with CFG_USE_TEMPERATURE_DETECT=0
// Method is used by libuart_debug_bk7231n.a / bkreg_run_command_implement()
void temp_detect_change_configuration(unsigned long intval, unsigned long thre, unsigned long dist) {}

118
cores/beken-7231u/base/config/sys_config.h Normal file
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#pragma once
#define BLE_DEFAULT_WIFI_REQUEST 2
#define BLE_VERSION_4_2 1
#define BLE_VERSION_5_x 2
#define BLE_WIFI_CO_REQUEST 3
#define CFG_AIRKISS_TEST 0
#define CFG_AP_MONITOR_COEXIST 0
#define CFG_AP_SUPPORT_HT_IE 0
#define CFG_BACKGROUND_PRINT 0
#define CFG_BK_AWARE 0
#define CFG_BK_AWARE_OUI "\xC8\x47\x8C"
#define CFG_BLE_VERSION BLE_VERSION_4_2
#define CFG_EASY_FLASH 1
#define CFG_ENABLE_BUTTON 0
#define CFG_ENABLE_DEMO_TEST 0
#define CFG_ENABLE_WPA_LOG 0
#define CFG_GENERAL_DMA 1
#define CFG_IEEE80211N 1
#define CFG_IEEE80211W 0
#define CFG_INT_WDG_ENABLED 0
#define CFG_INT_WDG_PERIOD_MS 10000
#define CFG_IPERF_TEST 0
#define CFG_JTAG_ENABLE 0
#define CFG_LESS_MEMERY_IN_RWNX 0
#define CFG_MAC_PHY_BAPASS 1
#define CFG_MSDU_RESV_HEAD_LEN 96
#define CFG_MSDU_RESV_TAIL_LEN 16
#define CFG_REAL_SDIO 0
#define CFG_RELEASE_FIRMWARE 0
#define CFG_RF_OTA_TEST 0
#define CFG_ROLE_LAUNCH 0
#define CFG_RUNNING_PLATFORM SOC_PLATFORM
#define CFG_RWNX_QOS_MSDU 1
#define CFG_RX_SENSITIVITY_TEST 1
#define CFG_SARADC_CALIBRATE 0
#define CFG_SDIO 0
#define CFG_SDIO_TRANS 0
#define CFG_SOC_NAME SOC_BK7231U
#define CFG_SUPPORT_BKREG 1
#define CFG_SUPPORT_BLE 1
#define CFG_SUPPORT_BLE_MESH 0
#define CFG_SUPPORT_BSSID_CONNECT 0
#define CFG_SUPPORT_CALIBRATION 1
#define CFG_SUPPORT_MANUAL_CALI 1
#define CFG_SUPPORT_OTA_HTTP 1
#define CFG_SUPPORT_OTA_TFTP 0
#define CFG_SUPPORT_TPC_PA_MAP 1
#define CFG_SYS_REDUCE_NORMAL_POWER 0
#define CFG_TASK_WDG_ENABLED 0
#define CFG_TASK_WDG_PERIOD_MS 60000
#define CFG_TCP_SERVER_TEST 0
#define CFG_TX_EVM_TEST 1
#define CFG_UART_DEBUG 0
#define CFG_UART_DEBUG_COMMAND_LINE 1
#define CFG_UDISK_MP3 0
#define CFG_USB 0
#define CFG_USE_AP_IDLE 0
#define CFG_USE_AP_PS 0
#define CFG_USE_APP_DEMO_VIDEO_TRANSFER 0
#define CFG_USE_AUD_ADC 0
#define CFG_USE_AUD_DAC 0
#define CFG_USE_AUDIO 0
#define CFG_USE_BLE_PS 1
#define CFG_USE_CAMERA_INTF 0
#define CFG_USE_DEEP_PS 1
#define CFG_USE_DHCP 1
#define CFG_USE_FAKERTC_PS 0
#define CFG_USE_FTPD_UPGRADE 0
#define CFG_USE_HSLAVE_SPI 0
#define CFG_USE_LWIP_NETSTACK 1
#define CFG_USE_MCU_PS 1
#define CFG_USE_PTA 0
#define CFG_USE_SDCARD_HOST 0
#define CFG_USE_SPIDMA 0
#define CFG_USE_STA_PS 1
#define CFG_USE_TEMPERATURE_DETECT 0
#define CFG_USE_TICK_CAL 1
#define CFG_USE_UART1 0
#define CFG_USE_USB_CHARGE 0
#define CFG_USE_USB_DEVICE 1
#define CFG_USE_USB_DEVICE_CARD_READER 1
#define CFG_USE_USB_HOST 0
#define CFG_USE_WPA_29 1
#define CFG_WFA_CERT 0
#define CFG_WIFI_RAW_TX_CMD 0
#define CFG_WIFI_SENSOR 0
#define CFG_WLAN_FAST_CONNECT 0
#define CFG_WPA_CTRL_IFACE 1
#define CFG_WPA3 0
#define CFG_XTAL_FREQUENCE CFG_XTAL_FREQUENCE_26M
#define CFG_XTAL_FREQUENCE_26M 26000000
#define CFG_XTAL_FREQUENCE_40M 40000000
#define CONFIG_APP_MP3PLAYER 0
#define FPGA_PLATFORM 0
#define OSMALLOC_STATISTICAL 0
#define RF_USE_POLICY WIFI_DEFAULT_BLE_REQUEST
#define SOC_BK7221U 3
#define SOC_BK7231 1
#define SOC_BK7231N 5
#define SOC_BK7231U 2
#define SOC_BK7271 4
#define SOC_PLATFORM 1
#define THD_APPLICATION_PRIORITY 3
#define THD_CORE_PRIORITY 2
#define THD_EXTENDED_APP_PRIORITY 5
#define THD_HOSTAPD_PRIORITY 5
#define THD_INIT_PRIORITY 4
#define THD_LWIP_PRIORITY 4
#define THD_MEDIA_PRIORITY 4
#define THD_RECONNECT_PRIORITY 4
#define THD_UBG_PRIORITY 5
#define THD_UMP3_PRIORITY 4
#define THD_WPAS_PRIORITY 5
#define THDD_KEY_SCAN_PRIORITY 7
#define UART1_USE_FIFO_REC 0
#define UART2_USE_FIFO_REC 0
#define WIFI_DEFAULT_BLE_REQUEST 1

499
cores/beken-7231u/src/fixups/boot_handlers_105_bk7231s.S Normal file
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/**
****************************************************************************************
*
* @file boot_handlers.s
*
* @brief ARM Exception Vector handler functions.
*
* Copyright (C) RivieraWaves 2011-2016
*
****************************************************************************************
*/
.globl entry_main
.globl intc_irq
.globl intc_fiq
.globl boot_reset
.globl boot_swi
.globl boot_undefined
.globl boot_pabort
.globl boot_dabort
.globl boot_reserved
.globl irq_handler
.globl fiq_handler
.globl vPortStartFirstTask
.globl do_irq
.globl do_fiq
.globl do_swi
.globl do_undefined
.globl do_pabort
.globl do_dabort
.globl do_reserved
.globl bk_trap_udef
.globl bk_trap_pabt
.globl bk_trap_dabt
.globl bk_trap_resv
#include "sys_config.h"
/* ========================================================================
* Macros
* ======================================================================== */
#define _FIQ_STACK_SIZE_ 0x7F0
#define _IRQ_STACK_SIZE_ 0xFF0
#define _SVC_STACK_SIZE_ 0x3F0
#define _SYS_STACK_SIZE_ 0x3F0
#define _UND_STACK_SIZE_ 0x010
#define _ABT_STACK_SIZE_ 0x010
#define BOOT_MODE_MASK 0x1F
#define BOOT_MODE_USR 0x10
#define BOOT_MODE_FIQ 0x11
#define BOOT_MODE_IRQ 0x12
#define BOOT_MODE_SVC 0x13
#define BOOT_MODE_ABT 0x17
#define BOOT_MODE_UND 0x1B
#define BOOT_MODE_SYS 0x1F
#define BOOT_FIQ_IRQ_MASK 0xC0
#define BOOT_IRQ_MASK 0x80
#define BOOT_COLOR_UNUSED 0xAAAAAAAA //Pattern to fill UNUSED stack
#define BOOT_COLOR_SVC 0xBBBBBBBB //Pattern to fill SVC stack
#define BOOT_COLOR_IRQ 0xCCCCCCCC //Pattern to fill IRQ stack
#define BOOT_COLOR_FIQ 0xDDDDDDDD //Pattern to fill FIQ stack
#define BOOT_COLOR_SYS 0xEEEEEEEE //Pattern to fill SYS stack
/* ========================================================================
Context save and restore macro definitions
* ======================================================================== */
/* ========================================================================*/
.macro portSAVE_CONTEXT
//Push R0 as we are going to use the register.
STMDB SP!, {R0}
MRS R0, spsr
AND R0, R0, #0x1F
CMP R0, #0x1F
BNE 10f
//Set R0 to point to the task stack pointer.
STMDB SP, {SP}^
NOP
SUB SP, SP, #4
LDMIA SP!, {R0}
//Push the return address onto the stack.
STMDB R0!, {LR}
//Now we have saved LR we can use it instead of R0.
MOV LR, R0
//Pop R0 so we can save it onto the system mode stack.
LDMIA SP!, {R0}
//Push all the system mode registers onto the task stack.
STMDB LR, {R0-R14}^
NOP
NOP
SUB LR, LR, #60
//Push the SPSR onto the task stack.
MRS R0, SPSR
STMDB LR!, {R0}
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB LR!, {R0}
//Store the new top of stack for the task.
LDR R0, =pxCurrentTCB
LDR R0, [R0]
STR LR, [R0]
B 11f
10:
LDMIA SP!, {R0}
STMDB r13!, {r0-r12,r14}
NOP
NOP
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB r13!, {R0}
LDR R0, =pxCurrentTCB
LDR R0, [R0]
STMDB r13!, {R0}
SUB r13, r13, #8
11:
MOV R0, R0
.endm
/* ========================================================================*/
.macro portRESTORE_CONTEXT
MRS R0, spsr
AND R0, R0, #0x1F
CMP R0, #0x1F
BNE 20f
//Set the LR to the task stack.
LDR R0, =pxCurrentTCB
LDR R0, [R0]
LDR LR, [R0]
//The critical nesting depth is the first item on the stack.
//Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
//Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
//Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
NOP
//Restore the return address.
LDR LR, [LR, #+60]
//And return - correcting the offset in the LR to obtain the
//correct address.
SUBS PC, LR, #4
20:
ADD r13, r13, #0x8
LDR R0, =pxCurrentTCB
LDMFD r13!, {R1}
STR R1, [R0]
LDR R0, =ulCriticalNesting
LDMFD r13!, {R1}
STR R1, [R0]
LDMIA r13!, {r0-r12,r14}
NOP
NOP
SUBS pc, r14, #0x4
.endm
/* ========================================================================*/
.macro firstRESTORE_CONTEXT
//Set the LR to the task stack.
LDR R0, =pxCurrentTCB
LDR R0, [R0]
LDR LR, [R0]
//The critical nesting depth is the first item on the stack.
//Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
//Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
//Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
NOP
//Restore the return address.
LDR LR, [LR, #+60]
//And return - correcting the offset in the LR to obtain the
//correct address.
SUBS PC, LR, #4
.endm
/* ========================================================================
* Macro for switching ARM mode
*/
.macro BOOT_CHANGE_MODE, mode, mode_mask
MRS R0, CPSR
BIC R0, R0, #\mode_mask
ORR R0, R0, #\mode
MSR CPSR_c, R0
.endm
/* ========================================================================
* Macro for setting the stack
*/
.macro BOOT_SET_STACK, stackStart, stackLen, color
LDR R0, \stackStart
LDR R1, \stackLen
ADD R1, R1, R0
MOV SP, R1 //Set stack pointer
LDR R2, =\color
3:
CMP R0, R1 //End of stack?
STRLT R2, [r0] //Colorize stack word
ADDLT R0, R0, #4
BLT 3b //branch to previous local label
.endm
.section .data
.align 3
.global und_stack_start
und_stack_start:
.space _UND_STACK_SIZE_
.align 3
.global abt_stack_start
abt_stack_start:
.space _ABT_STACK_SIZE_
.align 3
.global fiq_stack_start
fiq_stack_start:
.space _FIQ_STACK_SIZE_
.align 3
.global irq_stack_start
irq_stack_start:
.space _IRQ_STACK_SIZE_
.align 3
.global sys_stack_start
sys_stack_start:
.space _SYS_STACK_SIZE_
.align 3
.global svc_stack_start
svc_stack_start:
.space _SVC_STACK_SIZE_
/* ========================================================================
* Functions
* ========================================================================
* Function to handle reset vector
*/
.globl boot_reset
.section ".boot", "ax"
boot_reset:
//Disable IRQ and FIQ before starting anything
MRS R0, CPSR
ORR R0, R0, #0xC0
MSR CPSR_c, R0
//Setup all stacks //Note: Abt and Usr mode are not used
BOOT_CHANGE_MODE BOOT_MODE_SYS BOOT_MODE_MASK
BOOT_SET_STACK boot_stack_base_SYS boot_stack_len_SYS BOOT_COLOR_SYS
BOOT_CHANGE_MODE BOOT_MODE_ABT BOOT_MODE_MASK
BOOT_SET_STACK boot_stack_base_UNUSED boot_stack_len_UNUSED BOOT_COLOR_UNUSED
BOOT_CHANGE_MODE BOOT_MODE_UND BOOT_MODE_MASK
BOOT_SET_STACK boot_stack_base_UNUSED boot_stack_len_UNUSED BOOT_COLOR_UNUSED
BOOT_CHANGE_MODE BOOT_MODE_IRQ BOOT_MODE_MASK
BOOT_SET_STACK boot_stack_base_IRQ boot_stack_len_IRQ BOOT_COLOR_IRQ
BOOT_CHANGE_MODE BOOT_MODE_FIQ BOOT_MODE_MASK
BOOT_SET_STACK boot_stack_base_FIQ boot_stack_len_FIQ BOOT_COLOR_FIQ
//Clear FIQ banked registers while in FIQ mode
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
BOOT_CHANGE_MODE BOOT_MODE_SVC BOOT_MODE_MASK
BOOT_SET_STACK boot_stack_base_SVC boot_stack_len_SVC BOOT_COLOR_SVC
/*Stay in Supervisor Mode
copy data from binary to ram*/
BL _sysboot_copy_data_to_ram
/*Init the BSS section*/
BL _sysboot_zi_init
//==================
//Clear Registers
MOV R0, #0
MOV R1, #0
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
MOV R6, #0
MOV R7, #0
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
/* start main entry*/
B entry_main
B .
/* ========================================================================
* Globals
* ======================================================================== */
boot_stack_base_UNUSED:
.word und_stack_start
boot_stack_len_UNUSED:
.word _UND_STACK_SIZE_
boot_stack_base_IRQ:
.word irq_stack_start
boot_stack_len_IRQ:
.word _IRQ_STACK_SIZE_
boot_stack_base_SVC:
.word svc_stack_start
boot_stack_len_SVC:
.word _SVC_STACK_SIZE_
boot_stack_base_FIQ:
.word fiq_stack_start
boot_stack_len_FIQ:
.word _FIQ_STACK_SIZE_
boot_stack_base_SYS:
.word sys_stack_start
boot_stack_len_SYS:
.word _SYS_STACK_SIZE_
/*FUNCTION: _sysboot_copy_data_to_ram*/
/*DESCRIPTION: copy main stack code from FLASH/ROM to SRAM*/
_sysboot_copy_data_to_ram:
LDR R0, =_data_flash_begin
LDR R1, =_data_ram_begin
LDR R2, =_data_ram_end
4: CMP R1, R2
LDRLO R4, [R0], #4
STRLO R4, [R1], #4
BLO 4b
BX LR
/*FUNCTION: _sysboot_zi_init*/
/*DESCRIPTION: Initialise Zero-Init Data Segment*/
_sysboot_zi_init:
LDR R0, =_bss_start
LDR R1, =_bss_end
MOV R3, R1
MOV R4, R0
MOV R2, #0
5: CMP R4, R3
STRLO R2, [R4], #4
BLO 5b
BX LR
#if (CFG_SOC_NAME == SOC_BK7231N)
/*FUNCTION: _sysboot_copy_code_to_itcm*/
/*DESCRIPTION: copy itcm code from FLASH/ROM to SRAM*/
_sysboot_copy_code_to_itcm:
LDR R0, =_itcmcode_flash_begin
LDR R1, =_itcmcode_ram_begin
LDR R2, =_itcmcode_ram_end
6: CMP R1, R2
LDRLO R4, [R0], #4
STRLO R4, [R1], #4
BLO 6b
BX LR
/*FUNCTION: _sysboot_sdbss_init*/
/*DESCRIPTION: Initialise Zero-Init Data Segment of TCM */
_sysboot_tcmbss_init:
LDR R0, =_tcmbss_start
LDR R1, =_tcmbss_end
MOV R3, R1
MOV R4, R0
MOV R2, #0
8: CMP R4, R3
STRLO R2, [R4], #4
BLO 8b
BX LR
#endif
.align 5
boot_undefined:
B boot_undefined
.align 5
boot_swi:
B vPortYieldProcessor
.align 5
boot_pabort:
B boot_pabort
.align 5
boot_dabort:
B boot_dabort
.align 5
boot_reserved:
B boot_reserved
.align 5
irq_handler:
portSAVE_CONTEXT
LDR R0, =intc_irq
MOV LR, PC
BX R0
portRESTORE_CONTEXT
.align 5
fiq_handler:
portSAVE_CONTEXT
LDR R0, =intc_fiq
MOV LR, PC
BX R0
portRESTORE_CONTEXT
/*Starting the first task is just a matter of restoring the context that*/
/*was created by pxPortInitialiseStack().*/
vPortStartFirstTask:
firstRESTORE_CONTEXT
/*Manual context switch function. This is the SWI hander.*/
vPortYieldProcessor:
#if (0 == CFG_SUPPORT_BOOTLOADER)
ADD LR, LR, #4 //Add 4 to the LR to make the LR appear exactly
//as if the context was saved during and IRQ
//handler.
#endif // CFG_SUPPORT_BOOTLOADER
portSAVE_CONTEXT //Save the context of the current task...
LDR R0, =vTaskSwitchContext
MOV LR, PC
BX R0
portRESTORE_CONTEXT //Restore the context of the selected task.
.code 32
.global WFI
.type WFI,%function
WFI:
MOV R0, #0
MCR p15, 0, R0, c7, c0, 4
BX LR
/*EOF*/

134
cores/beken-7251/base/config/sys_config.h Normal file
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#pragma once
#define AT_SERVICE_CFG 0
#define BLE_DEFAULT_WIFI_REQUEST 2
#define BLE_VERSION_4_2 1
#define BLE_VERSION_5_x 2
#define BLE_WIFI_CO_REQUEST 3
#define CFG_AIRKISS_TEST 0
#define CFG_AP_MONITOR_COEXIST 0
#define CFG_AP_SUPPORT_HT_IE 0
#define CFG_BACKGROUND_PRINT 0
#define CFG_BK_AWARE 0
#define CFG_BK_AWARE_OUI "\xC8\x47\x8C"
#define CFG_BK7221_MDM_WATCHDOG_PATCH 0
#define CFG_BLE_VERSION BLE_VERSION_4_2
#define CFG_EASY_FLASH 1
#define CFG_ENABLE_BUTTON 0
#define CFG_ENABLE_DEMO_TEST 0
#define CFG_ENABLE_WPA_LOG 0
#define CFG_GENERAL_DMA 1
#define CFG_IEEE80211N 1
#define CFG_IEEE80211W 0
#define CFG_INT_WDG_ENABLED 1
#define CFG_INT_WDG_PERIOD_MS 10000
#define CFG_IPERF_TEST 0
#define CFG_JTAG_ENABLE 0
#define CFG_LESS_MEMERY_IN_RWNX 0
#define CFG_MAC_PHY_BAPASS 1
#define CFG_MSDU_RESV_HEAD_LEN 96
#define CFG_MSDU_RESV_TAIL_LEN 16
#define CFG_REAL_SDIO 0
#define CFG_RELEASE_FIRMWARE 0
#define CFG_ROLE_LAUNCH 0
#define CFG_RUNNING_PLATFORM SOC_PLATFORM
#define CFG_RWNX_QOS_MSDU 1
#define CFG_RX_SENSITIVITY_TEST 1
#define CFG_SARADC_CALIBRATE 0
#define CFG_SD_HOST_INTF SD1_HOST_INTF
#define CFG_SDIO 0
#define CFG_SDIO_TRANS 0
#define CFG_SOC_NAME SOC_BK7221U
#define CFG_SUPPOET_BSSID_CONNECT 0
#define CFG_SUPPORT_BKREG 1
#define CFG_SUPPORT_BLE 1
#define CFG_SUPPORT_BLE_MESH 0
#define CFG_SUPPORT_BSSID_CONNECT 0
#define CFG_SUPPORT_CALIBRATION 1
#define CFG_SUPPORT_CCD 0
#define CFG_SUPPORT_HID 0
#define CFG_SUPPORT_MANUAL_CALI 1
#define CFG_SUPPORT_MSD 0
#define CFG_SUPPORT_OTA_HTTP 1
#define CFG_SUPPORT_OTA_TFTP 0
#define CFG_SUPPORT_TPC_PA_MAP 1
#define CFG_SUPPORT_UVC 0
#define CFG_SYS_REDUCE_NORMAL_POWER 0
#define CFG_TASK_WDG_ENABLED 0
#define CFG_TASK_WDG_PERIOD_MS 60000
#define CFG_TCP_SERVER_TEST 0
#define CFG_TX_EVM_TEST 1
#define CFG_UART_DEBUG 0
#define CFG_UART_DEBUG_COMMAND_LINE 1
#define CFG_UDISK_MP3 0
#define CFG_USB 0
#define CFG_USE_AP_IDLE 0
#define CFG_USE_AP_PS 0
#define CFG_USE_APP_DEMO_VIDEO_TRANSFER 0
#define CFG_USE_AUD_ADC 1
#define CFG_USE_AUD_DAC 1
#define CFG_USE_AUDIO 1
#define CFG_USE_BLE_PS 1
#define CFG_USE_CAMERA_INTF 0
#define CFG_USE_DCACHE 0
#define CFG_USE_DEEP_PS 1
#define CFG_USE_DHCP 1
#define CFG_USE_FAKERTC_PS 0
#define CFG_USE_FFT 0
#define CFG_USE_FTPD_UPGRADE 0
#define CFG_USE_HSLAVE_SPI 0
#define CFG_USE_I2S 0
#define CFG_USE_IRDA 0
#define CFG_USE_LWIP_NETSTACK 1
#define CFG_USE_MCU_PS 1
#define CFG_USE_PTA 0
#define CFG_USE_QSPI 1
#define CFG_USE_SDCARD_HOST 1
#define CFG_USE_SECURITY 0
#define CFG_USE_SPI_MASTER 1
#define CFG_USE_SPI_MST_FLASH 1
#define CFG_USE_SPI_MST_PSRAM 0
#define CFG_USE_SPI_SLAVE 0
#define CFG_USE_SPIDMA 0
#define CFG_USE_STA_PS 1
#define CFG_USE_TEMPERATURE_DETECT 0
#define CFG_USE_TICK_CAL 1
#define CFG_USE_UART1 1
#define CFG_USE_USB_CHARGE 0
#define CFG_USE_USB_DEVICE 1
#define CFG_USE_USB_DEVICE_CARD_READER 1
#define CFG_USE_USB_HOST 0
#define CFG_USE_WPA_29 1
#define CFG_WFA_CERT 0
#define CFG_WIFI_RAW_TX_CMD 0
#define CFG_WIFI_SENSOR 0
#define CFG_WLAN_FAST_CONNECT 0
#define CFG_WPA_CTRL_IFACE 1
#define CFG_WPA3 0
#define CFG_XTAL_FREQUENCE CFG_XTAL_FREQUENCE_26M
#define CFG_XTAL_FREQUENCE_26M 26000000
#define CFG_XTAL_FREQUENCE_40M 40000000
#define CONFIG_APP_MP3PLAYER 0
#define FPGA_PLATFORM 0
#define OSMALLOC_STATISTICAL 0
#define RF_USE_POLICY WIFI_DEFAULT_BLE_REQUEST
#define SD_HOST_INTF 0
#define SD1_HOST_INTF 1
#define SOC_BK7221U 3
#define SOC_BK7231 1
#define SOC_BK7231N 5
#define SOC_BK7231U 2
#define SOC_PLATFORM 1
#define THD_APPLICATION_PRIORITY 3
#define THD_CORE_PRIORITY 2
#define THD_EXTENDED_APP_PRIORITY 5
#define THD_HOSTAPD_PRIORITY 5
#define THD_INIT_PRIORITY 4
#define THD_LWIP_PRIORITY 4
#define THD_MEDIA_PRIORITY 4
#define THD_RECONNECT_PRIORITY 4
#define THD_UBG_PRIORITY 5
#define THD_UMP3_PRIORITY 4
#define THD_WPAS_PRIORITY 5
#define THDD_KEY_SCAN_PRIORITY 7
#define WIFI_DEFAULT_BLE_REQUEST 1

19
cores/beken-72xx/base/config/lwipopts.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-06-27. */
#pragma once
#include "lwip-2.0.2/port/lwipopts.h"
#include <sys/time.h>
// mDNS support
#undef MEMP_NUM_UDP_PCB
#define LWIP_NUM_NETIF_CLIENT_DATA 2
#define MEMP_NUM_UDP_PCB (MAX_SOCKETS_UDP + 2 + 1)
#define ip_addr ip4_addr
#define ip_addr_t ip4_addr_t
// increase TCP/IP thread stack size (was 512)
#undef TCPIP_THREAD_STACKSIZE
#define TCPIP_THREAD_STACKSIZE 1024

8
cores/beken-72xx/base/inc/fixups/param_config.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-06-14. */
#pragma once
#include_next "param_config.h"
#undef WIFI_MAC_POS
#define WIFI_MAC_POS -1 // do not use stored MAC address by default

18
cores/beken-72xx/base/inc/fixups/uart_pub.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-06-20. */
#pragma once
#include_next "uart_pub.h"
#ifdef LIBRETUYA_ARDUINO
// make uart.c call __wrap_bk_printf() instead of bk_printf()
// standard wrapping does not work in this case, as bk_printf()
// is implemented in the same translation unit
extern void __wrap_bk_printf(const char *fmt, ...);
#undef bk_printf
#undef os_printf
#undef as_printf
// not defining bk_printf() again, as this would just change the impl name
#define os_printf __wrap_bk_printf
#define as_printf (__wrap_bk_printf("%s:%d\r\n", __FUNCTION__, __LINE__))
#endif

61
cores/beken-72xx/base/src/fixups/arch_main.c Normal file
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/**
****************************************************************************************
*
* @file arch_main.c
*
* @brief Main loop of the application.
*
* Copyright (C) Beken Corp 2011-2020
*
****************************************************************************************
*/
#include "BkDriverFlash.h"
#include "BkDriverWdg.h"
#include "driver_pub.h"
#include "func_pub.h"
#include "include.h"
#include "intc.h"
#include "param_config.h"
#include "start_type_pub.h"
#if CFG_SUPPORT_BOOTLOADER
void entry_set_world_flag(void) {
*(volatile uint32_t *)0x00400000 = 1;
}
#endif // CFG_SUPPORT_BOOTLOADER
extern void main(void);
// declare as weak to override with Arduino framework
__attribute__((weak)) void __wrap_bk_printf_disable();
__attribute__((weak)) void __wrap_bk_printf_enable();
unsigned char __bk_rf_is_init = 0;
void entry_main(void) {
// compatibility with BK7231S_1.0.5
#if CFG_SUPPORT_BOOTLOADER
entry_set_world_flag();
#endif
// suppress all output during initialization
__wrap_bk_printf_disable();
// read reboot cause into bk_misc_get_start_type()
bk_misc_init_start_type();
// register all sctrl drivers (driver/common/dd.c dd_init_tbl[])
driver_init();
// reboot the board if start_type == RESET_SOURCE_CRASH_PER_XAT0
bk_misc_check_start_type();
// init drivers
intc_init();
hal_flash_init();
cfg_param_init();
// enable watchdog
#if CFG_INT_WDG_ENABLED
bk_wdg_initialize(CFG_INT_WDG_PERIOD_MS);
bk_wdg_reload();
#endif
// enable bk_printf output again
__wrap_bk_printf_enable();
// run the app
main();
}

7
cores/beken-72xx/base/src/fixups/ate_app.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-06-14. */
#include "include.h"
uint32_t get_ate_mode_state(void) {
return 0;
}

127
cores/beken-72xx/base/src/fixups/clock_cal.c Normal file
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#include "include.h"
#include "bk_timer_pub.h"
#include "drv_model_pub.h"
#include "fake_clock_pub.h"
#include "mcu_ps_pub.h"
#include "power_save_pub.h"
#include "pwm_pub.h"
#include "sys_rtos.h"
static CAL_TICK_T cal_tick_save;
UINT32 use_cal_net = 0;
UINT32 fclk_cal_endvalue(UINT32 mode) {
UINT32 value = 1;
if (PWM_CLK_32K == mode) {
/* 32 kHz clock */
value = FCLK_DURATION_MS * 32;
} else if (PWM_CLK_26M == mode) {
/* 26 MHz clock */
value = FCLK_DURATION_MS * 26000;
}
return value;
}
#if CFG_USE_TICK_CAL
static UINT32 timer_cal_init(void) {
UINT32 fclk;
fclk = BK_TICKS_TO_MS(fclk_get_tick());
cal_tick_save.fclk_tick = fclk;
cal_tick_save.tmp1 = 0;
return 0;
}
extern int increase_tick;
static UINT32 timer_cal_tick(void) {
UINT32 fclk, tmp2;
UINT32 machw = 0;
INT32 lost;
GLOBAL_INT_DECLARATION();
GLOBAL_INT_DISABLE();
fclk = BK_TICKS_TO_MS(fclk_get_tick());
cal_tick_save.tmp1 += ONE_CAL_TIME;
tmp2 = fclk;
lost = (INT32)(cal_tick_save.tmp1 - (UINT32)tmp2);
if ((lost >= (2 * FCLK_DURATION_MS))) {
lost -= FCLK_DURATION_MS;
fclk_update_tick(BK_MS_TO_TICKS(lost));
increase_tick = 0;
} else {
if (lost <= (-(2 * FCLK_DURATION_MS))) {
if (lost < (-50000)) {
os_printf("m reset:%x %x\r\n", lost, machw);
}
increase_tick = lost + FCLK_DURATION_MS;
}
}
mcu_ps_machw_init();
GLOBAL_INT_RESTORE();
return 0;
}
static void cal_timer_hdl(UINT8 param) {
timer_cal_tick();
}
static void cal_timer_set(void) {
timer_param_t param;
UINT32 ret;
UINT32 timer_channel;
timer_cal_init();
param.channel = CAL_TIMER_ID;
param.div = 1;
param.period = ONE_CAL_TIME;
param.t_Int_Handler = cal_timer_hdl;
ret = sddev_control(TIMER_DEV_NAME, CMD_TIMER_INIT_PARAM, &param);
ASSERT(BK_TIMER_SUCCESS == ret);
timer_channel = param.channel;
ret = sddev_control(TIMER_DEV_NAME, CMD_TIMER_UNIT_ENABLE, &timer_channel);
ASSERT(BK_TIMER_SUCCESS == ret);
}
static void cal_timer_deset(void) {
UINT32 ret;
UINT32 timer_channel;
timer_channel = CAL_TIMER_ID;
ret = sddev_control(TIMER_DEV_NAME, CMD_TIMER_UNIT_DISABLE, &timer_channel);
ASSERT(BK_TIMER_SUCCESS == ret);
timer_cal_init();
}
UINT32 bk_cal_init(UINT32 setting) {
GLOBAL_INT_DECLARATION();
GLOBAL_INT_DISABLE();
if (1 == setting) {
cal_timer_deset();
use_cal_net = 1;
mcu_ps_machw_init();
os_printf("decset:%d %d %d %d\r\n", use_cal_net, fclk_get_tick(), fclk_get_second(), xTaskGetTickCount());
} else {
mcu_ps_machw_cal();
cal_timer_set();
use_cal_net = 0;
mcu_ps_machw_reset();
os_printf("cset:%d %d %d %d\r\n", use_cal_net, fclk_get_tick(), fclk_get_second(), xTaskGetTickCount());
}
GLOBAL_INT_RESTORE();
return 0;
}
#endif

125
cores/beken-72xx/base/src/fixups/clock_rtos.c Normal file
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#include "include.h"
#include "bk_timer_pub.h"
#include "drv_model_pub.h"
#include "fake_clock_pub.h"
#include "icu_pub.h"
#include "mcu_ps_pub.h"
#include "power_save_pub.h"
#include "pwm_pub.h"
#include "rtos_pub.h"
#include "sys_rtos.h"
#include "uart_pub.h"
// from LibreTuyaConfig.h
#ifndef LT_MICROS_HIGH_RES
#define LT_MICROS_HIGH_RES 1
#endif
// main FreeRTOS timer ID
static BK_HW_TIMER_INDEX fclk_id = BK_PWM_TIMER_ID0;
extern UINT32 bk_cal_init(UINT32 setting);
extern void mcu_ps_increase_clr(void);
extern uint32_t preempt_delayed_schedule_get_flag(void);
extern void preempt_delayed_schedule_clear_flag(void);
// forward definitions
static void fclk_timer_hw_init(BK_HW_TIMER_INDEX timer_id);
static void fclk_hdl(UINT8 param);
void fclk_init(void) {
#if (CFG_SOC_NAME == SOC_BK7231)
fclk_timer_hw_init(BK_PWM_TIMER_ID0);
#elif LT_MICROS_HIGH_RES
fclk_timer_hw_init(BK_TIMER_ID0);
#else
fclk_timer_hw_init(BK_TIMER_ID3);
#endif
#if CFG_USE_TICK_CAL
bk_cal_init(0);
#endif
}
/* timer_id: BK_PWM_TIMER_ID0 or BK_TIMER_ID3 */
static void fclk_timer_hw_init(BK_HW_TIMER_INDEX timer_id) {
#if (CFG_SOC_NAME == SOC_BK7231)
ASSERT(timer_id >= BK_PWM_TIMER_ID0);
#endif
fclk_id = timer_id;
if (fclk_id >= BK_PWM_TIMER_ID0) { // pwm timer
pwm_param_t param;
param.channel = (fclk_id - PWM0);
param.cfg.bits.en = PWM_ENABLE;
param.cfg.bits.int_en = PWM_INT_EN;
param.cfg.bits.mode = PWM_TIMER_MODE;
param.cfg.bits.clk = PWM_CLK_26M;
param.p_Int_Handler = fclk_hdl;
#if (CFG_SOC_NAME == SOC_BK7231N)
param.duty_cycle1 = 0;
#else
param.duty_cycle = 0;
#endif
param.end_value = fclk_cal_endvalue((UINT32)param.cfg.bits.clk);
sddev_control(PWM_DEV_NAME, CMD_PWM_INIT_PARAM, &param);
} else { // timer
timer_param_t param;
param.channel = fclk_id;
param.div = 1;
#if LT_MICROS_HIGH_RES
param.period = FCLK_DURATION_MS * 1000;
#else
param.period = FCLK_DURATION_MS;
#endif
param.t_Int_Handler = fclk_hdl;
#if LT_MICROS_HIGH_RES
UINT32 ret = sddev_control(TIMER_DEV_NAME, CMD_TIMER_INIT_PARAM_US, &param);
#else
UINT32 ret = sddev_control(TIMER_DEV_NAME, CMD_TIMER_INIT_PARAM, &param);
#endif
ASSERT(BK_TIMER_SUCCESS == ret);
sddev_control(TIMER_DEV_NAME, CMD_TIMER_UNIT_ENABLE, &param.channel);
}
}
static void fclk_hdl(UINT8 param) {
#if CFG_USE_TICK_CAL
if (!mcu_ps_need_pstick())
return;
#endif
GLOBAL_INT_DECLARATION();
GLOBAL_INT_DISABLE();
if (xTaskIncrementTick() != pdFALSE || preempt_delayed_schedule_get_flag()) {
preempt_delayed_schedule_clear_flag();
/* Select a new task to run. */
vTaskSwitchContext();
}
GLOBAL_INT_RESTORE();
}
UINT32 fclk_update_tick(UINT32 tick) {
GLOBAL_INT_DECLARATION();
if (tick == 0)
return 0;
GLOBAL_INT_DISABLE();
mcu_ps_increase_clr();
vTaskStepTick(tick);
GLOBAL_INT_RESTORE();
return 0;
}
UINT64 fclk_get_tick(void) {
return xTaskGetTickCount();
}
UINT32 fclk_get_second(void) {
return xTaskGetTickCount() / FCLK_SECOND;
}
BK_HW_TIMER_INDEX fclk_get_tick_id(void) {
return fclk_id;
}

420
cores/beken-72xx/base/src/fixups/intc.c Normal file
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/**
****************************************************************************************
*
* @file intc.c
*
* @brief Definition of the Interrupt Controller (INTCTRL) API.
*
* Copyright (C) RivieraWaves 2011-2016
*
****************************************************************************************
*/
/*
* INCLUDE FILES
****************************************************************************************
*/
#include "compiler.h"
#include "intc.h"
#include "intc_pub.h"
#include "include.h"
#include "arm_arch.h"
#include "drv_model_pub.h"
#include "icu_pub.h"
#include "mem_pub.h"
#include "uart_pub.h"
#include "power_save_pub.h"
#include "start_type_pub.h"
ISR_T _isrs[INTC_MAX_COUNT] = {{{0, 0}},};
static UINT32 isrs_mask = 0;
static ISR_LIST_T isr_hdr = {{&isr_hdr.isr, &isr_hdr.isr},};
void intc_hdl_entry(UINT32 int_status)
{
UINT32 i;
ISR_T *f;
UINT32 status;
LIST_HEADER_T *n;
LIST_HEADER_T *pos;
status = int_status & isrs_mask;
INTC_PRT("intc:%x:%x\r\n", int_status, status);
#if CFG_USE_STA_PS
power_save_dtim_wake(status);
#endif
list_for_each_safe(pos, n, &isr_hdr.isr)
{
f = list_entry(pos, ISR_T, list);
i = f->int_num;
if ((BIT(i) & status))
{
f->isr_func();
status &= ~(BIT(i));
}
if(0 == status)
{
return;
}
}
}
void intc_service_register(UINT8 int_num, UINT8 int_pri, FUNCPTR isr)
{
LIST_HEADER_T *pos, *n;
ISR_T *tmp_ptr, *cur_ptr;
ISR_T buf_ele;
GLOBAL_INT_DECLARATION();
buf_ele = _isrs[int_num];
cur_ptr = &_isrs[int_num];
cur_ptr->isr_func = isr;
cur_ptr->int_num = int_num;
cur_ptr->pri = int_pri;
INTC_PRT("reg_isr:%d:%d:%p\r\n", int_num, int_pri, isr);
GLOBAL_INT_DISABLE();
if (list_empty(&isr_hdr.isr))
{
list_add_head(&cur_ptr->list, &isr_hdr.isr);
goto ok;
}
/* Insert the ISR to the function list, this list is sorted by priority number */
list_for_each_safe(pos, n, &isr_hdr.isr)
{
tmp_ptr = list_entry(pos, ISR_T, list);
if (int_pri < tmp_ptr->pri)
{
/* add entry at the head of the queue */
list_add_tail(&cur_ptr->list, &tmp_ptr->list);
INTC_PRT("reg_isr_o1\r\n");
goto ok;
}
else if (int_pri == tmp_ptr->pri)
{
INTC_PRT("reg_isr_error\r\n");
goto error;
}
}
list_add_tail(&cur_ptr->list, &isr_hdr.isr);
INTC_PRT("reg_isr_o2\r\n");
ok:
isrs_mask |= BIT(int_num);
GLOBAL_INT_RESTORE();
return;
error:
/* something wrong */
_isrs[int_num] = buf_ele;
GLOBAL_INT_RESTORE();
return;
}
void intc_service_change_handler(UINT8 int_num, FUNCPTR isr)
{
LIST_HEADER_T *pos, *n;
ISR_T *tmp_ptr, *cur_ptr;
ISR_T buf_ele;
UINT8 int_pri;
GLOBAL_INT_DECLARATION();
buf_ele = _isrs[int_num];
cur_ptr = &_isrs[int_num];
int_pri = cur_ptr->pri;
if(!cur_ptr->isr_func)
return;
INTC_PRT("reg_isr:%d:%d:%p\r\n", int_num, int_pri, isr);
GLOBAL_INT_DISABLE();
if (list_empty(&isr_hdr.isr))
{
goto exit;
}
/* Insert the ISR to the function list, this list is sorted by priority number */
list_for_each_safe(pos, n, &isr_hdr.isr)
{
tmp_ptr = list_entry(pos, ISR_T, list);
if (int_pri == tmp_ptr->pri)
{
buf_ele.isr_func = isr;
break;
}
}
exit:
/* something wrong */
_isrs[int_num] = buf_ele;
GLOBAL_INT_RESTORE();
return;
}
/*
* FUNCTION DEFINITIONS
****************************************************************************************
*/
void intc_spurious(void)
{
ASSERT(0);
}
void intc_enable(int index)
{
UINT32 param;
param = (1UL << index);
sddev_control(ICU_DEV_NAME, CMD_ICU_INT_ENABLE, &param);
}
void intc_disable(int index)
{
UINT32 param;
param = (1UL << index);
sddev_control(ICU_DEV_NAME, CMD_ICU_INT_DISABLE, &param);
}
void rf_ps_wakeup_isr_idle_int_cb(void)
{
#if ( CONFIG_APP_MP3PLAYER == 1 )
UINT32 irq_status;
irq_status = sddev_control(ICU_DEV_NAME, CMD_GET_INTR_STATUS, 0);
if(irq_status & 1<<IRQ_I2S_PCM)
{
irq_status &= 1<<IRQ_I2S_PCM;
i2s_isr();
sddev_control(ICU_DEV_NAME, CMD_CLR_INTR_STATUS, &irq_status);
}
#endif
}
void intc_irq(void)
{
UINT32 irq_status;
irq_status = icu_ctrl(CMD_GET_INTR_STATUS, 0);
irq_status = irq_status & 0xFFFF;
if(0 == irq_status)
{
#if (! CFG_USE_STA_PS)
os_printf("irq:dead\r\n");
#endif
}
icu_ctrl(CMD_CLR_INTR_STATUS, &irq_status);
intc_hdl_entry(irq_status);
}
void intc_fiq(void)
{
UINT32 fiq_status;
fiq_status = icu_ctrl(CMD_GET_INTR_STATUS, 0);
fiq_status = fiq_status & 0xFFFF0000;
icu_ctrl(CMD_CLR_INTR_STATUS, &fiq_status);
intc_hdl_entry(fiq_status);
}
#if (CFG_SUPPORT_ALIOS)
void deafult_swi(void)
{
while(1);
}
#endif
void intc_init(void)
{
UINT32 param;
#if !CFG_SUPPORT_BOOTLOADER
*((volatile uint32_t *)0x400000) = (uint32_t)&do_irq;
*((volatile uint32_t *)0x400004) = (uint32_t)&do_fiq;
*((volatile uint32_t *)0x400008) = (uint32_t)&do_swi;
*((volatile uint32_t *)0x40000c) = (uint32_t)&do_undefined;
*((volatile uint32_t *)0x400010) = (uint32_t)&do_pabort;
*((volatile uint32_t *)0x400014) = (uint32_t)&do_dabort;
*((volatile uint32_t *)0x400018) = (uint32_t)&do_reserved;
#endif
intc_enable(FIQ_MAC_GENERAL);
intc_enable(FIQ_MAC_PROT_TRIGGER);
intc_enable(FIQ_MAC_TX_TRIGGER);
intc_enable(FIQ_MAC_RX_TRIGGER);
intc_enable(FIQ_MAC_TX_RX_MISC);
intc_enable(FIQ_MAC_TX_RX_TIMER);
intc_enable(FIQ_MODEM);
param = GINTR_FIQ_BIT | GINTR_IRQ_BIT;
sddev_control(ICU_DEV_NAME, CMD_ICU_GLOBAL_INT_ENABLE, &param);
return;
}
void intc_deinit(void)
{
UINT32 param;
for( int i = 0; i<=FIQ_DPLL_UNLOCK; i++)
{
intc_disable(i);
}
param = GINTR_FIQ_BIT | GINTR_IRQ_BIT;
sddev_control(ICU_DEV_NAME, CMD_ICU_GLOBAL_INT_DISABLE, &param);
return;
}
void bk_cpu_shutdown(void)
{
GLOBAL_INT_DECLARATION();
os_printf("shutdown...\n");
GLOBAL_INT_DISABLE();
while(1);
GLOBAL_INT_RESTORE();
}
void bk_show_register (struct arm_registers *regs)
{
os_printf("Current regs:\n");
os_printf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
regs->r0, regs->r1, regs->r2, regs->r3);
os_printf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n",
regs->r4, regs->r5, regs->r6, regs->r7);
os_printf("r08:0x%08x r09:0x%08x r10:0x%08x\n",
regs->r8, regs->r9, regs->r10);
os_printf("fp :0x%08x ip :0x%08x\n",
regs->fp, regs->ip);
os_printf("sp :0x%08x lr :0x%08x pc :0x%08x\n",
regs->sp, regs->lr, regs->pc);
os_printf("SPSR:0x%08x\n", regs->spsr);
os_printf("CPSR:0x%08x\n", regs->cpsr);
int i;
const unsigned int *reg1;
os_printf("\nseparate regs:\n");
reg1 = (const unsigned int *)0x400024;
os_printf("SYS:cpsr r8-r14\n");
for(i=0;i<0x20>>2;i++)
{
os_printf("0x%08x\n",*(reg1 + i));
}
os_printf("IRQ:cpsr spsr r8-r14\n");
reg1 = (const unsigned int *)0x400044;
for(i=0;i<0x24>>2;i++)
{
os_printf("0x%08x\n",*(reg1 + i));
}
os_printf("FIR:cpsr spsr r8-r14\n");
reg1 = (const unsigned int *)0x400068;
for(i=0;i<0x24>>2;i++)
{
os_printf("0x%08x\n",*(reg1 + i));
}
os_printf("ABT:cpsr spsr r8-r14\n");
reg1 = (const unsigned int *)0x40008c;
for(i=0;i<0x24>>2;i++)
{
os_printf("0x%08x\n",*(reg1 + i));
}
os_printf("UND:cpsr spsr r8-r14\n");
reg1 = (const unsigned int *)0x4000b0;
for(i=0;i<0x24>>2;i++)
{
os_printf("0x%08x\n",*(reg1 + i));
}
os_printf("SVC:cpsr spsr r8-r14\n");
reg1 = (const unsigned int *)0x4000d4;
for(i=0;i<0x24>>2;i++)
{
os_printf("0x%08x\n",*(reg1 + i));
}
os_printf("\r\n");
}
void bk_trap_udef(struct arm_registers *regs)
{
#if (CFG_SOC_NAME == SOC_BK7231N)
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_UNDEFINED_VALUE & 0xffff);
#else
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_UNDEFINED_VALUE;
#endif
os_printf("undefined instruction\n");
bk_show_register(regs);
bk_cpu_shutdown();
}
void bk_trap_pabt(struct arm_registers *regs)
{
#if (CFG_SOC_NAME == SOC_BK7231N)
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_PREFETCH_ABORT_VALUE & 0xffff);
#else
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_PREFETCH_ABORT_VALUE;
#endif
os_printf("prefetch abort\n");
bk_show_register(regs);
bk_cpu_shutdown();
}
void bk_trap_dabt(struct arm_registers *regs)
{
#if (CFG_SOC_NAME == SOC_BK7231N)
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_DATA_ABORT_VALUE & 0xffff);
#else
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_DATA_ABORT_VALUE;
#endif
os_printf("data abort\n");
bk_show_register(regs);
bk_cpu_shutdown();
}
void bk_trap_resv(struct arm_registers *regs)
{
#if (CFG_SOC_NAME == SOC_BK7231N)
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_UNUSED_VALUE & 0xffff);
#else
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_UNUSED_VALUE;
#endif
os_printf("not used\n");
bk_show_register(regs);
bk_cpu_shutdown();
}
/// @}

127
cores/beken-72xx/base/src/wraps/BkDriverFlash.c Normal file
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@@ -0,0 +1,127 @@
/* Copyright (c) Kuba Szczodrzyński 2022-07-07. */
#include "BkDriverFlash.h"
#include "drv_model_pub.h"
#include "uart_pub.h"
static const bk_logic_partition_t bk7231_partitions[BK_PARTITION_MAX] = {
{
.partition_owner = BK_FLASH_EMBEDDED,
.partition_description = "Bootloader",
.partition_start_addr = FLASH_BOOTLOADER_OFFSET,
.partition_length = FLASH_BOOTLOADER_LENGTH,
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
{
.partition_owner = BK_FLASH_EMBEDDED,
.partition_description = "Application",
.partition_start_addr = FLASH_APP_OFFSET,
.partition_length = FLASH_APP_LENGTH,
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
{
.partition_owner = BK_FLASH_EMBEDDED,
.partition_description = "ota",
.partition_start_addr = FLASH_DOWNLOAD_OFFSET,
.partition_length = FLASH_DOWNLOAD_LENGTH,
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
{
.partition_owner = BK_FLASH_EMBEDDED,
.partition_description = "RF Firmware",
.partition_start_addr = FLASH_CALIBRATION_OFFSET,
.partition_length = FLASH_CALIBRATION_LENGTH,
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
{
.partition_owner = BK_FLASH_EMBEDDED,
.partition_description = "NET info",
.partition_start_addr = FLASH_TLV_OFFSET,
.partition_length = FLASH_TLV_LENGTH,
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
};
bk_logic_partition_t *__wrap_bk_flash_get_info(bk_partition_t partition) {
if ((partition >= BK_PARTITION_BOOTLOADER) && (partition < BK_PARTITION_MAX))
return (bk_logic_partition_t *)&bk7231_partitions[partition];
return NULL;
}
OSStatus __wrap_bk_flash_erase(bk_partition_t partition, uint32_t off_set, uint32_t size) {
uint32_t i;
uint32_t param;
UINT32 status;
DD_HANDLE flash_hdl;
uint32_t start_sector, end_sector;
bk_logic_partition_t *partition_info;
GLOBAL_INT_DECLARATION();
partition_info = bk_flash_get_info(partition);
start_sector = off_set >> 12;
end_sector = (off_set + size - 1) >> 12;
flash_hdl = ddev_open(FLASH_DEV_NAME, &status, 0);
ASSERT(DD_HANDLE_UNVALID != flash_hdl);
for (i = start_sector; i <= end_sector; i++) {
param = partition_info->partition_start_addr + (i << 12);
GLOBAL_INT_DISABLE();
ddev_control(flash_hdl, CMD_FLASH_ERASE_SECTOR, (void *)&param);
GLOBAL_INT_RESTORE();
}
return kNoErr;
}
OSStatus
__wrap_bk_flash_write(bk_partition_t partition, volatile uint32_t off_set, uint8_t *inBuffer, uint32_t inBufferLength) {
UINT32 status;
DD_HANDLE flash_hdl;
uint32_t start_addr;
bk_logic_partition_t *partition_info;
GLOBAL_INT_DECLARATION();
if (NULL == inBuffer) {
os_printf("%s inBuffer=NULL\r\n", __FUNCTION__);
return kParamErr;
}
partition_info = bk_flash_get_info(partition);
if (NULL == partition_info) {
os_printf("%s partiion not found\r\n", __FUNCTION__);
return kNotFoundErr;
}
start_addr = partition_info->partition_start_addr + off_set;
flash_hdl = ddev_open(FLASH_DEV_NAME, &status, 0);
if (DD_HANDLE_UNVALID == flash_hdl) {
os_printf("%s open failed\r\n", __FUNCTION__);
return kOpenErr;
}
GLOBAL_INT_DISABLE();
ddev_write(flash_hdl, (char *)inBuffer, inBufferLength, start_addr);
GLOBAL_INT_RESTORE();
return kNoErr;
}
OSStatus
__wrap_bk_flash_read(bk_partition_t partition, volatile uint32_t off_set, uint8_t *outBuffer, uint32_t inBufferLength) {
UINT32 status;
uint32_t start_addr;
DD_HANDLE flash_hdl;
bk_logic_partition_t *partition_info;
GLOBAL_INT_DECLARATION();
if (NULL == outBuffer) {
os_printf("%s outBuffer=NULL\r\n", __FUNCTION__);
return kParamErr;
}
partition_info = bk_flash_get_info(partition);
if (NULL == partition_info) {
os_printf("%s partiion not found\r\n", __FUNCTION__);
return kNotFoundErr;
}
start_addr = partition_info->partition_start_addr + off_set;
flash_hdl = ddev_open(FLASH_DEV_NAME, &status, 0);
if (DD_HANDLE_UNVALID == flash_hdl) {
os_printf("%s open failed\r\n", __FUNCTION__);
return kOpenErr;
}
GLOBAL_INT_DISABLE();
ddev_read(flash_hdl, (char *)outBuffer, inBufferLength, start_addr);
GLOBAL_INT_RESTORE();
return kNoErr;
}

28
cores/beken-72xx/base/src/wraps/wlan_ui.c Normal file
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@@ -0,0 +1,28 @@
/* Copyright (c) Kuba Szczodrzyński 2022-07-01. */
#include <param_config.h>
#include <wlan_ui_pub.h>
// NOTE: this wrap is currently not used, as the related methods
// are in the same translation unit (wlan_ui.c), so wrapping doesn't work
extern void __real_bk_wlan_sta_init_adv(network_InitTypeDef_adv_st *inNetworkInitParaAdv);
extern sta_param_t *g_sta_param_ptr;
// enable/disable fast connect according to the config parameters
void __wrap_bk_wlan_sta_init_adv(network_InitTypeDef_adv_st *inNetworkInitParaAdv) {
// let it do the job first
__real_bk_wlan_sta_init_adv(inNetworkInitParaAdv);
// correct the parameter
bool fast_connect = false;
if (inNetworkInitParaAdv->ap_info.channel) {
// enable fast connect after finding first non-zero octet of BSSID
for (uint8_t i = 0; i < 6; i++) {
if (inNetworkInitParaAdv->ap_info.bssid[i] != 0x00) {
fast_connect = true;
break;
}
}
}
g_sta_param_ptr->fast_connect_set = fast_connect;
}

165
cores/beken-72xx/misc/bk7231_bsp.ld Normal file
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@@ -0,0 +1,165 @@
/*
* Script for GNU linker.
* Describes layout of sections, location of stack.
*
* In this case vectors are at location 0 (reset @ 0x08)
*
* +------------+ 0x00400020
* data |
* end
* |(heap) |
* . .
* . .
* |(heap limit)|
*
* |- - - - - - |
* stack bottom 256k
* +------------+
*
* +------------+ 0x0000000
* |vectors |
* | |
* |------------+
* |text |
* |data |
* | | 1024k
* +------------+
*/
/* Split memory into area for vectors and ram */
MEMORY
{
flash (rx) : ORIGIN = 0x00010000, LENGTH = 1912K
ram (rw!x): ORIGIN = 0x00400100, LENGTH = 256k - 0x100
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_vector_start);
_vector_start = ORIGIN(flash);
SECTIONS
{
/* vectors go to vectors region */
. = ORIGIN(flash);
.vectors :
{
KEEP(*(*.vectors))
KEEP( *(*.boot))
} > flash
/* instructions go to the text region*/
. = ALIGN(0x8);
/* code, instructions.for example: i=i+1; */
.text :
{
*(.text)
*(.text.*)
*(.stub)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
*(.glue_7t) *(.glue_7)
} > flash
/* read only data.for example: const int rom_data[3]={1,2,3}; */
.rodata ALIGN(8) :
{
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
} > flash
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > flash
/* globals.for example: int ram_data[3]={4,5,6}; */
/* VMA in RAM, but keep LMA in flash */
_begin_data = .;
.data : AT ( _begin_data )
{
*(.data .data.*)
*(.sdata)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
} >ram
/* Loader will copy data from _flash_begin to _ram_begin..ram_end */
_data_flash_begin = LOADADDR(.data);
_data_ram_begin = ADDR(.data);
_data_ram_end = .;
/* uninitialized data section - global int i; */
.bss ALIGN(8):
{
_bss_start = .;
*boot_handlers.O(.bss .bss.* .scommon .sbss .dynbss COMMON)
*(.bss .bss.*)
*(.scommon)
*(.sbss)
*(.dynbss)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
_bss_end = .;
} > ram /* in RAM */
. = ALIGN (8);
_empty_ram = .;
/* This symbol defines end of code/data sections. Heap starts here. */
PROVIDE(end = .);
}
GROUP(
libgcc.a
libg.a
libc.a
libm.a
libnosys.a
)

406
cores/beken-72xx/misc/bk7231n_bsp.ld Normal file
View File

@@ -0,0 +1,406 @@
/*
* Script for GNU linker.
* Describes layout of sections, location of stack.
*
* In this case vectors are at location 0 (reset @ 0x08)
*
* +------------+ 0x00400020
* data |
* end
* |(heap) |
* . .
* . .
* |(heap limit)|
*
* |- - - - - - |
* stack bottom 256k
* +------------+
*
* +------------+ 0x0000000
* |vectors |
* | |
* |------------+
* |text |
* |data |
* | | 1024k
* +------------+
*/
/* Split memory into area for vectors and ram */
MEMORY
{
flash (rx) : ORIGIN = 0x00010000, LENGTH = 1912K
tcm (rw!x): ORIGIN = 0x003F0000, LENGTH = 60k - 512
itcm (rwx): ORIGIN = 0x003FEE00, LENGTH = 4k + 512
ram (rw!x): ORIGIN = 0x00400100, LENGTH = 192k - 0x100
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_vector_start);
_vector_start = ORIGIN(flash);
SECTIONS
{
/* vectors go to vectors region */
. = ORIGIN(flash);
.vectors :
{
KEEP(*(*.vectors))
KEEP( *(*.boot))
} > flash
/* instructions go to the text region*/
. = ORIGIN(itcm);
.itcm.code ALIGN(8) :
{
/* itcm 4KB code */
*(.text.intc_hdl_entry)
*(.text.intc_irq)
*(.text.intc_fiq)
*(.text.bk_timer_isr)
*(.text.power_save_wakeup_isr)
*(.text.bmsg_rx_sender)
*(.text.bmsg_null_sender)
*(.text.fclk_get_tick)
*(.text.flash_read_sr)
*(.text.flash_write_sr)
*(.text.flash_clr_qwfr)
*(.text.set_flash_protect)
*(.text.flash_read)
*(.text.flash_read_data)
*(.text.flash_set_qe)
*(.text.flash_set_qwfr)
*(.text.flash_set_line_mode*)
*(.text.flash_get_line_mode)
*(.text.flash_write)
*(.text.flash_ctrl)
*(.text.power_save_dtim_wake)
*(.text.sctrl_fix_dpll_div)
*(.text.vTaskSuspendAll)
*(.text.xTaskGetTickCount)
*(.text.xTaskGetTickCountFromISR)
*(.text.vTaskStepTick)
*(.text.xTaskIncrementTick)
*(.text.xTaskResumeAll)
*(.text.vTaskSwitchContext)
*(.text.vApplicationIdleHook)
*(.text.platform_is_in_irq_context)
*(.text.platform_is_in_fiq_context)
*(.text.platform_is_in_interrupt_context)
*(.text.portENABLE_IRQ)
*(.text.portENABLE_FIQ)
*(.text.portDISABLE_FIQ)
*(.text.portDISABLE_IRQ)
*(.text.vPortEnterCritical)
*(.text.vPortExitCritical)
} > itcm AT>flash
_itcmcode_flash_begin = LOADADDR(.itcm.code);
_itcmcode_ram_begin = ADDR(.itcm.code);
_itcmcode_ram_end = _itcmcode_ram_begin + SIZEOF(.itcm.code);
. = ALIGN(0x8);
/* code, instructions.for example: i=i+1; */
.text :
{
*(.text)
*(.text.*)
*(.stub)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
*(.glue_7t) *(.glue_7)
} > flash
/* read only data.for example: const int rom_data[3]={1,2,3}; */
.rodata ALIGN(8) :
{
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
} > flash
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > flash
. = ORIGIN(tcm);
.tcm ALIGN(8) :
{
*apm_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*apm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_ble_init.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_ble_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_ble_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_ble.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_comm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_sdp.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_sec.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*app.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*arbitrate.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*arch_main*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ate_app*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*bam_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*bam.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*bk_timer.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*bk7011_cal*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*bk7231N_cal.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*BkDriverFlash.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble_aes.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble_main.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble_rf_port.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble_rf_xvr.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble_ui.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble_util_buf.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ble.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*chan.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*cmd_evm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*cmd_rx_sensitivity.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*comm_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*comm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*common_list.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*common_utils.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*common.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ctrl_iface.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dbg_mwsgen.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dbg_swdiag.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dbg_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dbg.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dd.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dhcp-server-main.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dhcp-server.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dhcp.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dma.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*dns.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*drv_model.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ecc_p256.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*eloop.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*etharp.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*fake_clock.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*flash.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*gapc_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*gapc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*gapm_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*gapm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*gattc_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*gattc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*hostapd*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*ip4.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*irda*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ke_env.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*kernel_event.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*kernel_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*kernel.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*l2cc_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*l2cc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*l2cm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*llc_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*llc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*lld_adv.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*lld_con.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*lld_init.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*lld_per_adv.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*lld_test.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*lld.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*llm_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*llm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*mac_phy_bypass.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*main_none.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*main_supplicant.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*manual_cal_bk7231U.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*me_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*me.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*mem_arch.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*mm_bcn.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*mm_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*mm_timer.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*mm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*net.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*netif.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*param_config.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*phy_trident*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ping.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*power_save*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*prf_utils.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*prf.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*ps.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*pwm_bk7231n.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*raw.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rf_xvr.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*role_launch.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*RomCallFlash.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rtos_pub*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rw_ieee80211.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rw_msg_rx.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rwble.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rwip_driver.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rwip.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rwip.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*rx_sensitivity.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rx_swdesc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rxl_cntrl.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rxl_hwdesc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*rxu_cntrl.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sa_ap.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sa_station.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*saradc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*scan_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*scan.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*scanu_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*scanu.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*sch_arb.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*sch_prog.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sch_slice.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*sdp_service_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sdp_service.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sm_task.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*spi*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*sta_mgmt.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*tasks.marm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*tcp_in.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*tcp.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*tcpip.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*td.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*tx_evm.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*tx_swdesc.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*uart_ble.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*uart.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*wdt.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*wlan_cli*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*wlan_ui*.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*wpa_debug.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*wpa_psk_cache.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*wpa_psk_cache.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
*wpa_supplicant.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
/* *memp.o(.bss .bss.* .scommon .sbss .dynbss COMMON) */
/* *mem.o(.bss .bss.* .scommon .sbss .dynbss COMMON) */
} >tcm AT>flash
_tcmbss_start = ADDR(.tcm);
_tcmbss_end = _tcmbss_start + SIZEOF(.tcm);
. = ORIGIN(ram);
/* globals.for example: int ram_data[3]={4,5,6}; */
/* VMA in RAM, but keep LMA in flash */
_begin_data = .;
.data :
{
*(.data .data.*)
*(.sdata)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
} >ram AT>flash
_end_data = .;
/* Loader will copy data from _flash_begin to _ram_begin..ram_end */
_data_flash_begin = LOADADDR(.data);
_data_ram_begin = ADDR(.data);
_data_ram_end = .;
/* uninitialized data section - global int i; */
.bss ALIGN(8):
{
_bss_start = .;
*boot_handlers.O(.bss .bss.* .scommon .sbss .dynbss COMMON)
*(.bss .bss.*)
*(.scommon)
*(.sbss)
*(.dynbss)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
_bss_end = .;
} > ram /* in RAM */
. = ALIGN (8);
_empty_ram = .;
/* This symbol defines end of code/data sections. Heap starts here. */
PROVIDE(end = .);
}
GROUP(
libgcc.a
libg.a
libc.a
libm.a
libnosys.a
)

48
cores/beken-72xx/misc/bk72xx.cfg Normal file
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@@ -0,0 +1,48 @@
# BK72XX OpenOCD config
# credit: @xabean at https://www.elektroda.com/rtvforum/viewtopic.php?p=20028605#20028605
# we only have CEN (aka chip enable, system reset)
reset_config srst_only
# CEN is normally pulled high, but sometimes it can help to force it high, not just low
reset_config srst_push_pull
# on connect, deassert (reset to HIGH) the SRST pin
reset_config connect_deassert_srst
# we have no TRST pin, tell OpenOCD to imagine it's tied to SRST
reset_config srst_pulls_trst
# use JTAG
transport select jtag
# 1000 kHz should work
adapter speed 1000
# wait 200ms after releasing srst before we send JTAG commands over TMS,
# we will never reset into halt because we have no tRST pin :(
adapter srst delay 200
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME bk7231t
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a little endian
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x15968001
}
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME

87
cores/common/base/config/lwipopts.h Normal file
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@@ -0,0 +1,87 @@
/* Copyright (c) Kuba Szczodrzyński 2022-08-26. */
#define LWIP_TIMEVAL_PRIVATE 0
#define LWIP_NETIF_HOSTNAME 1 // to support hostname changing
#define LWIP_SO_RCVBUF 1 // for ioctl(FIONREAD)
#define LWIP_MDNS_RESPONDER 1
#define MDNS_MAX_SERVICES 10
#include_next "lwipopts.h"
// set lwIP debugging options according to LT config
#if LT_DEBUG_LWIP
#undef LWIP_DEBUG
#define LWIP_DEBUG 1
// make lwIP use printf() library
#include <stdio.h>
#undef LWIP_PLATFORM_DIAG
// clang-format off
#define LWIP_PLATFORM_DIAG(x) do { printf x; } while (0)
// clang-format on
#endif
#if LT_DEBUG_LWIP_ASSERT
#undef LWIP_NOASSERT
#undef LWIP_PLATFORM_ASSERT
// clang-format off
#define LWIP_PLATFORM_ASSERT(x) do { printf("ASSERT \"%s\" - %s:%d\n", x, __FILE__, __LINE__); while (1) {}; } while (0)
// clang-format on
#endif
// remove family-defined debugging options (use lwIP defaults, or user-defined)
#undef ETHARP_DEBUG
#undef NETIF_DEBUG
#undef PBUF_DEBUG
#undef API_LIB_DEBUG
#undef API_MSG_DEBUG
#undef SOCKETS_DEBUG
#undef ICMP_DEBUG
#undef IGMP_DEBUG
#undef INET_DEBUG
#undef IP_DEBUG
#undef IP_REASS_DEBUG
#undef RAW_DEBUG
#undef MEM_DEBUG
#undef MEMP_DEBUG
#undef SYS_DEBUG
#undef TIMERS_DEBUG
#undef TCP_DEBUG
#undef TCP_INPUT_DEBUG
#undef TCP_FR_DEBUG
#undef TCP_RTO_DEBUG
#undef TCP_CWND_DEBUG
#undef TCP_WND_DEBUG
#undef TCP_OUTPUT_DEBUG
#undef TCP_RST_DEBUG
#undef TCP_QLEN_DEBUG
#undef UDP_DEBUG
#undef TCPIP_DEBUG
#undef SLIP_DEBUG
#undef DHCP_DEBUG
#undef AUTOIP_DEBUG
#undef DNS_DEBUG
#undef IP6_DEBUG
#undef MDNS_DEBUG
/** Set this to 1 to support DNS names (or IP address strings) to set sntp servers
* One server address/name can be defined as default if SNTP_SERVER_DNS == 1:
* \#define SNTP_SERVER_ADDRESS "pool.ntp.org"
*/
#define SNTP_SERVER_DNS 1
#define SNTP_SET_SYSTEM_TIME_US(sec, us) \
do { \
struct timeval tv = { .tv_sec = sec, .tv_usec = us }; \
settimeofday(&tv, NULL); \
} while (0);
#define SNTP_GET_SYSTEM_TIME(sec, us) \
do { \
struct timeval tv = { .tv_sec = 0, .tv_usec = 0 }; \
gettimeofday(&tv, NULL); \
(sec) = tv.tv_sec; \
(us) = tv.tv_usec; \
} while (0);

22
cores/common/base/inc/fixups/errno.h Normal file
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@@ -0,0 +1,22 @@
/* Copyright (c) Kuba Szczodrzyński 2022-06-13. */
#pragma once
// This is an attempt to bring at least some order to <errno.h>, as
// it's generally a source of problems everywhere.
// The idea is that all units will try to import this errno.h first,
// which means it won't use lwIP's error codes.
// The code below was moved from realtek-ambz/fixups during
// porting of BK72XX SDK, when the errno stroke again.
// There are two different errno's:
// - first is just an int
// - second is a macro that calls __errno()
// Here the first option is ensured in the entire project.
#include <sys/errno.h> // use system __errno() & error codes
#undef errno // undefine __errno() macro
extern int errno; // use a global errno variable
#define errno errno // for #ifdef errno in lwIP
// make sure lwIP never defines its own error codes
#undef LWIP_PROVIDE_ERRNO

5
cores/common/base/inc/fixups/lwip/errno.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-06-13. */
#pragma once
#include "../errno.h"

5
cores/common/base/inc/proxy/certs.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-06-13. */
#pragma once
#include <mbedtls/certs.h>

5
cores/common/base/inc/proxy/err.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-05-22. */
#pragma once
#include <lwip/err.h>

5
cores/common/base/inc/proxy/netdb.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-06-13. */
#pragma once
#include <lwip/netdb.h>

5
cores/common/base/inc/proxy/netif.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-07-20. */
#pragma once
#include <lwip/netif.h>

5
cores/common/base/inc/proxy/sockets.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-05-23. */
#pragma once
#include <lwip/sockets.h>

5
cores/common/base/inc/proxy/sys.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-05-22. */
#pragma once
#include <lwip/sys.h>

5
cores/common/base/inc/proxy/tcpip.h Normal file
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@@ -0,0 +1,5 @@
/* Copyright (c) Kuba Szczodrzyński 2022-05-22. */
#pragma once
#include <lwip/tcpip.h>

10
cores/common/base/inc/proxy/udp.h Normal file
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@@ -0,0 +1,10 @@
/* Copyright (c) Kuba Szczodrzyński 2022-05-23. */
#pragma once
#include <lwip/udp.h>
// this is included only by wifi_simple_config.c
// which uses lwip_ntohl without parentheses
// so the #define from lwip/def.h doesn't work
#define lwip_ntohl lwip_htonl

17
cores/realtek-amb/base/config/build_info.h Normal file
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@@ -0,0 +1,17 @@
#pragma once
#define RTL_FW_COMPILE_TIME "20020/01/01-00:00:00"
#define RTL_FW_COMPILE_DATE "20200101"
#define UTS_VERSION "2020/01/01-00:00:00"
#define RTL8195AFW_COMPILE_TIME "2020/01/01-00:00:00"
#define RTL8195AFW_COMPILE_DATE "2020/01/01"
#define RTL8195AFW_COMPILE_BY "root"
#define RTL8195AFW_COMPILE_HOST "localhost"
#define RTL8195AFW_COMPILE_DOMAIN "localhost"
#define RTL8195AFW_COMPILER "gcc"
#define RTL8710CFW_COMPILE_TIME "2020/01/01-00:00:00"
#define RTL8710CFW_COMPILE_DATE "20200101"
#define RTL8710CFW_COMPILE_BY "root"
#define RTL8710CFW_COMPILE_HOST "localhost"
#define RTL8710CFW_COMPILE_DOMAIN "localhost"
#define RTL8710CFW_COMPILER "gcc"

14
cores/realtek-amb/base/config/lwipopts.h Normal file
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@@ -0,0 +1,14 @@
/* Copyright (c) Kuba Szczodrzyński 2022-07-20. */
#pragma once
#include_next "lwipopts.h"
#define ip_addr ip4_addr // LwIP 2.0.x compatibility
#define ip_addr_t ip4_addr_t // LwIP 2.0.x compatibility
#define in_addr_t u32_t
#define IN_ADDR_T_DEFINED 1
#ifndef INT_MAX
#define INT_MAX 2147483647 // for RECV_BUFSIZE_DEFAULT
#endif

122
cores/realtek-amb/base/config/main.h Normal file
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@@ -0,0 +1,122 @@
#ifndef MAIN_H
#define MAIN_H
#include <autoconf.h>
#ifndef CONFIG_WLAN
#define CONFIG_WLAN 1
#endif
/* Header file declaration*/
void wlan_network();
/* Interactive Mode */
#define SERIAL_DEBUG_RX 1
/* WLAN and Netork */
#define STA_MODE_SSID "ap" /* Set SSID here */
#define AP_MODE_SSID "wlan_ap_ssid" /* Set SSID here */
#define AP_DEFAULT_CH 6
#define WLAN0_NAME "wlan0"
#define WLAN1_NAME "wlan1"
#define WPA_PASSPHRASE "1234567890" /* Max 32 cahracters */
#define WEP40_KEY {0x12, 0x34, 0x56, 0x78, 0x90}
#define ATVER_1 1 // For First AT command
#define ATVER_2 2 // For UART Module AT command
#if CONFIG_EXAMPLE_UART_ATCMD
#define ATCMD_VER ATVER_2
#else
#define ATCMD_VER ATVER_1
#endif
#if ATCMD_VER == ATVER_2
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
extern unsigned char sta_ip[4], sta_netmask[4], sta_gw[4];
extern unsigned char ap_ip[4], ap_netmask[4], ap_gw[4];
/*Static IP ADDRESS*/
#define IP_ADDR0 sta_ip[0]
#define IP_ADDR1 sta_ip[1]
#define IP_ADDR2 sta_ip[2]
#define IP_ADDR3 sta_ip[3]
/*NETMASK*/
#define NETMASK_ADDR0 sta_netmask[0]
#define NETMASK_ADDR1 sta_netmask[1]
#define NETMASK_ADDR2 sta_netmask[2]
#define NETMASK_ADDR3 sta_netmask[3]
/*Gateway Address*/
#define GW_ADDR0 sta_gw[0]
#define GW_ADDR1 sta_gw[1]
#define GW_ADDR2 sta_gw[2]
#define GW_ADDR3 sta_gw[3]
/*******************************************/
/*Static IP ADDRESS*/
#define AP_IP_ADDR0 ap_ip[0]
#define AP_IP_ADDR1 ap_ip[1]
#define AP_IP_ADDR2 ap_ip[2]
#define AP_IP_ADDR3 ap_ip[3]
/*NETMASK*/
#define AP_NETMASK_ADDR0 ap_netmask[0]
#define AP_NETMASK_ADDR1 ap_netmask[1]
#define AP_NETMASK_ADDR2 ap_netmask[2]
#define AP_NETMASK_ADDR3 ap_netmask[3]
/*Gateway Address*/
#define AP_GW_ADDR0 ap_gw[0]
#define AP_GW_ADDR1 ap_gw[1]
#define AP_GW_ADDR2 ap_gw[2]
#define AP_GW_ADDR3 ap_gw[3]
#else
/*Static IP ADDRESS*/
#define IP_ADDR0 192
#define IP_ADDR1 168
#define IP_ADDR2 1
#define IP_ADDR3 80
/*NETMASK*/
#define NETMASK_ADDR0 255
#define NETMASK_ADDR1 255
#define NETMASK_ADDR2 255
#define NETMASK_ADDR3 0
/*Gateway Address*/
#define GW_ADDR0 192
#define GW_ADDR1 168
#define GW_ADDR2 1
#define GW_ADDR3 1
/*******************************************/
/*Static IP ADDRESS*/
#define AP_IP_ADDR0 192
#define AP_IP_ADDR1 168
#define AP_IP_ADDR2 43
#define AP_IP_ADDR3 1
/*NETMASK*/
#define AP_NETMASK_ADDR0 255
#define AP_NETMASK_ADDR1 255
#define AP_NETMASK_ADDR2 255
#define AP_NETMASK_ADDR3 0
/*Gateway Address*/
#define AP_GW_ADDR0 192
#define AP_GW_ADDR1 168
#define AP_GW_ADDR2 43
#define AP_GW_ADDR3 1
#endif //#if ATCMD_VER == ATVER_2
#endif

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/*
FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest versions, license
and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
#include "platform_autoconf.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( uint32_t ) 1000 )
#define configSYSTICK_CLOCK_HZ 32768
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 512 )
#ifdef CONFIG_WIFI_EN
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 160 * 1024 ) )
#else
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) )
#endif
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configUSE_MUTEXES 1
#define configUSE_TIMERS 1
#define configMAX_PRIORITIES ( 11 )
#define PRIORITIE_OFFSET ( 4 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_ALTERNATIVE_API 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configGENERATE_RUN_TIME_STATS 0
#if configGENERATE_RUN_TIME_STATS
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() //( ulHighFrequencyTimerTicks = 0UL )
#define portGET_RUN_TIME_COUNTER_VALUE() xTickCount //ulHighFrequencyTimerTicks
#undef configUSE_TRACE_FACILITY
#define configUSE_TRACE_FACILITY 1
#define portCONFIGURE_STATS_PEROID_VALUE 1000 //unit Ticks
#endif
#define configTIMER_TASK_PRIORITY ( 1 )
#define configTIMER_QUEUE_LENGTH ( 10 )
#define configTIMER_TASK_STACK_DEPTH ( 512 ) //USE_MIN_STACK_SIZE modify from 512 to 256
#if (__IASMARM__ != 1)
extern void freertos_pre_sleep_processing(unsigned int *expected_idle_time);
extern void freertos_post_sleep_processing(unsigned int *expected_idle_time);
extern int freertos_ready_to_sleep();
/* Enable tickless power saving. */
#define configUSE_TICKLESS_IDLE 1
/* In wlan usage, this value is suggested to use value less than 80 milliseconds */
#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
/* It's magic trick that let us can use our own sleep function */
#define configPRE_SLEEP_PROCESSING( x ) ( freertos_pre_sleep_processing(&x) )
#define configPOST_SLEEP_PROCESSING( x ) ( freertos_post_sleep_processing(&x) )
/* It's magic trick that let us can enable/disable tickless dynamically */
#define traceLOW_POWER_IDLE_BEGIN(); do { \
if (!freertos_ready_to_sleep()) { \
mtCOVERAGE_TEST_MARKER(); \
break; \
}
// portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
#define traceLOW_POWER_IDLE_END(); } while (0);
/* It's FreeRTOS related feature but it's not included in FreeRTOS design. */
#define configUSE_WAKELOCK_PMU 1
#endif // #if (__IASMARM__ != 1)
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTimerPendFunctionCall 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
//#define RTK_MODE_TIMER
#endif /* FREERTOS_CONFIG_H */

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/* Copyright (c) Kuba Szczodrzyński 2022-07-20. */
#pragma once
#include_next "autoconf.h"

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// CHANGES:
// - 2022-05-08 undefine LWIP_PROVIDE_ERRNO
// - 2022-05-23 enable LWIP_MDNS_RESPONDER
// - 2022-05-23 set LWIP_NUM_NETIF_CLIENT_DATA to 1
// - 2022-05-23 set MEMP_NUM_UDP_PCB to 7
/**
******************************************************************************
* @file lwipopts.h
* @author MCD Application Team
* @version V1.1.0
* @date 07-October-2011
* @brief lwIP Options Configuration.
* This file is based on Utilities\lwip_v1.3.2\src\include\lwip\opt.h
* and contains the lwIP configuration for the STM32F2x7 demonstration.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
#include_next "lwipopts.h"
#include <platform/platform_stdlib.h>
#include "platform_opts.h"
#define WIFI_LOGO_CERTIFICATION_CONFIG 0 //for ping 10k test buffer setting
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 1
/* Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
should be used instead */
#define LWIP_COMPAT_MUTEX 1
#define LWIP_COMPAT_MUTEX_ALLOWED 1
#define LWIP_TCPIP_TIMEOUT 1
#define ETHARP_TRUST_IP_MAC 0
#define IP_REASSEMBLY 1
#define IP_FRAG 1
#define ARP_QUEUEING 0
/**
* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
* use lwIP facilities.
*/
#define NO_SYS 0
#ifndef CONFIG_DYNAMIC_TICKLESS
#define CONFIG_DYNAMIC_TICKLESS 0
#endif
/* ---------- Memory options ---------- */
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
byte alignment -> define MEM_ALIGNMENT to 2. */
#define MEM_ALIGNMENT 4
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
#if WIFI_LOGO_CERTIFICATION_CONFIG
#define MEM_SIZE (10*1024) //for ping 10k test
#elif CONFIG_ETHERNET
#define MEM_SIZE (6*1024) //for iperf test
#else
#define MEM_SIZE (5*1024)
#endif
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
should be set high. */
#define MEMP_NUM_PBUF 100
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
#define MEMP_NUM_UDP_PCB 7
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
#define MEMP_NUM_TCP_PCB 10
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
connections. */
#define MEMP_NUM_TCP_PCB_LISTEN 5
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
segments. */
#define MEMP_NUM_TCP_SEG 20
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts. */
#define MEMP_NUM_SYS_TIMEOUT 10
/* ---------- Pbuf options ---------- */
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
#if WIFI_LOGO_CERTIFICATION_CONFIG
#define PBUF_POOL_SIZE 30 //for ping 10k test
#else
#define PBUF_POOL_SIZE 20
#endif
/* IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.*/
#if WIFI_LOGO_CERTIFICATION_CONFIG
#define IP_REASS_MAX_PBUFS 30 //for ping 10k test
#else
#define IP_REASS_MAX_PBUFS 10
#endif
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
#define PBUF_POOL_BUFSIZE 500
/* ---------- TCP options ---------- */
#define LWIP_TCP 1
#define TCP_TTL 255
/* Controls if TCP should queue segments that arrive out of
order. Define to 0 if your device is low on memory. */
#define TCP_QUEUE_OOSEQ 1
/* TCP Maximum segment size. */
#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (5*TCP_MSS)
/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
#define TCP_SND_QUEUELEN (4* TCP_SND_BUF/TCP_MSS)
/* TCP receive window. */
#define TCP_WND (2*TCP_MSS)
/* ---------- ICMP options ---------- */
#define LWIP_ICMP 1
/* ---------- ARP options ----------- */
#define LWIP_ARP 1
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
turning this on does currently not work. */
#define LWIP_DHCP 1
/* ---------- UDP options ---------- */
#define LWIP_UDP 1
#define UDP_TTL 255
/* ---------- DNS options ---------- */
#define LWIP_DNS 1
/* ---------- UPNP options --------- */
#define LWIP_UPNP 0
/* Support Multicast */
#define LWIP_IGMP 1
#define LWIP_RAND() rand()
#define LWIP_SRAND() srand(sys_now())
/* Support TCP Keepalive */
#define LWIP_TCP_KEEPALIVE 1
/*LWIP_UART_ADAPTER==1: Enable LWIP_UART_ADAPTER when CONFIG_GAGENT is enabled,
because some GAGENT functions denpond on the following macro definitions.*/
#define LWIP_UART_ADAPTER 0
#if LWIP_UART_ADAPTER || CONFIG_ETHERNET
#undef LWIP_SO_SNDTIMEO
#define LWIP_SO_SNDTIMEO 1
#undef SO_REUSE
#define SO_REUSE 1
#undef MEMP_NUM_NETCONN
#define MEMP_NUM_NETCONN 10
#undef TCP_WND
#define TCP_WND (4*TCP_MSS)
#define TCP_KEEPIDLE_DEFAULT 10000UL
#define TCP_KEEPINTVL_DEFAULT 1000UL
#define TCP_KEEPCNT_DEFAULT 10U
#endif
#if CONFIG_EXAMPLE_UART_ATCMD || CONFIG_EXAMPLE_SPI_ATCMD
#undef LWIP_SO_SNDTIMEO
#define LWIP_SO_SNDTIMEO 1
#undef SO_REUSE
#define SO_REUSE 1
#undef SO_REUSE_RXTOALL
#define SO_REUSE_RXTOALL 1
#undef MEMP_NUM_NETCONN
#define MEMP_NUM_NETCONN 10
#undef MEMP_NUM_TCP_PCB
#define MEMP_NUM_TCP_PCB (MEMP_NUM_NETCONN)
#undef MEMP_NUM_UDP_PCB
#define MEMP_NUM_UDP_PCB (MEMP_NUM_NETCONN)
#undef TCP_WND
#define TCP_WND (4*TCP_MSS)
#define TCP_KEEPIDLE_DEFAULT 10000UL
#define TCP_KEEPINTVL_DEFAULT 1000UL
#define TCP_KEEPCNT_DEFAULT 10U
#define ERRNO 1
#endif
/* ---------- Statistics options ---------- */
#define LWIP_STATS 0
/*
--------------------------------------
---------- Checksum options ----------
--------------------------------------
*/
/*
The STM32F2x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
- To use this feature let the following define uncommented.
- To disable it and process by CPU comment the the checksum.
*/
//Do checksum by lwip - WLAN nic does not support Checksum offload
//#define CHECKSUM_BY_HARDWARE
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
#endif
/*
----------------------------------------------
---------- Sequential layer options ----------
----------------------------------------------
*/
/**
* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
*/
#define LWIP_NETCONN 1
/*
------------------------------------
---------- Socket options ----------
------------------------------------
*/
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 1
/*
-----------------------------------
---------- DEBUG options ----------
-----------------------------------
*/
#define LWIP_DEBUG 0
/*
---------------------------------
---------- OS options ----------
---------------------------------
*/
#define TCPIP_THREAD_STACKSIZE 1000
#define TCPIP_MBOX_SIZE 6
#define DEFAULT_UDP_RECVMBOX_SIZE 6
#define DEFAULT_TCP_RECVMBOX_SIZE 6
#define DEFAULT_RAW_RECVMBOX_SIZE 6
#define DEFAULT_ACCEPTMBOX_SIZE 6
#define DEFAULT_THREAD_STACKSIZE 500
#define TCPIP_THREAD_PRIO (configMAX_PRIORITIES - 2)
/* Added by Realtek */
#ifndef DNS_IGNORE_REPLY_ERR
#define DNS_IGNORE_REPLY_ERR 1
#endif /* DNS_IGNORE_REPLY_ERR */
// for mDNS support
#define LWIP_MDNS_RESPONDER 1
#define LWIP_NUM_NETIF_CLIENT_DATA 1
#endif /* __LWIPOPTS_H__ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/*
* Automatically generated by make menuconfig: don't edit
*/
#define AUTOCONF_INCLUDED
/*
* < MENUCONFIG FOR CHIP CONFIG
*/
/*
* < CONFIG CHIP
*/
#define CONFIG_RTL8711B 1
#undef ARM_CORE_CM3
#define ARM_CORE_CM4 1
#define CONFIG_CHIP_A_CUT 1
#undef CONFIG_FPGA
/*
* < CONFIG CPU CLK
*/
#define CONFIG_CPU_CLK 1
#define CONFIG_CPU_125MHZ 1
#undef CONFIG_CPU_62_5MHZ
#undef CONFIG_CPU_31_25MHZ
#undef CONFIG_CPU_15_625MHZ
#undef CONFIG_CPU_7_8125MHZ
#undef CONFIG_CPU_4MHZ
#undef CONFIG_FPGA_CLK
#define PLATFORM_CLOCK (125000000)
#define CPU_CLOCK_SEL_VALUE (0)
/*
* < CONFIG OSC8M CLK
*/
#define CONFIG_OSC8M_CLK 1
#define CONFIG_OSC8M_8388608HZ 1
#undef CONFIG_OSC8M_8192000HZ
#undef CONFIG_OSC8M_8000000HZ
#undef CONFIG_OSC8M_16777216HZ
#define OSC8M_CLOCK (8388608)
/*
* < CONFIG TEST MODE
*/
#undef CONFIG_MP
#undef CONFIG_CP
#undef CONFIG_FT
#undef CONFIG_EQC
#undef CONFIG_RTL_SIM
#undef CONFIG_POST_SIM
/*
* < CONFIG OS
*/
#define CONFIG_KERNEL 1
#define PLATFORM_FREERTOS 1
#undef PLATFORM_UCOSII
#undef PLATFORM_ECOS
#undef CONFIG_TASK_SCHEDUL_DIS
#define TASK_SCHEDULER_DISABLED (0)
/*
* < CONFIG GTIMER
*/
#define CONFIG_TIMER_EN 1
#define CONFIG_TIMER_MODULE 1
/*
* < CONFIG WDG
*/
#define CONFIG_WDG 1
#define CONFIG_WDG_MODULE 1
/*
* < CONFIG GDMA
*/
#define CONFIG_GDMA_EN 1
#define CONFIG_GDMA_MODULE 1
/*
* < CONFIG GPIO
*/
#define CONFIG_GPIO_EN 1
#define CONFIG_GPIO_MODULE 1
/*
* < CONFIG SPI
*/
#define CONFIG_SPI_COM_EN 1
#define CONFIG_SPI_COM_MODULE 1
/*
* < CONFIG UART
*/
#define CONFIG_UART_EN 1
#define CONFIG_UART_MODULE 1
/*
* < CONFIG I2C
*/
#define CONFIG_I2C_EN 1
#define CONFIG_I2C_MODULE 1
/*
* < CONFIG I2S
*/
#define CONFIG_I2S_EN 1
#define CONFIG_I2S_MODULE 1
/*
* < CONFIG SOC PS
*/
#define CONFIG_SOC_PS_EN 1
#define CONFIG_SOC_PS_MODULE 1
/*
* < CONFIG CRYPTO
*/
#define CONFIG_CRYPTO_EN 1
#define CONFIG_CRYPTO_MODULE 1
/*
* < CONFIG PWM
*/
#define CONFIG_PWM_EN 1
/*
* < CONFIG EFUSE
*/
#define CONFIG_EFUSE_EN 1
#define CONFIG_EFUSE_MODULE 1
/*
* < CONFIG SPIC
*/
#define CONFIG_SPIC_EN 1
#define CONFIG_SPIC_MODULE 1
#define CONFIG_SPIC_PHASE_CALIBATION 1
#undef CONFIG_SPIC_4BYTES_ADDRESS
/*
* < CONFIG ADC
*/
#define CONFIG_ADC_EN 1
#define CONFIG_ADC_MODULE 1
/*
* < CONFIG SDIO Device
*/
#define CONFIG_SDIO_DEVICE_EN 1
#define CONFIG_SDIO_DEVICE_NORMAL 1
#define CONFIG_SDIO_DEVICE_MODULE 1
/*
* < CONFIG USB
*/
#define CONFIG_USB_EN 1
#define CONFIG_USB_MODULE 1
/*
* < CONFIG RDP
*/
#define CONFIG_RDP_ENABLE 1
/*
* < CONFIG PINMUX
*/
#undef CONFIG_PINMAP_ENABLE
/*
* < CONFIG PER TEST
*/
#undef CONFIG_PER_TEST
/*
* < CONFIG WIFI
*/
#define CONFIG_WIFI_EN 1
#define CONFIG_WIFI_NORMAL 1
#undef CONFIG_WIFI_TEST
#define CONFIG_WIFI_MODULE 1
/*
* < CONFIG NETWORK
*/
#define CONFIG_NETWORK 1
/*
* < CONFIG INIC
*/
#undef CONFIG_INIC_EN
/*
* < CONFIG USB_NIC
*/
#undef CONFIG_USB_DONGLE_NIC_EN
/*
* < RTK STD lib
*/
#define CONFIG_RTLIB_EN 1
#define CONFIG_RTLIB_MODULE 1
#undef CONFIG_RTLIB_VERIFY
/*
* < Add MBED SDK
*/
#undef CONFIG_MBED_ENABLED
/*
* < Build App Demo
*/
#undef CONFIG_APP_DEMO
/*
* < Dhrystone
*/
#undef CONFIG_DHRYSTONE_TEST
/*
* < SSL
*/
#undef CONFIG_SSL_ROM_TEST
/*
* < System Debug Message Config
*/
#define CONFIG_UART_LOG_HISTORY 1
#define CONFIG_DEBUG_LOG 1
#define CONFIG_DEBUG_ERR_MSG 1
#undef CONFIG_DEBUG_WARN_MSG
#undef CONFIG_DEBUG_INFO_MSG
/*
* < Build Option
*/
#define CONFIG_TOOLCHAIN_ASDK 1
#undef CONFIG_TOOLCHAIN_ARM_GCC
#define CONFIG_LINK_ROM_LIB 1
#undef CONFIG_LINK_ROM_SYMB

345
cores/realtek-ambz/base/config/platform_opts.h Normal file
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// CHANGES:
// - 2022-05-08 change CONFIG_USE_POLARSSL to CONFIG_USE_MBEDTLS
// - 2022-05-08 use static int errno
// - 2022-05-18 include lwip/init.h
// - 2022-06-13 extract errno to common/fixups/errno.h
/**
******************************************************************************
*This file contains general configurations for ameba platform
******************************************************************************
*/
#ifndef __PLATFORM_OPTS_H__
#define __PLATFORM_OPTS_H__
#include "platform_autoconf.h"
#include <lwip/init.h>
/*For MP mode setting*/
//#define SUPPORT_MP_MODE 1
/**
* For AT cmd Log service configurations
*/
#define SUPPORT_LOG_SERVICE 1
#if SUPPORT_LOG_SERVICE
#define LOG_SERVICE_BUFLEN 100 //can't larger than UART_LOG_CMD_BUFLEN(127)
#define CONFIG_LOG_HISTORY 0
#if CONFIG_LOG_HISTORY
#define LOG_HISTORY_LEN 5
#endif
#define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode
#define CONFIG_LOG_SERVICE_LOCK 0
#endif
/* For DCT example*/
#define CONFIG_EXAMPLE_DCT 0
/**
* For interactive mode configurations, depents on log service
*/
#if SUPPORT_INTERACTIVE_MODE
#define CONFIG_INTERACTIVE_MODE 1
#define CONFIG_INTERACTIVE_EXT 0
#else
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#endif
/**
* For FreeRTOS tickless configurations
*/
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act
/******************************************************************************/
/**
* For common flash usage
*/
#define AP_SETTING_SECTOR 0x000FE000
#define UART_SETTING_SECTOR 0x000FC000
#define SPI_SETTING_SECTOR 0x000FC000
#define FAST_RECONNECT_DATA (0x80000 - 0x1000)
#define FLASH_SECTOR_SIZE 0x1000
#define CONFIG_ENABLE_RDP 0
/**
* For Wlan configurations
*/
#define CONFIG_WLAN 1
#if CONFIG_WLAN
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
#define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_WEBSERVER 0
#define CONFIG_OTA_UPDATE 1
#define CONFIG_BSD_TCP 1//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#define CONFIG_AIRKISS 0//on or off tencent airkiss
#define CONFIG_UART_SOCKET 0
#define CONFIG_UART_XMODEM 0//support uart xmodem upgrade or not
#define CONFIG_TRANSPORT 0//on or off the at command for transport socket
/* For WPS and P2P */
#define CONFIG_ENABLE_WPS 0
#define CONFIG_ENABLE_WPS_DISCOVERY 0
#if CONFIG_ENABLE_P2P
#define CONFIG_ENABLE_WPS_AP 1
#undef CONFIG_WIFI_IND_USE_THREAD
#define CONFIG_WIFI_IND_USE_THREAD 1
#endif
#if (CONFIG_ENABLE_P2P && ((CONFIG_ENABLE_WPS_AP == 0) || (CONFIG_ENABLE_WPS == 0)))
#error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1"
#endif
/* For SSL/TLS */
#define CONFIG_USE_POLARSSL 0
#define CONFIG_USE_MBEDTLS 1
#if ((CONFIG_USE_POLARSSL == 0) && (CONFIG_USE_MBEDTLS == 0)) || ((CONFIG_USE_POLARSSL == 1) && (CONFIG_USE_MBEDTLS == 1))
#undef CONFIG_USE_POLARSSL
#define CONFIG_USE_POLARSSL 1
#undef CONFIG_USE_MBEDTLS
#define CONFIG_USE_MBEDTLS 0
#endif
/* For Simple Link */
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
/*For fast reconnection*/
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#define CONFIG_GAGENT 0
/*Disable CONFIG_EXAMPLE_WLAN_FAST_CONNECT when CONFIG_GAGENT is enabled,because
reconnect to previous AP is not suitable when re-configuration.
*/
#if CONFIG_GAGENT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif //end of #if CONFIG_WLAN
/*******************************************************************************/
/**
* For Ethernet configurations
*/
#define CONFIG_ETHERNET 0
#if CONFIG_ETHERNET
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#endif
/**
* For user to adjust SLEEP_INTERVAL
*/
#define CONFIG_DYNAMIC_TICKLESS 1
/*******************************************************************************/
/**
* For iNIC configurations
*/
//#define CONFIG_INIC_EN 0//enable iNIC mode
#if CONFIG_INIC_EN
#ifndef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 0
#endif
#ifndef CONFIG_INIC_SDIO_HCI
#define CONFIG_INIC_SDIO_HCI 0 //for SDIO or USB iNIC
#endif
#ifndef CONFIG_INIC_CMD_RSP
#define CONFIG_INIC_CMD_RSP 0
#endif
#ifndef CONFIG_INIC_USB_HCI
#define CONFIG_INIC_USB_HCI 0
#endif
#endif
/******************End of iNIC configurations*******************/
/* For WIFI GET BEACON FRAME example */
#define CONFIG_EXAMPLE_GET_BEACON_FRAME 0
/* For WIFI MAC MONITOR example */
#define CONFIG_EXAMPLE_WIFI_MAC_MONITOR 0
/* For HTTP CLIENT example */
#define CONFIG_EXAMPLE_HTTP_CLIENT 0
/* For MQTT example */
#define CONFIG_EXAMPLE_MQTT 0
/* For mDNS example */
#define CONFIG_EXAMPLE_MDNS 0
/* For multicast example */
#define CONFIG_EXAMPLE_MCAST 0
/* For XML example */
#define CONFIG_EXAMPLE_XML 0
/* For socket select example */
#define CONFIG_EXAMPLE_SOCKET_SELECT 0
/* For socket nonblocking connect example */
#define CONFIG_EXAMPLE_NONBLOCK_CONNECT 0
/* For socket TCP bidirectional transmission example */
#define CONFIG_EXAMPLE_SOCKET_TCP_TRX 0
/* For ssl download example */
#define CONFIG_EXAMPLE_SSL_DOWNLOAD 0
/* For http download example */
#define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0
/* For httpc example */
#define CONFIG_EXAMPLE_HTTPC 0
/* For httpd example */
#define CONFIG_EXAMPLE_HTTPD 0
/* For tcp keepalive example */
#define CONFIG_EXAMPLE_TCP_KEEPALIVE 0
/* For sntp show time example */
#define CONFIG_EXAMPLE_SNTP_SHOWTIME 0
/* For websocket client example */
#define CONFIG_EXAMPLE_WEBSOCKET 0
/* For UART Module AT command example */
#define CONFIG_EXAMPLE_UART_ATCMD 0
#if CONFIG_EXAMPLE_UART_ATCMD
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 1
#undef CONFIG_TRANSPORT
#define CONFIG_TRANSPORT 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 1600
#undef CONFIG_LOG_SERVICE_LOCK
#define CONFIG_LOG_SERVICE_LOCK 1
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
/****************** For EAP method example *******************/
#define CONFIG_EXAMPLE_EAP 0
// on/off specified eap method
#define CONFIG_ENABLE_PEAP 0
#define CONFIG_ENABLE_TLS 0
#define CONFIG_ENABLE_TTLS 0
// optional feature: whether to verify the cert of radius server
#define ENABLE_EAP_SSL_VERIFY_SERVER 0
#if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS
#define CONFIG_ENABLE_EAP
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#if CONFIG_ENABLE_TLS
#define ENABLE_EAP_SSL_VERIFY_CLIENT 1
#else
#define ENABLE_EAP_SSL_VERIFY_CLIENT 0
#endif
/******************End of EAP configurations*******************/
/* For iNIC host example*/
#ifdef CONFIG_INIC_GSPI_HOST //this flag is defined in IAR project
#define CONFIG_EXAMPLE_INIC_GSPI_HOST 1
#if CONFIG_EXAMPLE_INIC_GSPI_HOST
#define CONFIG_INIC_HOST 1
#undef CONFIG_WLAN
#define CONFIG_WLAN 0
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#undef CONFIG_BSD_TCP
#define CONFIG_BSD_TCP 1
#endif
#endif
/*For uart update example*/
#define CONFIG_UART_UPDATE 0
#if CONFIG_UART_UPDATE
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
/* For uart adapter example */
/* Please also configure LWIP_UART_ADAPTER to 1
in lwip_opt.h for support uart adapter*/
#define CONFIG_EXAMPLE_UART_ADAPTER 0
#if CONFIG_EXAMPLE_UART_ADAPTER
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#undef CONFIG_EXAMPLE_MDNS
#define CONFIG_EXAMPLE_MDNS 1
#endif
/* For wifi scenarios example (Wi-Fi, WPS enrollee, P2P GO) */
// also need to enable WPS and P2P
#define CONFIG_EXAMPLE_WLAN_SCENARIO 0
/* For broadcast example */
#define CONFIG_EXAMPLE_BCAST 0
/* For high-load memory use case memory usage */
#define CONFIG_EXAMPLE_HIGH_LOAD_MEMORY_USE 0
/* For rarp example */
#define CONFIG_EXAMPLE_RARP 0
/* For ssl server example */
#define CONFIG_EXAMPLE_SSL_SERVER 0
#if CONFIG_QQ_LINK
#define FATFS_R_10C
#define FATFS_DISK_USB 0
#define FATFS_DISK_SD 1
#endif
#if CONFIG_ENABLE_WPS
#define WPS_CONNECT_RETRY_COUNT 4
#define WPS_CONNECT_RETRY_INTERVAL 5000 // in ms
#endif
#define AUTO_RECONNECT_COUNT 8
#define AUTO_RECONNECT_INTERVAL 5 // in sec
#if CONFIG_INIC_EN
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#define SUPPORT_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#define CONFIG_OTA_UPDATE 0
#endif
#endif

22
cores/realtek-ambz/base/inc/fixups/strproc.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-11-26. */
// make <strproc.h> not #define isprint, isdigit, isxdigit, islower and isspace
// this conflicts with stdlib <ctype.h>, if <strproc.h> is included before it
// include <ctype.h> before to get all its macros
#include <ctype.h>
// make 'static inline int _tolower' unused
#undef _tolower
#define _tolower _tolower_dummy
#include_next <strproc.h>
// restore _tolower to ctype's macro
#undef _tolower
#define _tolower(__c) ((unsigned char)(__c) - 'A' + 'a')
// dirty fix for compiling mbedTLS which uses _B as variable name
#ifdef CONFIG_SSL_RSA
#undef _B
#endif

5
cores/realtek-ambz/base/inc/proxy/lwip_timers.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-05-22. */
#pragma once
#include <lwip/timeouts.h>

118
cores/realtek-ambz/base/src/fixups/app_start_patch.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
// NOTE: this file has the default main() function removed.
#include "ameba_soc.h"
#include "build_info.h"
#if (defined(CONFIG_POST_SIM))
void Simulation_Init(void);
#endif
#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
extern void init_rom_wlan_ram_map(void);
extern VOID wlan_network(VOID);
#endif
#ifdef CONFIG_MBED_ENABLED
extern void __libc_fini_array (void);
extern void __libc_init_array (void);
extern void SVC_Handler (void);
extern void PendSV_Handler (void);
extern void SysTick_Handler (void);
void APP_StartMbed(void)
{
InterruptForOSInit((VOID*)SVC_Handler,
(VOID*)PendSV_Handler,
(VOID*)SysTick_Handler);
__asm (
"ldr r0, =SystemInit\n"
"blx r0\n"
"ldr r0, =_start\n"
"bx r0\n"
);
for(;;);
}
#endif
void APP_InitTrace(void)
{
u32 debug[4];
#if (defined(CONFIG_POST_SIM) || defined(CONFIG_CP))
return;
#endif
debug[LEVEL_ERROR] = BIT(MODULE_BOOT);
debug[LEVEL_WARN] = 0x0;
debug[LEVEL_INFO] = BIT(MODULE_BOOT);
debug[LEVEL_TRACE] = 0x0;
#ifdef CONFIG_DEBUG_ERR_MSG
debug[LEVEL_ERROR] = 0xFFFFFFFF;
#endif
#ifdef CONFIG_DEBUG_WARN_MSG
debug[LEVEL_WARN] = 0xFFFFFFFF;
#endif
#ifdef CONFIG_DEBUG_INFO_MSG
debug[LEVEL_INFO] = 0xFFFFFFFF;
#endif
LOG_MASK(debug);
DBG_PRINTF(MODULE_BOOT, LEVEL_INFO, "APP_InitTrace: %x:%x:%x:%x\n",debug[0], debug[1], debug[2], debug[3]);
DBG_PRINTF(MODULE_BOOT, LEVEL_ERROR, "APP_InitTrace: %x:%x:%x:%x\n",debug[0], debug[1], debug[2], debug[3]);
}
extern void main(void);
// The Main App entry point
void APP_Start(void)
{
#if CONFIG_SOC_PS_MODULE
SOCPS_InitSYSIRQ();
#endif
#ifdef CONFIG_KERNEL
#ifdef PLATFORM_FREERTOS
InterruptForOSInit((VOID*)vPortSVCHandler,
(VOID*)xPortPendSVHandler,
(VOID*)xPortSysTickHandler);
#endif
#endif
#ifdef CONFIG_MBED_ENABLED
APP_StartMbed();
#else
#if 0//def CONFIG_APP_DEMO
#ifdef PLATFORM_FREERTOS
xTaskCreate( (TaskFunction_t)main, "MAIN_APP__TASK", (2048 /4), (void *)NULL, (tskIDLE_PRIORITY + 1), NULL);
vTaskStartScheduler();
#endif
#else
#if defined ( __ICCARM__ )
__iar_cstart_call_ctors(NULL);
#endif
// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
__asm(
"mov r0, sp\n"
"bic r0, r0, #7\n"
"mov sp, r0\n"
);
main();
#endif // end of #if CONFIG_APP_DEMO
#endif // end of else of "#ifdef CONFIG_MBED_ENABLED"
}

11
cores/realtek-ambz/base/src/fixups/cmsis_ipsr.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-04-22. */
#include <stdint.h>
// for some reason, cmsis_os.c does not link properly when this method is inlined in core_cmFunc.h
// (or I am too stupid to understand this)
__attribute__((weak)) uint32_t __get_IPSR()
{
uint32_t result;
asm volatile ("MRS %0, ipsr" : "=r" (result) );
}

BIN
cores/realtek-ambz/base/src/fixups/lib_rtlstd_patch.a Normal file
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Binary file not shown.

10
cores/realtek-ambz/base/src/fixups/lib_rtlstd_patch.md Normal file
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@@ -0,0 +1,10 @@
# lib_rtlstd_patch.a
```
arm-none-eabi-gcc-ar xo lib_rtlstd.a
rm rtl_eabi_cast_ram.o
arm-none-eabi-objcopy --strip-debug --strip-unneeded ram_libc.o
arm-none-eabi-objcopy --strip-debug --strip-unneeded ram_libgloss_retarget.o
arm-none-eabi-objcopy --strip-debug --strip-unneeded rtl_math_ram.o
arm-none-eabi-gcc-ar qs lib_rtlstd_patch.a *.o
```

30
cores/realtek-ambz/base/src/fixups/log_uart.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-04-22. */
#include <ameba_soc.h>
#include <osdep_service.h>
// usage:
// extern int LOGUART_SetBaud(uint32_t BaudRate);
int LOGUART_SetBaud(uint32_t BaudRate)
{
UART_INTConfig(UART2_DEV, RUART_IER_ERBI | RUART_IER_ELSI, DISABLE);
UART_RxCmd(UART2_DEV, DISABLE);
UART_SetBaud(UART2_DEV, BaudRate);
UART_INTConfig(UART2_DEV, RUART_IER_ERBI | RUART_IER_ELSI, ENABLE);
UART_RxCmd(UART2_DEV, ENABLE);
return 1;
}
void LOGUART_SetBaud_FromFlash(void)
{
// useless, nop
}
void ReRegisterPlatformLogUart(void)
{
// useless, nop
}

739
cores/realtek-ambz/base/src/fixups/net_sockets.c Normal file
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/*
* TCP/IP or UDP/IP networking functions
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is part of mbed TLS (https://tls.mbed.org)
*/
#if !defined(MBEDTLS_CONFIG_FILE)
#include "mbedtls/config.h"
#else
#include MBEDTLS_CONFIG_FILE
#endif
#if defined(MBEDTLS_NET_C)
/*
#if !defined(unix) && !defined(__unix__) && !defined(__unix) && \
!defined(__APPLE__) && !defined(_WIN32)
#error "This module only works on Unix and Windows, see MBEDTLS_NET_C in config.h"
#endif
*/
#if defined(MBEDTLS_PLATFORM_C)
#include "mbedtls/platform.h"
#else
#include <stdlib.h>
#endif
#include "mbedtls/net_sockets.h"
#include <string.h>
#if (defined(_WIN32) || defined(_WIN32_WCE)) && !defined(EFIX64) && \
!defined(EFI32)
#ifdef _WIN32_WINNT
#undef _WIN32_WINNT
#endif
/* Enables getaddrinfo() & Co */
#define _WIN32_WINNT 0x0501
#include <ws2tcpip.h>
#include <winsock2.h>
#include <windows.h>
#if defined(_MSC_VER)
#if defined(_WIN32_WCE)
#pragma comment( lib, "ws2.lib" )
#else
#pragma comment( lib, "ws2_32.lib" )
#endif
#endif /* _MSC_VER */
#define read(fd,buf,len) recv(fd,(char*)buf,(int) len,0)
#define write(fd,buf,len) send(fd,(char*)buf,(int) len,0)
#define close(fd) closesocket(fd)
static int wsa_init_done = 0;
#elif defined(__ICCARM__) || defined(__CC_ARM) || defined ( __GNUC__ )
#include "lwip/sockets.h"
#include "lwip/inet.h"
#if LWIP_DNS
#include "lwip/netdb.h"
#endif
#include <errno.h>
#define net_htons(n) htons(n)
#define net_htonl(n) htonl(n)
#else /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#include <sys/time.h>
#include <unistd.h>
#include <signal.h>
#include <fcntl.h>
#include <netdb.h>
#include <errno.h>
#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */
/* Some MS functions want int and MSVC warns if we pass size_t,
* but the standard fucntions use socklen_t, so cast only for MSVC */
#if defined(_MSC_VER)
#define MSVC_INT_CAST (int)
#else
#define MSVC_INT_CAST
#endif
#include <stdio.h>
#include <time.h>
#include <stdint.h>
/*
* Prepare for using the sockets interface
*/
static int net_prepare( void )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
WSADATA wsaData;
if( wsa_init_done == 0 )
{
if( WSAStartup( MAKEWORD(2,0), &wsaData ) != 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
wsa_init_done = 1;
}
#else
#if !defined(EFIX64) && !defined(EFI32) && !defined(__ICCARM__) && !defined(__CC_ARM) && !defined ( __GNUC__ )
signal( SIGPIPE, SIG_IGN );
#endif
#endif
return( 0 );
}
/*
* Initialize a context
*/
void mbedtls_net_init( mbedtls_net_context *ctx )
{
ctx->fd = -1;
}
/*
* Initiate a TCP connection with host:port and the given protocol
*/
int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char *port, int proto )
{
#if defined(MBEDTLS_HAVE_IPV6)
int ret;
struct addrinfo hints, *addr_list, *cur;
if( ( ret = net_prepare() ) != 0 )
return( ret );
/* Do name resolution with both IPv6 and IPv4 */
memset( &hints, 0, sizeof( hints ) );
hints.ai_family = AF_UNSPEC;
hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM;
hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP;
if( getaddrinfo( host, port, &hints, &addr_list ) != 0 )
return( MBEDTLS_ERR_NET_UNKNOWN_HOST );
/* Try the sockaddrs until a connection succeeds */
ret = MBEDTLS_ERR_NET_UNKNOWN_HOST;
for( cur = addr_list; cur != NULL; cur = cur->ai_next )
{
ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype,
cur->ai_protocol );
if( ctx->fd < 0 )
{
ret = MBEDTLS_ERR_NET_SOCKET_FAILED;
continue;
}
if( connect( ctx->fd, cur->ai_addr, MSVC_INT_CAST cur->ai_addrlen ) == 0 )
{
ret = 0;
break;
}
close( ctx->fd );
ret = MBEDTLS_ERR_NET_CONNECT_FAILED;
}
freeaddrinfo( addr_list );
return( ret );
#else
/* Legacy IPv4-only version */
int ret;
int type, protocol;
struct sockaddr_in server_addr;
#if LWIP_DNS
struct hostent *server_host;
#endif
if( ( ret = net_prepare() ) != 0 )
return( ret );
type = ( proto == MBEDTLS_NET_PROTO_UDP ) ? SOCK_DGRAM : SOCK_STREAM;
protocol = ( proto == MBEDTLS_NET_PROTO_UDP ) ? IPPROTO_UDP : IPPROTO_TCP;
#if LWIP_DNS
if( ( server_host = gethostbyname( host ) ) == NULL )
return( MBEDTLS_ERR_NET_UNKNOWN_HOST );
if( ( ctx->fd = (int) socket( AF_INET, type, protocol ) ) < 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
memcpy( (void *) &server_addr.sin_addr,
(void *) server_host->h_addr,
server_host->h_length );
#else
if( ( ctx->fd = (int) socket( AF_INET, type, protocol ) ) < 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
server_addr.sin_len = sizeof(server_addr);
server_addr.sin_addr.s_addr = inet_addr(host);
#endif
server_addr.sin_family = AF_INET;
server_addr.sin_port = net_htons( atoi(port) );
if( connect( ctx->fd, (struct sockaddr *) &server_addr,
sizeof( server_addr ) ) < 0 )
{
close( ctx->fd );
return( MBEDTLS_ERR_NET_CONNECT_FAILED );
}
return( 0 );
#endif /* MBEDTLS_HAVE_IPV6 */
}
/*
* Create a listening socket on bind_ip:port
*/
int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto )
{
#if defined(MBEDTLS_HAVE_IPV6)
int n, ret;
struct addrinfo hints, *addr_list, *cur;
if( ( ret = net_prepare() ) != 0 )
return( ret );
/* Bind to IPv6 and/or IPv4, but only in the desired protocol */
memset( &hints, 0, sizeof( hints ) );
hints.ai_family = AF_UNSPEC;
hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM;
hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP;
if( bind_ip == NULL )
hints.ai_flags = AI_PASSIVE;
if( getaddrinfo( bind_ip, port, &hints, &addr_list ) != 0 )
return( MBEDTLS_ERR_NET_UNKNOWN_HOST );
/* Try the sockaddrs until a binding succeeds */
ret = MBEDTLS_ERR_NET_UNKNOWN_HOST;
for( cur = addr_list; cur != NULL; cur = cur->ai_next )
{
ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype,
cur->ai_protocol );
if( ctx->fd < 0 )
{
ret = MBEDTLS_ERR_NET_SOCKET_FAILED;
continue;
}
n = 1;
if( setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &n, sizeof( n ) ) != 0 )
{
close( ctx->fd );
ret = MBEDTLS_ERR_NET_SOCKET_FAILED;
continue;
}
if( bind( ctx->fd, cur->ai_addr, MSVC_INT_CAST cur->ai_addrlen ) != 0 )
{
close( ctx->fd );
ret = MBEDTLS_ERR_NET_BIND_FAILED;
continue;
}
/* Listen only makes sense for TCP */
if( proto == MBEDTLS_NET_PROTO_TCP )
{
if( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 )
{
close( ctx->fd );
ret = MBEDTLS_ERR_NET_LISTEN_FAILED;
continue;
}
}
/* I we ever get there, it's a success */
ret = 0;
break;
}
freeaddrinfo( addr_list );
return( ret );
#else
/* Legacy IPv4-only version */
int ret, n, c[4];
int type, protocol;
struct sockaddr_in server_addr;
if( ( ret = net_prepare() ) != 0 )
return( ret );
type = ( proto == MBEDTLS_NET_PROTO_UDP ) ? SOCK_DGRAM : SOCK_STREAM;
protocol = ( proto == MBEDTLS_NET_PROTO_UDP ) ? IPPROTO_UDP : IPPROTO_TCP;
if( ( ctx->fd = (int) socket( AF_INET, type, protocol ) ) < 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
n = 1;
setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &n, sizeof( n ) );
server_addr.sin_addr.s_addr = net_htonl( INADDR_ANY );
server_addr.sin_family = AF_INET;
server_addr.sin_port = net_htons( atoi(port) );
if( bind_ip != NULL )
{
memset( c, 0, sizeof( c ) );
sscanf( bind_ip, "%d.%d.%d.%d", &c[0], &c[1], &c[2], &c[3] );
for( n = 0; n < 4; n++ )
if( c[n] < 0 || c[n] > 255 )
break;
if( n == 4 )
server_addr.sin_addr.s_addr = net_htonl(
( (uint32_t) c[0] << 24 ) |
( (uint32_t) c[1] << 16 ) |
( (uint32_t) c[2] << 8 ) |
( (uint32_t) c[3] ) );
}
if( bind( ctx->fd, (struct sockaddr *) &server_addr,
sizeof( server_addr ) ) < 0 )
{
close( ctx->fd );
return( MBEDTLS_ERR_NET_BIND_FAILED );
}
/* Listen only makes sense for TCP */
if( proto == MBEDTLS_NET_PROTO_TCP )
{
if( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 )
{
close( ctx->fd );
return( MBEDTLS_ERR_NET_LISTEN_FAILED );
}
}
return( 0 );
#endif /* MBEDTLS_HAVE_IPV6 */
}
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
/*
* Check if the requested operation would be blocking on a non-blocking socket
* and thus 'failed' with a negative return value.
*/
static int net_would_block( const mbedtls_net_context *ctx )
{
((void) ctx);
return( WSAGetLastError() == WSAEWOULDBLOCK );
}
#else
/*
* Check if the requested operation would be blocking on a non-blocking socket
* and thus 'failed' with a negative return value.
*
* Note: on a blocking socket this function always returns 0!
*/
static int net_would_block( const mbedtls_net_context *ctx )
{
/*
* Never return 'WOULD BLOCK' on a non-blocking socket
*/
if( ( fcntl( ctx->fd, F_GETFL , 0 ) & O_NONBLOCK ) != O_NONBLOCK )
return( 0 );
switch( errno )
{
#if defined EAGAIN
case EAGAIN:
#endif
#if defined EWOULDBLOCK && EWOULDBLOCK != EAGAIN
case EWOULDBLOCK:
#endif
return( 1 );
}
return( 0 );
}
#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */
/*
* Accept a connection from a remote client
*/
int mbedtls_net_accept( mbedtls_net_context *bind_ctx,
mbedtls_net_context *client_ctx,
void *client_ip, size_t buf_size, size_t *ip_len )
{
int ret;
int type;
#if defined(MBEDTLS_HAVE_IPV6)
struct sockaddr_storage client_addr;
#else
struct sockaddr_in client_addr;
#endif
#if defined(__socklen_t_defined) || defined(_SOCKLEN_T) || \
defined(_SOCKLEN_T_DECLARED) || defined(__DEFINED_socklen_t)
socklen_t n = (socklen_t) sizeof( client_addr );
socklen_t type_len = (socklen_t) sizeof( type );
#else
int n = (int) sizeof( client_addr );
int type_len = (int) sizeof( type );
#endif
/* Is this a TCP or UDP socket? */
if( getsockopt( bind_ctx->fd, SOL_SOCKET, SO_TYPE,
(void *) &type, &type_len ) != 0 ||
( type != SOCK_STREAM && type != SOCK_DGRAM ) )
{
return( MBEDTLS_ERR_NET_ACCEPT_FAILED );
}
if( type == SOCK_STREAM )
{
/* TCP: actual accept() */
ret = client_ctx->fd = (int) accept( bind_ctx->fd,
(struct sockaddr *) &client_addr, &n );
}
else
{
/* UDP: wait for a message, but keep it in the queue */
char buf[1] = { 0 };
ret = (int) recvfrom( bind_ctx->fd, buf, sizeof( buf ), MSG_PEEK,
(struct sockaddr *) &client_addr, &n );
#if defined(_WIN32)
if( ret == SOCKET_ERROR &&
WSAGetLastError() == WSAEMSGSIZE )
{
/* We know buf is too small, thanks, just peeking here */
ret = 0;
}
#endif
}
if( ret < 0 )
{
if( net_would_block( bind_ctx ) != 0 )
return( MBEDTLS_ERR_SSL_WANT_READ );
return( MBEDTLS_ERR_NET_ACCEPT_FAILED );
}
/* UDP: hijack the listening socket to communicate with the client,
* then bind a new socket to accept new connections */
if( type != SOCK_STREAM )
{
#if defined(MBEDTLS_HAVE_IPV6)
struct sockaddr_storage local_addr;
#else
struct sockaddr_in local_addr;
#endif
int one = 1;
if( connect( bind_ctx->fd, (struct sockaddr *) &client_addr, n ) != 0 )
return( MBEDTLS_ERR_NET_ACCEPT_FAILED );
client_ctx->fd = bind_ctx->fd;
bind_ctx->fd = -1; /* In case we exit early */
#if defined(MBEDTLS_HAVE_IPV6)
n = sizeof( struct sockaddr_storage );
if( getsockname( client_ctx->fd,
(struct sockaddr *) &local_addr, &n ) != 0 ||
( bind_ctx->fd = (int) socket( local_addr.ss_family,
SOCK_DGRAM, IPPROTO_UDP ) ) < 0 ||
setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &one, sizeof( one ) ) != 0 )
{
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
}
#else
n = sizeof( struct sockaddr_in );
if( getsockname( client_ctx->fd,
(struct sockaddr *) &local_addr, &n ) != 0 ||
( bind_ctx->fd = (int) socket( local_addr.sin_family,
SOCK_DGRAM, IPPROTO_UDP ) ) < 0 ||
setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &one, sizeof( one ) ) != 0 )
{
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
}
#endif
if( bind( bind_ctx->fd, (struct sockaddr *) &local_addr, n ) != 0 )
{
return( MBEDTLS_ERR_NET_BIND_FAILED );
}
}
if( client_ip != NULL )
{
#if defined(MBEDTLS_HAVE_IPV6)
if( client_addr.ss_family == AF_INET )
{
struct sockaddr_in *addr4 = (struct sockaddr_in *) &client_addr;
*ip_len = sizeof( addr4->sin_addr.s_addr );
if( buf_size < *ip_len )
return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL );
memcpy( client_ip, &addr4->sin_addr.s_addr, *ip_len );
}
else
{
struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *) &client_addr;
*ip_len = sizeof( addr6->sin6_addr.s6_addr );
if( buf_size < *ip_len )
return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL );
memcpy( client_ip, &addr6->sin6_addr.s6_addr, *ip_len );
}
#else
*ip_len = sizeof( client_addr.sin_addr.s_addr );
if( buf_size < *ip_len )
return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL );
memcpy( client_ip, &client_addr.sin_addr.s_addr, *ip_len );
#endif /* MBEDTLS_HAVE_IPV6 */
}
return( 0 );
}
/*
* Set the socket blocking or non-blocking
*/
int mbedtls_net_set_block( mbedtls_net_context *ctx )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) || defined(__ICCARM__) || defined(__CC_ARM) || defined ( __GNUC__ ) ) && !defined(EFIX64) && \
!defined(EFI32)
unsigned long n = 0;
return( ioctlsocket( ctx->fd, FIONBIO, &n ) );
#else
return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL ) & ~O_NONBLOCK ) );
#endif
}
int mbedtls_net_set_nonblock( mbedtls_net_context *ctx )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) || defined(__ICCARM__) || defined(__CC_ARM) || defined ( __GNUC__ ) ) && !defined(EFIX64) && \
!defined(EFI32)
unsigned long n = 1;
return( ioctlsocket( ctx->fd, FIONBIO, &n ) );
#else
return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL ) | O_NONBLOCK ) );
#endif
}
/*
* Portable usleep helper
*/
void mbedtls_net_usleep( unsigned long usec )
{
#if defined(_WIN32)
Sleep( ( usec + 999 ) / 1000 );
#else
struct timeval tv;
tv.tv_sec = usec / 1000000;
#if defined(__unix__) || defined(__unix) || \
( defined(__APPLE__) && defined(__MACH__) )
tv.tv_usec = (suseconds_t) usec % 1000000;
#else
tv.tv_usec = usec % 1000000;
#endif
select( 0, NULL, NULL, NULL, &tv );
#endif
}
/*
* Read at most 'len' characters
*/
int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len )
{
int ret;
int fd = ((mbedtls_net_context *) ctx)->fd;
if( fd < 0 )
return( MBEDTLS_ERR_NET_INVALID_CONTEXT );
ret = (int) read( fd, buf, len );
if( ret < 0 )
{
if( net_would_block( ctx ) != 0 )
return( MBEDTLS_ERR_SSL_WANT_READ );
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
if( WSAGetLastError() == WSAECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
#else
#ifdef ERRNO
if( errno == EPIPE || errno == ECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
if( errno == EINTR )
return( MBEDTLS_ERR_SSL_WANT_READ );
#endif
#endif
return( MBEDTLS_ERR_NET_RECV_FAILED );
}
return( ret );
}
/*
* Read at most 'len' characters, blocking for at most 'timeout' ms
*/
int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len,
uint32_t timeout )
{
int ret;
struct timeval tv;
fd_set read_fds;
int fd = ((mbedtls_net_context *) ctx)->fd;
if( fd < 0 )
return( MBEDTLS_ERR_NET_INVALID_CONTEXT );
FD_ZERO( &read_fds );
FD_SET( fd, &read_fds );
tv.tv_sec = timeout / 1000;
tv.tv_usec = ( timeout % 1000 ) * 1000;
ret = select( fd + 1, &read_fds, NULL, NULL, timeout == 0 ? NULL : &tv );
/* Zero fds ready means we timed out */
if( ret == 0 )
return( MBEDTLS_ERR_SSL_TIMEOUT );
if( ret < 0 )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
if( WSAGetLastError() == WSAEINTR )
return( MBEDTLS_ERR_SSL_WANT_READ );
#else
#ifdef ERRNO
if( errno == EINTR )
return( MBEDTLS_ERR_SSL_WANT_READ );
#endif
#endif
return( MBEDTLS_ERR_NET_RECV_FAILED );
}
/* This call will not block */
return( mbedtls_net_recv( ctx, buf, len ) );
}
/*
* Write at most 'len' characters
*/
int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len )
{
int ret;
int fd = ((mbedtls_net_context *) ctx)->fd;
if( fd < 0 )
return( MBEDTLS_ERR_NET_INVALID_CONTEXT );
ret = (int) write( fd, buf, len );
if( ret < 0 )
{
if( net_would_block( ctx ) != 0 )
return( MBEDTLS_ERR_SSL_WANT_WRITE );
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
if( WSAGetLastError() == WSAECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
#else
#ifdef ERRNO
if( errno == EPIPE || errno == ECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
if( errno == EINTR )
return( MBEDTLS_ERR_SSL_WANT_WRITE );
#endif
#endif
return( MBEDTLS_ERR_NET_SEND_FAILED );
}
return( ret );
}
/*
* Gracefully close the connection
*/
void mbedtls_net_free( mbedtls_net_context *ctx )
{
if( ctx->fd == -1 )
return;
shutdown( ctx->fd, 2 );
close( ctx->fd );
ctx->fd = -1;
}
#endif /* MBEDTLS_NET_C */

7688
cores/realtek-ambz/base/src/fixups/ssl_tls.c Normal file
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6
cores/realtek-ambz/base/src/fixups/wifi_mode.c Normal file
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@@ -0,0 +1,6 @@
/* Copyright (c) Kuba Szczodrzyński 2022-04-22. */
#include <wifi_conf.h>
// wifi_mode is declared in atcmd_wifi.c, which is a part of the built-in trash console
rtw_mode_t wifi_mode = RTW_MODE_NONE;

59
cores/realtek-ambz/misc/amebaz.cfg Normal file
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@@ -0,0 +1,59 @@
# Main file for AmebaZ series Cortex-M3 parts
#
# !!!!!!
#
set CHIPNAME rtl8711b
set CHIPSERIES amebaz
transport select swd
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
error "CHIPNAME not set. Please do not include amebaz.cfg directly."
}
if { [info exists CHIPSERIES] } {
# Validate chip series is supported
if { $CHIPSERIES != "amebaz" } {
error "Unsupported chip series specified."
}
set _CHIPSERIES $CHIPSERIES
} else {
error "CHIPSERIES not set. Please do not include amebaz.cfg directly."
}
if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
# Amebaz use a Cortex M4 core.
if { $_CHIPSERIES == "amebaz" } {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _ENDIAN little
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
adapter speed 1000
adapter srst delay 200
# AmebaZ (Cortex M4 core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event reset-init {amebaz_init}

BIN
cores/realtek-ambz/misc/boot_all_10C7.bin Normal file
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BIN
cores/realtek-ambz/misc/boot_all_77F7.bin Normal file
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BIN
cores/realtek-ambz/misc/boot_all_C556.bin Normal file
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1427
cores/realtek-ambz/misc/export-rom_symbol_v01.txt Normal file
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222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip1_2M_468k_cpp.ld Normal file
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@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld Normal file
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@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip1_4M_980k_cpp.ld Normal file
View File

@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xF5000-0x20 /* XIP1: 980k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08100000+0x20, LENGTH = 0xF5000-0x20 /* XIP2: 980k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip2_2M_468k_cpp.ld Normal file
View File

@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip2_2M_cpp.ld Normal file
View File

@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip2_4M_980k_cpp.ld Normal file
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ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xF5000-0x20 /* XIP1: 980k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08100000+0x20, LENGTH = 0xF5000-0x20 /* XIP2: 980k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

299
cores/realtek-ambz2/base/config/FreeRTOSConfig.h Normal file
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/*
* FreeRTOS Kernel V10.2.0
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
See http://www.freertos.org/a00110.html for an explanation of the
definitions contained in this file.
******************************************************************************/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
* http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
/* Cortex M33 port configuration. */
#define configENABLE_MPU 0
#ifdef __ARMVFP__
#define configENABLE_FPU 1
#else
#define configENABLE_FPU 0
#endif
#if defined(CONFIG_BUILD_SECURE) || defined(CONFIG_BUILD_NONSECURE)
#define configENABLE_TRUSTZONE 1
#else
#define configENABLE_TRUSTZONE 0
#endif
/* Constants related to the behaviour or the scheduler. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configUSE_PREEMPTION 1
#define configUSE_TIME_SLICING 1
#define configTICK_RATE_HZ ( ( uint32_t ) 1000 )
#define configMAX_PRIORITIES ( 11 )
#define configIDLE_SHOULD_YIELD 1
#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
/* Constants that describe the hardware and memory usage. */
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) //number of double word
#define configMINIMAL_SECURE_STACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE*4 ) //number of byte
#define configMAX_TASK_NAME_LEN ( 10 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 160 * 1024 ) )
#define configAPPLICATION_ALLOCATED_HEAP 0
/* Constants that build features in or out. */
#define configUSE_MUTEXES 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_NEWLIB_REENTRANT 0
#define configUSE_CO_ROUTINES 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_QUEUE_SETS 1
#define configUSE_TASK_NOTIFICATIONS 1
#define configUSE_TRACE_FACILITY 0
/* Constants that define which hook (callback) functions should be used. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 1
#define secureconfigUSE_MALLOC_FAILED_HOOK 1
/* Constants provided for debugging and optimisation assistance. */
#define configCHECK_FOR_STACK_OVERFLOW 2
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH ( 10 + 32)
#define configTIMER_TASK_STACK_DEPTH ( 512 )
/* Set the following definitions to 1 to include the API function, or zero
* to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is
* only necessary if the linker does not automatically remove functions that are
* not referenced anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
#define INCLUDE_xTimerPendFunctionCall 1
/* This demo makes use of one or more example stats formatting functions. These
* format the raw data provided by the uxTaskGetSystemState() function in to
* human readable ASCII form. See the notes in the implementation of vTaskList()
* within FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.
* See the FreeRTOS+CLI documentation for more information:
* http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
/* Interrupt priority configuration follows...................... */
/* Use the system definition, if there is one. */
#ifdef __NVIC_PRIO_BITS
/* __NVIC_PRIO_BITS will be specified when CMSIS is being used. */
#if __NVIC_PRIO_BITS != 3
#error "__NVIC_PRIO_BITS is NOT correct for RTL8710C"
#endif
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 8 priority levels */
//#error "__NVIC_PRIO_BITS must be defined!"
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
* function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 7
/* The highest interrupt priority that can be used by any interrupt service
* routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT
* CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A
* HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
/* Interrupt priorities used by the kernel port layer itself. These are generic
* to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names - or at least those used in the unmodified vector table. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
/* The #ifdef guards against the file being included from IAR assembly files. */
#if !defined(__IASMARM__)
/* Constants related to the generation of run time stats. */
#define configGENERATE_RUN_TIME_STATS 0
#if configGENERATE_RUN_TIME_STATS
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE() xTickCount
#undef configUSE_TRACE_FACILITY
#define configUSE_TRACE_FACILITY 1
#define portCONFIGURE_STATS_PEROID_VALUE 1000 //unit Ticks
#endif
#include "diag.h"
#if defined(CONFIG_BUILD_SECURE) && (CONFIG_BUILD_SECURE == 1)
#define configASSERT(x) do { \
if( (x) == 0 ) { \
char *pcAssertTask = "ISR"; \
if(__get_IPSR() == 0) \
{ \
pcAssertTask = "TSK"; \
} \
dbg_printf("\n\r[%s]Assert(" #x ") failed on line %d in file %s\r\n", pcAssertTask, __LINE__, __FILE__); \
__disable_irq(); for(;;);} \
} while(0)
#else
#define configASSERT(x) do { \
if( (x) == 0 ) { \
char *pcAssertTask = "ISR"; \
if( (__get_IPSR() == 0) && (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) ) \
{ \
pcAssertTask = pcTaskGetName( NULL ); \
} \
dbg_printf("\n\r[%s]Assert(" #x ") failed on line %d in file %s\r\n", pcAssertTask, __LINE__, __FILE__); \
taskDISABLE_INTERRUPTS(); for(;;);} \
} while(0)
#endif
#define configPRINTF( x ) dbg_printf( x )
#endif /* __IASMARM__ */
/* use the low power tickless mode */
#define configUSE_TICKLESS_IDLE 0
#if defined(configUSE_TICKLESS_IDLE) && configUSE_TICKLESS_IDLE
#if !defined(__IASMARM__) || (__IASMARM__ != 1)
#if !defined(CONFIG_BUILD_SECURE) || (CONFIG_BUILD_SECURE == 0)
/* At least n further complete tick periods will pass before the kernel is due to transition an application task out of the Blocked state */
#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
/* use realtek customized low power tickless mode */
#define configUSE_CUSTOMIZED_TICKLESS_IDLE 0
#if defined(configUSE_CUSTOMIZED_TICKLESS_IDLE) && configUSE_CUSTOMIZED_TICKLESS_IDLE
extern void freertos_pre_sleep_processing(unsigned int *expected_idle_time);
extern void freertos_post_sleep_processing(unsigned int *expected_idle_time);
extern int freertos_ready_to_sleep(void);
extern void freertos_suppress_ticks_and_sleep(unsigned int xExpectedIdleTime);
/* configEXPECTED_IDLE_TIME_BEFORE_SLEEP is used for native tickless support
configEXPECTED_IDLE_TIME_BEFORE_CUSTOMIZED_SLEEP is used for realtek customized low power tickless mode
if xExpectedIdleTime < configEXPECTED_IDLE_TIME_BEFORE_CUSTOMIZED_SLEEP, system will go for native tickless mode
if xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_CUSTOMIZED_SLEEP, system will got for realtek customized tickless mode
In wlan usage, this value is suggested to use value less than 80 milliseconds */
#define configEXPECTED_IDLE_TIME_BEFORE_CUSTOMIZED_SLEEP 2
#if configEXPECTED_IDLE_TIME_BEFORE_CUSTOMIZED_SLEEP < configEXPECTED_IDLE_TIME_BEFORE_SLEEP
#error configEXPECTED_IDLE_TIME_BEFORE_CUSTOMIZED_SLEEP must not be less than configEXPECTED_IDLE_TIME_BEFORE_SLEEP
#endif
/* Enable tickless power saving. */
#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) do { \
if (freertos_ready_to_sleep() == FALSE) {\
x = 0;\
}\
} while(0)
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) do { \
freertos_suppress_ticks_and_sleep(xExpectedIdleTime); \
} while(0)
/* It's magic trick that let us can use our own sleep function */
#define configPRE_SLEEP_PROCESSING( x ) do { \
freertos_pre_sleep_processing((unsigned int *)&x); \
} while(0)
#define configPOST_SLEEP_PROCESSING( x ) do { \
freertos_post_sleep_processing((unsigned int *)&x); \
} while(0)
/* It's magic trick that let us can enable/disable tickless dynamically */
#define traceLOW_POWER_IDLE_BEGIN() do {
#define traceLOW_POWER_IDLE_END() } while (0)
/* It's FreeRTOS related feature but it's not included in FreeRTOS design. */
#define configUSE_WAKELOCK_PMU 1
#undef configMINIMAL_STACK_SIZE
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 192 )
#endif //#if defined(configUSE_CUSTOMIZED_TICKLESS_IDLE) && configUSE_CUSTOMIZED_TICKLESS_IDLE
#endif // #if !defined(CONFIG_BUILD_SECURE) || (CONFIG_BUILD_SECURE == 0)
#endif // #if !defined(__IASMARM__) || (__IASMARM__ != 1)
#endif // #if defined(configUSE_TICKLESS_IDLE) && configUSE_TICKLESS_IDLE
/* Add by Realtek to re-arrange the FreeRTOS priority*/
#define PRIORITIE_OFFSET ( 4 )
#if defined(__ICCARM__)
/* Keep below compiler pragma, below 10.2.0 remove them from portmacro.h
which will generate compiler warnings.
*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
the source code because to do so would cause other compilers to generate
warnings. */
#pragma diag_suppress=Pe191
#pragma diag_suppress=Pa082
#endif
#if defined(ENABLE_AMAZON_COMMON)
#include "FreeRTOSConfig_Amazon.h"
#endif
#endif /* FREERTOS_CONFIG_H */

5
cores/realtek-ambz2/base/config/autoconf.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-07-20. */
#pragma once
#include_next "autoconf.h"

5
cores/realtek-ambz2/base/config/lwipopts.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-07-20. */
#pragma once
#include_next "lwipopts.h"

406
cores/realtek-ambz2/base/config/platform_opts.h Normal file
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/**
******************************************************************************
*This file contains general configurations for ameba platform
******************************************************************************
*/
#ifndef __PLATFORM_OPTS_H__
#define __PLATFORM_OPTS_H__
/*For MP mode setting*/
#define SUPPORT_MP_MODE 1
/**
* For AT cmd Log service configurations
*/
#define SUPPORT_LOG_SERVICE 1
#if SUPPORT_LOG_SERVICE
#define LOG_SERVICE_BUFLEN 100 // can't larger than UART_LOG_CMD_BUFLEN(127)
#define CONFIG_LOG_HISTORY 0
#if CONFIG_LOG_HISTORY
#define LOG_HISTORY_LEN 5
#endif
#define SUPPORT_INTERACTIVE_MODE 0 // on/off wifi_interactive_mode
#define CONFIG_LOG_SERVICE_LOCK 0
#define CONFIG_ATCMD_MP 0 // support MP AT command
#define USE_MODE 1 // for test
#endif
/**
* For interactive mode configurations, depends on log service
*/
#if defined(SUPPORT_INTERACTIVE_MODE) && SUPPORT_INTERACTIVE_MODE
#define CONFIG_INTERACTIVE_MODE 1
#define CONFIG_INTERACTIVE_EXT 0
#else
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#endif
/**
* For FreeRTOS tickless configurations
*/
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act
/******************************************************************************/
/**
* For common flash usage
*/
#define FLASH_BAKEUP_SECTOR (0x3000)
#define FAST_RECONNECT_DATA (0x200000 - 0x1000)
#define BT_FTL_PHY_ADDR0 (0x200000 - 0x2000)
#define BT_FTL_PHY_ADDR1 (0x200000 - 0x3000)
#define BT_FTL_BKUP_ADDR (0x200000 - 0x4000)
#define UART_SETTING_SECTOR (0x200000 - 0x5000)
#define DCT_BEGIN_ADDR \
(0x200000 - 0x29000) /*!< DCT begin address of flash, ex: 0x200000 = 2M, the default size of DCT is 24K; ; if \
backup enabled, the size is 48k; if wear leveling enabled, the size is 144k*/
#define FLASH_APP_BASE \
(0x200000 - 0xA9000 \
) /*!< FATFS begin address, default size used is 512KB (can be adjusted based on user requirement)*/
#define BT_WHITELIST_BASE_1 (0x200000 - 0xA000)
#define BT_WHITELIST_PAGE_SIZE (0x1000)
#define BT_WHITELIST_BASE_2 (BT_WHITELIST_BASE_1 + BT_WHITELIST_PAGE_SIZE)
/**
* For Wlan configurations
*/
#define CONFIG_WLAN 1
#if CONFIG_WLAN
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 // init lwip layer when start up
#define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread
#define CONFIG_ENABLE_AP_POLLING_CLIENT_ALIVE 0 // on or off AP POLLING CLIENT
// on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_OTA_UPDATE 1
#define CONFIG_BSD_TCP 0 // NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#define CONFIG_AIRKISS 0 // on or off tencent airkiss
#define CONFIG_UART_SOCKET 0
#define CONFIG_JD_SMART 0 // on or off for jdsmart
#define CONFIG_JOYLINK 0 // on or off for jdsmart2.0
#define CONFIG_QQ_LINK 0 // on or off for qqlink
#define CONFIG_AIRKISS_CLOUD 0 // on or off for weixin hardware cloud
#define CONFIG_UART_YMODEM 0 // support uart ymodem upgrade or not
#define CONFIG_TRANSPORT 0 // on or off the at command for transport socket
#define CONFIG_ALINK 0 // on or off for alibaba alink
#define CONFIG_MIIO 0 // on or off for alibaba alink
#define CONFIG_RIC 0 // on or off for RICloud
#define CONFIG_LINKKIT_AWSS 0 // on or off for ali feiyan cloud
/* For WPS and P2P */
#define CONFIG_ENABLE_WPS 0
#define CONFIG_ENABLE_P2P 0
#if CONFIG_ENABLE_WPS
#define CONFIG_ENABLE_WPS_DISCOVERY 1
#endif
#if CONFIG_ENABLE_P2P
#define CONFIG_ENABLE_WPS_AP 1
#undef CONFIG_WIFI_IND_USE_THREAD
#define CONFIG_WIFI_IND_USE_THREAD 1
#endif
#if (CONFIG_ENABLE_P2P && ((CONFIG_ENABLE_WPS_AP == 0) || (CONFIG_ENABLE_WPS == 0)))
#error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1"
#endif
/* For Simple Link */
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
#define CONFIG_INCLUDE_DPP_CONFIG 0
/*For fast reconnection*/
#ifdef PLATFORM_OHOS
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#else
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#endif
#if CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_FAST_DHCP 1
#else
#define CONFIG_FAST_DHCP 0
#endif
/*For wowlan service settings*/
#define CONFIG_WOWLAN_SERVICE 0
#define CONFIG_GAGENT 0
/*Disable CONFIG_EXAMPLE_WLAN_FAST_CONNECT when CONFIG_GAGENT is enabled,because
reconnect to previous AP is not suitable when re-configuration.
*/
#if CONFIG_GAGENT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif // end of #if CONFIG_WLAN
/*******************************************************************************/
/* For SSL/TLS */
#define CONFIG_USE_POLARSSL 0 // polarssl is no longer suppported for AmebaZ2
#define CONFIG_USE_MBEDTLS 1
#if ((CONFIG_USE_POLARSSL == 0) && (CONFIG_USE_MBEDTLS == 0)) || \
((CONFIG_USE_POLARSSL == 1) && (CONFIG_USE_MBEDTLS == 1))
#undef CONFIG_USE_POLARSSL
#define CONFIG_USE_POLARSSL 1
#undef CONFIG_USE_MBEDTLS
#define CONFIG_USE_MBEDTLS 0
#endif
#define CONFIG_SSL_CLIENT_PRIVATE_IN_TZ 1
/* For LWIP configuration */
#define CONFIG_LWIP_DHCP_COARSE_TIMER 60
/*Enable CONFIG_LWIP_DHCP_FINE_TIMEOUT if lease time is less than or equal to CONFIG_LWIP_DHCP_COARSE_TIMER
* replace dhcp_coarse_tmr with dhcp_fine_tmr to manage and check for lease timeout
*/
#define CONFIG_LWIP_DHCP_FINE_TIMEOUT 0
/**
* For Ethernet configurations
*/
#define CONFIG_ETHERNET 0
#if CONFIG_ETHERNET
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 // init lwip layer when start up
// on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_BSD_TCP 0 // NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#endif
/* For Azure Examples */
#define CONFIG_USE_AZURE_EMBEDDED_C 1
#if CONFIG_USE_AZURE_EMBEDDED_C
/* For Azure embedded iot examples*/
#define CONFIG_EXAMPLE_AZURE 0
#if CONFIG_EXAMPLE_AZURE
#undef WAIT_FOR_ACK
#define WAIT_FOR_ACK
#endif
#else
/* For Azure iot hub telemetry example*/
#define CONFIG_EXAMPLE_AZURE_IOTHUB_TELEMETRY 0
/* For Azure iot hub x509 example*/
#define CONFIG_EXAMPLE_AZURE_IOTHUB_X509 0
#endif
/* for CoAP example*/
#define CONFIG_EXAMPLE_COAP 0
/* for lib CoAP example*/
#define CONFIG_EXAMPLE_COAP_SERVER 0
#define CONFIG_EXAMPLE_COAP_CLIENT 0
/* For WIFI GET BEACON FRAME example */
#define CONFIG_EXAMPLE_GET_BEACON_FRAME 0
/* For WIFI MAC MONITOR example */
#define CONFIG_EXAMPLE_WIFI_MAC_MONITOR 0
/* For HTTP CLIENT example */
#define CONFIG_EXAMPLE_HTTP_CLIENT 0
/* For MQTT example */
#define CONFIG_EXAMPLE_MQTT 0
/* For multicast example */
#define CONFIG_EXAMPLE_MCAST 0
/* For XML example */
#define CONFIG_EXAMPLE_XML 0
/* For JSON example */
#define CONFIG_EXAMPLE_CJSON 0
/* For socket select example */
#define CONFIG_EXAMPLE_SOCKET_SELECT 0
/* For socket nonblocking connect example */
#define CONFIG_EXAMPLE_NONBLOCK_CONNECT 0
/* For socket TCP bidirectional transmission example */
#define CONFIG_EXAMPLE_SOCKET_TCP_TRX 0
/* For ssl download example */
#define CONFIG_EXAMPLE_SSL_DOWNLOAD 0
/* For http download example */
#define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0
/* For httpc example */
#define CONFIG_EXAMPLE_HTTPC 0
/* For Amazon ffs example */
#define CONFIG_EXAMPLE_FFS 0
#if CONFIG_EXAMPLE_FFS
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#undef CONFIG_FAST_DHCP
#define CONFIG_FAST_DHCP 0
#endif
/* For httpd example */
#define CONFIG_EXAMPLE_HTTPD 0
/* For tcp keepalive example */
#define CONFIG_EXAMPLE_TCP_KEEPALIVE 0
/* For sntp show time example */
#define CONFIG_EXAMPLE_SNTP_SHOWTIME 0
/* For websocket client example */
#define CONFIG_EXAMPLE_WEBSOCKET_CLIENT 0
/* For DCT example*/
#define CONFIG_EXAMPLE_DCT 0
/****************** For EAP method example *******************/
#define CONFIG_EXAMPLE_EAP 0
// on/off specified eap method
#define CONFIG_ENABLE_PEAP 0
#define CONFIG_ENABLE_TLS 0
#define CONFIG_ENABLE_TTLS 0
// optional feature: whether to verify the cert of radius server
#define ENABLE_EAP_SSL_VERIFY_SERVER 0
#if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS
#define CONFIG_ENABLE_EAP
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#undef CONFIG_FAST_DHCP
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#define CONFIG_FAST_DHCP 0
#endif
#if CONFIG_ENABLE_TLS
#define ENABLE_EAP_SSL_VERIFY_CLIENT 1
#else
#define ENABLE_EAP_SSL_VERIFY_CLIENT 0
#endif
/******************End of EAP configurations*******************/
/* For FATFS example*/
#define CONFIG_EXAMPLE_FATFS 0
#if CONFIG_EXAMPLE_FATFS
#define CONFIG_FATFS_EN 1
#if CONFIG_FATFS_EN
// fatfs version
#define FATFS_R_10C
// fatfs disk interface
#define FATFS_DISK_USB 0
#define FATFS_DISK_SD 0
#define FATFS_DISK_FLASH 1
#endif
#endif
/* For iNIC host example*/
#ifdef CONFIG_INIC_GSPI_HOST // this flag is defined in IAR project
#define CONFIG_EXAMPLE_INIC_GSPI_HOST 1
#if CONFIG_EXAMPLE_INIC_GSPI_HOST
#define CONFIG_INIC_HOST 1
#undef CONFIG_WLAN
#define CONFIG_WLAN 0
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#undef CONFIG_BSD_TCP
#define CONFIG_BSD_TCP 1
#endif
#endif
/* For wifi scenarios example (Wi-Fi, WPS enrollee, P2P GO) */
// also need to enable WPS and P2P
#define CONFIG_EXAMPLE_WLAN_SCENARIO 0
/* For broadcast example */
#define CONFIG_EXAMPLE_BCAST 0
/* For high-load memory use case memory usage */
#define CONFIG_EXAMPLE_HIGH_LOAD_MEMORY_USE 0
/* For rarp example */
#define CONFIG_EXAMPLE_RARP 0
/* For ssl server example */
#define CONFIG_EXAMPLE_SSL_SERVER 0
/*For secure boot example */
#define CONFIG_EXAMPLE_SECURE_BOOT 0
/*For secure storage example */
#define CONFIG_EXAMPLE_SECURE_STORAGE 0
/* For ota update http example */
#define CONFIG_EXAMPLE_OTA_HTTP 0
/*For wifi roaming example*/
#define CONFIG_EXAMPLE_WIFI_ROAMING 0
/* for tickless roaming */
#define CONFIG_EXAMPLE_TICKLESS_WIFI_ROAMING 0
/*For ipv6 example*/
#define CONFIG_EXAMPLE_IPV6 0
#if CONFIG_ENABLE_WPS
#define WPS_CONNECT_RETRY_COUNT 4
#define WPS_CONNECT_RETRY_INTERVAL 5000 // in ms
#endif
#define AUTO_RECONNECT_COUNT 8
#define AUTO_RECONNECT_INTERVAL 5 // in sec
/*For trust zone example */
#define CONFIG_EXAMPLE_TRUST_ZONE 0
/* For Amazon FreeRTOS SDK example */
#define CONFIG_EXAMPLE_AMAZON_FREERTOS 0
#define CONFIG_EXAMPLE_AMAZON_AFQP_TESTS 0
#if (defined(CONFIG_EXAMPLE_AMAZON_FREERTOS) && CONFIG_EXAMPLE_AMAZON_FREERTOS) || \
(defined(CONFIG_EXAMPLE_AMAZON_AFQP_TESTS) && CONFIG_EXAMPLE_AMAZON_AFQP_TESTS)
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#undef CONFIG_FAST_DHCP
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#define CONFIG_FAST_DHCP 0
#if defined(CONFIG_BUILD_SECURE)
#define ENABLE_AMAZON_COMMON
#endif
#if defined(CONFIG_BUILD_NONSECURE) && (CONFIG_SSL_CLIENT_PRIVATE_IN_TZ == 0)
#undef SUPPORT_LOG_SERVICE
#define SUPPORT_LOG_SERVICE 0
#endif
#endif
/* For UART Module AT command example */
#define CONFIG_EXAMPLE_UART_ATCMD 0
#if (defined(CONFIG_EXAMPLE_UART_ATCMD) && CONFIG_EXAMPLE_UART_ATCMD)
#define UART_SETTING_BACKUP_SECTOR (FLASH_BAKEUP_SECTOR)
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 1
#undef CONFIG_TRANSPORT
#define CONFIG_TRANSPORT 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 1600
#undef CONFIG_LOG_SERVICE_LOCK
#define CONFIG_LOG_SERVICE_LOCK 1
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#if (SUPPORT_MP_MODE && CONFIG_MIIO)
#define CONFIG_MIIO_MP 0 // miio mp test and rw private data
#endif
#endif

69
cores/realtek-ambz2/base/config/platform_opts_bt.h Normal file
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#ifndef __PLATFORM_OPTS_BT_H__
#define __PLATFORM_OPTS_BT_H__
#define CONFIG_BT 0
#if CONFIG_BT
#define CONFIG_FTL_ENABLED
#define CONFIG_BT_CONFIG 0
#define CONFIG_BT_AIRSYNC_CONFIG 0
#define CONFIG_BT_PERIPHERAL 0
#define CONFIG_BT_CENTRAL 0
#define CONFIG_BT_SCATTERNET 0
#define CONFIG_BT_BEACON 0
#define CONFIG_BT_FUZZ_TEST 0
#define CONFIG_BT_OTA_CENTRAL_CLIENT 0
#define CONFIG_BT_DATATRANS 0
#define CONFIG_BT_MESH_PROVISIONER 0
#define CONFIG_BT_MESH_DEVICE 0
#define CONFIG_BT_MESH_PROVISIONER_MULTIPLE_PROFILE 0
#define CONFIG_BT_MESH_DEVICE_MULTIPLE_PROFILE 0
#define CONFIG_BT_MESH_CENTRAL 0
#define CONFIG_BT_MESH_PERIPHERAL 0
#define CONFIG_BT_MESH_SCATTERNET 0
#define CONFIG_BT_MESH_PROVISIONER_RTK_DEMO 0
#define CONFIG_BT_MESH_DEVICE_RTK_DEMO 0
#define CONFIG_BT_MESH_TEST 0
#define CONFIG_BT_ONLY_WITHOUT_WLAN 0
#endif // CONFIG_BT
#if defined CONFIG_BT_SCATTERNET && CONFIG_BT_SCATTERNET
#undef CONFIG_BT_PERIPHERAL
#undef CONFIG_BT_CENTRAL
#define CONFIG_BT_PERIPHERAL 1
#define CONFIG_BT_CENTRAL 1
#endif
#if defined CONFIG_BT_CENTRAL && CONFIG_BT_CENTRAL
#define CONFIG_BT_USER_COMMAND 0
#define CONFIG_BT_WHITE_LIST_TO_FLASH 0
#endif
#if defined CONFIG_BT_OTA_CENTRAL_CLIENT && CONFIG_BT_OTA_CENTRAL_CLIENT
#define CONFIG_BT_OTA_CENTRAL_CLIENT_SPLIT 0
#endif
#if ((defined CONFIG_BT_MESH_PROVISIONER && CONFIG_BT_MESH_PROVISIONER) || (defined CONFIG_BT_MESH_DEVICE && CONFIG_BT_MESH_DEVICE) || (defined CONFIG_BT_MESH_PROVISIONER_MULTIPLE_PROFILE && CONFIG_BT_MESH_PROVISIONER_MULTIPLE_PROFILE) || (defined CONFIG_BT_MESH_DEVICE_MULTIPLE_PROFILE && CONFIG_BT_MESH_DEVICE_MULTIPLE_PROFILE))
#define CONFIG_BT_MESH_USER_API 1
#define CONFIG_BT_MESH_IDLE_CHECK 0
#endif
#if defined CONFIG_BT_MESH_PROVISIONER_RTK_DEMO && CONFIG_BT_MESH_PROVISIONER_RTK_DEMO
#undef CONFIG_BT_CONFIG
#define CONFIG_BT_CONFIG 1
#endif
#if ((defined CONFIG_BT_MESH_PROVISIONER && CONFIG_BT_MESH_PROVISIONER) && (defined CONFIG_BT_MESH_DEVICE && CONFIG_BT_MESH_DEVICE))
#error "CONFIG_BT_MESH_PROVISIONER & CONFIG_BT_MESH_DEVICE can not open at the same time"
#endif
#if ((defined CONFIG_BT_MESH_PROVISIONER_MULTIPLE_PROFILE && CONFIG_BT_MESH_PROVISIONER_MULTIPLE_PROFILE) && (defined CONFIG_BT_MESH_DEVICE_MULTIPLE_PROFILE && CONFIG_BT_MESH_DEVICE_MULTIPLE_PROFILE))
#error \
"CONFIG_BT_MESH_PROVISIONER_MULTIPLE_PROFILE & CONFIG_BT_MESH_DEVICE_MULTIPLE_PROFILE can not open at the same time"
#endif
#if (((defined CONFIG_BT_MESH_CENTRAL && CONFIG_BT_MESH_CENTRAL) && (defined CONFIG_BT_MESH_PERIPHERAL && CONFIG_BT_MESH_PERIPHERAL)) || ((defined CONFIG_BT_MESH_CENTRAL && CONFIG_BT_MESH_CENTRAL) && (defined CONFIG_BT_MESH_SCATTERNET && CONFIG_BT_MESH_SCATTERNET)) || ((defined CONFIG_BT_MESH_PERIPHERAL && CONFIG_BT_MESH_PERIPHERAL) && (defined CONFIG_BT_MESH_SCATTERNET && CONFIG_BT_MESH_SCATTERNET)) || ((defined CONFIG_BT_MESH_CENTRAL && CONFIG_BT_MESH_CENTRAL) && (defined CONFIG_BT_MESH_PERIPHERAL && CONFIG_BT_MESH_PERIPHERAL) && (defined CONFIG_BT_MESH_SCATTERNET && CONFIG_BT_MESH_SCATTERNET)))
#error "Only one of CONFIG_BT_MESH_CENTRAL, CONFIG_BT_MESH_PERIPHERAL and CONFIG_BT_MESH_SCATTERNET can be enabled"
#endif
#endif // __PLATFORM_OPTS_BT_H__

8
cores/realtek-ambz2/base/inc/fixups/time64.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-07-21. */
#pragma once
#include_next "time64.h"
// GCC 10.3.1 does not provide these structs by default
#include <sys/_tz_structs.h>

364
cores/realtek-ambz2/misc/rtl8710c_ram.ld Normal file
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@@ -0,0 +1,364 @@
/* Linker script to configure memory regions. */
/* LT changes: added .ARM.exidx section */
/* !! the include symbole may failed if the symbol file name is too long!! */
INCLUDE "romsym_is.so"
MEMORY
{
/* The vector table, it must start with 256 bytes aligned address */
VECTORS_RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x100000A0 - 0x10000000
/* 0x100000A0 ~ 0x10000480 reserved for ROM code */
/* RAM functions entry table */
RAM_FUN_TABLE (rwx) : ORIGIN = 0x10000480, LENGTH = 0x100004F0 - 0x10000480
/* RAM image Signature */
RAM_IMG_SIGN (rwx) : ORIGIN = 0x100004F0, LENGTH = 0x10000500 - 0x100004F0
/* Internal RAM for program data & text */
DTCM_RAM (wrx) : ORIGIN = 0x10000500, LENGTH = 0x1003FA00 - 0x10000500
/* 0x1003FE70 - 0x1003FA00 is reserved for ROM(NS) code */
/* External PSRAM for text, rodata & data */
PSRAM (rwx) : ORIGIN = 0x60000000, LENGTH = 0x60400000 - 0x60000000
BTRACE (rx) : ORIGIN = 0x00800000, LENGTH = 0x00C00000 - 0x00800000 /* Bluetooth Trace */
/* Flash memory for XIP */
/* XIP image must start with 64K(0x10000) aligned address */
/* XIP Chiper section: TEXT/RODATA in this section can be encrypted (decrypt by SCE) */
XIP_FLASH_C (rx) : ORIGIN = 0x9B000000, LENGTH = 0x9B800000 - 0x9B000000
/* XIP Plantext section: RODATA in this section will not be encrypted */
XIP_FLASH_P (rx) : ORIGIN = 0x9B800000, LENGTH = 0x9BFF0000 - 0x9B800000
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
_start_addr = 0x1000;
ENTRY(_start_addr)
__eram_end__ = ORIGIN(PSRAM) + LENGTH(PSRAM);
__psram_start__ = ORIGIN(PSRAM);
__psram_end__ = ORIGIN(PSRAM) + LENGTH(PSRAM);
SECTIONS
{
.ram.vector :
{
. = ALIGN(256);
__ram_vector_start__ = .;
KEEP(*(.ram_vector_table))
__ram_vector_end__ = .;
. = ALIGN(4);
} > VECTORS_RAM
.ram.func.table :
{
. = ALIGN(32);
__ram_start_table_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
__ram_start_table_end__ = .;
} > RAM_FUN_TABLE
.ram.img.signature :
{
__ram_img_signature__ = .;
KEEP(*(.start.ram.sign*))
} > RAM_IMG_SIGN
.psram.data : AT (__psram_etext)
{
. = ALIGN(16);
__psram_etext = .;
__psram_data_start__ = .;
*(.psram.data*)
__psram_data_end__ = .;
} > PSRAM
.bluetooth_trace.text :
{
__btrace_start__ = .;
*(.BTTRACE)
__btrace_end__ = .;
} > BTRACE
.data :
{
. = ALIGN(16);
__etext = .;
__fw_img_start__ = .;
__data_start__ = .;
*(vtable)
*(.sram.data*)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > DTCM_RAM
.xip_c_reserved :
{
/* XIP image section must start with 64K aligned address, reserve 0x140 for image header */
. += 0x140;
/* If the XIP is the 1st sub-image, then we should reserve 0xE0 bytes meore for OTA Sign. and 6 Public Key */
/*. += 0xE0; */
} > XIP_FLASH_C
.xip_p_reserved :
{
/* XIP image section must start with 64K aligned address, reserve 0x140 for image header */
. += 0x140;
/* If the XIP is the 1st sub-image, then we should reserve 0xE0 bytes meore for OTA Sign. and 6 Public Key */
/*. += 0xE0; */
} > XIP_FLASH_P
.psram.code_text :
{
. = ALIGN(16);
__psram_code_text_start__ = .;
*(.psram.text*)
__psram_code_text_end__ = .;
} > PSRAM
.psram.code_rodata :
{
. = ALIGN(16);
__psram_code_rodata_start__ = .;
*(.psram.rodata*)
. = ALIGN(4);
__psram_code_rodata_end__ = .;
} > PSRAM
.psram.bss :
{
. = ALIGN(16);
__psram_bss_start__ = .;
*(.psram.bss*)
__psram_bss_end__ = .;
. = ALIGN(32);
__eram_bss_end__ = .;
} > PSRAM
.ram.code_text :
{
. = ALIGN(32);
__ram_entry_text_start__ = .;
*(.ram_entry_func.text*)
__ram_entry_text_end__ = .;
. = ALIGN(32);
__ram_code_text_start__ = .;
/* SPI flash controller related code should be located in SRAM, never locates them in XIP */
*hal_spic*.o(.text*)
*hal_flash*.o(.text*)
/* LPDDR controller related code should be located in SRAM, never locates them in LPDDR */
*hal_lpcram*.o(.text*)
*ram_start*.o(.text*)
*hal_power_mode*.o(.text*)
*hal_sys_ctrl*.o(.text*)
*rtl8710c_pinmux_patch*.o(.text*)
*hal_syson*.o(.text*)
*hal_pinmux*.o(.text*)
*hal_efuse*.o(.text*)
*sys_irq*.o(.text*)
*(.lpddr.text*)
*(.sram.text*)
. = ALIGN(4);
__ram_code_text_end__ = .;
} > DTCM_RAM
.ram.code_rodata :
{
. = ALIGN(16);
__ram_code_rodata_start__ = .;
/* SPI flash controller related code should be located in SRAM, never locates them in XIP */
*hal_spic*.o(.rodata*)
*hal_flash*.o(.rodata*)
/* LPDDR controller related code should be located in SRAM, never locates them in LPDDR */
*hal_lpcram*.o(.rodata*)
*ram_start*.o(.rodata*)
*hal_power_mode*.o(.rodata*)
*hal_sys_ctrl*.o(.rodata*)
*rtl8710c_pinmux_patch*.o(.rodata*)
*hal_syson*.o(.rodata*)
*hal_pinmux*.o(.rodata*)
*hal_efuse*.o(.rodata*)
*sys_irq*.o(.rodata*)
. = ALIGN(4);
__ram_code_rodata_end__ = .;
} > DTCM_RAM
.xip.code_c :
{
/* For xip encrypted section ram image signature */
KEEP(*(.xip.ram.sign.s))
/* code and RO data in this section will be encrypted */
. = ALIGN(16);
__xip_code_text_start__ = .;
*(.xip.text*)
*(.text*)
/* put RO data sections need to be encrypted here */
*(.xip.sec_rodata*)
__xip_code_text_end__ = .;
} > XIP_FLASH_C
.xip.code_p :
{
/* code and RO data in this section will NOT be encrypted */
/* put DMA RO data here */
__xip_code_rodata_start__ = .;
*(.xip.rodata*)
*(.rodata*)
*(.rodata.str1*)
. = ALIGN(4);
__xip_code_rodata_end__ = .;
} > XIP_FLASH_P
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > XIP_FLASH_P
.system_restore_data :
{
/* data in this section will not be initialed by ram_start() */
/* some of them will be initialed by boot loader */
. = ALIGN(32);
*(.sys_restore.bss*)
*(.ram.bss.noinit*)
} > DTCM_RAM
.bss :
{
. = ALIGN(16);
__bss_start__ = .;
*(.sram.bss*)
*(.bss*)
*(COMMON)
} > DTCM_RAM
.non_secure.bss :
{
. = ALIGN(16);
__ns_bss_start__ = .;
*(.nonsecure.bss*)
. = ALIGN(4);
__ns_bss_end__ = .;
. = ALIGN(32);
__bss_end__ = .;
} > DTCM_RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > DTCM_RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > DTCM_RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(DTCM_RAM) + LENGTH(DTCM_RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
PROVIDE(__sram_end__ = __StackLimit);
/* Check if data + heap + stack exceeds RAM limit */
/* TODO: ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") */
}