Files
libretiny/boards/_base/pcb/cb2l-test.json
Adrián Panella 1335b84391 [boards] Add Tuya CBU board (#106)
* add CBU module

* boardgen templates

These should go in boardgen package.
Included here for reference

* boardgen output

* [boards] Update for latest version of boardgen

* [boards] Change CBU silkscreen, add variant file

---------

Co-authored-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
2023-06-17 21:25:17 +02:00

107 lines
1.6 KiB
JSON

{
"pcb": {
"scale": 11,
"test_pads": {
"TRST": "cb2l.back.rst.anchor",
"TRX1": "cb2l.back.u1_rxd.anchor",
"TTX1": "cb2l.back.u1_txd.anchor",
"TTX2": "cb2l.back.u2_txd.anchor",
"TGND": "cb2l.back.gnd.anchor",
"TCSN": "cb2l.back.f_csn.anchor"
},
"back": [
{
"name": "test_pad_1mm",
"pos": "1.5,7.5"
},
{
"name": "label_line_down",
"pos": "0.4,4.7",
"vars": {
"DIR": "right",
"W": 0.2,
"H": 2.7
}
},
{
"id": "u1_rxd.anchor",
"type": "rect",
"pos": "0.9,5.0",
"size": "0,0",
"label_dir": "left",
"label_size": 2
},
{
"name": "test_pad_1mm",
"pos": "2.2,5.9"
},
{
"id": "u2_txd",
"name": "label_line_up",
"pos": "2.2,5.1",
"vars": {
"DIR": "left",
"W": 1.5,
"H": 2
}
},
{
"name": "test_pad_1mm",
"pos": "4.0,5.9"
},
{
"id": "u1_txd",
"name": "label_line_up",
"pos": "4.0,5.1",
"vars": {
"DIR": "left",
"W": 3.3,
"H": 4
}
},
{
"name": "test_pad_1mm",
"pos": "9.2,5.9"
},
{
"id": "gnd",
"name": "label_line_up",
"pos": "9.2,5.1",
"vars": {
"DIR": "left",
"W": 8.5,
"H": 6
}
},
{
"name": "test_pad_1mm",
"pos": "2.2,10.7"
},
{
"id": "rst",
"name": "label_line_up",
"pos": "2.2,9.9",
"vars": {
"DIR": "left",
"W": 1.5,
"H": 1.0
}
},
{
"name": "test_pad_1mm",
"pos": "2.2,12.0"
},
{
"id": "f_csn",
"name": "label_line_down",
"pos": "2.2,12.8",
"vars": {
"DIR": "left",
"W": 1.5,
"H": 1.0
}
}
]
}
}