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Merge branch 'master' of https://github.com/86Box/86Box

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This commit is contained in:
RichardG867
2020-10-14 20:29:11 -03:00
parent 65da6ae46f bdbccee369
commit 02ca6493e5
80 changed files with 2811 additions and 2163 deletions
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2
src/chipset/ali6117.c
View File

@@ -321,7 +321,7 @@ ali6117_init(const device_t *info)
ali6117_setup(dev);
ali6117_reset(dev);
pci_elcr_io_disable();
pic_elcr_io_handler(0);
refresh_at_enable = 0;
return dev;

72
src/chipset/intel_420ex.c
View File

@@ -24,6 +24,7 @@
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/pit.h>
@@ -48,6 +49,8 @@ typedef struct
uint16_t timer_base,
timer_latch;
smram_t *smram;
double fast_off_period;
pc_timer_t timer, fast_off_timer;
@@ -98,25 +101,11 @@ i420ex_map(uint32_t addr, uint32_t size, int state)
}
static void
i420ex_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
flushmmucache();
}
static void
i420ex_smram_handler_phase0(void)
{
/* Disable low extended SMRAM. */
if (smram[0].size != 0x00000000) {
i420ex_smram_map(0, smram[0].host_base, smram[0].size, 0);
i420ex_smram_map(1, smram[0].host_base, smram[0].size, 0);
memset(&smram[0], 0x00, sizeof(smram_t));
mem_mapping_disable(&ram_smram_mapping[0]);
}
smram_disable_all();
}
@@ -125,58 +114,43 @@ i420ex_smram_handler_phase1(i420ex_t *dev)
{
uint8_t *regs = (uint8_t *) dev->regs;
uint32_t base = 0x000a0000;
uint32_t host_base = 0x000a0000, ram_base = 0x000a0000;
uint32_t size = 0x00010000;
switch (regs[0x70] & 0x07) {
case 0: case 1:
default:
base = size = 0x00000000;
host_base = ram_base = 0x00000000;
size = 0x00000000;
break;
case 2:
base = 0x000a0000;
smram[0].host_base = 0x000a0000;
smram[0].ram_base = 0x000a0000;
host_base = 0x000a0000;
ram_base = 0x000a0000;
break;
case 3:
base = 0x000b0000;
smram[0].host_base = 0x000b0000;
smram[0].ram_base = 0x000b0000;
host_base = 0x000b0000;
ram_base = 0x000b0000;
break;
case 4:
base = 0x000c0000;
smram[0].host_base = 0x000c0000;
smram[0].ram_base = 0x000a0000;
host_base = 0x000c0000;
ram_base = 0x000a0000;
break;
case 5:
base = 0x000d0000;
smram[0].host_base = 0x000d0000;
smram[0].ram_base = 0x000a0000;
host_base = 0x000d0000;
ram_base = 0x000a0000;
break;
case 6:
base = 0x000e0000;
smram[0].host_base = 0x000e0000;
smram[0].ram_base = 0x000a0000;
host_base = 0x000e0000;
ram_base = 0x000a0000;
break;
case 7:
base = 0x000f0000;
smram[0].host_base = 0x000f0000;
smram[0].ram_base = 0x000a0000;
host_base = 0x000f0000;
ram_base = 0x000a0000;
break;
}
smram[0].size = size;
if (size != 0x00000000) {
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, 0x00010000);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
/* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */
i420ex_smram_map(0, base, size, (regs[0x70] & 0x70) == 0x40);
/* If the register is set accordingly, disable the mapping also in SMM. */
i420ex_smram_map(1, base, size, !(regs[0x70] & 0x20));
}
smram_enable(dev->smram, host_base, ram_base, size,
(regs[0x70] & 0x70) == 0x40, !(regs[0x70] & 0x20));
}
@@ -496,6 +470,8 @@ i420ex_close(void *p)
{
i420ex_t *dev = (i420ex_t *)p;
smram_del(dev->smram);
free(dev);
}
@@ -528,6 +504,8 @@ i420ex_init(const device_t *info)
i420ex_t *dev = (i420ex_t *) malloc(sizeof(i420ex_t));
memset(dev, 0, sizeof(i420ex_t));
dev->smram = smram_add();
pci_add_card(PCI_ADD_NORTHBRIDGE, i420ex_read, i420ex_write, dev);
dev->id = info->local;

81
src/chipset/intel_4x0.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/device.h>
@@ -57,6 +58,7 @@ typedef struct
drb_unit, drb_default;
uint8_t regs[256], regs_locked[256];
int type;
smram_t *smram_low, *smram_high;
} i4x0_t;
@@ -101,36 +103,18 @@ i4x0_map(uint32_t addr, uint32_t size, int state)
}
static void
i4x0_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
}
static void
i4x0_smram_handler_phase0(i4x0_t *dev)
{
uint32_t tom = (mem_size << 10);
/* Disable any active mappings. */
if (smram[0].size != 0x00000000) {
i4x0_smram_map(0, smram[0].host_base, smram[0].size, 0);
i4x0_smram_map(1, smram[0].host_base, smram[0].size, 0);
memset(&smram[0], 0x00, sizeof(smram_t));
mem_mapping_disable(&ram_smram_mapping[0]);
}
if ((dev->type >= INTEL_440BX) && (smram[1].size != 0x00000000)) {
i4x0_smram_map(1, smram[1].host_base, smram[1].size, 0);
if ((dev->type >= INTEL_440BX) && smram_enabled(dev->smram_high)) {
tom -= (1 << 20);
mem_set_mem_state_smm(tom, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
memset(&smram[1], 0x00, sizeof(smram_t));
mem_mapping_disable(&ram_smram_mapping[1]);
}
/* Disable any active mappings. */
smram_disable_all();
}
@@ -158,20 +142,9 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
}
}
if (((regs[0x72] & 0x70) == 0x40) || ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20))) {
smram[0].host_base = base[0];
smram[0].ram_base = base[0] & 0x000f0000;
smram[0].size = size[0];
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
/* If D_OPEN = 1 and D_LCK = 0, extended SMRAM is visible outside SMM. */
i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x70) == 0x40));
/* If the register is set accordingly, disable the mapping also in SMM. */
i4x0_smram_map(1, base[0], size[0], ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20)));
}
if (((regs[0x72] & 0x70) == 0x40) || ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20)))
smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0],
((regs[0x72] & 0x70) == 0x40), ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20)));
/* TSEG mapping. */
if (dev->type >= INTEL_440BX) {
@@ -183,18 +156,10 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
base[1] = size[1] = 0x00000000;
if (size[1] != 0x00000000) {
smram[1].host_base = base[1] + (1 << 28);
smram[1].ram_base = base[1];
smram[1].size = size[1];
mem_mapping_set_addr(&ram_smram_mapping[1], smram[1].host_base, smram[1].size);
if (smram[1].ram_base < (1 << 30))
mem_mapping_set_exec(&ram_smram_mapping[1], ram + smram[1].ram_base);
else
mem_mapping_set_exec(&ram_smram_mapping[1], ram2 + smram[1].ram_base - (1 << 30));
smram_enable(dev->smram_high, base[1] + (1 << 28), base[1], size[1],
0, 1);
mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY);
i4x0_smram_map(1, smram[1].host_base, size[1], 1);
}
}
} else {
@@ -220,18 +185,8 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
}
if (((((regs[0x72] & 0x38) == 0x20) || s) || (!(regs[0x72] & 0x10) || s)) && (size[0] != 0x00000000)) {
smram[0].host_base = base[0];
smram[0].ram_base = base[0];
smram[0].size = size[0];
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
/* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */
i4x0_smram_map(0, base[0], size[0], (((regs[0x72] & 0x38) == 0x20) || s));
/* If the register is set accordingly, disable the mapping also in SMM. */
i4x0_smram_map(0, base[0], size[0], (!(regs[0x72] & 0x10) || s));
smram_enable(dev->smram_low, base[0], base[0], size[0],
(((regs[0x72] & 0x38) == 0x20) || s), (!(regs[0x72] & 0x10) || s));
}
}
@@ -1306,9 +1261,12 @@ i4x0_reset(void *priv)
static void
i4x0_close(void *p)
{
i4x0_t *i4x0 = (i4x0_t *)p;
i4x0_t *dev = (i4x0_t *)p;
free(i4x0);
smram_del(dev->smram_high);
smram_del(dev->smram_low);
free(dev);
}
@@ -1320,6 +1278,9 @@ static void
memset(dev, 0, sizeof(i4x0_t));
dev->smram_low = smram_add();
dev->smram_high = smram_add();
dev->type = info->local & 0xff;
regs = (uint8_t *) dev->regs;

24
src/chipset/opti895.c
View File

@@ -30,6 +30,7 @@
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h>
@@ -41,6 +42,8 @@ typedef struct
uint8_t idx, forced_green,
regs[256],
scratch[2];
smram_t *smram;
} opti895_t;
@@ -123,13 +126,6 @@ opti895_recalc(opti895_t *dev)
}
static void
opti895_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
}
static void
opti895_write(uint16_t addr, uint8_t val, void *priv)
{
@@ -164,7 +160,7 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x24:
opti895_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80));
smram_state_change(dev->smram, 0, !!(val & 0x80));
break;
case 0xe0:
@@ -225,6 +221,8 @@ opti895_close(void *priv)
{
opti895_t *dev = (opti895_t *) priv;
smram_del(dev->smram);
free(dev);
}
@@ -262,15 +260,9 @@ opti895_init(const device_t *info)
io_sethandler(0x00e1, 0x0002, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev);
smram[0].host_base = 0x00030000;
smram[0].ram_base = 0x000b0000;
smram[0].size = 0x00010000;
dev->smram = smram_add();
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
opti895_smram_map(0, smram[0].host_base, smram[0].size, 0);
opti895_smram_map(1, smram[0].host_base, smram[0].size, 1);
smram_enable(dev->smram, 0x00030000, 0x000b0000, 0x00010000, 0, 1);
return dev;
}

4
src/chipset/scat.c
View File

@@ -1541,7 +1541,7 @@ scat_init(const device_t *info)
for (i = 0; i < 16; i++) {
mem_mapping_add(&dev->high_mapping[i], (i << 14) + 0xfc0000, 0x04000,
mem_read_bios, mem_read_biosw, mem_read_biosl,
bios_read, bios_readw, bios_readl,
mem_write_null, mem_write_nullw, mem_write_nulll,
rom + ((i << 14) & biosmask), 0, NULL);
mem_mapping_enable(&dev->high_mapping[i]);
@@ -1561,7 +1561,7 @@ scat_init(const device_t *info)
for (i = (dev->regs[SCAT_VERSION] < 4 ? 0 : 8); i < 16; i++) {
mem_mapping_add(&dev->high_mapping[i], (i << 14) + 0xfc0000, 0x04000,
mem_read_bios, mem_read_biosw, mem_read_biosl,
bios_read, bios_readw, bios_readl,
mem_write_null, mem_write_nullw, mem_write_nulll,
rom + ((i << 14) & biosmask), 0, NULL);
mem_mapping_enable(&dev->high_mapping[i]);

293
src/chipset/sis_85c471.c
View File

@@ -1,293 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the SiS 85c471 chip.
*
* SiS sis85c471 Super I/O Chip
* Used by DTK PKM-0038S E-2
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/lpt.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/timer.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/machine.h>
#include <86box/chipset.h>
typedef struct {
uint8_t cur_reg,
regs[39],
scratch[2];
port_92_t * port_92;
} sis_85c471_t;
static void
sis_85c471_recalcmapping(sis_85c471_t *dev)
{
uint32_t base;
uint32_t i, shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
for (i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
if ((i > 5) || (dev->regs[0x02] & (1 << i))) {
shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80);
shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40);
shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x02] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
mem_set_mem_state(base, 0x8000, shflags);
} else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTERNAL);
}
flushmmucache();
}
static void
sis_85c471_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
uint8_t valxor = 0x00;
if (port == 0x22) {
if ((val >= 0x50) && (val <= 0x76))
dev->cur_reg = val;
return;
} else if (port == 0x23) {
if ((dev->cur_reg < 0x50) || (dev->cur_reg > 0x76))
return;
valxor = val ^ dev->regs[dev->cur_reg - 0x50];
dev->regs[dev->cur_reg - 0x50] = val;
} else if ((port == 0xe1) || (port == 0xe2)) {
dev->scratch[port - 0xe1] = val;
return;
}
switch(dev->cur_reg) {
case 0x51:
cpu_cache_ext_enabled = ((val & 0x84) == 0x84);
cpu_update_waitstates();
break;
case 0x52:
sis_85c471_recalcmapping(dev);
break;
case 0x57:
if (valxor & 0x12)
port_92_set_features(dev->port_92, !!(val & 0x10), !!(val & 0x02));
if (valxor & 0x08) {
if (val & 0x08)
port_92_set_period(dev->port_92, 6ULL * TIMER_USEC);
else
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
}
break;
case 0x5b:
if (valxor & 0x02) {
if (val & 0x02)
mem_remap_top(0);
else
mem_remap_top(256);
}
break;
case 0x63:
if (valxor & 0x10) {
if (dev->regs[0x13] & 0x10)
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
break;
case 0x72:
if (valxor & 0x01) {
port_92_remove(dev->port_92);
if (val & 0x01)
port_92_add(dev->port_92);
}
break;
}
dev->cur_reg = 0;
}
static uint8_t
sis_85c471_read(uint16_t port, void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
uint8_t ret = 0xff;
if (port == 0x22)
ret = dev->cur_reg;
else if (port == 0x23) {
if ((dev->cur_reg >= 0x50) && (dev->cur_reg <= 0x76)) {
ret = dev->regs[dev->cur_reg - 0x50];
if (dev->cur_reg == 0x58)
ret &= 0xf7;
dev->cur_reg = 0;
}
} else if ((port == 0xe1) || (port == 0xe2))
ret = dev->scratch[port - 0xe1];
return ret;
}
static void
sis_85c471_close(void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
free(dev);
}
static void *
sis_85c471_init(const device_t *info)
{
int mem_size_mb, i = 0;
sis_85c471_t *dev = (sis_85c471_t *) malloc(sizeof(sis_85c471_t));
memset(dev, 0, sizeof(sis_85c471_t));
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x1f] = 0x20; /* Video access enabled. */
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed < 25000000)
dev->regs[0x08] |= 0x80;
io_sethandler(0x0022, 0x0002,
sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, dev);
dev->scratch[0] = dev->scratch[1] = 0xff;
io_sethandler(0x00e1, 0x0002,
sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, dev);
dev->port_92 = device_add(&port_92_device);
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
port_92_set_features(dev->port_92, 0, 0);
sis_85c471_recalcmapping(dev);
return dev;
}
const device_t sis_85c471_device = {
"SiS 85c471",
0,
0,
sis_85c471_init, sis_85c471_close, NULL,
NULL, NULL, NULL,
NULL
};

54
src/chipset/sis_85c496.c
View File

@@ -24,6 +24,7 @@
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
@@ -45,6 +46,7 @@ typedef struct sis_85c496_t
uint8_t cur_reg, rmsmiblk_count,
regs[127],
pci_conf[256];
smram_t *smram;
pc_timer_t rmsmiblk_timer;
port_92_t * port_92;
nvr_t * nvr;
@@ -185,14 +187,6 @@ sis_85c496_ide_handler(sis_85c496_t *dev)
}
static void
sis_85c496_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
flushmmucache();
}
/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
static void
sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
@@ -200,6 +194,7 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t old, valxor;
uint8_t smm_irq[4] = { 10, 11, 12, 15 };
uint32_t host_base, ram_base, size;
old = dev->pci_conf[addr];
valxor = (dev->pci_conf[addr]) ^ val;
@@ -299,40 +294,33 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
if (valxor & 0x3e) {
unmask_a20_in_smm = !!(val & 0x20);
if (smram[0].size != 0x00000000) {
sis_85c496_smram_map(0, smram[0].host_base, smram[0].size, 0);
sis_85c496_smram_map(1, smram[0].host_base, smram[0].size, 0);
memset(&smram[0], 0x00, sizeof(smram_t));
mem_mapping_disable(&ram_smram_mapping[0]);
}
smram_disable_all();
if (val & 0x06) {
smram[0].size = 0x00010000;
host_base = 0x00060000;
ram_base = 0x000a0000;
size = 0x00010000;
switch ((val >> 3) & 0x03) {
case 0x00:
smram[0].host_base = 0x00060000;
smram[0].ram_base = 0x000a0000;
host_base = 0x00060000;
ram_base = 0x000a0000;
break;
case 0x01:
smram[0].host_base = 0x00060000;
smram[0].ram_base = 0x000b0000;
host_base = 0x00060000;
ram_base = 0x000b0000;
break;
case 0x02:
smram[0].host_base = 0x000e0000;
smram[0].ram_base = 0x000a0000;
host_base = 0x000e0000;
ram_base = 0x000a0000;
break;
case 0x03:
smram[0].host_base = 0x000e0000;
smram[0].ram_base = 0x000b0000;
host_base = 0x000e0000;
ram_base = 0x000b0000;
break;
}
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, 0x00010000);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
sis_85c496_smram_map(0, smram[0].host_base, smram[0].size, ((val & 0x06) == 0x06));
sis_85c496_smram_map(1, smram[0].host_base, smram[0].size, (val & 0x02));
smram_enable(dev->smram, host_base, ram_base, size,
((val & 0x06) == 0x06), (val & 0x02));
}
}
break;
@@ -562,9 +550,11 @@ sis_85c496_reset(void *priv)
static void
sis_85c496_close(void *p)
{
sis_85c496_t *sis_85c496 = (sis_85c496_t *)p;
sis_85c496_t *dev = (sis_85c496_t *)p;
free(sis_85c496);
smram_del(dev->smram);
free(dev);
}
@@ -574,6 +564,8 @@ static void
sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
memset(dev, 0x00, sizeof(sis_85c496_t));
dev->smram = smram_add();
/* PCI Configuration Header Registers (00h ~ 3Fh) */
dev->pci_conf[0x00] = 0x39; /* SiS */
dev->pci_conf[0x01] = 0x10;

452
src/chipset/sis_85c4xx.c Normal file
View File

@@ -0,0 +1,452 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the SiS 85c401/85c402, 85c460, 85c461, and
* 85c407/85c471 chipsets.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019,2020 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/timer.h>
#include <86box/port_92.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/pic.h>
#include <86box/machine.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t cur_reg, tries,
reg_base, reg_last,
is_471,
regs[39], scratch[2];
smram_t *smram;
port_92_t *port_92;
} sis_85c4xx_t;
static void
sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
{
uint32_t base;
uint32_t i, shflags = 0;
uint32_t readext, writeext;
uint8_t romcs = 0xc0, cur_romcs;
shadowbios = 0;
shadowbios_write = 0;
if (dev->regs[0x03] & 0x40)
romcs |= 0x01;
if (dev->regs[0x03] & 0x80)
romcs |= 0x30;
if (dev->regs[0x08] & 0x04)
romcs |= 0x02;
for (i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
cur_romcs = romcs & (1 << i);
readext = cur_romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
writeext = cur_romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
if ((i > 5) || (dev->regs[0x02] & (1 << i))) {
shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80);
shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40);
shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : readext;
shflags |= (dev->regs[0x02] & 0x40) ? writeext : MEM_WRITE_INTERNAL;
mem_set_mem_state(base, 0x8000, shflags);
} else
mem_set_mem_state(base, 0x8000, readext | writeext);
}
flushmmucache();
}
static void
sis_85c4xx_sw_smi_out(uint16_t port, uint8_t val, void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
if (dev->regs[0x18] & 0x02) {
if (dev->regs[0x0b] & 0x10)
smi_line = 1;
else
picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12));
soft_reset_mask = 1;
dev->regs[0x19] |= 0x02;
}
}
static void
sis_85c4xx_sw_smi_handler(sis_85c4xx_t *dev)
{
uint16_t addr;
if (!dev->is_471)
return;
addr = dev->regs[0x14] | (dev->regs[0x15] << 8);
io_handler((dev->regs[0x0b] & 0x80) && (dev->regs[0x18] & 0x02), addr, 0x0001,
NULL, NULL, NULL, sis_85c4xx_sw_smi_out, NULL, NULL, dev);
}
static void
sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
uint8_t rel_reg = dev->cur_reg - dev->reg_base;
uint8_t valxor = 0x00;
uint32_t host_base = 0x000e0000, ram_base = 0x000a0000;
switch (port) {
case 0x22:
dev->cur_reg = val;
break;
case 0x23:
if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) {
valxor = val ^ dev->regs[rel_reg];
if (rel_reg == 0x19)
dev->regs[rel_reg] &= ~val;
else
dev->regs[rel_reg] = val;
switch (rel_reg) {
case 0x01:
cpu_cache_ext_enabled = ((val & 0x84) == 0x84);
cpu_update_waitstates();
break;
case 0x02: case 0x03:
case 0x08:
sis_85c4xx_recalcmapping(dev);
break;
case 0x0b:
sis_85c4xx_sw_smi_handler(dev);
if (dev->is_471 && (valxor & 0x02)) {
if (val & 0x02)
mem_remap_top(0);
else
mem_remap_top(256);
}
break;
case 0x13:
if (dev->is_471 && (valxor & 0xf0)) {
smram_disable(dev->smram);
host_base = (val & 0x80) ? 0x00060000 : 0x000e0000;
switch ((val >> 5) & 0x03) {
case 0x00:
ram_base = 0x000a0000;
break;
case 0x01:
ram_base = 0x000b0000;
break;
case 0x02:
ram_base = (val & 0x80) ? 0x00000000 : 0x000e0000;
break;
default:
ram_base = 0x00000000;
break;
}
if (ram_base != 0x00000000)
smram_enable(dev->smram, host_base, ram_base, 0x00010000, (val & 0x10), 1);
}
break;
case 0x14: case 0x15:
case 0x18:
sis_85c4xx_sw_smi_handler(dev);
break;
case 0x1c:
if (dev->is_471)
soft_reset_mask = 0;
break;
case 0x22:
if (dev->is_471 && (valxor & 0x01)) {
port_92_remove(dev->port_92);
if (val & 0x01)
port_92_add(dev->port_92);
}
break;
}
}
dev->cur_reg = 0x00;
break;
case 0xe1: case 0xe2:
dev->scratch[port - 0xe1] = val;
return;
}
}
static uint8_t
sis_85c4xx_in(uint16_t port, void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
uint8_t rel_reg = dev->cur_reg - dev->reg_base;
uint8_t ret = 0xff;
switch (port) {
case 0x23:
if (dev->is_471 && (dev->cur_reg == 0x1c))
ret = inb(0x70);
if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last))
ret = dev->regs[rel_reg];
dev->cur_reg = 0x00;
break;
case 0xe1: case 0xe2:
ret = dev->scratch[port - 0xe1];
}
return ret;
}
static void
sis_85c4xx_close(void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
if (dev->is_471)
smram_del(dev->smram);
free(dev);
}
static void *
sis_85c4xx_init(const device_t *info)
{
int mem_size_mb;
sis_85c4xx_t *dev = (sis_85c4xx_t *) malloc(sizeof(sis_85c4xx_t));
memset(dev, 0, sizeof(sis_85c4xx_t));
dev->is_471 = (info->local >> 8) & 0xff;
dev->reg_base = info->local & 0xff;
mem_size_mb = mem_size >> 10;
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed < 25000000)
dev->regs[0x08] = 0x80;
if (dev->is_471) {
dev->reg_last = dev->reg_base + 0x76;
dev->regs[0x09] = 0x40;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[0x09] |= 0x00;
break;
case 2: case 3:
dev->regs[0x09] |= 0x01;
break;
case 4:
dev->regs[0x09] |= 0x02;
break;
case 5:
dev->regs[0x09] |= 0x20;
break;
case 6: case 7:
dev->regs[0x09] |= 0x09;
break;
case 8: case 9:
dev->regs[0x09] |= 0x04;
break;
case 10: case 11:
dev->regs[0x09] |= 0x05;
break;
case 12: case 13: case 14: case 15:
dev->regs[0x09] |= 0x0b;
break;
case 16:
dev->regs[0x09] |= 0x13;
break;
case 17:
dev->regs[0x09] |= 0x21;
break;
case 18: case 19:
dev->regs[0x09] |= 0x06;
break;
case 20: case 21: case 22: case 23:
dev->regs[0x09] |= 0x0d;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[0x09] |= 0x0e;
break;
case 32: case 33: case 34: case 35:
dev->regs[0x09] |= 0x1b;
break;
case 36: case 37: case 38: case 39:
dev->regs[0x09] |= 0x0f;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[0x09] |= 0x17;
break;
case 48:
dev->regs[0x09] |= 0x1e;
break;
default:
if (mem_size_mb < 64)
dev->regs[0x09] |= 0x1e;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[0x09] |= 0x22;
else
dev->regs[0x09] |= 0x24;
break;
}
dev->regs[0x11] = 0x09;
dev->regs[0x12] = 0xff;
dev->regs[0x1f] = 0x20; /* Video access enabled. */
dev->regs[0x23] = 0xf0;
dev->regs[0x26] = 0x01;
dev->smram = smram_add();
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x00010000, 0, 1);
dev->port_92 = device_add(&port_92_device);
port_92_remove(dev->port_92);
} else {
dev->reg_last = dev->reg_base + 0x11;
switch (mem_size_mb) {
case 1:
default:
dev->regs[0x00] = 0x00;
break;
case 2:
dev->regs[0x00] = 0x01;
break;
case 4:
dev->regs[0x00] = 0x02;
break;
case 6:
dev->regs[0x00] = 0x03;
break;
case 8:
dev->regs[0x00] = 0x04;
break;
case 10:
dev->regs[0x00] = 0x05;
break;
case 12:
dev->regs[0x00] = 0x0b;
break;
case 16:
dev->regs[0x00] = 0x19;
break;
case 18:
dev->regs[0x00] = 0x06;
break;
case 20:
dev->regs[0x00] = 0x14;
break;
case 24:
dev->regs[0x00] = 0x15;
break;
case 32:
dev->regs[0x00] = 0x1b;
break;
case 36:
dev->regs[0x00] = 0x16;
break;
case 40:
dev->regs[0x00] = 0x17;
break;
case 48:
dev->regs[0x00] = 0x1e;
break;
case 64:
dev->regs[0x00] = 0x1f;
break;
}
dev->regs[0x11] = 0x01;
}
io_sethandler(0x0022, 0x0002,
sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev);
dev->scratch[0] = dev->scratch[1] = 0xff;
io_sethandler(0x00e1, 0x0002,
sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev);
sis_85c4xx_recalcmapping(dev);
return dev;
}
const device_t sis_85c401_device = {
"SiS 85c401/85c402",
0,
0x060,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
NULL
};
const device_t sis_85c460_device = {
"SiS 85c460",
0,
0x050,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
NULL
};
/* TODO: Log to make sure the registers are correct. */
const device_t sis_85c461_device = {
"SiS 85c461",
0,
0x050,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
NULL
};
const device_t sis_85c471_device = {
"SiS 85c407/85c471",
0,
0x150,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
NULL
};

187
src/chipset/stpc.c
View File

@@ -23,6 +23,7 @@
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
@@ -67,6 +68,7 @@ typedef struct stpc_t
/* PCI devices */
uint8_t pci_conf[4][256];
smram_t *smram;
usb_t *usb;
int ide_slot;
sff8038i_t *bm[2];
@@ -155,13 +157,6 @@ stpc_recalcmapping(stpc_t *dev)
}
static void
stpc_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
}
static void
stpc_host_write(uint16_t addr, uint8_t val, void *priv)
{
@@ -446,7 +441,7 @@ stpc_ide_read(int func, int addr, void *priv)
uint8_t ret;
if (func > 0)
ret = 0xff;
ret = 0xff;
else {
ret = dev->pci_conf[2][addr];
if (addr == 0x48) {
@@ -467,8 +462,8 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
stpc_t *dev = (stpc_t *) priv;
if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) {
stpc_ide_write(0, addr, val, priv);
return;
stpc_ide_write(0, addr, val, priv);
return;
}
stpc_log("STPC: isab_write(%d, %02X, %02X)\n", func, addr, val);
@@ -498,11 +493,11 @@ stpc_isab_read(int func, int addr, void *priv)
uint8_t ret;
if ((func == 1) && !(dev->local & STPC_IDE_ATLAS))
ret = stpc_ide_read(0, addr, priv);
ret = stpc_ide_read(0, addr, priv);
else if (func > 0)
ret = 0xff;
ret = 0xff;
else
ret = dev->pci_conf[1][addr];
ret = dev->pci_conf[1][addr];
stpc_log("STPC: isab_read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
@@ -552,9 +547,9 @@ stpc_usb_read(int func, int addr, void *priv)
uint8_t ret;
if (func > 0)
ret = 0xff;
ret = 0xff;
else
ret = dev->pci_conf[3][addr];
ret = dev->pci_conf[3][addr];
stpc_log("STPC: usb_read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
@@ -596,32 +591,32 @@ stpc_serial_handlers(uint8_t val)
{
stpc_serial_t *dev;
if (!(dev = device_get_priv(&stpc_serial_device))) {
stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val);
return 0;
stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val);
return 0;
}
uint16_t uart0_io = 0x3f8, uart0_irq = 4, uart1_io = 0x3f8, uart1_irq = 3;
if (val & 0x10)
uart1_io -= 0x100;
uart1_io -= 0x100;
if (val & 0x20)
uart1_io -= 0x10;
if (val & 0x40)
uart0_io -= 0x100;
uart0_io -= 0x100;
if (val & 0x80)
uart0_io -= 0x10;
if (uart0_io == uart1_io) {
/* Apply defaults if both UARTs are set to the same address. */
stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io);
uart0_io = 0x3f8;
uart1_io = 0x2f8;
/* Apply defaults if both UARTs are set to the same address. */
stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io);
uart0_io = 0x3f8;
uart1_io = 0x2f8;
}
if (uart0_io < 0x300) {
/* The address for UART0 defines the IRQs for both ports. */
uart0_irq = 3;
uart1_irq = 4;
/* The address for UART0 defines the IRQs for both ports. */
uart0_irq = 3;
uart1_irq = 4;
}
stpc_log("STPC: Remapping UART0 to %04X %d and UART1 to %04X %d (raw %02X)\n", uart0_io, uart0_irq, uart1_io, uart1_irq, val);
@@ -673,7 +668,7 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x25: case 0x26: case 0x27: case 0x28:
if (dev->reg_offset == 0x28) {
val &= 0xe3;
stpc_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80));
smram_state_change(dev->smram, 0, !!(val & 0x80));
}
dev->regs[dev->reg_offset] = val;
stpc_recalcmapping(dev);
@@ -694,7 +689,7 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x56: case 0x57:
elcr_write(dev->reg_offset, val, NULL);
pic_elcr_write(dev->reg_offset, val, NULL);
if (dev->reg_offset == 0x57)
refresh_at_enable = (val & 0x01);
break;
@@ -719,10 +714,10 @@ stpc_reg_read(uint16_t addr, void *priv)
if (addr == 0x22)
ret = dev->reg_offset;
else if (dev->reg_offset >= 0xc0)
return 0xff; /* Cyrix CPU registers: let the CPU code handle these */
return 0xff; /* Cyrix CPU registers: let the CPU code handle these */
else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) {
/* ELCR is in here, not in port 4D0h. */
ret = elcr_read(dev->reg_offset, NULL);
/* ELCR is in here, not in port 4D0h. */
ret = pic_elcr_read(dev->reg_offset, NULL);
if (dev->reg_offset == 0x57)
ret |= (dev->regs[dev->reg_offset] & 0x01);
} else
@@ -743,9 +738,9 @@ stpc_reset(void *priv)
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x7b] = 0xff;
if (device_get_priv(&stpc_lpt_device))
dev->regs[0x4c] |= 0x80; /* LPT strap */
dev->regs[0x4c] |= 0x80; /* LPT strap */
if (stpc_serial_handlers(0x00))
dev->regs[0x4c] |= 0x03; /* UART straps */
dev->regs[0x4c] |= 0x03; /* UART straps */
}
@@ -830,11 +825,11 @@ stpc_setup(stpc_t *dev)
}
if (dev->local & STPC_IDE_ATLAS) {
dev->pci_conf[2][0x02] = 0x28;
dev->pci_conf[2][0x03] = 0x02;
dev->pci_conf[2][0x02] = 0x28;
dev->pci_conf[2][0x03] = 0x02;
} else {
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
}
dev->pci_conf[2][0x06] = 0x80;
@@ -866,22 +861,22 @@ stpc_setup(stpc_t *dev)
/* USB */
if (dev->usb) {
dev->pci_conf[3][0x00] = 0x4a;
dev->pci_conf[3][0x01] = 0x10;
dev->pci_conf[3][0x02] = 0x30;
dev->pci_conf[3][0x03] = 0x02;
dev->pci_conf[3][0x00] = 0x4a;
dev->pci_conf[3][0x01] = 0x10;
dev->pci_conf[3][0x02] = 0x30;
dev->pci_conf[3][0x03] = 0x02;
dev->pci_conf[3][0x06] = 0x80;
dev->pci_conf[3][0x07] = 0x02;
dev->pci_conf[3][0x06] = 0x80;
dev->pci_conf[3][0x07] = 0x02;
dev->pci_conf[3][0x09] = 0x10;
dev->pci_conf[3][0x0a] = 0x03;
dev->pci_conf[3][0x0b] = 0x0c;
dev->pci_conf[3][0x09] = 0x10;
dev->pci_conf[3][0x0a] = 0x03;
dev->pci_conf[3][0x0b] = 0x0c;
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
indicates as well, and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
dev->pci_conf[3][0x0e] = /*0x40*/ 0x80;
dev->pci_conf[3][0x0e] = /*0x40*/ 0x80;
}
/* PCI setup */
@@ -899,8 +894,7 @@ stpc_close(void *priv)
stpc_log("STPC: close()\n");
io_removehandler(0x22, 2,
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
smram_del(dev->smram);
free(dev);
}
@@ -919,10 +913,10 @@ stpc_init(const device_t *info)
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
dev->ide_slot = pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev);
if (dev->local & STPC_IDE_ATLAS)
dev->ide_slot = pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
dev->ide_slot = pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
if (dev->local & STPC_USB) {
dev->usb = device_add(&usb_device);
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
dev->usb = device_add(&usb_device);
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
}
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
@@ -937,19 +931,13 @@ stpc_init(const device_t *info)
stpc_setup(dev);
stpc_reset(dev);
smram[0].host_base = 0x000a0000;
smram[0].ram_base = 0x000a0000;
smram[0].size = 0x00020000;
dev->smram = smram_add();
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
stpc_smram_map(0, smram[0].host_base, smram[0].size, 0);
stpc_smram_map(1, smram[0].host_base, smram[0].size, 1);
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x00020000, 0, 1);
device_add(&port_92_pci_device);
pci_elcr_io_disable();
pic_elcr_io_handler(0);
refresh_at_enable = 0;
return dev;
@@ -990,38 +978,38 @@ stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
uint8_t old_addr = (dev->reg1 & 0x03), new_addr = (val & 0x03);
switch (old_addr) {
case 0x1:
lpt3_remove();
break;
case 0x1:
lpt3_remove();
break;
case 0x2:
lpt1_remove();
break;
case 0x2:
lpt1_remove();
break;
case 0x3:
lpt2_remove();
break;
case 0x3:
lpt2_remove();
break;
}
switch (new_addr) {
case 0x1:
stpc_log("STPC: Remapping parallel port to LPT3\n");
lpt3_init(0x3bc);
break;
case 0x1:
stpc_log("STPC: Remapping parallel port to LPT3\n");
lpt3_init(0x3bc);
break;
case 0x2:
stpc_log("STPC: Remapping parallel port to LPT1\n");
lpt1_init(0x378);
break;
case 0x2:
stpc_log("STPC: Remapping parallel port to LPT1\n");
lpt1_init(0x378);
break;
case 0x3:
stpc_log("STPC: Remapping parallel port to LPT2\n");
lpt2_init(0x278);
break;
case 0x3:
stpc_log("STPC: Remapping parallel port to LPT2\n");
lpt2_init(0x278);
break;
default:
stpc_log("STPC: Disabling parallel port\n");
break;
default:
stpc_log("STPC: Disabling parallel port\n");
break;
}
dev->reg1 = (val & 0x08);
@@ -1036,22 +1024,22 @@ stpc_lpt_write(uint16_t addr, uint8_t val, void *priv)
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
if (dev->unlocked < 2) {
/* Cheat a little bit: in reality, any write to any
I/O port is supposed to reset the unlock counter. */
if ((addr == 0x3f0) && (val == 0x55))
dev->unlocked++;
else
dev->unlocked = 0;
/* Cheat a little bit: in reality, any write to any
I/O port is supposed to reset the unlock counter. */
if ((addr == 0x3f0) && (val == 0x55))
dev->unlocked++;
else
dev->unlocked = 0;
} else if (addr == 0x3f0) {
if (val == 0xaa)
dev->unlocked = 0;
else
dev->offset = val;
if (val == 0xaa)
dev->unlocked = 0;
else
dev->offset = val;
} else if (dev->offset == 1) {
/* dev->reg1 is set by stpc_lpt_handlers */
stpc_lpt_handlers(dev, val);
/* dev->reg1 is set by stpc_lpt_handlers */
stpc_lpt_handlers(dev, val);
} else if (dev->offset == 4) {
dev->reg4 = (val & 0x03);
dev->reg4 = (val & 0x03);
}
}
@@ -1078,9 +1066,6 @@ stpc_lpt_close(void *priv)
stpc_log("STPC: lpt_close()\n");
io_removehandler(0x3f0, 2,
NULL, NULL, NULL, stpc_lpt_write, NULL, NULL, dev);
free(dev);
}

75
src/chipset/via_apollo.c
View File

@@ -26,6 +26,7 @@
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/device.h>
@@ -37,8 +38,10 @@
typedef struct via_apollo_t
{
uint16_t id;
uint8_t pci_conf[256];
uint16_t id;
uint8_t pci_conf[256];
smram_t *smram;
} via_apollo_t;
@@ -65,17 +68,12 @@ apollo_map(uint32_t addr, uint32_t size, int state)
static void
apollo_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
apollo_smram_map(via_apollo_t *dev, int smm, uint32_t host_base, uint32_t size, int is_smram)
{
if (((is_smram & 0x03) == 0x01) || ((is_smram & 0x03) == 0x02)) {
smram[0].ram_base = 0x000a0000;
smram[0].size = size;
if (((is_smram & 0x03) == 0x01) || ((is_smram & 0x03) == 0x02))
smram_enable(dev->smram, host_base, 0x000a0000, size, 0, 1);
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
}
mem_set_mem_state_smram_ex(smm, addr, size, is_smram & 0x03);
mem_set_mem_state_smram_ex(smm, host_base, size, is_smram & 0x03);
flushmmucache();
}
@@ -249,64 +247,56 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
if ((dev->pci_conf[0x63] ^ val) & 0xc0)
apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
dev->pci_conf[0x63] = val;
if (smram[0].size != 0x00000000) {
mem_set_mem_state_smram_ex(0, smram[0].host_base, smram[0].size, 0x00);
mem_set_mem_state_smram_ex(1, smram[0].host_base, smram[0].size, 0x00);
memset(&smram[0], 0x00, sizeof(smram_t));
mem_mapping_disable(&ram_smram_mapping[0]);
flushmmucache();
}
smram_disable_all();
if (dev->id == 0x0691) switch (val & 0x03) {
case 0x00:
default:
apollo_smram_map(1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */
break;
case 0x01:
apollo_smram_map(1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(0, 0x000a0000, 0x00020000, 1); /* Non-SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); /* Non-SMM: Code DRAM, Data DRAM */
break;
case 0x02:
apollo_smram_map(1, 0x000a0000, 0x00020000, 3); /* SMM: Code Invalid, Data Invalid */
apollo_smram_map(0, 0x000a0000, 0x00020000, 2); /* Non-SMM: Code DRAM, Data PCI */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); /* SMM: Code Invalid, Data Invalid */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 2); /* Non-SMM: Code DRAM, Data PCI */
break;
case 0x03:
apollo_smram_map(1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(0, 0x000a0000, 0x00020000, 3); /* Non-SMM: Code Invalid, Data Invalid */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); /* Non-SMM: Code Invalid, Data Invalid */
break;
} else switch (val & 0x03) {
case 0x00:
default:
/* Disable SMI Address Redirection (default) */
apollo_smram_map(1, 0x000a0000, 0x00020000, 0);
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0);
if (dev->id == 0x0597)
apollo_smram_map(1, 0x00030000, 0x00020000, 1);
apollo_smram_map(0, 0x000a0000, 0x00020000, 0);
apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
break;
case 0x01:
/* Allow access to DRAM Axxxx-Bxxxx for both normal and SMI cycles */
apollo_smram_map(1, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1);
if (dev->id == 0x0597)
apollo_smram_map(1, 0x00030000, 0x00020000, 1);
apollo_smram_map(0, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1);
break;
case 0x02:
/* Reserved */
apollo_smram_map(1, 0x000a0000, 0x00020000, 3);
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3);
if (dev->id == 0x0597) {
/* SMI 3xxxx-4xxxx redirect to Axxxx-Bxxxx. */
smram[0].host_base = 0x00030000;
apollo_smram_map(1, 0x00030000, 0x00020000, 1);
apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1);
}
apollo_smram_map(0, 0x000a0000, 0x00020000, 3);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
break;
case 0x03:
/* Allow SMI Axxxx-Bxxxx DRAM access */
apollo_smram_map(1, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1);
if (dev->id == 0x0597)
apollo_smram_map(1, 0x00030000, 0x00020000, 1);
apollo_smram_map(0, 0x000a0000, 0x00020000, 0);
apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
break;
}
break;
@@ -444,6 +434,9 @@ via_apollo_init(const device_t *info)
via_apollo_t *dev = (via_apollo_t *) malloc(sizeof(via_apollo_t));
memset(dev, 0, sizeof(via_apollo_t));
dev->smram = smram_add();
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev);
dev->id = info->local;
@@ -474,6 +467,8 @@ via_apollo_close(void *priv)
{
via_apollo_t *dev = (via_apollo_t *) priv;
smram_del(dev->smram);
free(dev);
}

2
src/chipset/via_pipc.c
View File

@@ -491,7 +491,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
if (val & 0x01)
trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL);
pic_set_shadow(!!(val & 0x10));
pci_elcr_set_enabled(!!(val & 0x20));
pic_elcr_set_enabled(!!(val & 0x20));
dev->pci_isa_regs[0x47] = val & 0xfe;
break;
case 0x48:

255
src/chipset/via_vt82c49x.c
View File

@@ -10,12 +10,12 @@
*
*
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Tiseno100.
* Copyright 2020 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -30,15 +30,22 @@
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/pic.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t index,
regs[256];
uint8_t has_ide, index,
regs[256];
smram_t *smram_smm, *smram_low,
*smram_high;
} vt82c49x_t;
#ifdef ENABLE_VT82C49X_LOG
@@ -58,40 +65,100 @@ vt82c49x_log(const char *fmt, ...)
#define vt82c49x_log(fmt, ...)
#endif
static void vt82c49x_shadow_recalc(vt82c49x_t *dev)
static void
vt82c49x_recalc(vt82c49x_t *dev)
{
int i, state;
int relocate;
int wr_c0, wr_c8, wr_e8, wr_e0;
int rr_c0, rr_c8, rr_e8, rr_e0;
int wp_c0, wp_e0, wp_e8, wp_f;
uint32_t base;
uint32_t wp_c, wp_e, wp_f;
/* Register 33h */
wr_c8 = (dev->regs[0x33] & 0x80) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
wr_c0 = (dev->regs[0x33] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
wr_e8 = (dev->regs[0x33] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
wr_e0 = (dev->regs[0x33] & 0x10) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
rr_c8 = (dev->regs[0x33] & 0x80) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
rr_c0 = (dev->regs[0x33] & 0x40) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
rr_e8 = (dev->regs[0x33] & 0x20) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
rr_e0 = (dev->regs[0x33] & 0x10) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
relocate = (dev->regs[0x33] >> 2) & 0x03;
/* Register 40h */
wp_c = (dev->regs[0x40] & 0x80) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
wp_f = (dev->regs[0x40] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
wp_e = (dev->regs[0x40] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
/* Register 40h */
wp_c0 = (dev->regs[0x40] & 0x80) ? wr_c0 : MEM_WRITE_INTERNAL;
wp_f = (dev->regs[0x40] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
wp_e8 = (dev->regs[0x40] & 0x20) ? wr_e8 : MEM_WRITE_INTERNAL;
wp_e0 = (dev->regs[0x40] & 0x20) ? wr_e0 : MEM_WRITE_INTERNAL;
/* Register 30h */
mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0x30] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x01) ? wp_c : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0x30] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x04) ? wp_c : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0x30] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x10) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0x30] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x40) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
/* Registers 30h-32h */
if (relocate >= 2) {
mem_set_mem_state_both(0xc8000, 0x8000, wr_c8 | rr_c8);
mem_set_mem_state_both(0xc0000, 0x8000, wr_c0 | rr_c0);
/* Register 31h */
mem_set_mem_state_both(0xd0000, 0x4000, ((dev->regs[0x31] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x01) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xd4000, 0x4000, ((dev->regs[0x31] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xd8000, 0x4000, ((dev->regs[0x31] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x10) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xdc000, 0x4000, ((dev->regs[0x31] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x40) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xd0000, 0x10000, MEM_WRITE_EXTERNAL | MEM_READ_EXTERNAL);
} else for (i = 0; i < 8; i += 2) {
base = 0xc0000 + (i << 13);
if (base >= 0xc8000) {
state = (dev->regs[0x30] & i) ? MEM_WRITE_INTERNAL : wr_c8;
state |= (dev->regs[0x30] & (i + 1)) ? MEM_READ_INTERNAL : rr_c8;
} else {
state = (dev->regs[0x30] & i) ? wp_c0 : wr_c0;
state |= (dev->regs[0x30] & (i + 1)) ? MEM_READ_INTERNAL : rr_c0;
}
mem_set_mem_state_both(base, 0x4000, state);
/* Register 32h */
shadowbios = (dev->regs[0x40] & 0x20);
shadowbios_write = (dev->regs[0x40] & 0x10);
mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0x32] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x32] & 0x40) ? wp_e : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0x32] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x32] & 0x10) ? wp_f : MEM_WRITE_EXTANY));
base = 0xd0000 + (i << 13);
state = (dev->regs[0x31] & i) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
state |= (dev->regs[0x31] & (i + 1)) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
mem_set_mem_state_both(base, 0x4000, state);
}
state = (dev->regs[0x32] & 0x10) ? wp_f : MEM_WRITE_EXTANY;
state |= (dev->regs[0x32] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shadowbios_write = (dev->regs[0x32] & 0x10) ? ((wp_f == MEM_WRITE_INTERNAL) ? 1 : 0) : 0;
shadowbios = (dev->regs[0x32] & 0x20) ? 1 : 0;
mem_set_mem_state_both(0xf0000, 0x10000, state);
if (relocate == 3) {
mem_set_mem_state_both(0xe8000, 0x8000, wr_e8 | rr_e8);
mem_set_mem_state_both(0xe0000, 0x8000, wr_e0 | rr_e0);
} else {
state = (dev->regs[0x32] & 0x40) ? wp_e8 : wr_e8;
state |= (dev->regs[0x32] & 0x80) ? MEM_READ_INTERNAL : rr_e8;
shadowbios_write |= (dev->regs[0x32] & 0x40) ? ((wp_e8 == MEM_WRITE_INTERNAL) ? 1 : 0) : 0;
shadowbios |= (dev->regs[0x32] & 0x80) ? 1 : 0;
mem_set_mem_state_both(0xe8000, 0x8000, state);
state = (dev->regs[0x32] & 0x40) ? wp_e0 : wr_e0;
state |= (dev->regs[0x32] & 0x80) ? MEM_READ_INTERNAL : rr_e0;
shadowbios_write |= (dev->regs[0x32] & 0x40) ? ((wp_e0 == MEM_WRITE_INTERNAL) ? 1 : 0) : 0;
shadowbios |= (dev->regs[0x32] & 0x80) ? 1 : 0;
mem_set_mem_state_both(0xe0000, 0x8000, state);
}
switch (relocate) {
case 0x00:
default:
mem_remap_top(0);
break;
case 0x02:
mem_remap_top(256);
break;
case 0x03:
mem_remap_top(384);
break;
}
}
static void
vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
{
vt82c49x_t *dev = (vt82c49x_t *) priv;
uint8_t valxor;
switch (addr) {
case 0xa8:
@@ -99,40 +166,80 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0xa9:
dev->regs[dev->index] = val;
valxor = (val ^ dev->regs[dev->index]);
if (dev->index == 0x55)
dev->regs[dev->index] &= ~val;
else
dev->regs[dev->index] = val;
vt82c49x_log("dev->regs[0x%02x] = %02x\n", dev->index, val);
vt82c49x_log("dev->regs[0x%02x] = %02x\n", dev->index, val);
switch(dev->index){
/* Wait States */
case 0x03:
cpu_update_waitstates();
break;
switch(dev->index) {
/* Wait States */
case 0x03:
cpu_update_waitstates();
break;
/* Shadow RAM */
case 0x30:
case 0x31:
case 0x32:
case 0x40:
vt82c49x_shadow_recalc(dev);
break;
/* Shadow RAM and top of RAM relocation */
case 0x30:
case 0x31:
case 0x32:
case 0x33:
case 0x40:
vt82c49x_recalc(dev);
break;
/* External Cache Enable(Based on the 486-VC-HD BIOS) */
case 0x50:
cpu_cache_ext_enabled = (val & 0x84);
break;
/* External Cache Enable(Based on the 486-VC-HD BIOS) */
case 0x50:
cpu_cache_ext_enabled = (val & 0x84);
break;
/* SMI/SMM(Not at all perfect or even functional :/) */
case 0x5b:
/* Software SMI */
case 0x54:
if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) {
if (dev->regs[0x5b] & 0x20)
smi_line = 1;
else
picint(1 << 15);
dev->regs[0x55] = 0x01;
}
break;
if(val & 0x40)
mem_set_mem_state_smram(1, 0x30000, 0x20000, 0);
/* SMRAM */
case 0x5b:
smram_disable_all();
if(val & 0x20)
smi_line = 1;
if (val & 0x80) {
smram_enable(dev->smram_smm, (val & 0x40) ? 0x00060000 : 0x00030000, 0x000a0000, 0x00020000,
0, (val & 0x10));
smram_enable(dev->smram_high, 0x000a0000, 0x000a0000, 0x00020000,
(val & 0x08), (val & 0x08));
smram_enable(dev->smram_low, 0x00030000, 0x000a0000, 0x00020000,
(val & 0x02), 0);
}
break;
break;
}
/* Edge/Level IRQ Control */
case 0x62: case 0x63:
if (dev->index == 0x63)
pic_elcr_write(dev->index, val & 0xde, NULL);
else {
pic_elcr_write(dev->index, val & 0xf8, NULL);
pic_elcr_set_enabled(val & 0x01);
}
break;
/* Local Bus IDE Controller */
case 0x71:
if (dev->has_ide) {
ide_pri_disable();
ide_set_base(0, (val & 0x40) ? 0x170 : 0x1f0);
ide_set_side(0, (val & 0x40) ? 0x376 : 0x3f6);
if (val & 0x01)
ide_pri_enable();
}
break;
}
break;
}
}
@@ -146,7 +253,12 @@ vt82c49x_read(uint16_t addr, void *priv)
switch (addr) {
case 0xa9:
ret = dev->regs[dev->index];
if (dev->index == 0x63)
ret = pic_elcr_read(dev->index, NULL) | (dev->regs[dev->index] & 0x01);
else if (dev->index == 0x62)
ret = pic_elcr_read(dev->index, NULL) | (dev->regs[dev->index] & 0x07);
else
ret = dev->regs[dev->index];
break;
}
@@ -159,6 +271,10 @@ vt82c49x_close(void *priv)
{
vt82c49x_t *dev = (vt82c49x_t *) priv;
smram_del(dev->smram_high);
smram_del(dev->smram_low);
smram_del(dev->smram_smm);
free(dev);
}
@@ -167,17 +283,24 @@ static void *
vt82c49x_init(const device_t *info)
{
vt82c49x_t *dev = (vt82c49x_t *) malloc(sizeof(vt82c49x_t));
memset(dev, 0, sizeof(vt82c49x_t));
memset(dev, 0x00, sizeof(vt82c49x_t));
dev->smram_smm = smram_add();
dev->smram_low = smram_add();
dev->smram_high = smram_add();
dev->has_ide = info->local & 1;
if (dev->has_ide)
device_add(&ide_vlb_device);
device_add(&port_92_device);
io_sethandler(0x0a8, 0x0001, vt82c49x_read, NULL, NULL, vt82c49x_write, NULL, NULL, dev);
io_sethandler(0x0a9, 0x0001, vt82c49x_read, NULL, NULL, vt82c49x_write, NULL, NULL, dev);
io_sethandler(0x0a8, 0x0002, vt82c49x_read, NULL, NULL, vt82c49x_write, NULL, NULL, dev);
dev->regs[0x30] = 0x00;
dev->regs[0x31] = 0x00;
dev->regs[0x32] = 0x00;
vt82c49x_shadow_recalc(dev);
pic_elcr_io_handler(0);
pic_elcr_set_enabled(1);
vt82c49x_recalc(dev);
return dev;
}
@@ -191,3 +314,13 @@ const device_t via_vt82c49x_device = {
NULL, NULL, NULL,
NULL
};
const device_t via_vt82c49x_ide_device = {
"VIA VT82C49X (With IDE)",
0,
1,
vt82c49x_init, vt82c49x_close, NULL,
NULL, NULL, NULL,
NULL
};

88
src/chipset/via_vt82c505.c
View File

@@ -10,12 +10,12 @@
*
*
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Tiseno100.
* Copyright 2020 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
@@ -24,15 +24,18 @@
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
typedef struct vt82c505_t
{
uint8_t pci_conf[256];
} vt82c505_t;
static void
vt82c505_write(int func, int addr, uint8_t val, void *priv)
{
@@ -40,55 +43,51 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv)
vt82c505_t *dev = (vt82c505_t *) priv;
/* Read-Only Registers */
switch (addr)
{
case 0x00: case 0x01:
case 0x02: case 0x03:
return;
switch (addr) {
case 0x00: case 0x01:
case 0x02: case 0x03:
return;
}
switch(addr)
{
switch(addr) {
case 0x04:
dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x07) | (val & 0x07);
break;
case 0x04:
dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x07) | (val & 0x07);
break;
case 0x07:
dev->pci_conf[0x07] = (dev->pci_conf[0x07] & ~0x90) | (val & 0x90);
break;
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0x90);
break;
case 0x90:
if((dev->pci_conf[0x90] & 0x08) && ((val & 0x07) != 0))
pci_set_irq_routing(PCI_INTC, val & 0x07);
else
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
if ((dev->pci_conf[0x90] & 0x08) && ((val & 0x07) != 0))
pci_set_irq_routing(PCI_INTC, val & 0x07);
else
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
if((dev->pci_conf[0x90] & 0x80) && (((val & 0x07) << 4) != 0))
pci_set_irq_routing(PCI_INTD, ((val & 0x07) << 4));
else
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
break;
if ((dev->pci_conf[0x90] & 0x80) && (((val & 0x07) << 4) != 0))
pci_set_irq_routing(PCI_INTD, ((val & 0x07) << 4));
else
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
break;
case 0x91:
if((dev->pci_conf[0x91] & 0x08) && ((val & 0x07) != 0))
pci_set_irq_routing(PCI_INTA, val & 0x07);
else
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
if((dev->pci_conf[0x91] & 0x80) && (((val & 0x07) << 4) != 0))
pci_set_irq_routing(PCI_INTB, ((val & 0x07) << 4));
else
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
break;
case 0x91:
if ((dev->pci_conf[0x91] & 0x08) && ((val & 0x07) != 0))
pci_set_irq_routing(PCI_INTA, val & 0x07);
else
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
if ((dev->pci_conf[0x91] & 0x80) && (((val & 0x07) << 4) != 0))
pci_set_irq_routing(PCI_INTB, ((val & 0x07) << 4));
else
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
break;
}
}
static uint8_t
vt82c505_read(int func, int addr, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
@@ -97,17 +96,19 @@ vt82c505_read(int func, int addr, void *priv)
return ret;
}
static void
vt82c505_reset(void *priv)
{
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
pic_reset();
}
static void
vt82c505_close(void *priv)
{
@@ -116,10 +117,10 @@ vt82c505_close(void *priv)
free(dev);
}
static void *
vt82c505_init(const device_t *info)
{
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
memset(dev, 0, sizeof(vt82c505_t));
@@ -132,21 +133,18 @@ vt82c505_init(const device_t *info)
dev->pci_conf[0x03] = 0x05;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x90;
dev->pci_conf[0x81] = 0x01;
dev->pci_conf[0x84] = 0x03;
dev->pci_conf[0x85] = 0x00;
dev->pci_conf[0x93] = 0x40;
return dev;
}
const device_t via_vt82c505_device = {
"VIA VT82C505",
DEVICE_PCI,

2
src/codegen/codegen_ops_misc.h
View File

@@ -19,7 +19,9 @@ static uint32_t ropCLI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
return 0;
CLEAR_BITS((uintptr_t)&cpu_state.flags, I_FLAG);
#ifdef CHECK_INT
CLEAR_BITS((uintptr_t)&pic_pending, 0xffffffff);
#endif
return op_pc;
}
static uint32_t ropSTI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)

2
src/config.c
View File

@@ -594,7 +594,7 @@ load_video(void)
char *p;
int free_p = 0;
if (machines[machine].flags & MACHINE_VIDEO_FIXED) {
if (machines[machine].flags & MACHINE_VIDEO_ONLY) {
config_delete_var(cat, "gfxcard");
gfxcard = VID_INTERNAL;
} else {

4
src/cpu/386.c
View File

@@ -314,7 +314,7 @@ exec386(int cycs)
nmi_auto_clear = 0;
nmi = 0;
}
} else if ((cpu_state.flags & I_FLAG) && pic_intpending) {
} else if ((cpu_state.flags & I_FLAG) && pic.int_pending) {
vector = picinterrupt();
if (vector != -1) {
flags_rebuild();
@@ -341,7 +341,7 @@ exec386(int cycs)
}
if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t) tsc))
timer_process();
timer_process_inline();
}
}
}

24
src/cpu/386_common.c
View File

@@ -16,6 +16,7 @@
#include "x87.h"
#include <86box/nmi.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/fdd.h>
@@ -62,7 +63,7 @@ extern uint32_t pccache;
int in_sys = 0, unmask_a20_in_smm = 0;
uint32_t old_rammask = 0xffffffff;
smram_t temp_smram[2];
int soft_reset_mask = 0;
#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
@@ -1026,14 +1027,8 @@ enter_smm(int in_hlt)
EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP);
in_smm = 1;
if (smram[0].size)
mem_mapping_recalc(smram[0].host_base, smram[0].size);
if (smram[1].size)
mem_mapping_recalc(smram[1].host_base, smram[1].size);
/* This is used by leave_smm() to make sure we don't keep the old mappings in SMM mode if the SMM
handler has told the chipset to change the actual mappings. */
memcpy(temp_smram, smram, sizeof(temp_smram));
flushmmucache();
smram_backup_all();
smram_recalc_all(0);
memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
@@ -1173,16 +1168,7 @@ leave_smm(void)
smram_restore_state_p6(saved_state);
in_smm = 0;
if (temp_smram[0].size)
mem_mapping_recalc(temp_smram[0].host_base, temp_smram[0].size);
if (temp_smram[1].size)
mem_mapping_recalc(temp_smram[1].host_base, temp_smram[1].size);
memset(temp_smram, 0x00, sizeof(temp_smram));
if (smram[0].size)
mem_mapping_recalc(smram[0].host_base, smram[0].size);
if (smram[1].size)
mem_mapping_recalc(smram[1].host_base, smram[1].size);
flushmmucache();
smram_recalc_all(1);
cpu_state.op32 = use32;

8
src/cpu/386_dynarec.c
View File

@@ -391,7 +391,7 @@ void exec386_dynarec(int cycs)
CPU_BLOCK_END();
else if (nmi && nmi_enable && nmi_mask)
CPU_BLOCK_END();
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
else if ((cpu_state.flags & I_FLAG) && pic.int_pending)
CPU_BLOCK_END();
}
}
@@ -626,7 +626,7 @@ void exec386_dynarec(int cycs)
CPU_BLOCK_END();
else if (nmi && nmi_enable && nmi_mask)
CPU_BLOCK_END();
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
else if ((cpu_state.flags & I_FLAG) && pic.int_pending)
CPU_BLOCK_END();
}
@@ -715,7 +715,7 @@ void exec386_dynarec(int cycs)
CPU_BLOCK_END();
else if (nmi && nmi_enable && nmi_mask)
CPU_BLOCK_END();
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
else if ((cpu_state.flags & I_FLAG) && pic.int_pending)
CPU_BLOCK_END();
}
@@ -813,7 +813,7 @@ void exec386_dynarec(int cycs)
nmi = 0;
}
}
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
else if ((cpu_state.flags & I_FLAG) && pic.int_pending)
{
vector = picinterrupt();
if (vector != -1)

184
src/cpu/808x.c
View File

@@ -9,13 +9,11 @@
* 808x CPU emulation, mostly ported from reenigne's XTCE, which
* is cycle-accurate.
*
*
*
* Authors: Andrew Jenner, <https://www.reenigne.org>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2015-2019 Andrew Jenner.
* Copyright 2016-2019 Miran Grca.
* Copyright 2015-2020 Andrew Jenner.
* Copyright 2016-2020 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
@@ -91,15 +89,16 @@ static int noint = 0;
static int in_lock = 0;
static int cpu_alu_op, pfq_size;
static uint16_t cpu_src = 0, cpu_dest = 0;
static uint16_t cpu_data = 0, last_addr = 0x0000;
static uint32_t cpu_src = 0, cpu_dest = 0;
static uint32_t cpu_data = 0;
static uint16_t last_addr = 0x0000;
static uint32_t *ovr_seg = NULL;
static int prefetching = 1, completed = 1;
static int in_rep = 0, repeating = 0;
static int oldc, clear_lock = 0;
static int refresh = 0, takeint = 0;
static int cycdiff;
static int refresh = 0, cycdiff;
/* Various things needed for 8087. */
@@ -209,22 +208,6 @@ get_last_addr(void)
}
static int
irq_pending(void)
{
uint8_t temp;
if (takeint && !noint)
temp = 1;
else
temp = (nmi && nmi_enable && nmi_mask) || ((cpu_state.flags & T_FLAG) && !noint);
takeint = (cpu_state.flags & I_FLAG) && (pic.pend &~ pic.mask);
return temp;
}
static void
clock_start(void)
{
@@ -232,7 +215,7 @@ clock_start(void)
}
static void
static void
clock_end(void)
{
int diff = cycdiff - cycles;
@@ -294,20 +277,14 @@ sub_cycles(int c)
#undef readmeml
#undef readmemq
/* Common read function. */
static uint8_t
readmemb_common(uint32_t a)
{
uint8_t ret;
if (readlookup2 == NULL)
ret = readmembl(a);
else {
if (readlookup2[(a) >> 12] == ((uintptr_t) -1))
ret = readmembl(a);
else
ret = *(uint8_t *)(readlookup2[(a) >> 12] + (a));
}
ret = read_mem_b(a);
return ret;
}
@@ -414,14 +391,7 @@ readmemq(uint32_t s, uint16_t a)
static void
writememb_common(uint32_t a, uint8_t v)
{
if (writelookup2 == NULL)
writemembl(a, v);
else {
if (writelookup2[(a) >> 12] == ((uintptr_t) -1))
writemembl(a, v);
else
*(uint8_t *)(writelookup2[a >> 12] + a) = v;
}
write_mem_b(a, v);
if ((a >= 0xf0000) && (a <= 0xfffff))
last_addr = a & 0xffff;
@@ -896,6 +866,13 @@ makeznptable(void)
}
static void load_cs(uint16_t seg)
{
cpu_state.seg_cs.base = seg << 4;
CS = seg & 0xffff;
}
/* Common reset function. */
static void
reset_common(int hard)
@@ -933,11 +910,11 @@ reset_common(int hard)
cpu_state.eflags = 0;
cgate32 = 0;
if (AT) {
loadcs(0xF000);
load_cs(0xF000);
cpu_state.pc = 0xFFF0;
rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
} else {
loadcs(0xFFFF);
load_cs(0xFFFF);
cpu_state.pc = 0;
rammask = 0xfffff;
}
@@ -969,7 +946,6 @@ reset_common(int hard)
cpu_alt_reset = 0;
prefetching = 1;
takeint = 0;
cpu_ven_reset();
@@ -994,6 +970,8 @@ void
resetx86(void)
{
reset_common(1);
soft_reset_mask = 0;
}
@@ -1001,6 +979,9 @@ resetx86(void)
void
softresetx86(void)
{
if (soft_reset_mask)
return;
reset_common(0);
}
@@ -1125,7 +1106,9 @@ interrupt(uint16_t addr)
cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff;
access(6, 16);
new_cs = readmemw(0, cpu_state.eaaddr);
prefetching = 0;
pfq_clear();
ovr_seg = NULL;
access(39, 16);
tempf = cpu_state.flags & 0x0fd7;
push(&tempf);
@@ -1133,7 +1116,7 @@ interrupt(uint16_t addr)
access(40, 16);
push(&old_cs);
old_ip = cpu_state.pc;
loadcs(new_cs);
load_cs(new_cs);
access(68, 16);
set_ip(new_ip);
access(41, 16);
@@ -1141,6 +1124,20 @@ interrupt(uint16_t addr)
}
static int
irq_pending(void)
{
uint8_t temp;
if ((cpu_state.flags & I_FLAG) && pic.int_pending && !noint)
temp = 1;
else
temp = (nmi && nmi_enable && nmi_mask) || ((cpu_state.flags & T_FLAG) && !noint);
return temp;
}
static void
check_interrupts(void)
{
@@ -1156,16 +1153,24 @@ check_interrupts(void)
interrupt(2);
return;
}
temp = picinterrupt();
if (temp != -1) {
if ((cpu_state.flags & I_FLAG) && pic.int_pending && !noint) {
repeating = 0;
completed = 1;
ovr_seg = NULL;
wait(3, 0);
/* ACK to PIC */
temp = pic_irq_ack();
wait(1, 0);
/* ACK to PIC */
temp = pic_irq_ack();
wait(1, 0);
in_lock = 0;
clear_lock = 0;
ovr_seg = NULL;
wait(9, 0);
interrupt((uint16_t) (temp & 0xffff));
wait(1, 0);
/* Here is where temp should be filled, but we cheat. */
wait(3, 0);
opcode = 0x00;
interrupt(temp);
}
}
}
@@ -1511,6 +1516,7 @@ mul(uint16_t a, uint16_t b)
set_sf(bit_count);
set_pf();
set_af(0);
}
@@ -1521,12 +1527,19 @@ set_of_rotate(int bits)
}
static void
set_zf_ex(int bits, int zf)
{
cpu_state.flags = (cpu_state.flags & ~0x40) | (zf ? 0x40 : 0);
}
static void
set_zf(int bits)
{
int size_mask = (1 << bits) - 1;
cpu_state.flags = (cpu_state.flags & ~0x40) | (((cpu_data & size_mask) == 0) ? 0x40 : 0);
set_zf_ex(bits, (cpu_data & size_mask) == 0);
}
@@ -1544,6 +1557,9 @@ set_co_mul(int carry)
{
set_cf(carry);
set_of(carry);
/* NOTE: When implementing the V20, care should be taken to not change
the zero flag. */
set_zf(!carry);
if (!carry)
wait(1, 0);
}
@@ -1693,8 +1709,8 @@ stos(int bits)
static void
aa(void)
{
set_of(0);
AL &= 0x0f;
set_pzs(8);
AL = cpu_data & 0x0f;
wait(6, 0);
}
@@ -1771,6 +1787,7 @@ void
execx86(int cycs)
{
uint8_t temp = 0, temp2;
uint8_t old_af;
uint16_t addr, tempw;
uint16_t new_cs, new_ip;
uint32_t result;
@@ -1793,6 +1810,7 @@ execx86(int cycs)
}
completed = 1;
// pclog("[%04X:%04X] Opcode: %02X\n", CS, cpu_state.pc, opcode);
switch (opcode) {
case 0x06: case 0x0E: case 0x16: case 0x1E: /* PUSH seg */
access(29, 16);
@@ -1801,7 +1819,7 @@ execx86(int cycs)
case 0x07: case 0x0F: case 0x17: case 0x1F: /* POP seg */
access(22, 16);
if (opcode == 0x0F) {
loadcs(pop());
load_cs(pop());
pfq_pos = 0;
} else
loadseg(pop(), _opseg[(opcode >> 3) & 0x03]);
@@ -1878,15 +1896,15 @@ execx86(int cycs)
case 0x27: /*DAA*/
cpu_dest = AL;
set_of(0);
temp = !!(cpu_state.flags & A_FLAG);
old_af = !!(cpu_state.flags & A_FLAG);
if ((cpu_state.flags & A_FLAG) || (AL & 0x0f) > 9) {
cpu_src = 6;
cpu_data = cpu_dest + cpu_src;
set_of_add(8);
cpu_dest = cpu_data;
cpu_dest += cpu_data;
set_af(1);
}
if ((cpu_state.flags & C_FLAG) || AL > (temp ? 0x9f : 0x99)) {
if ((cpu_state.flags & C_FLAG) || AL > (old_af ? 0x9f : 0x99)) {
cpu_src = 0x60;
cpu_data = cpu_dest + cpu_src;
set_of_add(8);
@@ -1900,15 +1918,15 @@ execx86(int cycs)
case 0x2F: /*DAS*/
cpu_dest = AL;
set_of(0);
temp = !!(cpu_state.flags & A_FLAG);
if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9)) {
old_af = !!(cpu_state.flags & A_FLAG);
if ((cpu_state.flags & A_FLAG) || (AL & 0xf) > 9) {
cpu_src = 6;
cpu_data = cpu_dest - cpu_src;
set_of_sub(8);
cpu_dest = cpu_data;
set_af(1);
}
if ((cpu_state.flags & C_FLAG) || AL > (temp ? 0x9f : 0x99)) {
if ((cpu_state.flags & C_FLAG) || AL > (old_af ? 0x9f : 0x99)) {
cpu_src = 0x60;
cpu_data = cpu_dest - cpu_src;
set_of_sub(8);
@@ -1921,7 +1939,7 @@ execx86(int cycs)
break;
case 0x37: /*AAA*/
wait(1, 0);
if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9)) {
if ((cpu_state.flags & A_FLAG) || (AL & 0xf) > 9) {
cpu_src = 6;
++AH;
set_ca();
@@ -1932,13 +1950,12 @@ execx86(int cycs)
}
cpu_dest = AL;
cpu_data = cpu_dest + cpu_src;
AL = cpu_data;
set_of_add(8);
aa();
break;
case 0x3F: /*AAS*/
wait(1, 0);
if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9)) {
if ((cpu_state.flags & A_FLAG) || (AL & 0xf) > 9) {
cpu_src = 6;
--AH;
set_ca();
@@ -1949,7 +1966,6 @@ execx86(int cycs)
}
cpu_dest = AL;
cpu_data = cpu_dest - cpu_src;
AL = cpu_data;
set_of_sub(8);
aa();
break;
@@ -2137,7 +2153,7 @@ execx86(int cycs)
access(51, 16);
tempw = geteaw();
if ((rmdat & 0x18) == 0x08) {
loadcs(tempw);
load_cs(tempw);
pfq_pos = 0;
} else
loadseg(tempw, _opseg[(rmdat & 0x18) >> 3]);
@@ -2195,7 +2211,7 @@ execx86(int cycs)
push(&(CS));
access(60, 16);
cpu_state.oldpc = cpu_state.pc;
loadcs(new_cs);
load_cs(new_cs);
set_ip(new_ip);
access(32, 16);
push((uint16_t *) &(cpu_state.oldpc));
@@ -2407,7 +2423,7 @@ execx86(int cycs)
SP += cpu_src;
wait(1, 0);
}
loadcs(new_cs);
load_cs(new_cs);
access(72, bits);
set_ip(new_ip);
break;
@@ -2460,7 +2476,7 @@ execx86(int cycs)
wait(3, 0);
access(44, 8);
new_cs = pop();
loadcs(new_cs);
load_cs(new_cs);
access(62, 8);
set_ip(new_ip);
access(45, 8);
@@ -2494,6 +2510,7 @@ execx86(int cycs)
cpu_data <<= 1;
cpu_data |= ((cpu_state.flags & C_FLAG) ? 1 : 0);
set_of_rotate(bits);
set_af(0);
break;
case 0x08: /* ROR */
set_cf((cpu_data & 1) != 0);
@@ -2501,11 +2518,13 @@ execx86(int cycs)
if (cpu_state.flags & C_FLAG)
cpu_data |= (!(opcode & 1) ? 0x80 : 0x8000);
set_of_rotate(bits);
set_af(0);
break;
case 0x10: /* RCL */
set_cf(top_bit(cpu_data, bits));
cpu_data = (cpu_data << 1) | (oldc ? 1 : 0);
set_of_rotate(bits);
set_af(0);
break;
case 0x18: /* RCR */
set_cf((cpu_data & 1) != 0);
@@ -2514,18 +2533,20 @@ execx86(int cycs)
cpu_data |= (!(opcode & 0x01) ? 0x80 : 0x8000);
set_cf((cpu_dest & 1) != 0);
set_of_rotate(bits);
set_af(0);
break;
case 0x20: /* SHL */
set_cf(top_bit(cpu_data, bits));
cpu_data <<= 1;
set_of_rotate(bits);
set_af((cpu_data & 0x10) != 0);
set_pzs(bits);
break;
case 0x28: /* SHR */
set_cf((cpu_data & 1) != 0);
cpu_data >>= 1;
set_of_rotate(bits);
set_af(1);
set_af(0);
set_pzs(bits);
break;
case 0x30: /* SETMO - undocumented? */
@@ -2543,7 +2564,7 @@ execx86(int cycs)
else
cpu_data |= (cpu_dest & 0x8000);
set_of_rotate(bits);
set_af(1);
set_af(0);
set_pzs(bits);
break;
}
@@ -2564,9 +2585,11 @@ execx86(int cycs)
case 0xD5: /*AAD*/
wait(1, 0);
mul(pfq_fetchb(), AH);
AL += cpu_data;
cpu_dest = AL;
cpu_src = cpu_data;
add(8);
AL = cpu_data;
AH = 0x00;
set_pzs(16);
break;
case 0xD6: /*SALC*/
wait(1, 0);
@@ -2700,7 +2723,7 @@ execx86(int cycs)
addr = pfq_fetchw();
wait(1, 0);
tempw = pfq_fetchw();
loadcs(tempw);
load_cs(tempw);
access(70, 8);
pfq_clear();
set_ip(addr);
@@ -2783,25 +2806,24 @@ execx86(int cycs)
mul(AX, cpu_data);
AX = cpu_data;
DX = cpu_dest;
cpu_data |= DX;
result = ((uint32_t) DX << 16) | AX;
if ((rmdat & 0x38) == 0x20)
set_co_mul(DX != 0x0000);
else
set_co_mul(result != sign_extend32(AX));
cpu_data = DX;
} else {
mul(AL, cpu_data);
AL = (uint8_t) cpu_data;
AH = (uint8_t) cpu_dest;
cpu_data |= AH;
if ((rmdat & 0x38) == 0x20)
set_co_mul(AH != 0x00);
else
set_co_mul(AX != sign_extend(AL));
cpu_data = AH;
}
/* NOTE: When implementing the V20, care should be taken to not change
the zero flag. */
set_zf(bits);
set_sf(bits);
set_pf();
if (cpu_mod != 3)
wait(1, 0);
break;
@@ -2883,7 +2905,7 @@ execx86(int cycs)
access(64, bits);
wait(4, 0);
cpu_state.oldpc = cpu_state.pc;
loadcs(new_cs);
load_cs(new_cs);
set_ip(new_ip);
access(37, bits);
push((uint16_t *) &(cpu_state.oldpc));
@@ -2900,7 +2922,7 @@ execx86(int cycs)
if (!(opcode & 1))
cpu_data |= 0xff00;
new_cs = cpu_data;
loadcs(new_cs);
load_cs(new_cs);
access(66, bits);
set_ip(new_ip);
break;
@@ -2909,7 +2931,7 @@ execx86(int cycs)
if (cpu_mod != 3)
wait(1, 0);
access(38, bits);
push(&(cpu_data));
push((uint16_t *) &(cpu_data));
break;
}
break;

1
src/cpu/cpu.h
View File

@@ -492,6 +492,7 @@ extern uint32_t old_rammask;
extern int acycs;
#endif
extern int pic_pending, is_vpc;
extern int soft_reset_mask;
extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
extern uint32_t cpu_fast_off_flags;

4
src/cpu/x86_ops_misc.h
View File

@@ -614,10 +614,10 @@ static int opHLT(uint32_t fetchdat)
}
if (smi_line)
enter_smm_check(1);
else if (!((cpu_state.flags & I_FLAG) && pic_intpending))
else if (!((cpu_state.flags & I_FLAG) && pic.int_pending))
{
CLOCK_CYCLES_ALWAYS(100);
if (!((cpu_state.flags & I_FLAG) && pic_intpending))
if (!((cpu_state.flags & I_FLAG) && pic.int_pending))
cpu_state.pc--;
}
else

12
src/cpu/x86_ops_mov_ctrl.h
View File

@@ -12,6 +12,12 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
cpu_state.regs[cpu_rm].l = cr0;
if (is486 || isibm486)
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
else {
if (is386)
cpu_state.regs[cpu_rm].l |=0x7fffffe0;
else
cpu_state.regs[cpu_rm].l |=0x7ffffff0;
}
break;
case 2:
cpu_state.regs[cpu_rm].l = cr2;
@@ -48,6 +54,12 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
cpu_state.regs[cpu_rm].l = cr0;
if (is486 || isibm486)
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
else {
if (is386)
cpu_state.regs[cpu_rm].l |=0x7fffffe0;
else
cpu_state.regs[cpu_rm].l |=0x7ffffff0;
}
break;
case 2:
cpu_state.regs[cpu_rm].l = cr2;

2
src/cpu/x86_ops_pmode.h
View File

@@ -371,7 +371,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
if (is486 || isibm486) seteaw(msw);
else if (is386) seteaw(msw | 0xFF00);
else if (is386) seteaw(msw | /* 0xFF00 */ 0xFFE0);
else seteaw(msw | 0xFFF0);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);

18
src/device.c
View File

@@ -513,23 +513,23 @@ device_is_valid(const device_t *device, int mflags)
{
if (device == NULL) return(1);
if ((device->flags & DEVICE_AT) && !(mflags & MACHINE_AT)) return(0);
if ((device->flags & DEVICE_AT) && !(mflags & MACHINE_BUS_ISA16)) return(0);
if ((device->flags & DEVICE_CBUS) && !(mflags & MACHINE_CBUS)) return(0);
if ((device->flags & DEVICE_CBUS) && !(mflags & MACHINE_BUS_CBUS)) return(0);
if ((device->flags & DEVICE_ISA) && !(mflags & MACHINE_ISA)) return(0);
if ((device->flags & DEVICE_ISA) && !(mflags & MACHINE_BUS_ISA)) return(0);
if ((device->flags & DEVICE_MCA) && !(mflags & MACHINE_MCA)) return(0);
if ((device->flags & DEVICE_MCA) && !(mflags & MACHINE_BUS_MCA)) return(0);
if ((device->flags & DEVICE_EISA) && !(mflags & MACHINE_EISA)) return(0);
if ((device->flags & DEVICE_EISA) && !(mflags & MACHINE_BUS_EISA)) return(0);
if ((device->flags & DEVICE_VLB) && !(mflags & MACHINE_VLB)) return(0);
if ((device->flags & DEVICE_VLB) && !(mflags & MACHINE_BUS_VLB)) return(0);
if ((device->flags & DEVICE_PCI) && !(mflags & MACHINE_PCI)) return(0);
if ((device->flags & DEVICE_PCI) && !(mflags & MACHINE_BUS_PCI)) return(0);
if ((device->flags & DEVICE_AGP) && !(mflags & MACHINE_AGP)) return(0);
if ((device->flags & DEVICE_AGP) && !(mflags & MACHINE_BUS_AGP)) return(0);
if ((device->flags & DEVICE_PS2) && !(mflags & MACHINE_PS2)) return(0);
if ((device->flags & DEVICE_PS2) && !(mflags & MACHINE_BUS_PS2)) return(0);
return(1);
}

3
src/device/keyboard.c
View File

@@ -93,7 +93,8 @@ key_process(uint16_t scan, int down)
scancode *codes = scan_table;
int c;
if (! keyboard_scan) return;
if (!keyboard_scan || (keyboard_send == NULL))
return;
oldkey[scan] = down;
if (down && codes[scan].mk[0] == 0)

2
src/disk/hdc_esdi_at.c
View File

@@ -150,7 +150,7 @@ irq_lower(esdi_t *esdi)
static __inline void
irq_update(esdi_t *esdi)
{
if (esdi->irqstat && !((pic2.pend | pic2.ins) & 0x40) && !(esdi->fdisk & 2))
if (esdi->irqstat && !((pic2.irr | pic2.isr) & 0x40) && !(esdi->fdisk & 2))
picint(1 << 14);
}

17
src/disk/hdc_ide.c
View File

@@ -486,7 +486,7 @@ static void ide_hd_identify(ide_t *ide)
ide_log("Default CHS translation: %i, %i, %i\n", ide->buffer[1], ide->buffer[3], ide->buffer[6]);
ide_padstr((char *) (ide->buffer + 10), "", 20); /* Serial Number */
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION_EX, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), device_identify, 40); /* Model */
ide->buffer[20] = 3; /*Buffer type*/
ide->buffer[21] = 512; /*Buffer size*/
@@ -533,8 +533,8 @@ static void ide_hd_identify(ide_t *ide)
if (!ide_boards[ide->board]->force_ata3 && ide_bm[ide->board]) {
ide->buffer[47] = 32 | 0x8000; /*Max sectors on multiple transfer command*/
ide->buffer[80] = 0x1e; /*ATA-1 to ATA-4 supported*/
ide->buffer[81] = 0x18; /*ATA-4 revision 18 supported*/
ide->buffer[80] = 0x7e; /*ATA-1 to ATA-6 supported*/
ide->buffer[81] = 0x19; /*ATA-6 revision 3a supported*/
} else {
ide->buffer[47] = 16 | 0x8000; /*Max sectors on multiple transfer command*/
ide->buffer[80] = 0x0e; /*ATA-1 to ATA-3 supported*/
@@ -594,6 +594,12 @@ ide_identify(ide_t *ide)
ide->buffer[53] |= 0x0004;
for (i = 0; i <= max_udma; i++)
ide->buffer[88] |= (1 << i);
if (max_udma >= 4)
ide->buffer[93] = 0x6000; /* Drive reports 80-conductor cable */
if (ide->channel)
ide->buffer[93] |= 0x0d00;
else
ide->buffer[93] |= 0x007d;
}
if ((max_sdma != -1) || (max_mdma != -1) || (max_udma != -1)) {
@@ -620,9 +626,6 @@ ide_identify(ide_t *ide)
ide->buffer[88] |= d;
ide_log("PIDENTIFY DMA Mode: %04X, %04X\n", ide->buffer[62], ide->buffer[63]);
}
if (max_udma >= 4)
ide->buffer[93] = 0x6000; /* Drive reports 80-conductor cable */
}
@@ -724,7 +727,7 @@ ide_set_features(ide_t *ide)
mode = (features_data >> 3);
submode = features_data & 7;
switch(mode) {
switch (mode) {
case 0x00: /* PIO default */
if (submode != 0)
return 0;

2
src/disk/hdc_st506_at.c
View File

@@ -165,7 +165,7 @@ irq_lower(mfm_t *mfm)
static void
irq_update(mfm_t *mfm)
{
if (mfm->irqstat && !((pic2.pend | pic2.ins) & 0x40) && !(mfm->fdisk & 2))
if (mfm->irqstat && !((pic2.irr | pic2.isr) & 0x40) && !(mfm->fdisk & 2))
picint(1 << 14);
}

14
src/disk/hdd.c
View File

@@ -46,7 +46,7 @@ hdd_string_to_bus(char *str, int cdrom)
if (! strcmp(str, "none"))
return(HDD_BUS_DISABLED);
if (! strcmp(str, "mfm")) {
if (! strcmp(str, "mfm") || ! strcmp(str, "rll")) {
if (cdrom) {
no_cdrom:
ui_msgbox_header(MBX_ERROR, (wchar_t *) IDS_2130, (wchar_t *) IDS_4099);
@@ -70,10 +70,10 @@ no_cdrom:
return(HDD_BUS_IDE);
if (! strcmp(str, "atapi_pio_only"))
return(HDD_BUS_IDE);
return(HDD_BUS_ATAPI);
if (! strcmp(str, "atapi"))
return(HDD_BUS_IDE);
return(HDD_BUS_ATAPI);
if (! strcmp(str, "eide"))
return(HDD_BUS_IDE);
@@ -88,7 +88,7 @@ no_cdrom:
return(HDD_BUS_IDE);
if (! strcmp(str, "atapi_pio_and_dma"))
return(HDD_BUS_IDE);
return(HDD_BUS_ATAPI);
if (! strcmp(str, "scsi"))
return(HDD_BUS_SCSI);
@@ -120,7 +120,11 @@ hdd_bus_to_string(int bus, int cdrom)
break;
case HDD_BUS_IDE:
s = cdrom ? "atapi" : "ide";
s = "ide";
break;
case HDD_BUS_ATAPI:
s = "atapi";
break;
case HDD_BUS_SCSI:

8
src/disk/mo.c
View File

@@ -1736,7 +1736,7 @@ mo_command(scsi_common_t *sc, uint8_t *cdb)
} else {
ide_padstr8(dev->buffer + 8, 8, EMU_NAME); /* Vendor */
ide_padstr8(dev->buffer + 16, 16, device_identify); /* Product */
ide_padstr8(dev->buffer + 32, 4, EMU_VERSION); /* Revision */
ide_padstr8(dev->buffer + 32, 4, EMU_VERSION_EX); /* Revision */
}
idx = 36;
@@ -2059,13 +2059,13 @@ mo_do_identify(ide_t *ide, int ide_has_dma)
ide_padstr((char *) (ide->buffer + 27), model, 40); /* Model */
} else {
snprintf(model, 40, "%s %s%02i", EMU_NAME, "86B_MO", mo->id);
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION_EX, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), model, 40); /* Model */
}
if (ide_has_dma) {
ide->buffer[80] = 0x30; /*Supported ATA versions : ATA/ATAPI-4 ATA/ATAPI-5*/
ide->buffer[81] = 0x15; /*Maximum ATA revision supported : ATA/ATAPI-5 T13 1321D revision 1*/
ide->buffer[80] = 0x70; /*Supported ATA versions : ATA/ATAPI-4 ATA/ATAPI-6*/
ide->buffer[81] = 0x19; /*Maximum ATA revision supported : ATA/ATAPI-6 T13 1410D revision 3a*/
}
}

4
src/disk/zip.c
View File

@@ -2289,8 +2289,8 @@ zip_250_identify(ide_t *ide, int ide_has_dma)
ide_padstr((char *) (ide->buffer + 27), "IOMEGA ZIP 250 ATAPI", 40); /* Model */
if (ide_has_dma) {
ide->buffer[80] = 0x30; /*Supported ATA versions : ATA/ATAPI-4 ATA/ATAPI-5*/
ide->buffer[81] = 0x15; /*Maximum ATA revision supported : ATA/ATAPI-5 T13 1321D revision 1*/
ide->buffer[80] = 0x70; /*Supported ATA versions : ATA/ATAPI-4 ATA/ATAPI-6*/
ide->buffer[81] = 0x19; /*Maximum ATA revision supported : ATA/ATAPI-6 T13 1410D revision 3a*/
}
}

69
src/floppy/fdc.c
View File

@@ -622,8 +622,10 @@ static void
fdc_rate(fdc_t *fdc, int drive)
{
fdc_update_rate(fdc, drive);
fdc_log("FDD %c: Setting rate: %i, %i, %i (%i, %i)\n", 0x41 + drive, fdc->drvrate[drive], fdc->rate, fdc_get_densel(fdc, drive), fdc->rwc[drive], fdc->densel_force);
// fdc_log("FDD %c: Setting rate: %i, %i, %i (%i, %i)\n", 0x41 + drive, fdc->drvrate[drive], fdc->rate, fdc_get_densel(fdc, drive), fdc->rwc[drive], fdc->densel_force);
fdc_log("FDD %c: [%i] Setting rate: %i, %i, %i (%i, %i, %i)\n", 0x41 + drive, fdc->enh_mode, fdc->drvrate[drive], fdc->rate, fdc_get_densel(fdc, drive), fdc->rwc[drive], fdc->densel_force, fdc->densel_polarity);
fdd_set_densel(fdc_get_densel(fdc, drive));
fdc_log("FDD %c: [%i] Densel: %i\n", 0x41 + drive, fdc->enh_mode, fdc_get_densel(fdc, drive));
}
@@ -657,6 +659,17 @@ fdc_bad_command(fdc_t *fdc)
static void
fdc_io_command_phase1(fdc_t *fdc, int out)
{
#if 0
int i;
pclog_toggle_suppr();
pclog("%02X ", fdc->processed_cmd);
for (i = 0; i < fdc->pnum; i++)
pclog("%02X ", fdc->params[i]);
pclog("\n");
pclog_toggle_suppr();
#endif
fdc_reset_fifo_buf(fdc);
fdc_rate(fdc, fdc->drive);
fdc->head = fdc->params[2];
@@ -831,6 +844,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->command = val;
fdc->stat |= 0x10;
fdc_log("Starting FDC command %02X\n",fdc->command);
fdc->error = 0;
if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) ||
((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) ||
@@ -1417,7 +1431,8 @@ fdc_read(uint16_t addr, void *priv)
default:
ret = 0xFF;
}
fdc_log("Read FDC %04X %02X\n", addr, ret);
// fdc_log("Read FDC %04X %02X\n", addr, ret);
fdc_log("[%04X:%08X] Read FDC %04X %02X [%i:%02X]\n", CS, cpu_state.pc, addr, ret, drive, fdc->dor & (0x10 << drive));
return ret;
}
@@ -1431,6 +1446,13 @@ fdc_poll_common_finish(fdc_t *fdc, int compare, int st5)
fdc->st0 = fdc->res[4] = (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0) | fdc->rw_drive;
fdc->res[5] = st5;
fdc->res[6] = 0;
if (fdc->error) {
fdc->error = 0;
fdc->st0 |= 0x40;
fdc->res[4] |= 0x40;
fdc->res[5] |= fdc->st5;
fdc->res[6] |= fdc->st6;
}
if (fdc->wrong_am) {
fdc->res[6] |= 0x40;
fdc->wrong_am = 0;
@@ -1770,6 +1792,7 @@ fdc_callback(void *priv)
void
fdc_error(fdc_t *fdc, int st5, int st6)
{
#if 1
timer_disable(&fdc->timer);
fdc_int(fdc, 1);
@@ -1806,6 +1829,48 @@ fdc_error(fdc_t *fdc, int st5, int st6)
}
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 0);
fdc->paramstogo = 7;
#else
switch(fdc->interrupt) {
case 0x02:
case 0x05:
case 0x06:
case 0x09:
case 0x0C:
case 0x11:
case 0x16:
case 0x19:
case 0x1D:
fdc->error = 1;
fdc->st5 = st5;
fdc->st6 = st6;
fdc->tc = 1;
fdc->stat = 0x10;
fdc_callback(fdc);
break;
default:
timer_disable(&fdc->timer);
fdc_int(fdc, 1);
if (!(fdc->flags & FDC_FLAG_PS1))
fdc->fintr = 0;
fdc->stat = 0xD0;
fdc->st0 = fdc->res[4] = 0x40 | (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0) | fdc->rw_drive;
if (fdc->head && !fdd_is_double_sided(real_drive(fdc, fdc->drive)))
fdc->st0 |= 0x08;
fdc->res[5] = st5;
fdc->res[6] = st6;
fdc_log("FDC Error: %02X %02X %02X\n", fdc->res[4], fdc->res[5], fdc->res[6]);
fdc->res[7]=0;
fdc->res[8]=0;
fdc->res[9]=0;
fdc->res[10]=0;
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 0);
fdc->paramstogo = 7;
break;
}
#endif
}

13
src/floppy/fdd_86f.c
View File

@@ -1609,7 +1609,9 @@ d86f_read_sector_data(int drive, int side)
dev->data_find.sync_marks = dev->data_find.bits_obtained = dev->data_find.bytes_obtained = 0;
dev->error_condition = 0;
dev->state = STATE_IDLE;
if (dev->state == STATE_11_SCAN_DATA)
if (dev->state == STATE_02_READ_DATA)
fdc_track_finishread(d86f_fdc, dev->error_condition);
else if (dev->state == STATE_11_SCAN_DATA)
fdc_sector_finishcompare(d86f_fdc, (dev->satisfying_bytes == ((128 << ((uint32_t) dev->last_sector.id.n)) - 1)) ? 1 : 0);
else
fdc_sector_finishread(d86f_fdc);
@@ -2149,20 +2151,23 @@ d86f_turbo_read(int drive, int side)
dev->data_find.sync_marks = dev->data_find.bits_obtained = dev->data_find.bytes_obtained = 0;
if ((flags & SECTOR_CRC_ERROR) && (dev->state != STATE_02_READ_DATA)) {
#ifdef ENABLE_D86F_LOG
d86f_log("86F: Data CRC error in turbo mode\n");
d86f_log("86F: Data CRC error in turbo mode (%02X)\n", dev->state);
#endif
dev->error_condition = 0;
dev->state = STATE_IDLE;
fdc_finishread(d86f_fdc);
fdc_datacrcerror(d86f_fdc);
} else if ((dev->calc_crc.word != dev->track_crc.word) && (dev->state == STATE_02_READ_DATA)) {
} else if ((flags & SECTOR_CRC_ERROR) && (dev->state == STATE_02_READ_DATA)) {
#ifdef ENABLE_D86F_LOG
d86f_log("86F: Data CRC error in turbo mode at READ TRACK command\n");
#endif
dev->error_condition |= 2; /* Mark that there was a data error. */
dev->state = STATE_IDLE;
fdc_track_finishread(d86f_fdc, dev->error_condition);
} else {
/* CRC is valid. */
#ifdef ENABLE_D86F_LOG
d86f_log("86F: Data CRC OK error in turbo mode\n");
d86f_log("86F: Data CRC OK in turbo mode\n");
#endif
dev->error_condition = 0;
dev->state = STATE_IDLE;

5
src/floppy/fdd_json.c
View File

@@ -108,6 +108,7 @@ typedef struct {
static json_t *images[FDD_NUM];
#define ENABLE_JSON_LOG 1
#ifdef ENABLE_JSON_LOG
int json_do_log = ENABLE_JSON_LOG;
@@ -247,9 +248,9 @@ load_image(json_t *dev)
switch(state) {
case 0: /* read level header */
dev->dmf = 1;
if (c != '[') {
if ((c != '[') && (c != '{') && (c != '\r') && (c != '\n')) {
state = unexpect(c, state, level);
} else {
} else if (c == '[') {
if (++level == 3)
state++;
}

1
src/floppy/fdd_td0.c
View File

@@ -1121,6 +1121,7 @@ td0_seek(int drive, int track)
id[1] = dev->sects[track][side][actual_sector].head;
id[2] = real_sector;
id[3] = dev->sects[track][side][actual_sector].size;
pclog("track %i, side %i, %i,%i,%i,%i %i\n", track, side, id[0], id[1], id[2], id[3], dev->sects[track][side][actual_sector].flags);
fm = dev->sects[track][side][actual_sector].fm;
if (((dev->sects[track][side][actual_sector].flags & 0x42) || (id[3] > (dev->max_sector_size - fm))) && !fdd_get_turbo(drive))
ssize = 3;

2
src/include/86box/cdrom.h
View File

@@ -56,7 +56,7 @@ extern "C" {
enum {
CDROM_BUS_DISABLED = 0,
CDROM_BUS_ATAPI = 4,
CDROM_BUS_ATAPI = 5,
CDROM_BUS_SCSI,
CDROM_BUS_USB
};

8
src/include/86box/chipset.h
View File

@@ -89,6 +89,9 @@ extern const device_t opti5x7_device;
/* SiS */
extern const device_t rabbit_device;
extern const device_t sis_85c401_device;
extern const device_t sis_85c460_device;
extern const device_t sis_85c461_device;
extern const device_t sis_85c471_device;
extern const device_t sis_85c496_device;
extern const device_t sis_85c496_ls486e_device;
@@ -110,16 +113,13 @@ extern const device_t stpc_lpt_device;
extern const device_t umc491_device;
/* VIA */
extern const device_t via_vt82c49x_device;
extern const device_t via_vt82c49x_ide_device;
extern const device_t via_vt82c505_device;
extern const device_t via_vpx_device;
extern const device_t via_vp3_device;
extern const device_t via_mvp3_device;
extern const device_t via_apro_device;
extern const device_t via_vt82c586b_device;
extern const device_t via_vt82c596_device;
extern const device_t via_vt82c596b_device;

2
src/include/86box/fdc.h
View File

@@ -39,7 +39,7 @@ extern int fdc_type;
typedef struct {
uint8_t dor, stat, command, processed_cmd, dat, st0, swap, dtl;
uint8_t swwp, disable_write;
uint8_t swwp, disable_write, st5, st6, error;
uint8_t params[8], res[11];
uint8_t specify[2];
uint8_t config, pretrk;

1
src/include/86box/hdd.h
View File

@@ -66,6 +66,7 @@ enum {
HDD_BUS_XTA,
HDD_BUS_ESDI,
HDD_BUS_IDE,
HDD_BUS_ATAPI,
HDD_BUS_SCSI,
HDD_BUS_USB
};

22
src/include/86box/language.h
View File

@@ -144,18 +144,16 @@
#define IDS_4352 4352 // "MFM/RLL"
#define IDS_4353 4353 // "XT IDE"
#define IDS_4354 4354 // "ESDI"
#define IDS_4355 4355 // "IDE (PIO-only)"
#define IDS_4356 4356 // "IDE (PIO+DMA)"
#define IDS_4355 4355 // "IDE"
#define IDS_4356 4356 // "ATAPI"
#define IDS_4357 4357 // "SCSI"
#define IDS_4358 4358 // "SCSI (removable)"
#define IDS_4608 4608 // "MFM/RLL (%01i:%01i)"
#define IDS_4609 4609 // "XT IDE (%01i:%01i)"
#define IDS_4610 4610 // "ESDI (%01i:%01i)"
#define IDS_4611 4611 // "IDE (PIO-only) (%01i:%01i)"
#define IDS_4612 4612 // "IDE (PIO+DMA) (%01i:%01i)"
#define IDS_4611 4611 // "IDE (%01i:%01i)"
#define IDS_4612 4612 // "ATAPI (%01i:%01i)"
#define IDS_4613 4613 // "SCSI (%02i:%02i)"
#define IDS_4614 4614 // "SCSI (removable) (%02i:%02i)"
#define IDS_5120 5120 // "CD-ROM %i (%s): %s"
@@ -163,16 +161,16 @@
#define IDS_5377 5377 // <Reserved>
#define IDS_5378 5378 // <Reserved>
#define IDS_5379 5379 // <Reserved>
#define IDS_5380 5380 // "ATAPI (PIO-only)"
#define IDS_5381 5381 // "ATAPI (PIO and DMA)"
#define IDS_5380 5380 // <Reserved>
#define IDS_5381 5381 // "ATAPI"
#define IDS_5382 5382 // "SCSI"
#define IDS_5632 5632 // "Disabled"
#define IDS_5633 5633 // <Reserved>
#define IDS_5634 5634 // <Reserved>
#define IDS_5635 5635 // <Reserved>
#define IDS_5636 5636 // "ATAPI (PIO-only) (%01i:%01i)"
#define IDS_5637 5637 // "ATAPI (PIO and DMA) (%01i:%01i)"
#define IDS_5636 5636 // <Reserved>
#define IDS_5637 5637 // "ATAPI (%01i:%01i)"
#define IDS_5638 5638 // "SCSI (%02i:%02i)"
#define IDS_5888 5888 // "160 kB"
@@ -212,8 +210,8 @@
#define STR_NUM_2048 92
#define STR_NUM_3072 11
#define STR_NUM_4096 18
#define STR_NUM_4352 7
#define STR_NUM_4608 7
#define STR_NUM_4352 6
#define STR_NUM_4608 6
#define STR_NUM_5120 1
#define STR_NUM_5376 7
#define STR_NUM_5632 7

103
src/include/86box/machine.h
View File

@@ -23,43 +23,65 @@
/* Machine feature flags. */
#ifdef NEW_FLAGS
#define MACHINE_PC 0x000000 /* PC architecture */
#define MACHINE_AT 0x000001 /* PC/AT architecture */
#define MACHINE_PS2 0x000002 /* PS/2 architecture */
#define MACHINE_ISA 0x000010 /* sys has ISA bus */
#define MACHINE_CBUS 0x000020 /* sys has C-BUS bus */
#define MACHINE_EISA 0x000040 /* sys has EISA bus */
#define MACHINE_VLB 0x000080 /* sys has VL bus */
#define MACHINE_MCA 0x000100 /* sys has MCA bus */
#define MACHINE_PCI 0x000200 /* sys has PCI bus */
#define MACHINE_AGP 0x000400 /* sys has AGP bus */
#define MACHINE_HDC 0x001000 /* sys has int HDC */
#define MACHINE_VIDEO 0x002000 /* sys has int video */
#define MACHINE_VIDEO_FIXED 0x004000 /* sys has ONLY int video */
#define MACHINE_MOUSE 0x008000 /* sys has int mouse */
#define MACHINE_SOUND 0x010000 /* sys has int sound */
#define MACHINE_NONMI 0x020000 /* sys does not have NMI's */
#define MACHINE_FDC 0x040000 /* sys has int FDC */
#else
#define MACHINE_PC 0x000000 /* PC architecture */
#define MACHINE_AT 0x000001 /* PC/AT architecture */
#define MACHINE_PS2 0x000002 /* PS/2 architecture */
#define MACHINE_ISA 0x000010 /* sys has ISA bus */
#define MACHINE_CBUS 0x000020 /* sys has C-BUS bus */
#define MACHINE_EISA 0x000040 /* sys has EISA bus */
#define MACHINE_VLB 0x000080 /* sys has VL bus */
#define MACHINE_MCA 0x000100 /* sys has MCA bus */
#define MACHINE_PCI 0x000200 /* sys has PCI bus */
#define MACHINE_AGP 0x000400 /* sys has AGP bus */
#define MACHINE_HDC 0x001000 /* sys has int HDC */
#define MACHINE_VIDEO 0x002000 /* sys has int video */
#define MACHINE_VIDEO_FIXED 0x004000 /* sys has ONLY int video */
#define MACHINE_MOUSE 0x008000 /* sys has int mouse */
#define MACHINE_SOUND 0x010000 /* sys has int sound */
#define MACHINE_NONMI 0x020000 /* sys does not have NMI's */
#define MACHINE_FDC 0x040000 /* sys has int FDC */
#endif
// #define MACHINE_PC 0x00000000 /* PC architecture */
/* Feature flags for features. */
#define MACHINE_NONMI 0x00000001 /* sys does not have NMI's */
/* Feature flags for BUS'es. */
#define MACHINE_BUS_ISA 0x00000004 /* sys has ISA bus */
#define MACHINE_BUS_ISA16 0x00000008 /* sys has ISA16 bus - PC/AT architecture */
#define MACHINE_BUS_CBUS 0x00000010 /* sys has C-BUS bus */
#define MACHINE_BUS_PS2 0x00000020 /* system has PS/2 keyboard and mouse ports */
#define MACHINE_BUS_EISA 0x00000040 /* sys has EISA bus */
#define MACHINE_BUS_VLB 0x00000080 /* sys has VL bus */
#define MACHINE_BUS_MCA 0x00000100 /* sys has MCA bus */
#define MACHINE_BUS_PCI 0x00000200 /* sys has PCI bus */
#define MACHINE_BUS_PCMCIA 0x00000400 /* sys has PCMCIA bus */
#define MACHINE_BUS_AGP 0x00000800 /* sys has AGP bus */
/* Combined flags. */
#define MACHINE_PC 0x00000004 /* sys is PC/XT-compatible (ISA) */
#define MACHINE_AT 0x0000000C /* sys is AT-compatible (ISA + ISA16) */
#define MACHINE_PC98 0x00000010 /* sys is NEC PC-98x1 series */
#define MACHINE_EISA 0x0000004C /* sys is AT-compatible with EISA */
#define MACHINE_VLB 0x0000008C /* sys is AT-compatible with VLB */
#define MACHINE_VLB98 0x00000090 /* sys is NEC PC-98x1 series with VLB (did that even exist?) */
#define MACHINE_VLBE 0x000000CC /* sys is AT-compatible with EISA and VLB */
#define MACHINE_MCA 0x00000100 /* sys is MCA */
#define MACHINE_PCI 0x0000020C /* sys is AT-compatible with PCI */
#define MACHINE_PCI98 0x00000210 /* sys is NEC PC-98x1 series with PCI */
#define MACHINE_PCIE 0x0000024C /* sys is AT-compatible with PCI, and EISA */
#define MACHINE_PCIV 0x0000028C /* sys is AT-compatible with PCI and VLB */
#define MACHINE_PCIVE 0x000002CC /* sys is AT-compatible with PCI, VLB, and EISA */
#define MACHINE_PCMCIA 0x00000400 /* sys is AT-compatible laptop with PCMCIA */
#define MACHINE_AGP 0x00000A0C /* sys is AT-compatible with AGP */
#define MACHINE_AGP98 0x00000A10 /* sys is NEC PC-98x1 series with AGP (did that even exist?) */
#define MACHINE_IS_AT 0x00000FCC /* sys is AT-compatible (ISA + ISA16) */
/* Feature flags for miscellaneous internal devices. */
#define MACHINE_VIDEO 0x00001000 /* sys has int video */
#define MACHINE_VIDEO_ONLY 0x00002000 /* sys has fixed video */
#define MACHINE_MOUSE 0x00004000 /* sys has int mouse */
#define MACHINE_SOUND 0x00008000 /* sys has int sound */
#define MACHINE_FDC 0x00010000 /* sys has int FDC */
#define MACHINE_NIC 0x00020000 /* sys has int NIC */
/* Combined flags. */
#define MACHINE_VIDEO_FIXED 0x00003000 /* sys has fixed int video */
/* Feature flags for internal storage controllers. */
#define MACHINE_HDC 0x0FFC0000 /* sys has int HDC */
#define MACHINE_MFM 0x00100000 /* sys has int MFM/RLL */
#define MACHINE_XTA 0x00200000 /* sys has int XTA */
#define MACHINE_ESDI 0x00400000 /* sys has int ESDI */
#define MACHINE_IDE_PRI 0x00800000 /* sys has int pri IDE/ATAPI */
#define MACHINE_IDE_SEC 0x01000000 /* sys has int sec IDE/ATAPI */
#define MACHINE_IDE_TER 0x02000000 /* sys has int ter IDE/ATAPI */
#define MACHINE_IDE_QUA 0x04000000 /* sys has int qua IDE/ATAPI */
#define MACHINE_SCSI_PRI 0x08000000 /* sys has int pri SCSI */
#define MACHINE_SCSI_SEC 0x10000000 /* sys has int sec SCSI */
#define MACHINE_USB 0x20000000 /* sys has int USB */
/* Combined flags. */
#define MACHINE_IDE 0x00800000 /* sys has int single IDE/ATAPI - mark as pri IDE/ATAPI */
#define MACHINE_IDE_DUAL 0x01800000 /* sys has int dual IDE/ATAPI - mark as both pri and sec IDE/ATAPI */
#define MACHINE_IDE_QUAD 0x07800000 /* sys has int quad IDE/ATAPI - mark as dual + both ter and and qua IDE/ATAPI */
#define MACHINE_SCSI 0x08000000 /* sys has int single SCSI - mark as pri SCSI */
#define MACHINE_SCSI_DUAL 0x18000000 /* sys has int dual SCSI - mark as both pri and sec SCSI */
#define IS_ARCH(m, a) (machines[(m)].flags & (a)) ? 1 : 0;
@@ -274,17 +296,19 @@ extern int machine_at_opti495_mr_init(const machine_t *);
extern int machine_at_403tg_init(const machine_t *);
extern int machine_at_pc330_6571_init(const machine_t *);
extern int machine_at_sis401_init(const machine_t *);
extern int machine_at_vli486sv2g_init(const machine_t *);
extern int machine_at_ami471_init(const machine_t *);
extern int machine_at_dtk486_init(const machine_t *);
extern int machine_at_px471_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_WIN471)
extern int machine_at_win471_init(const machine_t *);
#endif
extern int machine_at_vi15g_init(const machine_t *);
extern int machine_at_r418_init(const machine_t *);
extern int machine_at_ls486e_init(const machine_t *);
extern int machine_at_4dps_init(const machine_t *);
extern int machine_at_4sa2_init(const machine_t *);
extern int machine_at_alfredo_init(const machine_t *);
extern int machine_at_486sp3g_init(const machine_t *);
extern int machine_at_486ap4_init(const machine_t *);
@@ -346,6 +370,7 @@ extern int machine_at_acerv30_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
extern const device_t *at_pb520r_get_device(void);
extern const device_t *at_thor_get_device(void);
#endif
/* m_at_socket7_s7.c */

53
src/include/86box/mem.h
View File

@@ -183,14 +183,6 @@ typedef struct _page_ {
#endif
typedef struct
{
uint32_t size,
host_base,
ram_base;
} smram_t;
extern uint8_t *ram, *ram2;
extern uint32_t rammask;
@@ -207,15 +199,13 @@ extern uintptr_t * writelookup2;
extern int writelnext;
extern uint32_t ram_mapped_addr[64];
extern mem_mapping_t base_mapping,
ram_low_mapping,
extern mem_mapping_t ram_low_mapping,
#if 1
ram_mid_mapping,
#endif
ram_remapped_mapping,
ram_high_mapping,
ram_2gb_mapping,
ram_smram_mapping[2],
bios_mapping,
bios_high_mapping;
@@ -225,7 +215,6 @@ extern page_t *pages,
**page_lookup;
extern uint32_t get_phys_virt, get_phys_phys;
extern smram_t smram[2];
extern int shadowbios,
shadowbios_write;
@@ -242,6 +231,9 @@ extern int mem_a20_state,
mem_a20_key;
extern uint8_t read_mem_b(uint32_t addr);
extern void write_mem_b(uint32_t addr, uint8_t val);
#ifndef USE_NEW_DYNAREC
#define readmemb(a) ((readlookup2[(a)>>12]==-1)?readmembl(a):*(uint8_t *)(readlookup2[(a) >> 12] + (a)))
#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl(s,a):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
@@ -258,14 +250,14 @@ extern void writememll(uint32_t seg, uint32_t addr, uint32_t val);
extern uint64_t readmemql(uint32_t seg, uint32_t addr);
extern void writememql(uint32_t seg, uint32_t addr, uint64_t val);
#else
uint8_t readmembl(uint32_t addr);
void writemembl(uint32_t addr, uint8_t val);
uint16_t readmemwl(uint32_t addr);
void writememwl(uint32_t addr, uint16_t val);
uint32_t readmemll(uint32_t addr);
void writememll(uint32_t addr, uint32_t val);
uint64_t readmemql(uint32_t addr);
void writememql(uint32_t addr, uint64_t val);
extern uint8_t readmembl(uint32_t addr);
extern void writemembl(uint32_t addr, uint8_t val);
extern uint16_t readmemwl(uint32_t addr);
extern void writememwl(uint32_t addr, uint16_t val);
extern uint32_t readmemll(uint32_t addr);
extern void writememll(uint32_t addr, uint32_t val);
extern uint64_t readmemql(uint32_t addr);
extern void writememql(uint32_t addr, uint64_t val);
#endif
extern uint8_t *getpccache(uint32_t a);
@@ -326,16 +318,12 @@ extern void mem_write_ram(uint32_t addr, uint8_t val, void *priv);
extern void mem_write_ramw(uint32_t addr, uint16_t val, void *priv);
extern void mem_write_raml(uint32_t addr, uint32_t val, void *priv);
extern uint8_t mem_read_smram(uint32_t addr, void *priv);
extern uint16_t mem_read_smramw(uint32_t addr, void *priv);
extern uint32_t mem_read_smraml(uint32_t addr, void *priv);
extern void mem_write_smram(uint32_t addr, uint8_t val, void *priv);
extern void mem_write_smramw(uint32_t addr, uint16_t val, void *priv);
extern void mem_write_smraml(uint32_t addr, uint32_t val, void *priv);
extern uint8_t mem_read_bios(uint32_t addr, void *priv);
extern uint16_t mem_read_biosw(uint32_t addr, void *priv);
extern uint32_t mem_read_biosl(uint32_t addr, void *priv);
extern uint8_t mem_read_ram_2gb(uint32_t addr, void *priv);
extern uint16_t mem_read_ram_2gbw(uint32_t addr, void *priv);
extern uint32_t mem_read_ram_2gbl(uint32_t addr, void *priv);
extern void mem_write_ram_2gb(uint32_t addr, uint8_t val, void *priv);
extern void mem_write_ram_2gbw(uint32_t addr, uint16_t val, void *priv);
extern void mem_write_ram_2gbl(uint32_t addr, uint32_t val, void *priv);
extern void mem_write_null(uint32_t addr, uint8_t val, void *p);
extern void mem_write_nullw(uint32_t addr, uint16_t val, void *p);
@@ -362,11 +350,8 @@ extern void mmu_invalidate(uint32_t addr);
extern void mem_a20_init(void);
extern void mem_a20_recalc(void);
extern void mem_add_upper_bios(void);
extern void mem_add_bios(void);
extern void mem_init(void);
extern void mem_close(void);
extern void mem_reset(void);
extern void mem_remap_top(int kb);

2
src/include/86box/mo.h
View File

@@ -85,7 +85,7 @@ static const mo_drive_type_t mo_drive_types[KNOWN_MO_DRIVE_TYPES] = {
enum {
MO_BUS_DISABLED = 0,
MO_BUS_ATAPI = 4,
MO_BUS_ATAPI = 5,
MO_BUS_SCSI,
MO_BUS_USB
};

5
src/include/86box/pci.h
View File

@@ -112,11 +112,6 @@ extern void trc_init(void);
extern uint8_t trc_read(uint16_t port, void *priv);
extern void trc_write(uint16_t port, uint8_t val, void *priv);
extern void pci_elcr_set_enabled(int enabled);
extern void pci_elcr_io_disable(void);
extern void elcr_write(uint16_t port, uint8_t val, void *priv);
extern uint8_t elcr_read(uint16_t port, void *priv);
#ifdef EMU_DEVICE_H
extern const device_t dec21150_device;

44
src/include/86box/pic.h
View File

@@ -1,29 +1,57 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the implementation of the Intel PIC chip emulation,
* partially ported from reenigne's XTCE.
*
* Authors: Andrew Jenner, <https://www.reenigne.org>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2015-2020 Andrew Jenner.
* Copyright 2016-2020 Miran Grca.
*/
#ifndef EMU_PIC_H
# define EMU_PIC_H
typedef struct PIC {
uint8_t icw1, icw3, icw4, mask, ins, pend, mask2, vector, ocw2, ocw3;
int icw, read;
} PIC;
typedef struct pic {
uint8_t icw1, icw2, icw3, icw4,
imr, isr, irr, ocw2,
ocw3, int_pending, is_master, elcr,
state, ack_bytes, priority, special_mask_mode,
auto_eoi_rotate, interrupt, lines, data_bus;
struct pic *slaves[8];
} pic_t;
extern PIC pic, pic2;
extern int pic_intpending, pic_pending;
extern pic_t pic, pic2;
extern int pic_elcr_get_enabled(void);
extern void pic_elcr_set_enabled(int enabled);
extern void pic_elcr_io_handler(int set);
extern void pic_elcr_write(uint16_t port, uint8_t val, void *priv);
extern uint8_t pic_elcr_read(uint16_t port, void *priv);
extern void pic_set_shadow(int sh);
extern void pic_init(void);
extern void pic_init_pcjr(void);
extern void pic2_init(void);
extern void pic_reset(void);
extern int picint_is_level(int irq);
extern void picint_common(uint16_t num, int level, int set);
extern void picint(uint16_t num);
extern void picintlevel(uint16_t num);
extern void picintc(uint16_t num);
extern int picinterrupt(void);
extern void picclear(int num);
extern void dumppic(void);
extern uint8_t pic_irq_ack(void);
#endif /*EMU_PIC_H*/

4
src/include/86box/rom.h
View File

@@ -54,6 +54,10 @@ extern int rom_load_linear(wchar_t *fn, uint32_t addr, int sz,
extern int rom_load_interleaved(wchar_t *fnl, wchar_t *fnh, uint32_t addr,
int sz, int off, uint8_t *ptr);
extern uint8_t bios_read(uint32_t addr, void *priv);
extern uint16_t bios_readw(uint32_t addr, void *priv);
extern uint32_t bios_readl(uint32_t addr, void *priv);
extern int bios_load(wchar_t *fn1, wchar_t *fn2, uint32_t addr, int sz,
int off, int flags);
extern int bios_load_linear_combined(wchar_t *fn1, wchar_t *fn2,

57
src/include/86box/smram.h Normal file
View File

@@ -0,0 +1,57 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Definitions for the SMRAM interface.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2020 Miran Grca.
*/
#ifndef EMU_SMRAM_H
# define EMU_SMRAM_H
typedef struct _smram_
{
struct _smram_ *prev, *next;
mem_mapping_t mapping;
uint32_t host_base, ram_base,
size,
old_host_base, old_size;
} smram_t;
/* Make a backup copy of host_base and size of all the SMRAM structs, needed so that if
the SMRAM mappings change while in SMM, they will be recalculated on return. */
extern void smram_backup_all(void);
/* Recalculate any mappings, including the backup if returning from SMM. */
extern void smram_recalc_all(int ret);
/* Delete a SMRAM mapping. */
extern void smram_del(smram_t *smr);
/* Add a SMRAM mapping. */
extern smram_t *smram_add(void);
/* Set memory state in the specified model (normal or SMM) according to the specified flags. */
extern void smram_map(int smm, uint32_t addr, uint32_t size, int is_smram);
/* Disable a specific SMRAM mapping. */
extern void smram_disable(smram_t *smr);
/* Disable all SMRAM mappings. */
extern void smram_disable_all(void);
/* Enable SMRAM mappings according to flags for both normal and SMM modes. */
extern void smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size,
int flags_normal, int flags_smm);
/* Checks if a SMRAM mapping is enabled or not. */
extern int smram_enabled(smram_t *smr);
/* Changes the SMRAM state. */
extern void smram_state_change(smram_t *smr, int smm, int flags);
#endif /*EMU_SMRAM_H*/

38
src/include/86box/timer.h
View File

@@ -80,17 +80,9 @@ extern void timer_add(pc_timer_t *timer, void (*callback)(void *p), void *p, int
extern uint64_t TIMER_USEC;
/*True if timer a expires before timer b*/
#if 0
#define TIMER_LESS_THAN(a, b) ((int32_t)((a)->ts_integer - (b)->ts_integer) <= 0)
#else
#define TIMER_LESS_THAN(a, b) ((int64_t)((a)->ts.ts64 - (b)->ts.ts64) <= 0)
#endif
/*True if timer a expires before 32 bit integer timestamp b*/
#if 0
#define TIMER_LESS_THAN_VAL(a, b) ((int32_t)((a)->ts_integer - (b)) <= 0)
#else
#define TIMER_LESS_THAN_VAL(a, b) ((int32_t)((a)->ts.ts32.integer - (b)) <= 0)
#endif
/*True if 32 bit integer timestamp a expires before 32 bit integer timestamp b*/
#define TIMER_VAL_LESS_THAN_VAL(a, b) ((int32_t)((a) - (b)) <= 0)
@@ -100,17 +92,7 @@ extern uint64_t TIMER_USEC;
static __inline void
timer_advance_u64(pc_timer_t *timer, uint64_t delay)
{
#if 0
uint32_t int_delay = delay >> 32;
uint32_t frac_delay = delay & 0xffffffff;
if ((frac_delay + timer->ts_frac) < frac_delay)
timer->ts_integer++;
timer->ts_frac += frac_delay;
timer->ts_integer += int_delay;
#else
timer->ts.ts64 += delay;
#endif
timer_enable(timer);
}
@@ -121,17 +103,9 @@ timer_advance_u64(pc_timer_t *timer, uint64_t delay)
static __inline void
timer_set_delay_u64(pc_timer_t *timer, uint64_t delay)
{
#if 0
uint32_t int_delay = delay >> 32;
uint32_t frac_delay = delay & 0xffffffff;
timer->ts_frac = frac_delay;
timer->ts_integer = int_delay + (uint32_t)tsc;
#else
timer->ts.ts64 = 0ULL;
timer->ts.ts32.integer = tsc;
timer->ts.ts64 += delay;
#endif
timer_enable(timer);
}
@@ -149,11 +123,7 @@ timer_is_enabled(pc_timer_t *timer)
static __inline uint32_t
timer_get_ts_int(pc_timer_t *timer)
{
#if 0
return timer->ts_integer;
#else
return timer->ts.ts32.integer;
#endif
}
@@ -165,11 +135,7 @@ timer_get_remaining_us(pc_timer_t *timer)
int64_t remaining;
if (timer->flags & TIMER_ENABLED) {
#if 0
remaining = (((uint64_t)timer->ts_integer << 32) | timer->ts_frac) - (tsc << 32);
#else
remaining = (int64_t) (timer->ts.ts64 - (uint64_t)(tsc << 32));
#endif
if (remaining < 0)
return 0;
@@ -188,11 +154,7 @@ timer_get_remaining_u64(pc_timer_t *timer)
int64_t remaining;
if (timer->flags & TIMER_ENABLED) {
#if 0
remaining = (((uint64_t)timer->ts_integer << 32) | timer->ts_frac) - (tsc << 32);
#else
remaining = (int64_t) (timer->ts.ts64 - (uint64_t)(tsc << 32));
#endif
if (remaining < 0)
return 0;

9
src/include/86box/version.h
View File

@@ -17,10 +17,11 @@
#define EMU_NAME "86Box"
#define EMU_NAME_W L"86Box"
#define EMU_VERSION "2.10"
#define EMU_VERSION_W L"2.10"
#define EMU_VERSION_MAJ 2
#define EMU_VERSION_MIN 10
#define EMU_VERSION "3.0"
#define EMU_VERSION_W L"3.0"
#define EMU_VERSION_EX "3.00"
#define EMU_VERSION_MAJ 3
#define EMU_VERSION_MIN 0
#define COPYRIGHT_YEAR "2020"

1
src/include/86box/video.h
View File

@@ -314,6 +314,7 @@ extern const device_t s3_phoenix_trio64_onboard_pci_device;
extern const device_t s3_phoenix_trio64_pci_device;
extern const device_t s3_phoenix_trio64vplus_vlb_device;
extern const device_t s3_phoenix_trio64vplus_pci_device;
extern const device_t s3_phoenix_trio64vplus_onboard_pci_device;
extern const device_t s3_phoenix_vision864_pci_device;
extern const device_t s3_phoenix_vision864_vlb_device;
extern const device_t s3_diamond_stealth64_pci_device;

2
src/include/86box/zip.h
View File

@@ -32,7 +32,7 @@
enum {
ZIP_BUS_DISABLED = 0,
ZIP_BUS_ATAPI = 4,
ZIP_BUS_ATAPI = 5,
ZIP_BUS_SCSI,
ZIP_BUS_USB
};

2
src/machine/m_at_286_386sx.c
View File

@@ -276,6 +276,8 @@ machine_at_gdc212m_init(const machine_t *model)
machine_at_scat_init(model, 0);
device_add(&ide_isa_device);
return ret;
}

75
src/machine/m_at_386dx_486.c
View File

@@ -83,6 +83,26 @@ machine_at_asus386_init(const machine_t *model)
}
int
machine_at_sis401_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/sis401/SIS401-2.AMI",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&sis_85c401_device);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ecs386_init(const machine_t *model)
{
@@ -134,7 +154,7 @@ machine_at_rycleopardlx_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
machine_at_common_ide_init(model);
device_add(&opti283_device);
device_add(&keyboard_at_ami_device);
@@ -143,6 +163,7 @@ machine_at_rycleopardlx_init(const machine_t *model)
return ret;
}
int
machine_at_486vchd_init(const machine_t *model)
{
@@ -480,7 +501,6 @@ machine_at_px471_init(const machine_t *model)
}
#if defined(DEV_BRANCH) && defined(USE_WIN471)
int
machine_at_win471_init(const machine_t *model)
{
@@ -498,7 +518,25 @@ machine_at_win471_init(const machine_t *model)
return ret;
}
#endif
int
machine_at_vi15g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/vi15g/vi15gr23.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&ide_vlb_device);
device_add(&keyboard_at_ami_device);
return ret;
}
static void
@@ -593,7 +631,35 @@ machine_at_4dps_init(const machine_t *model)
device_add(&w83787f_device);
device_add(&keyboard_ps2_pci_device);
// device_add(&sst_flash_29ee010_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_4sa2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/4sa2/4saw0911.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_device);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&pc87332_device);
device_add(&keyboard_ps2_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
@@ -695,6 +761,7 @@ machine_at_486ap4_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_486vipio2_init(const machine_t *model)

1
src/machine/m_at_compaq.c
View File

@@ -658,6 +658,7 @@ compaq_plasma_close(void *p)
compaq_plasma_t *self = (compaq_plasma_t *)p;
free(self->vram);
free(self);
}

12
src/machine/m_at_slot1.c
View File

@@ -129,7 +129,7 @@ machine_at_lx6_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SPECIAL, 1, 2, 3, 4);
device_add(&i440lx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
@@ -137,6 +137,7 @@ machine_at_lx6_init(const machine_t *model)
return ret;
}
int
machine_at_spitfire_init(const machine_t *model)
{
@@ -183,6 +184,7 @@ machine_at_spitfire_init(const machine_t *model)
return ret;
}
int
machine_at_p6i440e2_init(const machine_t *model)
{
@@ -204,7 +206,7 @@ machine_at_p6i440e2_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SPECIAL, 1, 2, 3, 4);
device_add(&i440ex_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x03, 256);
@@ -262,7 +264,7 @@ machine_at_p2bls_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SPECIAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
@@ -320,7 +322,7 @@ machine_at_p3bf_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SPECIAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
@@ -412,7 +414,7 @@ machine_at_ax6bc_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SPECIAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);

7
src/machine/m_at_socket370.c
View File

@@ -116,7 +116,8 @@ machine_at_cubx_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SPECIAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
// device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
@@ -203,7 +204,7 @@ machine_at_ambx133_init(const machine_t *model)
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
@@ -268,7 +269,7 @@ machine_at_63a_init(const machine_t *model)
device_add(&i440zx_device);
device_add(&piix4e_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);

32
src/machine/m_at_socket7_s7.c
View File

@@ -114,9 +114,10 @@ machine_at_thor_common_init(const machine_t *model, int mr)
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
@@ -626,7 +627,7 @@ machine_at_p55va_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_device);
@@ -811,7 +812,7 @@ machine_at_nupro592_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4); /* PIIX4 */
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
@@ -859,8 +860,13 @@ machine_at_tx97_init(const machine_t *model)
{
int ret;
#if 0
ret = bios_load_linear(L"roms/machines/tx97/0112.001",
0x000e0000, 131072, 0);
#else
ret = bios_load_linear(L"roms/machines/tx97/0112.001",
0x000c0000, 262144, 0);
#endif
if (bios_only || !ret)
return ret;
@@ -869,6 +875,7 @@ machine_at_tx97_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
#if 0
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
@@ -876,11 +883,22 @@ machine_at_tx97_init(const machine_t *model)
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
#else
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
#endif
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877tf_acorp_device);
device_add(&intel_flash_bxt_device);
// device_add(&piix4_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
// device_add(&w83877tf_acorp_device);
device_add(&pc87307_15c_device);
// device_add(&intel_flash_bxt_device);
device_add(&sst_flash_29ee020_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
hwm_values_t machine_hwm = {

9
src/machine/machine.c
View File

@@ -76,15 +76,14 @@ machine_init_ex(int m)
is_vpc = 0;
/* Set up the architecture flags. */
AT = IS_ARCH(machine, MACHINE_AT);
PCI = IS_ARCH(machine, MACHINE_PCI);
AT = IS_ARCH(machine, (MACHINE_BUS_ISA16 | MACHINE_BUS_MCA | MACHINE_BUS_PCMCIA));
PCI = IS_ARCH(machine, MACHINE_BUS_PCI);
/* Resize the memory. */
/* Reset the memory state. */
mem_reset();
smbase = is_am486 ? 0x00060000 : 0x00030000;
lpt_init();
smbase = 0x30000;
}
/* All good, boot the machine! */

413
src/machine/machine_table.c
View File

@@ -83,317 +83,326 @@ const machine_type_t machine_types[] = {
{ "Slot 2", MACHINE_TYPE_SLOT2 },
{ "Socket 370", MACHINE_TYPE_SOCKET370 },
{ "Miscellaneous", MACHINE_TYPE_MISC },
{ "Miscellaneous", MACHINE_TYPE_MISC }
};
const machine_t machines[] = {
/* 8088 Machines */
{ "[8088] IBM PC (1981)", "ibmpc", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 16, 64, 16, 0, machine_pc_init, NULL },
{ "[8088] IBM PC (1982)", "ibmpc82", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 256, 256, 0, machine_pc82_init, NULL },
{ "[8088] IBM PCjr", "ibmpcjr", MACHINE_TYPE_8088, {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT (1982)", "ibmxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 256, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM XT (1986)", "ibmxt86", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 64, 0, machine_xt86_init, NULL },
{ "[8088] American XT Computer", "americxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_americxt_init, NULL },
{ "[8088] AMI XT clone", "amixt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_amixt_init, NULL },
{ "[8088] Tandy 1000", "tandy", MACHINE_TYPE_8088, {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_tandy_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", "tandy1000hx", MACHINE_TYPE_8088, {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 256, 640, 128, 0, machine_tandy1000hx_init, tandy1k_hx_get_device },
{ "[8088] Compaq Portable", "portable", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 128, 640, 128, 0, machine_xt_compaq_portable_init, NULL },
{ "[8088] Generic XT clone", "genxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_genxt_init, NULL },
{ "[8088] DTK XT clone", "dtk", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] Juko XT clone", "jukopc", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] OpenXT", "open_xt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_open_xt_init, NULL },
{ "[8088] Phoenix XT clone", "pxxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_pxxt_init, NULL },
{ "[8088] Schneider EuroPC", "europc", MACHINE_TYPE_8088, {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_HDC | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Toshiba T1000", "t1000", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
{ "[8088] IBM PC (1981)", "ibmpc", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 16, 64, 16, 0, machine_pc_init, NULL },
{ "[8088] IBM PC (1982)", "ibmpc82", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 256, 256, 256, 0, machine_pc82_init, NULL },
{ "[8088] IBM PCjr", "ibmpcjr", MACHINE_TYPE_8088, {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT (1982)", "ibmxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 256, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM XT (1986)", "ibmxt86", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 256, 640, 64, 0, machine_xt86_init, NULL },
{ "[8088] American XT Computer", "americxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_xt_americxt_init, NULL },
{ "[8088] AMI XT clone", "amixt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_xt_amixt_init, NULL },
{ "[8088] Tandy 1000", "tandy", MACHINE_TYPE_8088, {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_tandy_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", "tandy1000hx", MACHINE_TYPE_8088, {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED, 256, 640, 128, 0, machine_tandy1000hx_init, tandy1k_hx_get_device },
{ "[8088] Compaq Portable", "portable", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_portable_init, NULL },
{ "[8088] Generic XT clone", "genxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_genxt_init, NULL },
{ "[8088] DTK XT clone", "dtk", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] Juko XT clone", "jukopc", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] OpenXT", "open_xt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_xt_open_xt_init, NULL },
{ "[8088] Phoenix XT clone", "pxxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 640, 64, 0, machine_xt_pxxt_init, NULL },
{ "[8088] Schneider EuroPC", "europc", MACHINE_TYPE_8088, {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_XTA | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Toshiba T1000", "t1000", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8088] VTech Laser Turbo XT", "ltxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 256, 0, machine_xt_laserxt_init, NULL },
{ "[8088] VTech Laser Turbo XT", "ltxt", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 256, 640, 256, 0, machine_xt_laserxt_init, NULL },
#endif
{ "[8088] Xi8088", "xi8088", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, xi8088_get_device },
{ "[8088] Zenith Data SupersPort", "zdsupers", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 128, 640, 128, 0, machine_xt_zenith_init, NULL },
{ "[8088] Xi8088", "xi8088", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, xi8088_get_device },
{ "[8088] Zenith Data SupersPort", "zdsupers", MACHINE_TYPE_8088, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 128, 640, 128, 0, machine_xt_zenith_init, NULL },
/* 8086 Machines */
{ "[8086] Amstrad PC1512", "pc1512", MACHINE_TYPE_8086, {{"Intel", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 512, 640, 128, 63, machine_pc1512_init, pc1512_get_device },
{ "[8086] Amstrad PC1640", "pc1640", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc1640_init, pc1640_get_device },
{ "[8086] Amstrad PC2086", "pc2086", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc2086_init, pc2086_get_device },
{ "[8086] Amstrad PC3086", "pc3086", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc3086_init, pc3086_get_device },
{ "[8086] Amstrad PC20(0)", "pc200", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_pc200_init, pc200_get_device },
{ "[8086] Amstrad PPC512/640", "ppc512", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M24", "olivetti_m24", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, m24_get_device },
{ "[8086] Schetmash Iskra-3104", "iskra3104", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 128, 640, 128, 0, machine_xt_iskra3104_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, tandy1k_sl_get_device },
{ "[8086] Toshiba T1200", "t1200", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
{ "[8086] Amstrad PC1512", "pc1512", MACHINE_TYPE_8086, {{"Intel", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 512, 640, 128, 63, machine_pc1512_init, pc1512_get_device },
{ "[8086] Amstrad PC1640", "pc1640", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc1640_init, pc1640_get_device },
{ "[8086] Amstrad PC2086", "pc2086", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc2086_init, pc2086_get_device },
{ "[8086] Amstrad PC3086", "pc3086", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc3086_init, pc3086_get_device },
{ "[8086] Amstrad PC20(0)", "pc200", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_pc200_init, pc200_get_device },
{ "[8086] Amstrad PPC512/640", "ppc512", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M24", "olivetti_m24", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, m24_get_device },
{ "[8086] Schetmash Iskra-3104", "iskra3104", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 128, 640, 128, 0, machine_xt_iskra3104_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, tandy1k_sl_get_device },
{ "[8086] Toshiba T1200", "t1200", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8086] VTech Laser XT3", "lxt3", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 256, 0, machine_xt_lxt3_init, NULL },
{ "[8086] VTech Laser XT3", "lxt3", MACHINE_TYPE_8086, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 256, 640, 256, 0, machine_xt_lxt3_init, NULL },
#endif
/* 286 XT machines */
#if defined(DEV_BRANCH) && defined(USE_HEDAKA)
{ "[Citygate D30 XT] Hedaka HED-919", "hed919", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 1024, 64, 0, machine_xt_hed919_init, NULL },
{ "[Citygate D30 XT] Hedaka HED-919", "hed919", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PC, 64, 1024, 64, 0, machine_xt_hed919_init, NULL },
#endif
/* 286 AT machines */
{ "[ISA] IBM AT", "ibmat", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL },
{ "[ISA] AMI IBM AT", "ibmatami", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatami_init, NULL },
{ "[ISA] Quadtel IBM AT", "ibmatquadtel", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatquadtel_init, NULL },
{ "[ISA] Phoenix IBM AT", "ibmatpx", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatpx_init, NULL },
{ "[ISA] IBM PS/1 model 2011", "ibmps1es", MACHINE_TYPE_286, {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC | MACHINE_PS2, 512,16384, 512, 63, machine_ps1_m2011_init, NULL },
{ "[ISA] IBM PS/2 model 30-286", "ibmps2_m30_286", MACHINE_TYPE_286, {{"Intel", cpus_ps2_m30_286}, {"IBM",cpus_IBM486SLC},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC | MACHINE_PS2, 1, 16, 1, 127, machine_ps2_m30_286_init, NULL },
{ "[ISA] IBM XT Model 286", "ibmxt286", MACHINE_TYPE_286, {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 127, machine_at_ibmxt286_init, NULL },
{ "[ISA] Commodore PC 30 III", "cmdpc30", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{ "[ISA] Compaq Portable II", "portableii", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL },
{ "[ISA] Compaq Portable III", "portableiii", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_portableiii_init, at_cpqiii_get_device },
{ "[NEAT] AMI 286 clone", "ami286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[NEAT] Phoenix 286 clone", "px286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_px286_init, NULL },
{ "[SCAT] Award 286 clone", "award286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_award286_init, NULL },
{ "[SCAT] GW-286CT GEAR", "gw286ct", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_gw286ct_init, NULL },
{ "[SCAT] Goldstar GDC-212M", "gdc212m", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2, 512, 4096, 512, 127, machine_at_gdc212m_init, NULL },
{ "[SCAT] Hyundai Super-286TR", "super286tr", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_super286tr_init, NULL },
{ "[SCAT] Samsung SPC-4200P", "spc4200p", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 512, 2048, 128, 127, machine_at_spc4200p_init, NULL },
{ "[SCAT] Samsung SPC-4216P", "spc4216p", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 1, 5, 1, 127, machine_at_spc4216p_init, NULL },
{ "[SCAT] Samsung Deskmaster 286", "deskmaster286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_deskmaster286_init, NULL },
{ "[GC103] Quadtel 286 clone", "quadt286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_quadt286_init, NULL },
{ "[GC103] Trigem 286M", "tg286m", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_tg286m_init, NULL },
{ "[ISA] MR 286 clone", "mr286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_mr286_init, NULL },
{ "[ISA] IBM AT", "ibmat", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL },
{ "[ISA] AMI IBM AT", "ibmatami", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatami_init, NULL },
{ "[ISA] Quadtel IBM AT", "ibmatquadtel", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatquadtel_init, NULL },
{ "[ISA] Phoenix IBM AT", "ibmatpx", MACHINE_TYPE_286, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatpx_init, NULL },
{ "[ISA] IBM PS/1 model 2011", "ibmps1es", MACHINE_TYPE_286, {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_XTA | MACHINE_VIDEO_FIXED, 512,16384, 512, 63, machine_ps1_m2011_init, NULL },
{ "[ISA] IBM PS/2 model 30-286", "ibmps2_m30_286", MACHINE_TYPE_286, {{"Intel", cpus_ps2_m30_286}, {"IBM",cpus_IBM486SLC},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_XTA | MACHINE_VIDEO_FIXED, 1, 16, 1, 127, machine_ps2_m30_286_init, NULL },
{ "[ISA] IBM XT Model 286", "ibmxt286", MACHINE_TYPE_286, {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 127, machine_at_ibmxt286_init, NULL },
{ "[ISA] Commodore PC 30 III", "cmdpc30", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{ "[ISA] Compaq Portable II", "portableii", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL },
{ "[ISA] Compaq Portable III", "portableiii", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_portableiii_init, at_cpqiii_get_device },
{ "[NEAT] AMI 286 clone", "ami286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[NEAT] Phoenix 286 clone", "px286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_px286_init, NULL },
{ "[SCAT] Award 286 clone", "award286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_award286_init, NULL },
{ "[SCAT] GW-286CT GEAR", "gw286ct", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_gw286ct_init, NULL },
{ "[SCAT] Goldstar GDC-212M", "gdc212m", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE | MACHINE_BUS_PS2, 512, 4096, 512, 127, machine_at_gdc212m_init, NULL },
{ "[SCAT] Hyundai Super-286TR", "super286tr", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_super286tr_init, NULL },
{ "[SCAT] Samsung SPC-4200P", "spc4200p", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2, 512, 2048, 128, 127, machine_at_spc4200p_init, NULL },
{ "[SCAT] Samsung SPC-4216P", "spc4216p", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2, 1, 5, 1, 127, machine_at_spc4216p_init, NULL },
{ "[SCAT] Samsung Deskmaster 286", "deskmaster286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_deskmaster286_init, NULL },
{ "[GC103] Quadtel 286 clone", "quadt286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_quadt286_init, NULL },
{ "[GC103] Trigem 286M", "tg286m", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE, 512, 8192, 128, 127, machine_at_tg286m_init, NULL },
{ "[ISA] MR 286 clone", "mr286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE, 512,16384, 128, 127, machine_at_mr286_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_SIEMENS)
{ "[ISA] Siemens PCD-2L", "siemens", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_siemens_init, NULL },
{ "[ISA] Siemens PCD-2L", "siemens", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 63, machine_at_siemens_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
{ "[ISA] OpenAT", "open_at", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_open_at_init, NULL },
{ "[ISA] OpenAT", "open_at", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT, 256,15872, 128, 63, machine_at_open_at_init, NULL },
#endif
{ "[ISA] Toshiba T3100e", "t3100e", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC, 1024, 5120, 256, 63, machine_at_t3100e_init, NULL },
{ "[ISA] Toshiba T3100e", "t3100e", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE | MACHINE_VIDEO_FIXED, 1024, 5120, 256, 63, machine_at_t3100e_init, NULL },
/* 286 machines that utilize the MCA bus */
{ "[MCA] IBM PS/2 model 50", "ibmps2_m50", MACHINE_TYPE_286, {{"Intel", cpus_ps2_m30_286}, {"IBM",cpus_IBM486SLC},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
{ "[MCA] IBM PS/2 model 50", "ibmps2_m50", MACHINE_TYPE_286, {{"Intel", cpus_ps2_m30_286}, {"IBM",cpus_IBM486SLC},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
/* 386SX machines */
{ "[ISA] IBM PS/1 model 2121", "ibmps1_2121", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 2, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[ISA] IBM PS/1 m.2121+ISA", "ibmps1_2121_isa", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 2, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
{ "[HT18] AMA-932J", "ama932j", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
{ "[WD76C10] Amstrad MegaPC", "megapc", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
{ "[SCAMP] Commodore SL386SX", "cbm_sl386sx25", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1024, 8192, 512, 127,machine_at_commodore_sl386sx_init, at_commodore_sl386sx_get_device },
{ "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[OPTi 291] DTK PPM-3333P", "awardsx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 16, 1, 127, machine_at_awardsx_init, NULL },
{ "[ISA] IBM PS/1 model 2121", "ibmps1_2121", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO_FIXED, 2, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[ISA] IBM PS/1 m.2121+ISA", "ibmps1_2121_isa", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
{ "[HT18] AMA-932J", "ama932j", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
{ "[WD76C10] Amstrad MegaPC", "megapc", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
{ "[SCAMP] Commodore SL386SX", "cbm_sl386sx25", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 8192, 512, 127,machine_at_commodore_sl386sx_init, at_commodore_sl386sx_get_device },
{ "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[OPTi 291] DTK PPM-3333P", "awardsx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 1, 16, 1, 127, machine_at_awardsx_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_M6117)
{ "[ALi M6117D] Acrosser AR-B1375", "arb1375", MACHINE_TYPE_386SX, {{"ALi", cpus_ALiM6117}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 32, 1, 127, machine_at_arb1375_init, NULL },
{ "[ALi M6117D] Acrosser PJ-A511M", "pja511m", MACHINE_TYPE_386SX, {{"ALi", cpus_ALiM6117}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 32, 1, 127, machine_at_pja511m_init, NULL },
{ "[ALi M6117D] Acrosser AR-B1375", "arb1375", MACHINE_TYPE_386SX, {{"ALi", cpus_ALiM6117}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1, 32, 1, 127, machine_at_arb1375_init, NULL },
{ "[ALi M6117D] Acrosser PJ-A511M", "pja511m", MACHINE_TYPE_386SX, {{"ALi", cpus_ALiM6117}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1, 32, 1, 127, machine_at_pja511m_init, NULL },
#endif
/* 386SX machines which utilize the MCA bus */
{ "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
{ "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
/* 386DX machines */
{ "[ACC 2168] AMI 386DX clone", "acc386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 16, 1, 127, machine_at_acc386_init, NULL },
{ "[SiS 310] ASUS ISA-386C", "asus386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 16384, 128, 127, machine_at_asus386_init, NULL },
{ "[ISA] Compaq Portable III (386)", "portableiii386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device },
{ "[ISA] Micronics 386 clone", "micronics386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_micronics386_init, NULL },
{ "[C&T 386] ECS 386/32", "ecs386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 16, 1, 127, machine_at_ecs386_init, NULL },
{ "[UMC 491] US Technologies 386", "ustechnologies386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 16, 1, 127,machine_at_ustechnologies386_init, NULL },
{ "[ACC 2168] AMI 386DX clone", "acc386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 1, 16, 1, 127, machine_at_acc386_init, NULL },
{ "[SiS 310] ASUS ISA-386C", "asus386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512,16384, 128, 127, machine_at_asus386_init, NULL },
{ "[ISA] Compaq Portable III (386)", "portableiii386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device },
{ "[ISA] Micronics 386 clone", "micronics386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 512, 8192, 128, 127, machine_at_micronics386_init, NULL },
{ "[C&T 386] ECS 386/32", "ecs386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 1, 16, 1, 127, machine_at_ecs386_init, NULL },
{ "[UMC 491] US Technologies 386", "ustechnologies386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_AT, 1, 16, 1, 127,machine_at_ustechnologies386_init, NULL },
/* 386DX machines which utilize the VLB bus */
{ "[OPTi 495] Award 386DX clone", "award386dx", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (386DX)", "ami386dx", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 495] MR 386DX clone", "mr386dx", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 495] Award 386DX clone", "award386dx", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (386DX)", "ami386dx", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 495] MR 386DX clone", "mr386dx", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
/* 386DX machines which utilize the MCA bus */
{ "[MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL },
{ "[MCA] IBM PS/2 model 80", "ibmps2_m80", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
{ "[MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL },
{ "[MCA] IBM PS/2 model 80", "ibmps2_m80", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
/* 486 machines with just the ISA slot */
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL },
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL },
/* 486 machines */
{ "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486, {{"IBM", cpus_IBM486SLC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_rycleopardlx_init, NULL },
{ "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (486)", "ami486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL },
{ "[OPTi 802G] IBM PC 330 (type 6571)", "pc330_6571", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 127, machine_at_pc330_6571_init, NULL },
{ "[CS4031] AMI 486 CS4031", "cs4031", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_cs4031_init, NULL },
{ "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_vli486sv2g_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ami471_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_WIN471)
{ "[SiS 471] AMI WinBIOS 486 clone", "win471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_win471_init, NULL },
#endif
{ "[SiS 471] DTK PKM-0038S E-2", "dtk486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_dtk486_init, NULL },
{ "[SiS 471] Phoenix SiS 471", "px471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_px471_init, NULL },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429] Olystar LIL1429", "ali1429", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_ali1429_init, NULL },
{ "[ALi M1429] AMI WinBIOS 486", "win486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_winbios1429_init, NULL },
{ "[VLSI 82C480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 2, 32, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device },
{ "[VIA VT82C495] FIC 486-VC-HD", "486vchd", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 32, 1, 127, machine_at_486vchd_init, NULL },
{ "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486, {{"IBM", cpus_IBM486SLC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE, 1, 16, 1, 127, machine_at_rycleopardlx_init, NULL },
{ "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (486)", "ami486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB, 1, 64, 1, 127, machine_at_403tg_init, NULL },
{ "[OPTi 802G] IBM PC 330 (type 6571)", "pc330_6571", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_BUS_PS2 | MACHINE_IDE, 1, 64, 1, 127, machine_at_pc330_6571_init, NULL },
{ "[CS4031] AMI 486 CS4031", "cs4031", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_VLB, 1, 64, 1, 127, machine_at_cs4031_init, NULL },
{ "[SiS 401] AMI 486 Clone", "sis401", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_IDE, 1, 64, 1, 127, machine_at_sis401_init, NULL },
{ "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE_DUAL, 1, 64, 1, 127, machine_at_vli486sv2g_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 64, 1, 127, machine_at_ami471_init, NULL },
{ "[SiS 471] AMI WinBIOS 486 clone", "win471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 64, 1, 127, machine_at_win471_init, NULL },
{ "[SiS 471] AOpen Vi15G", "vi15g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 64, 1, 127, machine_at_vi15g_init, NULL },
{ "[SiS 471] DTK PKM-0038S E-2", "dtk486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 64, 1, 127, machine_at_dtk486_init, NULL },
{ "[SiS 471] Phoenix SiS 471", "px471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 128, 1, 127, machine_at_px471_init, NULL },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429] Olystar LIL1429", "ali1429", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_ali1429_init, NULL },
{ "[ALi M1429] AMI WinBIOS 486", "win486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 1, 32, 1, 127, machine_at_winbios1429_init, NULL },
{ "[VLSI 82C480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_NONMI | MACHINE_VIDEO, 2, 32, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device },
{ "[VIA VT82C495] FIC 486-VC-HD", "486vchd", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_AT, 1, 32, 1, 127, machine_at_486vchd_init, NULL },
/* 486 machines with utilize the MCA bus */
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
{ "[MCA] IBM PS/2 model 70 (type 4)", "ibmps2_m70_type4", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type4_init, NULL },
{ "[MCA] IBM PS/2 model 70 (type 4)", "ibmps2_m70_type4", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type4_init, NULL },
#endif
/* 486 machines which utilize the PCI bus */
{ "[i420EX] ASUS PVI-486AP4", "486ap4", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_486ap4_init, NULL },
{ "[i420ZX] ASUS PCI/I-486SP3G", "486sp3g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_486sp3g_init, NULL },
{ "[i420TX] Intel Classic/PCI", "alfredo", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_alfredo_init, NULL },
{ "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 255, machine_at_ls486e_init, NULL },
{ "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_r418_init, NULL },
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_4dps_init, NULL },
{ "[i420EX] ASUS PVI-486AP4", "486ap4", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCIV | MACHINE_IDE_DUAL, 1, 128, 1, 127, machine_at_486ap4_init, NULL },
{ "[i420ZX] ASUS PCI/I-486SP3G", "486sp3g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_IDE_DUAL, 1, 128, 1, 127, machine_at_486sp3g_init, NULL },
{ "[i420TX] Intel Classic/PCI", "alfredo", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_alfredo_init, NULL },
{ "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_IDE_DUAL, 1, 128, 1, 255, machine_at_ls486e_init, NULL },
{ "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_IDE_DUAL, 1, 255, 1, 255, machine_at_r418_init, NULL },
{ "[SiS 496] Soyo 4SA2", "4sa2", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_IDE_DUAL, 1, 255, 1, 255, machine_at_4sa2_init, NULL },
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_IDE_DUAL, 1, 255, 1, 255, machine_at_4dps_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[VIA VT82C496G] FIC VIP-IO2", "486vipio2", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 255, machine_at_486vipio2_init, NULL },
{ "[VIA VT82C496G] FIC VIP-IO2", "486vipio2", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCIV | MACHINE_IDE_DUAL, 1, 128, 1, 255, machine_at_486vipio2_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_M1489)
{ "[ALi M1489] ABIT AB-PB4", "abpb4", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 255, machine_at_abpb4_init, NULL },
{ "[ALi M1489] ABIT AB-PB4", "abpb4", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_IDE_DUAL, 1, 64, 1, 255, machine_at_abpb4_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_STPC)
{ "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486, {{"ST", cpus_STPCDX}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_itoxstar_init, NULL },
{ "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, {{"ST", cpus_STPCDX2}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 160, 8, 255, machine_at_arb1479_init, NULL },
{ "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486, {{"ST", cpus_STPCDX2}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 96, 8, 255, machine_at_pcm9340_init, NULL },
{ "[STPC Atlas] AAEON PCM-5330", "pcm5330", MACHINE_TYPE_486, {{"ST", cpus_STPCDX2}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 128, 32, 255, machine_at_pcm5330_init, NULL },
{ "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486, {{"ST", cpus_STPCDX}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 255, machine_at_itoxstar_init, NULL },
{ "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, {{"ST", cpus_STPCDX2}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32, 160, 8, 255, machine_at_arb1479_init, NULL },
{ "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486, {{"ST", cpus_STPCDX2}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32, 96, 8, 255, machine_at_pcm9340_init, NULL },
{ "[STPC Atlas] AAEON PCM-5330", "pcm5330", MACHINE_TYPE_486, {{"ST", cpus_STPCDX2}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32, 128, 32, 255, machine_at_pcm5330_init, NULL },
#endif
/* Socket 4 machines */
/* OPTi 596/597 */
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 2, 64, 2, 127, machine_at_excalibur_init, NULL },
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_VLB | MACHINE_IDE, 2, 64, 2, 127, machine_at_excalibur_init, NULL },
/* 430LX */
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL },
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_batman_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_dellxp60_init, NULL },
#endif
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 136, 2, 127, machine_at_pb520r_init, at_pb520r_get_device },
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 136, 2, 127, machine_at_pb520r_init, at_pb520r_get_device },
/* Socket 5 machines */
/* 430NX */
{ "[i430NX] Intel Premiere/PCI II", "plato", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[i430NX] IBM Ambra DP90 PCI", "ambradp90", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_ambradp90_init, NULL },
{ "[i430NX] Gigabyte GA-586IP", "430nx", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_430nx_init, NULL },
{ "[i430NX] Intel Premiere/PCI II", "plato", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[i430NX] IBM Ambra DP90 PCI", "ambradp90", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_ambradp90_init, NULL },
{ "[i430NX] Gigabyte GA-586IP", "430nx", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2, 128, 2, 127, machine_at_430nx_init, NULL },
/* 430FX */
{ "[i430FX] Acer V30", "acerv30", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_acerv30_init, NULL },
{ "[i430FX] Acer V30", "acerv30", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_acerv30_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
{ "[i430FX] HP Vectra VL 5 Series 4", "vectra54", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2, 8, 128, 8, 511, machine_at_vectra54_init, NULL },
{ "[i430FX] HP Vectra VL 5 Series 4", "vectra54", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 511, machine_at_vectra54_init, NULL },
#endif
{ "[i430FX] Intel Advanced/ZP", "zappa", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_zappa_init, NULL },
{ "[i430FX] NEC PowerMate V", "powermate_v", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_powermate_v_init, NULL },
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb500n_init, NULL },
{ "[i430FX] Intel Advanced/ZP", "zappa", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_zappa_init, NULL },
{ "[i430FX] NEC PowerMate V", "powermate_v", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_powermate_v_init, NULL },
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_mb500n_init, NULL },
/* Socket 7 machines */
/* 430FX */
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
{ "[i430FX] ASUS P/I-P54TP4XE (MR BIOS)", "mr586", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2, 8, 128, 8, 127, machine_at_mr586_init, NULL },
{ "[i430FX] Gateway 2000 Thor", "gw2katx", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_gw2katx_init, NULL },
{ "[i430FX] Intel Advanced/ATX", "thor", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_thor_init, NULL },
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_mrthor_init, NULL },
{ "[i430FX] Intel Advanced/EV", "endeavor", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[i430FX] Packard Bell PB640", "pb640", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, at_pb640_get_device },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73VCH, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_chariot_init, NULL },
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
{ "[i430FX] ASUS P/I-P54TP4XE (MR BIOS)", "mr586", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_mr586_init, NULL },
{ "[i430FX] Gateway 2000 Thor", "gw2katx", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_gw2katx_init, NULL },
{ "[i430FX] Intel Advanced/ATX", "thor", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_thor_init, NULL },
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_mrthor_init, NULL },
{ "[i430FX] Intel Advanced/EV", "endeavor", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[i430FX] Packard Bell PB640", "pb640", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, at_pb640_get_device },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73VCH, MACHINE_PCI | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_chariot_init, NULL },
/* 430HX */
{ "[i430HX] Acer M3A", "acerm3a", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[i430HX] AOpen AP53", "ap53", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[i430HX] Biostar MB-8500TUC", "8500tuc", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_8500tuc_init, NULL },
{ "[i430HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
{ "[i430HX] Acer M3A", "acerm3a", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[i430HX] AOpen AP53", "ap53", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[i430HX] Biostar MB-8500TUC", "8500tuc", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_8500tuc_init, NULL },
{ "[i430HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_TYPE_SOCKET7_3V, MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerv35n_init, NULL },
{ "[i430HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_p55t2p4_init, NULL },
{ "[i430HX] Micronics M7S-Hi", "m7shi", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 511, machine_at_m7shi_init, NULL },
{ "[i430HX] Intel TC430HX", "tc430hx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_tc430hx_init, NULL },
{ "[i430HX] Toshiba Equium 5200D", "equium5200", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_equium5200_init, NULL },
{ "[i430HX] Sony VAIO PCV-240", "pcv240", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_pcv240_init, NULL },
{ "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)", "p65up5_cp55t2d", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cp55t2d_init, NULL },
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 192, 8, 127, machine_at_acerv35n_init, NULL },
{ "[i430HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 256, 8, 127, machine_at_p55t2p4_init, NULL },
{ "[i430HX] Micronics M7S-Hi", "m7shi", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 511, machine_at_m7shi_init, NULL },
{ "[i430HX] Intel TC430HX", "tc430hx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 255, machine_at_tc430hx_init, NULL },
{ "[i430HX] Toshiba Equium 5200D", "equium5200", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 192, 8, 127, machine_at_equium5200_init, NULL },
{ "[i430HX] Sony Vaio PCV-240", "pcv240", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 192, 8, 127, machine_at_pcv240_init, NULL },
{ "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)", "p65up5_cp55t2d", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_p65up5_cp55t2d_init, NULL },
/* 430VX */
{ "[i430VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[i430VX] Shuttle HOT-557", "430vx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[i430VX] HP Brio 80xx", "brio80xx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_brio80xx_init, NULL },
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_8500tvxa_init, NULL },
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_presario4500_init, NULL },
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_gw2kte_init, NULL },
{ "[i430VX] Packard Bell PB680", "pb680", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_pb680_init, NULL },
{ "[i430VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[i430VX] Shuttle HOT-557", "430vx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_gw2kte_init, NULL },
{ "[i430VX] HP Brio 80xx", "brio80xx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_brio80xx_init, NULL },
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_8500tvxa_init, NULL },
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_presario4500_init, NULL },
{ "[i430VX] Packard Bell PB680", "pb680", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_pb680_init, NULL },
/* 430TX */
{ "[i430TX] ADLink NuPRO-592", "nupro592", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_nupro592_init, NULL },
{ "[i430TX] ASUS TX97", "tx97", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_tx97_init, NULL },
{ "[i430TX] Intel YM430TX", "ym430tx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_ym430tx_init, NULL },
{ "[i430TX] PC Partner MB540N", "mb540n", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_mb540n_init, NULL },
{ "[i430TX] SuperMicro Super P5MMS98", "p5mms98", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p5mms98_init, NULL },
{ "[i430TX] ADLink NuPRO-592", "nupro592", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 256, 8, 255, machine_at_nupro592_init, NULL },
{ "[i430TX] ASUS TX97", "tx97", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 256, 8, 255, machine_at_tx97_init, NULL },
{ "[i430TX] Intel YM430TX", "ym430tx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 256, 8, 255, machine_at_ym430tx_init, NULL },
{ "[i430TX] PC Partner MB540N", "mb540n", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 256, 8, 255, machine_at_mb540n_init, NULL },
{ "[i430TX] SuperMicro Super P5MMS98", "p5mms98", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 256, 8, 255, machine_at_p5mms98_init, NULL },
/* Apollo VPX */
{ "[VIA VPX] FIC VA-502", "ficva502", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ficva502_init, NULL },
{ "[VIA VPX] FIC VA-502", "ficva502", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_ficva502_init, NULL },
/* Apollo VP3 */
{ "[VIA VP3] FIC PA-2012", "ficpa2012", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_ficpa2012_init, NULL },
{ "[VIA VP3] FIC PA-2012", "ficpa2012", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 127, machine_at_ficpa2012_init, NULL },
/* Super Socket 7 machines */
/* Apollo MVP3 */
{ "[VIA MVP3] AOpen AX59 Pro", "ax59pro", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_ax59pro_init, NULL },
{ "[VIA MVP3] FIC VA-503+", "ficva503p", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_mvp3_init, NULL },
{ "[VIA MVP3] FIC VA-503A", "ficva503a", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_ficva503a_init, NULL },
{ "[VIA MVP3] AOpen AX59 Pro", "ax59pro", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_ax59pro_init, NULL },
{ "[VIA MVP3] FIC VA-503+", "ficva503p", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_mvp3_init, NULL },
{ "[VIA MVP3] FIC VA-503A", "ficva503a", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_ficva503a_init, NULL },
/* Socket 8 machines */
/* 440FX */
{ "[i440FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_p65up5_cp6nd_init, NULL },
{ "[i440FX] Biostar MB-8600TTC", "8600ttc", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_8500ttc_init, NULL },
{ "[i440FX] Gigabyte GA-686NX", "686nx", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_686nx_init, NULL },
{ "[i440FX] Acer V60N", "v60n", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_v60n_init, NULL },
{ "[i440FX] Intel AP440FX", "ap440fx", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_ap440fx_init, NULL },
{ "[i440FX] Intel VS440FX", "vs440fx", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_vs440fx_init, NULL },
{ "[i440FX] Micronics M6Mi", "m6mi", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_m6mi_init, NULL },
{ "[i440FX] PC Partner MB600N", "mb600n", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_mb600n_init, NULL },
{ "[i440FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 127, machine_at_p65up5_cp6nd_init, NULL },
{ "[i440FX] Biostar MB-8600TTC", "8600ttc", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 127, machine_at_8500ttc_init, NULL },
{ "[i440FX] Gigabyte GA-686NX", "686nx", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_686nx_init, NULL },
{ "[i440FX] Acer V60N", "v60n", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_v60n_init, NULL },
{ "[i440FX] Intel AP440FX", "ap440fx", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 128, 8, 127, machine_at_ap440fx_init, NULL },
{ "[i440FX] Intel VS440FX", "vs440fx", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_vs440fx_init, NULL },
{ "[i440FX] Micronics M6Mi", "m6mi", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 127, machine_at_m6mi_init, NULL },
{ "[i440FX] PC Partner MB600N", "mb600n", MACHINE_TYPE_SOCKET8, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 127, machine_at_mb600n_init, NULL },
/* Slot 1 machines */
/* 440FX */
{ "[i440FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_p65up5_cpknd_init, NULL },
{ "[i440FX] ASUS KN97", "kn97", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_kn97_init, NULL },
{ "[i440FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 127, machine_at_p65up5_cpknd_init, NULL },
{ "[i440FX] ASUS KN97", "kn97", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 127, machine_at_kn97_init, NULL },
/* 440LX */
{ "[i440LX] ABIT LX6", "lx6", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_lx6_init, NULL },
{ "[i440LX] Micronics Spitfire", "spitfire", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_spitfire_init, NULL },
{ "[i440LX] ABIT LX6", "lx6", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_lx6_init, NULL },
{ "[i440LX] Micronics Spitfire", "spitfire", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_spitfire_init, NULL },
/* 440EX */
{ "[i440EX] QDI EXCELLENT II", "p6i440e2", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_p6i440e2_init, NULL },
{ "[i440EX] QDI EXCELLENT II", "p6i440e2", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 255, machine_at_p6i440e2_init, NULL },
/* 440BX */
{ "[i440BX] ASUS P2B-LS", "p2bls", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[i440BX] ASUS P3B-F", "p3bf", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p3bf_init, NULL },
{ "[i440BX] ABIT BF6", "bf6", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL },
{ "[i440BX] AOpen AX6BC", "ax6bc", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_ax6bc_init, NULL },
{ "[i440BX] A-Trend ATC6310BXII", "atc6310bxii", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_atc6310bxii_init, NULL },
{ "[i440BX] Tyan Tsunami ATX", "tsunamiatx", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_SOUND, 8, 1024, 8, 255, machine_at_tsunamiatx_init, at_tsunamiatx_get_device },
{ "[i440BX] SuperMicro Super P6SBA", "p6sba", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_p6sba_init, NULL },
{ "[VIA Apollo Pro] FIC KA-6100", "ficka6100", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_ficka6100_init, NULL },
{ "[i440BX] ASUS P2B-LS", "p2bls", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[i440BX] ASUS P3B-F", "p3bf", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_p3bf_init, NULL },
{ "[i440BX] ABIT BF6", "bf6", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_bf6_init, NULL },
{ "[i440BX] AOpen AX6BC", "ax6bc", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_ax6bc_init, NULL },
{ "[i440BX] A-Trend ATC6310BXII", "atc6310bxii", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_atc6310bxii_init, NULL },
{ "[i440BX] Tyan Tsunami ATX", "tsunamiatx", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_SOUND, 8, 1024, 8, 255, machine_at_tsunamiatx_init, at_tsunamiatx_get_device },
{ "[i440BX] SuperMicro Super P6SBA", "p6sba", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_p6sba_init, NULL },
/* VIA Apollo Pro */
{ "[VIA Apollo Pro] FIC KA-6100", "ficka6100", MACHINE_TYPE_SLOT1, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_ficka6100_init, NULL },
/* 440GX */
{ "[i440GX] Freeway FW-6400GX", "fw6400gx_s1", MACHINE_TYPE_SLOT2, {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16, 2032, 16, 511, machine_at_fw6400gx_init, NULL },
/* Slot 2 machines(Including Slot 1/2 Hybrids) */
/* 440GX */
{ "[i440GX] Gigabyte GA-6GXU", "6gxu", MACHINE_TYPE_SLOT2, {{"Intel", cpus_Xeon}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 16, 2048, 16, 511, machine_at_6gxu_init, NULL },
{ "[i440GX] SuperMicro Super S2DGE", "s2dge", MACHINE_TYPE_SLOT2, {{"Intel", cpus_Xeon}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 16, 2048, 16, 511, machine_at_s2dge_init, NULL },
{ "[i440GX] Freeway FW-6400GX", "fw6400gx", MACHINE_TYPE_SLOT2, {{"Intel/Slot1", cpus_PentiumII},{"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"Intel/Slot2", cpus_Xeon},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 16, 2032, 16, 511, machine_at_fw6400gx_init, NULL },
{ "[i440GX] Gigabyte GA-6GXU", "6gxu", MACHINE_TYPE_SLOT2, {{"Intel", cpus_Xeon}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16, 2048, 16, 511, machine_at_6gxu_init, NULL },
{ "[i440GX] SuperMicro Super S2DGE", "s2dge", MACHINE_TYPE_SLOT2, {{"Intel", cpus_Xeon}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16, 2048, 16, 511, machine_at_s2dge_init, NULL },
{ "[i440GX] Freeway FW-6400GX", "fw6400gx", MACHINE_TYPE_SLOT2, {{"Intel", cpus_Xeon}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16, 2032, 16, 511, machine_at_fw6400gx_init, NULL },
/* PGA370 machines */
/* 440LX */
{ "[i440LX] SuperMicro Super 370SLM", "s370slm", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_s370slm_init, NULL },
{ "[i440LX] SuperMicro Super 370SLM", "s370slm", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_s370slm_init, NULL },
/* 440BX */
{ "[i440BX] ASUS CUBX", "cubx", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_cubx_init, NULL },
{ "[i440BX] A-Trend ATC7020BXII", "atc7020bxii", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL },
{ "[i440BX] AmazePC AM-BX133", "ambx133", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_ambx133_init, NULL },
{ "[i440BX] AEWIN AW-O671R", "awo671r", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_awo671r_init, NULL },
{ "[i440BX] ASUS CUBX", "cubx", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_cubx_init, NULL },
{ "[i440BX] A-Trend ATC7020BXII", "atc7020bxii", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL },
{ "[i440BX] AmazePC AM-BX133", "ambx133", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_ambx133_init, NULL },
{ "[i440BX] AEWIN AW-O671R", "awo671r", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 255, machine_at_awo671r_init, NULL },
/* 440ZX */
{ "[i440ZX] Soltek SL-63A1", "63a", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
{ "[i440ZX] Soltek SL-63A1", "63a", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 512, 8, 255, machine_at_63a_init, NULL },
/* VIA Apollo Pro */
{ "[VIA Apollo Pro] PC Partner APAS3", "apas3", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_apas3_init, NULL },
{ "[VIA Apollo Pro] PC Partner APAS3", "apas3", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 768, 8, 255, machine_at_apas3_init, NULL },
/* Miscellaneous/Fake/Hypervisor machines */
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, {{"Intel", cpus_PentiumIID}, {"Intel/PGA370", cpus_Celeron},{"", NULL}, {"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_vpc2007_init, NULL },
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, {{"Intel", cpus_PentiumIID}, {"Intel/PGA370", cpus_Celeron},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8, 1024, 8, 255, machine_at_vpc2007_init, NULL },
{ NULL, NULL, MACHINE_TYPE_NONE, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
{ NULL, NULL, MACHINE_TYPE_NONE, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
};

436
src/mem/mem.c
View File

@@ -8,12 +8,6 @@
*
* Memory handling and MMU.
*
* NOTE: Experimenting with dynamically allocated lookup tables;
* the DYNAMIC_TABLES=1 enables this. Will eventually go
* away, either way...
*
*
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -58,12 +52,7 @@
#endif
#define FIXME 0
#define DYNAMIC_TABLES 0 /* experimental */
mem_mapping_t base_mapping,
ram_low_mapping, /* 0..640K mapping */
mem_mapping_t ram_low_mapping, /* 0..640K mapping */
#if 1
ram_mid_mapping,
#endif
@@ -72,7 +61,6 @@ mem_mapping_t base_mapping,
ram_2gb_mapping, /* 1024M+ mapping */
ram_remapped_mapping,
ram_split_mapping,
ram_smram_mapping[2],
bios_mapping,
bios_high_mapping;
@@ -110,8 +98,6 @@ int cachesize = 256;
uint32_t get_phys_virt,
get_phys_phys;
smram_t smram[2] = { { 0x000a0000, 0x000a0000 }, { 0x000a0000, 0x000a0000 } };
int mem_a20_key = 0,
mem_a20_alt = 0,
mem_a20_state = 0;
@@ -129,21 +115,13 @@ int use_phys_exec = 0;
/* FIXME: re-do this with a 'mem_ops' struct. */
static mem_mapping_t *base_mapping, *last_mapping;
static mem_mapping_t *read_mapping[MEM_MAPPINGS_NO];
static mem_mapping_t *write_mapping[MEM_MAPPINGS_NO];
static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff };
static uint8_t *_mem_exec[MEM_MAPPINGS_NO];
static uint32_t _mem_state[MEM_MAPPINGS_NO];
#if FIXME
#if (MEM_GRANULARITY_BITS >= 12)
static uint8_t ff_array[MEM_GRANULARITY_SIZE];
#else
static uint8_t ff_array[4096]; /* Must be at least one page. */
#endif
#else
static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff };
#endif
#ifdef ENABLE_MEM_LOG
int mem_do_log = ENABLE_MEM_LOG;
@@ -179,17 +157,8 @@ resetreadlookup(void)
{
int c;
/* This is NULL after app startup, when mem_init() has not yet run. */
#if DYNAMIC_TABLES
mem_log("MEM: reset_lookup: pages=%08lx, lookup=%08lx, pages_sz=%i\n", pages, page_lookup, pages_sz);
#endif
/* Initialize the page lookup table. */
#if DYNAMIC_TABLES
memset(page_lookup, 0x00, pages_sz*sizeof(page_t *));
#else
memset(page_lookup, 0x00, (1<<20)*sizeof(page_t *));
#endif
/* Initialize the tables for lower (<= 1024K) RAM. */
for (c = 0; c < 256; c++) {
@@ -198,13 +167,8 @@ mem_log("MEM: reset_lookup: pages=%08lx, lookup=%08lx, pages_sz=%i\n", pages, pa
}
/* Initialize the tables for high (> 1024K) RAM. */
#if DYNAMIC_TABLES
memset(readlookup2, 0xff, pages_sz*sizeof(uintptr_t));
memset(writelookup2, 0xff, pages_sz*sizeof(uintptr_t));
#else
memset(readlookup2, 0xff, (1<<20)*sizeof(uintptr_t));
memset(writelookup2, 0xff, (1<<20)*sizeof(uintptr_t));
#endif
readlnext = 0;
writelnext = 0;
@@ -692,11 +656,33 @@ getpccache(uint32_t a)
mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a >> 32), (uint32_t) (a & 0xffffffff));
#if FIXME
return &ff_array[0-(uintptr_t)(a2 & ~0xfff)];
#else
return (uint8_t *)&ff_pccache;
#endif
}
uint8_t
read_mem_b(uint32_t addr)
{
mem_mapping_t *map;
mem_logical_addr = addr;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
return map->read_b(addr, map->p);
return 0xff;
}
void
write_mem_b(uint32_t addr, uint8_t val)
{
mem_mapping_t *map;
mem_logical_addr = addr;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->p);
}
@@ -1093,8 +1079,7 @@ readmemwl(uint32_t seg, uint32_t addr)
}
if (is386) return readmemb386l(seg,addr)|(((uint16_t) readmemb386l(seg,addr+1))<<8);
else return readmembl(seg+addr)|(((uint16_t) readmembl(seg+addr+1))<<8);
}
else if (readlookup2[addr2 >> 12] != (uintptr_t) LOOKUP_INV)
} else if (readlookup2[addr2 >> 12] != (uintptr_t) LOOKUP_INV)
return *(uint16_t *)(readlookup2[addr2 >> 12] + addr2);
}
@@ -1584,7 +1569,8 @@ mem_read_ram(uint32_t addr, void *priv)
mem_log("Read B %02X from %08X\n", ram[addr], addr);
#endif
addreadlookup(mem_logical_addr, addr);
if (AT)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
@@ -1598,7 +1584,8 @@ mem_read_ramw(uint32_t addr, void *priv)
mem_log("Read W %04X from %08X\n", *(uint16_t *)&ram[addr], addr);
#endif
addreadlookup(mem_logical_addr, addr);
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *)&ram[addr];
}
@@ -1612,7 +1599,8 @@ mem_read_raml(uint32_t addr, void *priv)
mem_log("Read L %08X from %08X\n", *(uint32_t *)&ram[addr], addr);
#endif
addreadlookup(mem_logical_addr, addr);
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *)&ram[addr];
}
@@ -1660,45 +1648,6 @@ mem_read_ram_2gbl(uint32_t addr, void *priv)
}
uint8_t
mem_read_smram(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gb(new_addr, priv);
else
return mem_read_ram(new_addr, priv);
}
uint16_t
mem_read_smramw(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gbw(new_addr, priv);
else
return mem_read_ramw(new_addr, priv);
}
uint32_t
mem_read_smraml(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gbl(new_addr, priv);
else
return mem_read_raml(new_addr, priv);
}
#ifdef USE_NEW_DYNAREC
static inline int
page_index(page_t *p)
@@ -1894,8 +1843,11 @@ mem_write_ram(uint32_t addr, uint8_t val, void *priv)
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write B %02X to %08X\n", val, addr);
#endif
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[addr >> 12]);
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[addr >> 12]);
} else
ram[addr] = val;
}
@@ -1906,8 +1858,11 @@ mem_write_ramw(uint32_t addr, uint16_t val, void *priv)
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write W %04X to %08X\n", val, addr);
#endif
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[addr >> 12]);
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[addr >> 12]);
} else
*(uint16_t *)&ram[addr] = val;
}
@@ -1918,38 +1873,11 @@ mem_write_raml(uint32_t addr, uint32_t val, void *priv)
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write L %08X to %08X\n", val, addr);
#endif
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[addr >> 12]);
}
void
mem_write_smram(uint32_t addr, uint8_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
mem_write_ram(new_addr, val, priv);
}
void
mem_write_smramw(uint32_t addr, uint16_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
mem_write_ramw(new_addr, val, priv);
}
void
mem_write_smraml(uint32_t addr, uint32_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
mem_write_raml(new_addr, val, priv);
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[addr >> 12]);
} else
*(uint32_t *)&ram[addr] = val;
}
@@ -1958,7 +1886,8 @@ mem_read_remapped(uint32_t addr, void *priv)
{
if ((addr >= (mem_size * 1024)) && (addr < ((mem_size + 384) * 1024)))
addr = 0xA0000 + (addr - (mem_size * 1024));
addreadlookup(mem_logical_addr, addr);
if (AT)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
@@ -1968,7 +1897,8 @@ mem_read_remappedw(uint32_t addr, void *priv)
{
if ((addr >= (mem_size * 1024)) && (addr < ((mem_size + 384) * 1024)))
addr = 0xA0000 + (addr - (mem_size * 1024));
addreadlookup(mem_logical_addr, addr);
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *)&ram[addr];
}
@@ -1978,7 +1908,8 @@ mem_read_remappedl(uint32_t addr, void *priv)
{
if ((addr >= (mem_size * 1024)) && (addr < ((mem_size + 384) * 1024)))
addr = 0xA0000 + (addr - (mem_size * 1024));
addreadlookup(mem_logical_addr, addr);
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *)&ram[addr];
}
@@ -1989,8 +1920,11 @@ mem_write_remapped(uint32_t addr, uint8_t val, void *priv)
uint32_t oldaddr = addr;
if ((addr >= (mem_size * 1024)) && (addr < ((mem_size + 384) * 1024)))
addr = 0xA0000 + (addr - (mem_size * 1024));
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]);
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]);
} else
ram[addr] = val;
}
@@ -2000,8 +1934,11 @@ mem_write_remappedw(uint32_t addr, uint16_t val, void *priv)
uint32_t oldaddr = addr;
if ((addr >= (mem_size * 1024)) && (addr < ((mem_size + 384) * 1024)))
addr = 0xA0000 + (addr - (mem_size * 1024));
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]);
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]);
} else
*(uint16_t *)&ram[addr] = val;
}
@@ -2011,50 +1948,11 @@ mem_write_remappedl(uint32_t addr, uint32_t val, void *priv)
uint32_t oldaddr = addr;
if ((addr >= (mem_size * 1024)) && (addr < ((mem_size + 384) * 1024)))
addr = 0xA0000 + (addr - (mem_size * 1024));
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[oldaddr >> 12]);
}
uint8_t
mem_read_bios(uint32_t addr, void *priv)
{
uint8_t ret = 0xff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = rom[addr - biosaddr];
return ret;
}
uint16_t
mem_read_biosw(uint32_t addr, void *priv)
{
uint16_t ret = 0xffff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint16_t *)&rom[addr - biosaddr];
return ret;
}
uint32_t
mem_read_biosl(uint32_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint32_t *)&rom[addr - biosaddr];
return ret;
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[oldaddr >> 12]);
} else
*(uint32_t *)&ram[addr] = val;
}
@@ -2224,10 +2122,13 @@ mem_mapping_write_allowed(uint32_t flags, uint32_t state)
void
mem_mapping_recalc(uint64_t base, uint64_t size)
{
mem_mapping_t *map = base_mapping.next;
mem_mapping_t *map;
uint64_t c;
if (! size) return;
if (!size || (base_mapping == NULL))
return;
map = base_mapping;
/* Clear out old mappings. */
for (c = base; c < base + size; c += MEM_GRANULARITY_SIZE) {
@@ -2239,6 +2140,7 @@ mem_mapping_recalc(uint64_t base, uint64_t size)
/* Walk mapping list. */
while (map != NULL) {
/*In range?*/
mem_log("mem_mapping_recalc(): %08X -> %08X\n", map, map->next);
if (map->enable && (uint64_t)map->base < ((uint64_t)base + (uint64_t)size) && ((uint64_t)map->base + (uint64_t)map->size) > (uint64_t)base) {
uint64_t start = (map->base < base) ? map->base : base;
uint64_t end = (((uint64_t)map->base + (uint64_t)map->size) < (base + size)) ? ((uint64_t)map->base + (uint64_t)map->size) : (base + size);
@@ -2282,18 +2184,35 @@ mem_mapping_recalc(uint64_t base, uint64_t size)
void
mem_mapping_del(mem_mapping_t *map)
{
mem_mapping_t *ptr;
/* Do a sanity check */
if ((base_mapping == NULL) && (last_mapping != NULL)) {
fatal("mem_mapping_del(): NULL base mapping with non-NULL last mapping\n");
return;
} else if ((base_mapping != NULL) && (last_mapping == NULL)) {
fatal("mem_mapping_del(): Non-NULL base mapping with NULL last mapping\n");
return;
} else if ((base_mapping != NULL) && (base_mapping->prev != NULL)) {
fatal("mem_mapping_del(): Base mapping with a preceding mapping\n");
return;
} else if ((last_mapping != NULL) && (last_mapping->next != NULL)) {
fatal("mem_mapping_del(): Last mapping with a following mapping\n");
return;
}
/* Disable the entry. */
mem_mapping_disable(map);
/* Zap it from the list. */
for (ptr = &base_mapping; ptr->next != NULL; ptr = ptr->next) {
if (ptr->next == map) {
ptr->next = map->next;
break;
}
}
if (map->prev != NULL)
map->prev->next = map->next;
if (map->next != NULL)
map->next->prev = map->prev;
/* Check if it's the first or the last mapping. */
if (base_mapping == map)
base_mapping = map->next;
if (last_mapping == map)
last_mapping = map->prev;
}
@@ -2311,17 +2230,37 @@ mem_mapping_add(mem_mapping_t *map,
uint32_t fl,
void *p)
{
mem_mapping_t *dest = &base_mapping;
/* Do a sanity check */
if ((base_mapping == NULL) && (last_mapping != NULL)) {
fatal("mem_mapping_add(): NULL base mapping with non-NULL last mapping\n");
return;
} else if ((base_mapping != NULL) && (last_mapping == NULL)) {
fatal("mem_mapping_add(): Non-NULL base mapping with NULL last mapping\n");
return;
} else if ((base_mapping != NULL) && (base_mapping->prev != NULL)) {
fatal("mem_mapping_add(): Base mapping with a preceding mapping\n");
return;
} else if ((last_mapping != NULL) && (last_mapping->next != NULL)) {
fatal("mem_mapping_add(): Last mapping with a following mapping\n");
return;
}
/* Add mapping to the beginning of the list if necessary.*/
if (base_mapping == NULL)
base_mapping = map;
/* Add mapping to the end of the list.*/
while (dest->next)
dest = dest->next;
dest->next = map;
map->prev = dest;
if (last_mapping == NULL)
map->prev = NULL;
else {
map->prev = last_mapping;
last_mapping->next = map;
}
last_mapping = map;
if (size)
if (size != 0x00000000)
map->enable = 1;
else
else
map->enable = 0;
map->base = base;
map->size = size;
@@ -2336,8 +2275,11 @@ mem_mapping_add(mem_mapping_t *map,
map->p = p;
map->dev = NULL;
map->next = NULL;
mem_log("mem_mapping_add(): Linked list structure: %08X -> %08X -> %08X\n", map->prev, map, map->next);
mem_mapping_recalc(map->base, map->size);
/* If the mapping is disabled, there is no need to recalc anything. */
if (size != 0x00000000)
mem_mapping_recalc(map->base, map->size);
}
@@ -2474,47 +2416,6 @@ mem_set_state(int smm, int mode, uint32_t base, uint32_t size, uint32_t state)
}
void
mem_add_bios(void)
{
int temp_cpu_type, temp_cpu_16bitbus = 1;
if (AT) {
temp_cpu_type = machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type;
temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC );
}
if (biosmask > 0x1ffff) {
/* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */
mem_mapping_add(&bios_mapping, 0xe0000, 0x20000,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
&rom[0x20000], MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(0x0e0000, 0x20000,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
} else {
mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr, biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
if (AT) {
mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
}
void
mem_a20_init(void)
{
@@ -2530,15 +2431,28 @@ mem_a20_init(void)
}
/* Close all the memory mappings. */
void
mem_close(void)
{
mem_mapping_t *map = base_mapping, *next;
while (map != NULL) {
next = map->next;
mem_mapping_del(map);
map = next;
}
base_mapping = last_mapping = 0;
}
/* Reset the memory state. */
void
mem_reset(void)
{
uint32_t c, m, m2;
#if FIXME
memset(ff_array, 0xff, sizeof(ff_array));
#endif
memset(page_ff, 0xff, sizeof(page_ff));
m = 1024UL * mem_size;
@@ -2618,9 +2532,6 @@ mem_reset(void)
* Allocate and initialize the (new) page table.
* We only do this if the size of the page table has changed.
*/
#if DYNAMIC_TABLES
mem_log("MEM: reset: previous pages=%08lx, pages_sz=%i\n", pages, pages_sz);
#endif
if (pages_sz != m) {
pages_sz = m;
if (pages) {
@@ -2628,29 +2539,9 @@ mem_log("MEM: reset: previous pages=%08lx, pages_sz=%i\n", pages, pages_sz);
pages = NULL;
}
pages = (page_t *)malloc(m*sizeof(page_t));
#if DYNAMIC_TABLES
mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz);
#endif
#if DYNAMIC_TABLES
/* Allocate the (new) lookup tables. */
if (page_lookup != NULL) free(page_lookup);
page_lookup = (page_t **)malloc(pages_sz*sizeof(page_t *));
if (readlookup2 != NULL) free(readlookup2);
readlookup2 = malloc(pages_sz*sizeof(uintptr_t));
if (writelookup2 != NULL) free(writelookup2);
writelookup2 = malloc(pages_sz*sizeof(uintptr_t));
#endif
}
#if DYNAMIC_TABLES
memset(page_lookup, 0x00, pages_sz * sizeof(page_t *));
#else
memset(page_lookup, 0x00, (1 << 20) * sizeof(page_t *));
#endif
memset(pages, 0x00, pages_sz*sizeof(page_t));
@@ -2705,7 +2596,7 @@ mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz);
memset(_mem_exec, 0x00, sizeof(_mem_exec));
memset(&base_mapping, 0x00, sizeof(base_mapping));
base_mapping = last_mapping = NULL;
memset(_mem_state, 0x00, sizeof(_mem_state));
@@ -2766,27 +2657,13 @@ mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz);
ram + 0xa0000, MEM_MAPPING_INTERNAL, NULL);
}
mem_mapping_add(&ram_smram_mapping[0], 0xa0000, 0x60000,
mem_read_smram,mem_read_smramw,mem_read_smraml,
mem_write_smram,mem_write_smramw,mem_write_smraml,
ram + 0xa0000, MEM_MAPPING_SMRAM, &(smram[0]));
mem_mapping_add(&ram_smram_mapping[1], 0xa0000, 0x60000,
mem_read_smram,mem_read_smramw,mem_read_smraml,
mem_write_smram,mem_write_smramw,mem_write_smraml,
ram + 0xa0000, MEM_MAPPING_SMRAM, &(smram[1]));
mem_mapping_disable(&ram_smram_mapping[0]);
mem_mapping_disable(&ram_smram_mapping[1]);
mem_mapping_add(&ram_remapped_mapping, mem_size * 1024, 256 * 1024,
mem_read_remapped,mem_read_remappedw,mem_read_remappedl,
mem_write_remapped,mem_write_remappedw,mem_write_remappedl,
ram + 0xa0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_disable(&ram_remapped_mapping);
mem_a20_init();
smram[0].host_base = smram[0].ram_base = smram[0].size = 0x00000000;
smram[1].host_base = smram[1].ram_base = smram[1].size = 0x00000000;
mem_a20_init();
#ifdef USE_NEW_DYNAREC
purgable_page_list_head = 0;
@@ -2802,22 +2679,11 @@ mem_init(void)
ram = rom = NULL;
ram2 = NULL;
pages = NULL;
#if DYNAMIC_TABLES
page_lookup = NULL;
readlookup2 = NULL;
writelookup2 = NULL;
#else
/* Allocate the lookup tables. */
page_lookup = (page_t **)malloc((1<<20)*sizeof(page_t *));
readlookup2 = malloc((1<<20)*sizeof(uintptr_t));
writelookup2 = malloc((1<<20)*sizeof(uintptr_t));
#endif
/* Reset the memory state. */
mem_reset();
}

86
src/mem/rom.c
View File

@@ -30,6 +30,7 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/plat.h>
@@ -316,6 +317,89 @@ rom_reset(uint32_t addr, int sz)
}
uint8_t
bios_read(uint32_t addr, void *priv)
{
uint8_t ret = 0xff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = rom[addr - biosaddr];
return ret;
}
uint16_t
bios_readw(uint32_t addr, void *priv)
{
uint16_t ret = 0xffff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint16_t *)&rom[addr - biosaddr];
return ret;
}
uint32_t
bios_readl(uint32_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint32_t *)&rom[addr - biosaddr];
return ret;
}
static void
bios_add(void)
{
int temp_cpu_type, temp_cpu_16bitbus = 1;
if (AT) {
temp_cpu_type = machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type;
temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC );
}
if (biosmask > 0x1ffff) {
/* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */
mem_mapping_add(&bios_mapping, 0xe0000, 0x20000,
bios_read,bios_readw,bios_readl,
mem_write_null,mem_write_nullw,mem_write_nulll,
&rom[0x20000], MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(0x0e0000, 0x20000,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
} else {
mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1,
bios_read,bios_readw,bios_readl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr, biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
if (AT) {
mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
bios_read,bios_readw,bios_readl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
}
/* These four are for loading the BIOS. */
int
bios_load(wchar_t *fn1, wchar_t *fn2, uint32_t addr, int sz, int off, int flags)
@@ -359,7 +443,7 @@ bios_load(wchar_t *fn1, wchar_t *fn2, uint32_t addr, int sz, int off, int flags)
}
if (!bios_only && ret && !(flags & FLAG_AUX))
mem_add_bios();
bios_add();
return ret;
}

366
src/mem/smram.c Normal file
View File

@@ -0,0 +1,366 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* SMRAM handling.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2020 Miran Grca.
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include "x86_ops.h"
#include "x86.h"
#include <86box/config.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/smram.h>
static smram_t *base_smram, *last_smram;
#ifdef ENABLE_SMRAM_LOG
int smram_do_log = ENABLE_SMRAM_LOG;
static void
smram_log(const char *fmt, ...)
{
va_list ap;
if (smram_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define smram_log(fmt, ...)
#endif
static uint8_t
smram_read(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gb(new_addr, priv);
else
return mem_read_ram(new_addr, priv);
}
static uint16_t
smram_readw(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gbw(new_addr, priv);
else
return mem_read_ramw(new_addr, priv);
}
static uint32_t
smram_readl(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gbl(new_addr, priv);
else
return mem_read_raml(new_addr, priv);
}
static void
smram_write(uint32_t addr, uint8_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
mem_write_ram(new_addr, val, priv);
}
static void
smram_writew(uint32_t addr, uint16_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
mem_write_ramw(new_addr, val, priv);
}
static void
smram_writel(uint32_t addr, uint32_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
mem_write_raml(new_addr, val, priv);
}
/* Make a backup copy of host_base and size of all the SMRAM structs, needed so that if
the SMRAM mappings change while in SMM, they will be recalculated on return. */
void
smram_backup_all(void)
{
smram_t *temp_smram = base_smram, *next;
while (temp_smram != NULL) {
temp_smram->old_host_base = temp_smram->host_base;
temp_smram->old_size = temp_smram->size;
next = temp_smram->next;
temp_smram = next;
}
}
/* Recalculate any mappings, including the backup if returning from SMM. */
void
smram_recalc_all(int ret)
{
smram_t *temp_smram = base_smram, *next;
if (base_smram == NULL)
return;
if (ret) {
while (temp_smram != NULL) {
if (temp_smram->old_size != 0x00000000)
mem_mapping_recalc(temp_smram->old_host_base, temp_smram->old_size);
temp_smram->old_host_base = temp_smram->old_size = 0x00000000;
next = temp_smram->next;
temp_smram = next;
}
}
temp_smram = base_smram;
while (temp_smram != NULL) {
if (temp_smram->size != 0x00000000)
mem_mapping_recalc(temp_smram->host_base, temp_smram->size);
next = temp_smram->next;
temp_smram = next;
}
flushmmucache();
}
/* Delete a SMRAM mapping. */
void
smram_del(smram_t *smr)
{
/* Do a sanity check */
if ((base_smram == NULL) && (last_smram != NULL)) {
fatal("smram_del(): NULL base SMRAM with non-NULL last SMRAM\n");
return;
} else if ((base_smram != NULL) && (last_smram == NULL)) {
fatal("smram_del(): Non-NULL base SMRAM with NULL last SMRAM\n");
return;
} else if ((base_smram != NULL) && (base_smram->prev != NULL)) {
fatal("smram_del(): Base SMRAM with a preceding SMRAM\n");
return;
} else if ((last_smram != NULL) && (last_smram->next != NULL)) {
fatal("smram_del(): Last SMRAM with a following SMRAM\n");
return;
}
if (smr == NULL) {
fatal("smram_del(): Invalid SMRAM mapping\n");
return;
}
/* Disable the entry. */
smram_disable(smr);
/* Zap it from the list. */
if (smr->prev != NULL)
smr->prev->next = smr->next;
if (smr->next != NULL)
smr->next->prev = smr->prev;
/* Check if it's the first or the last mapping. */
if (base_smram == smr)
base_smram = smr->next;
if (last_smram == smr)
last_smram = smr->prev;
free(smr);
}
/* Add a SMRAM mapping. */
smram_t *
smram_add(void)
{
smram_t *temp_smram;
/* Do a sanity check */
if ((base_smram == NULL) && (last_smram != NULL)) {
fatal("smram_add(): NULL base SMRAM with non-NULL last SMRAM\n");
return NULL;
} else if ((base_smram != NULL) && (last_smram == NULL)) {
fatal("smram_add(): Non-NULL base SMRAM with NULL last SMRAM\n");
return NULL;
} else if ((base_smram != NULL) && (base_smram->prev != NULL)) {
fatal("smram_add(): Base SMRAM with a preceding SMRAM\n");
return NULL;
} else if ((last_smram != NULL) && (last_smram->next != NULL)) {
fatal("smram_add(): Last SMRAM with a following SMRAM\n");
return NULL;
}
temp_smram = (smram_t *) malloc(sizeof(smram_t));
if (temp_smram == NULL) {
fatal("smram_add(): temp_smram malloc failed\n");
return NULL;
}
memset(temp_smram, 0x00, sizeof(smram_t));
memset(&(temp_smram->mapping), 0x00, sizeof(mem_mapping_t));
/* Add struct to the beginning of the list if necessary.*/
if (base_smram == NULL)
base_smram = temp_smram;
/* Add struct to the end of the list.*/
if (last_smram == NULL)
temp_smram->prev = NULL;
else {
temp_smram->prev = last_smram;
last_smram->next = temp_smram;
}
last_smram = temp_smram;
mem_mapping_add(&(temp_smram->mapping), 0x00000000, 0x00000000,
smram_read,smram_readw,smram_readl,
smram_write,smram_writew,smram_writel,
ram, MEM_MAPPING_SMRAM, temp_smram);
return temp_smram;
}
/* Set memory state in the specified model (normal or SMM) according to the specified flags. */
void
smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
}
/* Disable a specific SMRAM mapping. */
void
smram_disable(smram_t *smr)
{
if (smr == NULL) {
fatal("smram_disable(): Invalid SMRAM mapping\n");
return;
}
if (smr->size != 0x00000000) {
smram_map(0, smr->host_base, smr->size, 0);
smram_map(1, smr->host_base, smr->size, 0);
smr->host_base = smr->ram_base = 0x00000000;
smr->size = 0x00000000;
mem_mapping_disable(&(smr->mapping));
}
}
/* Disable all SMRAM mappings. */
void
smram_disable_all(void)
{
smram_t *temp_smram = base_smram, *next;
while (temp_smram != NULL) {
smram_disable(temp_smram);
next = temp_smram->next;
temp_smram = next;
}
}
/* Enable SMRAM mappings according to flags for both normal and SMM modes. */
void
smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size, int flags_normal, int flags_smm)
{
if (smr == NULL) {
fatal("smram_add(): Invalid SMRAM mapping\n");
return;
}
if ((size != 0x00000000) && (flags_normal || flags_smm)) {
smr->host_base = host_base;
smr->ram_base = ram_base,
smr->size = size;
mem_mapping_set_addr(&(smr->mapping), smr->host_base, smr->size);
if (smr->ram_base < (1 << 30))
mem_mapping_set_exec(&(smr->mapping), ram + smr->ram_base);
else
mem_mapping_set_exec(&(smr->mapping), ram2 + smr->ram_base - (1 << 30));
smram_map(0, host_base, size, flags_normal);
smram_map(1, host_base, size, flags_smm);
} else
smram_disable(smr);
}
/* Checks if a SMRAM mapping is enabled or not. */
int
smram_enabled(smram_t *smr)
{
int ret = 0;
if (smr == NULL)
ret = 0;
else
ret = (smr->size != 0x00000000);
return ret;
}
/* Changes the SMRAM state. */
void
smram_state_change(smram_t *smr, int smm, int flags)
{
if (smr == NULL) {
fatal("smram_tate_change(): Invalid SMRAM mapping\n");
return;
}
smram_map(smm, smr->host_base, smr->size, flags);
}

2
src/mem/sst_flash.c
View File

@@ -323,7 +323,7 @@ sst_add_mappings(sst_t *dev)
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
}
mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000), 0x10000,
mem_mapping_add(&(dev->mapping_h[i]), (base | (cpu_16bitbus ? 0xf00000 : 0xfff00000)), 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);

4
src/nvr.c
View File

@@ -143,10 +143,12 @@ static void
onesec_timer(void *priv)
{
nvr_t *nvr = (nvr_t *)priv;
int is_at;
if (++nvr->onesec_cnt >= 100) {
/* Update the internal clock. */
if (!(machines[machine].flags & MACHINE_AT))
is_at = IS_ARCH(machine, (MACHINE_BUS_ISA16 | MACHINE_BUS_MCA | MACHINE_BUS_PCMCIA));
if (!is_at)
rtc_tick();
/* Update the RTC device if needed. */

2
src/nvr_at.c
View File

@@ -1015,7 +1015,7 @@ const device_t ps_nvr_device = {
const device_t amstrad_nvr_device = {
"Amstrad NVRAM",
MACHINE_ISA | MACHINE_AT,
DEVICE_ISA | DEVICE_AT,
3,
nvr_at_init, nvr_at_close, NULL,
NULL, nvr_at_speed_changed,

18
src/pc.c
View File

@@ -197,6 +197,9 @@ pclog_ex(const char *fmt, va_list ap)
#ifndef RELEASE_BUILD
char temp[1024];
if (strcmp(fmt, "") == 0)
return;
if (stdlog == NULL) {
if (log_path[0] != L'\0') {
stdlog = plat_fopen(log_path, L"w");
@@ -276,7 +279,6 @@ fatal(const char *fmt, ...)
config_save();
dumppic();
#ifdef ENABLE_808X_LOG
dumpregs(1);
#endif
@@ -686,6 +688,9 @@ pc_reset_hard_close(void)
{
ui_sb_set_ready(0);
/* Close all the memory mappings. */
mem_close();
network_timer_stop();
/* Turn off timer processing to avoid potential segmentation faults. */
@@ -868,6 +873,12 @@ pc_close(thread_t *ptr)
plat_mouse_capture(0);
/* Close all the memory mappings. */
mem_close();
network_timer_stop();
/* Turn off timer processing to avoid potential segmentation faults. */
timer_close();
lpt_devices_close();
@@ -875,10 +886,9 @@ pc_close(thread_t *ptr)
for (i=0; i<FDD_NUM; i++)
fdd_close(i);
if (dump_on_exit)
dumppic();
#ifdef ENABLE_808X_LOG
dumpregs(0);
if (dump_on_exit)
dumpregs(0);
#endif
video_close();

115
src/pci.c
View File

@@ -57,8 +57,7 @@ int pci_burst_time,
static pci_card_t pci_cards[32];
static uint8_t pci_pmc = 0, last_pci_card = 0, last_normal_pci_card = 0, last_pci_bus = 1;
static uint8_t pci_card_to_slot_mapping[256][32], pci_bus_number_to_index_mapping[256];
static uint8_t elcr[2] = { 0, 0 };
static uint8_t pci_irqs[4], pci_irq_level[4];
static uint8_t pci_irqs[16], pci_irq_level[16];
static uint64_t pci_irq_hold[16];
static pci_mirq_t pci_mirqs[3];
static int pci_type,
@@ -69,7 +68,7 @@ static int pci_type,
pci_bus,
pci_enable,
pci_key;
static int trc_reg = 0, elcr_enabled = 1;
static int trc_reg = 0;
static void pci_reset_regs(void);
@@ -128,21 +127,21 @@ pci_write(uint16_t port, uint8_t val, void *priv)
if (! pci_enable)
return;
pci_log("Writing %02X to PCI card on bus %i, slot %02X (pci_cards[%i]) (%02X:%02X)...\n", val, pci_bus, pci_card, slot, pci_func, pci_index);
pci_log("Writing %02X to PCI card on bus %i, slot %02X (pci_cards[%i]) (%02X:%02X)...\n", val, pci_bus, pci_card, slot, pci_func, pci_index | (port & 3));
slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card];
if (slot != 0xff) {
if (pci_cards[slot].write) {
pci_log("Writing to PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Writing to PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index | (port & 3));
pci_cards[slot].write(pci_func, pci_index | (port & 3), val, pci_cards[slot].priv);
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index | (port & 3));
#endif
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index | (port & 3));
#endif
break;
@@ -170,65 +169,21 @@ pci_read(uint16_t port, void *priv)
ret = pci_cards[slot].read(pci_func, pci_index | (port & 3), pci_cards[slot].priv);
#ifdef ENABLE_PCI_LOG
else
pci_log("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index | (port & 3));
#endif
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index | (port & 3));
#endif
}
pci_log("Reading %02X, from PCI card on bus %i, slot %02X (pci_cards[%i]) (%02X:%02X)...\n", ret, pci_bus, pci_card, slot, pci_func, pci_index);
pci_log("Reading %02X, from PCI card on bus %i, slot %02X (pci_cards[%i]) (%02X:%02X)...\n", ret, pci_bus, pci_card, slot, pci_func, pci_index | (port & 3));
return ret;
}
void
elcr_write(uint16_t port, uint8_t val, void *priv)
{
pci_log("ELCR%i: WRITE %02X\n", port & 1, val);
if (port & 1)
val &= 0xde;
else
val &= 0xf8;
elcr[port & 1] = val;
pci_log("ELCR %i: %c %c %c %c %c %c %c %c\n",
port & 1,
(val & 1) ? 'L' : 'E',
(val & 2) ? 'L' : 'E',
(val & 4) ? 'L' : 'E',
(val & 8) ? 'L' : 'E',
(val & 0x10) ? 'L' : 'E',
(val & 0x20) ? 'L' : 'E',
(val & 0x40) ? 'L' : 'E',
(val & 0x80) ? 'L' : 'E');
}
uint8_t
elcr_read(uint16_t port, void *priv)
{
pci_log("ELCR%i: READ %02X\n", port & 1, elcr[port & 1]);
return elcr[port & 1];
}
static void
elcr_reset(void)
{
pic_reset();
elcr[0] = 0x00;
elcr[1] = 0x00;
}
static void pci_type2_write(uint16_t port, uint8_t val, void *priv);
static uint8_t pci_type2_read(uint16_t port, void *priv);
@@ -359,28 +314,6 @@ pci_set_mirq_routing(int mirq, int irq)
}
int
pci_irq_is_level(int irq)
{
int real_irq = irq & 7;
if (elcr_enabled) {
if ((irq <= 2) || (irq == 8) || (irq == 13))
return 0;
if (irq > 7)
return !!(elcr[1] & (1 << real_irq));
return !!(elcr[0] & (1 << real_irq));
} else {
if (irq < 8)
return (pic.icw1 & 8) ? 1 : 0;
else
return (pic2.icw1 & 8) ? 1 : 0;
}
}
uint8_t
pci_use_mirq(uint8_t mirq)
{
@@ -484,7 +417,7 @@ pci_set_irq(uint8_t card, uint8_t pci_int)
} else
pci_log("pci_set_irq(%02X, %02X): Using IRQ %i\n", card, pci_int, irq_line);
if (pci_irq_is_level(irq_line) && (pci_irq_hold[irq_line] & (1ULL << slot))) {
if (picint_is_level(irq_line) && (pci_irq_hold[irq_line] & (1ULL << slot))) {
/* IRQ already held, do nothing. */
pci_log("pci_set_irq(%02X, %02X): Card is already holding the IRQ\n", card, pci_int);
return;
@@ -633,21 +566,6 @@ pci_get_int(uint8_t slot, uint8_t pci_int)
}
void
pci_elcr_set_enabled(int enabled)
{
elcr_enabled = enabled;
}
void
pci_elcr_io_disable(void)
{
io_removehandler(0x04d0, 0x0002,
elcr_read,NULL,NULL, elcr_write,NULL,NULL, NULL);
}
static void
pci_reset_regs(void)
{
@@ -674,7 +592,7 @@ pci_reset_hard(void)
}
}
elcr_reset();
pic_reset();
}
@@ -832,9 +750,12 @@ pci_init(int type)
pci_type2_read,NULL,NULL, pci_type2_write,NULL,NULL, NULL);
}
if (!(type & PCI_NO_IRQ_STEERING)) {
io_sethandler(0x04d0, 0x0002,
elcr_read,NULL,NULL, elcr_write,NULL,NULL, NULL);
if (type & PCI_NO_IRQ_STEERING) {
pic_elcr_io_handler(0);
pic_elcr_set_enabled(0);
} else {
pic_elcr_io_handler(1);
pic_elcr_set_enabled(1);
}
if ((type & PCI_CONFIG_TYPE_MASK) == PCI_CONFIG_TYPE_1) {
@@ -858,8 +779,6 @@ pci_init(int type)
pci_mirqs[c].enabled = 0;
pci_mirqs[c].irq_line = PCI_IRQ_DISABLED;
}
elcr_enabled = 1;
}

928
src/pic.c
View File

File diff suppressed because it is too large Load Diff

12
src/scsi/scsi_cdrom.c
View File

@@ -1431,9 +1431,9 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
device_identify[7] = dev->id + 0x30;
device_identify_ex[7] = dev->id + 0x30;
device_identify_ex[10] = EMU_VERSION[0];
device_identify_ex[12] = EMU_VERSION[2];
device_identify_ex[13] = EMU_VERSION[3];
device_identify_ex[10] = EMU_VERSION_EX[0];
device_identify_ex[12] = EMU_VERSION_EX[2];
device_identify_ex[13] = EMU_VERSION_EX[3];
memcpy(dev->current_cdb, cdb, 12);
@@ -2373,7 +2373,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
} else {
ide_padstr8(dev->buffer + 8, 8, EMU_NAME); /* Vendor */
ide_padstr8(dev->buffer + 16, 16, device_identify); /* Product */
ide_padstr8(dev->buffer + 32, 4, EMU_VERSION); /* Revision */
ide_padstr8(dev->buffer + 32, 4, EMU_VERSION_EX); /* Revision */
}
idx = 36;
@@ -2655,7 +2655,7 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma)
ide->buffer[0] = 0x8000 | (5<<8) | 0x80 | (2<<5); /* ATAPI device, CD-ROM drive, removable media, accelerated DRQ */
ide_padstr((char *) (ide->buffer + 10), "", 20); /* Serial Number */
#if 0
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION_EX, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), device_identify, 40); /* Model */
#else
ide_padstr((char *) (ide->buffer + 23), "4.20 ", 8); /* Firmware */
@@ -2667,6 +2667,8 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma)
if (ide_has_dma) {
ide->buffer[71] = 30;
ide->buffer[72] = 30;
ide->buffer[80] = 0x7e; /*ATA-1 to ATA-6 supported*/
ide->buffer[81] = 0x19; /*ATA-6 revision 3a supported*/
}
}

8
src/scsi/scsi_disk.c
View File

@@ -584,9 +584,9 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
device_identify_ex[6] = (dev->id / 10) + 0x30;
device_identify_ex[7] = (dev->id % 10) + 0x30;
device_identify_ex[10] = EMU_VERSION[0];
device_identify_ex[12] = EMU_VERSION[2];
device_identify_ex[13] = EMU_VERSION[3];
device_identify_ex[10] = EMU_VERSION_EX[0];
device_identify_ex[12] = EMU_VERSION_EX[2];
device_identify_ex[13] = EMU_VERSION_EX[3];
memcpy(dev->current_cdb, cdb, 12);
@@ -985,7 +985,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
ide_padstr8(dev->temp_buffer + 8, 8, EMU_NAME); /* Vendor */
ide_padstr8(dev->temp_buffer + 16, 16, device_identify); /* Product */
ide_padstr8(dev->temp_buffer + 32, 4, EMU_VERSION); /* Revision */
ide_padstr8(dev->temp_buffer + 32, 4, EMU_VERSION_EX); /* Revision */
idx = 36;
if (max_len == 96) {

7
src/scsi/scsi_ncr53c8xx.c
View File

@@ -52,9 +52,16 @@
#define HA_ID 7
#define CHIP_810 0x01
#define CHIP_820 0x02
#define CHIP_825 0x03
#define CHIP_815 0x04
#define CHIP_810AP 0x05
#define CHIP_860 0x06
#define CHIP_895 0x0c
#define CHIP_875 0x0f
#define CHIP_895A 0x12
#define CHIP_875A 0x13
#define CHIP_875J 0x8f
#define NCR_SCNTL0_TRG 0x01
#define NCR_SCNTL0_AAP 0x02

12
src/timer.c
View File

@@ -37,11 +37,7 @@ timer_enable(pc_timer_t *timer)
if (!timer_head) {
timer_head = timer;
timer->next = timer->prev = NULL;
#if 0
timer_target = timer_head->ts_integer;
#else
timer_target = timer_head->ts.ts32.integer;
#endif
return;
}
@@ -57,11 +53,7 @@ timer_enable(pc_timer_t *timer)
timer->prev->next = timer;
else {
timer_head = timer;
#if 0
timer_target = timer_head->ts_integer;
#else
timer_target = timer_head->ts.ts32.integer;
#endif
}
return;
}
@@ -142,11 +134,7 @@ timer_process(void)
timer->callback(timer->p);
}
#if 0
timer_target = timer_head->ts_integer;
#else
timer_target = timer_head->ts.ts32.integer;
#endif
}

2
src/video/vid_table.c
View File

@@ -232,7 +232,7 @@ video_reset(int card)
/* Do not initialize internal cards here. */
if (!(card == VID_NONE) && \
!(card == VID_INTERNAL) && !(machines[machine].flags & MACHINE_VIDEO_FIXED)) {
!(card == VID_INTERNAL) && !(machines[machine].flags & MACHINE_VIDEO_ONLY)) {
vid_table_log("VIDEO: initializing '%s'\n", video_cards[card].name);
/* Do an inform on the default values, so that that there's some sane values initialized

8
src/video/vid_voodoo.c
View File

@@ -7731,12 +7731,12 @@ void *voodoo_init()
void voodoo_card_close(voodoo_t *voodoo)
{
#ifndef RELEASE_BUILD
/* #ifndef RELEASE_BUILD
FILE *f;
#endif
#endif */
int c;
#ifndef RELEASE_BUILD
/* #ifndef RELEASE_BUILD
f = rom_fopen(L"texram.dmp", L"wb");
fwrite(voodoo->tex_mem[0], voodoo->texture_size*1024*1024, 1, f);
fclose(f);
@@ -7746,7 +7746,7 @@ void voodoo_card_close(voodoo_t *voodoo)
fwrite(voodoo->tex_mem[1], voodoo->texture_size*1024*1024, 1, f);
fclose(f);
}
#endif
#endif */
thread_kill(voodoo->fifo_thread);
thread_kill(voodoo->render_thread[0]);

2
src/win/86Box.manifest
View File

@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<assembly xmlns="urn:schemas-microsoft-com:asm.v1" manifestVersion="1.0">
<assemblyIdentity
version="1.20.0.0"
version="3.0.0.0"
processorArchitecture="*"
name="86Box.exe"
type="win32"

14
src/win/86Box.rc
View File

@@ -1060,24 +1060,24 @@ BEGIN
IDS_4353 "XTA"
IDS_4354 "ESDI"
IDS_4355 "IDE"
IDS_4356 "SCSI"
IDS_4356 "ATAPI"
IDS_4357 "SCSI"
IDS_4608 "MFM/RLL (%01i:%01i)"
IDS_4609 "XTA (%01i:%01i)"
IDS_4610 "ESDI (%01i:%01i)"
IDS_4611 "IDE (%01i:%01i)"
IDS_4612 "SCSI (ID %02i)"
IDS_4612 "ATAPI (%01i:%01i)"
IDS_4613 "SCSI (ID %02i)"
IDS_5120 "CD-ROM %i (%s): %s"
IDS_5376 "Disabled"
IDS_5380 "ATAPI"
IDS_5381 "SCSI"
IDS_5382 "SCSI (Chinon)"
IDS_5381 "ATAPI"
IDS_5382 "SCSI"
IDS_5632 "Disabled"
IDS_5636 "ATAPI (%01i:%01i)"
IDS_5637 "SCSI (ID %02i)"
IDS_5637 "ATAPI (%01i:%01i)"
IDS_5638 "SCSI (ID %02i)"
IDS_5888 "160 kB"

27
src/win/Makefile.mingw
View File

@@ -75,6 +75,9 @@ ifeq ($(DEV_BUILD), y)
ifndef S3TRIO3D2X
S3TRIO3D2X := y
endif
ifndef SEP
SEP := n
endif
ifndef SIEMENS
SIEMENS := y
endif
@@ -93,9 +96,6 @@ ifeq ($(DEV_BUILD), y)
ifndef VNC
VNC := y
endif
ifndef WIN471
WIN471 := y
endif
ifndef XL24
XL24 := y
endif
@@ -157,6 +157,9 @@ else
ifndef S3TRIO3D2X
S3TRIO3D2X := n
endif
ifndef SEP
SEP := n
endif
ifndef SIEMENS
SIEMENS := n
endif
@@ -175,9 +178,6 @@ else
ifndef VNC
VNC := n
endif
ifndef WIN471
WIN471 := n
endif
ifndef XL24
XL24 := n
endif
@@ -560,6 +560,10 @@ ifeq ($(S3TRIO3D2X), y)
OPTS += -DUSE_S3TRIO3D2X
endif
ifeq ($(SEP), y)
OPTS += -DUSE_SEP
endif
ifeq ($(SIEMENS), y)
OPTS += -DUSE_SIEMENS
endif
@@ -587,10 +591,6 @@ ifeq ($(VGAWONDER), y)
OPTS += -DUSE_VGAWONDER
endif
ifeq ($(WIN471), y)
OPTS += -DUSE_WIN471
endif
ifeq ($(XL24), y)
OPTS += -DUSE_XL24
endif
@@ -629,7 +629,7 @@ MAINOBJ := pc.o config.o random.o timer.o io.o acpi.o apm.o dma.o ddma.o \
usb.o device.o nvr.o nvr_at.o nvr_ps2.o \
$(VNCOBJ)
MEMOBJ := catalyst_flash.o intel_flash.o mem.o rom.o spd.o sst_flash.o
MEMOBJ := catalyst_flash.o intel_flash.o mem.o rom.o smram.o spd.o sst_flash.o
CPUOBJ := cpu.o cpu_table.o \
808x.o 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o $(CGTOBJ) \
@@ -639,7 +639,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o intel_82335.o cs4031.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
sis_85c310.o sis_85c471.o sis_85c496.o opti283.o opti291.o umc491.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o opti283.o opti291.o umc491.o \
via_apollo.o via_vpx.o via_pipc.o wd76c10.o vl82c480.o \
amd640.o
@@ -660,7 +660,8 @@ MCHOBJ := machine.o machine_table.o \
m_at_socket8.o m_at_slot1.o m_at_slot2.o m_at_socket370.o \
m_at_misc.o
DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm_5161.o isamem.o isartc.o lpt.o pci_bridge.o postcard.o serial.o vpc2007.o \
DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm_5161.o isamem.o isartc.o \
lpt.o pci_bridge.o postcard.o serial.o vpc2007.o \
smbus.o smbus_piix4.o \
keyboard.o \
keyboard_xt.o keyboard_at.o \

2
src/win/win_media_menu.c
View File

@@ -22,7 +22,7 @@
#include <86box/zip.h>
#include <86box/win.h>
#define MACHINE_HAS_IDE ((machines[machine].flags & MACHINE_HDC) || !memcmp(hdc_get_internal_name(hdc_current), "ide", 3))
#define MACHINE_HAS_IDE (machines[machine].flags & MACHINE_IDE_QUAD)
#define FDD_FIRST 0
#define CDROM_FIRST FDD_FIRST + FDD_NUM

2
src/win/win_sdl.c
View File

@@ -423,7 +423,7 @@ sdl_init_common(int flags)
*/
if (flags & RENDERER_HARDWARE) {
sdl_render = SDL_CreateRenderer(sdl_win, -1, SDL_RENDERER_ACCELERATED);
SDL_SetHint(SDL_HINT_RENDER_SCALE_QUALITY, "1");
SDL_SetHint(SDL_HINT_RENDER_SCALE_QUALITY, "2");
} else
sdl_render = SDL_CreateRenderer(sdl_win, -1, SDL_RENDERER_SOFTWARE);

29
src/win/win_settings.c
View File

@@ -663,7 +663,7 @@ static void
win_settings_machine_recalc_machine(HWND hdlg)
{
HWND h;
int c;
int c, is_at;
LPTSTR lptsTemp;
const char *stransi;
UDACCEL accel;
@@ -700,7 +700,8 @@ win_settings_machine_recalc_machine(HWND hdlg)
accel.nSec = 0;
accel.nInc = machines[temp_machine].ram_granularity;
SendMessage(h, UDM_SETACCEL, 1, (LPARAM)&accel);
if (!(machines[temp_machine].flags & MACHINE_AT) || (machines[temp_machine].ram_granularity >= 128)) {
is_at = IS_ARCH(temp_machine, (MACHINE_BUS_ISA16 | MACHINE_BUS_MCA | MACHINE_BUS_PCMCIA));
if (!is_at || (machines[temp_machine].ram_granularity >= 128)) {
SendMessage(h, UDM_SETPOS, 0, temp_mem_size);
h = GetDlgItem(hdlg, IDC_TEXT_MB);
SendMessage(h, WM_SETTEXT, 0, win_get_string(IDS_2088));
@@ -723,7 +724,7 @@ win_settings_machine_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
{
HWND h, h2;
int c, d, e, f;
int old_machine_type;
int old_machine_type, is_at;
LPTSTR lptsTemp;
char *stransi;
@@ -925,7 +926,8 @@ win_settings_machine_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
temp_mem_size = machines[temp_machine].min_ram;
else if (temp_mem_size > machines[temp_machine].max_ram)
temp_mem_size = machines[temp_machine].max_ram;
if ((machines[temp_machine].flags & MACHINE_AT) && (machines[temp_machine].ram_granularity < 128))
is_at = IS_ARCH(temp_machine, (MACHINE_BUS_ISA16 | MACHINE_BUS_MCA | MACHINE_BUS_PCMCIA));
if (is_at && (machines[temp_machine].ram_granularity < 128))
temp_mem_size *= 1024;
free(stransi);
free(lptsTemp);
@@ -977,7 +979,7 @@ recalc_vid_list(HWND hdlg)
}
if (!found_card)
SendMessage(h, CB_SETCURSEL, 0, 0);
EnableWindow(h, (machines[temp_machine].flags & MACHINE_VIDEO_FIXED) ? FALSE : TRUE);
EnableWindow(h, (machines[temp_machine].flags & MACHINE_VIDEO_ONLY) ? FALSE : TRUE);
h = GetDlgItem(hdlg, IDC_CHECK_VOODOO);
EnableWindow(h, (machines[temp_machine].flags & MACHINE_PCI) ? TRUE : FALSE);
@@ -1691,7 +1693,7 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
{
HWND h;
int c, d;
int e;
int e, is_at;
LPTSTR lptsTemp;
char *stransi;
const device_t *scsi_dev;
@@ -1786,16 +1788,17 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
EnableWindow(h, scsi_card_has_config(temp_scsi_card) ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_CHECK_IDE_TER);
EnableWindow(h, (machines[temp_machine].flags & MACHINE_AT) ? TRUE : FALSE);
is_at = IS_ARCH(temp_machine, (MACHINE_BUS_ISA16 | MACHINE_BUS_MCA | MACHINE_BUS_PCMCIA));
EnableWindow(h, is_at ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_BUTTON_IDE_TER);
EnableWindow(h, ((machines[temp_machine].flags & MACHINE_AT) && temp_ide_ter) ? TRUE : FALSE);
EnableWindow(h, (is_at && temp_ide_ter) ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_CHECK_IDE_QUA);
EnableWindow(h, (machines[temp_machine].flags & MACHINE_AT) ? TRUE : FALSE);
EnableWindow(h, is_at ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_BUTTON_IDE_QUA);
EnableWindow(h, ((machines[temp_machine].flags & MACHINE_AT) && temp_ide_qua) ? TRUE : FALSE);
EnableWindow(h, (is_at && temp_ide_qua) ? TRUE : FALSE);
h=GetDlgItem(hdlg, IDC_CHECK_IDE_TER);
SendMessage(h, BM_SETCHECK, temp_ide_ter, 0);
@@ -2260,7 +2263,7 @@ add_locations(HWND hdlg)
lptsTemp = (LPTSTR) malloc(512 * sizeof(WCHAR));
h = GetDlgItem(hdlg, IDC_COMBO_HD_BUS);
for (i = 0; i < 5; i++)
for (i = 0; i < 6; i++)
SendMessage(h, CB_ADDSTRING, 0, win_get_string(IDS_4352 + i));
h = GetDlgItem(hdlg, IDC_COMBO_HD_CHANNEL);
@@ -2550,7 +2553,7 @@ win_settings_hard_disks_update_item(HWND hwndList, int i, int column)
wsprintf(szText, plat_get_string(IDS_4611), temp_hdd[i].ide_channel >> 1, temp_hdd[i].ide_channel & 1);
break;
case HDD_BUS_SCSI:
wsprintf(szText, plat_get_string(IDS_4612), temp_hdd[i].scsi_id);
wsprintf(szText, plat_get_string(IDS_4613), temp_hdd[i].scsi_id);
break;
}
lvI.pszText = szText;
@@ -2617,7 +2620,7 @@ win_settings_hard_disks_recalc_list(HWND hwndList)
wsprintf(szText, plat_get_string(IDS_4611), temp_hdd[i].ide_channel >> 1, temp_hdd[i].ide_channel & 1);
break;
case HDD_BUS_SCSI:
wsprintf(szText, plat_get_string(IDS_4612), temp_hdd[i].scsi_id);
wsprintf(szText, plat_get_string(IDS_4613), temp_hdd[i].scsi_id);
break;
}
lvI.pszText = szText;