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synced 2026-02-23 18:08:20 -07:00
get rid of stupid bad code that had no understanding of dma
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@@ -687,45 +687,6 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name)
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nv3->pfifo.cache1_entries[current_put_address].method = method_offset;
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nv3->pfifo.cache1_entries[current_put_address].data = object_name;
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/*
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// I think we have to do this on PIO submission. Maybe not?
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uint32_t hash = nv3_ramht_hash(object_name, channel);
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uint32_t bucket_entries = 2;
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uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS;
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uint8_t ramht_size = (nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03;
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switch (ramht_size)
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{
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case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K:
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// stays as is
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break;
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case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K:
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bucket_entries = 4;
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break;
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case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K:
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bucket_entries = 8;
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break;
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case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K:
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bucket_entries = 16;
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break;
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}
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uint32_t ramin_address = ramht_base + hash * bucket_entries * 8;
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if (method_offset == 0)
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{
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nv3_ramin_write32(ramin_address, object_name, nv3);
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nv3_ramin_write32(ramin_address + 0x04, nv3->pfifo.cache1_settings.context[subchannel], nv3);
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}
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else
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{
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// MAYBE
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nv3_ramin_write32(ramin_address + method_offset, object_name, nv3);
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}
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*/
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// now we have to recalculate the cache1 put address
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uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1;
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